1 /**
2 ******************************************************************************
3 * @file stm32f0xx_ll_dac.h
4 * @author MCD Application Team
5 * @brief Header file of DAC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32F0xx_LL_DAC_H
21 #define __STM32F0xx_LL_DAC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f0xx.h"
29
30 /** @addtogroup STM32F0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (DAC1)
35
36 /** @defgroup DAC_LL DAC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
45 * @{
46 */
47
48 /* Internal masks for DAC channels definition */
49 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
50 /* - channel bits position into register CR */
51 /* - channel bits position into register SWTRIG */
52 /* - channel register offset of data holding register DHRx */
53 /* - channel register offset of data output register DORx */
54 #define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
55 #define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
56 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
57
58 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
59 #if defined(DAC_CHANNEL2_SUPPORT)
60 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
61 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
62 #else
63 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1)
64 #endif /* DAC_CHANNEL2_SUPPORT */
65
66 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
67 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
68 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
69 #if defined(DAC_CHANNEL2_SUPPORT)
70 #define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
71 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
72 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
73 #endif /* DAC_CHANNEL2_SUPPORT */
74 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
75 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
76 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
77 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
78
79 #define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
80 #if defined(DAC_CHANNEL2_SUPPORT)
81 #define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
82 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
83 #else
84 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET)
85 #endif /* DAC_CHANNEL2_SUPPORT */
86
87 #define DAC_REG_REGOFFSET_MASK_POSBIT0 0x0000000FU /* Mask of registers offset (DHR12Rx, DHR12Lx, DHR8Rx, DORx, ...) when shifted to position 0 */
88
89 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16U /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
90 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20U /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
91 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24U /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
92 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28U /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 28 bits) */
93
94 /* DAC registers bits positions */
95 #if defined(DAC_CHANNEL2_SUPPORT)
96 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
97 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
98 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
99 #endif /* DAC_CHANNEL2_SUPPORT */
100
101 /* Miscellaneous data */
102 #define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
103
104 /**
105 * @}
106 */
107
108
109 /* Private macros ------------------------------------------------------------*/
110 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
111 * @{
112 */
113
114 /**
115 * @brief Driver macro reserved for internal use: set a pointer to
116 * a register from a register basis from which an offset
117 * is applied.
118 * @param __REG__ Register basis from which the offset is applied.
119 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
120 * @retval Pointer to register address
121 */
122 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
123 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
124
125 /**
126 * @}
127 */
128
129
130 /* Exported types ------------------------------------------------------------*/
131 #if defined(USE_FULL_LL_DRIVER)
132 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
133 * @{
134 */
135
136 /**
137 * @brief Structure definition of some features of DAC instance.
138 */
139 typedef struct
140 {
141 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
142 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
143
144 This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
145
146 #if defined(DAC_CR_WAVE1)
147 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
148 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
149
150 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
151
152 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
153 If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
154 If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
155 @note If waveform automatic generation mode is disabled, this parameter is discarded.
156
157 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
158 #endif
159
160 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
161 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
162
163 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
164
165 } LL_DAC_InitTypeDef;
166
167 /**
168 * @}
169 */
170 #endif /* USE_FULL_LL_DRIVER */
171
172 /* Exported constants --------------------------------------------------------*/
173 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
174 * @{
175 */
176
177 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
178 * @brief Flags defines which can be used with LL_DAC_ReadReg function
179 * @{
180 */
181 /* DAC channel 1 flags */
182 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
183
184 #if defined(DAC_CHANNEL2_SUPPORT)
185 /* DAC channel 2 flags */
186 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
187 #endif /* DAC_CHANNEL2_SUPPORT */
188 /**
189 * @}
190 */
191
192 /** @defgroup DAC_LL_EC_IT DAC interruptions
193 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
194 * @{
195 */
196 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
197 #if defined(DAC_CHANNEL2_SUPPORT)
198 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
199 #endif /* DAC_CHANNEL2_SUPPORT */
200 /**
201 * @}
202 */
203
204 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
205 * @{
206 */
207 #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
208 #if defined(DAC_CHANNEL2_SUPPORT)
209 #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
210 #endif /* DAC_CHANNEL2_SUPPORT */
211 /**
212 * @}
213 */
214
215 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
216 * @{
217 */
218 #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
219 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
220 #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
221 #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
222 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
223 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
224 #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. */
225 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
226 /**
227 * @}
228 */
229
230 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
231 * @{
232 */
233 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */
234 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
235 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
236 /**
237 * @}
238 */
239
240 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
241 * @{
242 */
243 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
244 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
245 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
246 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
247 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
248 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
249 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
250 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
251 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
252 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
253 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
254 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
255 /**
256 * @}
257 */
258
259 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
260 * @{
261 */
262 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
263 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
264 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
265 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
266 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
267 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
268 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
269 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
270 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
271 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
272 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
273 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
274 /**
275 * @}
276 */
277
278 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
279 * @{
280 */
281 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
282 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
283 /**
284 * @}
285 */
286
287
288 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
289 * @{
290 */
291 #define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */
292 #define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */
293 /**
294 * @}
295 */
296
297 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
298 * @{
299 */
300 /* List of DAC registers intended to be used (most commonly) with */
301 /* DMA transfer. */
302 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
303 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
304 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
305 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
306 /**
307 * @}
308 */
309
310 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
311 * @note Only DAC IP HW delays are defined in DAC LL driver driver,
312 * not timeout values.
313 * For details on delays values, refer to descriptions in source code
314 * above each literal definition.
315 * @{
316 */
317
318 /* Delay for DAC channel voltage settling time from DAC channel startup */
319 /* (transition from disable to enable). */
320 /* Note: DAC channel startup time depends on board application environment: */
321 /* impedance connected to DAC channel output. */
322 /* The delay below is specified under conditions: */
323 /* - voltage maximum transition (lowest to highest value) */
324 /* - until voltage reaches final value +-1LSB */
325 /* - DAC channel output buffer enabled */
326 /* - load impedance of 5kOhm (min), 50pF (max) */
327 /* Literal set to maximum value (refer to device datasheet, */
328 /* parameter "tWAKEUP"). */
329 /* Unit: us */
330 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
331
332 /* Delay for DAC channel voltage settling time. */
333 /* Note: DAC channel startup time depends on board application environment: */
334 /* impedance connected to DAC channel output. */
335 /* The delay below is specified under conditions: */
336 /* - voltage maximum transition (lowest to highest value) */
337 /* - until voltage reaches final value +-1LSB */
338 /* - DAC channel output buffer enabled */
339 /* - load impedance of 5kOhm min, 50pF max */
340 /* Literal set to maximum value (refer to device datasheet, */
341 /* parameter "tSETTLING"). */
342 /* Unit: us */
343 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */
344 /**
345 * @}
346 */
347
348 /**
349 * @}
350 */
351
352 /* Exported macro ------------------------------------------------------------*/
353 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
354 * @{
355 */
356
357 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
358 * @{
359 */
360
361 /**
362 * @brief Write a value in DAC register
363 * @param __INSTANCE__ DAC Instance
364 * @param __REG__ Register to be written
365 * @param __VALUE__ Value to be written in the register
366 * @retval None
367 */
368 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
369
370 /**
371 * @brief Read a value in DAC register
372 * @param __INSTANCE__ DAC Instance
373 * @param __REG__ Register to be read
374 * @retval Register value
375 */
376 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
377
378 /**
379 * @}
380 */
381
382 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
383 * @{
384 */
385
386 /**
387 * @brief Helper macro to get DAC channel number in decimal format
388 * from literals LL_DAC_CHANNEL_x.
389 * Example:
390 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
391 * will return decimal number "1".
392 * @note The input can be a value from functions where a channel
393 * number is returned.
394 * @param __CHANNEL__ This parameter can be one of the following values:
395 * @arg @ref LL_DAC_CHANNEL_1
396 * @arg @ref LL_DAC_CHANNEL_2 (1)
397 *
398 * (1) On this STM32 series, parameter not available on all devices.
399 * Refer to device datasheet for channels availability.
400 * @retval 1...2 (value "2" depending on DAC channel 2 availability)
401 */
402 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
403 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
404
405 /**
406 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
407 * from number in decimal format.
408 * Example:
409 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
410 * will return a data equivalent to "LL_DAC_CHANNEL_1".
411 * @note If the input parameter does not correspond to a DAC channel,
412 * this macro returns value '0'.
413 * @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability)
414 * @retval Returned value can be one of the following values:
415 * @arg @ref LL_DAC_CHANNEL_1
416 * @arg @ref LL_DAC_CHANNEL_2 (1)
417 *
418 * (1) On this STM32 series, parameter not available on all devices.
419 * Refer to device datasheet for channels availability.
420 */
421 #if defined(DAC_CHANNEL2_SUPPORT)
422 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
423 (((__DECIMAL_NB__) == 1U) \
424 ? ( \
425 LL_DAC_CHANNEL_1 \
426 ) \
427 : \
428 (((__DECIMAL_NB__) == 2U) \
429 ? ( \
430 LL_DAC_CHANNEL_2 \
431 ) \
432 : \
433 ( \
434 0 \
435 ) \
436 ) \
437 )
438 #else
439 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
440 (((__DECIMAL_NB__) == 1U) \
441 ? ( \
442 LL_DAC_CHANNEL_1 \
443 ) \
444 : \
445 ( \
446 0 \
447 ) \
448 )
449 #endif /* DAC_CHANNEL2_SUPPORT */
450
451 /**
452 * @brief Helper macro to define the DAC conversion data full-scale digital
453 * value corresponding to the selected DAC resolution.
454 * @note DAC conversion data full-scale corresponds to voltage range
455 * determined by analog voltage references Vref+ and Vref-
456 * (refer to reference manual).
457 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
458 * @arg @ref LL_DAC_RESOLUTION_12B
459 * @arg @ref LL_DAC_RESOLUTION_8B
460 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
461 */
462 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
463 ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
464
465 /**
466 * @brief Helper macro to calculate the DAC conversion data (unit: digital
467 * value) corresponding to a voltage (unit: mVolt).
468 * @note This helper macro is intended to provide input data in voltage
469 * rather than digital value,
470 * to be used with LL DAC functions such as
471 * @ref LL_DAC_ConvertData12RightAligned().
472 * @note Analog reference voltage (Vref+) must be either known from
473 * user board environment or can be calculated using ADC measurement
474 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
475 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
476 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
477 * (unit: mVolt).
478 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
479 * @arg @ref LL_DAC_RESOLUTION_12B
480 * @arg @ref LL_DAC_RESOLUTION_8B
481 * @retval DAC conversion data (unit: digital value)
482 */
483 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
484 __DAC_VOLTAGE__,\
485 __DAC_RESOLUTION__) \
486 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
487 / (__VREFANALOG_VOLTAGE__) \
488 )
489
490 /**
491 * @}
492 */
493
494 /**
495 * @}
496 */
497
498
499 /* Exported functions --------------------------------------------------------*/
500 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
501 * @{
502 */
503 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
504 * @{
505 */
506
507 /**
508 * @brief Set the conversion trigger source for the selected DAC channel.
509 * @note For conversion trigger source to be effective, DAC trigger
510 * must be enabled using function @ref LL_DAC_EnableTrigger().
511 * @note To set conversion trigger source, DAC channel must be disabled.
512 * Otherwise, the setting is discarded.
513 * @note Availability of parameters of trigger sources from timer
514 * depends on timers availability on the selected device.
515 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
516 * CR TSEL2 LL_DAC_SetTriggerSource
517 * @param DACx DAC instance
518 * @param DAC_Channel This parameter can be one of the following values:
519 * @arg @ref LL_DAC_CHANNEL_1
520 * @arg @ref LL_DAC_CHANNEL_2 (1)
521 *
522 * (1) On this STM32 series, parameter not available on all devices.
523 * Refer to device datasheet for channels availability.
524 * @param TriggerSource This parameter can be one of the following values:
525 * @arg @ref LL_DAC_TRIG_SOFTWARE
526 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
527 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
528 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
529 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
530 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
531 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
532 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
533 * @retval None
534 */
LL_DAC_SetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriggerSource)535 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
536 {
537 MODIFY_REG(DACx->CR,
538 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
539 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
540 }
541
542 /**
543 * @brief Get the conversion trigger source for the selected DAC channel.
544 * @note For conversion trigger source to be effective, DAC trigger
545 * must be enabled using function @ref LL_DAC_EnableTrigger().
546 * @note Availability of parameters of trigger sources from timer
547 * depends on timers availability on the selected device.
548 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
549 * CR TSEL2 LL_DAC_GetTriggerSource
550 * @param DACx DAC instance
551 * @param DAC_Channel This parameter can be one of the following values:
552 * @arg @ref LL_DAC_CHANNEL_1
553 * @arg @ref LL_DAC_CHANNEL_2 (1)
554 *
555 * (1) On this STM32 series, parameter not available on all devices.
556 * Refer to device datasheet for channels availability.
557 * @retval Returned value can be one of the following values:
558 * @arg @ref LL_DAC_TRIG_SOFTWARE
559 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
560 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
561 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
562 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
563 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
564 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
565 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
566 */
LL_DAC_GetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel)567 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
568 {
569 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
570 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
571 );
572 }
573
574 #if defined(DAC_CR_WAVE1)
575 /**
576 * @brief Set the waveform automatic generation mode
577 * for the selected DAC channel.
578 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
579 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
580 * @param DACx DAC instance
581 * @param DAC_Channel This parameter can be one of the following values:
582 * @arg @ref LL_DAC_CHANNEL_1
583 * @arg @ref LL_DAC_CHANNEL_2 (1)
584 *
585 * (1) On this STM32 series, parameter not available on all devices.
586 * Refer to device datasheet for channels availability.
587 * @param WaveAutoGeneration This parameter can be one of the following values:
588 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
589 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
590 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
591 * @retval None
592 */
LL_DAC_SetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t WaveAutoGeneration)593 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
594 {
595 MODIFY_REG(DACx->CR,
596 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
597 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
598 }
599
600 /**
601 * @brief Get the waveform automatic generation mode
602 * for the selected DAC channel.
603 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
604 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
605 * @param DACx DAC instance
606 * @param DAC_Channel This parameter can be one of the following values:
607 * @arg @ref LL_DAC_CHANNEL_1
608 * @arg @ref LL_DAC_CHANNEL_2 (1)
609 *
610 * (1) On this STM32 series, parameter not available on all devices.
611 * Refer to device datasheet for channels availability.
612 * @retval Returned value can be one of the following values:
613 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
614 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
615 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
616 */
LL_DAC_GetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel)617 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
618 {
619 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
620 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
621 );
622 }
623
624 /**
625 * @brief Set the noise waveform generation for the selected DAC channel:
626 * Noise mode and parameters LFSR (linear feedback shift register).
627 * @note For wave generation to be effective, DAC channel
628 * wave generation mode must be enabled using
629 * function @ref LL_DAC_SetWaveAutoGeneration().
630 * @note This setting can be set when the selected DAC channel is disabled
631 * (otherwise, the setting operation is ignored).
632 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
633 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
634 * @param DACx DAC instance
635 * @param DAC_Channel This parameter can be one of the following values:
636 * @arg @ref LL_DAC_CHANNEL_1
637 * @arg @ref LL_DAC_CHANNEL_2 (1)
638 *
639 * (1) On this STM32 series, parameter not available on all devices.
640 * Refer to device datasheet for channels availability.
641 * @param NoiseLFSRMask This parameter can be one of the following values:
642 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
643 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
644 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
645 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
646 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
647 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
648 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
649 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
650 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
651 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
652 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
653 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
654 * @retval None
655 */
LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t NoiseLFSRMask)656 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
657 {
658 MODIFY_REG(DACx->CR,
659 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
660 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
661 }
662
663 /**
664 * @brief Set the noise waveform generation for the selected DAC channel:
665 * Noise mode and parameters LFSR (linear feedback shift register).
666 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
667 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
668 * @param DACx DAC instance
669 * @param DAC_Channel This parameter can be one of the following values:
670 * @arg @ref LL_DAC_CHANNEL_1
671 * @arg @ref LL_DAC_CHANNEL_2 (1)
672 *
673 * (1) On this STM32 series, parameter not available on all devices.
674 * Refer to device datasheet for channels availability.
675 * @retval Returned value can be one of the following values:
676 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
677 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
678 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
679 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
680 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
681 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
682 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
683 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
684 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
685 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
686 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
687 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
688 */
LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel)689 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
690 {
691 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
692 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
693 );
694 }
695
696 /**
697 * @brief Set the triangle waveform generation for the selected DAC channel:
698 * triangle mode and amplitude.
699 * @note For wave generation to be effective, DAC channel
700 * wave generation mode must be enabled using
701 * function @ref LL_DAC_SetWaveAutoGeneration().
702 * @note This setting can be set when the selected DAC channel is disabled
703 * (otherwise, the setting operation is ignored).
704 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
705 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
706 * @param DACx DAC instance
707 * @param DAC_Channel This parameter can be one of the following values:
708 * @arg @ref LL_DAC_CHANNEL_1
709 * @arg @ref LL_DAC_CHANNEL_2 (1)
710 *
711 * (1) On this STM32 series, parameter not available on all devices.
712 * Refer to device datasheet for channels availability.
713 * @param TriangleAmplitude This parameter can be one of the following values:
714 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
715 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
716 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
717 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
718 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
719 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
720 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
721 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
722 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
723 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
724 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
725 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
726 * @retval None
727 */
LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriangleAmplitude)728 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
729 {
730 MODIFY_REG(DACx->CR,
731 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
732 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
733 }
734
735 /**
736 * @brief Set the triangle waveform generation for the selected DAC channel:
737 * triangle mode and amplitude.
738 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
739 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
740 * @param DACx DAC instance
741 * @param DAC_Channel This parameter can be one of the following values:
742 * @arg @ref LL_DAC_CHANNEL_1
743 * @arg @ref LL_DAC_CHANNEL_2 (1)
744 *
745 * (1) On this STM32 series, parameter not available on all devices.
746 * Refer to device datasheet for channels availability.
747 * @retval Returned value can be one of the following values:
748 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
749 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
750 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
751 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
752 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
753 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
754 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
755 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
756 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
757 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
758 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
759 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
760 */
LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel)761 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
762 {
763 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
764 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
765 );
766 }
767 #endif
768
769 /**
770 * @brief Set the output buffer for the selected DAC channel.
771 * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
772 * CR BOFF2 LL_DAC_SetOutputBuffer
773 * @param DACx DAC instance
774 * @param DAC_Channel This parameter can be one of the following values:
775 * @arg @ref LL_DAC_CHANNEL_1
776 * @arg @ref LL_DAC_CHANNEL_2 (1)
777 *
778 * (1) On this STM32 series, parameter not available on all devices.
779 * Refer to device datasheet for channels availability.
780 * @param OutputBuffer This parameter can be one of the following values:
781 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
782 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
783 * @retval None
784 */
LL_DAC_SetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputBuffer)785 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
786 {
787 MODIFY_REG(DACx->CR,
788 DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
789 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
790 }
791
792 /**
793 * @brief Get the output buffer state for the selected DAC channel.
794 * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
795 * CR BOFF2 LL_DAC_GetOutputBuffer
796 * @param DACx DAC instance
797 * @param DAC_Channel This parameter can be one of the following values:
798 * @arg @ref LL_DAC_CHANNEL_1
799 * @arg @ref LL_DAC_CHANNEL_2 (1)
800 *
801 * (1) On this STM32 series, parameter not available on all devices.
802 * Refer to device datasheet for channels availability.
803 * @retval Returned value can be one of the following values:
804 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
805 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
806 */
LL_DAC_GetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel)807 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
808 {
809 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
810 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
811 );
812 }
813
814 /**
815 * @}
816 */
817
818 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
819 * @{
820 */
821
822 /**
823 * @brief Enable DAC DMA transfer request of the selected channel.
824 * @note To configure DMA source address (peripheral address),
825 * use function @ref LL_DAC_DMA_GetRegAddr().
826 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
827 * CR DMAEN2 LL_DAC_EnableDMAReq
828 * @param DACx DAC instance
829 * @param DAC_Channel This parameter can be one of the following values:
830 * @arg @ref LL_DAC_CHANNEL_1
831 * @arg @ref LL_DAC_CHANNEL_2 (1)
832 *
833 * (1) On this STM32 series, parameter not available on all devices.
834 * Refer to device datasheet for channels availability.
835 * @retval None
836 */
LL_DAC_EnableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)837 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
838 {
839 SET_BIT(DACx->CR,
840 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
841 }
842
843 /**
844 * @brief Disable DAC DMA transfer request of the selected channel.
845 * @note To configure DMA source address (peripheral address),
846 * use function @ref LL_DAC_DMA_GetRegAddr().
847 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
848 * CR DMAEN2 LL_DAC_DisableDMAReq
849 * @param DACx DAC instance
850 * @param DAC_Channel This parameter can be one of the following values:
851 * @arg @ref LL_DAC_CHANNEL_1
852 * @arg @ref LL_DAC_CHANNEL_2 (1)
853 *
854 * (1) On this STM32 series, parameter not available on all devices.
855 * Refer to device datasheet for channels availability.
856 * @retval None
857 */
LL_DAC_DisableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)858 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
859 {
860 CLEAR_BIT(DACx->CR,
861 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
862 }
863
864 /**
865 * @brief Get DAC DMA transfer request state of the selected channel.
866 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
867 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
868 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
869 * @param DACx DAC instance
870 * @param DAC_Channel This parameter can be one of the following values:
871 * @arg @ref LL_DAC_CHANNEL_1
872 * @arg @ref LL_DAC_CHANNEL_2 (1)
873 *
874 * (1) On this STM32 series, parameter not available on all devices.
875 * Refer to device datasheet for channels availability.
876 * @retval State of bit (1 or 0).
877 */
LL_DAC_IsDMAReqEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)878 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
879 {
880 return (READ_BIT(DACx->CR,
881 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
882 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
883 }
884
885 /**
886 * @brief Function to help to configure DMA transfer to DAC: retrieve the
887 * DAC register address from DAC instance and a list of DAC registers
888 * intended to be used (most commonly) with DMA transfer.
889 * @note These DAC registers are data holding registers:
890 * when DAC conversion is requested, DAC generates a DMA transfer
891 * request to have data available in DAC data holding registers.
892 * @note This macro is intended to be used with LL DMA driver, refer to
893 * function "LL_DMA_ConfigAddresses()".
894 * Example:
895 * LL_DMA_ConfigAddresses(DMA1,
896 * LL_DMA_CHANNEL_1,
897 * (uint32_t)&< array or variable >,
898 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
899 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
900 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
901 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
902 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
903 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
904 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
905 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
906 * @param DACx DAC instance
907 * @param DAC_Channel This parameter can be one of the following values:
908 * @arg @ref LL_DAC_CHANNEL_1
909 * @arg @ref LL_DAC_CHANNEL_2 (1)
910 *
911 * (1) On this STM32 series, parameter not available on all devices.
912 * Refer to device datasheet for channels availability.
913 * @param Register This parameter can be one of the following values:
914 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
915 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
916 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
917 * @retval DAC register address
918 */
LL_DAC_DMA_GetRegAddr(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Register)919 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
920 {
921 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
922 /* DAC channel selected. */
923 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> Register) & DAC_REG_REGOFFSET_MASK_POSBIT0))));
924 }
925 /**
926 * @}
927 */
928
929 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
930 * @{
931 */
932
933 /**
934 * @brief Enable DAC selected channel.
935 * @rmtoll CR EN1 LL_DAC_Enable\n
936 * CR EN2 LL_DAC_Enable
937 * @note After enable from off state, DAC channel requires a delay
938 * for output voltage to reach accuracy +/- 1 LSB.
939 * Refer to device datasheet, parameter "tWAKEUP".
940 * @param DACx DAC instance
941 * @param DAC_Channel This parameter can be one of the following values:
942 * @arg @ref LL_DAC_CHANNEL_1
943 * @arg @ref LL_DAC_CHANNEL_2 (1)
944 *
945 * (1) On this STM32 series, parameter not available on all devices.
946 * Refer to device datasheet for channels availability.
947 * @retval None
948 */
LL_DAC_Enable(DAC_TypeDef * DACx,uint32_t DAC_Channel)949 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
950 {
951 SET_BIT(DACx->CR,
952 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
953 }
954
955 /**
956 * @brief Disable DAC selected channel.
957 * @rmtoll CR EN1 LL_DAC_Disable\n
958 * CR EN2 LL_DAC_Disable
959 * @param DACx DAC instance
960 * @param DAC_Channel This parameter can be one of the following values:
961 * @arg @ref LL_DAC_CHANNEL_1
962 * @arg @ref LL_DAC_CHANNEL_2 (1)
963 *
964 * (1) On this STM32 series, parameter not available on all devices.
965 * Refer to device datasheet for channels availability.
966 * @retval None
967 */
LL_DAC_Disable(DAC_TypeDef * DACx,uint32_t DAC_Channel)968 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
969 {
970 CLEAR_BIT(DACx->CR,
971 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
972 }
973
974 /**
975 * @brief Get DAC enable state of the selected channel.
976 * (0: DAC channel is disabled, 1: DAC channel is enabled)
977 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
978 * CR EN2 LL_DAC_IsEnabled
979 * @param DACx DAC instance
980 * @param DAC_Channel This parameter can be one of the following values:
981 * @arg @ref LL_DAC_CHANNEL_1
982 * @arg @ref LL_DAC_CHANNEL_2 (1)
983 *
984 * (1) On this STM32 series, parameter not available on all devices.
985 * Refer to device datasheet for channels availability.
986 * @retval State of bit (1 or 0).
987 */
LL_DAC_IsEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)988 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
989 {
990 return (READ_BIT(DACx->CR,
991 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
992 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
993 }
994
995 /**
996 * @brief Enable DAC trigger of the selected channel.
997 * @note - If DAC trigger is disabled, DAC conversion is performed
998 * automatically once the data holding register is updated,
999 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1000 * @ref LL_DAC_ConvertData12RightAligned(), ...
1001 * - If DAC trigger is enabled, DAC conversion is performed
1002 * only when a hardware of software trigger event is occurring.
1003 * Select trigger source using
1004 * function @ref LL_DAC_SetTriggerSource().
1005 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
1006 * CR TEN2 LL_DAC_EnableTrigger
1007 * @param DACx DAC instance
1008 * @param DAC_Channel This parameter can be one of the following values:
1009 * @arg @ref LL_DAC_CHANNEL_1
1010 * @arg @ref LL_DAC_CHANNEL_2 (1)
1011 *
1012 * (1) On this STM32 series, parameter not available on all devices.
1013 * Refer to device datasheet for channels availability.
1014 * @retval None
1015 */
LL_DAC_EnableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1016 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1017 {
1018 SET_BIT(DACx->CR,
1019 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1020 }
1021
1022 /**
1023 * @brief Disable DAC trigger of the selected channel.
1024 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
1025 * CR TEN2 LL_DAC_DisableTrigger
1026 * @param DACx DAC instance
1027 * @param DAC_Channel This parameter can be one of the following values:
1028 * @arg @ref LL_DAC_CHANNEL_1
1029 * @arg @ref LL_DAC_CHANNEL_2 (1)
1030 *
1031 * (1) On this STM32 series, parameter not available on all devices.
1032 * Refer to device datasheet for channels availability.
1033 * @retval None
1034 */
LL_DAC_DisableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1035 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1036 {
1037 CLEAR_BIT(DACx->CR,
1038 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1039 }
1040
1041 /**
1042 * @brief Get DAC trigger state of the selected channel.
1043 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
1044 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
1045 * CR TEN2 LL_DAC_IsTriggerEnabled
1046 * @param DACx DAC instance
1047 * @param DAC_Channel This parameter can be one of the following values:
1048 * @arg @ref LL_DAC_CHANNEL_1
1049 * @arg @ref LL_DAC_CHANNEL_2 (1)
1050 *
1051 * (1) On this STM32 series, parameter not available on all devices.
1052 * Refer to device datasheet for channels availability.
1053 * @retval State of bit (1 or 0).
1054 */
LL_DAC_IsTriggerEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)1055 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1056 {
1057 return (READ_BIT(DACx->CR,
1058 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1059 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
1060 }
1061
1062 /**
1063 * @brief Trig DAC conversion by software for the selected DAC channel.
1064 * @note Preliminarily, DAC trigger must be set to software trigger
1065 * using function @ref LL_DAC_SetTriggerSource()
1066 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
1067 * and DAC trigger must be enabled using
1068 * function @ref LL_DAC_EnableTrigger().
1069 * @note For devices featuring DAC with 2 channels: this function
1070 * can perform a SW start of both DAC channels simultaneously.
1071 * Two channels can be selected as parameter.
1072 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
1073 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
1074 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
1075 * @param DACx DAC instance
1076 * @param DAC_Channel This parameter can a combination of the following values:
1077 * @arg @ref LL_DAC_CHANNEL_1
1078 * @arg @ref LL_DAC_CHANNEL_2 (1)
1079 *
1080 * (1) On this STM32 series, parameter not available on all devices.
1081 * Refer to device datasheet for channels availability.
1082 * @retval None
1083 */
LL_DAC_TrigSWConversion(DAC_TypeDef * DACx,uint32_t DAC_Channel)1084 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1085 {
1086 SET_BIT(DACx->SWTRIGR,
1087 (DAC_Channel & DAC_SWTR_CHX_MASK));
1088 }
1089
1090 /**
1091 * @brief Set the data to be loaded in the data holding register
1092 * in format 12 bits left alignment (LSB aligned on bit 0),
1093 * for the selected DAC channel.
1094 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
1095 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
1096 * @param DACx DAC instance
1097 * @param DAC_Channel This parameter can be one of the following values:
1098 * @arg @ref LL_DAC_CHANNEL_1
1099 * @arg @ref LL_DAC_CHANNEL_2 (1)
1100 *
1101 * (1) On this STM32 series, parameter not available on all devices.
1102 * Refer to device datasheet for channels availability.
1103 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1104 * @retval None
1105 */
LL_DAC_ConvertData12RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1106 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1107 {
1108 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
1109
1110 MODIFY_REG(*preg,
1111 DAC_DHR12R1_DACC1DHR,
1112 Data);
1113 }
1114
1115 /**
1116 * @brief Set the data to be loaded in the data holding register
1117 * in format 12 bits left alignment (MSB aligned on bit 15),
1118 * for the selected DAC channel.
1119 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
1120 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
1121 * @param DACx DAC instance
1122 * @param DAC_Channel This parameter can be one of the following values:
1123 * @arg @ref LL_DAC_CHANNEL_1
1124 * @arg @ref LL_DAC_CHANNEL_2 (1)
1125 *
1126 * (1) On this STM32 series, parameter not available on all devices.
1127 * Refer to device datasheet for channels availability.
1128 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1129 * @retval None
1130 */
LL_DAC_ConvertData12LeftAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1131 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1132 {
1133 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
1134
1135 MODIFY_REG(*preg,
1136 DAC_DHR12L1_DACC1DHR,
1137 Data);
1138 }
1139
1140 /**
1141 * @brief Set the data to be loaded in the data holding register
1142 * in format 8 bits left alignment (LSB aligned on bit 0),
1143 * for the selected DAC channel.
1144 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
1145 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
1146 * @param DACx DAC instance
1147 * @param DAC_Channel This parameter can be one of the following values:
1148 * @arg @ref LL_DAC_CHANNEL_1
1149 * @arg @ref LL_DAC_CHANNEL_2 (1)
1150 *
1151 * (1) On this STM32 series, parameter not available on all devices.
1152 * Refer to device datasheet for channels availability.
1153 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1154 * @retval None
1155 */
LL_DAC_ConvertData8RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1156 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1157 {
1158 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
1159
1160 MODIFY_REG(*preg,
1161 DAC_DHR8R1_DACC1DHR,
1162 Data);
1163 }
1164
1165 #if defined(DAC_CHANNEL2_SUPPORT)
1166 /**
1167 * @brief Set the data to be loaded in the data holding register
1168 * in format 12 bits left alignment (LSB aligned on bit 0),
1169 * for both DAC channels.
1170 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
1171 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
1172 * @param DACx DAC instance
1173 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1174 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1175 * @retval None
1176 */
LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1177 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1178 {
1179 MODIFY_REG(DACx->DHR12RD,
1180 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
1181 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1182 }
1183
1184 /**
1185 * @brief Set the data to be loaded in the data holding register
1186 * in format 12 bits left alignment (MSB aligned on bit 15),
1187 * for both DAC channels.
1188 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
1189 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
1190 * @param DACx DAC instance
1191 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1192 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1193 * @retval None
1194 */
LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1195 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1196 {
1197 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
1198 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
1199 /* the 4 LSB must be taken into account for the shift value. */
1200 MODIFY_REG(DACx->DHR12LD,
1201 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
1202 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
1203 }
1204
1205 /**
1206 * @brief Set the data to be loaded in the data holding register
1207 * in format 8 bits left alignment (LSB aligned on bit 0),
1208 * for both DAC channels.
1209 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
1210 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
1211 * @param DACx DAC instance
1212 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
1213 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
1214 * @retval None
1215 */
LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1216 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1217 {
1218 MODIFY_REG(DACx->DHR8RD,
1219 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
1220 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1221 }
1222
1223 #endif /* DAC_CHANNEL2_SUPPORT */
1224 /**
1225 * @brief Retrieve output data currently generated for the selected DAC channel.
1226 * @note Whatever alignment and resolution settings
1227 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1228 * @ref LL_DAC_ConvertData12RightAligned(), ...),
1229 * output data format is 12 bits right aligned (LSB aligned on bit 0).
1230 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
1231 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
1232 * @param DACx DAC instance
1233 * @param DAC_Channel This parameter can be one of the following values:
1234 * @arg @ref LL_DAC_CHANNEL_1
1235 * @arg @ref LL_DAC_CHANNEL_2 (1)
1236 *
1237 * (1) On this STM32 series, parameter not available on all devices.
1238 * Refer to device datasheet for channels availability.
1239 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1240 */
LL_DAC_RetrieveOutputData(DAC_TypeDef * DACx,uint32_t DAC_Channel)1241 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1242 {
1243 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
1244
1245 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1246 }
1247
1248 /**
1249 * @}
1250 */
1251
1252 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
1253 * @{
1254 */
1255 /**
1256 * @brief Get DAC underrun flag for DAC channel 1
1257 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
1258 * @param DACx DAC instance
1259 * @retval State of bit (1 or 0).
1260 */
LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef * DACx)1261 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
1262 {
1263 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
1264 }
1265
1266 #if defined(DAC_CHANNEL2_SUPPORT)
1267 /**
1268 * @brief Get DAC underrun flag for DAC channel 2
1269 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
1270 * @param DACx DAC instance
1271 * @retval State of bit (1 or 0).
1272 */
LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef * DACx)1273 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
1274 {
1275 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
1276 }
1277 #endif /* DAC_CHANNEL2_SUPPORT */
1278
1279 /**
1280 * @brief Clear DAC underrun flag for DAC channel 1
1281 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
1282 * @param DACx DAC instance
1283 * @retval None
1284 */
LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef * DACx)1285 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1286 {
1287 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1288 }
1289
1290 #if defined(DAC_CHANNEL2_SUPPORT)
1291 /**
1292 * @brief Clear DAC underrun flag for DAC channel 2
1293 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
1294 * @param DACx DAC instance
1295 * @retval None
1296 */
LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef * DACx)1297 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
1298 {
1299 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
1300 }
1301 #endif /* DAC_CHANNEL2_SUPPORT */
1302
1303 /**
1304 * @}
1305 */
1306
1307 /** @defgroup DAC_LL_EF_IT_Management IT management
1308 * @{
1309 */
1310
1311 /**
1312 * @brief Enable DMA underrun interrupt for DAC channel 1
1313 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
1314 * @param DACx DAC instance
1315 * @retval None
1316 */
LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef * DACx)1317 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1318 {
1319 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1320 }
1321
1322 #if defined(DAC_CHANNEL2_SUPPORT)
1323 /**
1324 * @brief Enable DMA underrun interrupt for DAC channel 2
1325 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
1326 * @param DACx DAC instance
1327 * @retval None
1328 */
LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef * DACx)1329 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
1330 {
1331 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1332 }
1333 #endif /* DAC_CHANNEL2_SUPPORT */
1334
1335 /**
1336 * @brief Disable DMA underrun interrupt for DAC channel 1
1337 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
1338 * @param DACx DAC instance
1339 * @retval None
1340 */
LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef * DACx)1341 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1342 {
1343 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1344 }
1345
1346 #if defined(DAC_CHANNEL2_SUPPORT)
1347 /**
1348 * @brief Disable DMA underrun interrupt for DAC channel 2
1349 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
1350 * @param DACx DAC instance
1351 * @retval None
1352 */
LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef * DACx)1353 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
1354 {
1355 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1356 }
1357 #endif /* DAC_CHANNEL2_SUPPORT */
1358
1359 /**
1360 * @brief Get DMA underrun interrupt for DAC channel 1
1361 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
1362 * @param DACx DAC instance
1363 * @retval State of bit (1 or 0).
1364 */
LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef * DACx)1365 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
1366 {
1367 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
1368 }
1369
1370 #if defined(DAC_CHANNEL2_SUPPORT)
1371 /**
1372 * @brief Get DMA underrun interrupt for DAC channel 2
1373 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
1374 * @param DACx DAC instance
1375 * @retval State of bit (1 or 0).
1376 */
LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef * DACx)1377 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
1378 {
1379 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
1380 }
1381 #endif /* DAC_CHANNEL2_SUPPORT */
1382
1383 /**
1384 * @}
1385 */
1386
1387 #if defined(USE_FULL_LL_DRIVER)
1388 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
1389 * @{
1390 */
1391
1392 ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
1393 ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
1394 void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
1395
1396 /**
1397 * @}
1398 */
1399 #endif /* USE_FULL_LL_DRIVER */
1400
1401 /**
1402 * @}
1403 */
1404
1405 /**
1406 * @}
1407 */
1408
1409 #endif /* DAC1 */
1410
1411 /**
1412 * @}
1413 */
1414
1415 #ifdef __cplusplus
1416 }
1417 #endif
1418
1419 #endif /* __STM32F0xx_LL_DAC_H */
1420
1421
