1 /**
2 ******************************************************************************
3 * @file stm32f0xx_ll_crs.h
4 * @author MCD Application Team
5 * @brief Header file of CRS LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32F0xx_LL_CRS_H
21 #define __STM32F0xx_LL_CRS_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f0xx.h"
29
30 /** @addtogroup STM32F0xx_LL_Driver
31 * @{
32 */
33
34 #if defined(CRS)
35
36 /** @defgroup CRS_LL CRS
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44
45 /* Exported types ------------------------------------------------------------*/
46 /* Exported constants --------------------------------------------------------*/
47 /** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
48 * @{
49 */
50
51 /** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
52 * @brief Flags defines which can be used with LL_CRS_ReadReg function
53 * @{
54 */
55 #define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
56 #define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
57 #define LL_CRS_ISR_ERRF CRS_ISR_ERRF
58 #define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
59 #define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
60 #define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
61 #define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
62 /**
63 * @}
64 */
65
66 /** @defgroup CRS_LL_EC_IT IT Defines
67 * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions
68 * @{
69 */
70 #define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
71 #define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
72 #define LL_CRS_CR_ERRIE CRS_CR_ERRIE
73 #define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
74 /**
75 * @}
76 */
77
78 /** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
79 * @{
80 */
81 #define LL_CRS_SYNC_DIV_1 ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */
82 #define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
83 #define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
84 #define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
85 #define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
86 #define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
87 #define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
88 #define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
89 /**
90 * @}
91 */
92
93 /** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
94 * @{
95 */
96 #define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal source GPIO */
97 #define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
98 #define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
99 /**
100 * @}
101 */
102
103 /** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
104 * @{
105 */
106 #define LL_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00U) /*!< Synchro Active on rising edge (default) */
107 #define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
108 /**
109 * @}
110 */
111
112 /** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
113 * @{
114 */
115 #define LL_CRS_FREQ_ERROR_DIR_UP ((uint32_t)0x00U) /*!< Upcounting direction, the actual frequency is above the target */
116 #define LL_CRS_FREQ_ERROR_DIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
117 /**
118 * @}
119 */
120
121 /** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
122 * @{
123 */
124 /**
125 * @brief Reset value of the RELOAD field
126 * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
127 * and a synchronization signal frequency of 1 kHz (SOF signal from USB)
128 */
129 #define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU)
130
131 /**
132 * @brief Reset value of Frequency error limit.
133 */
134 #define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U)
135
136 /**
137 * @brief Reset value of the HSI48 Calibration field
138 * @note The default value is 32, which corresponds to the middle of the trimming interval.
139 * The trimming step is around 67 kHz between two consecutive TRIM steps.
140 * A higher TRIM value corresponds to a higher output frequency
141 */
142 #define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20U)
143 /**
144 * @}
145 */
146
147 /**
148 * @}
149 */
150
151 /* Exported macro ------------------------------------------------------------*/
152 /** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
153 * @{
154 */
155
156 /** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
157 * @{
158 */
159
160 /**
161 * @brief Write a value in CRS register
162 * @param __INSTANCE__ CRS Instance
163 * @param __REG__ Register to be written
164 * @param __VALUE__ Value to be written in the register
165 * @retval None
166 */
167 #define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
168
169 /**
170 * @brief Read a value in CRS register
171 * @param __INSTANCE__ CRS Instance
172 * @param __REG__ Register to be read
173 * @retval Register value
174 */
175 #define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
176 /**
177 * @}
178 */
179
180 /** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
181 * @{
182 */
183
184 /**
185 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
186 * @note The RELOAD value should be selected according to the ratio between
187 * the target frequency and the frequency of the synchronization source after
188 * prescaling. It is then decreased by one in order to reach the expected
189 * synchronization on the zero value. The formula is the following:
190 * RELOAD = (fTARGET / fSYNC) -1
191 * @param __FTARGET__ Target frequency (value in Hz)
192 * @param __FSYNC__ Synchronization signal frequency (value in Hz)
193 * @retval Reload value (in Hz)
194 */
195 #define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
196
197 /**
198 * @}
199 */
200
201 /**
202 * @}
203 */
204
205 /* Exported functions --------------------------------------------------------*/
206 /** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
207 * @{
208 */
209
210 /** @defgroup CRS_LL_EF_Configuration Configuration
211 * @{
212 */
213
214 /**
215 * @brief Enable Frequency error counter
216 * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
217 * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter
218 * @retval None
219 */
LL_CRS_EnableFreqErrorCounter(void)220 __STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
221 {
222 SET_BIT(CRS->CR, CRS_CR_CEN);
223 }
224
225 /**
226 * @brief Disable Frequency error counter
227 * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter
228 * @retval None
229 */
LL_CRS_DisableFreqErrorCounter(void)230 __STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
231 {
232 CLEAR_BIT(CRS->CR, CRS_CR_CEN);
233 }
234
235 /**
236 * @brief Check if Frequency error counter is enabled or not
237 * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter
238 * @retval State of bit (1 or 0).
239 */
LL_CRS_IsEnabledFreqErrorCounter(void)240 __STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
241 {
242 return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN));
243 }
244
245 /**
246 * @brief Enable Automatic trimming counter
247 * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
248 * @retval None
249 */
LL_CRS_EnableAutoTrimming(void)250 __STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
251 {
252 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
253 }
254
255 /**
256 * @brief Disable Automatic trimming counter
257 * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
258 * @retval None
259 */
LL_CRS_DisableAutoTrimming(void)260 __STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
261 {
262 CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
263 }
264
265 /**
266 * @brief Check if Automatic trimming is enabled or not
267 * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
268 * @retval State of bit (1 or 0).
269 */
LL_CRS_IsEnabledAutoTrimming(void)270 __STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
271 {
272 return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN));
273 }
274
275 /**
276 * @brief Set HSI48 oscillator smooth trimming
277 * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
278 * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming
279 * @param Value a number between Min_Data = 0 and Max_Data = 63
280 * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
281 * @retval None
282 */
LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)283 __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
284 {
285 MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);
286 }
287
288 /**
289 * @brief Get HSI48 oscillator smooth trimming
290 * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming
291 * @retval a number between Min_Data = 0 and Max_Data = 63
292 */
LL_CRS_GetHSI48SmoothTrimming(void)293 __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
294 {
295 return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
296 }
297
298 /**
299 * @brief Set counter reload value
300 * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter
301 * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF
302 * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
303 * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
304 * @retval None
305 */
LL_CRS_SetReloadCounter(uint32_t Value)306 __STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
307 {
308 MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
309 }
310
311 /**
312 * @brief Get counter reload value
313 * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter
314 * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
315 */
LL_CRS_GetReloadCounter(void)316 __STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
317 {
318 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
319 }
320
321 /**
322 * @brief Set frequency error limit
323 * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit
324 * @param Value a number between Min_Data = 0 and Max_Data = 255
325 * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
326 * @retval None
327 */
LL_CRS_SetFreqErrorLimit(uint32_t Value)328 __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
329 {
330 MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);
331 }
332
333 /**
334 * @brief Get frequency error limit
335 * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit
336 * @retval A number between Min_Data = 0 and Max_Data = 255
337 */
LL_CRS_GetFreqErrorLimit(void)338 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
339 {
340 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);
341 }
342
343 /**
344 * @brief Set division factor for SYNC signal
345 * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider
346 * @param Divider This parameter can be one of the following values:
347 * @arg @ref LL_CRS_SYNC_DIV_1
348 * @arg @ref LL_CRS_SYNC_DIV_2
349 * @arg @ref LL_CRS_SYNC_DIV_4
350 * @arg @ref LL_CRS_SYNC_DIV_8
351 * @arg @ref LL_CRS_SYNC_DIV_16
352 * @arg @ref LL_CRS_SYNC_DIV_32
353 * @arg @ref LL_CRS_SYNC_DIV_64
354 * @arg @ref LL_CRS_SYNC_DIV_128
355 * @retval None
356 */
LL_CRS_SetSyncDivider(uint32_t Divider)357 __STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
358 {
359 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
360 }
361
362 /**
363 * @brief Get division factor for SYNC signal
364 * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider
365 * @retval Returned value can be one of the following values:
366 * @arg @ref LL_CRS_SYNC_DIV_1
367 * @arg @ref LL_CRS_SYNC_DIV_2
368 * @arg @ref LL_CRS_SYNC_DIV_4
369 * @arg @ref LL_CRS_SYNC_DIV_8
370 * @arg @ref LL_CRS_SYNC_DIV_16
371 * @arg @ref LL_CRS_SYNC_DIV_32
372 * @arg @ref LL_CRS_SYNC_DIV_64
373 * @arg @ref LL_CRS_SYNC_DIV_128
374 */
LL_CRS_GetSyncDivider(void)375 __STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
376 {
377 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
378 }
379
380 /**
381 * @brief Set SYNC signal source
382 * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource
383 * @param Source This parameter can be one of the following values:
384 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
385 * @arg @ref LL_CRS_SYNC_SOURCE_LSE
386 * @arg @ref LL_CRS_SYNC_SOURCE_USB
387 * @retval None
388 */
LL_CRS_SetSyncSignalSource(uint32_t Source)389 __STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
390 {
391 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
392 }
393
394 /**
395 * @brief Get SYNC signal source
396 * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource
397 * @retval Returned value can be one of the following values:
398 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
399 * @arg @ref LL_CRS_SYNC_SOURCE_LSE
400 * @arg @ref LL_CRS_SYNC_SOURCE_USB
401 */
LL_CRS_GetSyncSignalSource(void)402 __STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
403 {
404 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
405 }
406
407 /**
408 * @brief Set input polarity for the SYNC signal source
409 * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity
410 * @param Polarity This parameter can be one of the following values:
411 * @arg @ref LL_CRS_SYNC_POLARITY_RISING
412 * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
413 * @retval None
414 */
LL_CRS_SetSyncPolarity(uint32_t Polarity)415 __STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
416 {
417 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
418 }
419
420 /**
421 * @brief Get input polarity for the SYNC signal source
422 * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity
423 * @retval Returned value can be one of the following values:
424 * @arg @ref LL_CRS_SYNC_POLARITY_RISING
425 * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
426 */
LL_CRS_GetSyncPolarity(void)427 __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
428 {
429 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
430 }
431
432 /**
433 * @brief Configure CRS for the synchronization
434 * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n
435 * CFGR RELOAD LL_CRS_ConfigSynchronization\n
436 * CFGR FELIM LL_CRS_ConfigSynchronization\n
437 * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n
438 * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n
439 * CFGR SYNCPOL LL_CRS_ConfigSynchronization
440 * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
441 * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
442 * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255
443 * @param Settings This parameter can be a combination of the following values:
444 * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
445 * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
446 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
447 * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
448 * @retval None
449 */
LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue,uint32_t ErrorLimitValue,uint32_t ReloadValue,uint32_t Settings)450 __STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
451 {
452 MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue << CRS_CR_TRIM_Pos);
453 MODIFY_REG(CRS->CFGR,
454 CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
455 ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
456 }
457
458 /**
459 * @}
460 */
461
462 /** @defgroup CRS_LL_EF_CRS_Management CRS_Management
463 * @{
464 */
465
466 /**
467 * @brief Generate software SYNC event
468 * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
469 * @retval None
470 */
LL_CRS_GenerateEvent_SWSYNC(void)471 __STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
472 {
473 SET_BIT(CRS->CR, CRS_CR_SWSYNC);
474 }
475
476 /**
477 * @brief Get the frequency error direction latched in the time of the last
478 * SYNC event
479 * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection
480 * @retval Returned value can be one of the following values:
481 * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
482 * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
483 */
LL_CRS_GetFreqErrorDirection(void)484 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
485 {
486 return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
487 }
488
489 /**
490 * @brief Get the frequency error counter value latched in the time of the last SYNC event
491 * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture
492 * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
493 */
LL_CRS_GetFreqErrorCapture(void)494 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
495 {
496 return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
497 }
498
499 /**
500 * @}
501 */
502
503 /** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
504 * @{
505 */
506
507 /**
508 * @brief Check if SYNC event OK signal occurred or not
509 * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
510 * @retval State of bit (1 or 0).
511 */
LL_CRS_IsActiveFlag_SYNCOK(void)512 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
513 {
514 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF));
515 }
516
517 /**
518 * @brief Check if SYNC warning signal occurred or not
519 * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
520 * @retval State of bit (1 or 0).
521 */
LL_CRS_IsActiveFlag_SYNCWARN(void)522 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
523 {
524 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF));
525 }
526
527 /**
528 * @brief Check if Synchronization or trimming error signal occurred or not
529 * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR
530 * @retval State of bit (1 or 0).
531 */
LL_CRS_IsActiveFlag_ERR(void)532 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
533 {
534 return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF));
535 }
536
537 /**
538 * @brief Check if Expected SYNC signal occurred or not
539 * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
540 * @retval State of bit (1 or 0).
541 */
LL_CRS_IsActiveFlag_ESYNC(void)542 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
543 {
544 return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF));
545 }
546
547 /**
548 * @brief Check if SYNC error signal occurred or not
549 * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
550 * @retval State of bit (1 or 0).
551 */
LL_CRS_IsActiveFlag_SYNCERR(void)552 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
553 {
554 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR));
555 }
556
557 /**
558 * @brief Check if SYNC missed error signal occurred or not
559 * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
560 * @retval State of bit (1 or 0).
561 */
LL_CRS_IsActiveFlag_SYNCMISS(void)562 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
563 {
564 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS));
565 }
566
567 /**
568 * @brief Check if Trimming overflow or underflow occurred or not
569 * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
570 * @retval State of bit (1 or 0).
571 */
LL_CRS_IsActiveFlag_TRIMOVF(void)572 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
573 {
574 return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF));
575 }
576
577 /**
578 * @brief Clear the SYNC event OK flag
579 * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
580 * @retval None
581 */
LL_CRS_ClearFlag_SYNCOK(void)582 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
583 {
584 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
585 }
586
587 /**
588 * @brief Clear the SYNC warning flag
589 * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
590 * @retval None
591 */
LL_CRS_ClearFlag_SYNCWARN(void)592 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
593 {
594 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
595 }
596
597 /**
598 * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
599 * the ERR flag
600 * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR
601 * @retval None
602 */
LL_CRS_ClearFlag_ERR(void)603 __STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
604 {
605 WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
606 }
607
608 /**
609 * @brief Clear Expected SYNC flag
610 * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC
611 * @retval None
612 */
LL_CRS_ClearFlag_ESYNC(void)613 __STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
614 {
615 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
616 }
617
618 /**
619 * @}
620 */
621
622 /** @defgroup CRS_LL_EF_IT_Management IT_Management
623 * @{
624 */
625
626 /**
627 * @brief Enable SYNC event OK interrupt
628 * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
629 * @retval None
630 */
LL_CRS_EnableIT_SYNCOK(void)631 __STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
632 {
633 SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
634 }
635
636 /**
637 * @brief Disable SYNC event OK interrupt
638 * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
639 * @retval None
640 */
LL_CRS_DisableIT_SYNCOK(void)641 __STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
642 {
643 CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
644 }
645
646 /**
647 * @brief Check if SYNC event OK interrupt is enabled or not
648 * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
649 * @retval State of bit (1 or 0).
650 */
LL_CRS_IsEnabledIT_SYNCOK(void)651 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
652 {
653 return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE));
654 }
655
656 /**
657 * @brief Enable SYNC warning interrupt
658 * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
659 * @retval None
660 */
LL_CRS_EnableIT_SYNCWARN(void)661 __STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
662 {
663 SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
664 }
665
666 /**
667 * @brief Disable SYNC warning interrupt
668 * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
669 * @retval None
670 */
LL_CRS_DisableIT_SYNCWARN(void)671 __STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
672 {
673 CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
674 }
675
676 /**
677 * @brief Check if SYNC warning interrupt is enabled or not
678 * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
679 * @retval State of bit (1 or 0).
680 */
LL_CRS_IsEnabledIT_SYNCWARN(void)681 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
682 {
683 return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE));
684 }
685
686 /**
687 * @brief Enable Synchronization or trimming error interrupt
688 * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR
689 * @retval None
690 */
LL_CRS_EnableIT_ERR(void)691 __STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
692 {
693 SET_BIT(CRS->CR, CRS_CR_ERRIE);
694 }
695
696 /**
697 * @brief Disable Synchronization or trimming error interrupt
698 * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR
699 * @retval None
700 */
LL_CRS_DisableIT_ERR(void)701 __STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
702 {
703 CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
704 }
705
706 /**
707 * @brief Check if Synchronization or trimming error interrupt is enabled or not
708 * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR
709 * @retval State of bit (1 or 0).
710 */
LL_CRS_IsEnabledIT_ERR(void)711 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
712 {
713 return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE));
714 }
715
716 /**
717 * @brief Enable Expected SYNC interrupt
718 * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC
719 * @retval None
720 */
LL_CRS_EnableIT_ESYNC(void)721 __STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
722 {
723 SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
724 }
725
726 /**
727 * @brief Disable Expected SYNC interrupt
728 * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC
729 * @retval None
730 */
LL_CRS_DisableIT_ESYNC(void)731 __STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
732 {
733 CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
734 }
735
736 /**
737 * @brief Check if Expected SYNC interrupt is enabled or not
738 * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
739 * @retval State of bit (1 or 0).
740 */
LL_CRS_IsEnabledIT_ESYNC(void)741 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
742 {
743 return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE));
744 }
745
746 /**
747 * @}
748 */
749
750 #if defined(USE_FULL_LL_DRIVER)
751 /** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
752 * @{
753 */
754
755 ErrorStatus LL_CRS_DeInit(void);
756
757 /**
758 * @}
759 */
760 #endif /* USE_FULL_LL_DRIVER */
761
762 /**
763 * @}
764 */
765
766 /**
767 * @}
768 */
769
770 #endif /* defined(CRS) */
771
772 /**
773 * @}
774 */
775
776 #ifdef __cplusplus
777 }
778 #endif
779
780 #endif /* __STM32F0xx_LL_CRS_H */
781
