1 /**
2 ******************************************************************************
3 * @file stm32f0xx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32F0xx_LL_ADC_H
21 #define __STM32F0xx_LL_ADC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f0xx.h"
29
30 /** @addtogroup STM32F0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1)
35
36 /** @defgroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
45 * @{
46 */
47
48 /* Internal mask for ADC group regular trigger: */
49 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
50 /* - regular trigger source */
51 /* - regular trigger edge */
52 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
53
54 /* Mask containing trigger source masks for each of possible */
55 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
56 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
57 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0U)) | \
58 ((ADC_CFGR1_EXTSEL) << (4U * 1U)) | \
59 ((ADC_CFGR1_EXTSEL) << (4U * 2U)) | \
60 ((ADC_CFGR1_EXTSEL) << (4U * 3U)) )
61
62 /* Mask containing trigger edge masks for each of possible */
63 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
64 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
65 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0U)) | \
66 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1U)) | \
67 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2U)) | \
68 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3U)) )
69
70 /* Definition of ADC group regular trigger bits information. */
71 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_EXTSEL) */
72 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_EXTEN) */
73
74
75
76 /* Internal mask for ADC channel: */
77 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
78 /* - channel identifier defined by number */
79 /* - channel identifier defined by bitfield */
80 /* - channel differentiation between external channels (connected to */
81 /* GPIO pins) and internal channels (connected to internal paths) */
82 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWDCH)
83 #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL)
84 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
85 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
86 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
87 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FU) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
88
89 /* Channel differentiation between external and internal channels */
90 #define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000U) /* Marker of internal channel */
91 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH)
92
93 /* Definition of channels ID number information to be inserted into */
94 /* channels literals definition. */
95 #define ADC_CHANNEL_0_NUMBER (0x00000000U)
96 #define ADC_CHANNEL_1_NUMBER ( ADC_CFGR1_AWDCH_0)
97 #define ADC_CHANNEL_2_NUMBER ( ADC_CFGR1_AWDCH_1 )
98 #define ADC_CHANNEL_3_NUMBER ( ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
99 #define ADC_CHANNEL_4_NUMBER ( ADC_CFGR1_AWDCH_2 )
100 #define ADC_CHANNEL_5_NUMBER ( ADC_CFGR1_AWDCH_2 | ADC_CFGR1_AWDCH_0)
101 #define ADC_CHANNEL_6_NUMBER ( ADC_CFGR1_AWDCH_2 | ADC_CFGR1_AWDCH_1 )
102 #define ADC_CHANNEL_7_NUMBER ( ADC_CFGR1_AWDCH_2 | ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
103 #define ADC_CHANNEL_8_NUMBER ( ADC_CFGR1_AWDCH_3 )
104 #define ADC_CHANNEL_9_NUMBER ( ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_0)
105 #define ADC_CHANNEL_10_NUMBER ( ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_1 )
106 #define ADC_CHANNEL_11_NUMBER ( ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
107 #define ADC_CHANNEL_12_NUMBER ( ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_2 )
108 #define ADC_CHANNEL_13_NUMBER ( ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_2 | ADC_CFGR1_AWDCH_0)
109 #define ADC_CHANNEL_14_NUMBER ( ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_2 | ADC_CFGR1_AWDCH_1 )
110 #define ADC_CHANNEL_15_NUMBER ( ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_2 | ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
111 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR1_AWDCH_4 )
112 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR1_AWDCH_4 | ADC_CFGR1_AWDCH_0)
113 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR1_AWDCH_4 | ADC_CFGR1_AWDCH_1 )
114
115 /* Definition of channels ID bitfield information to be inserted into */
116 /* channels literals definition. */
117 #define ADC_CHANNEL_0_BITFIELD (ADC_CHSELR_CHSEL0)
118 #define ADC_CHANNEL_1_BITFIELD (ADC_CHSELR_CHSEL1)
119 #define ADC_CHANNEL_2_BITFIELD (ADC_CHSELR_CHSEL2)
120 #define ADC_CHANNEL_3_BITFIELD (ADC_CHSELR_CHSEL3)
121 #define ADC_CHANNEL_4_BITFIELD (ADC_CHSELR_CHSEL4)
122 #define ADC_CHANNEL_5_BITFIELD (ADC_CHSELR_CHSEL5)
123 #define ADC_CHANNEL_6_BITFIELD (ADC_CHSELR_CHSEL6)
124 #define ADC_CHANNEL_7_BITFIELD (ADC_CHSELR_CHSEL7)
125 #define ADC_CHANNEL_8_BITFIELD (ADC_CHSELR_CHSEL8)
126 #define ADC_CHANNEL_9_BITFIELD (ADC_CHSELR_CHSEL9)
127 #define ADC_CHANNEL_10_BITFIELD (ADC_CHSELR_CHSEL10)
128 #define ADC_CHANNEL_11_BITFIELD (ADC_CHSELR_CHSEL11)
129 #define ADC_CHANNEL_12_BITFIELD (ADC_CHSELR_CHSEL12)
130 #define ADC_CHANNEL_13_BITFIELD (ADC_CHSELR_CHSEL13)
131 #define ADC_CHANNEL_14_BITFIELD (ADC_CHSELR_CHSEL14)
132 #define ADC_CHANNEL_15_BITFIELD (ADC_CHSELR_CHSEL15)
133 #define ADC_CHANNEL_16_BITFIELD (ADC_CHSELR_CHSEL16)
134 #define ADC_CHANNEL_17_BITFIELD (ADC_CHSELR_CHSEL17)
135 #define ADC_CHANNEL_18_BITFIELD (ADC_CHSELR_CHSEL18)
136
137 /* Internal mask for ADC analog watchdog: */
138 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
139 /* (concatenation of multiple bits used in different analog watchdogs, */
140 /* (feature of several watchdogs not available on all STM32 families)). */
141 /* - analog watchdog 1: monitored channel defined by number, */
142 /* selection of ADC group (ADC group regular). */
143
144 /* Internal register offset for ADC analog watchdog channel configuration */
145 #define ADC_AWD_CR1_REGOFFSET (0x00000000U)
146
147 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
148
149 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)
150 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
151
152 /* Internal register offset for ADC analog watchdog threshold configuration */
153 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
154 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET)
155
156
157 /* ADC registers bits positions */
158 #define ADC_CFGR1_RES_BITOFFSET_POS ( 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_RES) */
159 #define ADC_CFGR1_AWDSGL_BITOFFSET_POS (22U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_AWDSGL) */
160 #define ADC_TR_HT_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
161 #define ADC_CHSELR_CHSEL0_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL0) */
162 #define ADC_CHSELR_CHSEL1_BITOFFSET_POS ( 1U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL1) */
163 #define ADC_CHSELR_CHSEL2_BITOFFSET_POS ( 2U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL2) */
164 #define ADC_CHSELR_CHSEL3_BITOFFSET_POS ( 3U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL3) */
165 #define ADC_CHSELR_CHSEL4_BITOFFSET_POS ( 4U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL4) */
166 #define ADC_CHSELR_CHSEL5_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL5) */
167 #define ADC_CHSELR_CHSEL6_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL6) */
168 #define ADC_CHSELR_CHSEL7_BITOFFSET_POS ( 7U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL7) */
169 #define ADC_CHSELR_CHSEL8_BITOFFSET_POS ( 8U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL8) */
170 #define ADC_CHSELR_CHSEL9_BITOFFSET_POS ( 9U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL9) */
171 #define ADC_CHSELR_CHSEL10_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL10) */
172 #define ADC_CHSELR_CHSEL11_BITOFFSET_POS (11U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL11) */
173 #define ADC_CHSELR_CHSEL12_BITOFFSET_POS (12U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL12) */
174 #define ADC_CHSELR_CHSEL13_BITOFFSET_POS (13U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL13) */
175 #define ADC_CHSELR_CHSEL14_BITOFFSET_POS (14U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL14) */
176 #define ADC_CHSELR_CHSEL15_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL15) */
177 #define ADC_CHSELR_CHSEL16_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL16) */
178 #define ADC_CHSELR_CHSEL17_BITOFFSET_POS (17U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL17) */
179 #define ADC_CHSELR_CHSEL18_BITOFFSET_POS (18U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL18) */
180
181
182 /* ADC registers bits groups */
183 #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
184
185
186 /* ADC internal channels related definitions */
187 /* Internal voltage reference VrefInt */
188 #define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFFF7BAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
189 #define VREFINT_CAL_VREF ( 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
190 /* Temperature sensor */
191 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFFF7B8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F0, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
192 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFFF7C2U)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F0, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
193 #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
194 #define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
195 #define TEMPSENSOR_CAL_VREFANALOG ( 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
196
197
198 /**
199 * @}
200 */
201
202
203 /* Exported types ------------------------------------------------------------*/
204 #if defined(USE_FULL_LL_DRIVER)
205 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
206 * @{
207 */
208
209 /**
210 * @brief Structure definition of some features of ADC instance.
211 * @note These parameters have an impact on ADC scope: ADC instance.
212 * Refer to corresponding unitary functions into
213 * @ref ADC_LL_EF_Configuration_ADC_Instance .
214 * @note The setting of these parameters by function @ref LL_ADC_Init()
215 * is conditioned to ADC state:
216 * ADC instance must be disabled.
217 * This condition is applied to all ADC features, for efficiency
218 * and compatibility over all STM32 families. However, the different
219 * features can be set under different ADC state conditions
220 * (setting possible with ADC enabled without conversion on going,
221 * ADC enabled with conversion on going, ...)
222 * Each feature can be updated afterwards with a unitary function
223 * and potentially with ADC in a different state than disabled,
224 * refer to description of each function for setting
225 * conditioned to ADC state.
226 */
227 typedef struct
228 {
229 uint32_t Clock; /*!< Set ADC instance clock source and prescaler.
230 This parameter can be a value of @ref ADC_LL_EC_CLOCK_SOURCE
231 @note On this STM32 series, this parameter has some clock ratio constraints:
232 ADC clock synchronous (from PCLK) with prescaler 1 must be enabled only if PCLK has a 50% duty clock cycle
233 (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle).
234
235
236 This feature can be modified afterwards using unitary function @ref LL_ADC_SetClock().
237 For more details, refer to description of this function. */
238
239 uint32_t Resolution; /*!< Set ADC resolution.
240 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
241
242 This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
243
244 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
245 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
246
247 This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
248
249 uint32_t LowPowerMode; /*!< Set ADC low power mode.
250 This parameter can be a value of @ref ADC_LL_EC_LP_MODE
251
252 This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
253
254 } LL_ADC_InitTypeDef;
255
256 /**
257 * @brief Structure definition of some features of ADC group regular.
258 * @note These parameters have an impact on ADC scope: ADC group regular.
259 * Refer to corresponding unitary functions into
260 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
261 * (functions with prefix "REG").
262 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
263 * is conditioned to ADC state:
264 * ADC instance must be disabled.
265 * This condition is applied to all ADC features, for efficiency
266 * and compatibility over all STM32 families. However, the different
267 * features can be set under different ADC state conditions
268 * (setting possible with ADC enabled without conversion on going,
269 * ADC enabled with conversion on going, ...)
270 * Each feature can be updated afterwards with a unitary function
271 * and potentially with ADC in a different state than disabled,
272 * refer to description of each function for setting
273 * conditioned to ADC state.
274 */
275 typedef struct
276 {
277 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
278 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
279 @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge
280 (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
281 In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
282
283 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
284
285 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
286 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
287 @note This parameter has an effect only if group regular sequencer is enabled
288 (several ADC channels enabled in group regular sequencer).
289
290 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
291
292 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
293 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
294 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
295
296 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
297
298 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
299 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
300
301 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
302
303 uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
304 data preserved or overwritten.
305 This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
306
307 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
308
309 } LL_ADC_REG_InitTypeDef;
310
311 /**
312 * @}
313 */
314 #endif /* USE_FULL_LL_DRIVER */
315
316 /* Exported constants --------------------------------------------------------*/
317 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
318 * @{
319 */
320
321 /** @defgroup ADC_LL_EC_FLAG ADC flags
322 * @brief Flags defines which can be used with LL_ADC_ReadReg function
323 * @{
324 */
325 #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
326 #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */
327 #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */
328 #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
329 #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
330 #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD /*!< ADC flag ADC analog watchdog 1 */
331 /**
332 * @}
333 */
334
335 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
336 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
337 * @{
338 */
339 #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
340 #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */
341 #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */
342 #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
343 #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */
344 #define LL_ADC_IT_AWD1 ADC_IER_AWDIE /*!< ADC interruption ADC analog watchdog 1 */
345 /**
346 * @}
347 */
348
349 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
350 * @{
351 */
352 /* List of ADC registers intended to be used (most commonly) with */
353 /* DMA transfer. */
354 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
355 #define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
356 /**
357 * @}
358 */
359
360 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
361 * @{
362 */
363 /* Note: Other measurement paths to internal channels may be available */
364 /* (connections to other peripherals). */
365 /* If they are not listed below, they do not require any specific */
366 /* path enable. In this case, Access to measurement path is done */
367 /* only by selecting the corresponding ADC internal channel. */
368 #define LL_ADC_PATH_INTERNAL_NONE (0x00000000U)/*!< ADC measurement paths all disabled */
369 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
370 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */
371 #if defined(ADC_CCR_VBATEN)
372 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
373 #endif
374 /**
375 * @}
376 */
377
378 /** @defgroup ADC_LL_EC_CLOCK_SOURCE ADC instance - Clock source
379 * @{
380 */
381 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by 4 */
382 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock divided by 2 */
383 #define LL_ADC_CLOCK_ASYNC (0x00000000U) /*!< ADC asynchronous clock. On this STM32 series, asynchronous clock has no prescaler. */
384 /**
385 * @}
386 */
387
388 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
389 * @{
390 */
391 #define LL_ADC_RESOLUTION_12B (0x00000000U) /*!< ADC resolution 12 bits */
392 #define LL_ADC_RESOLUTION_10B ( ADC_CFGR1_RES_0) /*!< ADC resolution 10 bits */
393 #define LL_ADC_RESOLUTION_8B (ADC_CFGR1_RES_1 ) /*!< ADC resolution 8 bits */
394 #define LL_ADC_RESOLUTION_6B (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution 6 bits */
395 /**
396 * @}
397 */
398
399 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
400 * @{
401 */
402 #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
403 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR1_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
404 /**
405 * @}
406 */
407
408 /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
409 * @{
410 */
411 #define LL_ADC_LP_MODE_NONE (0x00000000U) /*!< No ADC low power mode activated */
412 #define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_WAIT) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
413 #define LL_ADC_LP_AUTOPOWEROFF (ADC_CFGR1_AUTOFF) /*!< ADC low power mode auto power-off: the ADC automatically powers-off after a ADC conversion and automatically wakes up when a new ADC conversion is triggered (with startup time between trigger and start of sampling). See description with function @ref LL_ADC_SetLowPowerMode(). Note: On STM32F0, if enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) during auto wait phase. */
414 #define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF) /*!< ADC low power modes auto wait and auto power-off combined. See description with function @ref LL_ADC_SetLowPowerMode(). */
415 /**
416 * @}
417 */
418
419 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
420 * @{
421 */
422 #define LL_ADC_GROUP_REGULAR (0x00000001U) /*!< ADC group regular (available on all STM32 devices) */
423 /**
424 * @}
425 */
426
427 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
428 * @{
429 */
430 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
431 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
432 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
433 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
434 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
435 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
436 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
437 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
438 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
439 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
440 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
441 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
442 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
443 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
444 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
445 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
446 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
447 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
448 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */
449 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */
450 #if defined(ADC_CCR_VBATEN)
451 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
452 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/2: Vbat voltage through a divider ladder of factor 1/2 to have Vbat always below Vdda. */
453 #endif
454 /**
455 * @}
456 */
457
458 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
459 * @{
460 */
461 #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000U) /*!< ADC group regular conversion trigger internal: SW start. */
462 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
463 #define LL_ADC_REG_TRIG_EXT_TIM1_CH4 (ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
464 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
465 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
466 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
467 /**
468 * @}
469 */
470
471 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
472 * @{
473 */
474 #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
475 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
476 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
477 /**
478 * @}
479 */
480
481 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
482 * @{
483 */
484 #define LL_ADC_REG_CONV_SINGLE (0x00000000U) /*!< ADC conversions are performed in single mode: one conversion per trigger */
485 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
486 /**
487 * @}
488 */
489
490 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
491 * @{
492 */
493 #define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000U) /*!< ADC conversions are not transferred by DMA */
494 #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
495 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
496 /**
497 * @}
498 */
499
500 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
501 * @{
502 */
503 #define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000U)/*!< ADC group regular behavior in case of overrun: data preserved */
504 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */
505 /**
506 * @}
507 */
508
509 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION ADC group regular - Sequencer scan direction
510 * @{
511 */
512 #define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000U)/*!< ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other STM32 families, this setting is not available and the default scan direction is forward. */
513 #define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR) /*!< ADC group regular sequencer scan direction backward: from highest channel number to lowest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer) */
514 /**
515 * @}
516 */
517
518 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
519 * @{
520 */
521 #define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000U) /*!< ADC group regular sequencer discontinuous mode disable */
522 #define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
523 /**
524 * @}
525 */
526
527 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
528 * @{
529 */
530 #define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000U) /*!< Sampling time 1.5 ADC clock cycle */
531 #define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP_0) /*!< Sampling time 7.5 ADC clock cycles */
532 #define LL_ADC_SAMPLINGTIME_13CYCLES_5 (ADC_SMPR_SMP_1) /*!< Sampling time 13.5 ADC clock cycles */
533 #define LL_ADC_SAMPLINGTIME_28CYCLES_5 (ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0) /*!< Sampling time 28.5 ADC clock cycles */
534 #define LL_ADC_SAMPLINGTIME_41CYCLES_5 (ADC_SMPR_SMP_2) /*!< Sampling time 41.5 ADC clock cycles */
535 #define LL_ADC_SAMPLINGTIME_55CYCLES_5 (ADC_SMPR_SMP_2 | ADC_SMPR_SMP_0) /*!< Sampling time 55.5 ADC clock cycles */
536 #define LL_ADC_SAMPLINGTIME_71CYCLES_5 (ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1) /*!< Sampling time 71.5 ADC clock cycles */
537 #define LL_ADC_SAMPLINGTIME_239CYCLES_5 (ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0) /*!< Sampling time 239.5 ADC clock cycles */
538 /**
539 * @}
540 */
541
542 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
543 * @{
544 */
545 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
546 /**
547 * @}
548 */
549
550 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
551 * @{
552 */
553 #define LL_ADC_AWD_DISABLE (0x00000000U) /*!< ADC analog watchdog monitoring disabled */
554 #define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CFGR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
555 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
556 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
557 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
558 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
559 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
560 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
561 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
562 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
563 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
564 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
565 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
566 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
567 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
568 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
569 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
570 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
571 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
572 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
573 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
574 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
575 #if defined(ADC_CCR_VBATEN)
576 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
577 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
578 #endif
579 /**
580 * @}
581 */
582
583 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
584 * @{
585 */
586 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR_HT ) /*!< ADC analog watchdog threshold high */
587 #define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR_LT) /*!< ADC analog watchdog threshold low */
588 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR_HT | ADC_TR_LT) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */
589 /**
590 * @}
591 */
592
593
594 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
595 * @note Only ADC IP HW delays are defined in ADC LL driver driver,
596 * not timeout values.
597 * For details on delays values, refer to descriptions in source code
598 * above each literal definition.
599 * @{
600 */
601
602 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
603 /* not timeout values. */
604 /* Timeout values for ADC operations are dependent to device clock */
605 /* configuration (system clock versus ADC clock), */
606 /* and therefore must be defined in user application. */
607 /* Indications for estimation of ADC timeout delays, for this */
608 /* STM32 series: */
609 /* - ADC calibration time: maximum delay is 83/fADC. */
610 /* (refer to device datasheet, parameter "tCAL") */
611 /* - ADC enable time: maximum delay is 1 conversion cycle. */
612 /* (refer to device datasheet, parameter "tSTAB") */
613 /* - ADC disable time: maximum delay should be a few ADC clock cycles */
614 /* - ADC stop conversion time: maximum delay should be a few ADC clock */
615 /* cycles */
616 /* - ADC conversion time: duration depending on ADC clock and ADC */
617 /* configuration. */
618 /* (refer to device reference manual, section "Timing") */
619
620
621 /* Delay for internal voltage reference stabilization time. */
622 /* Delay set to maximum value (refer to device datasheet, */
623 /* parameter "tSTART"). */
624 /* Unit: us */
625 #define LL_ADC_DELAY_VREFINT_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */
626
627 /* Delay for temperature sensor stabilization time. */
628 /* Literal set to maximum value (refer to device datasheet, */
629 /* parameter "tSTART"). */
630 /* Unit: us */
631 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 10U) /*!< Delay for temperature sensor stabilization time */
632
633 /* Delay required between ADC end of calibration and ADC enable. */
634 /* Note: On this STM32 series, a minimum number of ADC clock cycles */
635 /* are required between ADC end of calibration and ADC enable. */
636 /* Wait time can be computed in user application by waiting for the */
637 /* equivalent number of CPU cycles, by taking into account */
638 /* ratio of CPU clock versus ADC clock prescalers. */
639 /* Unit: ADC clock cycles. */
640 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 2U) /*!< Delay required between ADC end of calibration and ADC enable */
641
642 /**
643 * @}
644 */
645
646 /**
647 * @}
648 */
649
650
651 /* Exported macro ------------------------------------------------------------*/
652 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
653 * @{
654 */
655
656 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
657 * @{
658 */
659
660 /**
661 * @brief Write a value in ADC register
662 * @param __INSTANCE__ ADC Instance
663 * @param __REG__ Register to be written
664 * @param __VALUE__ Value to be written in the register
665 * @retval None
666 */
667 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
668
669 /**
670 * @brief Read a value in ADC register
671 * @param __INSTANCE__ ADC Instance
672 * @param __REG__ Register to be read
673 * @retval Register value
674 */
675 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
676 /**
677 * @}
678 */
679
680 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
681 * @{
682 */
683
684 /**
685 * @brief Helper macro to get ADC channel number in decimal format
686 * from literals LL_ADC_CHANNEL_x.
687 * @note Example:
688 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
689 * will return decimal number "4".
690 * @note The input can be a value from functions where a channel
691 * number is returned, either defined with number
692 * or with bitfield (only one bit must be set).
693 * @param __CHANNEL__ This parameter can be one of the following values:
694 * @arg @ref LL_ADC_CHANNEL_0
695 * @arg @ref LL_ADC_CHANNEL_1
696 * @arg @ref LL_ADC_CHANNEL_2
697 * @arg @ref LL_ADC_CHANNEL_3
698 * @arg @ref LL_ADC_CHANNEL_4
699 * @arg @ref LL_ADC_CHANNEL_5
700 * @arg @ref LL_ADC_CHANNEL_6
701 * @arg @ref LL_ADC_CHANNEL_7
702 * @arg @ref LL_ADC_CHANNEL_8
703 * @arg @ref LL_ADC_CHANNEL_9
704 * @arg @ref LL_ADC_CHANNEL_10
705 * @arg @ref LL_ADC_CHANNEL_11
706 * @arg @ref LL_ADC_CHANNEL_12
707 * @arg @ref LL_ADC_CHANNEL_13
708 * @arg @ref LL_ADC_CHANNEL_14
709 * @arg @ref LL_ADC_CHANNEL_15
710 * @arg @ref LL_ADC_CHANNEL_16
711 * @arg @ref LL_ADC_CHANNEL_17
712 * @arg @ref LL_ADC_CHANNEL_18 (1)
713 * @arg @ref LL_ADC_CHANNEL_VREFINT
714 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
715 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
716 *
717 * (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
718 * @retval Value between Min_Data=0 and Max_Data=18
719 */
720 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
721 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0U) \
722 ? ( \
723 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
724 ) \
725 : \
726 ( \
727 (((__CHANNEL__) & ADC_CHSELR_CHSEL0) == ADC_CHSELR_CHSEL0) ? (0U) : \
728 ( \
729 (((__CHANNEL__) & ADC_CHSELR_CHSEL1) == ADC_CHSELR_CHSEL1) ? (1U) : \
730 ( \
731 (((__CHANNEL__) & ADC_CHSELR_CHSEL2) == ADC_CHSELR_CHSEL2) ? (2U) : \
732 ( \
733 (((__CHANNEL__) & ADC_CHSELR_CHSEL3) == ADC_CHSELR_CHSEL3) ? (3U) : \
734 ( \
735 (((__CHANNEL__) & ADC_CHSELR_CHSEL4) == ADC_CHSELR_CHSEL4) ? (4U) : \
736 ( \
737 (((__CHANNEL__) & ADC_CHSELR_CHSEL5) == ADC_CHSELR_CHSEL5) ? (5U) : \
738 ( \
739 (((__CHANNEL__) & ADC_CHSELR_CHSEL6) == ADC_CHSELR_CHSEL6) ? (6U) : \
740 ( \
741 (((__CHANNEL__) & ADC_CHSELR_CHSEL7) == ADC_CHSELR_CHSEL7) ? (7U) : \
742 ( \
743 (((__CHANNEL__) & ADC_CHSELR_CHSEL8) == ADC_CHSELR_CHSEL8) ? (8U) : \
744 ( \
745 (((__CHANNEL__) & ADC_CHSELR_CHSEL9) == ADC_CHSELR_CHSEL9) ? (9U) : \
746 ( \
747 (((__CHANNEL__) & ADC_CHSELR_CHSEL10) == ADC_CHSELR_CHSEL10) ? (10U) : \
748 ( \
749 (((__CHANNEL__) & ADC_CHSELR_CHSEL11) == ADC_CHSELR_CHSEL11) ? (11U) : \
750 ( \
751 (((__CHANNEL__) & ADC_CHSELR_CHSEL12) == ADC_CHSELR_CHSEL12) ? (12U) : \
752 ( \
753 (((__CHANNEL__) & ADC_CHSELR_CHSEL13) == ADC_CHSELR_CHSEL13) ? (13U) : \
754 ( \
755 (((__CHANNEL__) & ADC_CHSELR_CHSEL14) == ADC_CHSELR_CHSEL14) ? (14U) : \
756 ( \
757 (((__CHANNEL__) & ADC_CHSELR_CHSEL15) == ADC_CHSELR_CHSEL15) ? (15U) : \
758 ( \
759 (((__CHANNEL__) & ADC_CHSELR_CHSEL16) == ADC_CHSELR_CHSEL16) ? (16U) : \
760 ( \
761 (((__CHANNEL__) & ADC_CHSELR_CHSEL17) == ADC_CHSELR_CHSEL17) ? (17U) : \
762 ( \
763 (((__CHANNEL__) & ADC_CHSELR_CHSEL18) == ADC_CHSELR_CHSEL18) ? (18U) : \
764 (0U) \
765 ) \
766 ) \
767 ) \
768 ) \
769 ) \
770 ) \
771 ) \
772 ) \
773 ) \
774 ) \
775 ) \
776 ) \
777 ) \
778 ) \
779 ) \
780 ) \
781 ) \
782 ) \
783 ) \
784 )
785
786 /**
787 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
788 * from number in decimal format.
789 * @note Example:
790 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
791 * will return a data equivalent to "LL_ADC_CHANNEL_4".
792 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
793 * @retval Returned value can be one of the following values:
794 * @arg @ref LL_ADC_CHANNEL_0
795 * @arg @ref LL_ADC_CHANNEL_1
796 * @arg @ref LL_ADC_CHANNEL_2
797 * @arg @ref LL_ADC_CHANNEL_3
798 * @arg @ref LL_ADC_CHANNEL_4
799 * @arg @ref LL_ADC_CHANNEL_5
800 * @arg @ref LL_ADC_CHANNEL_6
801 * @arg @ref LL_ADC_CHANNEL_7
802 * @arg @ref LL_ADC_CHANNEL_8
803 * @arg @ref LL_ADC_CHANNEL_9
804 * @arg @ref LL_ADC_CHANNEL_10
805 * @arg @ref LL_ADC_CHANNEL_11
806 * @arg @ref LL_ADC_CHANNEL_12
807 * @arg @ref LL_ADC_CHANNEL_13
808 * @arg @ref LL_ADC_CHANNEL_14
809 * @arg @ref LL_ADC_CHANNEL_15
810 * @arg @ref LL_ADC_CHANNEL_16
811 * @arg @ref LL_ADC_CHANNEL_17
812 * @arg @ref LL_ADC_CHANNEL_18 (1)
813 * @arg @ref LL_ADC_CHANNEL_VREFINT (2)
814 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2)
815 * @arg @ref LL_ADC_CHANNEL_VBAT (1)(2)
816 *
817 * (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.\n
818 * (2) For ADC channel read back from ADC register,
819 * comparison with internal channel parameter to be done
820 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
821 */
822 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
823 ( \
824 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
825 (ADC_CHSELR_CHSEL0 << (__DECIMAL_NB__)) \
826 )
827
828 /**
829 * @brief Helper macro to determine whether the selected channel
830 * corresponds to literal definitions of driver.
831 * @note The different literal definitions of ADC channels are:
832 * - ADC internal channel:
833 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
834 * - ADC external channel (channel connected to a GPIO pin):
835 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
836 * @note The channel parameter must be a value defined from literal
837 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
838 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
839 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
840 * must not be a value from functions where a channel number is
841 * returned from ADC registers,
842 * because internal and external channels share the same channel
843 * number in ADC registers. The differentiation is made only with
844 * parameters definitions of driver.
845 * @param __CHANNEL__ This parameter can be one of the following values:
846 * @arg @ref LL_ADC_CHANNEL_0
847 * @arg @ref LL_ADC_CHANNEL_1
848 * @arg @ref LL_ADC_CHANNEL_2
849 * @arg @ref LL_ADC_CHANNEL_3
850 * @arg @ref LL_ADC_CHANNEL_4
851 * @arg @ref LL_ADC_CHANNEL_5
852 * @arg @ref LL_ADC_CHANNEL_6
853 * @arg @ref LL_ADC_CHANNEL_7
854 * @arg @ref LL_ADC_CHANNEL_8
855 * @arg @ref LL_ADC_CHANNEL_9
856 * @arg @ref LL_ADC_CHANNEL_10
857 * @arg @ref LL_ADC_CHANNEL_11
858 * @arg @ref LL_ADC_CHANNEL_12
859 * @arg @ref LL_ADC_CHANNEL_13
860 * @arg @ref LL_ADC_CHANNEL_14
861 * @arg @ref LL_ADC_CHANNEL_15
862 * @arg @ref LL_ADC_CHANNEL_16
863 * @arg @ref LL_ADC_CHANNEL_17
864 * @arg @ref LL_ADC_CHANNEL_18 (1)
865 * @arg @ref LL_ADC_CHANNEL_VREFINT
866 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
867 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
868 *
869 * (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
870 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
871 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
872 */
873 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
874 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
875
876 /**
877 * @brief Helper macro to convert a channel defined from parameter
878 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
879 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
880 * to its equivalent parameter definition of a ADC external channel
881 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
882 * @note The channel parameter can be, additionally to a value
883 * defined from parameter definition of a ADC internal channel
884 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
885 * a value defined from parameter definition of
886 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
887 * or a value from functions where a channel number is returned
888 * from ADC registers.
889 * @param __CHANNEL__ This parameter can be one of the following values:
890 * @arg @ref LL_ADC_CHANNEL_0
891 * @arg @ref LL_ADC_CHANNEL_1
892 * @arg @ref LL_ADC_CHANNEL_2
893 * @arg @ref LL_ADC_CHANNEL_3
894 * @arg @ref LL_ADC_CHANNEL_4
895 * @arg @ref LL_ADC_CHANNEL_5
896 * @arg @ref LL_ADC_CHANNEL_6
897 * @arg @ref LL_ADC_CHANNEL_7
898 * @arg @ref LL_ADC_CHANNEL_8
899 * @arg @ref LL_ADC_CHANNEL_9
900 * @arg @ref LL_ADC_CHANNEL_10
901 * @arg @ref LL_ADC_CHANNEL_11
902 * @arg @ref LL_ADC_CHANNEL_12
903 * @arg @ref LL_ADC_CHANNEL_13
904 * @arg @ref LL_ADC_CHANNEL_14
905 * @arg @ref LL_ADC_CHANNEL_15
906 * @arg @ref LL_ADC_CHANNEL_16
907 * @arg @ref LL_ADC_CHANNEL_17
908 * @arg @ref LL_ADC_CHANNEL_18 (1)
909 * @arg @ref LL_ADC_CHANNEL_VREFINT
910 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
911 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
912 *
913 * (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
914 * @retval Returned value can be one of the following values:
915 * @arg @ref LL_ADC_CHANNEL_0
916 * @arg @ref LL_ADC_CHANNEL_1
917 * @arg @ref LL_ADC_CHANNEL_2
918 * @arg @ref LL_ADC_CHANNEL_3
919 * @arg @ref LL_ADC_CHANNEL_4
920 * @arg @ref LL_ADC_CHANNEL_5
921 * @arg @ref LL_ADC_CHANNEL_6
922 * @arg @ref LL_ADC_CHANNEL_7
923 * @arg @ref LL_ADC_CHANNEL_8
924 * @arg @ref LL_ADC_CHANNEL_9
925 * @arg @ref LL_ADC_CHANNEL_10
926 * @arg @ref LL_ADC_CHANNEL_11
927 * @arg @ref LL_ADC_CHANNEL_12
928 * @arg @ref LL_ADC_CHANNEL_13
929 * @arg @ref LL_ADC_CHANNEL_14
930 * @arg @ref LL_ADC_CHANNEL_15
931 * @arg @ref LL_ADC_CHANNEL_16
932 * @arg @ref LL_ADC_CHANNEL_17
933 * @arg @ref LL_ADC_CHANNEL_18
934 */
935 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
936 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
937
938 /**
939 * @brief Helper macro to determine whether the internal channel
940 * selected is available on the ADC instance selected.
941 * @note The channel parameter must be a value defined from parameter
942 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
943 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
944 * must not be a value defined from parameter definition of
945 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
946 * or a value from functions where a channel number is
947 * returned from ADC registers,
948 * because internal and external channels share the same channel
949 * number in ADC registers. The differentiation is made only with
950 * parameters definitions of driver.
951 * @param __ADC_INSTANCE__ ADC instance
952 * @param __CHANNEL__ This parameter can be one of the following values:
953 * @arg @ref LL_ADC_CHANNEL_VREFINT
954 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
955 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
956 *
957 * (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
958 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
959 * Value "1" if the internal channel selected is available on the ADC instance selected.
960 */
961 #if defined(ADC_CCR_VBATEN)
962 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
963 ( \
964 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
965 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
966 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
967 )
968 #else
969 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
970 ( \
971 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
972 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \
973 )
974 #endif
975
976 /**
977 * @brief Helper macro to define ADC analog watchdog parameter:
978 * define a single channel to monitor with analog watchdog
979 * from sequencer channel and groups definition.
980 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
981 * Example:
982 * LL_ADC_SetAnalogWDMonitChannels(
983 * ADC1, LL_ADC_AWD1,
984 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
985 * @param __CHANNEL__ This parameter can be one of the following values:
986 * @arg @ref LL_ADC_CHANNEL_0
987 * @arg @ref LL_ADC_CHANNEL_1
988 * @arg @ref LL_ADC_CHANNEL_2
989 * @arg @ref LL_ADC_CHANNEL_3
990 * @arg @ref LL_ADC_CHANNEL_4
991 * @arg @ref LL_ADC_CHANNEL_5
992 * @arg @ref LL_ADC_CHANNEL_6
993 * @arg @ref LL_ADC_CHANNEL_7
994 * @arg @ref LL_ADC_CHANNEL_8
995 * @arg @ref LL_ADC_CHANNEL_9
996 * @arg @ref LL_ADC_CHANNEL_10
997 * @arg @ref LL_ADC_CHANNEL_11
998 * @arg @ref LL_ADC_CHANNEL_12
999 * @arg @ref LL_ADC_CHANNEL_13
1000 * @arg @ref LL_ADC_CHANNEL_14
1001 * @arg @ref LL_ADC_CHANNEL_15
1002 * @arg @ref LL_ADC_CHANNEL_16
1003 * @arg @ref LL_ADC_CHANNEL_17
1004 * @arg @ref LL_ADC_CHANNEL_18 (1)
1005 * @arg @ref LL_ADC_CHANNEL_VREFINT (2)
1006 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2)
1007 * @arg @ref LL_ADC_CHANNEL_VBAT (1)(2)
1008 *
1009 * (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.\n
1010 * (2) For ADC channel read back from ADC register,
1011 * comparison with internal channel parameter to be done
1012 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1013 * @param __GROUP__ This parameter can be one of the following values:
1014 * @arg @ref LL_ADC_GROUP_REGULAR
1015 * @retval Returned value can be one of the following values:
1016 * @arg @ref LL_ADC_AWD_DISABLE
1017 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
1018 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
1019 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
1020 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
1021 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
1022 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
1023 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
1024 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
1025 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
1026 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
1027 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
1028 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
1029 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
1030 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
1031 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
1032 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
1033 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
1034 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
1035 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
1036 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (1)
1037 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG
1038 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
1039 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
1040 *
1041 * (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
1042 */
1043 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
1044 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)
1045
1046 /**
1047 * @brief Helper macro to set the value of ADC analog watchdog threshold high
1048 * or low in function of ADC resolution, when ADC resolution is
1049 * different of 12 bits.
1050 * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
1051 * or @ref LL_ADC_SetAnalogWDThresholds().
1052 * Example, with a ADC resolution of 8 bits, to set the value of
1053 * analog watchdog threshold high (on 8 bits):
1054 * LL_ADC_SetAnalogWDThresholds
1055 * (< ADCx param >,
1056 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
1057 * );
1058 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1059 * @arg @ref LL_ADC_RESOLUTION_12B
1060 * @arg @ref LL_ADC_RESOLUTION_10B
1061 * @arg @ref LL_ADC_RESOLUTION_8B
1062 * @arg @ref LL_ADC_RESOLUTION_6B
1063 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
1064 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1065 */
1066 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
1067 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
1068
1069 /**
1070 * @brief Helper macro to get the value of ADC analog watchdog threshold high
1071 * or low in function of ADC resolution, when ADC resolution is
1072 * different of 12 bits.
1073 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1074 * Example, with a ADC resolution of 8 bits, to get the value of
1075 * analog watchdog threshold high (on 8 bits):
1076 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
1077 * (LL_ADC_RESOLUTION_8B,
1078 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
1079 * );
1080 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1081 * @arg @ref LL_ADC_RESOLUTION_12B
1082 * @arg @ref LL_ADC_RESOLUTION_10B
1083 * @arg @ref LL_ADC_RESOLUTION_8B
1084 * @arg @ref LL_ADC_RESOLUTION_6B
1085 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
1086 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1087 */
1088 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
1089 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
1090
1091 /**
1092 * @brief Helper macro to get the ADC analog watchdog threshold high
1093 * or low from raw value containing both thresholds concatenated.
1094 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1095 * Example, to get analog watchdog threshold high from the register raw value:
1096 * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
1097 * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
1098 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
1099 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
1100 * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1101 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1102 */
1103 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
1104 (((__AWD_THRESHOLD_TYPE__) == LL_ADC_AWD_THRESHOLD_LOW) \
1105 ? ( \
1106 (__AWD_THRESHOLDS__) & LL_ADC_AWD_THRESHOLD_LOW \
1107 ) \
1108 : \
1109 ( \
1110 ((__AWD_THRESHOLDS__) >> ADC_TR_HT_BITOFFSET_POS) & LL_ADC_AWD_THRESHOLD_LOW \
1111 ) \
1112 )
1113
1114 /**
1115 * @brief Helper macro to select the ADC common instance
1116 * to which is belonging the selected ADC instance.
1117 * @note ADC common register instance can be used for:
1118 * - Set parameters common to several ADC instances
1119 * - Multimode (for devices with several ADC instances)
1120 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1121 * @param __ADCx__ ADC instance
1122 * @retval ADC common register instance
1123 */
1124 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1125 (ADC1_COMMON)
1126
1127 /**
1128 * @brief Helper macro to check if all ADC instances sharing the same
1129 * ADC common instance are disabled.
1130 * @note This check is required by functions with setting conditioned to
1131 * ADC state:
1132 * All ADC instances of the ADC common group must be disabled.
1133 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1134 * @note On devices with only 1 ADC common instance, parameter of this macro
1135 * is useless and can be ignored (parameter kept for compatibility
1136 * with devices featuring several ADC common instances).
1137 * @param __ADCXY_COMMON__ ADC common instance
1138 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1139 * @retval Value "0" if all ADC instances sharing the same ADC common instance
1140 * are disabled.
1141 * Value "1" if at least one ADC instance sharing the same ADC common instance
1142 * is enabled.
1143 */
1144 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1145 LL_ADC_IsEnabled(ADC1)
1146
1147 /**
1148 * @brief Helper macro to define the ADC conversion data full-scale digital
1149 * value corresponding to the selected ADC resolution.
1150 * @note ADC conversion data full-scale corresponds to voltage range
1151 * determined by analog voltage references Vref+ and Vref-
1152 * (refer to reference manual).
1153 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1154 * @arg @ref LL_ADC_RESOLUTION_12B
1155 * @arg @ref LL_ADC_RESOLUTION_10B
1156 * @arg @ref LL_ADC_RESOLUTION_8B
1157 * @arg @ref LL_ADC_RESOLUTION_6B
1158 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1159 */
1160 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1161 (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U)))
1162
1163 /**
1164 * @brief Helper macro to convert the ADC conversion data from
1165 * a resolution to another resolution.
1166 * @param __DATA__ ADC conversion data to be converted
1167 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
1168 * This parameter can be one of the following values:
1169 * @arg @ref LL_ADC_RESOLUTION_12B
1170 * @arg @ref LL_ADC_RESOLUTION_10B
1171 * @arg @ref LL_ADC_RESOLUTION_8B
1172 * @arg @ref LL_ADC_RESOLUTION_6B
1173 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
1174 * This parameter can be one of the following values:
1175 * @arg @ref LL_ADC_RESOLUTION_12B
1176 * @arg @ref LL_ADC_RESOLUTION_10B
1177 * @arg @ref LL_ADC_RESOLUTION_8B
1178 * @arg @ref LL_ADC_RESOLUTION_6B
1179 * @retval ADC conversion data to the requested resolution
1180 */
1181 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \
1182 (((__DATA__) \
1183 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U))) \
1184 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U)) \
1185 )
1186
1187 /**
1188 * @brief Helper macro to calculate the voltage (unit: mVolt)
1189 * corresponding to a ADC conversion data (unit: digital value).
1190 * @note Analog reference voltage (Vref+) must be either known from
1191 * user board environment or can be calculated using ADC measurement
1192 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1193 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
1194 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
1195 * (unit: digital value).
1196 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1197 * @arg @ref LL_ADC_RESOLUTION_12B
1198 * @arg @ref LL_ADC_RESOLUTION_10B
1199 * @arg @ref LL_ADC_RESOLUTION_8B
1200 * @arg @ref LL_ADC_RESOLUTION_6B
1201 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1202 */
1203 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
1204 __ADC_DATA__,\
1205 __ADC_RESOLUTION__) \
1206 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
1207 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1208 )
1209
1210 /**
1211 * @brief Helper macro to calculate analog reference voltage (Vref+)
1212 * (unit: mVolt) from ADC conversion data of internal voltage
1213 * reference VrefInt.
1214 * @note Computation is using VrefInt calibration value
1215 * stored in system memory for each device during production.
1216 * @note This voltage depends on user board environment: voltage level
1217 * connected to pin Vref+.
1218 * On devices with small package, the pin Vref+ is not present
1219 * and internally bonded to pin Vdda.
1220 * @note On this STM32 series, calibration data of internal voltage reference
1221 * VrefInt corresponds to a resolution of 12 bits,
1222 * this is the recommended ADC resolution to convert voltage of
1223 * internal voltage reference VrefInt.
1224 * Otherwise, this macro performs the processing to scale
1225 * ADC conversion data to 12 bits.
1226 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
1227 * of internal voltage reference VrefInt (unit: digital value).
1228 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1229 * @arg @ref LL_ADC_RESOLUTION_12B
1230 * @arg @ref LL_ADC_RESOLUTION_10B
1231 * @arg @ref LL_ADC_RESOLUTION_8B
1232 * @arg @ref LL_ADC_RESOLUTION_6B
1233 * @retval Analog reference voltage (unit: mV)
1234 */
1235 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
1236 __ADC_RESOLUTION__) \
1237 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
1238 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
1239 (__ADC_RESOLUTION__), \
1240 LL_ADC_RESOLUTION_12B) \
1241 )
1242
1243 /**
1244 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1245 * from ADC conversion data of internal temperature sensor.
1246 * @note Computation is using temperature sensor calibration values
1247 * stored in system memory for each device during production.
1248 * @note Calculation formula:
1249 * Temperature = ((TS_ADC_DATA - TS_CAL1)
1250 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
1251 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
1252 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1253 * Avg_Slope = (TS_CAL2 - TS_CAL1)
1254 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
1255 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
1256 * TEMP_DEGC_CAL1 (calibrated in factory)
1257 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
1258 * TEMP_DEGC_CAL2 (calibrated in factory)
1259 * Caution: Calculation relevancy under reserve that calibration
1260 * parameters are correct (address and data).
1261 * To calculate temperature using temperature sensor
1262 * datasheet typical values (generic values less, therefore
1263 * less accurate than calibrated values),
1264 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
1265 * @note As calculation input, the analog reference voltage (Vref+) must be
1266 * defined as it impacts the ADC LSB equivalent voltage.
1267 * @note Analog reference voltage (Vref+) must be either known from
1268 * user board environment or can be calculated using ADC measurement
1269 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1270 * @note On this STM32 series, calibration data of temperature sensor
1271 * corresponds to a resolution of 12 bits,
1272 * this is the recommended ADC resolution to convert voltage of
1273 * temperature sensor.
1274 * Otherwise, this macro performs the processing to scale
1275 * ADC conversion data to 12 bits.
1276 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
1277 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
1278 * temperature sensor (unit: digital value).
1279 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
1280 * sensor voltage has been measured.
1281 * This parameter can be one of the following values:
1282 * @arg @ref LL_ADC_RESOLUTION_12B
1283 * @arg @ref LL_ADC_RESOLUTION_10B
1284 * @arg @ref LL_ADC_RESOLUTION_8B
1285 * @arg @ref LL_ADC_RESOLUTION_6B
1286 * @retval Temperature (unit: degree Celsius)
1287 */
1288 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
1289 __TEMPSENSOR_ADC_DATA__,\
1290 __ADC_RESOLUTION__) \
1291 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
1292 (__ADC_RESOLUTION__), \
1293 LL_ADC_RESOLUTION_12B) \
1294 * (__VREFANALOG_VOLTAGE__)) \
1295 / TEMPSENSOR_CAL_VREFANALOG) \
1296 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
1297 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
1298 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
1299 ) + TEMPSENSOR_CAL1_TEMP \
1300 )
1301
1302 /**
1303 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1304 * from ADC conversion data of internal temperature sensor.
1305 * @note Computation is using temperature sensor typical values
1306 * (refer to device datasheet).
1307 * @note Calculation formula:
1308 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
1309 * / Avg_Slope + CALx_TEMP
1310 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1311 * (unit: digital value)
1312 * Avg_Slope = temperature sensor slope
1313 * (unit: uV/Degree Celsius)
1314 * TS_TYP_CALx_VOLT = temperature sensor digital value at
1315 * temperature CALx_TEMP (unit: mV)
1316 * Caution: Calculation relevancy under reserve the temperature sensor
1317 * of the current device has characteristics in line with
1318 * datasheet typical values.
1319 * If temperature sensor calibration values are available on
1320 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
1321 * temperature calculation will be more accurate using
1322 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
1323 * @note As calculation input, the analog reference voltage (Vref+) must be
1324 * defined as it impacts the ADC LSB equivalent voltage.
1325 * @note Analog reference voltage (Vref+) must be either known from
1326 * user board environment or can be calculated using ADC measurement
1327 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1328 * @note ADC measurement data must correspond to a resolution of 12bits
1329 * (full scale digital value 4095). If not the case, the data must be
1330 * preliminarily rescaled to an equivalent resolution of 12 bits.
1331 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
1332 * On STM32F0, refer to device datasheet parameter "Avg_Slope".
1333 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
1334 * On STM32F0, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
1335 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
1336 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
1337 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
1338 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
1339 * This parameter can be one of the following values:
1340 * @arg @ref LL_ADC_RESOLUTION_12B
1341 * @arg @ref LL_ADC_RESOLUTION_10B
1342 * @arg @ref LL_ADC_RESOLUTION_8B
1343 * @arg @ref LL_ADC_RESOLUTION_6B
1344 * @retval Temperature (unit: degree Celsius)
1345 */
1346 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
1347 __TEMPSENSOR_TYP_CALX_V__,\
1348 __TEMPSENSOR_CALX_TEMP__,\
1349 __VREFANALOG_VOLTAGE__,\
1350 __TEMPSENSOR_ADC_DATA__,\
1351 __ADC_RESOLUTION__) \
1352 ((( ( \
1353 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
1354 * 1000) \
1355 - \
1356 (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
1357 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
1358 * 1000) \
1359 ) \
1360 ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
1361 ) + (__TEMPSENSOR_CALX_TEMP__) \
1362 )
1363
1364 /**
1365 * @}
1366 */
1367
1368 /**
1369 * @}
1370 */
1371
1372
1373 /* Exported functions --------------------------------------------------------*/
1374 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
1375 * @{
1376 */
1377
1378 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
1379 * @{
1380 */
1381 /* Note: LL ADC functions to set DMA transfer are located into sections of */
1382 /* configuration of ADC instance, groups and multimode (if available): */
1383 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
1384
1385 /**
1386 * @brief Function to help to configure DMA transfer from ADC: retrieve the
1387 * ADC register address from ADC instance and a list of ADC registers
1388 * intended to be used (most commonly) with DMA transfer.
1389 * @note These ADC registers are data registers:
1390 * when ADC conversion data is available in ADC data registers,
1391 * ADC generates a DMA transfer request.
1392 * @note This macro is intended to be used with LL DMA driver, refer to
1393 * function "LL_DMA_ConfigAddresses()".
1394 * Example:
1395 * LL_DMA_ConfigAddresses(DMA1,
1396 * LL_DMA_CHANNEL_1,
1397 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
1398 * (uint32_t)&< array or variable >,
1399 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
1400 * @note For devices with several ADC: in multimode, some devices
1401 * use a different data register outside of ADC instance scope
1402 * (common data register). This macro manages this register difference,
1403 * only ADC instance has to be set as parameter.
1404 * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr
1405 * @param ADCx ADC instance
1406 * @param Register This parameter can be one of the following values:
1407 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
1408 * @retval ADC register address
1409 */
LL_ADC_DMA_GetRegAddr(ADC_TypeDef * ADCx,uint32_t Register)1410 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
1411 {
1412 /* Prevent unused argument compilation warning */
1413 (void)Register;
1414
1415 /* Retrieve address of register DR */
1416 return (uint32_t)&(ADCx->DR);
1417 }
1418
1419 /**
1420 * @}
1421 */
1422
1423 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
1424 * @{
1425 */
1426
1427 /**
1428 * @brief Set parameter common to several ADC: measurement path to internal
1429 * channels (VrefInt, temperature sensor, ...).
1430 * @note One or several values can be selected.
1431 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1432 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1433 * @note Stabilization time of measurement path to internal channel:
1434 * After enabling internal paths, before starting ADC conversion,
1435 * a delay is required for internal voltage reference and
1436 * temperature sensor stabilization time.
1437 * Refer to device datasheet.
1438 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
1439 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
1440 * @note ADC internal channel sampling time constraint:
1441 * For ADC conversion of internal channels,
1442 * a sampling time minimum value is required.
1443 * Refer to device datasheet.
1444 * @note On this STM32 series, setting of this feature is conditioned to
1445 * ADC state:
1446 * All ADC instances of the ADC common group must be disabled.
1447 * This check can be done with function @ref LL_ADC_IsEnabled() for each
1448 * ADC instance or by using helper macro helper macro
1449 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
1450 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
1451 * CCR TSEN LL_ADC_SetCommonPathInternalCh\n
1452 * CCR VBATEN LL_ADC_SetCommonPathInternalCh
1453 * @param ADCxy_COMMON ADC common instance
1454 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1455 * @param PathInternal This parameter can be a combination of the following values:
1456 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1457 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1458 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1459 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT (1)
1460 *
1461 * (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
1462 * @retval None
1463 */
LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)1464 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
1465 {
1466 #if defined(ADC_CCR_VBATEN)
1467 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
1468 #else
1469 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN, PathInternal);
1470 #endif
1471 }
1472
1473 /**
1474 * @brief Get parameter common to several ADC: measurement path to internal
1475 * channels (VrefInt, temperature sensor, ...).
1476 * @note One or several values can be selected.
1477 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1478 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1479 * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
1480 * CCR TSEN LL_ADC_GetCommonPathInternalCh\n
1481 * CCR VBATEN LL_ADC_GetCommonPathInternalCh
1482 * @param ADCxy_COMMON ADC common instance
1483 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1484 * @retval Returned value can be a combination of the following values:
1485 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1486 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1487 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1488 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT (1)
1489 *
1490 * (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
1491 */
LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON)1492 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
1493 {
1494 #if defined(ADC_CCR_VBATEN)
1495 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
1496 #else
1497 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN));
1498 #endif
1499 }
1500
1501 /**
1502 * @}
1503 */
1504
1505 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
1506 * @{
1507 */
1508
1509 /**
1510 * @brief Set ADC instance clock source and prescaler.
1511 * @note On this STM32 series, setting of this feature is conditioned to
1512 * ADC state:
1513 * ADC must be disabled.
1514 * @rmtoll CFGR2 CKMODE LL_ADC_SetClock
1515 * @param ADCx ADC instance
1516 * @param ClockSource This parameter can be one of the following values:
1517 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
1518 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
1519 * @arg @ref LL_ADC_CLOCK_ASYNC (1)
1520 *
1521 * (1) On this STM32 series, synchronous clock has no prescaler.
1522 * @retval None
1523 */
LL_ADC_SetClock(ADC_TypeDef * ADCx,uint32_t ClockSource)1524 __STATIC_INLINE void LL_ADC_SetClock(ADC_TypeDef *ADCx, uint32_t ClockSource)
1525 {
1526 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource);
1527 }
1528
1529 /**
1530 * @brief Get ADC instance clock source and prescaler.
1531 * @rmtoll CFGR2 CKMODE LL_ADC_GetClock
1532 * @param ADCx ADC instance
1533 * @retval Returned value can be one of the following values:
1534 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
1535 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
1536 * @arg @ref LL_ADC_CLOCK_ASYNC (1)
1537 *
1538 * (1) On this STM32 series, synchronous clock has no prescaler.
1539 */
LL_ADC_GetClock(ADC_TypeDef * ADCx)1540 __STATIC_INLINE uint32_t LL_ADC_GetClock(ADC_TypeDef *ADCx)
1541 {
1542 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE));
1543 }
1544
1545 /**
1546 * @brief Set ADC resolution.
1547 * Refer to reference manual for alignments formats
1548 * dependencies to ADC resolutions.
1549 * @note On this STM32 series, setting of this feature is conditioned to
1550 * ADC state:
1551 * ADC must be disabled or enabled without conversion on going
1552 * on group regular.
1553 * @rmtoll CFGR1 RES LL_ADC_SetResolution
1554 * @param ADCx ADC instance
1555 * @param Resolution This parameter can be one of the following values:
1556 * @arg @ref LL_ADC_RESOLUTION_12B
1557 * @arg @ref LL_ADC_RESOLUTION_10B
1558 * @arg @ref LL_ADC_RESOLUTION_8B
1559 * @arg @ref LL_ADC_RESOLUTION_6B
1560 * @retval None
1561 */
LL_ADC_SetResolution(ADC_TypeDef * ADCx,uint32_t Resolution)1562 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
1563 {
1564 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution);
1565 }
1566
1567 /**
1568 * @brief Get ADC resolution.
1569 * Refer to reference manual for alignments formats
1570 * dependencies to ADC resolutions.
1571 * @rmtoll CFGR1 RES LL_ADC_GetResolution
1572 * @param ADCx ADC instance
1573 * @retval Returned value can be one of the following values:
1574 * @arg @ref LL_ADC_RESOLUTION_12B
1575 * @arg @ref LL_ADC_RESOLUTION_10B
1576 * @arg @ref LL_ADC_RESOLUTION_8B
1577 * @arg @ref LL_ADC_RESOLUTION_6B
1578 */
LL_ADC_GetResolution(ADC_TypeDef * ADCx)1579 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
1580 {
1581 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES));
1582 }
1583
1584 /**
1585 * @brief Set ADC conversion data alignment.
1586 * @note Refer to reference manual for alignments formats
1587 * dependencies to ADC resolutions.
1588 * @note On this STM32 series, setting of this feature is conditioned to
1589 * ADC state:
1590 * ADC must be disabled or enabled without conversion on going
1591 * on group regular.
1592 * @rmtoll CFGR1 ALIGN LL_ADC_SetDataAlignment
1593 * @param ADCx ADC instance
1594 * @param DataAlignment This parameter can be one of the following values:
1595 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
1596 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
1597 * @retval None
1598 */
LL_ADC_SetDataAlignment(ADC_TypeDef * ADCx,uint32_t DataAlignment)1599 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
1600 {
1601 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_ALIGN, DataAlignment);
1602 }
1603
1604 /**
1605 * @brief Get ADC conversion data alignment.
1606 * @note Refer to reference manual for alignments formats
1607 * dependencies to ADC resolutions.
1608 * @rmtoll CFGR1 ALIGN LL_ADC_GetDataAlignment
1609 * @param ADCx ADC instance
1610 * @retval Returned value can be one of the following values:
1611 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
1612 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
1613 */
LL_ADC_GetDataAlignment(ADC_TypeDef * ADCx)1614 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
1615 {
1616 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN));
1617 }
1618
1619 /**
1620 * @brief Set ADC low power mode.
1621 * @note Description of ADC low power modes:
1622 * - ADC low power mode "auto wait": Dynamic low power mode,
1623 * ADC conversions occurrences are limited to the minimum necessary
1624 * in order to reduce power consumption.
1625 * New ADC conversion starts only when the previous
1626 * unitary conversion data (for ADC group regular)
1627 * has been retrieved by user software.
1628 * In the meantime, ADC remains idle: does not performs any
1629 * other conversion.
1630 * This mode allows to automatically adapt the ADC conversions
1631 * triggers to the speed of the software that reads the data.
1632 * Moreover, this avoids risk of overrun for low frequency
1633 * applications.
1634 * How to use this low power mode:
1635 * - Do not use with interruption or DMA since these modes
1636 * have to clear immediately the EOC flag to free the
1637 * IRQ vector sequencer.
1638 * - Do use with polling: 1. Start conversion,
1639 * 2. Later on, when conversion data is needed: poll for end of
1640 * conversion to ensure that conversion is completed and
1641 * retrieve ADC conversion data. This will trig another
1642 * ADC conversion start.
1643 * - ADC low power mode "auto power-off" (feature available on
1644 * this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
1645 * the ADC automatically powers-off after a conversion and
1646 * automatically wakes up when a new conversion is triggered
1647 * (with startup time between trigger and start of sampling).
1648 * This feature can be combined with low power mode "auto wait".
1649 * @note With ADC low power mode "auto wait", the ADC conversion data read
1650 * is corresponding to previous ADC conversion start, independently
1651 * of delay during which ADC was idle.
1652 * Therefore, the ADC conversion data may be outdated: does not
1653 * correspond to the current voltage level on the selected
1654 * ADC channel.
1655 * @note On this STM32 series, setting of this feature is conditioned to
1656 * ADC state:
1657 * ADC must be disabled or enabled without conversion on going
1658 * on group regular.
1659 * @rmtoll CFGR1 WAIT LL_ADC_SetLowPowerMode\n
1660 * CFGR1 AUTOFF LL_ADC_SetLowPowerMode
1661 * @param ADCx ADC instance
1662 * @param LowPowerMode This parameter can be one of the following values:
1663 * @arg @ref LL_ADC_LP_MODE_NONE
1664 * @arg @ref LL_ADC_LP_AUTOWAIT
1665 * @arg @ref LL_ADC_LP_AUTOPOWEROFF
1666 * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF
1667 * @retval None
1668 */
LL_ADC_SetLowPowerMode(ADC_TypeDef * ADCx,uint32_t LowPowerMode)1669 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
1670 {
1671 MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF), LowPowerMode);
1672 }
1673
1674 /**
1675 * @brief Get ADC low power mode:
1676 * @note Description of ADC low power modes:
1677 * - ADC low power mode "auto wait": Dynamic low power mode,
1678 * ADC conversions occurrences are limited to the minimum necessary
1679 * in order to reduce power consumption.
1680 * New ADC conversion starts only when the previous
1681 * unitary conversion data (for ADC group regular)
1682 * has been retrieved by user software.
1683 * In the meantime, ADC remains idle: does not performs any
1684 * other conversion.
1685 * This mode allows to automatically adapt the ADC conversions
1686 * triggers to the speed of the software that reads the data.
1687 * Moreover, this avoids risk of overrun for low frequency
1688 * applications.
1689 * How to use this low power mode:
1690 * - Do not use with interruption or DMA since these modes
1691 * have to clear immediately the EOC flag to free the
1692 * IRQ vector sequencer.
1693 * - Do use with polling: 1. Start conversion,
1694 * 2. Later on, when conversion data is needed: poll for end of
1695 * conversion to ensure that conversion is completed and
1696 * retrieve ADC conversion data. This will trig another
1697 * ADC conversion start.
1698 * - ADC low power mode "auto power-off" (feature available on
1699 * this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
1700 * the ADC automatically powers-off after a conversion and
1701 * automatically wakes up when a new conversion is triggered
1702 * (with startup time between trigger and start of sampling).
1703 * This feature can be combined with low power mode "auto wait".
1704 * @note With ADC low power mode "auto wait", the ADC conversion data read
1705 * is corresponding to previous ADC conversion start, independently
1706 * of delay during which ADC was idle.
1707 * Therefore, the ADC conversion data may be outdated: does not
1708 * correspond to the current voltage level on the selected
1709 * ADC channel.
1710 * @rmtoll CFGR1 WAIT LL_ADC_GetLowPowerMode\n
1711 * CFGR1 AUTOFF LL_ADC_GetLowPowerMode
1712 * @param ADCx ADC instance
1713 * @retval Returned value can be one of the following values:
1714 * @arg @ref LL_ADC_LP_MODE_NONE
1715 * @arg @ref LL_ADC_LP_AUTOWAIT
1716 * @arg @ref LL_ADC_LP_AUTOPOWEROFF
1717 * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF
1718 */
LL_ADC_GetLowPowerMode(ADC_TypeDef * ADCx)1719 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
1720 {
1721 return (uint32_t)(READ_BIT(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF)));
1722 }
1723
1724 /**
1725 * @brief Set sampling time common to a group of channels.
1726 * @note Unit: ADC clock cycles.
1727 * @note On this STM32 series, sampling time scope is on ADC instance:
1728 * Sampling time common to all channels.
1729 * (on some other STM32 families, sampling time is channel wise)
1730 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
1731 * converted:
1732 * sampling time constraints must be respected (sampling time can be
1733 * adjusted in function of ADC clock frequency and sampling time
1734 * setting).
1735 * Refer to device datasheet for timings values (parameters TS_vrefint,
1736 * TS_temp, ...).
1737 * @note Conversion time is the addition of sampling time and processing time.
1738 * On this STM32 series, ADC processing time is:
1739 * - 12.5 ADC clock cycles at ADC resolution 12 bits
1740 * - 10.5 ADC clock cycles at ADC resolution 10 bits
1741 * - 8.5 ADC clock cycles at ADC resolution 8 bits
1742 * - 6.5 ADC clock cycles at ADC resolution 6 bits
1743 * @note In case of ADC conversion of internal channel (VrefInt,
1744 * temperature sensor, ...), a sampling time minimum value
1745 * is required.
1746 * Refer to device datasheet.
1747 * @note On this STM32 series, setting of this feature is conditioned to
1748 * ADC state:
1749 * ADC must be disabled or enabled without conversion on going
1750 * on group regular.
1751 * @rmtoll SMPR SMP LL_ADC_SetSamplingTimeCommonChannels
1752 * @param ADCx ADC instance
1753 * @param SamplingTime This parameter can be one of the following values:
1754 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
1755 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
1756 * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
1757 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
1758 * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
1759 * @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
1760 * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
1761 * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
1762 * @retval None
1763 */
LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef * ADCx,uint32_t SamplingTime)1764 __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTime)
1765 {
1766 MODIFY_REG(ADCx->SMPR, ADC_SMPR_SMP, SamplingTime);
1767 }
1768
1769 /**
1770 * @brief Get sampling time common to a group of channels.
1771 * @note Unit: ADC clock cycles.
1772 * @note On this STM32 series, sampling time scope is on ADC instance:
1773 * Sampling time common to all channels.
1774 * (on some other STM32 families, sampling time is channel wise)
1775 * @note Conversion time is the addition of sampling time and processing time.
1776 * Refer to reference manual for ADC processing time of
1777 * this STM32 series.
1778 * @rmtoll SMPR SMP LL_ADC_GetSamplingTimeCommonChannels
1779 * @param ADCx ADC instance
1780 * @retval Returned value can be one of the following values:
1781 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
1782 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
1783 * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
1784 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
1785 * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
1786 * @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
1787 * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
1788 * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
1789 */
LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef * ADCx)1790 __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx)
1791 {
1792 return (uint32_t)(READ_BIT(ADCx->SMPR, ADC_SMPR_SMP));
1793 }
1794
1795 /**
1796 * @}
1797 */
1798
1799 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
1800 * @{
1801 */
1802
1803 /**
1804 * @brief Set ADC group regular conversion trigger source:
1805 * internal (SW start) or from external IP (timer event,
1806 * external interrupt line).
1807 * @note On this STM32 series, setting trigger source to external trigger
1808 * also set trigger polarity to rising edge
1809 * (default setting for compatibility with some ADC on other
1810 * STM32 families having this setting set by HW default value).
1811 * In case of need to modify trigger edge, use
1812 * function @ref LL_ADC_REG_SetTriggerEdge().
1813 * @note Availability of parameters of trigger sources from timer
1814 * depends on timers availability on the selected device.
1815 * @note On this STM32 series, setting of this feature is conditioned to
1816 * ADC state:
1817 * ADC must be disabled or enabled without conversion on going
1818 * on group regular.
1819 * @rmtoll CFGR1 EXTSEL LL_ADC_REG_SetTriggerSource\n
1820 * CFGR1 EXTEN LL_ADC_REG_SetTriggerSource
1821 * @param ADCx ADC instance
1822 * @param TriggerSource This parameter can be one of the following values:
1823 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
1824 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
1825 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4
1826 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO (1)
1827 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
1828 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO (1)
1829 *
1830 * (1) On STM32F0, parameter not available on all devices
1831 * @retval None
1832 */
LL_ADC_REG_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)1833 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
1834 {
1835 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource);
1836 }
1837
1838 /**
1839 * @brief Get ADC group regular conversion trigger source:
1840 * internal (SW start) or from external IP (timer event,
1841 * external interrupt line).
1842 * @note To determine whether group regular trigger source is
1843 * internal (SW start) or external, without detail
1844 * of which peripheral is selected as external trigger,
1845 * (equivalent to
1846 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
1847 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
1848 * @note Availability of parameters of trigger sources from timer
1849 * depends on timers availability on the selected device.
1850 * @rmtoll CFGR1 EXTSEL LL_ADC_REG_GetTriggerSource\n
1851 * CFGR1 EXTEN LL_ADC_REG_GetTriggerSource
1852 * @param ADCx ADC instance
1853 * @retval Returned value can be one of the following values:
1854 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
1855 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
1856 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4
1857 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO (1)
1858 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
1859 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO (1)
1860 *
1861 * (1) On STM32F0, parameter not available on all devices
1862 */
LL_ADC_REG_GetTriggerSource(ADC_TypeDef * ADCx)1863 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
1864 {
1865 uint32_t TriggerSource = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN);
1866
1867 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
1868 /* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}. */
1869 uint32_t ShiftExten = ((TriggerSource & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
1870
1871 /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL */
1872 /* to match with triggers literals definition. */
1873 return ((TriggerSource
1874 & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR1_EXTSEL)
1875 | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR1_EXTEN)
1876 );
1877 }
1878
1879 /**
1880 * @brief Get ADC group regular conversion trigger source internal (SW start)
1881 or external.
1882 * @note In case of group regular trigger source set to external trigger,
1883 * to determine which peripheral is selected as external trigger,
1884 * use function @ref LL_ADC_REG_GetTriggerSource().
1885 * @rmtoll CFGR1 EXTEN LL_ADC_REG_IsTriggerSourceSWStart
1886 * @param ADCx ADC instance
1887 * @retval Value "0" if trigger source external trigger
1888 * Value "1" if trigger source SW start.
1889 */
LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef * ADCx)1890 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
1891 {
1892 return (READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN));
1893 }
1894
1895 /**
1896 * @brief Set ADC group regular conversion trigger polarity.
1897 * @note Applicable only for trigger source set to external trigger.
1898 * @note On this STM32 series, setting of this feature is conditioned to
1899 * ADC state:
1900 * ADC must be disabled or enabled without conversion on going
1901 * on group regular.
1902 * @rmtoll CFGR1 EXTEN LL_ADC_REG_SetTriggerEdge
1903 * @param ADCx ADC instance
1904 * @param ExternalTriggerEdge This parameter can be one of the following values:
1905 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
1906 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
1907 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
1908 * @retval None
1909 */
LL_ADC_REG_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)1910 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
1911 {
1912 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge);
1913 }
1914
1915 /**
1916 * @brief Get ADC group regular conversion trigger polarity.
1917 * @note Applicable only for trigger source set to external trigger.
1918 * @rmtoll CFGR1 EXTEN LL_ADC_REG_GetTriggerEdge
1919 * @param ADCx ADC instance
1920 * @retval Returned value can be one of the following values:
1921 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
1922 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
1923 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
1924 */
LL_ADC_REG_GetTriggerEdge(ADC_TypeDef * ADCx)1925 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
1926 {
1927 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN));
1928 }
1929
1930
1931 /**
1932 * @brief Set ADC group regular sequencer scan direction.
1933 * @note On some other STM32 families, this setting is not available and
1934 * the default scan direction is forward.
1935 * @note On this STM32 series, setting of this feature is conditioned to
1936 * ADC state:
1937 * ADC must be disabled or enabled without conversion on going
1938 * on group regular.
1939 * @rmtoll CFGR1 SCANDIR LL_ADC_REG_SetSequencerScanDirection
1940 * @param ADCx ADC instance
1941 * @param ScanDirection This parameter can be one of the following values:
1942 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
1943 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
1944 * @retval None
1945 */
LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef * ADCx,uint32_t ScanDirection)1946 __STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uint32_t ScanDirection)
1947 {
1948 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_SCANDIR, ScanDirection);
1949 }
1950
1951 /**
1952 * @brief Get ADC group regular sequencer scan direction.
1953 * @note On some other STM32 families, this setting is not available and
1954 * the default scan direction is forward.
1955 * @rmtoll CFGR1 SCANDIR LL_ADC_REG_GetSequencerScanDirection
1956 * @param ADCx ADC instance
1957 * @retval Returned value can be one of the following values:
1958 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
1959 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
1960 */
LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef * ADCx)1961 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef *ADCx)
1962 {
1963 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR));
1964 }
1965
1966 /**
1967 * @brief Set ADC group regular sequencer discontinuous mode:
1968 * sequence subdivided and scan conversions interrupted every selected
1969 * number of ranks.
1970 * @note It is not possible to enable both ADC group regular
1971 * continuous mode and sequencer discontinuous mode.
1972 * @note On this STM32 series, setting of this feature is conditioned to
1973 * ADC state:
1974 * ADC must be disabled or enabled without conversion on going
1975 * on group regular.
1976 * @rmtoll CFGR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
1977 * @param ADCx ADC instance
1978 * @param SeqDiscont This parameter can be one of the following values:
1979 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
1980 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
1981 * @retval None
1982 */
LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)1983 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
1984 {
1985 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN, SeqDiscont);
1986 }
1987
1988 /**
1989 * @brief Get ADC group regular sequencer discontinuous mode:
1990 * sequence subdivided and scan conversions interrupted every selected
1991 * number of ranks.
1992 * @rmtoll CFGR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
1993 * @param ADCx ADC instance
1994 * @retval Returned value can be one of the following values:
1995 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
1996 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
1997 */
LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef * ADCx)1998 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
1999 {
2000 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN));
2001 }
2002
2003 /**
2004 * @brief Set ADC group regular sequence: channel on rank corresponding to
2005 * channel number.
2006 * @note This function performs:
2007 * - Channels ordering into each rank of scan sequence:
2008 * rank of each channel is fixed by channel HW number
2009 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2010 * - Set channels selected by overwriting the current sequencer
2011 * configuration.
2012 * @note On this STM32 series, ADC group regular sequencer is
2013 * not fully configurable: sequencer length and each rank
2014 * affectation to a channel are fixed by channel HW number.
2015 * @note Depending on devices and packages, some channels may not be available.
2016 * Refer to device datasheet for channels availability.
2017 * @note On this STM32 series, to measure internal channels (VrefInt,
2018 * TempSensor, ...), measurement paths to internal channels must be
2019 * enabled separately.
2020 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2021 * @note On this STM32 series, setting of this feature is conditioned to
2022 * ADC state:
2023 * ADC must be disabled or enabled without conversion on going
2024 * on group regular.
2025 * @note One or several values can be selected.
2026 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
2027 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChannels\n
2028 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChannels\n
2029 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChannels\n
2030 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChannels\n
2031 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChannels\n
2032 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChannels\n
2033 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChannels\n
2034 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChannels\n
2035 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChannels\n
2036 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChannels\n
2037 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChannels\n
2038 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChannels\n
2039 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChannels\n
2040 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChannels\n
2041 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChannels\n
2042 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChannels\n
2043 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChannels\n
2044 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChannels\n
2045 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChannels
2046 * @param ADCx ADC instance
2047 * @param Channel This parameter can be a combination of the following values:
2048 * @arg @ref LL_ADC_CHANNEL_0
2049 * @arg @ref LL_ADC_CHANNEL_1
2050 * @arg @ref LL_ADC_CHANNEL_2
2051 * @arg @ref LL_ADC_CHANNEL_3
2052 * @arg @ref LL_ADC_CHANNEL_4
2053 * @arg @ref LL_ADC_CHANNEL_5
2054 * @arg @ref LL_ADC_CHANNEL_6
2055 * @arg @ref LL_ADC_CHANNEL_7
2056 * @arg @ref LL_ADC_CHANNEL_8
2057 * @arg @ref LL_ADC_CHANNEL_9
2058 * @arg @ref LL_ADC_CHANNEL_10
2059 * @arg @ref LL_ADC_CHANNEL_11
2060 * @arg @ref LL_ADC_CHANNEL_12
2061 * @arg @ref LL_ADC_CHANNEL_13
2062 * @arg @ref LL_ADC_CHANNEL_14
2063 * @arg @ref LL_ADC_CHANNEL_15
2064 * @arg @ref LL_ADC_CHANNEL_16
2065 * @arg @ref LL_ADC_CHANNEL_17
2066 * @arg @ref LL_ADC_CHANNEL_18 (1)
2067 * @arg @ref LL_ADC_CHANNEL_VREFINT
2068 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
2069 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2070 *
2071 * (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
2072 * @retval None
2073 */
LL_ADC_REG_SetSequencerChannels(ADC_TypeDef * ADCx,uint32_t Channel)2074 __STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel)
2075 {
2076 /* Parameter "Channel" is used with masks because containing */
2077 /* other bits reserved for other purpose. */
2078 WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
2079 }
2080
2081 /**
2082 * @brief Add channel to ADC group regular sequence: channel on rank corresponding to
2083 * channel number.
2084 * @note This function performs:
2085 * - Channels ordering into each rank of scan sequence:
2086 * rank of each channel is fixed by channel HW number
2087 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2088 * - Set channels selected by adding them to the current sequencer
2089 * configuration.
2090 * @note On this STM32 series, ADC group regular sequencer is
2091 * not fully configurable: sequencer length and each rank
2092 * affectation to a channel are fixed by channel HW number.
2093 * @note Depending on devices and packages, some channels may not be available.
2094 * Refer to device datasheet for channels availability.
2095 * @note On this STM32 series, to measure internal channels (VrefInt,
2096 * TempSensor, ...), measurement paths to internal channels must be
2097 * enabled separately.
2098 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2099 * @note On this STM32 series, setting of this feature is conditioned to
2100 * ADC state:
2101 * ADC must be disabled or enabled without conversion on going
2102 * on group regular.
2103 * @note One or several values can be selected.
2104 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
2105 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChAdd\n
2106 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChAdd\n
2107 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChAdd\n
2108 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChAdd\n
2109 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChAdd\n
2110 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChAdd\n
2111 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChAdd\n
2112 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChAdd\n
2113 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChAdd\n
2114 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChAdd\n
2115 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChAdd\n
2116 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChAdd\n
2117 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChAdd\n
2118 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChAdd\n
2119 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChAdd\n
2120 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChAdd\n
2121 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChAdd\n
2122 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChAdd\n
2123 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChAdd
2124 * @param ADCx ADC instance
2125 * @param Channel This parameter can be a combination of the following values:
2126 * @arg @ref LL_ADC_CHANNEL_0
2127 * @arg @ref LL_ADC_CHANNEL_1
2128 * @arg @ref LL_ADC_CHANNEL_2
2129 * @arg @ref LL_ADC_CHANNEL_3
2130 * @arg @ref LL_ADC_CHANNEL_4
2131 * @arg @ref LL_ADC_CHANNEL_5
2132 * @arg @ref LL_ADC_CHANNEL_6
2133 * @arg @ref LL_ADC_CHANNEL_7
2134 * @arg @ref LL_ADC_CHANNEL_8
2135 * @arg @ref LL_ADC_CHANNEL_9
2136 * @arg @ref LL_ADC_CHANNEL_10
2137 * @arg @ref LL_ADC_CHANNEL_11
2138 * @arg @ref LL_ADC_CHANNEL_12
2139 * @arg @ref LL_ADC_CHANNEL_13
2140 * @arg @ref LL_ADC_CHANNEL_14
2141 * @arg @ref LL_ADC_CHANNEL_15
2142 * @arg @ref LL_ADC_CHANNEL_16
2143 * @arg @ref LL_ADC_CHANNEL_17
2144 * @arg @ref LL_ADC_CHANNEL_18 (1)
2145 * @arg @ref LL_ADC_CHANNEL_VREFINT
2146 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
2147 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2148 *
2149 * (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
2150 * @retval None
2151 */
LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef * ADCx,uint32_t Channel)2152 __STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel)
2153 {
2154 /* Parameter "Channel" is used with masks because containing */
2155 /* other bits reserved for other purpose. */
2156 SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
2157 }
2158
2159 /**
2160 * @brief Remove channel to ADC group regular sequence: channel on rank corresponding to
2161 * channel number.
2162 * @note This function performs:
2163 * - Channels ordering into each rank of scan sequence:
2164 * rank of each channel is fixed by channel HW number
2165 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2166 * - Set channels selected by removing them to the current sequencer
2167 * configuration.
2168 * @note On this STM32 series, ADC group regular sequencer is
2169 * not fully configurable: sequencer length and each rank
2170 * affectation to a channel are fixed by channel HW number.
2171 * @note Depending on devices and packages, some channels may not be available.
2172 * Refer to device datasheet for channels availability.
2173 * @note On this STM32 series, to measure internal channels (VrefInt,
2174 * TempSensor, ...), measurement paths to internal channels must be
2175 * enabled separately.
2176 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2177 * @note On this STM32 series, setting of this feature is conditioned to
2178 * ADC state:
2179 * ADC must be disabled or enabled without conversion on going
2180 * on group regular.
2181 * @note One or several values can be selected.
2182 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
2183 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChRem\n
2184 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChRem\n
2185 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChRem\n
2186 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChRem\n
2187 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChRem\n
2188 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChRem\n
2189 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChRem\n
2190 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChRem\n
2191 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChRem\n
2192 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChRem\n
2193 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChRem\n
2194 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChRem\n
2195 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChRem\n
2196 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChRem\n
2197 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChRem\n
2198 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChRem\n
2199 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChRem\n
2200 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChRem\n
2201 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChRem
2202 * @param ADCx ADC instance
2203 * @param Channel This parameter can be a combination of the following values:
2204 * @arg @ref LL_ADC_CHANNEL_0
2205 * @arg @ref LL_ADC_CHANNEL_1
2206 * @arg @ref LL_ADC_CHANNEL_2
2207 * @arg @ref LL_ADC_CHANNEL_3
2208 * @arg @ref LL_ADC_CHANNEL_4
2209 * @arg @ref LL_ADC_CHANNEL_5
2210 * @arg @ref LL_ADC_CHANNEL_6
2211 * @arg @ref LL_ADC_CHANNEL_7
2212 * @arg @ref LL_ADC_CHANNEL_8
2213 * @arg @ref LL_ADC_CHANNEL_9
2214 * @arg @ref LL_ADC_CHANNEL_10
2215 * @arg @ref LL_ADC_CHANNEL_11
2216 * @arg @ref LL_ADC_CHANNEL_12
2217 * @arg @ref LL_ADC_CHANNEL_13
2218 * @arg @ref LL_ADC_CHANNEL_14
2219 * @arg @ref LL_ADC_CHANNEL_15
2220 * @arg @ref LL_ADC_CHANNEL_16
2221 * @arg @ref LL_ADC_CHANNEL_17
2222 * @arg @ref LL_ADC_CHANNEL_18 (1)
2223 * @arg @ref LL_ADC_CHANNEL_VREFINT
2224 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
2225 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2226 *
2227 * (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
2228 * @retval None
2229 */
LL_ADC_REG_SetSequencerChRem(ADC_TypeDef * ADCx,uint32_t Channel)2230 __STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel)
2231 {
2232 /* Parameter "Channel" is used with masks because containing */
2233 /* other bits reserved for other purpose. */
2234 CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
2235 }
2236
2237 /**
2238 * @brief Get ADC group regular sequence: channel on rank corresponding to
2239 * channel number.
2240 * @note This function performs:
2241 * - Channels order reading into each rank of scan sequence:
2242 * rank of each channel is fixed by channel HW number
2243 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2244 * @note On this STM32 series, ADC group regular sequencer is
2245 * not fully configurable: sequencer length and each rank
2246 * affectation to a channel are fixed by channel HW number.
2247 * @note Depending on devices and packages, some channels may not be available.
2248 * Refer to device datasheet for channels availability.
2249 * @note On this STM32 series, to measure internal channels (VrefInt,
2250 * TempSensor, ...), measurement paths to internal channels must be
2251 * enabled separately.
2252 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2253 * @note On this STM32 series, setting of this feature is conditioned to
2254 * ADC state:
2255 * ADC must be disabled or enabled without conversion on going
2256 * on group regular.
2257 * @note One or several values can be retrieved.
2258 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
2259 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_GetSequencerChannels\n
2260 * CHSELR CHSEL1 LL_ADC_REG_GetSequencerChannels\n
2261 * CHSELR CHSEL2 LL_ADC_REG_GetSequencerChannels\n
2262 * CHSELR CHSEL3 LL_ADC_REG_GetSequencerChannels\n
2263 * CHSELR CHSEL4 LL_ADC_REG_GetSequencerChannels\n
2264 * CHSELR CHSEL5 LL_ADC_REG_GetSequencerChannels\n
2265 * CHSELR CHSEL6 LL_ADC_REG_GetSequencerChannels\n
2266 * CHSELR CHSEL7 LL_ADC_REG_GetSequencerChannels\n
2267 * CHSELR CHSEL8 LL_ADC_REG_GetSequencerChannels\n
2268 * CHSELR CHSEL9 LL_ADC_REG_GetSequencerChannels\n
2269 * CHSELR CHSEL10 LL_ADC_REG_GetSequencerChannels\n
2270 * CHSELR CHSEL11 LL_ADC_REG_GetSequencerChannels\n
2271 * CHSELR CHSEL12 LL_ADC_REG_GetSequencerChannels\n
2272 * CHSELR CHSEL13 LL_ADC_REG_GetSequencerChannels\n
2273 * CHSELR CHSEL14 LL_ADC_REG_GetSequencerChannels\n
2274 * CHSELR CHSEL15 LL_ADC_REG_GetSequencerChannels\n
2275 * CHSELR CHSEL16 LL_ADC_REG_GetSequencerChannels\n
2276 * CHSELR CHSEL17 LL_ADC_REG_GetSequencerChannels\n
2277 * CHSELR CHSEL18 LL_ADC_REG_GetSequencerChannels
2278 * @param ADCx ADC instance
2279 * @retval Returned value can be a combination of the following values:
2280 * @arg @ref LL_ADC_CHANNEL_0
2281 * @arg @ref LL_ADC_CHANNEL_1
2282 * @arg @ref LL_ADC_CHANNEL_2
2283 * @arg @ref LL_ADC_CHANNEL_3
2284 * @arg @ref LL_ADC_CHANNEL_4
2285 * @arg @ref LL_ADC_CHANNEL_5
2286 * @arg @ref LL_ADC_CHANNEL_6
2287 * @arg @ref LL_ADC_CHANNEL_7
2288 * @arg @ref LL_ADC_CHANNEL_8
2289 * @arg @ref LL_ADC_CHANNEL_9
2290 * @arg @ref LL_ADC_CHANNEL_10
2291 * @arg @ref LL_ADC_CHANNEL_11
2292 * @arg @ref LL_ADC_CHANNEL_12
2293 * @arg @ref LL_ADC_CHANNEL_13
2294 * @arg @ref LL_ADC_CHANNEL_14
2295 * @arg @ref LL_ADC_CHANNEL_15
2296 * @arg @ref LL_ADC_CHANNEL_16
2297 * @arg @ref LL_ADC_CHANNEL_17
2298 * @arg @ref LL_ADC_CHANNEL_18 (1)
2299 * @arg @ref LL_ADC_CHANNEL_VREFINT
2300 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
2301 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2302 *
2303 * (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
2304 */
LL_ADC_REG_GetSequencerChannels(ADC_TypeDef * ADCx)2305 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx)
2306 {
2307 uint32_t ChannelsBitfield = READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL);
2308
2309 return ( (((ChannelsBitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0)
2310 | (((ChannelsBitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1)
2311 | (((ChannelsBitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2)
2312 | (((ChannelsBitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3)
2313 | (((ChannelsBitfield & ADC_CHSELR_CHSEL4) >> ADC_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4)
2314 | (((ChannelsBitfield & ADC_CHSELR_CHSEL5) >> ADC_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5)
2315 | (((ChannelsBitfield & ADC_CHSELR_CHSEL6) >> ADC_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6)
2316 | (((ChannelsBitfield & ADC_CHSELR_CHSEL7) >> ADC_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7)
2317 | (((ChannelsBitfield & ADC_CHSELR_CHSEL8) >> ADC_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_CHANNEL_8)
2318 | (((ChannelsBitfield & ADC_CHSELR_CHSEL9) >> ADC_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_CHANNEL_9)
2319 | (((ChannelsBitfield & ADC_CHSELR_CHSEL10) >> ADC_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10)
2320 | (((ChannelsBitfield & ADC_CHSELR_CHSEL11) >> ADC_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11)
2321 | (((ChannelsBitfield & ADC_CHSELR_CHSEL12) >> ADC_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12)
2322 | (((ChannelsBitfield & ADC_CHSELR_CHSEL13) >> ADC_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13)
2323 | (((ChannelsBitfield & ADC_CHSELR_CHSEL14) >> ADC_CHSELR_CHSEL14_BITOFFSET_POS) * LL_ADC_CHANNEL_14)
2324 | (((ChannelsBitfield & ADC_CHSELR_CHSEL15) >> ADC_CHSELR_CHSEL15_BITOFFSET_POS) * LL_ADC_CHANNEL_15)
2325 | (((ChannelsBitfield & ADC_CHSELR_CHSEL16) >> ADC_CHSELR_CHSEL16_BITOFFSET_POS) * LL_ADC_CHANNEL_16)
2326 | (((ChannelsBitfield & ADC_CHSELR_CHSEL17) >> ADC_CHSELR_CHSEL17_BITOFFSET_POS) * LL_ADC_CHANNEL_17)
2327 #if defined(ADC_CCR_VBATEN)
2328 | (((ChannelsBitfield & ADC_CHSELR_CHSEL18) >> ADC_CHSELR_CHSEL18_BITOFFSET_POS) * LL_ADC_CHANNEL_18)
2329 #endif
2330 );
2331 }
2332 /**
2333 * @brief Set ADC continuous conversion mode on ADC group regular.
2334 * @note Description of ADC continuous conversion mode:
2335 * - single mode: one conversion per trigger
2336 * - continuous mode: after the first trigger, following
2337 * conversions launched successively automatically.
2338 * @note It is not possible to enable both ADC group regular
2339 * continuous mode and sequencer discontinuous mode.
2340 * @note On this STM32 series, setting of this feature is conditioned to
2341 * ADC state:
2342 * ADC must be disabled or enabled without conversion on going
2343 * on group regular.
2344 * @rmtoll CFGR1 CONT LL_ADC_REG_SetContinuousMode
2345 * @param ADCx ADC instance
2346 * @param Continuous This parameter can be one of the following values:
2347 * @arg @ref LL_ADC_REG_CONV_SINGLE
2348 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
2349 * @retval None
2350 */
LL_ADC_REG_SetContinuousMode(ADC_TypeDef * ADCx,uint32_t Continuous)2351 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
2352 {
2353 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous);
2354 }
2355
2356 /**
2357 * @brief Get ADC continuous conversion mode on ADC group regular.
2358 * @note Description of ADC continuous conversion mode:
2359 * - single mode: one conversion per trigger
2360 * - continuous mode: after the first trigger, following
2361 * conversions launched successively automatically.
2362 * @rmtoll CFGR1 CONT LL_ADC_REG_GetContinuousMode
2363 * @param ADCx ADC instance
2364 * @retval Returned value can be one of the following values:
2365 * @arg @ref LL_ADC_REG_CONV_SINGLE
2366 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
2367 */
LL_ADC_REG_GetContinuousMode(ADC_TypeDef * ADCx)2368 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
2369 {
2370 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT));
2371 }
2372
2373 /**
2374 * @brief Set ADC group regular conversion data transfer: no transfer or
2375 * transfer by DMA, and DMA requests mode.
2376 * @note If transfer by DMA selected, specifies the DMA requests
2377 * mode:
2378 * - Limited mode (One shot mode): DMA transfer requests are stopped
2379 * when number of DMA data transfers (number of
2380 * ADC conversions) is reached.
2381 * This ADC mode is intended to be used with DMA mode non-circular.
2382 * - Unlimited mode: DMA transfer requests are unlimited,
2383 * whatever number of DMA data transfers (number of
2384 * ADC conversions).
2385 * This ADC mode is intended to be used with DMA mode circular.
2386 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
2387 * mode non-circular:
2388 * when DMA transfers size will be reached, DMA will stop transfers of
2389 * ADC conversions data ADC will raise an overrun error
2390 * (overrun flag and interruption if enabled).
2391 * @note To configure DMA source address (peripheral address),
2392 * use function @ref LL_ADC_DMA_GetRegAddr().
2393 * @note On this STM32 series, setting of this feature is conditioned to
2394 * ADC state:
2395 * ADC must be disabled or enabled without conversion on going
2396 * on group regular.
2397 * @rmtoll CFGR1 DMAEN LL_ADC_REG_SetDMATransfer\n
2398 * CFGR1 DMACFG LL_ADC_REG_SetDMATransfer
2399 * @param ADCx ADC instance
2400 * @param DMATransfer This parameter can be one of the following values:
2401 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
2402 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
2403 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
2404 * @retval None
2405 */
LL_ADC_REG_SetDMATransfer(ADC_TypeDef * ADCx,uint32_t DMATransfer)2406 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
2407 {
2408 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG, DMATransfer);
2409 }
2410
2411 /**
2412 * @brief Get ADC group regular conversion data transfer: no transfer or
2413 * transfer by DMA, and DMA requests mode.
2414 * @note If transfer by DMA selected, specifies the DMA requests
2415 * mode:
2416 * - Limited mode (One shot mode): DMA transfer requests are stopped
2417 * when number of DMA data transfers (number of
2418 * ADC conversions) is reached.
2419 * This ADC mode is intended to be used with DMA mode non-circular.
2420 * - Unlimited mode: DMA transfer requests are unlimited,
2421 * whatever number of DMA data transfers (number of
2422 * ADC conversions).
2423 * This ADC mode is intended to be used with DMA mode circular.
2424 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
2425 * mode non-circular:
2426 * when DMA transfers size will be reached, DMA will stop transfers of
2427 * ADC conversions data ADC will raise an overrun error
2428 * (overrun flag and interruption if enabled).
2429 * @note To configure DMA source address (peripheral address),
2430 * use function @ref LL_ADC_DMA_GetRegAddr().
2431 * @rmtoll CFGR1 DMAEN LL_ADC_REG_GetDMATransfer\n
2432 * CFGR1 DMACFG LL_ADC_REG_GetDMATransfer
2433 * @param ADCx ADC instance
2434 * @retval Returned value can be one of the following values:
2435 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
2436 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
2437 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
2438 */
LL_ADC_REG_GetDMATransfer(ADC_TypeDef * ADCx)2439 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
2440 {
2441 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG));
2442 }
2443
2444 /**
2445 * @brief Set ADC group regular behavior in case of overrun:
2446 * data preserved or overwritten.
2447 * @note Compatibility with devices without feature overrun:
2448 * other devices without this feature have a behavior
2449 * equivalent to data overwritten.
2450 * The default setting of overrun is data preserved.
2451 * Therefore, for compatibility with all devices, parameter
2452 * overrun should be set to data overwritten.
2453 * @note On this STM32 series, setting of this feature is conditioned to
2454 * ADC state:
2455 * ADC must be disabled or enabled without conversion on going
2456 * on group regular.
2457 * @rmtoll CFGR1 OVRMOD LL_ADC_REG_SetOverrun
2458 * @param ADCx ADC instance
2459 * @param Overrun This parameter can be one of the following values:
2460 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
2461 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
2462 * @retval None
2463 */
LL_ADC_REG_SetOverrun(ADC_TypeDef * ADCx,uint32_t Overrun)2464 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
2465 {
2466 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun);
2467 }
2468
2469 /**
2470 * @brief Get ADC group regular behavior in case of overrun:
2471 * data preserved or overwritten.
2472 * @rmtoll CFGR1 OVRMOD LL_ADC_REG_GetOverrun
2473 * @param ADCx ADC instance
2474 * @retval Returned value can be one of the following values:
2475 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
2476 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
2477 */
LL_ADC_REG_GetOverrun(ADC_TypeDef * ADCx)2478 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
2479 {
2480 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD));
2481 }
2482
2483 /**
2484 * @}
2485 */
2486
2487
2488 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
2489 * @{
2490 */
2491
2492 /**
2493 * @brief Set ADC analog watchdog monitored channels:
2494 * a single channel or all channels,
2495 * on ADC group regular.
2496 * @note Once monitored channels are selected, analog watchdog
2497 * is enabled.
2498 * @note In case of need to define a single channel to monitor
2499 * with analog watchdog from sequencer channel definition,
2500 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
2501 * @note On this STM32 series, there is only 1 kind of analog watchdog
2502 * instance:
2503 * - AWD standard (instance AWD1):
2504 * - channels monitored: can monitor 1 channel or all channels.
2505 * - groups monitored: ADC group regular.
2506 * - resolution: resolution is not limited (corresponds to
2507 * ADC resolution configured).
2508 * @note On this STM32 series, setting of this feature is conditioned to
2509 * ADC state:
2510 * ADC must be disabled or enabled without conversion on going
2511 * on group regular.
2512 * @rmtoll CFGR1 AWDCH LL_ADC_SetAnalogWDMonitChannels\n
2513 * CFGR1 AWDSGL LL_ADC_SetAnalogWDMonitChannels\n
2514 * CFGR1 AWDEN LL_ADC_SetAnalogWDMonitChannels
2515 * @param ADCx ADC instance
2516 * @param AWDChannelGroup This parameter can be one of the following values:
2517 * @arg @ref LL_ADC_AWD_DISABLE
2518 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
2519 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
2520 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
2521 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
2522 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
2523 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
2524 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
2525 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
2526 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
2527 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
2528 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
2529 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
2530 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
2531 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
2532 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
2533 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
2534 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
2535 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
2536 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
2537 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (1)
2538 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG
2539 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
2540 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
2541 *
2542 * (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
2543 * @retval None
2544 */
LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDChannelGroup)2545 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
2546 {
2547 MODIFY_REG(ADCx->CFGR1,
2548 (ADC_CFGR1_AWDCH | ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN),
2549 (AWDChannelGroup & ADC_AWD_CR_ALL_CHANNEL_MASK));
2550 }
2551
2552 /**
2553 * @brief Get ADC analog watchdog monitored channel.
2554 * @note Usage of the returned channel number:
2555 * - To reinject this channel into another function LL_ADC_xxx:
2556 * the returned channel number is only partly formatted on definition
2557 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
2558 * with parts of literals LL_ADC_CHANNEL_x or using
2559 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2560 * Then the selected literal LL_ADC_CHANNEL_x can be used
2561 * as parameter for another function.
2562 * - To get the channel number in decimal format:
2563 * process the returned value with the helper macro
2564 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2565 * Applicable only when the analog watchdog is set to monitor
2566 * one channel.
2567 * @note On this STM32 series, there is only 1 kind of analog watchdog
2568 * instance:
2569 * - AWD standard (instance AWD1):
2570 * - channels monitored: can monitor 1 channel or all channels.
2571 * - groups monitored: ADC group regular.
2572 * - resolution: resolution is not limited (corresponds to
2573 * ADC resolution configured).
2574 * @note On this STM32 series, setting of this feature is conditioned to
2575 * ADC state:
2576 * ADC must be disabled or enabled without conversion on going
2577 * on group regular.
2578 * @rmtoll CFGR1 AWDCH LL_ADC_GetAnalogWDMonitChannels\n
2579 * CFGR1 AWDSGL LL_ADC_GetAnalogWDMonitChannels\n
2580 * CFGR1 AWDEN LL_ADC_GetAnalogWDMonitChannels
2581 * @param ADCx ADC instance
2582 * @retval Returned value can be one of the following values:
2583 * @arg @ref LL_ADC_AWD_DISABLE
2584 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
2585 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
2586 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
2587 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
2588 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
2589 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
2590 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
2591 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
2592 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
2593 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
2594 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
2595 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
2596 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
2597 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
2598 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
2599 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
2600 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
2601 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
2602 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
2603 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
2604 */
LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef * ADCx)2605 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
2606 {
2607 uint32_t AWDChannelGroup = READ_BIT(ADCx->CFGR1, (ADC_CFGR1_AWDCH | ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN));
2608
2609 /* Note: Set variable according to channel definition including channel ID */
2610 /* with bitfield. */
2611 uint32_t AWDChannelSingle = ((AWDChannelGroup & ADC_CFGR1_AWDSGL) >> ADC_CFGR1_AWDSGL_BITOFFSET_POS);
2612 uint32_t AWDChannelBitField = (ADC_CHANNEL_0_BITFIELD << ((AWDChannelGroup & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS));
2613
2614 return (AWDChannelGroup | (AWDChannelBitField * AWDChannelSingle));
2615 }
2616
2617 /**
2618 * @brief Set ADC analog watchdog thresholds value of both thresholds
2619 * high and low.
2620 * @note If value of only one threshold high or low must be set,
2621 * use function @ref LL_ADC_SetAnalogWDThresholds().
2622 * @note In case of ADC resolution different of 12 bits,
2623 * analog watchdog thresholds data require a specific shift.
2624 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
2625 * @note On this STM32 series, there is only 1 kind of analog watchdog
2626 * instance:
2627 * - AWD standard (instance AWD1):
2628 * - channels monitored: can monitor 1 channel or all channels.
2629 * - groups monitored: ADC group regular.
2630 * - resolution: resolution is not limited (corresponds to
2631 * ADC resolution configured).
2632 * @note On this STM32 series, setting of this feature is conditioned to
2633 * ADC state:
2634 * ADC must be disabled or enabled without conversion on going
2635 * on group regular.
2636 * @rmtoll TR HT LL_ADC_ConfigAnalogWDThresholds\n
2637 * TR LT LL_ADC_ConfigAnalogWDThresholds
2638 * @param ADCx ADC instance
2639 * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
2640 * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
2641 * @retval None
2642 */
LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDThresholdHighValue,uint32_t AWDThresholdLowValue)2643 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
2644 {
2645 MODIFY_REG(ADCx->TR,
2646 ADC_TR_HT | ADC_TR_LT,
2647 (AWDThresholdHighValue << ADC_TR_HT_BITOFFSET_POS) | AWDThresholdLowValue);
2648 }
2649
2650 /**
2651 * @brief Set ADC analog watchdog threshold value of threshold
2652 * high or low.
2653 * @note If values of both thresholds high or low must be set,
2654 * use function @ref LL_ADC_ConfigAnalogWDThresholds().
2655 * @note In case of ADC resolution different of 12 bits,
2656 * analog watchdog thresholds data require a specific shift.
2657 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
2658 * @note On this STM32 series, there is only 1 kind of analog watchdog
2659 * instance:
2660 * - AWD standard (instance AWD1):
2661 * - channels monitored: can monitor 1 channel or all channels.
2662 * - groups monitored: ADC group regular.
2663 * - resolution: resolution is not limited (corresponds to
2664 * ADC resolution configured).
2665 * @note On this STM32 series, setting of this feature is conditioned to
2666 * ADC state:
2667 * ADC must be disabled or enabled without conversion on going
2668 * on group regular.
2669 * @rmtoll TR HT LL_ADC_SetAnalogWDThresholds\n
2670 * TR LT LL_ADC_SetAnalogWDThresholds
2671 * @param ADCx ADC instance
2672 * @param AWDThresholdsHighLow This parameter can be one of the following values:
2673 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
2674 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
2675 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
2676 * @retval None
2677 */
LL_ADC_SetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDThresholdsHighLow,uint32_t AWDThresholdValue)2678 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
2679 {
2680 /* Parameter "AWDThresholdsHighLow" is used with mask "0x00000010" */
2681 /* to be equivalent to "POSITION_VAL(AWDThresholdsHighLow)": if threshold */
2682 /* high is selected, then data is shifted to LSB. Else(threshold low), */
2683 /* data is not shifted. */
2684 MODIFY_REG(ADCx->TR,
2685 AWDThresholdsHighLow,
2686 AWDThresholdValue << ((AWDThresholdsHighLow >> ADC_TR_HT_BITOFFSET_POS) & 0x00000010U));
2687 }
2688
2689 /**
2690 * @brief Get ADC analog watchdog threshold value of threshold high,
2691 * threshold low or raw data with ADC thresholds high and low
2692 * concatenated.
2693 * @note If raw data with ADC thresholds high and low is retrieved,
2694 * the data of each threshold high or low can be isolated
2695 * using helper macro:
2696 * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
2697 * @note In case of ADC resolution different of 12 bits,
2698 * analog watchdog thresholds data require a specific shift.
2699 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
2700 * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n
2701 * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n
2702 * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n
2703 * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n
2704 * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n
2705 * TR3 LT3 LL_ADC_GetAnalogWDThresholds
2706 * @param ADCx ADC instance
2707 * @param AWDThresholdsHighLow This parameter can be one of the following values:
2708 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
2709 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
2710 * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
2711 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2712 */
LL_ADC_GetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDThresholdsHighLow)2713 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
2714 {
2715 /* Parameter "AWDThresholdsHighLow" is used with mask "0x00000010" */
2716 /* to be equivalent to "POSITION_VAL(AWDThresholdsHighLow)": if threshold */
2717 /* high is selected, then data is shifted to LSB. Else(threshold low or */
2718 /* both thresholds), data is not shifted. */
2719 return (uint32_t)(READ_BIT(ADCx->TR,
2720 (AWDThresholdsHighLow | ADC_TR_LT))
2721 >> ((~AWDThresholdsHighLow) & 0x00000010U)
2722 );
2723 }
2724
2725 /**
2726 * @}
2727 */
2728
2729 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
2730 * @{
2731 */
2732
2733 /**
2734 * @brief Enable the selected ADC instance.
2735 * @note On this STM32 series, after ADC enable, a delay for
2736 * ADC internal analog stabilization is required before performing a
2737 * ADC conversion start.
2738 * Refer to device datasheet, parameter tSTAB.
2739 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
2740 * is enabled and when conversion clock is active.
2741 * (not only core clock: this ADC has a dual clock domain)
2742 * @note On this STM32 series, setting of this feature is conditioned to
2743 * ADC state:
2744 * ADC must be ADC disabled and ADC internal voltage regulator enabled.
2745 * @rmtoll CR ADEN LL_ADC_Enable
2746 * @param ADCx ADC instance
2747 * @retval None
2748 */
LL_ADC_Enable(ADC_TypeDef * ADCx)2749 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
2750 {
2751 /* Note: Write register with some additional bits forced to state reset */
2752 /* instead of modifying only the selected bit for this function, */
2753 /* to not interfere with bits with HW property "rs". */
2754 MODIFY_REG(ADCx->CR,
2755 ADC_CR_BITS_PROPERTY_RS,
2756 ADC_CR_ADEN);
2757 }
2758
2759 /**
2760 * @brief Disable the selected ADC instance.
2761 * @note On this STM32 series, setting of this feature is conditioned to
2762 * ADC state:
2763 * ADC must be not disabled. Must be enabled without conversion on going
2764 * on group regular.
2765 * @rmtoll CR ADDIS LL_ADC_Disable
2766 * @param ADCx ADC instance
2767 * @retval None
2768 */
LL_ADC_Disable(ADC_TypeDef * ADCx)2769 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
2770 {
2771 /* Note: Write register with some additional bits forced to state reset */
2772 /* instead of modifying only the selected bit for this function, */
2773 /* to not interfere with bits with HW property "rs". */
2774 MODIFY_REG(ADCx->CR,
2775 ADC_CR_BITS_PROPERTY_RS,
2776 ADC_CR_ADDIS);
2777 }
2778
2779 /**
2780 * @brief Get the selected ADC instance enable state.
2781 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
2782 * is enabled and when conversion clock is active.
2783 * (not only core clock: this ADC has a dual clock domain)
2784 * @rmtoll CR ADEN LL_ADC_IsEnabled
2785 * @param ADCx ADC instance
2786 * @retval 0: ADC is disabled, 1: ADC is enabled.
2787 */
LL_ADC_IsEnabled(ADC_TypeDef * ADCx)2788 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
2789 {
2790 return (READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN));
2791 }
2792
2793 /**
2794 * @brief Get the selected ADC instance disable state.
2795 * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
2796 * @param ADCx ADC instance
2797 * @retval 0: no ADC disable command on going.
2798 */
LL_ADC_IsDisableOngoing(ADC_TypeDef * ADCx)2799 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
2800 {
2801 return (READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS));
2802 }
2803
2804 /**
2805 * @brief Start ADC calibration in the mode single-ended
2806 * or differential (for devices with differential mode available).
2807 * @note On this STM32 series, a minimum number of ADC clock cycles
2808 * are required between ADC end of calibration and ADC enable.
2809 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
2810 * @note In case of usage of ADC with DMA transfer:
2811 * On this STM32 series, ADC DMA transfer request should be disabled
2812 * during calibration:
2813 * Calibration factor is available in data register
2814 * and also transferred by DMA.
2815 * To not insert ADC calibration factor among ADC conversion data
2816 * in array variable, DMA transfer must be disabled during
2817 * calibration.
2818 * (DMA transfer setting backup and disable before calibration,
2819 * DMA transfer setting restore after calibration.
2820 * Refer to functions @ref LL_ADC_REG_GetDMATransfer(),
2821 * @ref LL_ADC_REG_SetDMATransfer() ).
2822 * @note On this STM32 series, setting of this feature is conditioned to
2823 * ADC state:
2824 * ADC must be ADC disabled.
2825 * @rmtoll CR ADCAL LL_ADC_StartCalibration
2826 * @param ADCx ADC instance
2827 * @retval None
2828 */
LL_ADC_StartCalibration(ADC_TypeDef * ADCx)2829 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx)
2830 {
2831 /* Note: Write register with some additional bits forced to state reset */
2832 /* instead of modifying only the selected bit for this function, */
2833 /* to not interfere with bits with HW property "rs". */
2834 MODIFY_REG(ADCx->CR,
2835 ADC_CR_BITS_PROPERTY_RS,
2836 ADC_CR_ADCAL);
2837 }
2838
2839 /**
2840 * @brief Get ADC calibration state.
2841 * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
2842 * @param ADCx ADC instance
2843 * @retval 0: calibration complete, 1: calibration in progress.
2844 */
LL_ADC_IsCalibrationOnGoing(ADC_TypeDef * ADCx)2845 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
2846 {
2847 return (READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL));
2848 }
2849
2850 /**
2851 * @}
2852 */
2853
2854 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
2855 * @{
2856 */
2857
2858 /**
2859 * @brief Start ADC group regular conversion.
2860 * @note On this STM32 series, this function is relevant for both
2861 * internal trigger (SW start) and external trigger:
2862 * - If ADC trigger has been set to software start, ADC conversion
2863 * starts immediately.
2864 * - If ADC trigger has been set to external trigger, ADC conversion
2865 * will start at next trigger event (on the selected trigger edge)
2866 * following the ADC start conversion command.
2867 * @note On this STM32 series, setting of this feature is conditioned to
2868 * ADC state:
2869 * ADC must be enabled without conversion on going on group regular,
2870 * without conversion stop command on going on group regular,
2871 * without ADC disable command on going.
2872 * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
2873 * @param ADCx ADC instance
2874 * @retval None
2875 */
LL_ADC_REG_StartConversion(ADC_TypeDef * ADCx)2876 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
2877 {
2878 /* Note: Write register with some additional bits forced to state reset */
2879 /* instead of modifying only the selected bit for this function, */
2880 /* to not interfere with bits with HW property "rs". */
2881 MODIFY_REG(ADCx->CR,
2882 ADC_CR_BITS_PROPERTY_RS,
2883 ADC_CR_ADSTART);
2884 }
2885
2886 /**
2887 * @brief Stop ADC group regular conversion.
2888 * @note On this STM32 series, setting of this feature is conditioned to
2889 * ADC state:
2890 * ADC must be enabled with conversion on going on group regular,
2891 * without ADC disable command on going.
2892 * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
2893 * @param ADCx ADC instance
2894 * @retval None
2895 */
LL_ADC_REG_StopConversion(ADC_TypeDef * ADCx)2896 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
2897 {
2898 /* Note: Write register with some additional bits forced to state reset */
2899 /* instead of modifying only the selected bit for this function, */
2900 /* to not interfere with bits with HW property "rs". */
2901 MODIFY_REG(ADCx->CR,
2902 ADC_CR_BITS_PROPERTY_RS,
2903 ADC_CR_ADSTP);
2904 }
2905
2906 /**
2907 * @brief Get ADC group regular conversion state.
2908 * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
2909 * @param ADCx ADC instance
2910 * @retval 0: no conversion is on going on ADC group regular.
2911 */
LL_ADC_REG_IsConversionOngoing(ADC_TypeDef * ADCx)2912 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
2913 {
2914 return (READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART));
2915 }
2916
2917 /**
2918 * @brief Get ADC group regular command of conversion stop state
2919 * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
2920 * @param ADCx ADC instance
2921 * @retval 0: no command of conversion stop is on going on ADC group regular.
2922 */
LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef * ADCx)2923 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
2924 {
2925 return (READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP));
2926 }
2927
2928 /**
2929 * @brief Get ADC group regular conversion data, range fit for
2930 * all ADC configurations: all ADC resolutions and
2931 * all oversampling increased data width (for devices
2932 * with feature oversampling).
2933 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData32
2934 * @param ADCx ADC instance
2935 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2936 */
LL_ADC_REG_ReadConversionData32(ADC_TypeDef * ADCx)2937 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
2938 {
2939 return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
2940 }
2941
2942 /**
2943 * @brief Get ADC group regular conversion data, range fit for
2944 * ADC resolution 12 bits.
2945 * @note For devices with feature oversampling: Oversampling
2946 * can increase data width, function for extended range
2947 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
2948 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData12
2949 * @param ADCx ADC instance
2950 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2951 */
LL_ADC_REG_ReadConversionData12(ADC_TypeDef * ADCx)2952 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
2953 {
2954 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
2955 }
2956
2957 /**
2958 * @brief Get ADC group regular conversion data, range fit for
2959 * ADC resolution 10 bits.
2960 * @note For devices with feature oversampling: Oversampling
2961 * can increase data width, function for extended range
2962 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
2963 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData10
2964 * @param ADCx ADC instance
2965 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
2966 */
LL_ADC_REG_ReadConversionData10(ADC_TypeDef * ADCx)2967 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
2968 {
2969 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
2970 }
2971
2972 /**
2973 * @brief Get ADC group regular conversion data, range fit for
2974 * ADC resolution 8 bits.
2975 * @note For devices with feature oversampling: Oversampling
2976 * can increase data width, function for extended range
2977 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
2978 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData8
2979 * @param ADCx ADC instance
2980 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
2981 */
LL_ADC_REG_ReadConversionData8(ADC_TypeDef * ADCx)2982 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
2983 {
2984 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
2985 }
2986
2987 /**
2988 * @brief Get ADC group regular conversion data, range fit for
2989 * ADC resolution 6 bits.
2990 * @note For devices with feature oversampling: Oversampling
2991 * can increase data width, function for extended range
2992 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
2993 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData6
2994 * @param ADCx ADC instance
2995 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
2996 */
LL_ADC_REG_ReadConversionData6(ADC_TypeDef * ADCx)2997 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
2998 {
2999 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3000 }
3001
3002 /**
3003 * @}
3004 */
3005
3006 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
3007 * @{
3008 */
3009
3010 /**
3011 * @brief Get flag ADC ready.
3012 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
3013 * is enabled and when conversion clock is active.
3014 * (not only core clock: this ADC has a dual clock domain)
3015 * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
3016 * @param ADCx ADC instance
3017 * @retval State of bit (1 or 0).
3018 */
LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef * ADCx)3019 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
3020 {
3021 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY));
3022 }
3023
3024 /**
3025 * @brief Get flag ADC group regular end of unitary conversion.
3026 * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
3027 * @param ADCx ADC instance
3028 * @retval State of bit (1 or 0).
3029 */
LL_ADC_IsActiveFlag_EOC(ADC_TypeDef * ADCx)3030 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
3031 {
3032 return (READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC));
3033 }
3034
3035 /**
3036 * @brief Get flag ADC group regular end of sequence conversions.
3037 * @rmtoll ISR EOSEQ LL_ADC_IsActiveFlag_EOS
3038 * @param ADCx ADC instance
3039 * @retval State of bit (1 or 0).
3040 */
LL_ADC_IsActiveFlag_EOS(ADC_TypeDef * ADCx)3041 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
3042 {
3043 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS));
3044 }
3045
3046 /**
3047 * @brief Get flag ADC group regular overrun.
3048 * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
3049 * @param ADCx ADC instance
3050 * @retval State of bit (1 or 0).
3051 */
LL_ADC_IsActiveFlag_OVR(ADC_TypeDef * ADCx)3052 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
3053 {
3054 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));
3055 }
3056
3057 /**
3058 * @brief Get flag ADC group regular end of sampling phase.
3059 * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
3060 * @param ADCx ADC instance
3061 * @retval State of bit (1 or 0).
3062 */
LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef * ADCx)3063 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
3064 {
3065 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP));
3066 }
3067
3068 /**
3069 * @brief Get flag ADC analog watchdog 1 flag
3070 * @rmtoll ISR AWD LL_ADC_IsActiveFlag_AWD1
3071 * @param ADCx ADC instance
3072 * @retval State of bit (1 or 0).
3073 */
LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef * ADCx)3074 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
3075 {
3076 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
3077 }
3078
3079 /**
3080 * @brief Clear flag ADC ready.
3081 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
3082 * is enabled and when conversion clock is active.
3083 * (not only core clock: this ADC has a dual clock domain)
3084 * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
3085 * @param ADCx ADC instance
3086 * @retval None
3087 */
LL_ADC_ClearFlag_ADRDY(ADC_TypeDef * ADCx)3088 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
3089 {
3090 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
3091 }
3092
3093 /**
3094 * @brief Clear flag ADC group regular end of unitary conversion.
3095 * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
3096 * @param ADCx ADC instance
3097 * @retval None
3098 */
LL_ADC_ClearFlag_EOC(ADC_TypeDef * ADCx)3099 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
3100 {
3101 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
3102 }
3103
3104 /**
3105 * @brief Clear flag ADC group regular end of sequence conversions.
3106 * @rmtoll ISR EOSEQ LL_ADC_ClearFlag_EOS
3107 * @param ADCx ADC instance
3108 * @retval None
3109 */
LL_ADC_ClearFlag_EOS(ADC_TypeDef * ADCx)3110 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
3111 {
3112 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
3113 }
3114
3115 /**
3116 * @brief Clear flag ADC group regular overrun.
3117 * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
3118 * @param ADCx ADC instance
3119 * @retval None
3120 */
LL_ADC_ClearFlag_OVR(ADC_TypeDef * ADCx)3121 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
3122 {
3123 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
3124 }
3125
3126 /**
3127 * @brief Clear flag ADC group regular end of sampling phase.
3128 * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
3129 * @param ADCx ADC instance
3130 * @retval None
3131 */
LL_ADC_ClearFlag_EOSMP(ADC_TypeDef * ADCx)3132 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
3133 {
3134 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
3135 }
3136
3137 /**
3138 * @brief Clear flag ADC analog watchdog 1.
3139 * @rmtoll ISR AWD LL_ADC_ClearFlag_AWD1
3140 * @param ADCx ADC instance
3141 * @retval None
3142 */
LL_ADC_ClearFlag_AWD1(ADC_TypeDef * ADCx)3143 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
3144 {
3145 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
3146 }
3147
3148 /**
3149 * @}
3150 */
3151
3152 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
3153 * @{
3154 */
3155
3156 /**
3157 * @brief Enable ADC ready.
3158 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
3159 * @param ADCx ADC instance
3160 * @retval None
3161 */
LL_ADC_EnableIT_ADRDY(ADC_TypeDef * ADCx)3162 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
3163 {
3164 SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
3165 }
3166
3167 /**
3168 * @brief Enable interruption ADC group regular end of unitary conversion.
3169 * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
3170 * @param ADCx ADC instance
3171 * @retval None
3172 */
LL_ADC_EnableIT_EOC(ADC_TypeDef * ADCx)3173 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
3174 {
3175 SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
3176 }
3177
3178 /**
3179 * @brief Enable interruption ADC group regular end of sequence conversions.
3180 * @rmtoll IER EOSEQIE LL_ADC_EnableIT_EOS
3181 * @param ADCx ADC instance
3182 * @retval None
3183 */
LL_ADC_EnableIT_EOS(ADC_TypeDef * ADCx)3184 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
3185 {
3186 SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
3187 }
3188
3189 /**
3190 * @brief Enable ADC group regular interruption overrun.
3191 * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
3192 * @param ADCx ADC instance
3193 * @retval None
3194 */
LL_ADC_EnableIT_OVR(ADC_TypeDef * ADCx)3195 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
3196 {
3197 SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
3198 }
3199
3200 /**
3201 * @brief Enable interruption ADC group regular end of sampling.
3202 * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
3203 * @param ADCx ADC instance
3204 * @retval None
3205 */
LL_ADC_EnableIT_EOSMP(ADC_TypeDef * ADCx)3206 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
3207 {
3208 SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
3209 }
3210
3211 /**
3212 * @brief Enable interruption ADC analog watchdog 1.
3213 * @rmtoll IER AWDIE LL_ADC_EnableIT_AWD1
3214 * @param ADCx ADC instance
3215 * @retval None
3216 */
LL_ADC_EnableIT_AWD1(ADC_TypeDef * ADCx)3217 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
3218 {
3219 SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
3220 }
3221
3222 /**
3223 * @brief Disable interruption ADC ready.
3224 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
3225 * @param ADCx ADC instance
3226 * @retval None
3227 */
LL_ADC_DisableIT_ADRDY(ADC_TypeDef * ADCx)3228 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
3229 {
3230 CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
3231 }
3232
3233 /**
3234 * @brief Disable interruption ADC group regular end of unitary conversion.
3235 * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
3236 * @param ADCx ADC instance
3237 * @retval None
3238 */
LL_ADC_DisableIT_EOC(ADC_TypeDef * ADCx)3239 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
3240 {
3241 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
3242 }
3243
3244 /**
3245 * @brief Disable interruption ADC group regular end of sequence conversions.
3246 * @rmtoll IER EOSEQIE LL_ADC_DisableIT_EOS
3247 * @param ADCx ADC instance
3248 * @retval None
3249 */
LL_ADC_DisableIT_EOS(ADC_TypeDef * ADCx)3250 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
3251 {
3252 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
3253 }
3254
3255 /**
3256 * @brief Disable interruption ADC group regular overrun.
3257 * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
3258 * @param ADCx ADC instance
3259 * @retval None
3260 */
LL_ADC_DisableIT_OVR(ADC_TypeDef * ADCx)3261 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
3262 {
3263 CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
3264 }
3265
3266 /**
3267 * @brief Disable interruption ADC group regular end of sampling.
3268 * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
3269 * @param ADCx ADC instance
3270 * @retval None
3271 */
LL_ADC_DisableIT_EOSMP(ADC_TypeDef * ADCx)3272 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
3273 {
3274 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
3275 }
3276
3277 /**
3278 * @brief Disable interruption ADC analog watchdog 1.
3279 * @rmtoll IER AWDIE LL_ADC_DisableIT_AWD1
3280 * @param ADCx ADC instance
3281 * @retval None
3282 */
LL_ADC_DisableIT_AWD1(ADC_TypeDef * ADCx)3283 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
3284 {
3285 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
3286 }
3287
3288 /**
3289 * @brief Get state of interruption ADC ready
3290 * (0: interrupt disabled, 1: interrupt enabled).
3291 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
3292 * @param ADCx ADC instance
3293 * @retval State of bit (1 or 0).
3294 */
LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef * ADCx)3295 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
3296 {
3297 return (READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY));
3298 }
3299
3300 /**
3301 * @brief Get state of interruption ADC group regular end of unitary conversion
3302 * (0: interrupt disabled, 1: interrupt enabled).
3303 * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
3304 * @param ADCx ADC instance
3305 * @retval State of bit (1 or 0).
3306 */
LL_ADC_IsEnabledIT_EOC(ADC_TypeDef * ADCx)3307 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
3308 {
3309 return (READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC));
3310 }
3311
3312 /**
3313 * @brief Get state of interruption ADC group regular end of sequence conversions
3314 * (0: interrupt disabled, 1: interrupt enabled).
3315 * @rmtoll IER EOSEQIE LL_ADC_IsEnabledIT_EOS
3316 * @param ADCx ADC instance
3317 * @retval State of bit (1 or 0).
3318 */
LL_ADC_IsEnabledIT_EOS(ADC_TypeDef * ADCx)3319 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
3320 {
3321 return (READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS));
3322 }
3323
3324 /**
3325 * @brief Get state of interruption ADC group regular overrun
3326 * (0: interrupt disabled, 1: interrupt enabled).
3327 * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
3328 * @param ADCx ADC instance
3329 * @retval State of bit (1 or 0).
3330 */
LL_ADC_IsEnabledIT_OVR(ADC_TypeDef * ADCx)3331 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
3332 {
3333 return (READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));
3334 }
3335
3336 /**
3337 * @brief Get state of interruption ADC group regular end of sampling
3338 * (0: interrupt disabled, 1: interrupt enabled).
3339 * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
3340 * @param ADCx ADC instance
3341 * @retval State of bit (1 or 0).
3342 */
LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef * ADCx)3343 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
3344 {
3345 return (READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP));
3346 }
3347
3348 /**
3349 * @brief Get state of interruption ADC analog watchdog 1
3350 * (0: interrupt disabled, 1: interrupt enabled).
3351 * @rmtoll IER AWDIE LL_ADC_IsEnabledIT_AWD1
3352 * @param ADCx ADC instance
3353 * @retval State of bit (1 or 0).
3354 */
LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef * ADCx)3355 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
3356 {
3357 return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
3358 }
3359
3360 /**
3361 * @}
3362 */
3363
3364 #if defined(USE_FULL_LL_DRIVER)
3365 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
3366 * @{
3367 */
3368
3369 /* Initialization of some features of ADC common parameters and multimode */
3370 /* Note: On this STM32 series, there is no ADC common initialization */
3371 /* function. */
3372 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
3373
3374 /* De-initialization of ADC instance */
3375 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
3376
3377 /* Initialization of some features of ADC instance */
3378 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
3379 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
3380
3381 /* Initialization of some features of ADC instance and ADC group regular */
3382 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
3383 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
3384
3385 /**
3386 * @}
3387 */
3388 #endif /* USE_FULL_LL_DRIVER */
3389
3390 /**
3391 * @}
3392 */
3393
3394 /**
3395 * @}
3396 */
3397
3398 #endif /* ADC1 */
3399
3400 /**
3401 * @}
3402 */
3403
3404 #ifdef __cplusplus
3405 }
3406 #endif
3407
3408 #endif /* __STM32F0xx_LL_ADC_H */
3409
3410