1 /** 2 ****************************************************************************** 3 * @file stm32f0xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extension module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef __STM32F0xx_HAL_RCC_EX_H 20 #define __STM32F0xx_HAL_RCC_EX_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32f0xx_hal_def.h" 28 29 /** @addtogroup STM32F0xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup RCC 34 * @{ 35 */ 36 37 /** @addtogroup RCC_Private_Macros 38 * @{ 39 */ 40 #if defined(RCC_HSI48_SUPPORT) 41 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ 42 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 43 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 44 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 45 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ 46 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) || \ 47 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)) 48 49 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ 50 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ 51 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \ 52 ((SOURCE) == RCC_SYSCLKSOURCE_HSI48)) 53 54 #define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ 55 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ 56 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) || \ 57 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48)) 58 59 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ 60 ((SOURCE) == RCC_PLLSOURCE_HSI48) || \ 61 ((SOURCE) == RCC_PLLSOURCE_HSE)) 62 63 #define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON)) 64 65 #else 66 67 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ 68 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 69 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 70 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 71 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ 72 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14)) 73 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ 74 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ 75 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) 76 77 #define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ 78 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ 79 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) 80 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ 81 ((SOURCE) == RCC_PLLSOURCE_HSE)) 82 83 #endif /* RCC_HSI48_SUPPORT */ 84 85 #if defined(RCC_CFGR_PLLNODIV) && !defined(RCC_CFGR_MCO_HSI48) 86 87 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ 88 ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ 89 ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ 90 ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ 91 ((SOURCE) == RCC_MCO1SOURCE_HSI) || \ 92 ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ 93 ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \ 94 ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \ 95 ((SOURCE) == RCC_MCO1SOURCE_HSI14)) 96 97 #elif defined(RCC_CFGR_PLLNODIV) && defined(RCC_CFGR_MCO_HSI48) 98 99 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ 100 ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ 101 ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ 102 ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ 103 ((SOURCE) == RCC_MCO1SOURCE_HSI) || \ 104 ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ 105 ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \ 106 ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \ 107 ((SOURCE) == RCC_MCO1SOURCE_HSI14) || \ 108 ((SOURCE) == RCC_MCO1SOURCE_HSI48)) 109 110 #elif !defined(RCC_CFGR_PLLNODIV) && !defined(RCC_CFGR_MCO_HSI48) 111 112 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ 113 ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ 114 ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ 115 ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ 116 ((SOURCE) == RCC_MCO1SOURCE_HSI) || \ 117 ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ 118 ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \ 119 ((SOURCE) == RCC_MCO1SOURCE_HSI14)) 120 121 #endif /* RCC_CFGR_PLLNODIV && !RCC_CFGR_MCO_HSI48 */ 122 123 /** 124 * @} 125 */ 126 127 /** @addtogroup RCC_Exported_Constants 128 * @{ 129 */ 130 #if defined(RCC_HSI48_SUPPORT) 131 132 /** @addtogroup RCC_PLL_Clock_Source 133 * @{ 134 */ 135 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV 136 #define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV 137 138 /** 139 * @} 140 */ 141 142 /** @addtogroup RCC_Interrupt 143 * @{ 144 */ 145 #define RCC_IT_HSI48 RCC_CIR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ 146 /** 147 * @} 148 */ 149 150 /** @addtogroup RCC_Flag 151 * @{ 152 */ 153 #define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5U) | RCC_CR2_HSI48RDY_BitNumber)) 154 /** 155 * @} 156 */ 157 158 /** @addtogroup RCC_System_Clock_Source 159 * @{ 160 */ 161 #define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48 162 /** 163 * @} 164 */ 165 166 /** @addtogroup RCC_System_Clock_Source_Status 167 * @{ 168 */ 169 #define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48 170 /** 171 * @} 172 */ 173 174 #else 175 /** @addtogroup RCC_PLL_Clock_Source 176 * @{ 177 */ 178 179 #if defined(STM32F070xB) || defined(STM32F070x6) || defined(STM32F030xC) 180 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV 181 #else 182 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2 183 #endif 184 185 /** 186 * @} 187 */ 188 189 #endif /* RCC_HSI48_SUPPORT */ 190 191 /** @addtogroup RCC_MCO_Clock_Source 192 * @{ 193 */ 194 195 #if defined(RCC_CFGR_PLLNODIV) 196 197 #define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV) 198 199 #endif /* RCC_CFGR_PLLNODIV */ 200 201 #if defined(RCC_CFGR_MCO_HSI48) 202 203 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO_HSI48 204 205 #endif /* SRCC_CFGR_MCO_HSI48 */ 206 /** 207 * @} 208 */ 209 210 /** 211 * @} 212 */ 213 214 /** 215 * @} 216 */ 217 218 /** @addtogroup RCCEx 219 * @{ 220 */ 221 222 /* Private Constants -------------------------------------------------------------*/ 223 #if defined(CRS) 224 /** @addtogroup RCCEx_Private_Constants 225 * @{ 226 */ 227 228 /* CRS IT Error Mask */ 229 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) 230 231 /* CRS Flag Error Mask */ 232 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) 233 234 /** 235 * @} 236 */ 237 #endif /* CRS */ 238 239 /* Private macro -------------------------------------------------------------*/ 240 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros 241 * @{ 242 */ 243 #if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\ 244 || defined(STM32F030xC) 245 246 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ 247 RCC_PERIPHCLK_RTC)) 248 #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || 249 STM32F030xC */ 250 251 #if defined(STM32F070x6) || defined(STM32F070xB) 252 253 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ 254 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB)) 255 #endif /* STM32F070x6 || STM32F070xB */ 256 257 #if defined(STM32F042x6) || defined(STM32F048xx) 258 259 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ 260 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \ 261 RCC_PERIPHCLK_USB)) 262 #endif /* STM32F042x6 || STM32F048xx */ 263 264 #if defined(STM32F051x8) || defined(STM32F058xx) 265 266 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ 267 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC)) 268 #endif /* STM32F051x8 || STM32F058xx */ 269 270 #if defined(STM32F071xB) 271 272 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ 273 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ 274 RCC_PERIPHCLK_RTC)) 275 #endif /* STM32F071xB */ 276 277 #if defined(STM32F072xB) || defined(STM32F078xx) 278 279 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ 280 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ 281 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB)) 282 #endif /* STM32F072xB || STM32F078xx */ 283 284 #if defined(STM32F091xC) || defined(STM32F098xx) 285 286 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ 287 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ 288 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 )) 289 #endif /* STM32F091xC || STM32F098xx */ 290 291 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) 292 293 #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) || \ 294 ((SOURCE) == RCC_USBCLKSOURCE_PLL)) 295 296 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */ 297 298 #if defined(STM32F070x6) || defined(STM32F070xB) 299 300 #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_NONE) || \ 301 ((SOURCE) == RCC_USBCLKSOURCE_PLL)) 302 303 #endif /* STM32F070x6 || STM32F070xB */ 304 305 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ 306 || defined(STM32F091xC) || defined(STM32F098xx) 307 308 #define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \ 309 ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \ 310 ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \ 311 ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) 312 313 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ 314 /* STM32F091xC || STM32F098xx */ 315 316 #if defined(STM32F091xC) || defined(STM32F098xx) 317 318 #define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \ 319 ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \ 320 ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \ 321 ((SOURCE) == RCC_USART3CLKSOURCE_HSI)) 322 #endif /* STM32F091xC || STM32F098xx */ 323 324 325 #if defined(STM32F042x6) || defined(STM32F048xx)\ 326 || defined(STM32F051x8) || defined(STM32F058xx)\ 327 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ 328 || defined(STM32F091xC) || defined(STM32F098xx) 329 330 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \ 331 ((SOURCE) == RCC_CECCLKSOURCE_LSE)) 332 #endif /* STM32F042x6 || STM32F048xx || */ 333 /* STM32F051x8 || STM32F058xx || */ 334 /* STM32F071xB || STM32F072xB || STM32F078xx || */ 335 /* STM32F091xC || STM32F098xx */ 336 337 #if defined(RCC_CFGR_MCOPRE) 338 339 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ 340 ((DIV) == RCC_MCODIV_4) || ((DIV) == RCC_MCODIV_8) || \ 341 ((DIV) == RCC_MCODIV_16) || ((DIV) == RCC_MCODIV_32) || \ 342 ((DIV) == RCC_MCODIV_64) || ((DIV) == RCC_MCODIV_128)) 343 #else 344 345 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)) 346 347 #endif /* RCC_CFGR_MCOPRE */ 348 349 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ 350 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ 351 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ 352 ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) 353 354 #if defined(CRS) 355 356 #define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) || \ 357 ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) || \ 358 ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB)) 359 #define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) || ((_DIV_) == RCC_CRS_SYNC_DIV2) || \ 360 ((_DIV_) == RCC_CRS_SYNC_DIV4) || ((_DIV_) == RCC_CRS_SYNC_DIV8) || \ 361 ((_DIV_) == RCC_CRS_SYNC_DIV16) || ((_DIV_) == RCC_CRS_SYNC_DIV32) || \ 362 ((_DIV_) == RCC_CRS_SYNC_DIV64) || ((_DIV_) == RCC_CRS_SYNC_DIV128)) 363 #define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) || \ 364 ((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING)) 365 #define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFFU)) 366 #define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFFU)) 367 #define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3FU)) 368 #define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) || \ 369 ((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN)) 370 #endif /* CRS */ 371 /** 372 * @} 373 */ 374 375 /* Exported types ------------------------------------------------------------*/ 376 377 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 378 * @{ 379 */ 380 381 /** 382 * @brief RCC extended clocks structure definition 383 */ 384 #if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\ 385 || defined(STM32F030xC) 386 typedef struct 387 { 388 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 389 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 390 391 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection 392 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 393 394 uint32_t Usart1ClockSelection; /*!< USART1 clock source 395 This parameter can be a value of @ref RCC_USART1_Clock_Source */ 396 397 uint32_t I2c1ClockSelection; /*!< I2C1 clock source 398 This parameter can be a value of @ref RCC_I2C1_Clock_Source */ 399 400 }RCC_PeriphCLKInitTypeDef; 401 #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || 402 STM32F030xC */ 403 404 #if defined(STM32F070x6) || defined(STM32F070xB) 405 typedef struct 406 { 407 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 408 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 409 410 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection 411 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 412 413 uint32_t Usart1ClockSelection; /*!< USART1 clock source 414 This parameter can be a value of @ref RCC_USART1_Clock_Source */ 415 416 uint32_t I2c1ClockSelection; /*!< I2C1 clock source 417 This parameter can be a value of @ref RCC_I2C1_Clock_Source */ 418 419 uint32_t UsbClockSelection; /*!< USB clock source 420 This parameter can be a value of @ref RCCEx_USB_Clock_Source */ 421 422 }RCC_PeriphCLKInitTypeDef; 423 #endif /* STM32F070x6 || STM32F070xB */ 424 425 #if defined(STM32F042x6) || defined(STM32F048xx) 426 typedef struct 427 { 428 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 429 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 430 431 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection 432 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 433 434 uint32_t Usart1ClockSelection; /*!< USART1 clock source 435 This parameter can be a value of @ref RCC_USART1_Clock_Source */ 436 437 uint32_t I2c1ClockSelection; /*!< I2C1 clock source 438 This parameter can be a value of @ref RCC_I2C1_Clock_Source */ 439 440 uint32_t CecClockSelection; /*!< HDMI CEC clock source 441 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ 442 443 uint32_t UsbClockSelection; /*!< USB clock source 444 This parameter can be a value of @ref RCCEx_USB_Clock_Source */ 445 446 }RCC_PeriphCLKInitTypeDef; 447 #endif /* STM32F042x6 || STM32F048xx */ 448 449 #if defined(STM32F051x8) || defined(STM32F058xx) 450 typedef struct 451 { 452 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 453 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 454 455 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection 456 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 457 458 uint32_t Usart1ClockSelection; /*!< USART1 clock source 459 This parameter can be a value of @ref RCC_USART1_Clock_Source */ 460 461 uint32_t I2c1ClockSelection; /*!< I2C1 clock source 462 This parameter can be a value of @ref RCC_I2C1_Clock_Source */ 463 464 uint32_t CecClockSelection; /*!< HDMI CEC clock source 465 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ 466 467 }RCC_PeriphCLKInitTypeDef; 468 #endif /* STM32F051x8 || STM32F058xx */ 469 470 #if defined(STM32F071xB) 471 typedef struct 472 { 473 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 474 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 475 476 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection 477 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 478 479 uint32_t Usart1ClockSelection; /*!< USART1 clock source 480 This parameter can be a value of @ref RCC_USART1_Clock_Source */ 481 482 uint32_t Usart2ClockSelection; /*!< USART2 clock source 483 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ 484 485 uint32_t I2c1ClockSelection; /*!< I2C1 clock source 486 This parameter can be a value of @ref RCC_I2C1_Clock_Source */ 487 488 uint32_t CecClockSelection; /*!< HDMI CEC clock source 489 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ 490 491 }RCC_PeriphCLKInitTypeDef; 492 #endif /* STM32F071xB */ 493 494 #if defined(STM32F072xB) || defined(STM32F078xx) 495 typedef struct 496 { 497 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 498 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 499 500 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection 501 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 502 503 uint32_t Usart1ClockSelection; /*!< USART1 clock source 504 This parameter can be a value of @ref RCC_USART1_Clock_Source */ 505 506 uint32_t Usart2ClockSelection; /*!< USART2 clock source 507 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ 508 509 uint32_t I2c1ClockSelection; /*!< I2C1 clock source 510 This parameter can be a value of @ref RCC_I2C1_Clock_Source */ 511 512 uint32_t CecClockSelection; /*!< HDMI CEC clock source 513 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ 514 515 uint32_t UsbClockSelection; /*!< USB clock source 516 This parameter can be a value of @ref RCCEx_USB_Clock_Source */ 517 518 }RCC_PeriphCLKInitTypeDef; 519 #endif /* STM32F072xB || STM32F078xx */ 520 521 522 #if defined(STM32F091xC) || defined(STM32F098xx) 523 typedef struct 524 { 525 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 526 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 527 528 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection 529 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 530 531 uint32_t Usart1ClockSelection; /*!< USART1 clock source 532 This parameter can be a value of @ref RCC_USART1_Clock_Source */ 533 534 uint32_t Usart2ClockSelection; /*!< USART2 clock source 535 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ 536 537 uint32_t Usart3ClockSelection; /*!< USART3 clock source 538 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ 539 540 uint32_t I2c1ClockSelection; /*!< I2C1 clock source 541 This parameter can be a value of @ref RCC_I2C1_Clock_Source */ 542 543 uint32_t CecClockSelection; /*!< HDMI CEC clock source 544 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ 545 546 }RCC_PeriphCLKInitTypeDef; 547 #endif /* STM32F091xC || STM32F098xx */ 548 549 #if defined(CRS) 550 551 /** 552 * @brief RCC_CRS Init structure definition 553 */ 554 typedef struct 555 { 556 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. 557 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ 558 559 uint32_t Source; /*!< Specifies the SYNC signal source. 560 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ 561 562 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. 563 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ 564 565 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. 566 It can be calculated in using macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) 567 This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ 568 569 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. 570 This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ 571 572 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. 573 This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ 574 575 }RCC_CRSInitTypeDef; 576 577 /** 578 * @brief RCC_CRS Synchronization structure definition 579 */ 580 typedef struct 581 { 582 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. 583 This parameter must be a number between 0 and 0xFFFFU */ 584 585 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. 586 This parameter must be a number between 0 and 0x3FU */ 587 588 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter 589 value latched in the time of the last SYNC event. 590 This parameter must be a number between 0 and 0xFFFFU */ 591 592 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the 593 frequency error counter latched in the time of the last SYNC event. 594 It shows whether the actual frequency is below or above the target. 595 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ 596 597 }RCC_CRSSynchroInfoTypeDef; 598 599 #endif /* CRS */ 600 601 /** 602 * @} 603 */ 604 605 /* Exported constants --------------------------------------------------------*/ 606 607 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 608 * @{ 609 */ 610 611 /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection 612 * @{ 613 */ 614 #if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\ 615 || defined(STM32F030xC) 616 #define RCC_PERIPHCLK_USART1 (0x00000001U) 617 #define RCC_PERIPHCLK_I2C1 (0x00000020U) 618 #define RCC_PERIPHCLK_RTC (0x00010000U) 619 620 #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || 621 STM32F030xC */ 622 623 #if defined(STM32F070x6) || defined(STM32F070xB) 624 #define RCC_PERIPHCLK_USART1 (0x00000001U) 625 #define RCC_PERIPHCLK_I2C1 (0x00000020U) 626 #define RCC_PERIPHCLK_RTC (0x00010000U) 627 #define RCC_PERIPHCLK_USB (0x00020000U) 628 629 #endif /* STM32F070x6 || STM32F070xB */ 630 631 #if defined(STM32F042x6) || defined(STM32F048xx) 632 #define RCC_PERIPHCLK_USART1 (0x00000001U) 633 #define RCC_PERIPHCLK_I2C1 (0x00000020U) 634 #define RCC_PERIPHCLK_CEC (0x00000400U) 635 #define RCC_PERIPHCLK_RTC (0x00010000U) 636 #define RCC_PERIPHCLK_USB (0x00020000U) 637 638 #endif /* STM32F042x6 || STM32F048xx */ 639 640 #if defined(STM32F051x8) || defined(STM32F058xx) 641 #define RCC_PERIPHCLK_USART1 (0x00000001U) 642 #define RCC_PERIPHCLK_I2C1 (0x00000020U) 643 #define RCC_PERIPHCLK_CEC (0x00000400U) 644 #define RCC_PERIPHCLK_RTC (0x00010000U) 645 646 #endif /* STM32F051x8 || STM32F058xx */ 647 648 #if defined(STM32F071xB) 649 #define RCC_PERIPHCLK_USART1 (0x00000001U) 650 #define RCC_PERIPHCLK_USART2 (0x00000002U) 651 #define RCC_PERIPHCLK_I2C1 (0x00000020U) 652 #define RCC_PERIPHCLK_CEC (0x00000400U) 653 #define RCC_PERIPHCLK_RTC (0x00010000U) 654 655 #endif /* STM32F071xB */ 656 657 #if defined(STM32F072xB) || defined(STM32F078xx) 658 #define RCC_PERIPHCLK_USART1 (0x00000001U) 659 #define RCC_PERIPHCLK_USART2 (0x00000002U) 660 #define RCC_PERIPHCLK_I2C1 (0x00000020U) 661 #define RCC_PERIPHCLK_CEC (0x00000400U) 662 #define RCC_PERIPHCLK_RTC (0x00010000U) 663 #define RCC_PERIPHCLK_USB (0x00020000U) 664 665 #endif /* STM32F072xB || STM32F078xx */ 666 667 #if defined(STM32F091xC) || defined(STM32F098xx) 668 #define RCC_PERIPHCLK_USART1 (0x00000001U) 669 #define RCC_PERIPHCLK_USART2 (0x00000002U) 670 #define RCC_PERIPHCLK_I2C1 (0x00000020U) 671 #define RCC_PERIPHCLK_CEC (0x00000400U) 672 #define RCC_PERIPHCLK_RTC (0x00010000U) 673 #define RCC_PERIPHCLK_USART3 (0x00040000U) 674 675 #endif /* STM32F091xC || STM32F098xx */ 676 677 /** 678 * @} 679 */ 680 681 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) 682 683 /** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source 684 * @{ 685 */ 686 #define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48 /*!< HSI48 clock selected as USB clock source */ 687 #define RCC_USBCLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /*!< PLL clock (PLLCLK) selected as USB clock */ 688 689 /** 690 * @} 691 */ 692 693 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */ 694 695 #if defined(STM32F070x6) || defined(STM32F070xB) 696 697 /** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source 698 * @{ 699 */ 700 #define RCC_USBCLKSOURCE_NONE (0x00000000U) /*!< USB clock disabled */ 701 #define RCC_USBCLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /*!< PLL clock (PLLCLK) selected as USB clock */ 702 703 /** 704 * @} 705 */ 706 707 #endif /* STM32F070x6 || STM32F070xB */ 708 709 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ 710 || defined(STM32F091xC) || defined(STM32F098xx) 711 712 /** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source 713 * @{ 714 */ 715 #define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK 716 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK 717 #define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE 718 #define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI 719 720 /** 721 * @} 722 */ 723 724 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ 725 /* STM32F091xC || STM32F098xx */ 726 727 #if defined(STM32F091xC) || defined(STM32F098xx) 728 729 /** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source 730 * @{ 731 */ 732 #define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK 733 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK 734 #define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE 735 #define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI 736 737 /** 738 * @} 739 */ 740 741 #endif /* STM32F091xC || STM32F098xx */ 742 743 744 #if defined(STM32F042x6) || defined(STM32F048xx)\ 745 || defined(STM32F051x8) || defined(STM32F058xx)\ 746 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ 747 || defined(STM32F091xC) || defined(STM32F098xx) 748 749 /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source 750 * @{ 751 */ 752 #define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244 753 #define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE 754 755 /** 756 * @} 757 */ 758 759 #endif /* STM32F042x6 || STM32F048xx || */ 760 /* STM32F051x8 || STM32F058xx || */ 761 /* STM32F071xB || STM32F072xB || STM32F078xx || */ 762 /* STM32F091xC || STM32F098xx */ 763 764 /** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler 765 * @{ 766 */ 767 768 #if defined(RCC_CFGR_MCOPRE) 769 770 #define RCC_MCODIV_1 (0x00000000U) 771 #define RCC_MCODIV_2 (0x10000000U) 772 #define RCC_MCODIV_4 (0x20000000U) 773 #define RCC_MCODIV_8 (0x30000000U) 774 #define RCC_MCODIV_16 (0x40000000U) 775 #define RCC_MCODIV_32 (0x50000000U) 776 #define RCC_MCODIV_64 (0x60000000U) 777 #define RCC_MCODIV_128 (0x70000000U) 778 779 #else 780 781 #define RCC_MCODIV_1 (0x00000000U) 782 783 #endif /* RCC_CFGR_MCOPRE */ 784 785 /** 786 * @} 787 */ 788 789 /** @defgroup RCCEx_LSEDrive_Configuration RCC LSE Drive Configuration 790 * @{ 791 */ 792 793 #define RCC_LSEDRIVE_LOW (0x00000000U) /*!< Xtal mode lower driving capability */ 794 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */ 795 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */ 796 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ 797 798 /** 799 * @} 800 */ 801 802 #if defined(CRS) 803 804 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status 805 * @{ 806 */ 807 #define RCC_CRS_NONE (0x00000000U) 808 #define RCC_CRS_TIMEOUT (0x00000001U) 809 #define RCC_CRS_SYNCOK (0x00000002U) 810 #define RCC_CRS_SYNCWARN (0x00000004U) 811 #define RCC_CRS_SYNCERR (0x00000008U) 812 #define RCC_CRS_SYNCMISS (0x00000010U) 813 #define RCC_CRS_TRIMOVF (0x00000020U) 814 815 /** 816 * @} 817 */ 818 819 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS Synchronization Source 820 * @{ 821 */ 822 #define RCC_CRS_SYNC_SOURCE_GPIO (0x00000000U) /*!< Synchro Signal source GPIO */ 823 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ 824 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ 825 /** 826 * @} 827 */ 828 829 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS Synchronization Divider 830 * @{ 831 */ 832 #define RCC_CRS_SYNC_DIV1 (0x00000000U) /*!< Synchro Signal not divided (default) */ 833 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ 834 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ 835 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ 836 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ 837 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ 838 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ 839 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ 840 /** 841 * @} 842 */ 843 844 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS Synchronization Polarity 845 * @{ 846 */ 847 #define RCC_CRS_SYNC_POLARITY_RISING (0x00000000U) /*!< Synchro Active on rising edge (default) */ 848 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ 849 /** 850 * @} 851 */ 852 853 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS Default Reload Value 854 * @{ 855 */ 856 #define RCC_CRS_RELOADVALUE_DEFAULT (0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds 857 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ 858 /** 859 * @} 860 */ 861 862 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS Default Error Limit Value 863 * @{ 864 */ 865 #define RCC_CRS_ERRORLIMIT_DEFAULT (0x00000022U) /*!< Default Frequency error limit */ 866 /** 867 * @} 868 */ 869 870 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS Default HSI48 Calibration vakye 871 * @{ 872 */ 873 #define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval. 874 The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value 875 corresponds to a higher output frequency */ 876 /** 877 * @} 878 */ 879 880 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS Frequency Error Direction 881 * @{ 882 */ 883 #define RCC_CRS_FREQERRORDIR_UP (0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */ 884 #define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ 885 /** 886 * @} 887 */ 888 889 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources 890 * @{ 891 */ 892 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ 893 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ 894 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ 895 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ 896 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ 897 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ 898 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ 899 900 /** 901 * @} 902 */ 903 904 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags 905 * @{ 906 */ 907 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ 908 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ 909 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ 910 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ 911 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ 912 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ 913 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ 914 915 /** 916 * @} 917 */ 918 919 #endif /* CRS */ 920 921 /** 922 * @} 923 */ 924 925 /* Exported macros ------------------------------------------------------------*/ 926 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 927 * @{ 928 */ 929 930 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable 931 * @brief Enables or disables the AHB1 peripheral clock. 932 * @note After reset, the peripheral clock (used for registers read/write access) 933 * is disabled and the application software has to enable this clock before 934 * using it. 935 * @{ 936 */ 937 #if defined(GPIOD) 938 939 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 940 __IO uint32_t tmpreg; \ 941 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ 942 /* Delay after an RCC peripheral clock enabling */ \ 943 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ 944 UNUSED(tmpreg); \ 945 } while(0U) 946 947 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN)) 948 949 #endif /* GPIOD */ 950 951 #if defined(GPIOE) 952 953 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 954 __IO uint32_t tmpreg; \ 955 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ 956 /* Delay after an RCC peripheral clock enabling */ \ 957 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ 958 UNUSED(tmpreg); \ 959 } while(0U) 960 961 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) 962 963 #endif /* GPIOE */ 964 965 #if defined(STM32F042x6) || defined(STM32F048xx)\ 966 || defined(STM32F051x8) || defined(STM32F058xx)\ 967 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ 968 || defined(STM32F091xC) || defined(STM32F098xx) 969 970 #define __HAL_RCC_TSC_CLK_ENABLE() do { \ 971 __IO uint32_t tmpreg; \ 972 SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ 973 /* Delay after an RCC peripheral clock enabling */ \ 974 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ 975 UNUSED(tmpreg); \ 976 } while(0U) 977 978 #define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN)) 979 980 #endif /* STM32F042x6 || STM32F048xx || */ 981 /* STM32F051x8 || STM32F058xx || */ 982 /* STM32F071xB || STM32F072xB || STM32F078xx || */ 983 /* STM32F091xC || STM32F098xx */ 984 985 #if defined(STM32F091xC) || defined(STM32F098xx) 986 987 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ 988 __IO uint32_t tmpreg; \ 989 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ 990 /* Delay after an RCC peripheral clock enabling */ \ 991 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ 992 UNUSED(tmpreg); \ 993 } while(0U) 994 995 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) 996 997 #endif /* STM32F091xC || STM32F098xx */ 998 999 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 1000 * @note After reset, the peripheral clock (used for registers read/write access) 1001 * is disabled and the application software has to enable this clock before 1002 * using it. 1003 */ 1004 #if defined(STM32F030x8)\ 1005 || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ 1006 || defined(STM32F051x8) || defined(STM32F058xx)\ 1007 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ 1008 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) 1009 1010 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 1011 __IO uint32_t tmpreg; \ 1012 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ 1013 /* Delay after an RCC peripheral clock enabling */ \ 1014 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ 1015 UNUSED(tmpreg); \ 1016 } while(0U) 1017 1018 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) 1019 1020 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ 1021 /* STM32F051x8 || STM32F058xx || STM32F070x6 || */ 1022 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ 1023 /* STM32F091xC || STM32F098xx || STM32F030xC */ 1024 1025 #if defined(STM32F030x8)\ 1026 || defined(STM32F042x6) || defined(STM32F048xx)\ 1027 || defined(STM32F051x8) || defined(STM32F058xx)\ 1028 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ 1029 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) 1030 1031 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 1032 __IO uint32_t tmpreg; \ 1033 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ 1034 /* Delay after an RCC peripheral clock enabling */ \ 1035 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ 1036 UNUSED(tmpreg); \ 1037 } while(0U) 1038 1039 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) 1040 1041 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ 1042 /* STM32F051x8 || STM32F058xx || */ 1043 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ 1044 /* STM32F091xC || STM32F098xx || STM32F030xC */ 1045 1046 #if defined(STM32F031x6) || defined(STM32F038xx)\ 1047 || defined(STM32F042x6) || defined(STM32F048xx)\ 1048 || defined(STM32F051x8) || defined(STM32F058xx)\ 1049 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ 1050 || defined(STM32F091xC) || defined(STM32F098xx) 1051 1052 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 1053 __IO uint32_t tmpreg; \ 1054 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 1055 /* Delay after an RCC peripheral clock enabling */ \ 1056 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 1057 UNUSED(tmpreg); \ 1058 } while(0U) 1059 1060 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 1061 1062 #endif /* STM32F031x6 || STM32F038xx || */ 1063 /* STM32F042x6 || STM32F048xx || */ 1064 /* STM32F051x8 || STM32F058xx || */ 1065 /* STM32F071xB || STM32F072xB || STM32F078xx || */ 1066 /* STM32F091xC || STM32F098xx */ 1067 1068 #if defined(STM32F030x8) \ 1069 || defined(STM32F051x8) || defined(STM32F058xx)\ 1070 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ 1071 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) 1072 1073 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 1074 __IO uint32_t tmpreg; \ 1075 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 1076 /* Delay after an RCC peripheral clock enabling */ \ 1077 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 1078 UNUSED(tmpreg); \ 1079 } while(0U) 1080 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 1081 __IO uint32_t tmpreg; \ 1082 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ 1083 /* Delay after an RCC peripheral clock enabling */ \ 1084 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ 1085 UNUSED(tmpreg); \ 1086 } while(0U) 1087 1088 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 1089 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) 1090 1091 #endif /* STM32F030x8 || */ 1092 /* STM32F051x8 || STM32F058xx || */ 1093 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ 1094 /* STM32F091xC || STM32F098xx || STM32F030xC */ 1095 1096 #if defined(STM32F051x8) || defined(STM32F058xx)\ 1097 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ 1098 || defined(STM32F091xC) || defined(STM32F098xx) 1099 1100 #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ 1101 __IO uint32_t tmpreg; \ 1102 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 1103 /* Delay after an RCC peripheral clock enabling */ \ 1104 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 1105 UNUSED(tmpreg); \ 1106 } while(0U) 1107 1108 #define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 1109 1110 #endif /* STM32F051x8 || STM32F058xx || */ 1111 /* STM32F071xB || STM32F072xB || STM32F078xx || */ 1112 /* STM32F091xC || STM32F098xx */ 1113 1114 #if defined(STM32F042x6) || defined(STM32F048xx)\ 1115 || defined(STM32F051x8) || defined(STM32F058xx)\ 1116 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ 1117 || defined(STM32F091xC) || defined(STM32F098xx) 1118 1119 #define __HAL_RCC_CEC_CLK_ENABLE() do { \ 1120 __IO uint32_t tmpreg; \ 1121 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ 1122 /* Delay after an RCC peripheral clock enabling */ \ 1123 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ 1124 UNUSED(tmpreg); \ 1125 } while(0U) 1126 1127 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) 1128 1129 #endif /* STM32F042x6 || STM32F048xx || */ 1130 /* STM32F051x8 || STM32F058xx || */ 1131 /* STM32F071xB || STM32F072xB || STM32F078xx || */ 1132 /* STM32F091xC || STM32F098xx */ 1133 1134 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ 1135 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) 1136 1137 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 1138 __IO uint32_t tmpreg; \ 1139 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 1140 /* Delay after an RCC peripheral clock enabling */ \ 1141 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 1142 UNUSED(tmpreg); \ 1143 } while(0U) 1144 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 1145 __IO uint32_t tmpreg; \ 1146 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 1147 /* Delay after an RCC peripheral clock enabling */ \ 1148 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 1149 UNUSED(tmpreg); \ 1150 } while(0U) 1151 #define __HAL_RCC_USART4_CLK_ENABLE() do { \ 1152 __IO uint32_t tmpreg; \ 1153 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\ 1154 /* Delay after an RCC peripheral clock enabling */ \ 1155 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\ 1156 UNUSED(tmpreg); \ 1157 } while(0U) 1158 1159 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 1160 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) 1161 #define __HAL_RCC_USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN)) 1162 1163 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ 1164 /* STM32F091xC || STM32F098xx || STM32F030xC */ 1165 1166 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ 1167 || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) 1168 1169 #define __HAL_RCC_USB_CLK_ENABLE() do { \ 1170 __IO uint32_t tmpreg; \ 1171 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ 1172 /* Delay after an RCC peripheral clock enabling */ \ 1173 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ 1174 UNUSED(tmpreg); \ 1175 } while(0U) 1176 1177 #define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) 1178 1179 #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */ 1180 /* STM32F072xB || STM32F078xx || STM32F070xB */ 1181 1182 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\ 1183 || defined(STM32F091xC) || defined(STM32F098xx) 1184 1185 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 1186 __IO uint32_t tmpreg; \ 1187 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\ 1188 /* Delay after an RCC peripheral clock enabling */ \ 1189 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\ 1190 UNUSED(tmpreg); \ 1191 } while(0U) 1192 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN)) 1193 1194 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */ 1195 /* STM32F091xC || STM32F098xx */ 1196 1197 #if defined(CRS) 1198 1199 #define __HAL_RCC_CRS_CLK_ENABLE() do { \ 1200 __IO uint32_t tmpreg; \ 1201 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\ 1202 /* Delay after an RCC peripheral clock enabling */ \ 1203 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\ 1204 UNUSED(tmpreg); \ 1205 } while(0U) 1206 1207 #define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN)) 1208 1209 #endif /* CRS */ 1210 1211 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) 1212 1213 #define __HAL_RCC_USART5_CLK_ENABLE() do { \ 1214 __IO uint32_t tmpreg; \ 1215 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\ 1216 /* Delay after an RCC peripheral clock enabling */ \ 1217 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\ 1218 UNUSED(tmpreg); \ 1219 } while(0U) 1220 1221 #define __HAL_RCC_USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN)) 1222 1223 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */ 1224 1225 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock. 1226 * @note After reset, the peripheral clock (used for registers read/write access) 1227 * is disabled and the application software has to enable this clock before 1228 * using it. 1229 */ 1230 #if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ 1231 || defined(STM32F051x8) || defined(STM32F058xx)\ 1232 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ 1233 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) 1234 1235 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ 1236 __IO uint32_t tmpreg; \ 1237 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ 1238 /* Delay after an RCC peripheral clock enabling */ \ 1239 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ 1240 UNUSED(tmpreg); \ 1241 } while(0U) 1242 1243 #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) 1244 1245 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ 1246 /* STM32F051x8 || STM32F058xx || */ 1247 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ 1248 /* STM32F091xC || STM32F098xx || STM32F030xC */ 1249 1250 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) 1251 1252 #define __HAL_RCC_USART6_CLK_ENABLE() do { \ 1253 __IO uint32_t tmpreg; \ 1254 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ 1255 /* Delay after an RCC peripheral clock enabling */ \ 1256 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ 1257 UNUSED(tmpreg); \ 1258 } while(0U) 1259 1260 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) 1261 1262 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */ 1263 1264 #if defined(STM32F091xC) || defined(STM32F098xx) 1265 1266 #define __HAL_RCC_USART7_CLK_ENABLE() do { \ 1267 __IO uint32_t tmpreg; \ 1268 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\ 1269 /* Delay after an RCC peripheral clock enabling */ \ 1270 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\ 1271 UNUSED(tmpreg); \ 1272 } while(0U) 1273 #define __HAL_RCC_USART8_CLK_ENABLE() do { \ 1274 __IO uint32_t tmpreg; \ 1275 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\ 1276 /* Delay after an RCC peripheral clock enabling */ \ 1277 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\ 1278 UNUSED(tmpreg); \ 1279 } while(0U) 1280 1281 #define __HAL_RCC_USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN)) 1282 #define __HAL_RCC_USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN)) 1283 1284 #endif /* STM32F091xC || STM32F098xx */ 1285 1286 /** 1287 * @} 1288 */ 1289 1290 1291 /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset 1292 * @brief Forces or releases peripheral reset. 1293 * @{ 1294 */ 1295 1296 /** @brief Force or release AHB peripheral reset. 1297 */ 1298 #if defined(GPIOD) 1299 1300 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST)) 1301 1302 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST)) 1303 1304 #endif /* GPIOD */ 1305 1306 #if defined(GPIOE) 1307 1308 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST)) 1309 1310 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST)) 1311 1312 #endif /* GPIOE */ 1313 1314 #if defined(STM32F042x6) || defined(STM32F048xx)\ 1315 || defined(STM32F051x8) || defined(STM32F058xx)\ 1316 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ 1317 || defined(STM32F091xC) || defined(STM32F098xx) 1318 1319 #define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST)) 1320 1321 #define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST)) 1322 1323 #endif /* STM32F042x6 || STM32F048xx || */ 1324 /* STM32F051x8 || STM32F058xx || */ 1325 /* STM32F071xB || STM32F072xB || STM32F078xx || */ 1326 /* STM32F091xC || STM32F098xx */ 1327 1328 /** @brief Force or release APB1 peripheral reset. 1329 */ 1330 #if defined(STM32F030x8) \ 1331 || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ 1332 || defined(STM32F051x8) || defined(STM32F058xx)\ 1333 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ 1334 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) 1335 1336 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) 1337 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) 1338 1339 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) 1340 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) 1341 1342 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ 1343 /* STM32F051x8 || STM32F058xx || */ 1344 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ 1345 /* STM32F091xC || STM32F098xx || STM32F030xC */ 1346 1347 #if defined(STM32F031x6) || defined(STM32F038xx)\ 1348 || defined(STM32F042x6) || defined(STM32F048xx)\ 1349 || defined(STM32F051x8) || defined(STM32F058xx)\ 1350 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ 1351 || defined(STM32F091xC) || defined(STM32F098xx) 1352 1353 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 1354 1355 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 1356 1357 #endif /* STM32F031x6 || STM32F038xx || */ 1358 /* STM32F042x6 || STM32F048xx || */ 1359 /* STM32F051x8 || STM32F058xx || */ 1360 /* STM32F071xB || STM32F072xB || STM32F078xx || */ 1361 /* STM32F091xC || STM32F098xx */ 1362 1363 #if defined(STM32F030x8) \ 1364 || defined(STM32F051x8) || defined(STM32F058xx)\ 1365 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ 1366 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) 1367 1368 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 1369 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) 1370 1371 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 1372 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) 1373 1374 #endif /* STM32F030x8 || */ 1375 /* STM32F051x8 || STM32F058xx || */ 1376 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ 1377 /* STM32F091xC || STM32F098xx || STM32F030xC */ 1378 1379 #if defined(STM32F051x8) || defined(STM32F058xx)\ 1380 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ 1381 || defined(STM32F091xC) || defined(STM32F098xx) 1382 1383 #define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 1384 1385 #define __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 1386 1387 #endif /* STM32F051x8 || STM32F058xx || */ 1388 /* STM32F071xB || STM32F072xB || STM32F078xx || */ 1389 /* STM32F091xC || STM32F098xx */ 1390 1391 #if defined(STM32F042x6) || defined(STM32F048xx)\ 1392 || defined(STM32F051x8) || defined(STM32F058xx)\ 1393 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ 1394 || defined(STM32F091xC) || defined(STM32F098xx) 1395 1396 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) 1397 1398 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) 1399 1400 #endif /* STM32F042x6 || STM32F048xx || */ 1401 /* STM32F051x8 || STM32F058xx || */ 1402 /* STM32F071xB || STM32F072xB || STM32F078xx || */ 1403 /* STM32F091xC || STM32F098xx */ 1404 1405 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ 1406 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) 1407 1408 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 1409 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) 1410 #define __HAL_RCC_USART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART4RST)) 1411 1412 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 1413 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) 1414 #define __HAL_RCC_USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST)) 1415 1416 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ 1417 /* STM32F091xC || STM32F098xx || STM32F030xC */ 1418 1419 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ 1420 || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) 1421 1422 #define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) 1423 1424 #define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) 1425 1426 #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */ 1427 /* STM32F072xB || STM32F078xx || STM32F070xB */ 1428 1429 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\ 1430 || defined(STM32F091xC) || defined(STM32F098xx) 1431 1432 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST)) 1433 1434 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST)) 1435 1436 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */ 1437 /* STM32F091xC || STM32F098xx */ 1438 1439 #if defined(CRS) 1440 1441 #define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST)) 1442 1443 #define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST)) 1444 1445 #endif /* CRS */ 1446 1447 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) 1448 1449 #define __HAL_RCC_USART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART5RST)) 1450 1451 #define __HAL_RCC_USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST)) 1452 1453 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */ 1454 1455 1456 /** @brief Force or release APB2 peripheral reset. 1457 */ 1458 #if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ 1459 || defined(STM32F051x8) || defined(STM32F058xx)\ 1460 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ 1461 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) 1462 1463 #define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST)) 1464 1465 #define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST)) 1466 1467 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ 1468 /* STM32F051x8 || STM32F058xx || */ 1469 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ 1470 /* STM32F091xC || STM32F098xx || STM32F030xC */ 1471 1472 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) 1473 1474 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) 1475 1476 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST)) 1477 1478 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */ 1479 1480 #if defined(STM32F091xC) || defined(STM32F098xx) 1481 1482 #define __HAL_RCC_USART7_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART7RST)) 1483 #define __HAL_RCC_USART8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART8RST)) 1484 1485 #define __HAL_RCC_USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST)) 1486 #define __HAL_RCC_USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST)) 1487 1488 #endif /* STM32F091xC || STM32F098xx */ 1489 1490 /** 1491 * @} 1492 */ 1493 1494 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status 1495 * @brief Get the enable or disable status of peripheral clock. 1496 * @note After reset, the peripheral clock (used for registers read/write access) 1497 * is disabled and the application software has to enable this clock before 1498 * using it. 1499 * @{ 1500 */ 1501 /** @brief AHB Peripheral Clock Enable Disable Status 1502 */ 1503 #if defined(GPIOD) 1504 1505 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET) 1506 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET) 1507 1508 #endif /* GPIOD */ 1509 1510 #if defined(GPIOE) 1511 1512 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET) 1513 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET) 1514 1515 #endif /* GPIOE */ 1516 1517 #if defined(STM32F042x6) || defined(STM32F048xx)\ 1518 || defined(STM32F051x8) || defined(STM32F058xx)\ 1519 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ 1520 || defined(STM32F091xC) || defined(STM32F098xx) 1521 1522 #define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET) 1523 #define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET) 1524 1525 #endif /* STM32F042x6 || STM32F048xx || */ 1526 /* STM32F051x8 || STM32F058xx || */ 1527 /* STM32F071xB || STM32F072xB || STM32F078xx || */ 1528 /* STM32F091xC || STM32F098xx */ 1529 1530 #if defined(STM32F091xC) || defined(STM32F098xx) 1531 1532 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET) 1533 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET) 1534 1535 #endif /* STM32F091xC || STM32F098xx */ 1536 1537 /** @brief APB1 Peripheral Clock Enable Disable Status 1538 */ 1539 #if defined(STM32F030x8)\ 1540 || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ 1541 || defined(STM32F051x8) || defined(STM32F058xx)\ 1542 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ 1543 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) 1544 1545 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) 1546 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) 1547 1548 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ 1549 /* STM32F051x8 || STM32F058xx || STM32F070x6 || */ 1550 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ 1551 /* STM32F091xC || STM32F098xx || STM32F030xC */ 1552 1553 #if defined(STM32F030x8)\ 1554 || defined(STM32F042x6) || defined(STM32F048xx)\ 1555 || defined(STM32F051x8) || defined(STM32F058xx)\ 1556 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ 1557 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) 1558 1559 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) 1560 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) 1561 1562 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ 1563 /* STM32F051x8 || STM32F058xx || */ 1564 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ 1565 /* STM32F091xC || STM32F098xx || STM32F030xC */ 1566 1567 #if defined(STM32F031x6) || defined(STM32F038xx)\ 1568 || defined(STM32F042x6) || defined(STM32F048xx)\ 1569 || defined(STM32F051x8) || defined(STM32F058xx)\ 1570 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ 1571 || defined(STM32F091xC) || defined(STM32F098xx) 1572 1573 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 1574 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 1575 1576 #endif /* STM32F031x6 || STM32F038xx || */ 1577 /* STM32F042x6 || STM32F048xx || */ 1578 /* STM32F051x8 || STM32F058xx || */ 1579 /* STM32F071xB || STM32F072xB || STM32F078xx || */ 1580 /* STM32F091xC || STM32F098xx */ 1581 1582 #if defined(STM32F030x8) \ 1583 || defined(STM32F051x8) || defined(STM32F058xx)\ 1584 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ 1585 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) 1586 1587 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 1588 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) 1589 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 1590 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) 1591 1592 #endif /* STM32F030x8 || */ 1593 /* STM32F051x8 || STM32F058xx || */ 1594 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ 1595 /* STM32F091xC || STM32F098xx || STM32F030xC */ 1596 1597 #if defined(STM32F051x8) || defined(STM32F058xx)\ 1598 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ 1599 || defined(STM32F091xC) || defined(STM32F098xx) 1600 1601 #define __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET) 1602 #define __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET) 1603 1604 #endif /* STM32F051x8 || STM32F058xx || */ 1605 /* STM32F071xB || STM32F072xB || STM32F078xx || */ 1606 /* STM32F091xC || STM32F098xx */ 1607 1608 #if defined(STM32F042x6) || defined(STM32F048xx)\ 1609 || defined(STM32F051x8) || defined(STM32F058xx)\ 1610 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ 1611 || defined(STM32F091xC) || defined(STM32F098xx) 1612 1613 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) 1614 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) 1615 1616 #endif /* STM32F042x6 || STM32F048xx || */ 1617 /* STM32F051x8 || STM32F058xx || */ 1618 /* STM32F071xB || STM32F072xB || STM32F078xx || */ 1619 /* STM32F091xC || STM32F098xx */ 1620 1621 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ 1622 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) 1623 1624 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 1625 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 1626 #define __HAL_RCC_USART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) != RESET) 1627 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 1628 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 1629 #define __HAL_RCC_USART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) == RESET) 1630 1631 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ 1632 /* STM32F091xC || STM32F098xx || STM32F030xC */ 1633 1634 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ 1635 || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) 1636 1637 #define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET) 1638 #define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET) 1639 1640 #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */ 1641 /* STM32F072xB || STM32F078xx || STM32F070xB */ 1642 1643 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\ 1644 || defined(STM32F091xC) || defined(STM32F098xx) 1645 1646 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) 1647 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) 1648 1649 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */ 1650 /* STM32F091xC || STM32F098xx */ 1651 1652 #if defined(CRS) 1653 1654 #define __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) != RESET) 1655 #define __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) == RESET) 1656 1657 #endif /* CRS */ 1658 1659 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) 1660 1661 #define __HAL_RCC_USART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) != RESET) 1662 #define __HAL_RCC_USART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) == RESET) 1663 1664 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */ 1665 1666 /** @brief APB1 Peripheral Clock Enable Disable Status 1667 */ 1668 #if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ 1669 || defined(STM32F051x8) || defined(STM32F058xx)\ 1670 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ 1671 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) 1672 1673 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET) 1674 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET) 1675 1676 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ 1677 /* STM32F051x8 || STM32F058xx || */ 1678 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ 1679 /* STM32F091xC || STM32F098xx || STM32F030xC */ 1680 1681 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) 1682 1683 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET) 1684 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET) 1685 1686 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */ 1687 1688 #if defined(STM32F091xC) || defined(STM32F098xx) 1689 1690 #define __HAL_RCC_USART7_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) != RESET) 1691 #define __HAL_RCC_USART8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) != RESET) 1692 #define __HAL_RCC_USART7_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) == RESET) 1693 #define __HAL_RCC_USART8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) == RESET) 1694 1695 #endif /* STM32F091xC || STM32F098xx */ 1696 /** 1697 * @} 1698 */ 1699 1700 1701 /** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable 1702 * @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48). 1703 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. 1704 * @note HSI48 can not be stopped if it is used as system clock source. In this case, 1705 * you have to select another source of the system clock then stop the HSI14. 1706 * @note After enabling the HSI48 with __HAL_RCC_HSI48_ENABLE(), the application software 1707 * should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be 1708 * used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used. 1709 * @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI48 oscillator 1710 * clock cycles. 1711 * @{ 1712 */ 1713 #if defined(RCC_HSI48_SUPPORT) 1714 1715 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON) 1716 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON) 1717 1718 /** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state. 1719 * @retval The clock source can be one of the following values: 1720 * @arg @ref RCC_HSI48_ON HSI48 enabled 1721 * @arg @ref RCC_HSI48_OFF HSI48 disabled 1722 */ 1723 #define __HAL_RCC_GET_HSI48_STATE() \ 1724 (((uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF) 1725 1726 #endif /* RCC_HSI48_SUPPORT */ 1727 1728 /** 1729 * @} 1730 */ 1731 1732 /** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config 1733 * @{ 1734 */ 1735 #if defined(STM32F042x6) || defined(STM32F048xx)\ 1736 || defined(STM32F072xB) || defined(STM32F078xx)\ 1737 || defined(STM32F070x6) || defined(STM32F070xB) 1738 1739 /** @brief Macro to configure the USB clock (USBCLK). 1740 * @param __USBCLKSOURCE__ specifies the USB clock source. 1741 * This parameter can be one of the following values: 1742 @if STM32F070xB 1743 @elseif STM32F070x6 1744 @else 1745 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock 1746 @endif 1747 * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock 1748 */ 1749 #define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \ 1750 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, (uint32_t)(__USBCLKSOURCE__)) 1751 1752 /** @brief Macro to get the USB clock source. 1753 * @retval The clock source can be one of the following values: 1754 @if STM32F070xB 1755 @elseif STM32F070x6 1756 @else 1757 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock 1758 @endif 1759 * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock 1760 */ 1761 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW))) 1762 1763 #endif /* STM32F042x6 || STM32F048xx || */ 1764 /* STM32F072xB || STM32F078xx || */ 1765 /* STM32F070x6 || STM32F070xB */ 1766 1767 #if defined(STM32F042x6) || defined(STM32F048xx)\ 1768 || defined(STM32F051x8) || defined(STM32F058xx)\ 1769 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ 1770 || defined(STM32F091xC) || defined(STM32F098xx) 1771 1772 /** @brief Macro to configure the CEC clock. 1773 * @param __CECCLKSOURCE__ specifies the CEC clock source. 1774 * This parameter can be one of the following values: 1775 * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock 1776 * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock 1777 */ 1778 #define __HAL_RCC_CEC_CONFIG(__CECCLKSOURCE__) \ 1779 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSOURCE__)) 1780 1781 /** @brief Macro to get the HDMI CEC clock source. 1782 * @retval The clock source can be one of the following values: 1783 * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock 1784 * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock 1785 */ 1786 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW))) 1787 1788 #endif /* STM32F042x6 || STM32F048xx || */ 1789 /* STM32F051x8 || STM32F058xx || */ 1790 /* STM32F071xB || STM32F072xB || STM32F078xx || */ 1791 /* STM32F091xC || defined(STM32F098xx) */ 1792 1793 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ 1794 || defined(STM32F091xC) || defined(STM32F098xx) 1795 /** @brief Macro to configure the USART2 clock (USART2CLK). 1796 * @param __USART2CLKSOURCE__ specifies the USART2 clock source. 1797 * This parameter can be one of the following values: 1798 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 1799 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 1800 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 1801 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 1802 */ 1803 #define __HAL_RCC_USART2_CONFIG(__USART2CLKSOURCE__) \ 1804 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSOURCE__)) 1805 1806 /** @brief Macro to get the USART2 clock source. 1807 * @retval The clock source can be one of the following values: 1808 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 1809 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 1810 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 1811 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 1812 */ 1813 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW))) 1814 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx*/ 1815 1816 #if defined(STM32F091xC) || defined(STM32F098xx) 1817 /** @brief Macro to configure the USART3 clock (USART3CLK). 1818 * @param __USART3CLKSOURCE__ specifies the USART3 clock source. 1819 * This parameter can be one of the following values: 1820 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock 1821 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 1822 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock 1823 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 1824 */ 1825 #define __HAL_RCC_USART3_CONFIG(__USART3CLKSOURCE__) \ 1826 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSOURCE__)) 1827 1828 /** @brief Macro to get the USART3 clock source. 1829 * @retval The clock source can be one of the following values: 1830 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock 1831 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 1832 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock 1833 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 1834 */ 1835 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW))) 1836 1837 #endif /* STM32F091xC || STM32F098xx */ 1838 /** 1839 * @} 1840 */ 1841 1842 /** @defgroup RCCEx_LSE_Configuration LSE Drive Configuration 1843 * @{ 1844 */ 1845 1846 /** 1847 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. 1848 * @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability. 1849 * This parameter can be one of the following values: 1850 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. 1851 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. 1852 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. 1853 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. 1854 * @retval None 1855 */ 1856 #define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->BDCR,\ 1857 RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) )) 1858 1859 /** 1860 * @} 1861 */ 1862 1863 #if defined(CRS) 1864 1865 /** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag 1866 * @{ 1867 */ 1868 /* Interrupt & Flag management */ 1869 1870 /** 1871 * @brief Enable the specified CRS interrupts. 1872 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. 1873 * This parameter can be any combination of the following values: 1874 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1875 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1876 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1877 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1878 * @retval None 1879 */ 1880 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) 1881 1882 /** 1883 * @brief Disable the specified CRS interrupts. 1884 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. 1885 * This parameter can be any combination of the following values: 1886 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1887 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1888 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1889 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1890 * @retval None 1891 */ 1892 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) 1893 1894 /** @brief Check whether the CRS interrupt has occurred or not. 1895 * @param __INTERRUPT__ specifies the CRS interrupt source to check. 1896 * This parameter can be one of the following values: 1897 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1898 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1899 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1900 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1901 * @retval The new state of __INTERRUPT__ (SET or RESET). 1902 */ 1903 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET) 1904 1905 /** @brief Clear the CRS interrupt pending bits 1906 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1907 * This parameter can be any combination of the following values: 1908 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1909 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1910 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1911 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1912 * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt 1913 * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt 1914 * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt 1915 */ 1916 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ 1917 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \ 1918 { \ 1919 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ 1920 } \ 1921 else \ 1922 { \ 1923 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ 1924 } \ 1925 } while(0U) 1926 1927 /** 1928 * @brief Check whether the specified CRS flag is set or not. 1929 * @param __FLAG__ specifies the flag to check. 1930 * This parameter can be one of the following values: 1931 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 1932 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 1933 * @arg @ref RCC_CRS_FLAG_ERR Error 1934 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 1935 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 1936 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 1937 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 1938 * @retval The new state of _FLAG_ (TRUE or FALSE). 1939 */ 1940 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) 1941 1942 /** 1943 * @brief Clear the CRS specified FLAG. 1944 * @param __FLAG__ specifies the flag to clear. 1945 * This parameter can be one of the following values: 1946 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 1947 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 1948 * @arg @ref RCC_CRS_FLAG_ERR Error 1949 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 1950 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 1951 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 1952 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 1953 * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR 1954 * @retval None 1955 */ 1956 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ 1957 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \ 1958 { \ 1959 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ 1960 } \ 1961 else \ 1962 { \ 1963 WRITE_REG(CRS->ICR, (__FLAG__)); \ 1964 } \ 1965 } while(0U) 1966 1967 /** 1968 * @} 1969 */ 1970 1971 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features 1972 * @{ 1973 */ 1974 /** 1975 * @brief Enable the oscillator clock for frequency error counter. 1976 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. 1977 * @retval None 1978 */ 1979 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) 1980 1981 /** 1982 * @brief Disable the oscillator clock for frequency error counter. 1983 * @retval None 1984 */ 1985 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) 1986 1987 /** 1988 * @brief Enable the automatic hardware adjustment of TRIM bits. 1989 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. 1990 * @retval None 1991 */ 1992 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 1993 1994 /** 1995 * @brief Disable the automatic hardware adjustment of TRIM bits. 1996 * @retval None 1997 */ 1998 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 1999 2000 /** 2001 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies 2002 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency 2003 * of the synchronization source after prescaling. It is then decreased by one in order to 2004 * reach the expected synchronization on the zero value. The formula is the following: 2005 * RELOAD = (fTARGET / fSYNC) -1 2006 * @param __FTARGET__ Target frequency (value in Hz) 2007 * @param __FSYNC__ Synchronization signal frequency (value in Hz) 2008 * @retval None 2009 */ 2010 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) 2011 2012 /** 2013 * @} 2014 */ 2015 2016 #endif /* CRS */ 2017 2018 /** 2019 * @} 2020 */ 2021 2022 /* Exported functions --------------------------------------------------------*/ 2023 /** @addtogroup RCCEx_Exported_Functions 2024 * @{ 2025 */ 2026 2027 /** @addtogroup RCCEx_Exported_Functions_Group1 2028 * @{ 2029 */ 2030 2031 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 2032 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 2033 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 2034 2035 /** 2036 * @} 2037 */ 2038 2039 #if defined(CRS) 2040 2041 /** @addtogroup RCCEx_Exported_Functions_Group3 2042 * @{ 2043 */ 2044 2045 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); 2046 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); 2047 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); 2048 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); 2049 void HAL_RCCEx_CRS_IRQHandler(void); 2050 void HAL_RCCEx_CRS_SyncOkCallback(void); 2051 void HAL_RCCEx_CRS_SyncWarnCallback(void); 2052 void HAL_RCCEx_CRS_ExpectedSyncCallback(void); 2053 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); 2054 2055 /** 2056 * @} 2057 */ 2058 2059 #endif /* CRS */ 2060 2061 /** 2062 * @} 2063 */ 2064 2065 /** 2066 * @} 2067 */ 2068 2069 /** 2070 * @} 2071 */ 2072 2073 /** 2074 * @} 2075 */ 2076 2077 #ifdef __cplusplus 2078 } 2079 #endif 2080 2081 #endif /* __STM32F0xx_HAL_RCC_EX_H */ 2082 2083
