1 /** 2 ****************************************************************************** 3 * @file stm32f0xx_hal_adc.h 4 * @author MCD Application Team 5 * @brief Header file containing functions prototypes of ADC HAL library. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32F0xx_HAL_ADC_H 21 #define STM32F0xx_HAL_ADC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f0xx_hal_def.h" 29 30 /** @addtogroup STM32F0xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup ADC 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup ADC_Exported_Types ADC Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief Structure definition of ADC initialization and regular group 45 * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. 46 * ADC state can be either: 47 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ClockPrescaler') 48 * - For all parameters except 'ClockPrescaler' and 'resolution': ADC enabled without conversion on going on regular group. 49 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 50 * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). 51 */ 52 typedef struct 53 { 54 uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from ADC dedicated HSI RC oscillator 14MHz) and clock prescaler. 55 This parameter can be a value of @ref ADC_ClockPrescaler 56 Note: In case of usage of the ADC dedicated HSI RC oscillator, it must be preliminarily enabled at RCC top level. 57 Note: This parameter can be modified only if the ADC is disabled */ 58 uint32_t Resolution; /*!< Configures the ADC resolution. 59 This parameter can be a value of @ref ADC_Resolution */ 60 uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right. 61 This parameter can be a value of @ref ADC_Data_align */ 62 uint32_t ScanConvMode; /*!< Configures the sequencer of regular group. 63 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. 64 Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other STM32 devices): 65 If only 1 channel is set: Conversion is performed in single mode. 66 If several channels are set: Conversions are performed in sequence mode (ranks defined by each channel number: channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). 67 Scan direction can be set to forward (from channel 0 to channel 18) or backward (from channel 18 to channel 0). 68 This parameter can be a value of @ref ADC_Scan_mode */ 69 uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. 70 This parameter can be a value of @ref ADC_EOCSelection. */ 71 FunctionalState LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous 72 conversion (for regular group) has been treated by user software, using function HAL_ADC_GetValue(). 73 This feature automatically adapts the ADC conversions trigs to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. 74 This parameter can be set to ENABLE or DISABLE. 75 Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer. 76 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed 77 and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion. */ 78 FunctionalState LowPowerAutoPowerOff; /*!< Selects the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling). 79 This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait'). 80 This parameter can be set to ENABLE or DISABLE. 81 Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */ 82 FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, 83 after the selected trigger occurred (software start or external trigger). 84 This parameter can be set to ENABLE or DISABLE. */ 85 FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). 86 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 87 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. 88 This parameter can be set to ENABLE or DISABLE 89 Note: Number of discontinuous ranks increment is fixed to one-by-one. */ 90 uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. 91 If set to ADC_SOFTWARE_START, external triggers are disabled. 92 This parameter can be a value of @ref ADC_External_trigger_source_Regular */ 93 uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group. 94 If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. 95 This parameter can be a value of @ref ADC_External_trigger_edge_Regular */ 96 FunctionalState DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) 97 or in Continuous mode (DMA transfer unlimited, whatever number of conversions). 98 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. 99 This parameter can be set to ENABLE or DISABLE. */ 100 uint32_t Overrun; /*!< Select the behaviour in case of overrun: data preserved or overwritten 101 This parameter has an effect on regular group only, including in DMA mode. 102 This parameter can be a value of @ref ADC_Overrun */ 103 uint32_t SamplingTimeCommon; /*!< Sampling time value to be set for the selected channel. 104 Unit: ADC clock cycles 105 Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 106 Note: On STM32F0 devices, the sampling time setting is common to all channels. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure. 107 This parameter can be a value of @ref ADC_sampling_times 108 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 109 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 110 Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17us). */ 111 }ADC_InitTypeDef; 112 113 /** 114 * @brief Structure definition of ADC channel for regular group 115 * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. 116 * ADC state can be either: 117 * - For all parameters: ADC disabled or enabled without conversion on going on regular group. 118 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 119 * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). 120 */ 121 typedef struct 122 { 123 uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. 124 This parameter can be a value of @ref ADC_channels 125 Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */ 126 uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer. 127 On STM32F0 devices, number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).. 128 Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer. 129 This parameter can be a value of @ref ADC_rank */ 130 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 131 Unit: ADC clock cycles 132 Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 133 This parameter can be a value of @ref ADC_sampling_times 134 Caution: this setting impacts the entire regular group. Therefore, call of HAL_ADC_ConfigChannel() to configure a channel can impact the configuration of other channels previously set. 135 Caution: Obsolete parameter. Use parameter "SamplingTimeCommon" in ADC initialization structure. 136 If parameter "SamplingTimeCommon" is set to a valid sampling time, parameter "SamplingTime" is discarded. 137 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 138 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 139 Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17us). */ 140 }ADC_ChannelConfTypeDef; 141 142 /** 143 * @brief Structure definition of ADC analog watchdog 144 * @note The setting of these parameters with function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. 145 * ADC state can be either: ADC disabled or ADC enabled without conversion on going on regular group. 146 */ 147 typedef struct 148 { 149 uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all/none channels. 150 This parameter can be a value of @ref ADC_analog_watchdog_mode. */ 151 uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog. 152 This parameter has an effect only if parameter 'WatchdogMode' is configured on single channel. Only 1 channel can be monitored. 153 This parameter can be a value of @ref ADC_channels. */ 154 FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode. 155 This parameter can be set to ENABLE or DISABLE */ 156 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. 157 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ 158 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. 159 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ 160 }ADC_AnalogWDGConfTypeDef; 161 162 /** 163 * @brief HAL ADC state machine: ADC states definition (bitfields) 164 * @note ADC state machine is managed by bitfields, state must be compared 165 * with bit by bit. 166 * For example: 167 * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) " 168 * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " 169 */ 170 /* States of ADC global scope */ 171 #define HAL_ADC_STATE_RESET (0x00000000U) /*!< ADC not yet initialized or disabled */ 172 #define HAL_ADC_STATE_READY (0x00000001U) /*!< ADC peripheral ready for use */ 173 #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */ 174 #define HAL_ADC_STATE_TIMEOUT (0x00000004U) /*!< TimeOut occurrence */ 175 176 /* States of ADC errors */ 177 #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010U) /*!< Internal error occurrence */ 178 #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020U) /*!< Configuration error occurrence */ 179 #define HAL_ADC_STATE_ERROR_DMA (0x00000040U) /*!< DMA error occurrence */ 180 181 /* States of ADC group regular */ 182 #define HAL_ADC_STATE_REG_BUSY (0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, 183 external trigger, low power auto power-on, multimode ADC master control) */ 184 #define HAL_ADC_STATE_REG_EOC (0x00000200U) /*!< Conversion data available on group regular */ 185 #define HAL_ADC_STATE_REG_OVR (0x00000400U) /*!< Overrun occurrence */ 186 #define HAL_ADC_STATE_REG_EOSMP (0x00000800U) /*!< Not available on STM32F0 device: End Of Sampling flag raised */ 187 188 /* States of ADC group injected */ 189 #define HAL_ADC_STATE_INJ_BUSY (0x00001000U) /*!< Not available on STM32F0 device: A conversion on group injected is ongoing or can occur (either by auto-injection mode, 190 external trigger, low power auto power-on, multimode ADC master control) */ 191 #define HAL_ADC_STATE_INJ_EOC (0x00002000U) /*!< Not available on STM32F0 device: Conversion data available on group injected */ 192 #define HAL_ADC_STATE_INJ_JQOVF (0x00004000U) /*!< Not available on STM32F0 device: Not available on STM32F0 device: Injected queue overflow occurrence */ 193 194 /* States of ADC analog watchdogs */ 195 #define HAL_ADC_STATE_AWD1 (0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */ 196 #define HAL_ADC_STATE_AWD2 (0x00020000U) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 2 */ 197 #define HAL_ADC_STATE_AWD3 (0x00040000U) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 3 */ 198 199 /* States of ADC multi-mode */ 200 #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U) /*!< Not available on STM32F0 device: ADC in multimode slave state, controlled by another ADC master ( */ 201 202 203 /** 204 * @brief ADC handle Structure definition 205 */ 206 typedef struct __ADC_HandleTypeDef 207 { 208 ADC_TypeDef *Instance; /*!< Register base address */ 209 210 ADC_InitTypeDef Init; /*!< ADC required parameters */ 211 212 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 213 214 HAL_LockTypeDef Lock; /*!< ADC locking object */ 215 216 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ 217 218 __IO uint32_t ErrorCode; /*!< ADC Error code */ 219 220 221 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 222 void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ 223 void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ 224 void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ 225 void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ 226 void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ 227 void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ 228 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 229 }ADC_HandleTypeDef; 230 231 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 232 /** 233 * @brief HAL ADC Callback ID enumeration definition 234 */ 235 typedef enum 236 { 237 HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ 238 HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ 239 HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ 240 HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ 241 HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ 242 HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ 243 HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ 244 } HAL_ADC_CallbackIDTypeDef; 245 246 /** 247 * @brief HAL ADC Callback pointer definition 248 */ 249 typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ 250 251 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 252 253 /** 254 * @} 255 */ 256 257 258 259 /* Exported constants --------------------------------------------------------*/ 260 261 /** @defgroup ADC_Exported_Constants ADC Exported Constants 262 * @{ 263 */ 264 265 /** @defgroup ADC_Error_Code ADC Error Code 266 * @{ 267 */ 268 #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ 269 #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error: if problem of clocking, 270 enable/disable, erroneous state */ 271 #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ 272 #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ 273 274 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 275 #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ 276 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 277 278 /** 279 * @} 280 */ 281 282 /** @defgroup ADC_ClockPrescaler ADC ClockPrescaler 283 * @{ 284 */ 285 #define ADC_CLOCK_ASYNC_DIV1 (0x00000000U) /*!< ADC asynchronous clock derived from ADC dedicated HSI */ 286 287 #define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2 */ 288 #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4 */ 289 290 /** 291 * @} 292 */ 293 294 /** @defgroup ADC_Resolution ADC Resolution 295 * @{ 296 */ 297 #define ADC_RESOLUTION_12B (0x00000000U) /*!< ADC 12-bit resolution */ 298 #define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR1_RES_0) /*!< ADC 10-bit resolution */ 299 #define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR1_RES_1) /*!< ADC 8-bit resolution */ 300 #define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR1_RES) /*!< ADC 6-bit resolution */ 301 /** 302 * @} 303 */ 304 305 /** @defgroup ADC_Data_align ADC Data_align 306 * @{ 307 */ 308 #define ADC_DATAALIGN_RIGHT (0x00000000U) 309 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR1_ALIGN) 310 /** 311 * @} 312 */ 313 314 /** @defgroup ADC_Scan_mode ADC Scan mode 315 * @{ 316 */ 317 /* Note: Scan mode values must be compatible with other STM32 devices having */ 318 /* a configurable sequencer. */ 319 /* Scan direction setting values are defined by taking in account */ 320 /* already defined values for other STM32 devices: */ 321 /* ADC_SCAN_DISABLE (0x00000000U) */ 322 /* ADC_SCAN_ENABLE (0x00000001U) */ 323 /* Scan direction forward is considered as default setting equivalent */ 324 /* to scan enable. */ 325 /* Scan direction backward is considered as additional setting. */ 326 /* In case of migration from another STM32 device, the user will be */ 327 /* warned of change of setting choices with assert check. */ 328 #define ADC_SCAN_DIRECTION_FORWARD (0x00000001U) /*!< Scan direction forward: from channel 0 to channel 18 */ 329 #define ADC_SCAN_DIRECTION_BACKWARD (0x00000002U) /*!< Scan direction backward: from channel 18 to channel 0 */ 330 331 #define ADC_SCAN_ENABLE ADC_SCAN_DIRECTION_FORWARD /* For compatibility with other STM32 devices */ 332 333 /** 334 * @} 335 */ 336 337 /** @defgroup ADC_External_trigger_edge_Regular ADC External trigger edge Regular 338 * @{ 339 */ 340 #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000U) 341 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR1_EXTEN_0) 342 #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR1_EXTEN_1) 343 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR1_EXTEN) 344 /** 345 * @} 346 */ 347 348 /** @defgroup ADC_EOCSelection ADC EOCSelection 349 * @{ 350 */ 351 #define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC) 352 #define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS) 353 /** 354 * @} 355 */ 356 357 /** @defgroup ADC_Overrun ADC Overrun 358 * @{ 359 */ 360 #define ADC_OVR_DATA_OVERWRITTEN (0x00000000U) 361 #define ADC_OVR_DATA_PRESERVED (0x00000001U) 362 /** 363 * @} 364 */ 365 366 /** @defgroup ADC_rank ADC rank 367 * @{ 368 */ 369 #define ADC_RANK_CHANNEL_NUMBER (0x00001000U) /*!< Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */ 370 #define ADC_RANK_NONE (0x00001001U) /*!< Disable the selected rank (selected channel) from sequencer */ 371 /** 372 * @} 373 */ 374 375 /** @defgroup ADC_sampling_times ADC sampling times 376 * @{ 377 */ 378 /* Note: Parameter "ADC_SAMPLETIME_1CYCLE_5" defined with a dummy bit */ 379 /* to distinguish this parameter versus reset value 0x00000000, */ 380 /* in the context of management of parameters "SamplingTimeCommon" */ 381 /* and "SamplingTime" (obsolete)). */ 382 #define ADC_SAMPLETIME_1CYCLE_5 (0x10000000U) /*!< Sampling time 1.5 ADC clock cycle */ 383 #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t) ADC_SMPR_SMP_0) /*!< Sampling time 7.5 ADC clock cycles */ 384 #define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t) ADC_SMPR_SMP_1) /*!< Sampling time 13.5 ADC clock cycles */ 385 #define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0)) /*!< Sampling time 28.5 ADC clock cycles */ 386 #define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t) ADC_SMPR_SMP_2) /*!< Sampling time 41.5 ADC clock cycles */ 387 #define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_2 | ADC_SMPR_SMP_0)) /*!< Sampling time 55.5 ADC clock cycles */ 388 #define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1)) /*!< Sampling time 71.5 ADC clock cycles */ 389 #define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t) ADC_SMPR_SMP) /*!< Sampling time 239.5 ADC clock cycles */ 390 /** 391 * @} 392 */ 393 394 /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode 395 * @{ 396 */ 397 #define ADC_ANALOGWATCHDOG_NONE ( 0x00000000U) 398 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN)) 399 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR1_AWDEN) 400 /** 401 * @} 402 */ 403 404 /** @defgroup ADC_Event_type ADC Event type 405 * @{ 406 */ 407 #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog 1 event */ 408 #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */ 409 /** 410 * @} 411 */ 412 413 /** @defgroup ADC_interrupts_definition ADC interrupts definition 414 * @{ 415 */ 416 #define ADC_IT_AWD ADC_IER_AWDIE /*!< ADC Analog watchdog interrupt source */ 417 #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ 418 #define ADC_IT_EOS ADC_IER_EOSEQIE /*!< ADC End of Regular sequence of Conversions interrupt source */ 419 #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of Regular Conversion interrupt source */ 420 #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of Sampling interrupt source */ 421 #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ 422 /** 423 * @} 424 */ 425 426 /** @defgroup ADC_flags_definition ADC flags definition 427 * @{ 428 */ 429 #define ADC_FLAG_AWD ADC_ISR_AWD /*!< ADC Analog watchdog flag */ 430 #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ 431 #define ADC_FLAG_EOS ADC_ISR_EOSEQ /*!< ADC End of Regular sequence of Conversions flag */ 432 #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ 433 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ 434 #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ 435 /** 436 * @} 437 */ 438 439 /** 440 * @} 441 */ 442 443 444 /* Private constants ---------------------------------------------------------*/ 445 446 /** @addtogroup ADC_Private_Constants ADC Private Constants 447 * @{ 448 */ 449 450 /** @defgroup ADC_Internal_HAL_driver_Ext_trig_src_Regular ADC Internal HAL driver Ext trig src Regular 451 * @{ 452 */ 453 454 /* List of external triggers of regular group for ADC1: */ 455 /* (used internally by HAL driver. To not use into HAL structure parameters) */ 456 #define ADC1_2_EXTERNALTRIG_T1_TRGO (0x00000000U) 457 #define ADC1_2_EXTERNALTRIG_T1_CC4 ((uint32_t)ADC_CFGR1_EXTSEL_0) 458 #define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_1) 459 #define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0)) 460 #define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_2) 461 /** 462 * @} 463 */ 464 465 /* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */ 466 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC) 467 468 /** 469 * @} 470 */ 471 472 473 /* Exported macro ------------------------------------------------------------*/ 474 475 /** @defgroup ADC_Exported_Macros ADC Exported Macros 476 * @{ 477 */ 478 /* Macro for internal HAL driver usage, and possibly can be used into code of */ 479 /* final user. */ 480 481 /** 482 * @brief Enable the ADC peripheral 483 * @param __HANDLE__ ADC handle 484 * @retval None 485 */ 486 #define __HAL_ADC_ENABLE(__HANDLE__) \ 487 ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN) 488 489 /** 490 * @brief Disable the ADC peripheral 491 * @param __HANDLE__ ADC handle 492 * @retval None 493 */ 494 #define __HAL_ADC_DISABLE(__HANDLE__) \ 495 do{ \ 496 (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; \ 497 __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \ 498 } while(0) 499 500 /** 501 * @brief Enable the ADC end of conversion interrupt. 502 * @param __HANDLE__ ADC handle 503 * @param __INTERRUPT__ ADC Interrupt 504 * This parameter can be any combination of the following values: 505 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source 506 * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source 507 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source 508 * @arg ADC_IT_OVR: ADC overrun interrupt source 509 * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source 510 * @arg ADC_IT_RDY: ADC Ready interrupt source 511 * @retval None 512 */ 513 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 514 (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) 515 516 /** 517 * @brief Disable the ADC end of conversion interrupt. 518 * @param __HANDLE__ ADC handle 519 * @param __INTERRUPT__ ADC Interrupt 520 * This parameter can be any combination of the following values: 521 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source 522 * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source 523 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source 524 * @arg ADC_IT_OVR: ADC overrun interrupt source 525 * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source 526 * @arg ADC_IT_RDY: ADC Ready interrupt source 527 * @retval None 528 */ 529 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 530 (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) 531 532 /** @brief Checks if the specified ADC interrupt source is enabled or disabled. 533 * @param __HANDLE__ ADC handle 534 * @param __INTERRUPT__ ADC interrupt source to check 535 * This parameter can be any combination of the following values: 536 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source 537 * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source 538 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source 539 * @arg ADC_IT_OVR: ADC overrun interrupt source 540 * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source 541 * @arg ADC_IT_RDY: ADC Ready interrupt source 542 * @retval State ofinterruption (SET or RESET) 543 */ 544 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 545 (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) 546 547 /** 548 * @brief Get the selected ADC's flag status. 549 * @param __HANDLE__ ADC handle 550 * @param __FLAG__ ADC flag 551 * This parameter can be any combination of the following values: 552 * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag 553 * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag 554 * @arg ADC_FLAG_AWD: ADC Analog watchdog flag 555 * @arg ADC_FLAG_OVR: ADC overrun flag 556 * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag 557 * @arg ADC_FLAG_RDY: ADC Ready flag 558 * @retval None 559 */ 560 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ 561 ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) 562 563 /** 564 * @brief Clear the ADC's pending flags 565 * @param __HANDLE__ ADC handle 566 * @param __FLAG__ ADC flag 567 * This parameter can be any combination of the following values: 568 * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag 569 * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag 570 * @arg ADC_FLAG_AWD: ADC Analog watchdog flag 571 * @arg ADC_FLAG_OVR: ADC overrun flag 572 * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag 573 * @arg ADC_FLAG_RDY: ADC Ready flag 574 * @retval None 575 */ 576 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ 577 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 578 (((__HANDLE__)->Instance->ISR) = (__FLAG__)) 579 580 /** @brief Reset ADC handle state 581 * @param __HANDLE__ ADC handle 582 * @retval None 583 */ 584 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 585 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 586 do{ \ 587 (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ 588 (__HANDLE__)->MspInitCallback = NULL; \ 589 (__HANDLE__)->MspDeInitCallback = NULL; \ 590 } while(0) 591 #else 592 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 593 ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 594 #endif 595 596 /** 597 * @} 598 */ 599 600 601 /* Private macro -------------------------------------------------------------*/ 602 603 /** @defgroup ADC_Private_Macros ADC Private Macros 604 * @{ 605 */ 606 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 607 /* code of final user. */ 608 609 610 /** 611 * @brief Verification of hardware constraints before ADC can be enabled 612 * @param __HANDLE__ ADC handle 613 * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled) 614 */ 615 #define ADC_ENABLING_CONDITIONS(__HANDLE__) \ 616 (( ( ((__HANDLE__)->Instance->CR) & \ 617 (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) \ 618 ) == RESET \ 619 ) ? SET : RESET) 620 621 /** 622 * @brief Verification of hardware constraints before ADC can be disabled 623 * @param __HANDLE__ ADC handle 624 * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled) 625 */ 626 #define ADC_DISABLING_CONDITIONS(__HANDLE__) \ 627 (( ( ((__HANDLE__)->Instance->CR) & \ 628 (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \ 629 ) ? SET : RESET) 630 631 /** 632 * @brief Verification of ADC state: enabled or disabled 633 * @param __HANDLE__ ADC handle 634 * @retval SET (ADC enabled) or RESET (ADC disabled) 635 */ 636 /* Note: If low power mode AutoPowerOff is enabled, power-on/off phases are */ 637 /* performed automatically by hardware and flag ADC_FLAG_RDY is not */ 638 /* set. */ 639 #define ADC_IS_ENABLE(__HANDLE__) \ 640 (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ 641 (((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) || \ 642 ((((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_AUTOFF) == ADC_CFGR1_AUTOFF) ) \ 643 ) ? SET : RESET) 644 645 /** 646 * @brief Test if conversion trigger of regular group is software start 647 * or external trigger. 648 * @param __HANDLE__ ADC handle 649 * @retval SET (software start) or RESET (external trigger) 650 */ 651 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ 652 (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET) 653 654 /** 655 * @brief Check if no conversion on going on regular group 656 * @param __HANDLE__ ADC handle 657 * @retval SET (conversion is on going) or RESET (no conversion is on going) 658 */ 659 #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ 660 (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \ 661 ) ? RESET : SET) 662 663 /** 664 * @brief Returns resolution bits in CFGR1 register: RES[1:0]. 665 * Returned value is among parameters to @ref ADC_Resolution. 666 * @param __HANDLE__ ADC handle 667 * @retval None 668 */ 669 #define ADC_GET_RESOLUTION(__HANDLE__) \ 670 (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES) 671 672 /** 673 * @brief Returns ADC sample time bits in SMPR register: SMP[2:0]. 674 * Returned value is among parameters to @ref ADC_Resolution. 675 * @param __HANDLE__ ADC handle 676 * @retval None 677 */ 678 #define ADC_GET_SAMPLINGTIME(__HANDLE__) \ 679 (((__HANDLE__)->Instance->SMPR) & ADC_SMPR_SMP) 680 681 /** 682 * @brief Simultaneously clears and sets specific bits of the handle State 683 * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 684 * the first parameter is the ADC handle State, the second parameter is the 685 * bit field to clear, the third and last parameter is the bit field to set. 686 * @retval None 687 */ 688 #define ADC_STATE_CLR_SET MODIFY_REG 689 690 /** 691 * @brief Clear ADC error code (set it to error code: "no error") 692 * @param __HANDLE__ ADC handle 693 * @retval None 694 */ 695 #define ADC_CLEAR_ERRORCODE(__HANDLE__) \ 696 ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 697 698 699 /** 700 * @brief Configure the channel number into channel selection register 701 * @param _CHANNEL_ ADC Channel 702 * @retval None 703 */ 704 /* This function converts ADC channels from numbers (see defgroup ADC_channels) 705 to bitfields, to get the equivalence of CMSIS channels: 706 ADC_CHANNEL_0 ((uint32_t) ADC_CHSELR_CHSEL0) 707 ADC_CHANNEL_1 ((uint32_t) ADC_CHSELR_CHSEL1) 708 ADC_CHANNEL_2 ((uint32_t) ADC_CHSELR_CHSEL2) 709 ADC_CHANNEL_3 ((uint32_t) ADC_CHSELR_CHSEL3) 710 ADC_CHANNEL_4 ((uint32_t) ADC_CHSELR_CHSEL4) 711 ADC_CHANNEL_5 ((uint32_t) ADC_CHSELR_CHSEL5) 712 ADC_CHANNEL_6 ((uint32_t) ADC_CHSELR_CHSEL6) 713 ADC_CHANNEL_7 ((uint32_t) ADC_CHSELR_CHSEL7) 714 ADC_CHANNEL_8 ((uint32_t) ADC_CHSELR_CHSEL8) 715 ADC_CHANNEL_9 ((uint32_t) ADC_CHSELR_CHSEL9) 716 ADC_CHANNEL_10 ((uint32_t) ADC_CHSELR_CHSEL10) 717 ADC_CHANNEL_11 ((uint32_t) ADC_CHSELR_CHSEL11) 718 ADC_CHANNEL_12 ((uint32_t) ADC_CHSELR_CHSEL12) 719 ADC_CHANNEL_13 ((uint32_t) ADC_CHSELR_CHSEL13) 720 ADC_CHANNEL_14 ((uint32_t) ADC_CHSELR_CHSEL14) 721 ADC_CHANNEL_15 ((uint32_t) ADC_CHSELR_CHSEL15) 722 ADC_CHANNEL_16 ((uint32_t) ADC_CHSELR_CHSEL16) 723 ADC_CHANNEL_17 ((uint32_t) ADC_CHSELR_CHSEL17) 724 ADC_CHANNEL_18 ((uint32_t) ADC_CHSELR_CHSEL18) 725 */ 726 #define ADC_CHSELR_CHANNEL(_CHANNEL_) \ 727 ( 1U << (_CHANNEL_)) 728 729 /** 730 * @brief Set the ADC's sample time 731 * @param _SAMPLETIME_ Sample time parameter. 732 * @retval None 733 */ 734 /* Note: ADC sampling time set using mask ADC_SMPR_SMP due to parameter */ 735 /* "ADC_SAMPLETIME_1CYCLE_5" defined with a dummy bit (bit used to */ 736 /* distinguish this parameter versus reset value 0x00000000, */ 737 /* in the context of management of parameters "SamplingTimeCommon" */ 738 /* and "SamplingTime" (obsolete)). */ 739 #define ADC_SMPR_SET(_SAMPLETIME_) \ 740 ((_SAMPLETIME_) & (ADC_SMPR_SMP)) 741 742 /** 743 * @brief Set the Analog Watchdog 1 channel. 744 * @param _CHANNEL_ channel to be monitored by Analog Watchdog 1. 745 * @retval None 746 */ 747 #define ADC_CFGR_AWDCH(_CHANNEL_) \ 748 ((_CHANNEL_) << 26U) 749 750 /** 751 * @brief Enable ADC discontinuous conversion mode for regular group 752 * @param _REG_DISCONTINUOUS_MODE_ Regular discontinuous mode. 753 * @retval None 754 */ 755 #define ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) \ 756 ((_REG_DISCONTINUOUS_MODE_) << 16U) 757 758 /** 759 * @brief Enable the ADC auto off mode. 760 * @param _AUTOOFF_ Auto off bit enable or disable. 761 * @retval None 762 */ 763 #define ADC_CFGR1_AUTOOFF(_AUTOOFF_) \ 764 ((_AUTOOFF_) << 15U) 765 766 /** 767 * @brief Enable the ADC auto delay mode. 768 * @param _AUTOWAIT_ Auto delay bit enable or disable. 769 * @retval None 770 */ 771 #define ADC_CFGR1_AUTOWAIT(_AUTOWAIT_) \ 772 ((_AUTOWAIT_) << 14U) 773 774 /** 775 * @brief Enable ADC continuous conversion mode. 776 * @param _CONTINUOUS_MODE_ Continuous mode. 777 * @retval None 778 */ 779 #define ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) \ 780 ((_CONTINUOUS_MODE_) << 13U) 781 782 /** 783 * @brief Enable ADC overrun mode. 784 * @param _OVERRUN_MODE_ Overrun mode. 785 * @retval Overrun bit setting to be programmed into CFGR register 786 */ 787 /* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */ 788 /* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it */ 789 /* as the default case to be compliant with other STM32 devices. */ 790 #define ADC_CFGR1_OVERRUN(_OVERRUN_MODE_) \ 791 ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \ 792 )? (ADC_CFGR1_OVRMOD) : (0x00000000) \ 793 ) 794 795 /** 796 * @brief Enable ADC scan mode to convert multiple ranks with sequencer. 797 * @param _SCAN_MODE_ Scan conversion mode. 798 * @retval None 799 */ 800 /* Note: Scan mode set using this macro (instead of parameter direct set) */ 801 /* due to different modes on other STM32 devices: to avoid any */ 802 /* unwanted setting, the exact parameter corresponding to the device */ 803 /* must be passed to this macro. */ 804 #define ADC_SCANDIR(_SCAN_MODE_) \ 805 ( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD) \ 806 )? (ADC_CFGR1_SCANDIR) : (0x00000000) \ 807 ) 808 809 /** 810 * @brief Enable the ADC DMA continuous request. 811 * @param _DMACONTREQ_MODE_ DMA continuous request mode. 812 * @retval None 813 */ 814 #define ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_) \ 815 ((_DMACONTREQ_MODE_) << 1U) 816 817 /** 818 * @brief Configure the analog watchdog high threshold into register TR. 819 * @param _Threshold_ Threshold value 820 * @retval None 821 */ 822 #define ADC_TRX_HIGHTHRESHOLD(_Threshold_) \ 823 ((_Threshold_) << 16U) 824 825 /** 826 * @brief Shift the AWD threshold in function of the selected ADC resolution. 827 * Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. 828 * If resolution 12 bits, no shift. 829 * If resolution 10 bits, shift of 2 ranks on the left. 830 * If resolution 8 bits, shift of 4 ranks on the left. 831 * If resolution 6 bits, shift of 6 ranks on the left. 832 * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)) 833 * @param __HANDLE__ ADC handle 834 * @param _Threshold_ Value to be shifted 835 * @retval None 836 */ 837 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \ 838 ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2)) 839 840 841 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || \ 842 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ 843 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ) 844 845 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ 846 ((RESOLUTION) == ADC_RESOLUTION_10B) || \ 847 ((RESOLUTION) == ADC_RESOLUTION_8B) || \ 848 ((RESOLUTION) == ADC_RESOLUTION_6B) ) 849 850 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ 851 ((ALIGN) == ADC_DATAALIGN_LEFT) ) 852 853 #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || \ 854 ((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD) ) 855 856 #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 857 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ 858 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ 859 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) 860 861 #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \ 862 ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) ) 863 864 #define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \ 865 ((OVR) == ADC_OVR_DATA_OVERWRITTEN) ) 866 867 #define IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) || \ 868 ((WATCHDOG) == ADC_RANK_NONE) ) 869 870 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \ 871 ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \ 872 ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \ 873 ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \ 874 ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \ 875 ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \ 876 ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \ 877 ((TIME) == ADC_SAMPLETIME_239CYCLES_5) ) 878 879 #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ 880 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 881 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) ) 882 883 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \ 884 ((EVENT) == ADC_OVR_EVENT) ) 885 886 /** @defgroup ADC_range_verification ADC range verification 887 * in function of ADC resolution selected (12, 10, 8 or 6 bits) 888 * @{ 889 */ 890 #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \ 891 ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= (0x0FFFU))) || \ 892 (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= (0x03FFU))) || \ 893 (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= (0x00FFU))) || \ 894 (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= (0x003FU))) ) 895 /** 896 * @} 897 */ 898 899 /** @defgroup ADC_regular_rank_verification ADC regular rank verification 900 * @{ 901 */ 902 #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= (1U)) && ((RANK) <= (16U))) 903 /** 904 * @} 905 */ 906 907 /** 908 * @} 909 */ 910 911 /* Include ADC HAL Extension module */ 912 #include "stm32f0xx_hal_adc_ex.h" 913 914 /* Exported functions --------------------------------------------------------*/ 915 /** @addtogroup ADC_Exported_Functions 916 * @{ 917 */ 918 919 /** @addtogroup ADC_Exported_Functions_Group1 920 * @{ 921 */ 922 923 924 /* Initialization and de-initialization functions **********************************/ 925 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); 926 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 927 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); 928 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); 929 930 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 931 /* Callbacks Register/UnRegister functions ***********************************/ 932 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback); 933 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); 934 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 935 936 /** 937 * @} 938 */ 939 940 /* IO operation functions *****************************************************/ 941 942 /** @addtogroup ADC_Exported_Functions_Group2 943 * @{ 944 */ 945 946 947 /* Blocking mode: Polling */ 948 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); 949 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); 950 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); 951 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); 952 953 /* Non-blocking mode: Interruption */ 954 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); 955 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); 956 957 /* Non-blocking mode: DMA */ 958 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); 959 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); 960 961 /* ADC retrieve conversion value intended to be used with polling or interruption */ 962 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); 963 964 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ 965 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); 966 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); 967 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); 968 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); 969 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 970 /** 971 * @} 972 */ 973 974 975 /* Peripheral Control functions ***********************************************/ 976 /** @addtogroup ADC_Exported_Functions_Group3 977 * @{ 978 */ 979 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); 980 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); 981 /** 982 * @} 983 */ 984 985 986 /* Peripheral State functions *************************************************/ 987 /** @addtogroup ADC_Exported_Functions_Group4 988 * @{ 989 */ 990 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); 991 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); 992 /** 993 * @} 994 */ 995 996 997 /** 998 * @} 999 */ 1000 1001 1002 /** 1003 * @} 1004 */ 1005 1006 /** 1007 * @} 1008 */ 1009 1010 #ifdef __cplusplus 1011 } 1012 #endif 1013 1014 1015 #endif /* STM32F0xx_HAL_ADC_H */ 1016 1017 1018
