1 /**
2 ******************************************************************************
3 * @file stm32c0xx_ll_spi.c
4 * @author MCD Application Team
5 * @brief SPI LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32c0xx_ll_spi.h"
22 #include "stm32c0xx_ll_bus.h"
23 #include "stm32c0xx_ll_rcc.h"
24
25 #ifdef USE_FULL_ASSERT
26 #include "stm32_assert.h"
27 #else
28 #define assert_param(expr) ((void)0U)
29 #endif /* USE_FULL_ASSERT */
30
31 /** @addtogroup STM32C0xx_LL_Driver
32 * @{
33 */
34
35 #if defined (SPI1)
36
37 /** @addtogroup SPI_LL
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45 /** @defgroup SPI_LL_Private_Constants SPI Private Constants
46 * @{
47 */
48 /* SPI registers Masks */
49 #define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
50 SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
51 SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_CRCL | \
52 SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
53 SPI_CR1_BIDIMODE)
54 /**
55 * @}
56 */
57
58 /* Private macros ------------------------------------------------------------*/
59 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
60 * @{
61 */
62 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
63 || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
64 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
65 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
66
67 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
68 || ((__VALUE__) == LL_SPI_MODE_SLAVE))
69
70 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \
71 || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \
72 || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \
73 || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \
74 || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
75 || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \
76 || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
77 || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
78 || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
79 || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
80 || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
81 || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
82 || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
83
84 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
85 || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
86
87 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
88 || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
89
90 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
91 || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
92 || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
93
94 #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
95 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
96 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
97 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
98 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
99 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
100 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
101 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
102
103 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
104 || ((__VALUE__) == LL_SPI_MSB_FIRST))
105
106 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
107 || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
108
109 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
110
111 /**
112 * @}
113 */
114
115 /* Private function prototypes -----------------------------------------------*/
116
117 /* Exported functions --------------------------------------------------------*/
118 /** @addtogroup SPI_LL_Exported_Functions
119 * @{
120 */
121
122 /** @addtogroup SPI_LL_EF_Init
123 * @{
124 */
125
126 /**
127 * @brief De-initialize the SPI registers to their default reset values.
128 * @param SPIx SPI Instance
129 * @retval An ErrorStatus enumeration value:
130 * - SUCCESS: SPI registers are de-initialized
131 * - ERROR: SPI registers are not de-initialized
132 */
LL_SPI_DeInit(SPI_TypeDef * SPIx)133 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
134 {
135 ErrorStatus status = ERROR;
136
137 /* Check the parameters */
138 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
139
140 #if defined(SPI1)
141 if (SPIx == SPI1)
142 {
143 /* Force reset of SPI clock */
144 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
145
146 /* Release reset of SPI clock */
147 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
148
149 status = SUCCESS;
150 }
151 #endif /* SPI1 */
152
153 return status;
154 }
155
156 /**
157 * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
158 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
159 * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
160 * @param SPIx SPI Instance
161 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
162 * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
163 */
LL_SPI_Init(SPI_TypeDef * SPIx,LL_SPI_InitTypeDef * SPI_InitStruct)164 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
165 {
166 ErrorStatus status = ERROR;
167
168 /* Check the SPI Instance SPIx*/
169 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
170
171 /* Check the SPI parameters from SPI_InitStruct*/
172 assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
173 assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
174 assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
175 assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
176 assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
177 assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
178 assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
179 assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
180 assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
181
182 if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
183 {
184 /*---------------------------- SPIx CR1 Configuration ------------------------
185 * Configure SPIx CR1 with parameters:
186 * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
187 * - Master/Slave Mode: SPI_CR1_MSTR bit
188 * - ClockPolarity: SPI_CR1_CPOL bit
189 * - ClockPhase: SPI_CR1_CPHA bit
190 * - NSS management: SPI_CR1_SSM bit
191 * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
192 * - BitOrder: SPI_CR1_LSBFIRST bit
193 * - CRCCalculation: SPI_CR1_CRCEN bit
194 */
195 MODIFY_REG(SPIx->CR1,
196 SPI_CR1_CLEAR_MASK,
197 SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
198 SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
199 SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
200 SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
201
202 /*---------------------------- SPIx CR2 Configuration ------------------------
203 * Configure SPIx CR2 with parameters:
204 * - DataWidth: DS[3:0] bits
205 * - NSS management: SSOE bit
206 */
207 MODIFY_REG(SPIx->CR2,
208 SPI_CR2_DS | SPI_CR2_SSOE,
209 SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
210
211 /* Set Rx FIFO to Quarter (1 Byte) in case of 8 Bits mode. No DataPacking by default */
212 if (SPI_InitStruct->DataWidth < LL_SPI_DATAWIDTH_9BIT)
213 {
214 LL_SPI_SetRxFIFOThreshold(SPIx, LL_SPI_RX_FIFO_TH_QUARTER);
215 }
216
217 /*---------------------------- SPIx CRCPR Configuration ----------------------
218 * Configure SPIx CRCPR with parameters:
219 * - CRCPoly: CRCPOLY[15:0] bits
220 */
221 if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
222 {
223 assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
224 LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
225 }
226 status = SUCCESS;
227 }
228
229 #if defined (SPI_I2S_SUPPORT)
230 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
231 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
232 #endif /* SPI_I2S_SUPPORT */
233 return status;
234 }
235
236 /**
237 * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
238 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
239 * whose fields will be set to default values.
240 * @retval None
241 */
LL_SPI_StructInit(LL_SPI_InitTypeDef * SPI_InitStruct)242 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
243 {
244 /* Set SPI_InitStruct fields to default values */
245 SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
246 SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
247 SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
248 SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
249 SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
250 SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
251 SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
252 SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
253 SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
254 SPI_InitStruct->CRCPoly = 7U;
255 }
256
257 /**
258 * @}
259 */
260
261 /**
262 * @}
263 */
264
265 /**
266 * @}
267 */
268
269 #if defined(SPI_I2S_SUPPORT)
270 /** @addtogroup I2S_LL
271 * @{
272 */
273
274 /* Private types -------------------------------------------------------------*/
275 /* Private variables ---------------------------------------------------------*/
276 /* Private constants ---------------------------------------------------------*/
277 /** @defgroup I2S_LL_Private_Constants I2S Private Constants
278 * @{
279 */
280 /* I2S registers Masks */
281 #define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
282 SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
283 SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
284
285 #define I2S_I2SPR_CLEAR_MASK 0x0002U
286 /**
287 * @}
288 */
289 /* Private macros ------------------------------------------------------------*/
290 /** @defgroup I2S_LL_Private_Macros I2S Private Macros
291 * @{
292 */
293
294 #define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
295 || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
296 || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
297 || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
298
299 #define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
300 || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
301
302 #define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
303 || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
304 || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
305 || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
306 || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
307
308 #define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
309 || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
310 || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
311 || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
312
313 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
314 || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
315
316 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
317 && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
318 || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
319
320 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
321
322 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
323 || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
324 /**
325 * @}
326 */
327
328 /* Private function prototypes -----------------------------------------------*/
329
330 /* Exported functions --------------------------------------------------------*/
331 /** @addtogroup I2S_LL_Exported_Functions
332 * @{
333 */
334
335 /** @addtogroup I2S_LL_EF_Init
336 * @{
337 */
338
339 /**
340 * @brief De-initialize the SPI/I2S registers to their default reset values.
341 * @param SPIx SPI Instance
342 * @retval An ErrorStatus enumeration value:
343 * - SUCCESS: SPI registers are de-initialized
344 * - ERROR: SPI registers are not de-initialized
345 */
LL_I2S_DeInit(SPI_TypeDef * SPIx)346 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
347 {
348 return LL_SPI_DeInit(SPIx);
349 }
350
351 /**
352 * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
353 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
354 * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
355 * @param SPIx SPI Instance
356 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
357 * @retval An ErrorStatus enumeration value:
358 * - SUCCESS: SPI registers are Initialized
359 * - ERROR: SPI registers are not Initialized
360 */
LL_I2S_Init(SPI_TypeDef * SPIx,LL_I2S_InitTypeDef * I2S_InitStruct)361 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
362 {
363 uint32_t i2sdiv = 2U;
364 uint32_t i2sodd = 0U;
365 uint32_t packetlength = 1U;
366 uint32_t tmp;
367 LL_RCC_ClocksTypeDef rcc_clocks;
368 uint32_t sourceclock;
369 ErrorStatus status = ERROR;
370
371 /* Check the I2S parameters */
372 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
373 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
374 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
375 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
376 assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
377 assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
378 assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
379
380 if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
381 {
382 /*---------------------------- SPIx I2SCFGR Configuration --------------------
383 * Configure SPIx I2SCFGR with parameters:
384 * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
385 * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
386 * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
387 * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
388 */
389
390 /* Write to SPIx I2SCFGR */
391 MODIFY_REG(SPIx->I2SCFGR,
392 I2S_I2SCFGR_CLEAR_MASK,
393 I2S_InitStruct->Mode | I2S_InitStruct->Standard |
394 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
395 SPI_I2SCFGR_I2SMOD);
396
397 /*---------------------------- SPIx I2SPR Configuration ----------------------
398 * Configure SPIx I2SPR with parameters:
399 * - MCLKOutput: SPI_I2SPR_MCKOE bit
400 * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
401 */
402
403 /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
404 * else, default values are used: i2sodd = 0U, i2sdiv = 2U.
405 */
406 if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
407 {
408 /* Check the frame length (For the Prescaler computing)
409 * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
410 */
411 if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
412 {
413 /* Packet length is 32 bits */
414 packetlength = 2U;
415 }
416
417 /* I2S Clock source is System clock: Get System Clock frequency */
418 LL_RCC_GetSystemClocksFreq(&rcc_clocks);
419
420 /* Get the source clock value: based on System Clock value */
421 sourceclock = rcc_clocks.SYSCLK_Frequency;
422
423 /* Compute the Real divider depending on the MCLK output state with a floating point */
424 if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
425 {
426 /* MCLK output is enabled */
427 tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
428 }
429 else
430 {
431 /* MCLK output is disabled */
432 tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
433 }
434
435 /* Remove the floating point */
436 tmp = tmp / 10U;
437
438 /* Check the parity of the divider */
439 i2sodd = (tmp & (uint16_t)0x0001U);
440
441 /* Compute the i2sdiv prescaler */
442 i2sdiv = ((tmp - i2sodd) / 2U);
443
444 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
445 i2sodd = (i2sodd << 8U);
446 }
447
448 /* Test if the divider is 1 or 0 or greater than 0xFF */
449 if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
450 {
451 /* Set the default values */
452 i2sdiv = 2U;
453 i2sodd = 0U;
454 }
455
456 /* Write to SPIx I2SPR register the computed value */
457 WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
458
459 status = SUCCESS;
460 }
461 return status;
462 }
463
464 /**
465 * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
466 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
467 * whose fields will be set to default values.
468 * @retval None
469 */
LL_I2S_StructInit(LL_I2S_InitTypeDef * I2S_InitStruct)470 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
471 {
472 /*--------------- Reset I2S init structure parameters values -----------------*/
473 I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
474 I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
475 I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
476 I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
477 I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
478 I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
479 }
480
481 /**
482 * @brief Set linear and parity prescaler.
483 * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
484 * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
485 * @param SPIx SPI Instance
486 * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF.
487 * @param PrescalerParity This parameter can be one of the following values:
488 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
489 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
490 * @retval None
491 */
LL_I2S_ConfigPrescaler(SPI_TypeDef * SPIx,uint32_t PrescalerLinear,uint32_t PrescalerParity)492 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
493 {
494 /* Check the I2S parameters */
495 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
496 assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
497 assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
498
499 /* Write to SPIx I2SPR */
500 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
501 }
502
503 /**
504 * @}
505 */
506
507 /**
508 * @}
509 */
510
511 /**
512 * @}
513 */
514 #endif /* SPI_I2S_SUPPORT */
515
516 #endif /* defined (SPI1) */
517
518 /**
519 * @}
520 */
521
522 #endif /* USE_FULL_LL_DRIVER */
523
524
