1 /**
2 ******************************************************************************
3 * @file stm32c0xx_ll_adc.c
4 * @author MCD Application Team
5 * @brief ADC LL module driver
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32c0xx_ll_adc.h"
22 #include "stm32c0xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif
29
30 /** @addtogroup STM32C0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1)
35
36 /** @addtogroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @addtogroup ADC_LL_Private_Constants
44 * @{
45 */
46
47 /* Definitions of ADC hardware constraints delays */
48 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
49 /* not timeout values: */
50 /* Timeout values for ADC operations are dependent to device clock */
51 /* configuration (system clock versus ADC clock), */
52 /* and therefore must be defined in user application. */
53 /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
54 /* values definition. */
55 /* Note: ADC timeout values are defined here in CPU cycles to be independent */
56 /* of device clock setting. */
57 /* In user application, ADC timeout values should be defined with */
58 /* temporal values, in function of device clock settings. */
59 /* Highest ratio CPU clock frequency vs ADC clock frequency: */
60 /* - ADC clock from synchronous clock with AHB prescaler 512, */
61 /* APB prescaler 16, ADC prescaler 4. */
62 /* - ADC clock from asynchronous clock (HSI) with prescaler 1, */
63 /* with highest ratio CPU clock frequency vs HSI clock frequency: */
64 /* CPU clock frequency max 48MHz, HSI frequency 16MHz: ratio 4. */
65 /* Unit: CPU cycles. */
66 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)
67 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
68 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
69 /* Note: CCRDY handshake requires 1APB + 2 ADC + 3 APB cycles */
70 /* after the channel configuration has been changed. */
71 /* Driver timeout is approximated to 6 CPU cycles. */
72 #define ADC_TIMEOUT_CCRDY_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 6UL)
73
74 /**
75 * @}
76 */
77
78 /* Private macros ------------------------------------------------------------*/
79
80 /** @addtogroup ADC_LL_Private_Macros
81 * @{
82 */
83
84 /* Check of parameters for configuration of ADC hierarchical scope: */
85 /* common to several ADC instances. */
86 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
87 (((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
88 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
89 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \
90 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \
91 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \
92 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \
93 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \
94 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \
95 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \
96 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \
97 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
98 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
99 )
100
101 #define IS_LL_ADC_CLOCK_FREQ_MODE(__CLOCK_FREQ_MODE__) \
102 (((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_HIGH) \
103 || ((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_LOW) \
104 )
105
106 /* Check of parameters for configuration of ADC hierarchical scope: */
107 /* ADC instance. */
108 #define IS_LL_ADC_CLOCK(__CLOCK__) \
109 (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
110 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
111 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
112 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC) \
113 )
114
115 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
116 (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
117 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
118 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
119 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
120 )
121
122 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
123 (((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
124 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
125 )
126
127 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
128 (((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
129 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
130 || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF) \
131 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF) \
132 )
133
134 /* Check of parameters for configuration of ADC hierarchical scope: */
135 /* ADC group regular */
136 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
137 (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
138 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
139 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 ) \
140 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
141 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
142 )
143 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
144 (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
145 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
146 )
147
148 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
149 (((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
150 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
151 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
152 )
153
154 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
155 (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
156 || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
157 )
158
159 #define IS_LL_ADC_REG_SEQ_MODE(__REG_SEQ_MODE__) \
160 (((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_FIXED) \
161 || ((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_CONFIGURABLE) \
162 )
163
164 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
165 (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
166 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
167 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
168 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
169 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
170 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
171 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
172 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
173 )
174
175 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
176 (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
177 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
178 )
179
180 /**
181 * @}
182 */
183
184
185 /* Private function prototypes -----------------------------------------------*/
186
187 /* Exported functions --------------------------------------------------------*/
188 /** @addtogroup ADC_LL_Exported_Functions
189 * @{
190 */
191
192 /** @addtogroup ADC_LL_EF_Init
193 * @{
194 */
195
196 /**
197 * @brief De-initialize registers of all ADC instances belonging to
198 * the same ADC common instance to their default reset values.
199 * @note This function is performing a hard reset, using high level
200 * clock source RCC ADC reset.
201 * @param ADCxy_COMMON ADC common instance
202 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
203 * @retval An ErrorStatus enumeration value:
204 * - SUCCESS: ADC common registers are de-initialized
205 * - ERROR: not applicable
206 */
LL_ADC_CommonDeInit(ADC_Common_TypeDef * ADCxy_COMMON)207 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
208 {
209 /* Check the parameters */
210 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
211
212 /* Force reset of ADC clock (core clock) */
213 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC);
214
215 /* Release reset of ADC clock (core clock) */
216 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC);
217
218 return SUCCESS;
219 }
220
221 /**
222 * @brief Initialize some features of ADC common parameters
223 * (all ADC instances belonging to the same ADC common instance)
224 * and multimode (for devices with several ADC instances available).
225 * @note The setting of ADC common parameters is conditioned to
226 * ADC instances state:
227 * All ADC instances belonging to the same ADC common instance
228 * must be disabled.
229 * @param ADCxy_COMMON ADC common instance
230 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
231 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
232 * @retval An ErrorStatus enumeration value:
233 * - SUCCESS: ADC common registers are initialized
234 * - ERROR: ADC common registers are not initialized
235 */
LL_ADC_CommonInit(ADC_Common_TypeDef * ADCxy_COMMON,LL_ADC_CommonInitTypeDef * ADC_CommonInitStruct)236 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
237 {
238 ErrorStatus status = SUCCESS;
239
240 /* Check the parameters */
241 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
242 assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
243
244 /* Note: Hardware constraint (refer to description of functions */
245 /* "LL_ADC_SetCommonXXX()": */
246 /* On this STM32 series, setting of these features is conditioned to */
247 /* ADC state: */
248 /* All ADC instances of the ADC common group must be disabled. */
249 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
250 {
251 /* Configuration of ADC hierarchical scope: */
252 /* - common to several ADC */
253 /* (all ADC instances belonging to the same ADC common instance) */
254 /* - Set ADC clock (conversion clock) */
255 LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
256 }
257 else
258 {
259 /* Initialization error: One or several ADC instances belonging to */
260 /* the same ADC common instance are not disabled. */
261 status = ERROR;
262 }
263
264 return status;
265 }
266
267 /**
268 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
269 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
270 * whose fields will be set to default values.
271 * @retval None
272 */
LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef * ADC_CommonInitStruct)273 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
274 {
275 /* Set ADC_CommonInitStruct fields to default values */
276 /* Set fields of ADC common */
277 /* (all ADC instances belonging to the same ADC common instance) */
278 ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2;
279
280 }
281
282 /**
283 * @brief De-initialize registers of the selected ADC instance
284 * to their default reset values.
285 * @note To reset all ADC instances quickly (perform a hard reset),
286 * use function @ref LL_ADC_CommonDeInit().
287 * @note If this functions returns error status, it means that ADC instance
288 * is in an unknown state.
289 * In this case, perform a hard reset using high level
290 * clock source RCC ADC reset.
291 * Refer to function @ref LL_ADC_CommonDeInit().
292 * @param ADCx ADC instance
293 * @retval An ErrorStatus enumeration value:
294 * - SUCCESS: ADC registers are de-initialized
295 * - ERROR: ADC registers are not de-initialized
296 */
LL_ADC_DeInit(ADC_TypeDef * ADCx)297 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
298 {
299 ErrorStatus status = SUCCESS;
300
301 __IO uint32_t timeout_cpu_cycles = 0UL;
302
303 /* Check the parameters */
304 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
305
306 /* Disable ADC instance if not already disabled. */
307 if (LL_ADC_IsEnabled(ADCx) == 1UL)
308 {
309 /* Set ADC group regular trigger source to SW start to ensure to not */
310 /* have an external trigger event occurring during the conversion stop */
311 /* ADC disable process. */
312 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
313
314 /* Stop potential ADC conversion on going on ADC group regular. */
315 if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
316 {
317 if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL)
318 {
319 LL_ADC_REG_StopConversion(ADCx);
320 }
321 }
322
323 /* Wait for ADC conversions are effectively stopped */
324 timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
325 while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1UL)
326 {
327 timeout_cpu_cycles--;
328 if (timeout_cpu_cycles == 0UL)
329 {
330 /* Time-out error */
331 status = ERROR;
332 break;
333 }
334 }
335
336 /* Disable the ADC instance */
337 LL_ADC_Disable(ADCx);
338
339 /* Wait for ADC instance is effectively disabled */
340 timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
341 while (LL_ADC_IsDisableOngoing(ADCx) == 1UL)
342 {
343 timeout_cpu_cycles--;
344 if (timeout_cpu_cycles == 0UL)
345 {
346 /* Time-out error */
347 status = ERROR;
348 break;
349 }
350 }
351 }
352
353 /* Check whether ADC state is compliant with expected state */
354 if (READ_BIT(ADCx->CR,
355 (ADC_CR_ADSTP | ADC_CR_ADSTART
356 | ADC_CR_ADDIS | ADC_CR_ADEN)
357 )
358 == 0UL)
359 {
360 /* ========== Reset ADC registers ========== */
361 /* Reset register IER */
362 CLEAR_BIT(ADCx->IER,
363 (LL_ADC_IT_ADRDY
364 | LL_ADC_IT_EOC
365 | LL_ADC_IT_EOS
366 | LL_ADC_IT_OVR
367 | LL_ADC_IT_EOSMP
368 | LL_ADC_IT_AWD1
369 | LL_ADC_IT_AWD2
370 | LL_ADC_IT_AWD3
371 | LL_ADC_IT_EOCAL
372 | LL_ADC_IT_CCRDY
373 )
374 );
375
376 /* Reset register ISR */
377 SET_BIT(ADCx->ISR,
378 (LL_ADC_FLAG_ADRDY
379 | LL_ADC_FLAG_EOC
380 | LL_ADC_FLAG_EOS
381 | LL_ADC_FLAG_OVR
382 | LL_ADC_FLAG_EOSMP
383 | LL_ADC_FLAG_AWD1
384 | LL_ADC_FLAG_AWD2
385 | LL_ADC_FLAG_AWD3
386 | LL_ADC_FLAG_EOCAL
387 | LL_ADC_FLAG_CCRDY
388 )
389 );
390
391 /* Reset register CR */
392 /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
393 /* "read-set": no direct reset applicable. */
394 CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN);
395
396 /* Reset register CFGR1 */
397 CLEAR_BIT(ADCx->CFGR1,
398 (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN
399 | ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD
400 | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES
401 | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN)
402 );
403
404 /* Reset register CFGR2 */
405 /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
406 /* already done above. */
407 CLEAR_BIT(ADCx->CFGR2,
408 (ADC_CFGR2_CKMODE
409 | ADC_CFGR2_TOVS | ADC_CFGR2_OVSS | ADC_CFGR2_OVSR
410 | ADC_CFGR2_OVSE)
411 );
412
413 /* Reset register SMPR */
414 CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP1 | ADC_SMPR_SMP2 | ADC_SMPR_SMPSEL);
415
416 /* Reset register AWD1TR */
417 MODIFY_REG(ADCx->AWD1TR, ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1, ADC_AWD1TR_HT1);
418
419 /* Reset register AWD2TR */
420 MODIFY_REG(ADCx->AWD2TR, ADC_AWD2TR_HT2 | ADC_AWD2TR_LT2, ADC_AWD2TR_HT2);
421
422 /* Reset register AWD3TR */
423 MODIFY_REG(ADCx->AWD3TR, ADC_AWD3TR_HT3 | ADC_AWD3TR_LT3, ADC_AWD3TR_HT3);
424
425 /* Reset register CHSELR */
426 CLEAR_BIT(ADCx->CHSELR,
427 (ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16
428 | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
429 | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8
430 | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4
431 | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0)
432 );
433
434 /* Wait for ADC channel configuration ready */
435 timeout_cpu_cycles = ADC_TIMEOUT_CCRDY_CPU_CYCLES;
436 while (LL_ADC_IsActiveFlag_CCRDY(ADCx) == 0UL)
437 {
438 timeout_cpu_cycles--;
439 if (timeout_cpu_cycles == 0UL)
440 {
441 /* Time-out error */
442 status = ERROR;
443 break;
444 }
445 }
446
447 /* Clear flag ADC channel configuration ready */
448 LL_ADC_ClearFlag_CCRDY(ADCx);
449
450 /* Reset register DR */
451 /* bits in access mode read only, no direct reset applicable */
452
453 /* Reset register CALFACT */
454 CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT);
455
456 }
457 else
458 {
459 /* ADC instance is in an unknown state */
460 /* Need to performing a hard reset of ADC instance, using high level */
461 /* clock source RCC ADC reset. */
462 /* Caution: On this STM32 series, if several ADC instances are available */
463 /* on the selected device, RCC ADC reset will reset */
464 /* all ADC instances belonging to the common ADC instance. */
465 status = ERROR;
466 }
467
468 return status;
469 }
470
471 /**
472 * @brief Initialize some features of ADC instance.
473 * @note These parameters have an impact on ADC scope: ADC instance.
474 * Refer to corresponding unitary functions into
475 * @ref ADC_LL_EF_Configuration_ADC_Instance .
476 * @note The setting of these parameters by function @ref LL_ADC_Init()
477 * is conditioned to ADC state:
478 * ADC instance must be disabled.
479 * This condition is applied to all ADC features, for efficiency
480 * and compatibility over all STM32 families. However, the different
481 * features can be set under different ADC state conditions
482 * (setting possible with ADC enabled without conversion on going,
483 * ADC enabled with conversion on going, ...)
484 * Each feature can be updated afterwards with a unitary function
485 * and potentially with ADC in a different state than disabled,
486 * refer to description of each function for setting
487 * conditioned to ADC state.
488 * @note After using this function, some other features must be configured
489 * using LL unitary functions.
490 * The minimum configuration remaining to be done is:
491 * - Set ADC group regular sequencer:
492 * Depending on the sequencer mode (refer to
493 * function @ref LL_ADC_REG_SetSequencerConfigurable() ):
494 * - map channel on the selected sequencer rank.
495 * Refer to function @ref LL_ADC_REG_SetSequencerRanks();
496 * - map channel on rank corresponding to channel number.
497 * Refer to function @ref LL_ADC_REG_SetSequencerChannels();
498 * - Set ADC channel sampling time
499 * Refer to function LL_ADC_SetSamplingTimeCommonChannels();
500 * Refer to function LL_ADC_SetChannelSamplingTime();
501 * @param ADCx ADC instance
502 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
503 * @retval An ErrorStatus enumeration value:
504 * - SUCCESS: ADC registers are initialized
505 * - ERROR: ADC registers are not initialized
506 */
LL_ADC_Init(ADC_TypeDef * ADCx,LL_ADC_InitTypeDef * ADC_InitStruct)507 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
508 {
509 ErrorStatus status = SUCCESS;
510
511 /* Check the parameters */
512 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
513
514 assert_param(IS_LL_ADC_CLOCK(ADC_InitStruct->Clock));
515 assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
516 assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
517 assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
518
519 /* Note: Hardware constraint (refer to description of this function): */
520 /* ADC instance must be disabled. */
521 if (LL_ADC_IsEnabled(ADCx) == 0UL)
522 {
523 /* Configuration of ADC hierarchical scope: */
524 /* - ADC instance */
525 /* - Set ADC data resolution */
526 /* - Set ADC conversion data alignment */
527 /* - Set ADC low power mode */
528 MODIFY_REG(ADCx->CFGR1,
529 ADC_CFGR1_RES
530 | ADC_CFGR1_ALIGN
531 | ADC_CFGR1_WAIT
532 | ADC_CFGR1_AUTOFF
533 ,
534 ADC_InitStruct->Resolution
535 | ADC_InitStruct->DataAlignment
536 | ADC_InitStruct->LowPowerMode
537 );
538
539 MODIFY_REG(ADCx->CFGR2,
540 ADC_CFGR2_CKMODE
541 ,
542 ADC_InitStruct->Clock
543 );
544 }
545 else
546 {
547 /* Initialization error: ADC instance is not disabled. */
548 status = ERROR;
549 }
550
551 return status;
552 }
553
554 /**
555 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
556 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
557 * whose fields will be set to default values.
558 * @retval None
559 */
LL_ADC_StructInit(LL_ADC_InitTypeDef * ADC_InitStruct)560 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
561 {
562 /* Set ADC_InitStruct fields to default values */
563 /* Set fields of ADC instance */
564 ADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
565 ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
566 ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
567 ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
568
569 }
570
571 /**
572 * @brief Initialize some features of ADC group regular.
573 * @note These parameters have an impact on ADC scope: ADC group regular.
574 * Refer to corresponding unitary functions into
575 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
576 * (functions with prefix "REG").
577 * @note The setting of these parameters by function @ref LL_ADC_Init()
578 * is conditioned to ADC state:
579 * ADC instance must be disabled.
580 * This condition is applied to all ADC features, for efficiency
581 * and compatibility over all STM32 families. However, the different
582 * features can be set under different ADC state conditions
583 * (setting possible with ADC enabled without conversion on going,
584 * ADC enabled with conversion on going, ...)
585 * Each feature can be updated afterwards with a unitary function
586 * and potentially with ADC in a different state than disabled,
587 * refer to description of each function for setting
588 * conditioned to ADC state.
589 * @note Before using this function, ADC group regular sequencer
590 * must be configured: refer to function
591 * @ref LL_ADC_REG_SetSequencerConfigurable().
592 * @note After using this function, other features must be configured
593 * using LL unitary functions.
594 * The minimum configuration remaining to be done is:
595 * - Set ADC group regular sequencer:
596 * Depending on the sequencer mode (refer to
597 * function @ref LL_ADC_REG_SetSequencerConfigurable() ):
598 * - map channel on the selected sequencer rank.
599 * Refer to function @ref LL_ADC_REG_SetSequencerRanks();
600 * - map channel on rank corresponding to channel number.
601 * Refer to function @ref LL_ADC_REG_SetSequencerChannels();
602 * - Set ADC channel sampling time
603 * Refer to function LL_ADC_SetSamplingTimeCommonChannels();
604 * Refer to function LL_ADC_SetChannelSamplingTime();
605 * @param ADCx ADC instance
606 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
607 * @retval An ErrorStatus enumeration value:
608 * - SUCCESS: ADC registers are initialized
609 * - ERROR: ADC registers are not initialized
610 */
LL_ADC_REG_Init(ADC_TypeDef * ADCx,LL_ADC_REG_InitTypeDef * ADC_REG_InitStruct)611 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
612 {
613 ErrorStatus status = SUCCESS;
614
615 /* Check the parameters */
616 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
617 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
618 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
619 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
620 assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
621
622 if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
623 {
624 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
625 }
626
627 if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
628 || (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
629 )
630 {
631 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
632
633 /* ADC group regular continuous mode and discontinuous mode */
634 /* can not be enabled simultenaeously */
635 assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
636 || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
637 }
638
639 /* Note: Hardware constraint (refer to description of this function): */
640 /* ADC instance must be disabled. */
641 if (LL_ADC_IsEnabled(ADCx) == 0UL)
642 {
643 /* Configuration of ADC hierarchical scope: */
644 /* - ADC group regular */
645 /* - Set ADC group regular trigger source */
646 /* - Set ADC group regular sequencer length */
647 /* - Set ADC group regular sequencer discontinuous mode */
648 /* - Set ADC group regular continuous mode */
649 /* - Set ADC group regular conversion data transfer: no transfer or */
650 /* transfer by DMA, and DMA requests mode */
651 /* - Set ADC group regular overrun behavior */
652 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
653 /* setting of trigger source to SW start. */
654 if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
655 || (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
656 )
657 {
658 /* Case of sequencer mode fixed
659 or sequencer length >= 2 ranks with sequencer mode fully configurable:
660 discontinuous mode configured */
661 MODIFY_REG(ADCx->CFGR1,
662 ADC_CFGR1_EXTSEL
663 | ADC_CFGR1_EXTEN
664 | ADC_CFGR1_DISCEN
665 | ADC_CFGR1_CONT
666 | ADC_CFGR1_DMAEN
667 | ADC_CFGR1_DMACFG
668 | ADC_CFGR1_OVRMOD
669 ,
670 ADC_REG_InitStruct->TriggerSource
671 | ADC_REG_InitStruct->SequencerDiscont
672 | ADC_REG_InitStruct->ContinuousMode
673 | ADC_REG_InitStruct->DMATransfer
674 | ADC_REG_InitStruct->Overrun
675 );
676 }
677 else
678 {
679 /* Case of sequencer mode fully configurable
680 and sequencer length 1 rank (sequencer disabled):
681 discontinuous mode discarded (fixed to disable) */
682 MODIFY_REG(ADCx->CFGR1,
683 ADC_CFGR1_EXTSEL
684 | ADC_CFGR1_EXTEN
685 | ADC_CFGR1_DISCEN
686 | ADC_CFGR1_CONT
687 | ADC_CFGR1_DMAEN
688 | ADC_CFGR1_DMACFG
689 | ADC_CFGR1_OVRMOD
690 ,
691 ADC_REG_InitStruct->TriggerSource
692 | LL_ADC_REG_SEQ_DISCONT_DISABLE
693 | ADC_REG_InitStruct->ContinuousMode
694 | ADC_REG_InitStruct->DMATransfer
695 | ADC_REG_InitStruct->Overrun
696 );
697 }
698
699 /* Set ADC group regular sequencer length */
700 if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
701 {
702 LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
703 }
704 }
705 else
706 {
707 /* Initialization error: ADC instance is not disabled. */
708 status = ERROR;
709 }
710 return status;
711 }
712
713 /**
714 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
715 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
716 * whose fields will be set to default values.
717 * @retval None
718 */
LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef * ADC_REG_InitStruct)719 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
720 {
721 /* Set ADC_REG_InitStruct fields to default values */
722 /* Set fields of ADC group regular */
723 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
724 /* setting of trigger source to SW start. */
725 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
726 ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
727 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
728 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
729 ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
730 ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
731 }
732
733 /**
734 * @}
735 */
736
737 /**
738 * @}
739 */
740
741 /**
742 * @}
743 */
744
745 #endif /* ADC1 */
746
747 /**
748 * @}
749 */
750
751 #endif /* USE_FULL_LL_DRIVER */
752
