1 /**
2 ******************************************************************************
3 * @file stm32c0xx_hal_tim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer (TIM) peripheral:
8 * + TIM Time Base Initialization
9 * + TIM Time Base Start
10 * + TIM Time Base Start Interruption
11 * + TIM Time Base Start DMA
12 * + TIM Output Compare/PWM Initialization
13 * + TIM Output Compare/PWM Channel Configuration
14 * + TIM Output Compare/PWM Start
15 * + TIM Output Compare/PWM Start Interruption
16 * + TIM Output Compare/PWM Start DMA
17 * + TIM Input Capture Initialization
18 * + TIM Input Capture Channel Configuration
19 * + TIM Input Capture Start
20 * + TIM Input Capture Start Interruption
21 * + TIM Input Capture Start DMA
22 * + TIM One Pulse Initialization
23 * + TIM One Pulse Channel Configuration
24 * + TIM One Pulse Start
25 * + TIM Encoder Interface Initialization
26 * + TIM Encoder Interface Start
27 * + TIM Encoder Interface Start Interruption
28 * + TIM Encoder Interface Start DMA
29 * + Commutation Event configuration with Interruption and DMA
30 * + TIM OCRef clear configuration
31 * + TIM External Clock configuration
32 ******************************************************************************
33 * @attention
34 *
35 * Copyright (c) 2022 STMicroelectronics.
36 * All rights reserved.
37 *
38 * This software is licensed under terms that can be found in the LICENSE file
39 * in the root directory of this software component.
40 * If no LICENSE file comes with this software, it is provided AS-IS.
41 *
42 ******************************************************************************
43 @verbatim
44 ==============================================================================
45 ##### TIMER Generic features #####
46 ==============================================================================
47 [..] The Timer features include:
48 (#) 16-bit up, down, up/down auto-reload counter.
49 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
50 counter clock frequency either by any factor between 1 and 65536.
51 (#) Up to 4 independent channels for:
52 (++) Input Capture
53 (++) Output Compare
54 (++) PWM generation (Edge and Center-aligned Mode)
55 (++) One-pulse mode output
56 (#) Synchronization circuit to control the timer with external signals and to interconnect
57 several timers together.
58 (#) Supports incremental encoder for positioning purposes
59
60 ##### How to use this driver #####
61 ==============================================================================
62 [..]
63 (#) Initialize the TIM low level resources by implementing the following functions
64 depending on the selected feature:
65 (++) Time Base : HAL_TIM_Base_MspInit()
66 (++) Input Capture : HAL_TIM_IC_MspInit()
67 (++) Output Compare : HAL_TIM_OC_MspInit()
68 (++) PWM generation : HAL_TIM_PWM_MspInit()
69 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
70 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
71
72 (#) Initialize the TIM low level resources :
73 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
74 (##) TIM pins configuration
75 (+++) Enable the clock for the TIM GPIOs using the following function:
76 __HAL_RCC_GPIOx_CLK_ENABLE();
77 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
78
79 (#) The external Clock can be configured, if needed (the default clock is the
80 internal clock from the APBx), using the following function:
81 HAL_TIM_ConfigClockSource, the clock configuration should be done before
82 any start function.
83
84 (#) Configure the TIM in the desired functioning mode using one of the
85 Initialization function of this driver:
86 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
87 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
88 Output Compare signal.
89 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
90 PWM signal.
91 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
92 external signal.
93 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
94 in One Pulse Mode.
95 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
96
97 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
98 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
99 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
100 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
101 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
102 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
103 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
104
105 (#) The DMA Burst is managed with the two following functions:
106 HAL_TIM_DMABurst_WriteStart()
107 HAL_TIM_DMABurst_ReadStart()
108
109 *** Callback registration ***
110 =============================================
111
112 [..]
113 The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
114 allows the user to configure dynamically the driver callbacks.
115
116 [..]
117 Use Function HAL_TIM_RegisterCallback() to register a callback.
118 HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
119 the Callback ID and a pointer to the user callback function.
120
121 [..]
122 Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
123 weak function.
124 HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
125 and the Callback ID.
126
127 [..]
128 These functions allow to register/unregister following callbacks:
129 (+) Base_MspInitCallback : TIM Base Msp Init Callback.
130 (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
131 (+) IC_MspInitCallback : TIM IC Msp Init Callback.
132 (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
133 (+) OC_MspInitCallback : TIM OC Msp Init Callback.
134 (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
135 (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
136 (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
137 (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
138 (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
139 (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
140 (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
141 (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.
142 (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.
143 (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
144 (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.
145 (+) TriggerCallback : TIM Trigger Callback.
146 (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
147 (+) IC_CaptureCallback : TIM Input Capture Callback.
148 (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.
149 (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
150 (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
151 (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
152 (+) ErrorCallback : TIM Error Callback.
153 (+) CommutationCallback : TIM Commutation Callback.
154 (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.
155 (+) BreakCallback : TIM Break Callback.
156 (+) Break2Callback : TIM Break2 Callback.
157
158 [..]
159 By default, after the Init and when the state is HAL_TIM_STATE_RESET
160 all interrupt callbacks are set to the corresponding weak functions:
161 examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
162
163 [..]
164 Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
165 functionalities in the Init / DeInit only when these callbacks are null
166 (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
167 keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
168
169 [..]
170 Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
171 Exception done MspInit / MspDeInit that can be registered / unregistered
172 in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
173 thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
174 In that case first register the MspInit/MspDeInit user callbacks
175 using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
176
177 [..]
178 When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
179 not defined, the callback registration feature is not available and all callbacks
180 are set to the corresponding weak functions.
181
182 @endverbatim
183 ******************************************************************************
184 */
185
186 /* Includes ------------------------------------------------------------------*/
187 #include "stm32c0xx_hal.h"
188
189 /** @addtogroup STM32C0xx_HAL_Driver
190 * @{
191 */
192
193 /** @defgroup TIM TIM
194 * @brief TIM HAL module driver
195 * @{
196 */
197
198 #ifdef HAL_TIM_MODULE_ENABLED
199
200 /* Private typedef -----------------------------------------------------------*/
201 /* Private define ------------------------------------------------------------*/
202 /** @addtogroup TIM_Private_Constants
203 * @{
204 */
205 #define TIMx_OR1_OCREF_CLR 0x00000001U
206 /**
207 * @}
208 */
209
210 /* Private macros ------------------------------------------------------------*/
211 /* Private variables ---------------------------------------------------------*/
212 /* Private function prototypes -----------------------------------------------*/
213 /** @addtogroup TIM_Private_Functions
214 * @{
215 */
216 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
217 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
218 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
219 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
220 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
221 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
222 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
223 uint32_t TIM_ICFilter);
224 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
225 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
226 uint32_t TIM_ICFilter);
227 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
228 uint32_t TIM_ICFilter);
229 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
230 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
231 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
232 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
233 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
234 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
235 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
236 const TIM_SlaveConfigTypeDef *sSlaveConfig);
237 /**
238 * @}
239 */
240 /* Exported functions --------------------------------------------------------*/
241
242 /** @defgroup TIM_Exported_Functions TIM Exported Functions
243 * @{
244 */
245
246 /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
247 * @brief Time Base functions
248 *
249 @verbatim
250 ==============================================================================
251 ##### Time Base functions #####
252 ==============================================================================
253 [..]
254 This section provides functions allowing to:
255 (+) Initialize and configure the TIM base.
256 (+) De-initialize the TIM base.
257 (+) Start the Time Base.
258 (+) Stop the Time Base.
259 (+) Start the Time Base and enable interrupt.
260 (+) Stop the Time Base and disable interrupt.
261 (+) Start the Time Base and enable DMA transfer.
262 (+) Stop the Time Base and disable DMA transfer.
263
264 @endverbatim
265 * @{
266 */
267 /**
268 * @brief Initializes the TIM Time base Unit according to the specified
269 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
270 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
271 * requires a timer reset to avoid unexpected direction
272 * due to DIR bit readonly in center aligned mode.
273 * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
274 * @param htim TIM Base handle
275 * @retval HAL status
276 */
HAL_TIM_Base_Init(TIM_HandleTypeDef * htim)277 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
278 {
279 /* Check the TIM handle allocation */
280 if (htim == NULL)
281 {
282 return HAL_ERROR;
283 }
284
285 /* Check the parameters */
286 assert_param(IS_TIM_INSTANCE(htim->Instance));
287 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
288 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
289 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
290 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
291
292 if (htim->State == HAL_TIM_STATE_RESET)
293 {
294 /* Allocate lock resource and initialize it */
295 htim->Lock = HAL_UNLOCKED;
296
297 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
298 /* Reset interrupt callbacks to legacy weak callbacks */
299 TIM_ResetCallback(htim);
300
301 if (htim->Base_MspInitCallback == NULL)
302 {
303 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
304 }
305 /* Init the low level hardware : GPIO, CLOCK, NVIC */
306 htim->Base_MspInitCallback(htim);
307 #else
308 /* Init the low level hardware : GPIO, CLOCK, NVIC */
309 HAL_TIM_Base_MspInit(htim);
310 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
311 }
312
313 /* Set the TIM state */
314 htim->State = HAL_TIM_STATE_BUSY;
315
316 /* Set the Time Base configuration */
317 TIM_Base_SetConfig(htim->Instance, &htim->Init);
318
319 /* Initialize the DMA burst operation state */
320 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
321
322 /* Initialize the TIM channels state */
323 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
324 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
325
326 /* Initialize the TIM state*/
327 htim->State = HAL_TIM_STATE_READY;
328
329 return HAL_OK;
330 }
331
332 /**
333 * @brief DeInitializes the TIM Base peripheral
334 * @param htim TIM Base handle
335 * @retval HAL status
336 */
HAL_TIM_Base_DeInit(TIM_HandleTypeDef * htim)337 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
338 {
339 /* Check the parameters */
340 assert_param(IS_TIM_INSTANCE(htim->Instance));
341
342 htim->State = HAL_TIM_STATE_BUSY;
343
344 /* Disable the TIM Peripheral Clock */
345 __HAL_TIM_DISABLE(htim);
346
347 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
348 if (htim->Base_MspDeInitCallback == NULL)
349 {
350 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
351 }
352 /* DeInit the low level hardware */
353 htim->Base_MspDeInitCallback(htim);
354 #else
355 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
356 HAL_TIM_Base_MspDeInit(htim);
357 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
358
359 /* Change the DMA burst operation state */
360 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
361
362 /* Change the TIM channels state */
363 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
364 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
365
366 /* Change TIM state */
367 htim->State = HAL_TIM_STATE_RESET;
368
369 /* Release Lock */
370 __HAL_UNLOCK(htim);
371
372 return HAL_OK;
373 }
374
375 /**
376 * @brief Initializes the TIM Base MSP.
377 * @param htim TIM Base handle
378 * @retval None
379 */
HAL_TIM_Base_MspInit(TIM_HandleTypeDef * htim)380 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
381 {
382 /* Prevent unused argument(s) compilation warning */
383 UNUSED(htim);
384
385 /* NOTE : This function should not be modified, when the callback is needed,
386 the HAL_TIM_Base_MspInit could be implemented in the user file
387 */
388 }
389
390 /**
391 * @brief DeInitializes TIM Base MSP.
392 * @param htim TIM Base handle
393 * @retval None
394 */
HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef * htim)395 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
396 {
397 /* Prevent unused argument(s) compilation warning */
398 UNUSED(htim);
399
400 /* NOTE : This function should not be modified, when the callback is needed,
401 the HAL_TIM_Base_MspDeInit could be implemented in the user file
402 */
403 }
404
405
406 /**
407 * @brief Starts the TIM Base generation.
408 * @param htim TIM Base handle
409 * @retval HAL status
410 */
HAL_TIM_Base_Start(TIM_HandleTypeDef * htim)411 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
412 {
413 uint32_t tmpsmcr;
414
415 /* Check the parameters */
416 assert_param(IS_TIM_INSTANCE(htim->Instance));
417
418 /* Check the TIM state */
419 if (htim->State != HAL_TIM_STATE_READY)
420 {
421 return HAL_ERROR;
422 }
423
424 /* Set the TIM state */
425 htim->State = HAL_TIM_STATE_BUSY;
426
427 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
428 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
429 {
430 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
431 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
432 {
433 __HAL_TIM_ENABLE(htim);
434 }
435 }
436 else
437 {
438 __HAL_TIM_ENABLE(htim);
439 }
440
441 /* Return function status */
442 return HAL_OK;
443 }
444
445 /**
446 * @brief Stops the TIM Base generation.
447 * @param htim TIM Base handle
448 * @retval HAL status
449 */
HAL_TIM_Base_Stop(TIM_HandleTypeDef * htim)450 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
451 {
452 /* Check the parameters */
453 assert_param(IS_TIM_INSTANCE(htim->Instance));
454
455 /* Disable the Peripheral */
456 __HAL_TIM_DISABLE(htim);
457
458 /* Set the TIM state */
459 htim->State = HAL_TIM_STATE_READY;
460
461 /* Return function status */
462 return HAL_OK;
463 }
464
465 /**
466 * @brief Starts the TIM Base generation in interrupt mode.
467 * @param htim TIM Base handle
468 * @retval HAL status
469 */
HAL_TIM_Base_Start_IT(TIM_HandleTypeDef * htim)470 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
471 {
472 uint32_t tmpsmcr;
473
474 /* Check the parameters */
475 assert_param(IS_TIM_INSTANCE(htim->Instance));
476
477 /* Check the TIM state */
478 if (htim->State != HAL_TIM_STATE_READY)
479 {
480 return HAL_ERROR;
481 }
482
483 /* Set the TIM state */
484 htim->State = HAL_TIM_STATE_BUSY;
485
486 /* Enable the TIM Update interrupt */
487 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
488
489 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
490 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
491 {
492 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
493 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
494 {
495 __HAL_TIM_ENABLE(htim);
496 }
497 }
498 else
499 {
500 __HAL_TIM_ENABLE(htim);
501 }
502
503 /* Return function status */
504 return HAL_OK;
505 }
506
507 /**
508 * @brief Stops the TIM Base generation in interrupt mode.
509 * @param htim TIM Base handle
510 * @retval HAL status
511 */
HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef * htim)512 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
513 {
514 /* Check the parameters */
515 assert_param(IS_TIM_INSTANCE(htim->Instance));
516
517 /* Disable the TIM Update interrupt */
518 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
519
520 /* Disable the Peripheral */
521 __HAL_TIM_DISABLE(htim);
522
523 /* Set the TIM state */
524 htim->State = HAL_TIM_STATE_READY;
525
526 /* Return function status */
527 return HAL_OK;
528 }
529
530 /**
531 * @brief Starts the TIM Base generation in DMA mode.
532 * @param htim TIM Base handle
533 * @param pData The source Buffer address.
534 * @param Length The length of data to be transferred from memory to peripheral.
535 * @retval HAL status
536 */
HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef * htim,const uint32_t * pData,uint16_t Length)537 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length)
538 {
539 uint32_t tmpsmcr;
540
541 /* Check the parameters */
542 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
543
544 /* Set the TIM state */
545 if (htim->State == HAL_TIM_STATE_BUSY)
546 {
547 return HAL_BUSY;
548 }
549 else if (htim->State == HAL_TIM_STATE_READY)
550 {
551 if ((pData == NULL) || (Length == 0U))
552 {
553 return HAL_ERROR;
554 }
555 else
556 {
557 htim->State = HAL_TIM_STATE_BUSY;
558 }
559 }
560 else
561 {
562 return HAL_ERROR;
563 }
564
565 /* Set the DMA Period elapsed callbacks */
566 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
567 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
568
569 /* Set the DMA error callback */
570 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
571
572 /* Enable the DMA channel */
573 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
574 Length) != HAL_OK)
575 {
576 /* Return error status */
577 return HAL_ERROR;
578 }
579
580 /* Enable the TIM Update DMA request */
581 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
582
583 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
584 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
585 {
586 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
587 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
588 {
589 __HAL_TIM_ENABLE(htim);
590 }
591 }
592 else
593 {
594 __HAL_TIM_ENABLE(htim);
595 }
596
597 /* Return function status */
598 return HAL_OK;
599 }
600
601 /**
602 * @brief Stops the TIM Base generation in DMA mode.
603 * @param htim TIM Base handle
604 * @retval HAL status
605 */
HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef * htim)606 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
607 {
608 /* Check the parameters */
609 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
610
611 /* Disable the TIM Update DMA request */
612 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
613
614 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
615
616 /* Disable the Peripheral */
617 __HAL_TIM_DISABLE(htim);
618
619 /* Set the TIM state */
620 htim->State = HAL_TIM_STATE_READY;
621
622 /* Return function status */
623 return HAL_OK;
624 }
625
626 /**
627 * @}
628 */
629
630 /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
631 * @brief TIM Output Compare functions
632 *
633 @verbatim
634 ==============================================================================
635 ##### TIM Output Compare functions #####
636 ==============================================================================
637 [..]
638 This section provides functions allowing to:
639 (+) Initialize and configure the TIM Output Compare.
640 (+) De-initialize the TIM Output Compare.
641 (+) Start the TIM Output Compare.
642 (+) Stop the TIM Output Compare.
643 (+) Start the TIM Output Compare and enable interrupt.
644 (+) Stop the TIM Output Compare and disable interrupt.
645 (+) Start the TIM Output Compare and enable DMA transfer.
646 (+) Stop the TIM Output Compare and disable DMA transfer.
647
648 @endverbatim
649 * @{
650 */
651 /**
652 * @brief Initializes the TIM Output Compare according to the specified
653 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
654 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
655 * requires a timer reset to avoid unexpected direction
656 * due to DIR bit readonly in center aligned mode.
657 * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
658 * @param htim TIM Output Compare handle
659 * @retval HAL status
660 */
HAL_TIM_OC_Init(TIM_HandleTypeDef * htim)661 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
662 {
663 /* Check the TIM handle allocation */
664 if (htim == NULL)
665 {
666 return HAL_ERROR;
667 }
668
669 /* Check the parameters */
670 assert_param(IS_TIM_INSTANCE(htim->Instance));
671 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
672 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
673 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
674 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
675
676 if (htim->State == HAL_TIM_STATE_RESET)
677 {
678 /* Allocate lock resource and initialize it */
679 htim->Lock = HAL_UNLOCKED;
680
681 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
682 /* Reset interrupt callbacks to legacy weak callbacks */
683 TIM_ResetCallback(htim);
684
685 if (htim->OC_MspInitCallback == NULL)
686 {
687 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
688 }
689 /* Init the low level hardware : GPIO, CLOCK, NVIC */
690 htim->OC_MspInitCallback(htim);
691 #else
692 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
693 HAL_TIM_OC_MspInit(htim);
694 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
695 }
696
697 /* Set the TIM state */
698 htim->State = HAL_TIM_STATE_BUSY;
699
700 /* Init the base time for the Output Compare */
701 TIM_Base_SetConfig(htim->Instance, &htim->Init);
702
703 /* Initialize the DMA burst operation state */
704 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
705
706 /* Initialize the TIM channels state */
707 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
708 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
709
710 /* Initialize the TIM state*/
711 htim->State = HAL_TIM_STATE_READY;
712
713 return HAL_OK;
714 }
715
716 /**
717 * @brief DeInitializes the TIM peripheral
718 * @param htim TIM Output Compare handle
719 * @retval HAL status
720 */
HAL_TIM_OC_DeInit(TIM_HandleTypeDef * htim)721 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
722 {
723 /* Check the parameters */
724 assert_param(IS_TIM_INSTANCE(htim->Instance));
725
726 htim->State = HAL_TIM_STATE_BUSY;
727
728 /* Disable the TIM Peripheral Clock */
729 __HAL_TIM_DISABLE(htim);
730
731 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
732 if (htim->OC_MspDeInitCallback == NULL)
733 {
734 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
735 }
736 /* DeInit the low level hardware */
737 htim->OC_MspDeInitCallback(htim);
738 #else
739 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
740 HAL_TIM_OC_MspDeInit(htim);
741 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
742
743 /* Change the DMA burst operation state */
744 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
745
746 /* Change the TIM channels state */
747 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
748 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
749
750 /* Change TIM state */
751 htim->State = HAL_TIM_STATE_RESET;
752
753 /* Release Lock */
754 __HAL_UNLOCK(htim);
755
756 return HAL_OK;
757 }
758
759 /**
760 * @brief Initializes the TIM Output Compare MSP.
761 * @param htim TIM Output Compare handle
762 * @retval None
763 */
HAL_TIM_OC_MspInit(TIM_HandleTypeDef * htim)764 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
765 {
766 /* Prevent unused argument(s) compilation warning */
767 UNUSED(htim);
768
769 /* NOTE : This function should not be modified, when the callback is needed,
770 the HAL_TIM_OC_MspInit could be implemented in the user file
771 */
772 }
773
774 /**
775 * @brief DeInitializes TIM Output Compare MSP.
776 * @param htim TIM Output Compare handle
777 * @retval None
778 */
HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef * htim)779 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
780 {
781 /* Prevent unused argument(s) compilation warning */
782 UNUSED(htim);
783
784 /* NOTE : This function should not be modified, when the callback is needed,
785 the HAL_TIM_OC_MspDeInit could be implemented in the user file
786 */
787 }
788
789 /**
790 * @brief Starts the TIM Output Compare signal generation.
791 * @param htim TIM Output Compare handle
792 * @param Channel TIM Channel to be enabled
793 * This parameter can be one of the following values:
794 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
795 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
796 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
797 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
798 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
799 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
800 * @retval HAL status
801 */
HAL_TIM_OC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)802 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
803 {
804 uint32_t tmpsmcr;
805
806 /* Check the parameters */
807 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
808
809 /* Check the TIM channel state */
810 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
811 {
812 return HAL_ERROR;
813 }
814
815 /* Set the TIM channel state */
816 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
817
818 /* Enable the Output compare channel */
819 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
820
821 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
822 {
823 /* Enable the main output */
824 __HAL_TIM_MOE_ENABLE(htim);
825 }
826
827 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
828 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
829 {
830 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
831 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
832 {
833 __HAL_TIM_ENABLE(htim);
834 }
835 }
836 else
837 {
838 __HAL_TIM_ENABLE(htim);
839 }
840
841 /* Return function status */
842 return HAL_OK;
843 }
844
845 /**
846 * @brief Stops the TIM Output Compare signal generation.
847 * @param htim TIM Output Compare handle
848 * @param Channel TIM Channel to be disabled
849 * This parameter can be one of the following values:
850 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
851 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
852 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
853 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
854 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
855 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
856 * @retval HAL status
857 */
HAL_TIM_OC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)858 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
859 {
860 /* Check the parameters */
861 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
862
863 /* Disable the Output compare channel */
864 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
865
866 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
867 {
868 /* Disable the Main Output */
869 __HAL_TIM_MOE_DISABLE(htim);
870 }
871
872 /* Disable the Peripheral */
873 __HAL_TIM_DISABLE(htim);
874
875 /* Set the TIM channel state */
876 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
877
878 /* Return function status */
879 return HAL_OK;
880 }
881
882 /**
883 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
884 * @param htim TIM Output Compare handle
885 * @param Channel TIM Channel to be enabled
886 * This parameter can be one of the following values:
887 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
888 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
889 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
890 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
891 * @retval HAL status
892 */
HAL_TIM_OC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)893 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
894 {
895 HAL_StatusTypeDef status = HAL_OK;
896 uint32_t tmpsmcr;
897
898 /* Check the parameters */
899 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
900
901 /* Check the TIM channel state */
902 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
903 {
904 return HAL_ERROR;
905 }
906
907 /* Set the TIM channel state */
908 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
909
910 switch (Channel)
911 {
912 case TIM_CHANNEL_1:
913 {
914 /* Enable the TIM Capture/Compare 1 interrupt */
915 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
916 break;
917 }
918
919 case TIM_CHANNEL_2:
920 {
921 /* Enable the TIM Capture/Compare 2 interrupt */
922 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
923 break;
924 }
925
926 case TIM_CHANNEL_3:
927 {
928 /* Enable the TIM Capture/Compare 3 interrupt */
929 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
930 break;
931 }
932
933 case TIM_CHANNEL_4:
934 {
935 /* Enable the TIM Capture/Compare 4 interrupt */
936 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
937 break;
938 }
939
940 default:
941 status = HAL_ERROR;
942 break;
943 }
944
945 if (status == HAL_OK)
946 {
947 /* Enable the Output compare channel */
948 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
949
950 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
951 {
952 /* Enable the main output */
953 __HAL_TIM_MOE_ENABLE(htim);
954 }
955
956 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
957 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
958 {
959 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
960 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
961 {
962 __HAL_TIM_ENABLE(htim);
963 }
964 }
965 else
966 {
967 __HAL_TIM_ENABLE(htim);
968 }
969 }
970
971 /* Return function status */
972 return status;
973 }
974
975 /**
976 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
977 * @param htim TIM Output Compare handle
978 * @param Channel TIM Channel to be disabled
979 * This parameter can be one of the following values:
980 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
981 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
982 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
983 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
984 * @retval HAL status
985 */
HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)986 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
987 {
988 HAL_StatusTypeDef status = HAL_OK;
989
990 /* Check the parameters */
991 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
992
993 switch (Channel)
994 {
995 case TIM_CHANNEL_1:
996 {
997 /* Disable the TIM Capture/Compare 1 interrupt */
998 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
999 break;
1000 }
1001
1002 case TIM_CHANNEL_2:
1003 {
1004 /* Disable the TIM Capture/Compare 2 interrupt */
1005 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1006 break;
1007 }
1008
1009 case TIM_CHANNEL_3:
1010 {
1011 /* Disable the TIM Capture/Compare 3 interrupt */
1012 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1013 break;
1014 }
1015
1016 case TIM_CHANNEL_4:
1017 {
1018 /* Disable the TIM Capture/Compare 4 interrupt */
1019 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1020 break;
1021 }
1022
1023 default:
1024 status = HAL_ERROR;
1025 break;
1026 }
1027
1028 if (status == HAL_OK)
1029 {
1030 /* Disable the Output compare channel */
1031 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1032
1033 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1034 {
1035 /* Disable the Main Output */
1036 __HAL_TIM_MOE_DISABLE(htim);
1037 }
1038
1039 /* Disable the Peripheral */
1040 __HAL_TIM_DISABLE(htim);
1041
1042 /* Set the TIM channel state */
1043 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1044 }
1045
1046 /* Return function status */
1047 return status;
1048 }
1049
1050 /**
1051 * @brief Starts the TIM Output Compare signal generation in DMA mode.
1052 * @param htim TIM Output Compare handle
1053 * @param Channel TIM Channel to be enabled
1054 * This parameter can be one of the following values:
1055 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1056 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1057 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1058 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1059 * @param pData The source Buffer address.
1060 * @param Length The length of data to be transferred from memory to TIM peripheral
1061 * @retval HAL status
1062 */
HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1063 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1064 uint16_t Length)
1065 {
1066 HAL_StatusTypeDef status = HAL_OK;
1067 uint32_t tmpsmcr;
1068
1069 /* Check the parameters */
1070 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1071
1072 /* Set the TIM channel state */
1073 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1074 {
1075 return HAL_BUSY;
1076 }
1077 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1078 {
1079 if ((pData == NULL) || (Length == 0U))
1080 {
1081 return HAL_ERROR;
1082 }
1083 else
1084 {
1085 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1086 }
1087 }
1088 else
1089 {
1090 return HAL_ERROR;
1091 }
1092
1093 switch (Channel)
1094 {
1095 case TIM_CHANNEL_1:
1096 {
1097 /* Set the DMA compare callbacks */
1098 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1099 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1100
1101 /* Set the DMA error callback */
1102 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1103
1104 /* Enable the DMA channel */
1105 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1106 Length) != HAL_OK)
1107 {
1108 /* Return error status */
1109 return HAL_ERROR;
1110 }
1111
1112 /* Enable the TIM Capture/Compare 1 DMA request */
1113 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1114 break;
1115 }
1116
1117 case TIM_CHANNEL_2:
1118 {
1119 /* Set the DMA compare callbacks */
1120 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1121 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1122
1123 /* Set the DMA error callback */
1124 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1125
1126 /* Enable the DMA channel */
1127 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1128 Length) != HAL_OK)
1129 {
1130 /* Return error status */
1131 return HAL_ERROR;
1132 }
1133
1134 /* Enable the TIM Capture/Compare 2 DMA request */
1135 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1136 break;
1137 }
1138
1139 case TIM_CHANNEL_3:
1140 {
1141 /* Set the DMA compare callbacks */
1142 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1143 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1144
1145 /* Set the DMA error callback */
1146 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1147
1148 /* Enable the DMA channel */
1149 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1150 Length) != HAL_OK)
1151 {
1152 /* Return error status */
1153 return HAL_ERROR;
1154 }
1155 /* Enable the TIM Capture/Compare 3 DMA request */
1156 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1157 break;
1158 }
1159
1160 case TIM_CHANNEL_4:
1161 {
1162 /* Set the DMA compare callbacks */
1163 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1164 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1165
1166 /* Set the DMA error callback */
1167 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1168
1169 /* Enable the DMA channel */
1170 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1171 Length) != HAL_OK)
1172 {
1173 /* Return error status */
1174 return HAL_ERROR;
1175 }
1176 /* Enable the TIM Capture/Compare 4 DMA request */
1177 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1178 break;
1179 }
1180
1181 default:
1182 status = HAL_ERROR;
1183 break;
1184 }
1185
1186 if (status == HAL_OK)
1187 {
1188 /* Enable the Output compare channel */
1189 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1190
1191 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1192 {
1193 /* Enable the main output */
1194 __HAL_TIM_MOE_ENABLE(htim);
1195 }
1196
1197 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1198 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1199 {
1200 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1201 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1202 {
1203 __HAL_TIM_ENABLE(htim);
1204 }
1205 }
1206 else
1207 {
1208 __HAL_TIM_ENABLE(htim);
1209 }
1210 }
1211
1212 /* Return function status */
1213 return status;
1214 }
1215
1216 /**
1217 * @brief Stops the TIM Output Compare signal generation in DMA mode.
1218 * @param htim TIM Output Compare handle
1219 * @param Channel TIM Channel to be disabled
1220 * This parameter can be one of the following values:
1221 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1222 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1223 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1224 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1225 * @retval HAL status
1226 */
HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1227 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1228 {
1229 HAL_StatusTypeDef status = HAL_OK;
1230
1231 /* Check the parameters */
1232 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1233
1234 switch (Channel)
1235 {
1236 case TIM_CHANNEL_1:
1237 {
1238 /* Disable the TIM Capture/Compare 1 DMA request */
1239 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1240 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1241 break;
1242 }
1243
1244 case TIM_CHANNEL_2:
1245 {
1246 /* Disable the TIM Capture/Compare 2 DMA request */
1247 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1248 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1249 break;
1250 }
1251
1252 case TIM_CHANNEL_3:
1253 {
1254 /* Disable the TIM Capture/Compare 3 DMA request */
1255 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1256 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1257 break;
1258 }
1259
1260 case TIM_CHANNEL_4:
1261 {
1262 /* Disable the TIM Capture/Compare 4 interrupt */
1263 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1264 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1265 break;
1266 }
1267
1268 default:
1269 status = HAL_ERROR;
1270 break;
1271 }
1272
1273 if (status == HAL_OK)
1274 {
1275 /* Disable the Output compare channel */
1276 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1277
1278 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1279 {
1280 /* Disable the Main Output */
1281 __HAL_TIM_MOE_DISABLE(htim);
1282 }
1283
1284 /* Disable the Peripheral */
1285 __HAL_TIM_DISABLE(htim);
1286
1287 /* Set the TIM channel state */
1288 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1289 }
1290
1291 /* Return function status */
1292 return status;
1293 }
1294
1295 /**
1296 * @}
1297 */
1298
1299 /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
1300 * @brief TIM PWM functions
1301 *
1302 @verbatim
1303 ==============================================================================
1304 ##### TIM PWM functions #####
1305 ==============================================================================
1306 [..]
1307 This section provides functions allowing to:
1308 (+) Initialize and configure the TIM PWM.
1309 (+) De-initialize the TIM PWM.
1310 (+) Start the TIM PWM.
1311 (+) Stop the TIM PWM.
1312 (+) Start the TIM PWM and enable interrupt.
1313 (+) Stop the TIM PWM and disable interrupt.
1314 (+) Start the TIM PWM and enable DMA transfer.
1315 (+) Stop the TIM PWM and disable DMA transfer.
1316
1317 @endverbatim
1318 * @{
1319 */
1320 /**
1321 * @brief Initializes the TIM PWM Time Base according to the specified
1322 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1323 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1324 * requires a timer reset to avoid unexpected direction
1325 * due to DIR bit readonly in center aligned mode.
1326 * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
1327 * @param htim TIM PWM handle
1328 * @retval HAL status
1329 */
HAL_TIM_PWM_Init(TIM_HandleTypeDef * htim)1330 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
1331 {
1332 /* Check the TIM handle allocation */
1333 if (htim == NULL)
1334 {
1335 return HAL_ERROR;
1336 }
1337
1338 /* Check the parameters */
1339 assert_param(IS_TIM_INSTANCE(htim->Instance));
1340 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1341 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1342 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
1343 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1344
1345 if (htim->State == HAL_TIM_STATE_RESET)
1346 {
1347 /* Allocate lock resource and initialize it */
1348 htim->Lock = HAL_UNLOCKED;
1349
1350 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1351 /* Reset interrupt callbacks to legacy weak callbacks */
1352 TIM_ResetCallback(htim);
1353
1354 if (htim->PWM_MspInitCallback == NULL)
1355 {
1356 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
1357 }
1358 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1359 htim->PWM_MspInitCallback(htim);
1360 #else
1361 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1362 HAL_TIM_PWM_MspInit(htim);
1363 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1364 }
1365
1366 /* Set the TIM state */
1367 htim->State = HAL_TIM_STATE_BUSY;
1368
1369 /* Init the base time for the PWM */
1370 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1371
1372 /* Initialize the DMA burst operation state */
1373 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
1374
1375 /* Initialize the TIM channels state */
1376 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1377 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1378
1379 /* Initialize the TIM state*/
1380 htim->State = HAL_TIM_STATE_READY;
1381
1382 return HAL_OK;
1383 }
1384
1385 /**
1386 * @brief DeInitializes the TIM peripheral
1387 * @param htim TIM PWM handle
1388 * @retval HAL status
1389 */
HAL_TIM_PWM_DeInit(TIM_HandleTypeDef * htim)1390 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
1391 {
1392 /* Check the parameters */
1393 assert_param(IS_TIM_INSTANCE(htim->Instance));
1394
1395 htim->State = HAL_TIM_STATE_BUSY;
1396
1397 /* Disable the TIM Peripheral Clock */
1398 __HAL_TIM_DISABLE(htim);
1399
1400 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1401 if (htim->PWM_MspDeInitCallback == NULL)
1402 {
1403 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
1404 }
1405 /* DeInit the low level hardware */
1406 htim->PWM_MspDeInitCallback(htim);
1407 #else
1408 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1409 HAL_TIM_PWM_MspDeInit(htim);
1410 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1411
1412 /* Change the DMA burst operation state */
1413 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
1414
1415 /* Change the TIM channels state */
1416 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1417 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1418
1419 /* Change TIM state */
1420 htim->State = HAL_TIM_STATE_RESET;
1421
1422 /* Release Lock */
1423 __HAL_UNLOCK(htim);
1424
1425 return HAL_OK;
1426 }
1427
1428 /**
1429 * @brief Initializes the TIM PWM MSP.
1430 * @param htim TIM PWM handle
1431 * @retval None
1432 */
HAL_TIM_PWM_MspInit(TIM_HandleTypeDef * htim)1433 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1434 {
1435 /* Prevent unused argument(s) compilation warning */
1436 UNUSED(htim);
1437
1438 /* NOTE : This function should not be modified, when the callback is needed,
1439 the HAL_TIM_PWM_MspInit could be implemented in the user file
1440 */
1441 }
1442
1443 /**
1444 * @brief DeInitializes TIM PWM MSP.
1445 * @param htim TIM PWM handle
1446 * @retval None
1447 */
HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef * htim)1448 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1449 {
1450 /* Prevent unused argument(s) compilation warning */
1451 UNUSED(htim);
1452
1453 /* NOTE : This function should not be modified, when the callback is needed,
1454 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1455 */
1456 }
1457
1458 /**
1459 * @brief Starts the PWM signal generation.
1460 * @param htim TIM handle
1461 * @param Channel TIM Channels to be enabled
1462 * This parameter can be one of the following values:
1463 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1464 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1465 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1466 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1467 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1468 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1469 * @retval HAL status
1470 */
HAL_TIM_PWM_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1471 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1472 {
1473 uint32_t tmpsmcr;
1474
1475 /* Check the parameters */
1476 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1477
1478 /* Check the TIM channel state */
1479 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1480 {
1481 return HAL_ERROR;
1482 }
1483
1484 /* Set the TIM channel state */
1485 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1486
1487 /* Enable the Capture compare channel */
1488 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1489
1490 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1491 {
1492 /* Enable the main output */
1493 __HAL_TIM_MOE_ENABLE(htim);
1494 }
1495
1496 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1497 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1498 {
1499 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1500 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1501 {
1502 __HAL_TIM_ENABLE(htim);
1503 }
1504 }
1505 else
1506 {
1507 __HAL_TIM_ENABLE(htim);
1508 }
1509
1510 /* Return function status */
1511 return HAL_OK;
1512 }
1513
1514 /**
1515 * @brief Stops the PWM signal generation.
1516 * @param htim TIM PWM handle
1517 * @param Channel TIM Channels to be disabled
1518 * This parameter can be one of the following values:
1519 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1520 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1521 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1522 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1523 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1524 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1525 * @retval HAL status
1526 */
HAL_TIM_PWM_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1527 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1528 {
1529 /* Check the parameters */
1530 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1531
1532 /* Disable the Capture compare channel */
1533 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1534
1535 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1536 {
1537 /* Disable the Main Output */
1538 __HAL_TIM_MOE_DISABLE(htim);
1539 }
1540
1541 /* Disable the Peripheral */
1542 __HAL_TIM_DISABLE(htim);
1543
1544 /* Set the TIM channel state */
1545 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1546
1547 /* Return function status */
1548 return HAL_OK;
1549 }
1550
1551 /**
1552 * @brief Starts the PWM signal generation in interrupt mode.
1553 * @param htim TIM PWM handle
1554 * @param Channel TIM Channel to be enabled
1555 * This parameter can be one of the following values:
1556 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1557 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1558 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1559 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1560 * @retval HAL status
1561 */
HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1562 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1563 {
1564 HAL_StatusTypeDef status = HAL_OK;
1565 uint32_t tmpsmcr;
1566
1567 /* Check the parameters */
1568 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1569
1570 /* Check the TIM channel state */
1571 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1572 {
1573 return HAL_ERROR;
1574 }
1575
1576 /* Set the TIM channel state */
1577 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1578
1579 switch (Channel)
1580 {
1581 case TIM_CHANNEL_1:
1582 {
1583 /* Enable the TIM Capture/Compare 1 interrupt */
1584 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1585 break;
1586 }
1587
1588 case TIM_CHANNEL_2:
1589 {
1590 /* Enable the TIM Capture/Compare 2 interrupt */
1591 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1592 break;
1593 }
1594
1595 case TIM_CHANNEL_3:
1596 {
1597 /* Enable the TIM Capture/Compare 3 interrupt */
1598 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1599 break;
1600 }
1601
1602 case TIM_CHANNEL_4:
1603 {
1604 /* Enable the TIM Capture/Compare 4 interrupt */
1605 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1606 break;
1607 }
1608
1609 default:
1610 status = HAL_ERROR;
1611 break;
1612 }
1613
1614 if (status == HAL_OK)
1615 {
1616 /* Enable the Capture compare channel */
1617 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1618
1619 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1620 {
1621 /* Enable the main output */
1622 __HAL_TIM_MOE_ENABLE(htim);
1623 }
1624
1625 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1626 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1627 {
1628 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1629 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1630 {
1631 __HAL_TIM_ENABLE(htim);
1632 }
1633 }
1634 else
1635 {
1636 __HAL_TIM_ENABLE(htim);
1637 }
1638 }
1639
1640 /* Return function status */
1641 return status;
1642 }
1643
1644 /**
1645 * @brief Stops the PWM signal generation in interrupt mode.
1646 * @param htim TIM PWM handle
1647 * @param Channel TIM Channels to be disabled
1648 * This parameter can be one of the following values:
1649 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1650 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1651 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1652 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1653 * @retval HAL status
1654 */
HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1655 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1656 {
1657 HAL_StatusTypeDef status = HAL_OK;
1658
1659 /* Check the parameters */
1660 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1661
1662 switch (Channel)
1663 {
1664 case TIM_CHANNEL_1:
1665 {
1666 /* Disable the TIM Capture/Compare 1 interrupt */
1667 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1668 break;
1669 }
1670
1671 case TIM_CHANNEL_2:
1672 {
1673 /* Disable the TIM Capture/Compare 2 interrupt */
1674 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1675 break;
1676 }
1677
1678 case TIM_CHANNEL_3:
1679 {
1680 /* Disable the TIM Capture/Compare 3 interrupt */
1681 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1682 break;
1683 }
1684
1685 case TIM_CHANNEL_4:
1686 {
1687 /* Disable the TIM Capture/Compare 4 interrupt */
1688 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1689 break;
1690 }
1691
1692 default:
1693 status = HAL_ERROR;
1694 break;
1695 }
1696
1697 if (status == HAL_OK)
1698 {
1699 /* Disable the Capture compare channel */
1700 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1701
1702 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1703 {
1704 /* Disable the Main Output */
1705 __HAL_TIM_MOE_DISABLE(htim);
1706 }
1707
1708 /* Disable the Peripheral */
1709 __HAL_TIM_DISABLE(htim);
1710
1711 /* Set the TIM channel state */
1712 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1713 }
1714
1715 /* Return function status */
1716 return status;
1717 }
1718
1719 /**
1720 * @brief Starts the TIM PWM signal generation in DMA mode.
1721 * @param htim TIM PWM handle
1722 * @param Channel TIM Channels to be enabled
1723 * This parameter can be one of the following values:
1724 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1725 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1726 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1727 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1728 * @param pData The source Buffer address.
1729 * @param Length The length of data to be transferred from memory to TIM peripheral
1730 * @retval HAL status
1731 */
HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1732 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1733 uint16_t Length)
1734 {
1735 HAL_StatusTypeDef status = HAL_OK;
1736 uint32_t tmpsmcr;
1737
1738 /* Check the parameters */
1739 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1740
1741 /* Set the TIM channel state */
1742 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1743 {
1744 return HAL_BUSY;
1745 }
1746 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1747 {
1748 if ((pData == NULL) || (Length == 0U))
1749 {
1750 return HAL_ERROR;
1751 }
1752 else
1753 {
1754 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1755 }
1756 }
1757 else
1758 {
1759 return HAL_ERROR;
1760 }
1761
1762 switch (Channel)
1763 {
1764 case TIM_CHANNEL_1:
1765 {
1766 /* Set the DMA compare callbacks */
1767 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1768 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1769
1770 /* Set the DMA error callback */
1771 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1772
1773 /* Enable the DMA channel */
1774 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1775 Length) != HAL_OK)
1776 {
1777 /* Return error status */
1778 return HAL_ERROR;
1779 }
1780
1781 /* Enable the TIM Capture/Compare 1 DMA request */
1782 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1783 break;
1784 }
1785
1786 case TIM_CHANNEL_2:
1787 {
1788 /* Set the DMA compare callbacks */
1789 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1790 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1791
1792 /* Set the DMA error callback */
1793 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1794
1795 /* Enable the DMA channel */
1796 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1797 Length) != HAL_OK)
1798 {
1799 /* Return error status */
1800 return HAL_ERROR;
1801 }
1802 /* Enable the TIM Capture/Compare 2 DMA request */
1803 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1804 break;
1805 }
1806
1807 case TIM_CHANNEL_3:
1808 {
1809 /* Set the DMA compare callbacks */
1810 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1811 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1812
1813 /* Set the DMA error callback */
1814 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1815
1816 /* Enable the DMA channel */
1817 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1818 Length) != HAL_OK)
1819 {
1820 /* Return error status */
1821 return HAL_ERROR;
1822 }
1823 /* Enable the TIM Output Capture/Compare 3 request */
1824 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1825 break;
1826 }
1827
1828 case TIM_CHANNEL_4:
1829 {
1830 /* Set the DMA compare callbacks */
1831 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1832 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1833
1834 /* Set the DMA error callback */
1835 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1836
1837 /* Enable the DMA channel */
1838 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1839 Length) != HAL_OK)
1840 {
1841 /* Return error status */
1842 return HAL_ERROR;
1843 }
1844 /* Enable the TIM Capture/Compare 4 DMA request */
1845 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1846 break;
1847 }
1848
1849 default:
1850 status = HAL_ERROR;
1851 break;
1852 }
1853
1854 if (status == HAL_OK)
1855 {
1856 /* Enable the Capture compare channel */
1857 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1858
1859 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1860 {
1861 /* Enable the main output */
1862 __HAL_TIM_MOE_ENABLE(htim);
1863 }
1864
1865 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1866 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1867 {
1868 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1869 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1870 {
1871 __HAL_TIM_ENABLE(htim);
1872 }
1873 }
1874 else
1875 {
1876 __HAL_TIM_ENABLE(htim);
1877 }
1878 }
1879
1880 /* Return function status */
1881 return status;
1882 }
1883
1884 /**
1885 * @brief Stops the TIM PWM signal generation in DMA mode.
1886 * @param htim TIM PWM handle
1887 * @param Channel TIM Channels to be disabled
1888 * This parameter can be one of the following values:
1889 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1890 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1891 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1892 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1893 * @retval HAL status
1894 */
HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1895 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1896 {
1897 HAL_StatusTypeDef status = HAL_OK;
1898
1899 /* Check the parameters */
1900 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1901
1902 switch (Channel)
1903 {
1904 case TIM_CHANNEL_1:
1905 {
1906 /* Disable the TIM Capture/Compare 1 DMA request */
1907 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1908 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1909 break;
1910 }
1911
1912 case TIM_CHANNEL_2:
1913 {
1914 /* Disable the TIM Capture/Compare 2 DMA request */
1915 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1916 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1917 break;
1918 }
1919
1920 case TIM_CHANNEL_3:
1921 {
1922 /* Disable the TIM Capture/Compare 3 DMA request */
1923 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1924 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1925 break;
1926 }
1927
1928 case TIM_CHANNEL_4:
1929 {
1930 /* Disable the TIM Capture/Compare 4 interrupt */
1931 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1932 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1933 break;
1934 }
1935
1936 default:
1937 status = HAL_ERROR;
1938 break;
1939 }
1940
1941 if (status == HAL_OK)
1942 {
1943 /* Disable the Capture compare channel */
1944 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1945
1946 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1947 {
1948 /* Disable the Main Output */
1949 __HAL_TIM_MOE_DISABLE(htim);
1950 }
1951
1952 /* Disable the Peripheral */
1953 __HAL_TIM_DISABLE(htim);
1954
1955 /* Set the TIM channel state */
1956 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1957 }
1958
1959 /* Return function status */
1960 return status;
1961 }
1962
1963 /**
1964 * @}
1965 */
1966
1967 /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
1968 * @brief TIM Input Capture functions
1969 *
1970 @verbatim
1971 ==============================================================================
1972 ##### TIM Input Capture functions #####
1973 ==============================================================================
1974 [..]
1975 This section provides functions allowing to:
1976 (+) Initialize and configure the TIM Input Capture.
1977 (+) De-initialize the TIM Input Capture.
1978 (+) Start the TIM Input Capture.
1979 (+) Stop the TIM Input Capture.
1980 (+) Start the TIM Input Capture and enable interrupt.
1981 (+) Stop the TIM Input Capture and disable interrupt.
1982 (+) Start the TIM Input Capture and enable DMA transfer.
1983 (+) Stop the TIM Input Capture and disable DMA transfer.
1984
1985 @endverbatim
1986 * @{
1987 */
1988 /**
1989 * @brief Initializes the TIM Input Capture Time base according to the specified
1990 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1991 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1992 * requires a timer reset to avoid unexpected direction
1993 * due to DIR bit readonly in center aligned mode.
1994 * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
1995 * @param htim TIM Input Capture handle
1996 * @retval HAL status
1997 */
HAL_TIM_IC_Init(TIM_HandleTypeDef * htim)1998 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
1999 {
2000 /* Check the TIM handle allocation */
2001 if (htim == NULL)
2002 {
2003 return HAL_ERROR;
2004 }
2005
2006 /* Check the parameters */
2007 assert_param(IS_TIM_INSTANCE(htim->Instance));
2008 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2009 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2010 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
2011 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2012
2013 if (htim->State == HAL_TIM_STATE_RESET)
2014 {
2015 /* Allocate lock resource and initialize it */
2016 htim->Lock = HAL_UNLOCKED;
2017
2018 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2019 /* Reset interrupt callbacks to legacy weak callbacks */
2020 TIM_ResetCallback(htim);
2021
2022 if (htim->IC_MspInitCallback == NULL)
2023 {
2024 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
2025 }
2026 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2027 htim->IC_MspInitCallback(htim);
2028 #else
2029 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2030 HAL_TIM_IC_MspInit(htim);
2031 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2032 }
2033
2034 /* Set the TIM state */
2035 htim->State = HAL_TIM_STATE_BUSY;
2036
2037 /* Init the base time for the input capture */
2038 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2039
2040 /* Initialize the DMA burst operation state */
2041 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2042
2043 /* Initialize the TIM channels state */
2044 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
2045 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
2046
2047 /* Initialize the TIM state*/
2048 htim->State = HAL_TIM_STATE_READY;
2049
2050 return HAL_OK;
2051 }
2052
2053 /**
2054 * @brief DeInitializes the TIM peripheral
2055 * @param htim TIM Input Capture handle
2056 * @retval HAL status
2057 */
HAL_TIM_IC_DeInit(TIM_HandleTypeDef * htim)2058 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
2059 {
2060 /* Check the parameters */
2061 assert_param(IS_TIM_INSTANCE(htim->Instance));
2062
2063 htim->State = HAL_TIM_STATE_BUSY;
2064
2065 /* Disable the TIM Peripheral Clock */
2066 __HAL_TIM_DISABLE(htim);
2067
2068 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2069 if (htim->IC_MspDeInitCallback == NULL)
2070 {
2071 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
2072 }
2073 /* DeInit the low level hardware */
2074 htim->IC_MspDeInitCallback(htim);
2075 #else
2076 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
2077 HAL_TIM_IC_MspDeInit(htim);
2078 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2079
2080 /* Change the DMA burst operation state */
2081 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2082
2083 /* Change the TIM channels state */
2084 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2085 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2086
2087 /* Change TIM state */
2088 htim->State = HAL_TIM_STATE_RESET;
2089
2090 /* Release Lock */
2091 __HAL_UNLOCK(htim);
2092
2093 return HAL_OK;
2094 }
2095
2096 /**
2097 * @brief Initializes the TIM Input Capture MSP.
2098 * @param htim TIM Input Capture handle
2099 * @retval None
2100 */
HAL_TIM_IC_MspInit(TIM_HandleTypeDef * htim)2101 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
2102 {
2103 /* Prevent unused argument(s) compilation warning */
2104 UNUSED(htim);
2105
2106 /* NOTE : This function should not be modified, when the callback is needed,
2107 the HAL_TIM_IC_MspInit could be implemented in the user file
2108 */
2109 }
2110
2111 /**
2112 * @brief DeInitializes TIM Input Capture MSP.
2113 * @param htim TIM handle
2114 * @retval None
2115 */
HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef * htim)2116 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
2117 {
2118 /* Prevent unused argument(s) compilation warning */
2119 UNUSED(htim);
2120
2121 /* NOTE : This function should not be modified, when the callback is needed,
2122 the HAL_TIM_IC_MspDeInit could be implemented in the user file
2123 */
2124 }
2125
2126 /**
2127 * @brief Starts the TIM Input Capture measurement.
2128 * @param htim TIM Input Capture handle
2129 * @param Channel TIM Channels to be enabled
2130 * This parameter can be one of the following values:
2131 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2132 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2133 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2134 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2135 * @retval HAL status
2136 */
HAL_TIM_IC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)2137 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2138 {
2139 uint32_t tmpsmcr;
2140 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2141 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2142
2143 /* Check the parameters */
2144 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2145
2146 /* Check the TIM channel state */
2147 if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2148 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2149 {
2150 return HAL_ERROR;
2151 }
2152
2153 /* Set the TIM channel state */
2154 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2155 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2156
2157 /* Enable the Input Capture channel */
2158 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2159
2160 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2161 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2162 {
2163 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2164 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2165 {
2166 __HAL_TIM_ENABLE(htim);
2167 }
2168 }
2169 else
2170 {
2171 __HAL_TIM_ENABLE(htim);
2172 }
2173
2174 /* Return function status */
2175 return HAL_OK;
2176 }
2177
2178 /**
2179 * @brief Stops the TIM Input Capture measurement.
2180 * @param htim TIM Input Capture handle
2181 * @param Channel TIM Channels to be disabled
2182 * This parameter can be one of the following values:
2183 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2184 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2185 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2186 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2187 * @retval HAL status
2188 */
HAL_TIM_IC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)2189 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2190 {
2191 /* Check the parameters */
2192 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2193
2194 /* Disable the Input Capture channel */
2195 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2196
2197 /* Disable the Peripheral */
2198 __HAL_TIM_DISABLE(htim);
2199
2200 /* Set the TIM channel state */
2201 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2202 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2203
2204 /* Return function status */
2205 return HAL_OK;
2206 }
2207
2208 /**
2209 * @brief Starts the TIM Input Capture measurement in interrupt mode.
2210 * @param htim TIM Input Capture handle
2211 * @param Channel TIM Channels to be enabled
2212 * This parameter can be one of the following values:
2213 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2214 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2215 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2216 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2217 * @retval HAL status
2218 */
HAL_TIM_IC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2219 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2220 {
2221 HAL_StatusTypeDef status = HAL_OK;
2222 uint32_t tmpsmcr;
2223
2224 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2225 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2226
2227 /* Check the parameters */
2228 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2229
2230 /* Check the TIM channel state */
2231 if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2232 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2233 {
2234 return HAL_ERROR;
2235 }
2236
2237 /* Set the TIM channel state */
2238 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2239 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2240
2241 switch (Channel)
2242 {
2243 case TIM_CHANNEL_1:
2244 {
2245 /* Enable the TIM Capture/Compare 1 interrupt */
2246 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2247 break;
2248 }
2249
2250 case TIM_CHANNEL_2:
2251 {
2252 /* Enable the TIM Capture/Compare 2 interrupt */
2253 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2254 break;
2255 }
2256
2257 case TIM_CHANNEL_3:
2258 {
2259 /* Enable the TIM Capture/Compare 3 interrupt */
2260 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
2261 break;
2262 }
2263
2264 case TIM_CHANNEL_4:
2265 {
2266 /* Enable the TIM Capture/Compare 4 interrupt */
2267 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
2268 break;
2269 }
2270
2271 default:
2272 status = HAL_ERROR;
2273 break;
2274 }
2275
2276 if (status == HAL_OK)
2277 {
2278 /* Enable the Input Capture channel */
2279 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2280
2281 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2282 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2283 {
2284 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2285 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2286 {
2287 __HAL_TIM_ENABLE(htim);
2288 }
2289 }
2290 else
2291 {
2292 __HAL_TIM_ENABLE(htim);
2293 }
2294 }
2295
2296 /* Return function status */
2297 return status;
2298 }
2299
2300 /**
2301 * @brief Stops the TIM Input Capture measurement in interrupt mode.
2302 * @param htim TIM Input Capture handle
2303 * @param Channel TIM Channels to be disabled
2304 * This parameter can be one of the following values:
2305 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2306 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2307 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2308 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2309 * @retval HAL status
2310 */
HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2311 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2312 {
2313 HAL_StatusTypeDef status = HAL_OK;
2314
2315 /* Check the parameters */
2316 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2317
2318 switch (Channel)
2319 {
2320 case TIM_CHANNEL_1:
2321 {
2322 /* Disable the TIM Capture/Compare 1 interrupt */
2323 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2324 break;
2325 }
2326
2327 case TIM_CHANNEL_2:
2328 {
2329 /* Disable the TIM Capture/Compare 2 interrupt */
2330 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2331 break;
2332 }
2333
2334 case TIM_CHANNEL_3:
2335 {
2336 /* Disable the TIM Capture/Compare 3 interrupt */
2337 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
2338 break;
2339 }
2340
2341 case TIM_CHANNEL_4:
2342 {
2343 /* Disable the TIM Capture/Compare 4 interrupt */
2344 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
2345 break;
2346 }
2347
2348 default:
2349 status = HAL_ERROR;
2350 break;
2351 }
2352
2353 if (status == HAL_OK)
2354 {
2355 /* Disable the Input Capture channel */
2356 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2357
2358 /* Disable the Peripheral */
2359 __HAL_TIM_DISABLE(htim);
2360
2361 /* Set the TIM channel state */
2362 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2363 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2364 }
2365
2366 /* Return function status */
2367 return status;
2368 }
2369
2370 /**
2371 * @brief Starts the TIM Input Capture measurement in DMA mode.
2372 * @param htim TIM Input Capture handle
2373 * @param Channel TIM Channels to be enabled
2374 * This parameter can be one of the following values:
2375 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2376 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2377 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2378 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2379 * @param pData The destination Buffer address.
2380 * @param Length The length of data to be transferred from TIM peripheral to memory.
2381 * @retval HAL status
2382 */
HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)2383 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
2384 {
2385 HAL_StatusTypeDef status = HAL_OK;
2386 uint32_t tmpsmcr;
2387
2388 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2389 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2390
2391 /* Check the parameters */
2392 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2393 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2394
2395 /* Set the TIM channel state */
2396 if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
2397 || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
2398 {
2399 return HAL_BUSY;
2400 }
2401 else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
2402 && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
2403 {
2404 if ((pData == NULL) || (Length == 0U))
2405 {
2406 return HAL_ERROR;
2407 }
2408 else
2409 {
2410 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2411 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2412 }
2413 }
2414 else
2415 {
2416 return HAL_ERROR;
2417 }
2418
2419 /* Enable the Input Capture channel */
2420 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2421
2422 switch (Channel)
2423 {
2424 case TIM_CHANNEL_1:
2425 {
2426 /* Set the DMA capture callbacks */
2427 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2428 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2429
2430 /* Set the DMA error callback */
2431 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2432
2433 /* Enable the DMA channel */
2434 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
2435 Length) != HAL_OK)
2436 {
2437 /* Return error status */
2438 return HAL_ERROR;
2439 }
2440 /* Enable the TIM Capture/Compare 1 DMA request */
2441 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2442 break;
2443 }
2444
2445 case TIM_CHANNEL_2:
2446 {
2447 /* Set the DMA capture callbacks */
2448 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2449 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2450
2451 /* Set the DMA error callback */
2452 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
2453
2454 /* Enable the DMA channel */
2455 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
2456 Length) != HAL_OK)
2457 {
2458 /* Return error status */
2459 return HAL_ERROR;
2460 }
2461 /* Enable the TIM Capture/Compare 2 DMA request */
2462 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2463 break;
2464 }
2465
2466 case TIM_CHANNEL_3:
2467 {
2468 /* Set the DMA capture callbacks */
2469 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
2470 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2471
2472 /* Set the DMA error callback */
2473 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
2474
2475 /* Enable the DMA channel */
2476 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
2477 Length) != HAL_OK)
2478 {
2479 /* Return error status */
2480 return HAL_ERROR;
2481 }
2482 /* Enable the TIM Capture/Compare 3 DMA request */
2483 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
2484 break;
2485 }
2486
2487 case TIM_CHANNEL_4:
2488 {
2489 /* Set the DMA capture callbacks */
2490 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
2491 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2492
2493 /* Set the DMA error callback */
2494 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
2495
2496 /* Enable the DMA channel */
2497 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
2498 Length) != HAL_OK)
2499 {
2500 /* Return error status */
2501 return HAL_ERROR;
2502 }
2503 /* Enable the TIM Capture/Compare 4 DMA request */
2504 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
2505 break;
2506 }
2507
2508 default:
2509 status = HAL_ERROR;
2510 break;
2511 }
2512
2513 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2514 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2515 {
2516 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2517 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2518 {
2519 __HAL_TIM_ENABLE(htim);
2520 }
2521 }
2522 else
2523 {
2524 __HAL_TIM_ENABLE(htim);
2525 }
2526
2527 /* Return function status */
2528 return status;
2529 }
2530
2531 /**
2532 * @brief Stops the TIM Input Capture measurement in DMA mode.
2533 * @param htim TIM Input Capture handle
2534 * @param Channel TIM Channels to be disabled
2535 * This parameter can be one of the following values:
2536 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2537 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2538 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2539 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2540 * @retval HAL status
2541 */
HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)2542 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2543 {
2544 HAL_StatusTypeDef status = HAL_OK;
2545
2546 /* Check the parameters */
2547 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2548 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2549
2550 /* Disable the Input Capture channel */
2551 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2552
2553 switch (Channel)
2554 {
2555 case TIM_CHANNEL_1:
2556 {
2557 /* Disable the TIM Capture/Compare 1 DMA request */
2558 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2559 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
2560 break;
2561 }
2562
2563 case TIM_CHANNEL_2:
2564 {
2565 /* Disable the TIM Capture/Compare 2 DMA request */
2566 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2567 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
2568 break;
2569 }
2570
2571 case TIM_CHANNEL_3:
2572 {
2573 /* Disable the TIM Capture/Compare 3 DMA request */
2574 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
2575 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
2576 break;
2577 }
2578
2579 case TIM_CHANNEL_4:
2580 {
2581 /* Disable the TIM Capture/Compare 4 DMA request */
2582 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
2583 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
2584 break;
2585 }
2586
2587 default:
2588 status = HAL_ERROR;
2589 break;
2590 }
2591
2592 if (status == HAL_OK)
2593 {
2594 /* Disable the Peripheral */
2595 __HAL_TIM_DISABLE(htim);
2596
2597 /* Set the TIM channel state */
2598 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2599 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2600 }
2601
2602 /* Return function status */
2603 return status;
2604 }
2605 /**
2606 * @}
2607 */
2608
2609 /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
2610 * @brief TIM One Pulse functions
2611 *
2612 @verbatim
2613 ==============================================================================
2614 ##### TIM One Pulse functions #####
2615 ==============================================================================
2616 [..]
2617 This section provides functions allowing to:
2618 (+) Initialize and configure the TIM One Pulse.
2619 (+) De-initialize the TIM One Pulse.
2620 (+) Start the TIM One Pulse.
2621 (+) Stop the TIM One Pulse.
2622 (+) Start the TIM One Pulse and enable interrupt.
2623 (+) Stop the TIM One Pulse and disable interrupt.
2624 (+) Start the TIM One Pulse and enable DMA transfer.
2625 (+) Stop the TIM One Pulse and disable DMA transfer.
2626
2627 @endverbatim
2628 * @{
2629 */
2630 /**
2631 * @brief Initializes the TIM One Pulse Time Base according to the specified
2632 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
2633 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2634 * requires a timer reset to avoid unexpected direction
2635 * due to DIR bit readonly in center aligned mode.
2636 * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
2637 * @note When the timer instance is initialized in One Pulse mode, timer
2638 * channels 1 and channel 2 are reserved and cannot be used for other
2639 * purpose.
2640 * @param htim TIM One Pulse handle
2641 * @param OnePulseMode Select the One pulse mode.
2642 * This parameter can be one of the following values:
2643 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
2644 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
2645 * @retval HAL status
2646 */
HAL_TIM_OnePulse_Init(TIM_HandleTypeDef * htim,uint32_t OnePulseMode)2647 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
2648 {
2649 /* Check the TIM handle allocation */
2650 if (htim == NULL)
2651 {
2652 return HAL_ERROR;
2653 }
2654
2655 /* Check the parameters */
2656 assert_param(IS_TIM_INSTANCE(htim->Instance));
2657 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2658 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2659 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
2660 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
2661 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2662
2663 if (htim->State == HAL_TIM_STATE_RESET)
2664 {
2665 /* Allocate lock resource and initialize it */
2666 htim->Lock = HAL_UNLOCKED;
2667
2668 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2669 /* Reset interrupt callbacks to legacy weak callbacks */
2670 TIM_ResetCallback(htim);
2671
2672 if (htim->OnePulse_MspInitCallback == NULL)
2673 {
2674 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
2675 }
2676 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2677 htim->OnePulse_MspInitCallback(htim);
2678 #else
2679 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2680 HAL_TIM_OnePulse_MspInit(htim);
2681 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2682 }
2683
2684 /* Set the TIM state */
2685 htim->State = HAL_TIM_STATE_BUSY;
2686
2687 /* Configure the Time base in the One Pulse Mode */
2688 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2689
2690 /* Reset the OPM Bit */
2691 htim->Instance->CR1 &= ~TIM_CR1_OPM;
2692
2693 /* Configure the OPM Mode */
2694 htim->Instance->CR1 |= OnePulseMode;
2695
2696 /* Initialize the DMA burst operation state */
2697 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2698
2699 /* Initialize the TIM channels state */
2700 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2701 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2702 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2703 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2704
2705 /* Initialize the TIM state*/
2706 htim->State = HAL_TIM_STATE_READY;
2707
2708 return HAL_OK;
2709 }
2710
2711 /**
2712 * @brief DeInitializes the TIM One Pulse
2713 * @param htim TIM One Pulse handle
2714 * @retval HAL status
2715 */
HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef * htim)2716 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
2717 {
2718 /* Check the parameters */
2719 assert_param(IS_TIM_INSTANCE(htim->Instance));
2720
2721 htim->State = HAL_TIM_STATE_BUSY;
2722
2723 /* Disable the TIM Peripheral Clock */
2724 __HAL_TIM_DISABLE(htim);
2725
2726 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2727 if (htim->OnePulse_MspDeInitCallback == NULL)
2728 {
2729 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
2730 }
2731 /* DeInit the low level hardware */
2732 htim->OnePulse_MspDeInitCallback(htim);
2733 #else
2734 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2735 HAL_TIM_OnePulse_MspDeInit(htim);
2736 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2737
2738 /* Change the DMA burst operation state */
2739 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2740
2741 /* Set the TIM channel state */
2742 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2743 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2744 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2745 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2746
2747 /* Change TIM state */
2748 htim->State = HAL_TIM_STATE_RESET;
2749
2750 /* Release Lock */
2751 __HAL_UNLOCK(htim);
2752
2753 return HAL_OK;
2754 }
2755
2756 /**
2757 * @brief Initializes the TIM One Pulse MSP.
2758 * @param htim TIM One Pulse handle
2759 * @retval None
2760 */
HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef * htim)2761 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
2762 {
2763 /* Prevent unused argument(s) compilation warning */
2764 UNUSED(htim);
2765
2766 /* NOTE : This function should not be modified, when the callback is needed,
2767 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
2768 */
2769 }
2770
2771 /**
2772 * @brief DeInitializes TIM One Pulse MSP.
2773 * @param htim TIM One Pulse handle
2774 * @retval None
2775 */
HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef * htim)2776 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
2777 {
2778 /* Prevent unused argument(s) compilation warning */
2779 UNUSED(htim);
2780
2781 /* NOTE : This function should not be modified, when the callback is needed,
2782 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2783 */
2784 }
2785
2786 /**
2787 * @brief Starts the TIM One Pulse signal generation.
2788 * @note Though OutputChannel parameter is deprecated and ignored by the function
2789 * it has been kept to avoid HAL_TIM API compatibility break.
2790 * @note The pulse output channel is determined when calling
2791 * @ref HAL_TIM_OnePulse_ConfigChannel().
2792 * @param htim TIM One Pulse handle
2793 * @param OutputChannel See note above
2794 * @retval HAL status
2795 */
HAL_TIM_OnePulse_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2796 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2797 {
2798 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2799 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2800 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2801 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2802
2803 /* Prevent unused argument(s) compilation warning */
2804 UNUSED(OutputChannel);
2805
2806 /* Check the TIM channels state */
2807 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2808 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2809 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2810 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2811 {
2812 return HAL_ERROR;
2813 }
2814
2815 /* Set the TIM channels state */
2816 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2817 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2818 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2819 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2820
2821 /* Enable the Capture compare and the Input Capture channels
2822 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2823 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2824 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2825 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2826
2827 No need to enable the counter, it's enabled automatically by hardware
2828 (the counter starts in response to a stimulus and generate a pulse */
2829
2830 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2831 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2832
2833 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2834 {
2835 /* Enable the main output */
2836 __HAL_TIM_MOE_ENABLE(htim);
2837 }
2838
2839 /* Return function status */
2840 return HAL_OK;
2841 }
2842
2843 /**
2844 * @brief Stops the TIM One Pulse signal generation.
2845 * @note Though OutputChannel parameter is deprecated and ignored by the function
2846 * it has been kept to avoid HAL_TIM API compatibility break.
2847 * @note The pulse output channel is determined when calling
2848 * @ref HAL_TIM_OnePulse_ConfigChannel().
2849 * @param htim TIM One Pulse handle
2850 * @param OutputChannel See note above
2851 * @retval HAL status
2852 */
HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2853 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2854 {
2855 /* Prevent unused argument(s) compilation warning */
2856 UNUSED(OutputChannel);
2857
2858 /* Disable the Capture compare and the Input Capture channels
2859 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2860 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2861 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2862 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2863
2864 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2865 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2866
2867 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2868 {
2869 /* Disable the Main Output */
2870 __HAL_TIM_MOE_DISABLE(htim);
2871 }
2872
2873 /* Disable the Peripheral */
2874 __HAL_TIM_DISABLE(htim);
2875
2876 /* Set the TIM channels state */
2877 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2878 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2879 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2880 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2881
2882 /* Return function status */
2883 return HAL_OK;
2884 }
2885
2886 /**
2887 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2888 * @note Though OutputChannel parameter is deprecated and ignored by the function
2889 * it has been kept to avoid HAL_TIM API compatibility break.
2890 * @note The pulse output channel is determined when calling
2891 * @ref HAL_TIM_OnePulse_ConfigChannel().
2892 * @param htim TIM One Pulse handle
2893 * @param OutputChannel See note above
2894 * @retval HAL status
2895 */
HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2896 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2897 {
2898 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2899 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2900 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2901 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2902
2903 /* Prevent unused argument(s) compilation warning */
2904 UNUSED(OutputChannel);
2905
2906 /* Check the TIM channels state */
2907 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2908 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2909 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2910 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2911 {
2912 return HAL_ERROR;
2913 }
2914
2915 /* Set the TIM channels state */
2916 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2917 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2918 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2919 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2920
2921 /* Enable the Capture compare and the Input Capture channels
2922 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2923 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2924 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2925 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2926
2927 No need to enable the counter, it's enabled automatically by hardware
2928 (the counter starts in response to a stimulus and generate a pulse */
2929
2930 /* Enable the TIM Capture/Compare 1 interrupt */
2931 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2932
2933 /* Enable the TIM Capture/Compare 2 interrupt */
2934 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2935
2936 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2937 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2938
2939 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2940 {
2941 /* Enable the main output */
2942 __HAL_TIM_MOE_ENABLE(htim);
2943 }
2944
2945 /* Return function status */
2946 return HAL_OK;
2947 }
2948
2949 /**
2950 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2951 * @note Though OutputChannel parameter is deprecated and ignored by the function
2952 * it has been kept to avoid HAL_TIM API compatibility break.
2953 * @note The pulse output channel is determined when calling
2954 * @ref HAL_TIM_OnePulse_ConfigChannel().
2955 * @param htim TIM One Pulse handle
2956 * @param OutputChannel See note above
2957 * @retval HAL status
2958 */
HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2959 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2960 {
2961 /* Prevent unused argument(s) compilation warning */
2962 UNUSED(OutputChannel);
2963
2964 /* Disable the TIM Capture/Compare 1 interrupt */
2965 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2966
2967 /* Disable the TIM Capture/Compare 2 interrupt */
2968 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2969
2970 /* Disable the Capture compare and the Input Capture channels
2971 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2972 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2973 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2974 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2975 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2976 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2977
2978 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2979 {
2980 /* Disable the Main Output */
2981 __HAL_TIM_MOE_DISABLE(htim);
2982 }
2983
2984 /* Disable the Peripheral */
2985 __HAL_TIM_DISABLE(htim);
2986
2987 /* Set the TIM channels state */
2988 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2989 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2990 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2991 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2992
2993 /* Return function status */
2994 return HAL_OK;
2995 }
2996
2997 /**
2998 * @}
2999 */
3000
3001 /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
3002 * @brief TIM Encoder functions
3003 *
3004 @verbatim
3005 ==============================================================================
3006 ##### TIM Encoder functions #####
3007 ==============================================================================
3008 [..]
3009 This section provides functions allowing to:
3010 (+) Initialize and configure the TIM Encoder.
3011 (+) De-initialize the TIM Encoder.
3012 (+) Start the TIM Encoder.
3013 (+) Stop the TIM Encoder.
3014 (+) Start the TIM Encoder and enable interrupt.
3015 (+) Stop the TIM Encoder and disable interrupt.
3016 (+) Start the TIM Encoder and enable DMA transfer.
3017 (+) Stop the TIM Encoder and disable DMA transfer.
3018
3019 @endverbatim
3020 * @{
3021 */
3022 /**
3023 * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
3024 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
3025 * requires a timer reset to avoid unexpected direction
3026 * due to DIR bit readonly in center aligned mode.
3027 * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
3028 * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
3029 * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
3030 * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
3031 * @note When the timer instance is initialized in Encoder mode, timer
3032 * channels 1 and channel 2 are reserved and cannot be used for other
3033 * purpose.
3034 * @param htim TIM Encoder Interface handle
3035 * @param sConfig TIM Encoder Interface configuration structure
3036 * @retval HAL status
3037 */
HAL_TIM_Encoder_Init(TIM_HandleTypeDef * htim,const TIM_Encoder_InitTypeDef * sConfig)3038 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
3039 {
3040 uint32_t tmpsmcr;
3041 uint32_t tmpccmr1;
3042 uint32_t tmpccer;
3043
3044 /* Check the TIM handle allocation */
3045 if (htim == NULL)
3046 {
3047 return HAL_ERROR;
3048 }
3049
3050 /* Check the parameters */
3051 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3052 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
3053 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
3054 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
3055 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
3056 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
3057 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
3058 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
3059 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
3060 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
3061 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
3062 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
3063 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
3064 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
3065
3066 if (htim->State == HAL_TIM_STATE_RESET)
3067 {
3068 /* Allocate lock resource and initialize it */
3069 htim->Lock = HAL_UNLOCKED;
3070
3071 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3072 /* Reset interrupt callbacks to legacy weak callbacks */
3073 TIM_ResetCallback(htim);
3074
3075 if (htim->Encoder_MspInitCallback == NULL)
3076 {
3077 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
3078 }
3079 /* Init the low level hardware : GPIO, CLOCK, NVIC */
3080 htim->Encoder_MspInitCallback(htim);
3081 #else
3082 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
3083 HAL_TIM_Encoder_MspInit(htim);
3084 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3085 }
3086
3087 /* Set the TIM state */
3088 htim->State = HAL_TIM_STATE_BUSY;
3089
3090 /* Reset the SMS and ECE bits */
3091 htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
3092
3093 /* Configure the Time base in the Encoder Mode */
3094 TIM_Base_SetConfig(htim->Instance, &htim->Init);
3095
3096 /* Get the TIMx SMCR register value */
3097 tmpsmcr = htim->Instance->SMCR;
3098
3099 /* Get the TIMx CCMR1 register value */
3100 tmpccmr1 = htim->Instance->CCMR1;
3101
3102 /* Get the TIMx CCER register value */
3103 tmpccer = htim->Instance->CCER;
3104
3105 /* Set the encoder Mode */
3106 tmpsmcr |= sConfig->EncoderMode;
3107
3108 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
3109 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
3110 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
3111
3112 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
3113 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
3114 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
3115 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
3116 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
3117
3118 /* Set the TI1 and the TI2 Polarities */
3119 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
3120 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
3121 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
3122
3123 /* Write to TIMx SMCR */
3124 htim->Instance->SMCR = tmpsmcr;
3125
3126 /* Write to TIMx CCMR1 */
3127 htim->Instance->CCMR1 = tmpccmr1;
3128
3129 /* Write to TIMx CCER */
3130 htim->Instance->CCER = tmpccer;
3131
3132 /* Initialize the DMA burst operation state */
3133 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
3134
3135 /* Set the TIM channels state */
3136 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3137 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3138 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3139 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3140
3141 /* Initialize the TIM state*/
3142 htim->State = HAL_TIM_STATE_READY;
3143
3144 return HAL_OK;
3145 }
3146
3147
3148 /**
3149 * @brief DeInitializes the TIM Encoder interface
3150 * @param htim TIM Encoder Interface handle
3151 * @retval HAL status
3152 */
HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef * htim)3153 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
3154 {
3155 /* Check the parameters */
3156 assert_param(IS_TIM_INSTANCE(htim->Instance));
3157
3158 htim->State = HAL_TIM_STATE_BUSY;
3159
3160 /* Disable the TIM Peripheral Clock */
3161 __HAL_TIM_DISABLE(htim);
3162
3163 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3164 if (htim->Encoder_MspDeInitCallback == NULL)
3165 {
3166 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
3167 }
3168 /* DeInit the low level hardware */
3169 htim->Encoder_MspDeInitCallback(htim);
3170 #else
3171 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
3172 HAL_TIM_Encoder_MspDeInit(htim);
3173 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3174
3175 /* Change the DMA burst operation state */
3176 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
3177
3178 /* Set the TIM channels state */
3179 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3180 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3181 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3182 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3183
3184 /* Change TIM state */
3185 htim->State = HAL_TIM_STATE_RESET;
3186
3187 /* Release Lock */
3188 __HAL_UNLOCK(htim);
3189
3190 return HAL_OK;
3191 }
3192
3193 /**
3194 * @brief Initializes the TIM Encoder Interface MSP.
3195 * @param htim TIM Encoder Interface handle
3196 * @retval None
3197 */
HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef * htim)3198 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
3199 {
3200 /* Prevent unused argument(s) compilation warning */
3201 UNUSED(htim);
3202
3203 /* NOTE : This function should not be modified, when the callback is needed,
3204 the HAL_TIM_Encoder_MspInit could be implemented in the user file
3205 */
3206 }
3207
3208 /**
3209 * @brief DeInitializes TIM Encoder Interface MSP.
3210 * @param htim TIM Encoder Interface handle
3211 * @retval None
3212 */
HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef * htim)3213 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
3214 {
3215 /* Prevent unused argument(s) compilation warning */
3216 UNUSED(htim);
3217
3218 /* NOTE : This function should not be modified, when the callback is needed,
3219 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
3220 */
3221 }
3222
3223 /**
3224 * @brief Starts the TIM Encoder Interface.
3225 * @param htim TIM Encoder Interface handle
3226 * @param Channel TIM Channels to be enabled
3227 * This parameter can be one of the following values:
3228 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3229 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3230 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3231 * @retval HAL status
3232 */
HAL_TIM_Encoder_Start(TIM_HandleTypeDef * htim,uint32_t Channel)3233 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
3234 {
3235 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3236 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3237 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3238 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3239
3240 /* Check the parameters */
3241 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3242
3243 /* Set the TIM channel(s) state */
3244 if (Channel == TIM_CHANNEL_1)
3245 {
3246 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3247 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3248 {
3249 return HAL_ERROR;
3250 }
3251 else
3252 {
3253 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3254 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3255 }
3256 }
3257 else if (Channel == TIM_CHANNEL_2)
3258 {
3259 if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3260 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3261 {
3262 return HAL_ERROR;
3263 }
3264 else
3265 {
3266 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3267 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3268 }
3269 }
3270 else
3271 {
3272 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3273 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3274 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3275 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3276 {
3277 return HAL_ERROR;
3278 }
3279 else
3280 {
3281 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3282 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3283 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3284 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3285 }
3286 }
3287
3288 /* Enable the encoder interface channels */
3289 switch (Channel)
3290 {
3291 case TIM_CHANNEL_1:
3292 {
3293 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3294 break;
3295 }
3296
3297 case TIM_CHANNEL_2:
3298 {
3299 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3300 break;
3301 }
3302
3303 default :
3304 {
3305 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3306 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3307 break;
3308 }
3309 }
3310 /* Enable the Peripheral */
3311 __HAL_TIM_ENABLE(htim);
3312
3313 /* Return function status */
3314 return HAL_OK;
3315 }
3316
3317 /**
3318 * @brief Stops the TIM Encoder Interface.
3319 * @param htim TIM Encoder Interface handle
3320 * @param Channel TIM Channels to be disabled
3321 * This parameter can be one of the following values:
3322 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3323 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3324 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3325 * @retval HAL status
3326 */
HAL_TIM_Encoder_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)3327 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
3328 {
3329 /* Check the parameters */
3330 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3331
3332 /* Disable the Input Capture channels 1 and 2
3333 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3334 switch (Channel)
3335 {
3336 case TIM_CHANNEL_1:
3337 {
3338 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3339 break;
3340 }
3341
3342 case TIM_CHANNEL_2:
3343 {
3344 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3345 break;
3346 }
3347
3348 default :
3349 {
3350 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3351 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3352 break;
3353 }
3354 }
3355
3356 /* Disable the Peripheral */
3357 __HAL_TIM_DISABLE(htim);
3358
3359 /* Set the TIM channel(s) state */
3360 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3361 {
3362 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3363 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3364 }
3365 else
3366 {
3367 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3368 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3369 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3370 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3371 }
3372
3373 /* Return function status */
3374 return HAL_OK;
3375 }
3376
3377 /**
3378 * @brief Starts the TIM Encoder Interface in interrupt mode.
3379 * @param htim TIM Encoder Interface handle
3380 * @param Channel TIM Channels to be enabled
3381 * This parameter can be one of the following values:
3382 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3383 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3384 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3385 * @retval HAL status
3386 */
HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3387 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3388 {
3389 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3390 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3391 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3392 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3393
3394 /* Check the parameters */
3395 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3396
3397 /* Set the TIM channel(s) state */
3398 if (Channel == TIM_CHANNEL_1)
3399 {
3400 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3401 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3402 {
3403 return HAL_ERROR;
3404 }
3405 else
3406 {
3407 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3408 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3409 }
3410 }
3411 else if (Channel == TIM_CHANNEL_2)
3412 {
3413 if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3414 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3415 {
3416 return HAL_ERROR;
3417 }
3418 else
3419 {
3420 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3421 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3422 }
3423 }
3424 else
3425 {
3426 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3427 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3428 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3429 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3430 {
3431 return HAL_ERROR;
3432 }
3433 else
3434 {
3435 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3436 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3437 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3438 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3439 }
3440 }
3441
3442 /* Enable the encoder interface channels */
3443 /* Enable the capture compare Interrupts 1 and/or 2 */
3444 switch (Channel)
3445 {
3446 case TIM_CHANNEL_1:
3447 {
3448 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3449 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3450 break;
3451 }
3452
3453 case TIM_CHANNEL_2:
3454 {
3455 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3456 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3457 break;
3458 }
3459
3460 default :
3461 {
3462 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3463 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3464 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3465 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3466 break;
3467 }
3468 }
3469
3470 /* Enable the Peripheral */
3471 __HAL_TIM_ENABLE(htim);
3472
3473 /* Return function status */
3474 return HAL_OK;
3475 }
3476
3477 /**
3478 * @brief Stops the TIM Encoder Interface in interrupt mode.
3479 * @param htim TIM Encoder Interface handle
3480 * @param Channel TIM Channels to be disabled
3481 * This parameter can be one of the following values:
3482 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3483 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3484 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3485 * @retval HAL status
3486 */
HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3487 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3488 {
3489 /* Check the parameters */
3490 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3491
3492 /* Disable the Input Capture channels 1 and 2
3493 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3494 if (Channel == TIM_CHANNEL_1)
3495 {
3496 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3497
3498 /* Disable the capture compare Interrupts 1 */
3499 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3500 }
3501 else if (Channel == TIM_CHANNEL_2)
3502 {
3503 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3504
3505 /* Disable the capture compare Interrupts 2 */
3506 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3507 }
3508 else
3509 {
3510 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3511 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3512
3513 /* Disable the capture compare Interrupts 1 and 2 */
3514 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3515 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3516 }
3517
3518 /* Disable the Peripheral */
3519 __HAL_TIM_DISABLE(htim);
3520
3521 /* Set the TIM channel(s) state */
3522 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3523 {
3524 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3525 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3526 }
3527 else
3528 {
3529 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3530 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3531 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3532 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3533 }
3534
3535 /* Return function status */
3536 return HAL_OK;
3537 }
3538
3539 /**
3540 * @brief Starts the TIM Encoder Interface in DMA mode.
3541 * @param htim TIM Encoder Interface handle
3542 * @param Channel TIM Channels to be enabled
3543 * This parameter can be one of the following values:
3544 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3545 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3546 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3547 * @param pData1 The destination Buffer address for IC1.
3548 * @param pData2 The destination Buffer address for IC2.
3549 * @param Length The length of data to be transferred from TIM peripheral to memory.
3550 * @retval HAL status
3551 */
HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData1,uint32_t * pData2,uint16_t Length)3552 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
3553 uint32_t *pData2, uint16_t Length)
3554 {
3555 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3556 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3557 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3558 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3559
3560 /* Check the parameters */
3561 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3562
3563 /* Set the TIM channel(s) state */
3564 if (Channel == TIM_CHANNEL_1)
3565 {
3566 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3567 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
3568 {
3569 return HAL_BUSY;
3570 }
3571 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3572 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
3573 {
3574 if ((pData1 == NULL) || (Length == 0U))
3575 {
3576 return HAL_ERROR;
3577 }
3578 else
3579 {
3580 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3581 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3582 }
3583 }
3584 else
3585 {
3586 return HAL_ERROR;
3587 }
3588 }
3589 else if (Channel == TIM_CHANNEL_2)
3590 {
3591 if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3592 || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3593 {
3594 return HAL_BUSY;
3595 }
3596 else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3597 && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3598 {
3599 if ((pData2 == NULL) || (Length == 0U))
3600 {
3601 return HAL_ERROR;
3602 }
3603 else
3604 {
3605 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3606 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3607 }
3608 }
3609 else
3610 {
3611 return HAL_ERROR;
3612 }
3613 }
3614 else
3615 {
3616 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3617 || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3618 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3619 || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3620 {
3621 return HAL_BUSY;
3622 }
3623 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3624 && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3625 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3626 && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3627 {
3628 if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U))
3629 {
3630 return HAL_ERROR;
3631 }
3632 else
3633 {
3634 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3635 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3636 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3637 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3638 }
3639 }
3640 else
3641 {
3642 return HAL_ERROR;
3643 }
3644 }
3645
3646 switch (Channel)
3647 {
3648 case TIM_CHANNEL_1:
3649 {
3650 /* Set the DMA capture callbacks */
3651 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3652 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3653
3654 /* Set the DMA error callback */
3655 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3656
3657 /* Enable the DMA channel */
3658 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3659 Length) != HAL_OK)
3660 {
3661 /* Return error status */
3662 return HAL_ERROR;
3663 }
3664 /* Enable the TIM Input Capture DMA request */
3665 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3666
3667 /* Enable the Capture compare channel */
3668 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3669
3670 /* Enable the Peripheral */
3671 __HAL_TIM_ENABLE(htim);
3672
3673 break;
3674 }
3675
3676 case TIM_CHANNEL_2:
3677 {
3678 /* Set the DMA capture callbacks */
3679 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3680 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3681
3682 /* Set the DMA error callback */
3683 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
3684 /* Enable the DMA channel */
3685 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3686 Length) != HAL_OK)
3687 {
3688 /* Return error status */
3689 return HAL_ERROR;
3690 }
3691 /* Enable the TIM Input Capture DMA request */
3692 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3693
3694 /* Enable the Capture compare channel */
3695 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3696
3697 /* Enable the Peripheral */
3698 __HAL_TIM_ENABLE(htim);
3699
3700 break;
3701 }
3702
3703 default:
3704 {
3705 /* Set the DMA capture callbacks */
3706 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3707 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3708
3709 /* Set the DMA error callback */
3710 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3711
3712 /* Enable the DMA channel */
3713 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3714 Length) != HAL_OK)
3715 {
3716 /* Return error status */
3717 return HAL_ERROR;
3718 }
3719
3720 /* Set the DMA capture callbacks */
3721 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3722 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3723
3724 /* Set the DMA error callback */
3725 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3726
3727 /* Enable the DMA channel */
3728 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3729 Length) != HAL_OK)
3730 {
3731 /* Return error status */
3732 return HAL_ERROR;
3733 }
3734
3735 /* Enable the TIM Input Capture DMA request */
3736 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3737 /* Enable the TIM Input Capture DMA request */
3738 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3739
3740 /* Enable the Capture compare channel */
3741 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3742 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3743
3744 /* Enable the Peripheral */
3745 __HAL_TIM_ENABLE(htim);
3746
3747 break;
3748 }
3749 }
3750
3751 /* Return function status */
3752 return HAL_OK;
3753 }
3754
3755 /**
3756 * @brief Stops the TIM Encoder Interface in DMA mode.
3757 * @param htim TIM Encoder Interface handle
3758 * @param Channel TIM Channels to be enabled
3759 * This parameter can be one of the following values:
3760 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3761 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3762 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3763 * @retval HAL status
3764 */
HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)3765 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
3766 {
3767 /* Check the parameters */
3768 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3769
3770 /* Disable the Input Capture channels 1 and 2
3771 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3772 if (Channel == TIM_CHANNEL_1)
3773 {
3774 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3775
3776 /* Disable the capture compare DMA Request 1 */
3777 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3778 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3779 }
3780 else if (Channel == TIM_CHANNEL_2)
3781 {
3782 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3783
3784 /* Disable the capture compare DMA Request 2 */
3785 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3786 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3787 }
3788 else
3789 {
3790 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3791 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3792
3793 /* Disable the capture compare DMA Request 1 and 2 */
3794 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3795 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3796 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3797 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3798 }
3799
3800 /* Disable the Peripheral */
3801 __HAL_TIM_DISABLE(htim);
3802
3803 /* Set the TIM channel(s) state */
3804 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3805 {
3806 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3807 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3808 }
3809 else
3810 {
3811 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3812 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3813 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3814 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3815 }
3816
3817 /* Return function status */
3818 return HAL_OK;
3819 }
3820
3821 /**
3822 * @}
3823 */
3824 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
3825 * @brief TIM IRQ handler management
3826 *
3827 @verbatim
3828 ==============================================================================
3829 ##### IRQ handler management #####
3830 ==============================================================================
3831 [..]
3832 This section provides Timer IRQ handler function.
3833
3834 @endverbatim
3835 * @{
3836 */
3837 /**
3838 * @brief This function handles TIM interrupts requests.
3839 * @param htim TIM handle
3840 * @retval None
3841 */
HAL_TIM_IRQHandler(TIM_HandleTypeDef * htim)3842 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
3843 {
3844 uint32_t itsource = htim->Instance->DIER;
3845 uint32_t itflag = htim->Instance->SR;
3846
3847 /* Capture compare 1 event */
3848 if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
3849 {
3850 if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
3851 {
3852 {
3853 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
3854 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3855
3856 /* Input capture event */
3857 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
3858 {
3859 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3860 htim->IC_CaptureCallback(htim);
3861 #else
3862 HAL_TIM_IC_CaptureCallback(htim);
3863 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3864 }
3865 /* Output compare event */
3866 else
3867 {
3868 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3869 htim->OC_DelayElapsedCallback(htim);
3870 htim->PWM_PulseFinishedCallback(htim);
3871 #else
3872 HAL_TIM_OC_DelayElapsedCallback(htim);
3873 HAL_TIM_PWM_PulseFinishedCallback(htim);
3874 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3875 }
3876 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3877 }
3878 }
3879 }
3880 /* Capture compare 2 event */
3881 if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
3882 {
3883 if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
3884 {
3885 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
3886 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3887 /* Input capture event */
3888 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
3889 {
3890 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3891 htim->IC_CaptureCallback(htim);
3892 #else
3893 HAL_TIM_IC_CaptureCallback(htim);
3894 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3895 }
3896 /* Output compare event */
3897 else
3898 {
3899 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3900 htim->OC_DelayElapsedCallback(htim);
3901 htim->PWM_PulseFinishedCallback(htim);
3902 #else
3903 HAL_TIM_OC_DelayElapsedCallback(htim);
3904 HAL_TIM_PWM_PulseFinishedCallback(htim);
3905 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3906 }
3907 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3908 }
3909 }
3910 /* Capture compare 3 event */
3911 if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
3912 {
3913 if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
3914 {
3915 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
3916 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3917 /* Input capture event */
3918 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
3919 {
3920 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3921 htim->IC_CaptureCallback(htim);
3922 #else
3923 HAL_TIM_IC_CaptureCallback(htim);
3924 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3925 }
3926 /* Output compare event */
3927 else
3928 {
3929 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3930 htim->OC_DelayElapsedCallback(htim);
3931 htim->PWM_PulseFinishedCallback(htim);
3932 #else
3933 HAL_TIM_OC_DelayElapsedCallback(htim);
3934 HAL_TIM_PWM_PulseFinishedCallback(htim);
3935 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3936 }
3937 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3938 }
3939 }
3940 /* Capture compare 4 event */
3941 if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
3942 {
3943 if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
3944 {
3945 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
3946 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3947 /* Input capture event */
3948 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
3949 {
3950 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3951 htim->IC_CaptureCallback(htim);
3952 #else
3953 HAL_TIM_IC_CaptureCallback(htim);
3954 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3955 }
3956 /* Output compare event */
3957 else
3958 {
3959 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3960 htim->OC_DelayElapsedCallback(htim);
3961 htim->PWM_PulseFinishedCallback(htim);
3962 #else
3963 HAL_TIM_OC_DelayElapsedCallback(htim);
3964 HAL_TIM_PWM_PulseFinishedCallback(htim);
3965 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3966 }
3967 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3968 }
3969 }
3970 /* TIM Update event */
3971 if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
3972 {
3973 if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
3974 {
3975 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
3976 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3977 htim->PeriodElapsedCallback(htim);
3978 #else
3979 HAL_TIM_PeriodElapsedCallback(htim);
3980 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3981 }
3982 }
3983 /* TIM Break input event */
3984 if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK))
3985 {
3986 if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
3987 {
3988 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
3989 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3990 htim->BreakCallback(htim);
3991 #else
3992 HAL_TIMEx_BreakCallback(htim);
3993 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3994 }
3995 }
3996 /* TIM Break2 input event */
3997 if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
3998 {
3999 if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
4000 {
4001 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
4002 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4003 htim->Break2Callback(htim);
4004 #else
4005 HAL_TIMEx_Break2Callback(htim);
4006 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4007 }
4008 }
4009 /* TIM Trigger detection event */
4010 if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
4011 {
4012 if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
4013 {
4014 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
4015 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4016 htim->TriggerCallback(htim);
4017 #else
4018 HAL_TIM_TriggerCallback(htim);
4019 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4020 }
4021 }
4022 /* TIM commutation event */
4023 if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
4024 {
4025 if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
4026 {
4027 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
4028 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4029 htim->CommutationCallback(htim);
4030 #else
4031 HAL_TIMEx_CommutCallback(htim);
4032 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4033 }
4034 }
4035 }
4036
4037 /**
4038 * @}
4039 */
4040
4041 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
4042 * @brief TIM Peripheral Control functions
4043 *
4044 @verbatim
4045 ==============================================================================
4046 ##### Peripheral Control functions #####
4047 ==============================================================================
4048 [..]
4049 This section provides functions allowing to:
4050 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
4051 (+) Configure External Clock source.
4052 (+) Configure Complementary channels, break features and dead time.
4053 (+) Configure Master and the Slave synchronization.
4054 (+) Configure the DMA Burst Mode.
4055
4056 @endverbatim
4057 * @{
4058 */
4059
4060 /**
4061 * @brief Initializes the TIM Output Compare Channels according to the specified
4062 * parameters in the TIM_OC_InitTypeDef.
4063 * @param htim TIM Output Compare handle
4064 * @param sConfig TIM Output Compare configuration structure
4065 * @param Channel TIM Channels to configure
4066 * This parameter can be one of the following values:
4067 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4068 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4069 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4070 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4071 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
4072 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
4073 * @retval HAL status
4074 */
HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_OC_InitTypeDef * sConfig,uint32_t Channel)4075 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
4076 const TIM_OC_InitTypeDef *sConfig,
4077 uint32_t Channel)
4078 {
4079 HAL_StatusTypeDef status = HAL_OK;
4080
4081 /* Check the parameters */
4082 assert_param(IS_TIM_CHANNELS(Channel));
4083 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
4084 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4085
4086 /* Process Locked */
4087 __HAL_LOCK(htim);
4088
4089 switch (Channel)
4090 {
4091 case TIM_CHANNEL_1:
4092 {
4093 /* Check the parameters */
4094 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4095
4096 /* Configure the TIM Channel 1 in Output Compare */
4097 TIM_OC1_SetConfig(htim->Instance, sConfig);
4098 break;
4099 }
4100
4101 case TIM_CHANNEL_2:
4102 {
4103 /* Check the parameters */
4104 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4105
4106 /* Configure the TIM Channel 2 in Output Compare */
4107 TIM_OC2_SetConfig(htim->Instance, sConfig);
4108 break;
4109 }
4110
4111 case TIM_CHANNEL_3:
4112 {
4113 /* Check the parameters */
4114 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4115
4116 /* Configure the TIM Channel 3 in Output Compare */
4117 TIM_OC3_SetConfig(htim->Instance, sConfig);
4118 break;
4119 }
4120
4121 case TIM_CHANNEL_4:
4122 {
4123 /* Check the parameters */
4124 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4125
4126 /* Configure the TIM Channel 4 in Output Compare */
4127 TIM_OC4_SetConfig(htim->Instance, sConfig);
4128 break;
4129 }
4130
4131 case TIM_CHANNEL_5:
4132 {
4133 /* Check the parameters */
4134 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
4135
4136 /* Configure the TIM Channel 5 in Output Compare */
4137 TIM_OC5_SetConfig(htim->Instance, sConfig);
4138 break;
4139 }
4140
4141 case TIM_CHANNEL_6:
4142 {
4143 /* Check the parameters */
4144 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
4145
4146 /* Configure the TIM Channel 6 in Output Compare */
4147 TIM_OC6_SetConfig(htim->Instance, sConfig);
4148 break;
4149 }
4150
4151 default:
4152 status = HAL_ERROR;
4153 break;
4154 }
4155
4156 __HAL_UNLOCK(htim);
4157
4158 return status;
4159 }
4160
4161 /**
4162 * @brief Initializes the TIM Input Capture Channels according to the specified
4163 * parameters in the TIM_IC_InitTypeDef.
4164 * @param htim TIM IC handle
4165 * @param sConfig TIM Input Capture configuration structure
4166 * @param Channel TIM Channel to configure
4167 * This parameter can be one of the following values:
4168 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4169 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4170 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4171 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4172 * @retval HAL status
4173 */
HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_IC_InitTypeDef * sConfig,uint32_t Channel)4174 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
4175 {
4176 HAL_StatusTypeDef status = HAL_OK;
4177
4178 /* Check the parameters */
4179 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4180 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
4181 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
4182 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
4183 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
4184
4185 /* Process Locked */
4186 __HAL_LOCK(htim);
4187
4188 if (Channel == TIM_CHANNEL_1)
4189 {
4190 /* TI1 Configuration */
4191 TIM_TI1_SetConfig(htim->Instance,
4192 sConfig->ICPolarity,
4193 sConfig->ICSelection,
4194 sConfig->ICFilter);
4195
4196 /* Reset the IC1PSC Bits */
4197 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4198
4199 /* Set the IC1PSC value */
4200 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
4201 }
4202 else if (Channel == TIM_CHANNEL_2)
4203 {
4204 /* TI2 Configuration */
4205 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4206
4207 TIM_TI2_SetConfig(htim->Instance,
4208 sConfig->ICPolarity,
4209 sConfig->ICSelection,
4210 sConfig->ICFilter);
4211
4212 /* Reset the IC2PSC Bits */
4213 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4214
4215 /* Set the IC2PSC value */
4216 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
4217 }
4218 else if (Channel == TIM_CHANNEL_3)
4219 {
4220 /* TI3 Configuration */
4221 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4222
4223 TIM_TI3_SetConfig(htim->Instance,
4224 sConfig->ICPolarity,
4225 sConfig->ICSelection,
4226 sConfig->ICFilter);
4227
4228 /* Reset the IC3PSC Bits */
4229 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
4230
4231 /* Set the IC3PSC value */
4232 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
4233 }
4234 else if (Channel == TIM_CHANNEL_4)
4235 {
4236 /* TI4 Configuration */
4237 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4238
4239 TIM_TI4_SetConfig(htim->Instance,
4240 sConfig->ICPolarity,
4241 sConfig->ICSelection,
4242 sConfig->ICFilter);
4243
4244 /* Reset the IC4PSC Bits */
4245 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
4246
4247 /* Set the IC4PSC value */
4248 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
4249 }
4250 else
4251 {
4252 status = HAL_ERROR;
4253 }
4254
4255 __HAL_UNLOCK(htim);
4256
4257 return status;
4258 }
4259
4260 /**
4261 * @brief Initializes the TIM PWM channels according to the specified
4262 * parameters in the TIM_OC_InitTypeDef.
4263 * @param htim TIM PWM handle
4264 * @param sConfig TIM PWM configuration structure
4265 * @param Channel TIM Channels to be configured
4266 * This parameter can be one of the following values:
4267 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4268 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4269 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4270 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4271 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
4272 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
4273 * @retval HAL status
4274 */
HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_OC_InitTypeDef * sConfig,uint32_t Channel)4275 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
4276 const TIM_OC_InitTypeDef *sConfig,
4277 uint32_t Channel)
4278 {
4279 HAL_StatusTypeDef status = HAL_OK;
4280
4281 /* Check the parameters */
4282 assert_param(IS_TIM_CHANNELS(Channel));
4283 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
4284 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4285 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
4286
4287 /* Process Locked */
4288 __HAL_LOCK(htim);
4289
4290 switch (Channel)
4291 {
4292 case TIM_CHANNEL_1:
4293 {
4294 /* Check the parameters */
4295 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4296
4297 /* Configure the Channel 1 in PWM mode */
4298 TIM_OC1_SetConfig(htim->Instance, sConfig);
4299
4300 /* Set the Preload enable bit for channel1 */
4301 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
4302
4303 /* Configure the Output Fast mode */
4304 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
4305 htim->Instance->CCMR1 |= sConfig->OCFastMode;
4306 break;
4307 }
4308
4309 case TIM_CHANNEL_2:
4310 {
4311 /* Check the parameters */
4312 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4313
4314 /* Configure the Channel 2 in PWM mode */
4315 TIM_OC2_SetConfig(htim->Instance, sConfig);
4316
4317 /* Set the Preload enable bit for channel2 */
4318 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
4319
4320 /* Configure the Output Fast mode */
4321 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
4322 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
4323 break;
4324 }
4325
4326 case TIM_CHANNEL_3:
4327 {
4328 /* Check the parameters */
4329 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4330
4331 /* Configure the Channel 3 in PWM mode */
4332 TIM_OC3_SetConfig(htim->Instance, sConfig);
4333
4334 /* Set the Preload enable bit for channel3 */
4335 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
4336
4337 /* Configure the Output Fast mode */
4338 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
4339 htim->Instance->CCMR2 |= sConfig->OCFastMode;
4340 break;
4341 }
4342
4343 case TIM_CHANNEL_4:
4344 {
4345 /* Check the parameters */
4346 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4347
4348 /* Configure the Channel 4 in PWM mode */
4349 TIM_OC4_SetConfig(htim->Instance, sConfig);
4350
4351 /* Set the Preload enable bit for channel4 */
4352 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
4353
4354 /* Configure the Output Fast mode */
4355 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
4356 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
4357 break;
4358 }
4359
4360 case TIM_CHANNEL_5:
4361 {
4362 /* Check the parameters */
4363 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
4364
4365 /* Configure the Channel 5 in PWM mode */
4366 TIM_OC5_SetConfig(htim->Instance, sConfig);
4367
4368 /* Set the Preload enable bit for channel5*/
4369 htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
4370
4371 /* Configure the Output Fast mode */
4372 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
4373 htim->Instance->CCMR3 |= sConfig->OCFastMode;
4374 break;
4375 }
4376
4377 case TIM_CHANNEL_6:
4378 {
4379 /* Check the parameters */
4380 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
4381
4382 /* Configure the Channel 6 in PWM mode */
4383 TIM_OC6_SetConfig(htim->Instance, sConfig);
4384
4385 /* Set the Preload enable bit for channel6 */
4386 htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
4387
4388 /* Configure the Output Fast mode */
4389 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
4390 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
4391 break;
4392 }
4393
4394 default:
4395 status = HAL_ERROR;
4396 break;
4397 }
4398
4399 __HAL_UNLOCK(htim);
4400
4401 return status;
4402 }
4403
4404 /**
4405 * @brief Initializes the TIM One Pulse Channels according to the specified
4406 * parameters in the TIM_OnePulse_InitTypeDef.
4407 * @param htim TIM One Pulse handle
4408 * @param sConfig TIM One Pulse configuration structure
4409 * @param OutputChannel TIM output channel to configure
4410 * This parameter can be one of the following values:
4411 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4412 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4413 * @param InputChannel TIM input Channel to configure
4414 * This parameter can be one of the following values:
4415 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4416 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4417 * @note To output a waveform with a minimum delay user can enable the fast
4418 * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
4419 * output is forced in response to the edge detection on TIx input,
4420 * without taking in account the comparison.
4421 * @retval HAL status
4422 */
HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OnePulse_InitTypeDef * sConfig,uint32_t OutputChannel,uint32_t InputChannel)4423 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
4424 uint32_t OutputChannel, uint32_t InputChannel)
4425 {
4426 HAL_StatusTypeDef status = HAL_OK;
4427 TIM_OC_InitTypeDef temp1;
4428
4429 /* Check the parameters */
4430 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
4431 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
4432
4433 if (OutputChannel != InputChannel)
4434 {
4435 /* Process Locked */
4436 __HAL_LOCK(htim);
4437
4438 htim->State = HAL_TIM_STATE_BUSY;
4439
4440 /* Extract the Output compare configuration from sConfig structure */
4441 temp1.OCMode = sConfig->OCMode;
4442 temp1.Pulse = sConfig->Pulse;
4443 temp1.OCPolarity = sConfig->OCPolarity;
4444 temp1.OCNPolarity = sConfig->OCNPolarity;
4445 temp1.OCIdleState = sConfig->OCIdleState;
4446 temp1.OCNIdleState = sConfig->OCNIdleState;
4447
4448 switch (OutputChannel)
4449 {
4450 case TIM_CHANNEL_1:
4451 {
4452 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4453
4454 TIM_OC1_SetConfig(htim->Instance, &temp1);
4455 break;
4456 }
4457
4458 case TIM_CHANNEL_2:
4459 {
4460 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4461
4462 TIM_OC2_SetConfig(htim->Instance, &temp1);
4463 break;
4464 }
4465
4466 default:
4467 status = HAL_ERROR;
4468 break;
4469 }
4470
4471 if (status == HAL_OK)
4472 {
4473 switch (InputChannel)
4474 {
4475 case TIM_CHANNEL_1:
4476 {
4477 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4478
4479 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
4480 sConfig->ICSelection, sConfig->ICFilter);
4481
4482 /* Reset the IC1PSC Bits */
4483 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4484
4485 /* Select the Trigger source */
4486 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4487 htim->Instance->SMCR |= TIM_TS_TI1FP1;
4488
4489 /* Select the Slave Mode */
4490 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4491 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4492 break;
4493 }
4494
4495 case TIM_CHANNEL_2:
4496 {
4497 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4498
4499 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
4500 sConfig->ICSelection, sConfig->ICFilter);
4501
4502 /* Reset the IC2PSC Bits */
4503 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4504
4505 /* Select the Trigger source */
4506 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4507 htim->Instance->SMCR |= TIM_TS_TI2FP2;
4508
4509 /* Select the Slave Mode */
4510 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4511 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4512 break;
4513 }
4514
4515 default:
4516 status = HAL_ERROR;
4517 break;
4518 }
4519 }
4520
4521 htim->State = HAL_TIM_STATE_READY;
4522
4523 __HAL_UNLOCK(htim);
4524
4525 return status;
4526 }
4527 else
4528 {
4529 return HAL_ERROR;
4530 }
4531 }
4532
4533 /**
4534 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
4535 * @param htim TIM handle
4536 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4537 * This parameter can be one of the following values:
4538 * @arg TIM_DMABASE_CR1
4539 * @arg TIM_DMABASE_CR2
4540 * @arg TIM_DMABASE_SMCR
4541 * @arg TIM_DMABASE_DIER
4542 * @arg TIM_DMABASE_SR
4543 * @arg TIM_DMABASE_EGR
4544 * @arg TIM_DMABASE_CCMR1
4545 * @arg TIM_DMABASE_CCMR2
4546 * @arg TIM_DMABASE_CCER
4547 * @arg TIM_DMABASE_CNT
4548 * @arg TIM_DMABASE_PSC
4549 * @arg TIM_DMABASE_ARR
4550 * @arg TIM_DMABASE_RCR
4551 * @arg TIM_DMABASE_CCR1
4552 * @arg TIM_DMABASE_CCR2
4553 * @arg TIM_DMABASE_CCR3
4554 * @arg TIM_DMABASE_CCR4
4555 * @arg TIM_DMABASE_BDTR
4556 * @arg TIM_DMABASE_CCMR3
4557 * @arg TIM_DMABASE_CCR5
4558 * @arg TIM_DMABASE_CCR6
4559 * @arg TIM_DMABASE_AF1
4560 * @arg TIM_DMABASE_AF2
4561 * @arg TIM_DMABASE_TISEL
4562 * @param BurstRequestSrc TIM DMA Request sources
4563 * This parameter can be one of the following values:
4564 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4565 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4566 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4567 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4568 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4569 * @arg TIM_DMA_COM: TIM Commutation DMA source
4570 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4571 * @param BurstBuffer The Buffer address.
4572 * @param BurstLength DMA Burst length. This parameter can be one value
4573 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4574 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4575 * @retval HAL status
4576 */
HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,const uint32_t * BurstBuffer,uint32_t BurstLength)4577 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4578 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength)
4579 {
4580 HAL_StatusTypeDef status;
4581
4582 status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4583 ((BurstLength) >> 8U) + 1U);
4584
4585
4586
4587 return status;
4588 }
4589
4590 /**
4591 * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
4592 * @param htim TIM handle
4593 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4594 * This parameter can be one of the following values:
4595 * @arg TIM_DMABASE_CR1
4596 * @arg TIM_DMABASE_CR2
4597 * @arg TIM_DMABASE_SMCR
4598 * @arg TIM_DMABASE_DIER
4599 * @arg TIM_DMABASE_SR
4600 * @arg TIM_DMABASE_EGR
4601 * @arg TIM_DMABASE_CCMR1
4602 * @arg TIM_DMABASE_CCMR2
4603 * @arg TIM_DMABASE_CCER
4604 * @arg TIM_DMABASE_CNT
4605 * @arg TIM_DMABASE_PSC
4606 * @arg TIM_DMABASE_ARR
4607 * @arg TIM_DMABASE_RCR
4608 * @arg TIM_DMABASE_CCR1
4609 * @arg TIM_DMABASE_CCR2
4610 * @arg TIM_DMABASE_CCR3
4611 * @arg TIM_DMABASE_CCR4
4612 * @arg TIM_DMABASE_BDTR
4613 * @arg TIM_DMABASE_CCMR3
4614 * @arg TIM_DMABASE_CCR5
4615 * @arg TIM_DMABASE_CCR6
4616 * @arg TIM_DMABASE_AF1
4617 * @arg TIM_DMABASE_AF2
4618 * @arg TIM_DMABASE_TISEL
4619 * @param BurstRequestSrc TIM DMA Request sources
4620 * This parameter can be one of the following values:
4621 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4622 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4623 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4624 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4625 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4626 * @arg TIM_DMA_COM: TIM Commutation DMA source
4627 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4628 * @param BurstBuffer The Buffer address.
4629 * @param BurstLength DMA Burst length. This parameter can be one value
4630 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4631 * @param DataLength Data length. This parameter can be one value
4632 * between 1 and 0xFFFF.
4633 * @retval HAL status
4634 */
HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,const uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)4635 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4636 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
4637 uint32_t BurstLength, uint32_t DataLength)
4638 {
4639 HAL_StatusTypeDef status = HAL_OK;
4640
4641 /* Check the parameters */
4642 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4643 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4644 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4645 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4646 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4647
4648 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
4649 {
4650 return HAL_BUSY;
4651 }
4652 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
4653 {
4654 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4655 {
4656 return HAL_ERROR;
4657 }
4658 else
4659 {
4660 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
4661 }
4662 }
4663 else
4664 {
4665 /* nothing to do */
4666 }
4667
4668 switch (BurstRequestSrc)
4669 {
4670 case TIM_DMA_UPDATE:
4671 {
4672 /* Set the DMA Period elapsed callbacks */
4673 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4674 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4675
4676 /* Set the DMA error callback */
4677 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4678
4679 /* Enable the DMA channel */
4680 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
4681 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4682 {
4683 /* Return error status */
4684 return HAL_ERROR;
4685 }
4686 break;
4687 }
4688 case TIM_DMA_CC1:
4689 {
4690 /* Set the DMA compare callbacks */
4691 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
4692 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4693
4694 /* Set the DMA error callback */
4695 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4696
4697 /* Enable the DMA channel */
4698 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
4699 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4700 {
4701 /* Return error status */
4702 return HAL_ERROR;
4703 }
4704 break;
4705 }
4706 case TIM_DMA_CC2:
4707 {
4708 /* Set the DMA compare callbacks */
4709 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
4710 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4711
4712 /* Set the DMA error callback */
4713 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4714
4715 /* Enable the DMA channel */
4716 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
4717 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4718 {
4719 /* Return error status */
4720 return HAL_ERROR;
4721 }
4722 break;
4723 }
4724 case TIM_DMA_CC3:
4725 {
4726 /* Set the DMA compare callbacks */
4727 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
4728 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4729
4730 /* Set the DMA error callback */
4731 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4732
4733 /* Enable the DMA channel */
4734 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
4735 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4736 {
4737 /* Return error status */
4738 return HAL_ERROR;
4739 }
4740 break;
4741 }
4742 case TIM_DMA_CC4:
4743 {
4744 /* Set the DMA compare callbacks */
4745 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
4746 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4747
4748 /* Set the DMA error callback */
4749 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4750
4751 /* Enable the DMA channel */
4752 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
4753 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4754 {
4755 /* Return error status */
4756 return HAL_ERROR;
4757 }
4758 break;
4759 }
4760 case TIM_DMA_COM:
4761 {
4762 /* Set the DMA commutation callbacks */
4763 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
4764 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
4765
4766 /* Set the DMA error callback */
4767 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
4768
4769 /* Enable the DMA channel */
4770 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
4771 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4772 {
4773 /* Return error status */
4774 return HAL_ERROR;
4775 }
4776 break;
4777 }
4778 case TIM_DMA_TRIGGER:
4779 {
4780 /* Set the DMA trigger callbacks */
4781 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4782 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
4783
4784 /* Set the DMA error callback */
4785 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4786
4787 /* Enable the DMA channel */
4788 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
4789 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4790 {
4791 /* Return error status */
4792 return HAL_ERROR;
4793 }
4794 break;
4795 }
4796 default:
4797 status = HAL_ERROR;
4798 break;
4799 }
4800
4801 if (status == HAL_OK)
4802 {
4803 /* Configure the DMA Burst Mode */
4804 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
4805 /* Enable the TIM DMA Request */
4806 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4807 }
4808
4809 /* Return function status */
4810 return status;
4811 }
4812
4813 /**
4814 * @brief Stops the TIM DMA Burst mode
4815 * @param htim TIM handle
4816 * @param BurstRequestSrc TIM DMA Request sources to disable
4817 * @retval HAL status
4818 */
HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)4819 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4820 {
4821 HAL_StatusTypeDef status = HAL_OK;
4822
4823 /* Check the parameters */
4824 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4825
4826 /* Abort the DMA transfer (at least disable the DMA channel) */
4827 switch (BurstRequestSrc)
4828 {
4829 case TIM_DMA_UPDATE:
4830 {
4831 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4832 break;
4833 }
4834 case TIM_DMA_CC1:
4835 {
4836 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
4837 break;
4838 }
4839 case TIM_DMA_CC2:
4840 {
4841 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
4842 break;
4843 }
4844 case TIM_DMA_CC3:
4845 {
4846 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
4847 break;
4848 }
4849 case TIM_DMA_CC4:
4850 {
4851 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
4852 break;
4853 }
4854 case TIM_DMA_COM:
4855 {
4856 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
4857 break;
4858 }
4859 case TIM_DMA_TRIGGER:
4860 {
4861 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
4862 break;
4863 }
4864 default:
4865 status = HAL_ERROR;
4866 break;
4867 }
4868
4869 if (status == HAL_OK)
4870 {
4871 /* Disable the TIM Update DMA request */
4872 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
4873
4874 /* Change the DMA burst operation state */
4875 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
4876 }
4877
4878 /* Return function status */
4879 return status;
4880 }
4881
4882 /**
4883 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4884 * @param htim TIM handle
4885 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4886 * This parameter can be one of the following values:
4887 * @arg TIM_DMABASE_CR1
4888 * @arg TIM_DMABASE_CR2
4889 * @arg TIM_DMABASE_SMCR
4890 * @arg TIM_DMABASE_DIER
4891 * @arg TIM_DMABASE_SR
4892 * @arg TIM_DMABASE_EGR
4893 * @arg TIM_DMABASE_CCMR1
4894 * @arg TIM_DMABASE_CCMR2
4895 * @arg TIM_DMABASE_CCER
4896 * @arg TIM_DMABASE_CNT
4897 * @arg TIM_DMABASE_PSC
4898 * @arg TIM_DMABASE_ARR
4899 * @arg TIM_DMABASE_RCR
4900 * @arg TIM_DMABASE_CCR1
4901 * @arg TIM_DMABASE_CCR2
4902 * @arg TIM_DMABASE_CCR3
4903 * @arg TIM_DMABASE_CCR4
4904 * @arg TIM_DMABASE_BDTR
4905 * @arg TIM_DMABASE_CCMR3
4906 * @arg TIM_DMABASE_CCR5
4907 * @arg TIM_DMABASE_CCR6
4908 * @arg TIM_DMABASE_AF1
4909 * @arg TIM_DMABASE_AF2
4910 * @arg TIM_DMABASE_TISEL
4911 * @param BurstRequestSrc TIM DMA Request sources
4912 * This parameter can be one of the following values:
4913 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4914 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4915 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4916 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4917 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4918 * @arg TIM_DMA_COM: TIM Commutation DMA source
4919 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4920 * @param BurstBuffer The Buffer address.
4921 * @param BurstLength DMA Burst length. This parameter can be one value
4922 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4923 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4924 * @retval HAL status
4925 */
HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)4926 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4927 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
4928 {
4929 HAL_StatusTypeDef status;
4930
4931 status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4932 ((BurstLength) >> 8U) + 1U);
4933
4934
4935 return status;
4936 }
4937
4938 /**
4939 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4940 * @param htim TIM handle
4941 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4942 * This parameter can be one of the following values:
4943 * @arg TIM_DMABASE_CR1
4944 * @arg TIM_DMABASE_CR2
4945 * @arg TIM_DMABASE_SMCR
4946 * @arg TIM_DMABASE_DIER
4947 * @arg TIM_DMABASE_SR
4948 * @arg TIM_DMABASE_EGR
4949 * @arg TIM_DMABASE_CCMR1
4950 * @arg TIM_DMABASE_CCMR2
4951 * @arg TIM_DMABASE_CCER
4952 * @arg TIM_DMABASE_CNT
4953 * @arg TIM_DMABASE_PSC
4954 * @arg TIM_DMABASE_ARR
4955 * @arg TIM_DMABASE_RCR
4956 * @arg TIM_DMABASE_CCR1
4957 * @arg TIM_DMABASE_CCR2
4958 * @arg TIM_DMABASE_CCR3
4959 * @arg TIM_DMABASE_CCR4
4960 * @arg TIM_DMABASE_BDTR
4961 * @arg TIM_DMABASE_CCMR3
4962 * @arg TIM_DMABASE_CCR5
4963 * @arg TIM_DMABASE_CCR6
4964 * @arg TIM_DMABASE_AF1
4965 * @arg TIM_DMABASE_AF2
4966 * @arg TIM_DMABASE_TISEL
4967 * @param BurstRequestSrc TIM DMA Request sources
4968 * This parameter can be one of the following values:
4969 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4970 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4971 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4972 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4973 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4974 * @arg TIM_DMA_COM: TIM Commutation DMA source
4975 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4976 * @param BurstBuffer The Buffer address.
4977 * @param BurstLength DMA Burst length. This parameter can be one value
4978 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4979 * @param DataLength Data length. This parameter can be one value
4980 * between 1 and 0xFFFF.
4981 * @retval HAL status
4982 */
HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)4983 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4984 uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
4985 uint32_t BurstLength, uint32_t DataLength)
4986 {
4987 HAL_StatusTypeDef status = HAL_OK;
4988
4989 /* Check the parameters */
4990 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4991 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4992 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4993 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4994 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4995
4996 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
4997 {
4998 return HAL_BUSY;
4999 }
5000 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
5001 {
5002 if ((BurstBuffer == NULL) && (BurstLength > 0U))
5003 {
5004 return HAL_ERROR;
5005 }
5006 else
5007 {
5008 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
5009 }
5010 }
5011 else
5012 {
5013 /* nothing to do */
5014 }
5015 switch (BurstRequestSrc)
5016 {
5017 case TIM_DMA_UPDATE:
5018 {
5019 /* Set the DMA Period elapsed callbacks */
5020 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
5021 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
5022
5023 /* Set the DMA error callback */
5024 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
5025
5026 /* Enable the DMA channel */
5027 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5028 DataLength) != HAL_OK)
5029 {
5030 /* Return error status */
5031 return HAL_ERROR;
5032 }
5033 break;
5034 }
5035 case TIM_DMA_CC1:
5036 {
5037 /* Set the DMA capture callbacks */
5038 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
5039 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5040
5041 /* Set the DMA error callback */
5042 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
5043
5044 /* Enable the DMA channel */
5045 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5046 DataLength) != HAL_OK)
5047 {
5048 /* Return error status */
5049 return HAL_ERROR;
5050 }
5051 break;
5052 }
5053 case TIM_DMA_CC2:
5054 {
5055 /* Set the DMA capture callbacks */
5056 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
5057 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5058
5059 /* Set the DMA error callback */
5060 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
5061
5062 /* Enable the DMA channel */
5063 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5064 DataLength) != HAL_OK)
5065 {
5066 /* Return error status */
5067 return HAL_ERROR;
5068 }
5069 break;
5070 }
5071 case TIM_DMA_CC3:
5072 {
5073 /* Set the DMA capture callbacks */
5074 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
5075 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5076
5077 /* Set the DMA error callback */
5078 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
5079
5080 /* Enable the DMA channel */
5081 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5082 DataLength) != HAL_OK)
5083 {
5084 /* Return error status */
5085 return HAL_ERROR;
5086 }
5087 break;
5088 }
5089 case TIM_DMA_CC4:
5090 {
5091 /* Set the DMA capture callbacks */
5092 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
5093 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5094
5095 /* Set the DMA error callback */
5096 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
5097
5098 /* Enable the DMA channel */
5099 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5100 DataLength) != HAL_OK)
5101 {
5102 /* Return error status */
5103 return HAL_ERROR;
5104 }
5105 break;
5106 }
5107 case TIM_DMA_COM:
5108 {
5109 /* Set the DMA commutation callbacks */
5110 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
5111 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
5112
5113 /* Set the DMA error callback */
5114 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
5115
5116 /* Enable the DMA channel */
5117 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5118 DataLength) != HAL_OK)
5119 {
5120 /* Return error status */
5121 return HAL_ERROR;
5122 }
5123 break;
5124 }
5125 case TIM_DMA_TRIGGER:
5126 {
5127 /* Set the DMA trigger callbacks */
5128 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
5129 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
5130
5131 /* Set the DMA error callback */
5132 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
5133
5134 /* Enable the DMA channel */
5135 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5136 DataLength) != HAL_OK)
5137 {
5138 /* Return error status */
5139 return HAL_ERROR;
5140 }
5141 break;
5142 }
5143 default:
5144 status = HAL_ERROR;
5145 break;
5146 }
5147
5148 if (status == HAL_OK)
5149 {
5150 /* Configure the DMA Burst Mode */
5151 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
5152
5153 /* Enable the TIM DMA Request */
5154 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
5155 }
5156
5157 /* Return function status */
5158 return status;
5159 }
5160
5161 /**
5162 * @brief Stop the DMA burst reading
5163 * @param htim TIM handle
5164 * @param BurstRequestSrc TIM DMA Request sources to disable.
5165 * @retval HAL status
5166 */
HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)5167 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
5168 {
5169 HAL_StatusTypeDef status = HAL_OK;
5170
5171 /* Check the parameters */
5172 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
5173
5174 /* Abort the DMA transfer (at least disable the DMA channel) */
5175 switch (BurstRequestSrc)
5176 {
5177 case TIM_DMA_UPDATE:
5178 {
5179 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
5180 break;
5181 }
5182 case TIM_DMA_CC1:
5183 {
5184 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
5185 break;
5186 }
5187 case TIM_DMA_CC2:
5188 {
5189 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
5190 break;
5191 }
5192 case TIM_DMA_CC3:
5193 {
5194 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
5195 break;
5196 }
5197 case TIM_DMA_CC4:
5198 {
5199 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
5200 break;
5201 }
5202 case TIM_DMA_COM:
5203 {
5204 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
5205 break;
5206 }
5207 case TIM_DMA_TRIGGER:
5208 {
5209 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
5210 break;
5211 }
5212 default:
5213 status = HAL_ERROR;
5214 break;
5215 }
5216
5217 if (status == HAL_OK)
5218 {
5219 /* Disable the TIM Update DMA request */
5220 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
5221
5222 /* Change the DMA burst operation state */
5223 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
5224 }
5225
5226 /* Return function status */
5227 return status;
5228 }
5229
5230 /**
5231 * @brief Generate a software event
5232 * @param htim TIM handle
5233 * @param EventSource specifies the event source.
5234 * This parameter can be one of the following values:
5235 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
5236 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
5237 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
5238 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
5239 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
5240 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
5241 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
5242 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
5243 * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
5244 * @note Basic timers can only generate an update event.
5245 * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
5246 * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
5247 * only for timer instances supporting break input(s).
5248 * @retval HAL status
5249 */
5250
HAL_TIM_GenerateEvent(TIM_HandleTypeDef * htim,uint32_t EventSource)5251 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
5252 {
5253 /* Check the parameters */
5254 assert_param(IS_TIM_INSTANCE(htim->Instance));
5255 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
5256
5257 /* Process Locked */
5258 __HAL_LOCK(htim);
5259
5260 /* Change the TIM state */
5261 htim->State = HAL_TIM_STATE_BUSY;
5262
5263 /* Set the event sources */
5264 htim->Instance->EGR = EventSource;
5265
5266 /* Change the TIM state */
5267 htim->State = HAL_TIM_STATE_READY;
5268
5269 __HAL_UNLOCK(htim);
5270
5271 /* Return function status */
5272 return HAL_OK;
5273 }
5274
5275 /**
5276 * @brief Configures the OCRef clear feature
5277 * @param htim TIM handle
5278 * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
5279 * contains the OCREF clear feature and parameters for the TIM peripheral.
5280 * @param Channel specifies the TIM Channel
5281 * This parameter can be one of the following values:
5282 * @arg TIM_CHANNEL_1: TIM Channel 1
5283 * @arg TIM_CHANNEL_2: TIM Channel 2
5284 * @arg TIM_CHANNEL_3: TIM Channel 3
5285 * @arg TIM_CHANNEL_4: TIM Channel 4
5286 * @arg TIM_CHANNEL_5: TIM Channel 5
5287 * @arg TIM_CHANNEL_6: TIM Channel 6
5288 * @retval HAL status
5289 */
HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef * htim,const TIM_ClearInputConfigTypeDef * sClearInputConfig,uint32_t Channel)5290 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
5291 const TIM_ClearInputConfigTypeDef *sClearInputConfig,
5292 uint32_t Channel)
5293 {
5294 HAL_StatusTypeDef status = HAL_OK;
5295
5296 /* Check the parameters */
5297 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
5298 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
5299
5300 /* Process Locked */
5301 __HAL_LOCK(htim);
5302
5303 htim->State = HAL_TIM_STATE_BUSY;
5304
5305 switch (sClearInputConfig->ClearInputSource)
5306 {
5307 case TIM_CLEARINPUTSOURCE_NONE:
5308 {
5309 /* Clear the OCREF clear selection bit and the the ETR Bits */
5310 CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
5311 break;
5312 }
5313
5314 case TIM_CLEARINPUTSOURCE_ETR:
5315 {
5316 /* Check the parameters */
5317 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
5318 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
5319 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
5320
5321 /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
5322 if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
5323 {
5324 htim->State = HAL_TIM_STATE_READY;
5325 __HAL_UNLOCK(htim);
5326 return HAL_ERROR;
5327 }
5328
5329 TIM_ETR_SetConfig(htim->Instance,
5330 sClearInputConfig->ClearInputPrescaler,
5331 sClearInputConfig->ClearInputPolarity,
5332 sClearInputConfig->ClearInputFilter);
5333
5334 /* Set the OCREF clear selection bit */
5335 SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
5336 break;
5337 }
5338
5339 default:
5340 status = HAL_ERROR;
5341 break;
5342 }
5343
5344 if (status == HAL_OK)
5345 {
5346 switch (Channel)
5347 {
5348 case TIM_CHANNEL_1:
5349 {
5350 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5351 {
5352 /* Enable the OCREF clear feature for Channel 1 */
5353 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5354 }
5355 else
5356 {
5357 /* Disable the OCREF clear feature for Channel 1 */
5358 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5359 }
5360 break;
5361 }
5362 case TIM_CHANNEL_2:
5363 {
5364 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5365 {
5366 /* Enable the OCREF clear feature for Channel 2 */
5367 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5368 }
5369 else
5370 {
5371 /* Disable the OCREF clear feature for Channel 2 */
5372 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5373 }
5374 break;
5375 }
5376 case TIM_CHANNEL_3:
5377 {
5378 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5379 {
5380 /* Enable the OCREF clear feature for Channel 3 */
5381 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5382 }
5383 else
5384 {
5385 /* Disable the OCREF clear feature for Channel 3 */
5386 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5387 }
5388 break;
5389 }
5390 case TIM_CHANNEL_4:
5391 {
5392 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5393 {
5394 /* Enable the OCREF clear feature for Channel 4 */
5395 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5396 }
5397 else
5398 {
5399 /* Disable the OCREF clear feature for Channel 4 */
5400 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5401 }
5402 break;
5403 }
5404 case TIM_CHANNEL_5:
5405 {
5406 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5407 {
5408 /* Enable the OCREF clear feature for Channel 5 */
5409 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
5410 }
5411 else
5412 {
5413 /* Disable the OCREF clear feature for Channel 5 */
5414 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
5415 }
5416 break;
5417 }
5418 case TIM_CHANNEL_6:
5419 {
5420 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5421 {
5422 /* Enable the OCREF clear feature for Channel 6 */
5423 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
5424 }
5425 else
5426 {
5427 /* Disable the OCREF clear feature for Channel 6 */
5428 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
5429 }
5430 break;
5431 }
5432 default:
5433 break;
5434 }
5435 }
5436
5437 htim->State = HAL_TIM_STATE_READY;
5438
5439 __HAL_UNLOCK(htim);
5440
5441 return status;
5442 }
5443
5444 /**
5445 * @brief Configures the clock source to be used
5446 * @param htim TIM handle
5447 * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
5448 * contains the clock source information for the TIM peripheral.
5449 * @retval HAL status
5450 */
HAL_TIM_ConfigClockSource(TIM_HandleTypeDef * htim,const TIM_ClockConfigTypeDef * sClockSourceConfig)5451 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
5452 {
5453 HAL_StatusTypeDef status = HAL_OK;
5454 uint32_t tmpsmcr;
5455
5456 /* Process Locked */
5457 __HAL_LOCK(htim);
5458
5459 htim->State = HAL_TIM_STATE_BUSY;
5460
5461 /* Check the parameters */
5462 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
5463
5464 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
5465 tmpsmcr = htim->Instance->SMCR;
5466 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
5467 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
5468 htim->Instance->SMCR = tmpsmcr;
5469
5470 switch (sClockSourceConfig->ClockSource)
5471 {
5472 case TIM_CLOCKSOURCE_INTERNAL:
5473 {
5474 assert_param(IS_TIM_INSTANCE(htim->Instance));
5475 break;
5476 }
5477
5478 case TIM_CLOCKSOURCE_ETRMODE1:
5479 {
5480 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
5481 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
5482
5483 /* Check ETR input conditioning related parameters */
5484 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5485 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5486 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5487
5488 /* Configure the ETR Clock source */
5489 TIM_ETR_SetConfig(htim->Instance,
5490 sClockSourceConfig->ClockPrescaler,
5491 sClockSourceConfig->ClockPolarity,
5492 sClockSourceConfig->ClockFilter);
5493
5494 /* Select the External clock mode1 and the ETRF trigger */
5495 tmpsmcr = htim->Instance->SMCR;
5496 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
5497 /* Write to TIMx SMCR */
5498 htim->Instance->SMCR = tmpsmcr;
5499 break;
5500 }
5501
5502 case TIM_CLOCKSOURCE_ETRMODE2:
5503 {
5504 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
5505 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
5506
5507 /* Check ETR input conditioning related parameters */
5508 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5509 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5510 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5511
5512 /* Configure the ETR Clock source */
5513 TIM_ETR_SetConfig(htim->Instance,
5514 sClockSourceConfig->ClockPrescaler,
5515 sClockSourceConfig->ClockPolarity,
5516 sClockSourceConfig->ClockFilter);
5517 /* Enable the External clock mode2 */
5518 htim->Instance->SMCR |= TIM_SMCR_ECE;
5519 break;
5520 }
5521
5522 case TIM_CLOCKSOURCE_TI1:
5523 {
5524 /* Check whether or not the timer instance supports external clock mode 1 */
5525 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5526
5527 /* Check TI1 input conditioning related parameters */
5528 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5529 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5530
5531 TIM_TI1_ConfigInputStage(htim->Instance,
5532 sClockSourceConfig->ClockPolarity,
5533 sClockSourceConfig->ClockFilter);
5534 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
5535 break;
5536 }
5537
5538 case TIM_CLOCKSOURCE_TI2:
5539 {
5540 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
5541 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5542
5543 /* Check TI2 input conditioning related parameters */
5544 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5545 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5546
5547 TIM_TI2_ConfigInputStage(htim->Instance,
5548 sClockSourceConfig->ClockPolarity,
5549 sClockSourceConfig->ClockFilter);
5550 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
5551 break;
5552 }
5553
5554 case TIM_CLOCKSOURCE_TI1ED:
5555 {
5556 /* Check whether or not the timer instance supports external clock mode 1 */
5557 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5558
5559 /* Check TI1 input conditioning related parameters */
5560 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5561 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5562
5563 TIM_TI1_ConfigInputStage(htim->Instance,
5564 sClockSourceConfig->ClockPolarity,
5565 sClockSourceConfig->ClockFilter);
5566 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
5567 break;
5568 }
5569
5570 case TIM_CLOCKSOURCE_ITR0:
5571 case TIM_CLOCKSOURCE_ITR1:
5572 case TIM_CLOCKSOURCE_ITR2:
5573 case TIM_CLOCKSOURCE_ITR3:
5574 {
5575 /* Check whether or not the timer instance supports internal trigger input */
5576 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
5577
5578 TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
5579 break;
5580 }
5581
5582 default:
5583 status = HAL_ERROR;
5584 break;
5585 }
5586 htim->State = HAL_TIM_STATE_READY;
5587
5588 __HAL_UNLOCK(htim);
5589
5590 return status;
5591 }
5592
5593 /**
5594 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
5595 * or a XOR combination between CH1_input, CH2_input & CH3_input
5596 * @param htim TIM handle.
5597 * @param TI1_Selection Indicate whether or not channel 1 is connected to the
5598 * output of a XOR gate.
5599 * This parameter can be one of the following values:
5600 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
5601 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
5602 * pins are connected to the TI1 input (XOR combination)
5603 * @retval HAL status
5604 */
HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef * htim,uint32_t TI1_Selection)5605 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
5606 {
5607 uint32_t tmpcr2;
5608
5609 /* Check the parameters */
5610 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
5611 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
5612
5613 /* Get the TIMx CR2 register value */
5614 tmpcr2 = htim->Instance->CR2;
5615
5616 /* Reset the TI1 selection */
5617 tmpcr2 &= ~TIM_CR2_TI1S;
5618
5619 /* Set the TI1 selection */
5620 tmpcr2 |= TI1_Selection;
5621
5622 /* Write to TIMxCR2 */
5623 htim->Instance->CR2 = tmpcr2;
5624
5625 return HAL_OK;
5626 }
5627
5628 /**
5629 * @brief Configures the TIM in Slave mode
5630 * @param htim TIM handle.
5631 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5632 * contains the selected trigger (internal trigger input, filtered
5633 * timer input or external trigger input) and the Slave mode
5634 * (Disable, Reset, Gated, Trigger, External clock mode 1).
5635 * @retval HAL status
5636 */
HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)5637 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
5638 {
5639 /* Check the parameters */
5640 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5641 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5642 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
5643
5644 __HAL_LOCK(htim);
5645
5646 htim->State = HAL_TIM_STATE_BUSY;
5647
5648 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5649 {
5650 htim->State = HAL_TIM_STATE_READY;
5651 __HAL_UNLOCK(htim);
5652 return HAL_ERROR;
5653 }
5654
5655 /* Disable Trigger Interrupt */
5656 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
5657
5658 /* Disable Trigger DMA request */
5659 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5660
5661 htim->State = HAL_TIM_STATE_READY;
5662
5663 __HAL_UNLOCK(htim);
5664
5665 return HAL_OK;
5666 }
5667
5668 /**
5669 * @brief Configures the TIM in Slave mode in interrupt mode
5670 * @param htim TIM handle.
5671 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5672 * contains the selected trigger (internal trigger input, filtered
5673 * timer input or external trigger input) and the Slave mode
5674 * (Disable, Reset, Gated, Trigger, External clock mode 1).
5675 * @retval HAL status
5676 */
HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)5677 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
5678 const TIM_SlaveConfigTypeDef *sSlaveConfig)
5679 {
5680 /* Check the parameters */
5681 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5682 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5683 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
5684
5685 __HAL_LOCK(htim);
5686
5687 htim->State = HAL_TIM_STATE_BUSY;
5688
5689 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5690 {
5691 htim->State = HAL_TIM_STATE_READY;
5692 __HAL_UNLOCK(htim);
5693 return HAL_ERROR;
5694 }
5695
5696 /* Enable Trigger Interrupt */
5697 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
5698
5699 /* Disable Trigger DMA request */
5700 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5701
5702 htim->State = HAL_TIM_STATE_READY;
5703
5704 __HAL_UNLOCK(htim);
5705
5706 return HAL_OK;
5707 }
5708
5709 /**
5710 * @brief Read the captured value from Capture Compare unit
5711 * @param htim TIM handle.
5712 * @param Channel TIM Channels to be enabled
5713 * This parameter can be one of the following values:
5714 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
5715 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
5716 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
5717 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
5718 * @retval Captured value
5719 */
HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef * htim,uint32_t Channel)5720 uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel)
5721 {
5722 uint32_t tmpreg = 0U;
5723
5724 switch (Channel)
5725 {
5726 case TIM_CHANNEL_1:
5727 {
5728 /* Check the parameters */
5729 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
5730
5731 /* Return the capture 1 value */
5732 tmpreg = htim->Instance->CCR1;
5733
5734 break;
5735 }
5736 case TIM_CHANNEL_2:
5737 {
5738 /* Check the parameters */
5739 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
5740
5741 /* Return the capture 2 value */
5742 tmpreg = htim->Instance->CCR2;
5743
5744 break;
5745 }
5746
5747 case TIM_CHANNEL_3:
5748 {
5749 /* Check the parameters */
5750 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
5751
5752 /* Return the capture 3 value */
5753 tmpreg = htim->Instance->CCR3;
5754
5755 break;
5756 }
5757
5758 case TIM_CHANNEL_4:
5759 {
5760 /* Check the parameters */
5761 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
5762
5763 /* Return the capture 4 value */
5764 tmpreg = htim->Instance->CCR4;
5765
5766 break;
5767 }
5768
5769 default:
5770 break;
5771 }
5772
5773 return tmpreg;
5774 }
5775
5776 /**
5777 * @}
5778 */
5779
5780 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
5781 * @brief TIM Callbacks functions
5782 *
5783 @verbatim
5784 ==============================================================================
5785 ##### TIM Callbacks functions #####
5786 ==============================================================================
5787 [..]
5788 This section provides TIM callback functions:
5789 (+) TIM Period elapsed callback
5790 (+) TIM Output Compare callback
5791 (+) TIM Input capture callback
5792 (+) TIM Trigger callback
5793 (+) TIM Error callback
5794
5795 @endverbatim
5796 * @{
5797 */
5798
5799 /**
5800 * @brief Period elapsed callback in non-blocking mode
5801 * @param htim TIM handle
5802 * @retval None
5803 */
HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef * htim)5804 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
5805 {
5806 /* Prevent unused argument(s) compilation warning */
5807 UNUSED(htim);
5808
5809 /* NOTE : This function should not be modified, when the callback is needed,
5810 the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
5811 */
5812 }
5813
5814 /**
5815 * @brief Period elapsed half complete callback in non-blocking mode
5816 * @param htim TIM handle
5817 * @retval None
5818 */
HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef * htim)5819 __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
5820 {
5821 /* Prevent unused argument(s) compilation warning */
5822 UNUSED(htim);
5823
5824 /* NOTE : This function should not be modified, when the callback is needed,
5825 the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
5826 */
5827 }
5828
5829 /**
5830 * @brief Output Compare callback in non-blocking mode
5831 * @param htim TIM OC handle
5832 * @retval None
5833 */
HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef * htim)5834 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
5835 {
5836 /* Prevent unused argument(s) compilation warning */
5837 UNUSED(htim);
5838
5839 /* NOTE : This function should not be modified, when the callback is needed,
5840 the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
5841 */
5842 }
5843
5844 /**
5845 * @brief Input Capture callback in non-blocking mode
5846 * @param htim TIM IC handle
5847 * @retval None
5848 */
HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef * htim)5849 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
5850 {
5851 /* Prevent unused argument(s) compilation warning */
5852 UNUSED(htim);
5853
5854 /* NOTE : This function should not be modified, when the callback is needed,
5855 the HAL_TIM_IC_CaptureCallback could be implemented in the user file
5856 */
5857 }
5858
5859 /**
5860 * @brief Input Capture half complete callback in non-blocking mode
5861 * @param htim TIM IC handle
5862 * @retval None
5863 */
HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef * htim)5864 __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
5865 {
5866 /* Prevent unused argument(s) compilation warning */
5867 UNUSED(htim);
5868
5869 /* NOTE : This function should not be modified, when the callback is needed,
5870 the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
5871 */
5872 }
5873
5874 /**
5875 * @brief PWM Pulse finished callback in non-blocking mode
5876 * @param htim TIM handle
5877 * @retval None
5878 */
HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef * htim)5879 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
5880 {
5881 /* Prevent unused argument(s) compilation warning */
5882 UNUSED(htim);
5883
5884 /* NOTE : This function should not be modified, when the callback is needed,
5885 the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
5886 */
5887 }
5888
5889 /**
5890 * @brief PWM Pulse finished half complete callback in non-blocking mode
5891 * @param htim TIM handle
5892 * @retval None
5893 */
HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef * htim)5894 __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
5895 {
5896 /* Prevent unused argument(s) compilation warning */
5897 UNUSED(htim);
5898
5899 /* NOTE : This function should not be modified, when the callback is needed,
5900 the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
5901 */
5902 }
5903
5904 /**
5905 * @brief Hall Trigger detection callback in non-blocking mode
5906 * @param htim TIM handle
5907 * @retval None
5908 */
HAL_TIM_TriggerCallback(TIM_HandleTypeDef * htim)5909 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
5910 {
5911 /* Prevent unused argument(s) compilation warning */
5912 UNUSED(htim);
5913
5914 /* NOTE : This function should not be modified, when the callback is needed,
5915 the HAL_TIM_TriggerCallback could be implemented in the user file
5916 */
5917 }
5918
5919 /**
5920 * @brief Hall Trigger detection half complete callback in non-blocking mode
5921 * @param htim TIM handle
5922 * @retval None
5923 */
HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef * htim)5924 __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
5925 {
5926 /* Prevent unused argument(s) compilation warning */
5927 UNUSED(htim);
5928
5929 /* NOTE : This function should not be modified, when the callback is needed,
5930 the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
5931 */
5932 }
5933
5934 /**
5935 * @brief Timer error callback in non-blocking mode
5936 * @param htim TIM handle
5937 * @retval None
5938 */
HAL_TIM_ErrorCallback(TIM_HandleTypeDef * htim)5939 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
5940 {
5941 /* Prevent unused argument(s) compilation warning */
5942 UNUSED(htim);
5943
5944 /* NOTE : This function should not be modified, when the callback is needed,
5945 the HAL_TIM_ErrorCallback could be implemented in the user file
5946 */
5947 }
5948
5949 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5950 /**
5951 * @brief Register a User TIM callback to be used instead of the weak predefined callback
5952 * @param htim tim handle
5953 * @param CallbackID ID of the callback to be registered
5954 * This parameter can be one of the following values:
5955 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
5956 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
5957 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
5958 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
5959 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
5960 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
5961 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
5962 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
5963 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
5964 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
5965 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
5966 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
5967 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
5968 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
5969 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
5970 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
5971 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
5972 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
5973 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
5974 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
5975 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
5976 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
5977 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
5978 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
5979 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
5980 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
5981 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
5982 * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
5983 * @param pCallback pointer to the callback function
5984 * @retval status
5985 */
HAL_TIM_RegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID,pTIM_CallbackTypeDef pCallback)5986 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
5987 pTIM_CallbackTypeDef pCallback)
5988 {
5989 HAL_StatusTypeDef status = HAL_OK;
5990
5991 if (pCallback == NULL)
5992 {
5993 return HAL_ERROR;
5994 }
5995
5996 if (htim->State == HAL_TIM_STATE_READY)
5997 {
5998 switch (CallbackID)
5999 {
6000 case HAL_TIM_BASE_MSPINIT_CB_ID :
6001 htim->Base_MspInitCallback = pCallback;
6002 break;
6003
6004 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6005 htim->Base_MspDeInitCallback = pCallback;
6006 break;
6007
6008 case HAL_TIM_IC_MSPINIT_CB_ID :
6009 htim->IC_MspInitCallback = pCallback;
6010 break;
6011
6012 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6013 htim->IC_MspDeInitCallback = pCallback;
6014 break;
6015
6016 case HAL_TIM_OC_MSPINIT_CB_ID :
6017 htim->OC_MspInitCallback = pCallback;
6018 break;
6019
6020 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6021 htim->OC_MspDeInitCallback = pCallback;
6022 break;
6023
6024 case HAL_TIM_PWM_MSPINIT_CB_ID :
6025 htim->PWM_MspInitCallback = pCallback;
6026 break;
6027
6028 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6029 htim->PWM_MspDeInitCallback = pCallback;
6030 break;
6031
6032 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6033 htim->OnePulse_MspInitCallback = pCallback;
6034 break;
6035
6036 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6037 htim->OnePulse_MspDeInitCallback = pCallback;
6038 break;
6039
6040 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6041 htim->Encoder_MspInitCallback = pCallback;
6042 break;
6043
6044 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6045 htim->Encoder_MspDeInitCallback = pCallback;
6046 break;
6047
6048 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6049 htim->HallSensor_MspInitCallback = pCallback;
6050 break;
6051
6052 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6053 htim->HallSensor_MspDeInitCallback = pCallback;
6054 break;
6055
6056 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
6057 htim->PeriodElapsedCallback = pCallback;
6058 break;
6059
6060 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
6061 htim->PeriodElapsedHalfCpltCallback = pCallback;
6062 break;
6063
6064 case HAL_TIM_TRIGGER_CB_ID :
6065 htim->TriggerCallback = pCallback;
6066 break;
6067
6068 case HAL_TIM_TRIGGER_HALF_CB_ID :
6069 htim->TriggerHalfCpltCallback = pCallback;
6070 break;
6071
6072 case HAL_TIM_IC_CAPTURE_CB_ID :
6073 htim->IC_CaptureCallback = pCallback;
6074 break;
6075
6076 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
6077 htim->IC_CaptureHalfCpltCallback = pCallback;
6078 break;
6079
6080 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
6081 htim->OC_DelayElapsedCallback = pCallback;
6082 break;
6083
6084 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
6085 htim->PWM_PulseFinishedCallback = pCallback;
6086 break;
6087
6088 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
6089 htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
6090 break;
6091
6092 case HAL_TIM_ERROR_CB_ID :
6093 htim->ErrorCallback = pCallback;
6094 break;
6095
6096 case HAL_TIM_COMMUTATION_CB_ID :
6097 htim->CommutationCallback = pCallback;
6098 break;
6099
6100 case HAL_TIM_COMMUTATION_HALF_CB_ID :
6101 htim->CommutationHalfCpltCallback = pCallback;
6102 break;
6103
6104 case HAL_TIM_BREAK_CB_ID :
6105 htim->BreakCallback = pCallback;
6106 break;
6107
6108 case HAL_TIM_BREAK2_CB_ID :
6109 htim->Break2Callback = pCallback;
6110 break;
6111
6112 default :
6113 /* Return error status */
6114 status = HAL_ERROR;
6115 break;
6116 }
6117 }
6118 else if (htim->State == HAL_TIM_STATE_RESET)
6119 {
6120 switch (CallbackID)
6121 {
6122 case HAL_TIM_BASE_MSPINIT_CB_ID :
6123 htim->Base_MspInitCallback = pCallback;
6124 break;
6125
6126 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6127 htim->Base_MspDeInitCallback = pCallback;
6128 break;
6129
6130 case HAL_TIM_IC_MSPINIT_CB_ID :
6131 htim->IC_MspInitCallback = pCallback;
6132 break;
6133
6134 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6135 htim->IC_MspDeInitCallback = pCallback;
6136 break;
6137
6138 case HAL_TIM_OC_MSPINIT_CB_ID :
6139 htim->OC_MspInitCallback = pCallback;
6140 break;
6141
6142 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6143 htim->OC_MspDeInitCallback = pCallback;
6144 break;
6145
6146 case HAL_TIM_PWM_MSPINIT_CB_ID :
6147 htim->PWM_MspInitCallback = pCallback;
6148 break;
6149
6150 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6151 htim->PWM_MspDeInitCallback = pCallback;
6152 break;
6153
6154 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6155 htim->OnePulse_MspInitCallback = pCallback;
6156 break;
6157
6158 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6159 htim->OnePulse_MspDeInitCallback = pCallback;
6160 break;
6161
6162 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6163 htim->Encoder_MspInitCallback = pCallback;
6164 break;
6165
6166 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6167 htim->Encoder_MspDeInitCallback = pCallback;
6168 break;
6169
6170 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6171 htim->HallSensor_MspInitCallback = pCallback;
6172 break;
6173
6174 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6175 htim->HallSensor_MspDeInitCallback = pCallback;
6176 break;
6177
6178 default :
6179 /* Return error status */
6180 status = HAL_ERROR;
6181 break;
6182 }
6183 }
6184 else
6185 {
6186 /* Return error status */
6187 status = HAL_ERROR;
6188 }
6189
6190 return status;
6191 }
6192
6193 /**
6194 * @brief Unregister a TIM callback
6195 * TIM callback is redirected to the weak predefined callback
6196 * @param htim tim handle
6197 * @param CallbackID ID of the callback to be unregistered
6198 * This parameter can be one of the following values:
6199 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
6200 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
6201 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
6202 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
6203 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
6204 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
6205 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
6206 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
6207 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
6208 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
6209 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
6210 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
6211 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
6212 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
6213 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
6214 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
6215 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
6216 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
6217 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
6218 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
6219 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
6220 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
6221 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
6222 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
6223 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
6224 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
6225 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
6226 * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
6227 * @retval status
6228 */
HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID)6229 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
6230 {
6231 HAL_StatusTypeDef status = HAL_OK;
6232
6233 if (htim->State == HAL_TIM_STATE_READY)
6234 {
6235 switch (CallbackID)
6236 {
6237 case HAL_TIM_BASE_MSPINIT_CB_ID :
6238 /* Legacy weak Base MspInit Callback */
6239 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
6240 break;
6241
6242 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6243 /* Legacy weak Base Msp DeInit Callback */
6244 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
6245 break;
6246
6247 case HAL_TIM_IC_MSPINIT_CB_ID :
6248 /* Legacy weak IC Msp Init Callback */
6249 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
6250 break;
6251
6252 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6253 /* Legacy weak IC Msp DeInit Callback */
6254 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
6255 break;
6256
6257 case HAL_TIM_OC_MSPINIT_CB_ID :
6258 /* Legacy weak OC Msp Init Callback */
6259 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
6260 break;
6261
6262 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6263 /* Legacy weak OC Msp DeInit Callback */
6264 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
6265 break;
6266
6267 case HAL_TIM_PWM_MSPINIT_CB_ID :
6268 /* Legacy weak PWM Msp Init Callback */
6269 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
6270 break;
6271
6272 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6273 /* Legacy weak PWM Msp DeInit Callback */
6274 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
6275 break;
6276
6277 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6278 /* Legacy weak One Pulse Msp Init Callback */
6279 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
6280 break;
6281
6282 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6283 /* Legacy weak One Pulse Msp DeInit Callback */
6284 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
6285 break;
6286
6287 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6288 /* Legacy weak Encoder Msp Init Callback */
6289 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
6290 break;
6291
6292 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6293 /* Legacy weak Encoder Msp DeInit Callback */
6294 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
6295 break;
6296
6297 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6298 /* Legacy weak Hall Sensor Msp Init Callback */
6299 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
6300 break;
6301
6302 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6303 /* Legacy weak Hall Sensor Msp DeInit Callback */
6304 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
6305 break;
6306
6307 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
6308 /* Legacy weak Period Elapsed Callback */
6309 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
6310 break;
6311
6312 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
6313 /* Legacy weak Period Elapsed half complete Callback */
6314 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
6315 break;
6316
6317 case HAL_TIM_TRIGGER_CB_ID :
6318 /* Legacy weak Trigger Callback */
6319 htim->TriggerCallback = HAL_TIM_TriggerCallback;
6320 break;
6321
6322 case HAL_TIM_TRIGGER_HALF_CB_ID :
6323 /* Legacy weak Trigger half complete Callback */
6324 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
6325 break;
6326
6327 case HAL_TIM_IC_CAPTURE_CB_ID :
6328 /* Legacy weak IC Capture Callback */
6329 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
6330 break;
6331
6332 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
6333 /* Legacy weak IC Capture half complete Callback */
6334 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
6335 break;
6336
6337 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
6338 /* Legacy weak OC Delay Elapsed Callback */
6339 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
6340 break;
6341
6342 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
6343 /* Legacy weak PWM Pulse Finished Callback */
6344 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
6345 break;
6346
6347 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
6348 /* Legacy weak PWM Pulse Finished half complete Callback */
6349 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
6350 break;
6351
6352 case HAL_TIM_ERROR_CB_ID :
6353 /* Legacy weak Error Callback */
6354 htim->ErrorCallback = HAL_TIM_ErrorCallback;
6355 break;
6356
6357 case HAL_TIM_COMMUTATION_CB_ID :
6358 /* Legacy weak Commutation Callback */
6359 htim->CommutationCallback = HAL_TIMEx_CommutCallback;
6360 break;
6361
6362 case HAL_TIM_COMMUTATION_HALF_CB_ID :
6363 /* Legacy weak Commutation half complete Callback */
6364 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
6365 break;
6366
6367 case HAL_TIM_BREAK_CB_ID :
6368 /* Legacy weak Break Callback */
6369 htim->BreakCallback = HAL_TIMEx_BreakCallback;
6370 break;
6371
6372 case HAL_TIM_BREAK2_CB_ID :
6373 /* Legacy weak Break2 Callback */
6374 htim->Break2Callback = HAL_TIMEx_Break2Callback;
6375 break;
6376
6377 default :
6378 /* Return error status */
6379 status = HAL_ERROR;
6380 break;
6381 }
6382 }
6383 else if (htim->State == HAL_TIM_STATE_RESET)
6384 {
6385 switch (CallbackID)
6386 {
6387 case HAL_TIM_BASE_MSPINIT_CB_ID :
6388 /* Legacy weak Base MspInit Callback */
6389 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
6390 break;
6391
6392 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6393 /* Legacy weak Base Msp DeInit Callback */
6394 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
6395 break;
6396
6397 case HAL_TIM_IC_MSPINIT_CB_ID :
6398 /* Legacy weak IC Msp Init Callback */
6399 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
6400 break;
6401
6402 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6403 /* Legacy weak IC Msp DeInit Callback */
6404 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
6405 break;
6406
6407 case HAL_TIM_OC_MSPINIT_CB_ID :
6408 /* Legacy weak OC Msp Init Callback */
6409 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
6410 break;
6411
6412 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6413 /* Legacy weak OC Msp DeInit Callback */
6414 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
6415 break;
6416
6417 case HAL_TIM_PWM_MSPINIT_CB_ID :
6418 /* Legacy weak PWM Msp Init Callback */
6419 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
6420 break;
6421
6422 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6423 /* Legacy weak PWM Msp DeInit Callback */
6424 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
6425 break;
6426
6427 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6428 /* Legacy weak One Pulse Msp Init Callback */
6429 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
6430 break;
6431
6432 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6433 /* Legacy weak One Pulse Msp DeInit Callback */
6434 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
6435 break;
6436
6437 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6438 /* Legacy weak Encoder Msp Init Callback */
6439 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
6440 break;
6441
6442 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6443 /* Legacy weak Encoder Msp DeInit Callback */
6444 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
6445 break;
6446
6447 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6448 /* Legacy weak Hall Sensor Msp Init Callback */
6449 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
6450 break;
6451
6452 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6453 /* Legacy weak Hall Sensor Msp DeInit Callback */
6454 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
6455 break;
6456
6457 default :
6458 /* Return error status */
6459 status = HAL_ERROR;
6460 break;
6461 }
6462 }
6463 else
6464 {
6465 /* Return error status */
6466 status = HAL_ERROR;
6467 }
6468
6469 return status;
6470 }
6471 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6472
6473 /**
6474 * @}
6475 */
6476
6477 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
6478 * @brief TIM Peripheral State functions
6479 *
6480 @verbatim
6481 ==============================================================================
6482 ##### Peripheral State functions #####
6483 ==============================================================================
6484 [..]
6485 This subsection permits to get in run-time the status of the peripheral
6486 and the data flow.
6487
6488 @endverbatim
6489 * @{
6490 */
6491
6492 /**
6493 * @brief Return the TIM Base handle state.
6494 * @param htim TIM Base handle
6495 * @retval HAL state
6496 */
HAL_TIM_Base_GetState(const TIM_HandleTypeDef * htim)6497 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim)
6498 {
6499 return htim->State;
6500 }
6501
6502 /**
6503 * @brief Return the TIM OC handle state.
6504 * @param htim TIM Output Compare handle
6505 * @retval HAL state
6506 */
HAL_TIM_OC_GetState(const TIM_HandleTypeDef * htim)6507 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim)
6508 {
6509 return htim->State;
6510 }
6511
6512 /**
6513 * @brief Return the TIM PWM handle state.
6514 * @param htim TIM handle
6515 * @retval HAL state
6516 */
HAL_TIM_PWM_GetState(const TIM_HandleTypeDef * htim)6517 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim)
6518 {
6519 return htim->State;
6520 }
6521
6522 /**
6523 * @brief Return the TIM Input Capture handle state.
6524 * @param htim TIM IC handle
6525 * @retval HAL state
6526 */
HAL_TIM_IC_GetState(const TIM_HandleTypeDef * htim)6527 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim)
6528 {
6529 return htim->State;
6530 }
6531
6532 /**
6533 * @brief Return the TIM One Pulse Mode handle state.
6534 * @param htim TIM OPM handle
6535 * @retval HAL state
6536 */
HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef * htim)6537 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim)
6538 {
6539 return htim->State;
6540 }
6541
6542 /**
6543 * @brief Return the TIM Encoder Mode handle state.
6544 * @param htim TIM Encoder Interface handle
6545 * @retval HAL state
6546 */
HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef * htim)6547 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim)
6548 {
6549 return htim->State;
6550 }
6551
6552 /**
6553 * @brief Return the TIM Encoder Mode handle state.
6554 * @param htim TIM handle
6555 * @retval Active channel
6556 */
HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef * htim)6557 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim)
6558 {
6559 return htim->Channel;
6560 }
6561
6562 /**
6563 * @brief Return actual state of the TIM channel.
6564 * @param htim TIM handle
6565 * @param Channel TIM Channel
6566 * This parameter can be one of the following values:
6567 * @arg TIM_CHANNEL_1: TIM Channel 1
6568 * @arg TIM_CHANNEL_2: TIM Channel 2
6569 * @arg TIM_CHANNEL_3: TIM Channel 3
6570 * @arg TIM_CHANNEL_4: TIM Channel 4
6571 * @arg TIM_CHANNEL_5: TIM Channel 5
6572 * @arg TIM_CHANNEL_6: TIM Channel 6
6573 * @retval TIM Channel state
6574 */
HAL_TIM_GetChannelState(const TIM_HandleTypeDef * htim,uint32_t Channel)6575 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel)
6576 {
6577 HAL_TIM_ChannelStateTypeDef channel_state;
6578
6579 /* Check the parameters */
6580 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
6581
6582 channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
6583
6584 return channel_state;
6585 }
6586
6587 /**
6588 * @brief Return actual state of a DMA burst operation.
6589 * @param htim TIM handle
6590 * @retval DMA burst state
6591 */
HAL_TIM_DMABurstState(const TIM_HandleTypeDef * htim)6592 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim)
6593 {
6594 /* Check the parameters */
6595 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
6596
6597 return htim->DMABurstState;
6598 }
6599
6600 /**
6601 * @}
6602 */
6603
6604 /**
6605 * @}
6606 */
6607
6608 /** @defgroup TIM_Private_Functions TIM Private Functions
6609 * @{
6610 */
6611
6612 /**
6613 * @brief TIM DMA error callback
6614 * @param hdma pointer to DMA handle.
6615 * @retval None
6616 */
TIM_DMAError(DMA_HandleTypeDef * hdma)6617 void TIM_DMAError(DMA_HandleTypeDef *hdma)
6618 {
6619 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6620
6621 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6622 {
6623 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6624 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6625 }
6626 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6627 {
6628 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6629 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6630 }
6631 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6632 {
6633 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6634 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6635 }
6636 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6637 {
6638 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6639 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6640 }
6641 else
6642 {
6643 htim->State = HAL_TIM_STATE_READY;
6644 }
6645
6646 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6647 htim->ErrorCallback(htim);
6648 #else
6649 HAL_TIM_ErrorCallback(htim);
6650 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6651
6652 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6653 }
6654
6655 /**
6656 * @brief TIM DMA Delay Pulse complete callback.
6657 * @param hdma pointer to DMA handle.
6658 * @retval None
6659 */
TIM_DMADelayPulseCplt(DMA_HandleTypeDef * hdma)6660 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
6661 {
6662 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6663
6664 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6665 {
6666 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6667
6668 if (hdma->Init.Mode == DMA_NORMAL)
6669 {
6670 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6671 }
6672 }
6673 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6674 {
6675 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6676
6677 if (hdma->Init.Mode == DMA_NORMAL)
6678 {
6679 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6680 }
6681 }
6682 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6683 {
6684 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6685
6686 if (hdma->Init.Mode == DMA_NORMAL)
6687 {
6688 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6689 }
6690 }
6691 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6692 {
6693 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6694
6695 if (hdma->Init.Mode == DMA_NORMAL)
6696 {
6697 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6698 }
6699 }
6700 else
6701 {
6702 /* nothing to do */
6703 }
6704
6705 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6706 htim->PWM_PulseFinishedCallback(htim);
6707 #else
6708 HAL_TIM_PWM_PulseFinishedCallback(htim);
6709 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6710
6711 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6712 }
6713
6714 /**
6715 * @brief TIM DMA Delay Pulse half complete callback.
6716 * @param hdma pointer to DMA handle.
6717 * @retval None
6718 */
TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef * hdma)6719 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
6720 {
6721 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6722
6723 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6724 {
6725 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6726 }
6727 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6728 {
6729 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6730 }
6731 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6732 {
6733 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6734 }
6735 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6736 {
6737 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6738 }
6739 else
6740 {
6741 /* nothing to do */
6742 }
6743
6744 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6745 htim->PWM_PulseFinishedHalfCpltCallback(htim);
6746 #else
6747 HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
6748 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6749
6750 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6751 }
6752
6753 /**
6754 * @brief TIM DMA Capture complete callback.
6755 * @param hdma pointer to DMA handle.
6756 * @retval None
6757 */
TIM_DMACaptureCplt(DMA_HandleTypeDef * hdma)6758 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
6759 {
6760 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6761
6762 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6763 {
6764 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6765
6766 if (hdma->Init.Mode == DMA_NORMAL)
6767 {
6768 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6769 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6770 }
6771 }
6772 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6773 {
6774 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6775
6776 if (hdma->Init.Mode == DMA_NORMAL)
6777 {
6778 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6779 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6780 }
6781 }
6782 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6783 {
6784 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6785
6786 if (hdma->Init.Mode == DMA_NORMAL)
6787 {
6788 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6789 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6790 }
6791 }
6792 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6793 {
6794 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6795
6796 if (hdma->Init.Mode == DMA_NORMAL)
6797 {
6798 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6799 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6800 }
6801 }
6802 else
6803 {
6804 /* nothing to do */
6805 }
6806
6807 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6808 htim->IC_CaptureCallback(htim);
6809 #else
6810 HAL_TIM_IC_CaptureCallback(htim);
6811 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6812
6813 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6814 }
6815
6816 /**
6817 * @brief TIM DMA Capture half complete callback.
6818 * @param hdma pointer to DMA handle.
6819 * @retval None
6820 */
TIM_DMACaptureHalfCplt(DMA_HandleTypeDef * hdma)6821 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
6822 {
6823 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6824
6825 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6826 {
6827 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6828 }
6829 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6830 {
6831 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6832 }
6833 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6834 {
6835 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6836 }
6837 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6838 {
6839 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6840 }
6841 else
6842 {
6843 /* nothing to do */
6844 }
6845
6846 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6847 htim->IC_CaptureHalfCpltCallback(htim);
6848 #else
6849 HAL_TIM_IC_CaptureHalfCpltCallback(htim);
6850 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6851
6852 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6853 }
6854
6855 /**
6856 * @brief TIM DMA Period Elapse complete callback.
6857 * @param hdma pointer to DMA handle.
6858 * @retval None
6859 */
TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef * hdma)6860 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
6861 {
6862 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6863
6864 if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
6865 {
6866 htim->State = HAL_TIM_STATE_READY;
6867 }
6868
6869 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6870 htim->PeriodElapsedCallback(htim);
6871 #else
6872 HAL_TIM_PeriodElapsedCallback(htim);
6873 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6874 }
6875
6876 /**
6877 * @brief TIM DMA Period Elapse half complete callback.
6878 * @param hdma pointer to DMA handle.
6879 * @retval None
6880 */
TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef * hdma)6881 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
6882 {
6883 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6884
6885 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6886 htim->PeriodElapsedHalfCpltCallback(htim);
6887 #else
6888 HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
6889 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6890 }
6891
6892 /**
6893 * @brief TIM DMA Trigger callback.
6894 * @param hdma pointer to DMA handle.
6895 * @retval None
6896 */
TIM_DMATriggerCplt(DMA_HandleTypeDef * hdma)6897 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
6898 {
6899 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6900
6901 if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
6902 {
6903 htim->State = HAL_TIM_STATE_READY;
6904 }
6905
6906 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6907 htim->TriggerCallback(htim);
6908 #else
6909 HAL_TIM_TriggerCallback(htim);
6910 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6911 }
6912
6913 /**
6914 * @brief TIM DMA Trigger half complete callback.
6915 * @param hdma pointer to DMA handle.
6916 * @retval None
6917 */
TIM_DMATriggerHalfCplt(DMA_HandleTypeDef * hdma)6918 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
6919 {
6920 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6921
6922 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6923 htim->TriggerHalfCpltCallback(htim);
6924 #else
6925 HAL_TIM_TriggerHalfCpltCallback(htim);
6926 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6927 }
6928
6929 /**
6930 * @brief Time Base configuration
6931 * @param TIMx TIM peripheral
6932 * @param Structure TIM Base configuration structure
6933 * @retval None
6934 */
TIM_Base_SetConfig(TIM_TypeDef * TIMx,const TIM_Base_InitTypeDef * Structure)6935 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
6936 {
6937 uint32_t tmpcr1;
6938 tmpcr1 = TIMx->CR1;
6939
6940 /* Set TIM Time Base Unit parameters ---------------------------------------*/
6941 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
6942 {
6943 /* Select the Counter Mode */
6944 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
6945 tmpcr1 |= Structure->CounterMode;
6946 }
6947
6948 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
6949 {
6950 /* Set the clock division */
6951 tmpcr1 &= ~TIM_CR1_CKD;
6952 tmpcr1 |= (uint32_t)Structure->ClockDivision;
6953 }
6954
6955 /* Set the auto-reload preload */
6956 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
6957
6958 TIMx->CR1 = tmpcr1;
6959
6960 /* Set the Autoreload value */
6961 TIMx->ARR = (uint32_t)Structure->Period ;
6962
6963 /* Set the Prescaler value */
6964 TIMx->PSC = Structure->Prescaler;
6965
6966 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
6967 {
6968 /* Set the Repetition Counter value */
6969 TIMx->RCR = Structure->RepetitionCounter;
6970 }
6971
6972 /* Generate an update event to reload the Prescaler
6973 and the repetition counter (only for advanced timer) value immediately */
6974 TIMx->EGR = TIM_EGR_UG;
6975 }
6976
6977 /**
6978 * @brief Timer Output Compare 1 configuration
6979 * @param TIMx to select the TIM peripheral
6980 * @param OC_Config The output configuration structure
6981 * @retval None
6982 */
TIM_OC1_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)6983 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
6984 {
6985 uint32_t tmpccmrx;
6986 uint32_t tmpccer;
6987 uint32_t tmpcr2;
6988
6989 /* Get the TIMx CCER register value */
6990 tmpccer = TIMx->CCER;
6991
6992 /* Disable the Channel 1: Reset the CC1E Bit */
6993 TIMx->CCER &= ~TIM_CCER_CC1E;
6994
6995 /* Get the TIMx CR2 register value */
6996 tmpcr2 = TIMx->CR2;
6997
6998 /* Get the TIMx CCMR1 register value */
6999 tmpccmrx = TIMx->CCMR1;
7000
7001 /* Reset the Output Compare Mode Bits */
7002 tmpccmrx &= ~TIM_CCMR1_OC1M;
7003 tmpccmrx &= ~TIM_CCMR1_CC1S;
7004 /* Select the Output Compare Mode */
7005 tmpccmrx |= OC_Config->OCMode;
7006
7007 /* Reset the Output Polarity level */
7008 tmpccer &= ~TIM_CCER_CC1P;
7009 /* Set the Output Compare Polarity */
7010 tmpccer |= OC_Config->OCPolarity;
7011
7012 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
7013 {
7014 /* Check parameters */
7015 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7016
7017 /* Reset the Output N Polarity level */
7018 tmpccer &= ~TIM_CCER_CC1NP;
7019 /* Set the Output N Polarity */
7020 tmpccer |= OC_Config->OCNPolarity;
7021 /* Reset the Output N State */
7022 tmpccer &= ~TIM_CCER_CC1NE;
7023 }
7024
7025 if (IS_TIM_BREAK_INSTANCE(TIMx))
7026 {
7027 /* Check parameters */
7028 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7029 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7030
7031 /* Reset the Output Compare and Output Compare N IDLE State */
7032 tmpcr2 &= ~TIM_CR2_OIS1;
7033 tmpcr2 &= ~TIM_CR2_OIS1N;
7034 /* Set the Output Idle state */
7035 tmpcr2 |= OC_Config->OCIdleState;
7036 /* Set the Output N Idle state */
7037 tmpcr2 |= OC_Config->OCNIdleState;
7038 }
7039
7040 /* Write to TIMx CR2 */
7041 TIMx->CR2 = tmpcr2;
7042
7043 /* Write to TIMx CCMR1 */
7044 TIMx->CCMR1 = tmpccmrx;
7045
7046 /* Set the Capture Compare Register value */
7047 TIMx->CCR1 = OC_Config->Pulse;
7048
7049 /* Write to TIMx CCER */
7050 TIMx->CCER = tmpccer;
7051 }
7052
7053 /**
7054 * @brief Timer Output Compare 2 configuration
7055 * @param TIMx to select the TIM peripheral
7056 * @param OC_Config The output configuration structure
7057 * @retval None
7058 */
TIM_OC2_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7059 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7060 {
7061 uint32_t tmpccmrx;
7062 uint32_t tmpccer;
7063 uint32_t tmpcr2;
7064
7065 /* Get the TIMx CCER register value */
7066 tmpccer = TIMx->CCER;
7067
7068 /* Disable the Channel 2: Reset the CC2E Bit */
7069 TIMx->CCER &= ~TIM_CCER_CC2E;
7070
7071 /* Get the TIMx CR2 register value */
7072 tmpcr2 = TIMx->CR2;
7073
7074 /* Get the TIMx CCMR1 register value */
7075 tmpccmrx = TIMx->CCMR1;
7076
7077 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7078 tmpccmrx &= ~TIM_CCMR1_OC2M;
7079 tmpccmrx &= ~TIM_CCMR1_CC2S;
7080
7081 /* Select the Output Compare Mode */
7082 tmpccmrx |= (OC_Config->OCMode << 8U);
7083
7084 /* Reset the Output Polarity level */
7085 tmpccer &= ~TIM_CCER_CC2P;
7086 /* Set the Output Compare Polarity */
7087 tmpccer |= (OC_Config->OCPolarity << 4U);
7088
7089 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
7090 {
7091 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7092
7093 /* Reset the Output N Polarity level */
7094 tmpccer &= ~TIM_CCER_CC2NP;
7095 /* Set the Output N Polarity */
7096 tmpccer |= (OC_Config->OCNPolarity << 4U);
7097 /* Reset the Output N State */
7098 tmpccer &= ~TIM_CCER_CC2NE;
7099
7100 }
7101
7102 if (IS_TIM_BREAK_INSTANCE(TIMx))
7103 {
7104 /* Check parameters */
7105 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7106 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7107
7108 /* Reset the Output Compare and Output Compare N IDLE State */
7109 tmpcr2 &= ~TIM_CR2_OIS2;
7110 tmpcr2 &= ~TIM_CR2_OIS2N;
7111 /* Set the Output Idle state */
7112 tmpcr2 |= (OC_Config->OCIdleState << 2U);
7113 /* Set the Output N Idle state */
7114 tmpcr2 |= (OC_Config->OCNIdleState << 2U);
7115 }
7116
7117 /* Write to TIMx CR2 */
7118 TIMx->CR2 = tmpcr2;
7119
7120 /* Write to TIMx CCMR1 */
7121 TIMx->CCMR1 = tmpccmrx;
7122
7123 /* Set the Capture Compare Register value */
7124 TIMx->CCR2 = OC_Config->Pulse;
7125
7126 /* Write to TIMx CCER */
7127 TIMx->CCER = tmpccer;
7128 }
7129
7130 /**
7131 * @brief Timer Output Compare 3 configuration
7132 * @param TIMx to select the TIM peripheral
7133 * @param OC_Config The output configuration structure
7134 * @retval None
7135 */
TIM_OC3_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7136 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7137 {
7138 uint32_t tmpccmrx;
7139 uint32_t tmpccer;
7140 uint32_t tmpcr2;
7141
7142 /* Get the TIMx CCER register value */
7143 tmpccer = TIMx->CCER;
7144
7145 /* Disable the Channel 3: Reset the CC2E Bit */
7146 TIMx->CCER &= ~TIM_CCER_CC3E;
7147
7148 /* Get the TIMx CR2 register value */
7149 tmpcr2 = TIMx->CR2;
7150
7151 /* Get the TIMx CCMR2 register value */
7152 tmpccmrx = TIMx->CCMR2;
7153
7154 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7155 tmpccmrx &= ~TIM_CCMR2_OC3M;
7156 tmpccmrx &= ~TIM_CCMR2_CC3S;
7157 /* Select the Output Compare Mode */
7158 tmpccmrx |= OC_Config->OCMode;
7159
7160 /* Reset the Output Polarity level */
7161 tmpccer &= ~TIM_CCER_CC3P;
7162 /* Set the Output Compare Polarity */
7163 tmpccer |= (OC_Config->OCPolarity << 8U);
7164
7165 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
7166 {
7167 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7168
7169 /* Reset the Output N Polarity level */
7170 tmpccer &= ~TIM_CCER_CC3NP;
7171 /* Set the Output N Polarity */
7172 tmpccer |= (OC_Config->OCNPolarity << 8U);
7173 /* Reset the Output N State */
7174 tmpccer &= ~TIM_CCER_CC3NE;
7175 }
7176
7177 if (IS_TIM_BREAK_INSTANCE(TIMx))
7178 {
7179 /* Check parameters */
7180 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7181 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7182
7183 /* Reset the Output Compare and Output Compare N IDLE State */
7184 tmpcr2 &= ~TIM_CR2_OIS3;
7185 tmpcr2 &= ~TIM_CR2_OIS3N;
7186 /* Set the Output Idle state */
7187 tmpcr2 |= (OC_Config->OCIdleState << 4U);
7188 /* Set the Output N Idle state */
7189 tmpcr2 |= (OC_Config->OCNIdleState << 4U);
7190 }
7191
7192 /* Write to TIMx CR2 */
7193 TIMx->CR2 = tmpcr2;
7194
7195 /* Write to TIMx CCMR2 */
7196 TIMx->CCMR2 = tmpccmrx;
7197
7198 /* Set the Capture Compare Register value */
7199 TIMx->CCR3 = OC_Config->Pulse;
7200
7201 /* Write to TIMx CCER */
7202 TIMx->CCER = tmpccer;
7203 }
7204
7205 /**
7206 * @brief Timer Output Compare 4 configuration
7207 * @param TIMx to select the TIM peripheral
7208 * @param OC_Config The output configuration structure
7209 * @retval None
7210 */
TIM_OC4_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7211 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7212 {
7213 uint32_t tmpccmrx;
7214 uint32_t tmpccer;
7215 uint32_t tmpcr2;
7216
7217 /* Get the TIMx CCER register value */
7218 tmpccer = TIMx->CCER;
7219
7220 /* Disable the Channel 4: Reset the CC4E Bit */
7221 TIMx->CCER &= ~TIM_CCER_CC4E;
7222
7223 /* Get the TIMx CR2 register value */
7224 tmpcr2 = TIMx->CR2;
7225
7226 /* Get the TIMx CCMR2 register value */
7227 tmpccmrx = TIMx->CCMR2;
7228
7229 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7230 tmpccmrx &= ~TIM_CCMR2_OC4M;
7231 tmpccmrx &= ~TIM_CCMR2_CC4S;
7232
7233 /* Select the Output Compare Mode */
7234 tmpccmrx |= (OC_Config->OCMode << 8U);
7235
7236 /* Reset the Output Polarity level */
7237 tmpccer &= ~TIM_CCER_CC4P;
7238 /* Set the Output Compare Polarity */
7239 tmpccer |= (OC_Config->OCPolarity << 12U);
7240
7241 if (IS_TIM_BREAK_INSTANCE(TIMx))
7242 {
7243 /* Check parameters */
7244 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7245
7246 /* Reset the Output Compare IDLE State */
7247 tmpcr2 &= ~TIM_CR2_OIS4;
7248
7249 /* Set the Output Idle state */
7250 tmpcr2 |= (OC_Config->OCIdleState << 6U);
7251 }
7252
7253 /* Write to TIMx CR2 */
7254 TIMx->CR2 = tmpcr2;
7255
7256 /* Write to TIMx CCMR2 */
7257 TIMx->CCMR2 = tmpccmrx;
7258
7259 /* Set the Capture Compare Register value */
7260 TIMx->CCR4 = OC_Config->Pulse;
7261
7262 /* Write to TIMx CCER */
7263 TIMx->CCER = tmpccer;
7264 }
7265
7266 /**
7267 * @brief Timer Output Compare 5 configuration
7268 * @param TIMx to select the TIM peripheral
7269 * @param OC_Config The output configuration structure
7270 * @retval None
7271 */
TIM_OC5_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7272 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
7273 const TIM_OC_InitTypeDef *OC_Config)
7274 {
7275 uint32_t tmpccmrx;
7276 uint32_t tmpccer;
7277 uint32_t tmpcr2;
7278
7279 /* Get the TIMx CCER register value */
7280 tmpccer = TIMx->CCER;
7281
7282 /* Disable the output: Reset the CCxE Bit */
7283 TIMx->CCER &= ~TIM_CCER_CC5E;
7284
7285 /* Get the TIMx CR2 register value */
7286 tmpcr2 = TIMx->CR2;
7287 /* Get the TIMx CCMR1 register value */
7288 tmpccmrx = TIMx->CCMR3;
7289
7290 /* Reset the Output Compare Mode Bits */
7291 tmpccmrx &= ~(TIM_CCMR3_OC5M);
7292 /* Select the Output Compare Mode */
7293 tmpccmrx |= OC_Config->OCMode;
7294
7295 /* Reset the Output Polarity level */
7296 tmpccer &= ~TIM_CCER_CC5P;
7297 /* Set the Output Compare Polarity */
7298 tmpccer |= (OC_Config->OCPolarity << 16U);
7299
7300 if (IS_TIM_BREAK_INSTANCE(TIMx))
7301 {
7302 /* Reset the Output Compare IDLE State */
7303 tmpcr2 &= ~TIM_CR2_OIS5;
7304 /* Set the Output Idle state */
7305 tmpcr2 |= (OC_Config->OCIdleState << 8U);
7306 }
7307 /* Write to TIMx CR2 */
7308 TIMx->CR2 = tmpcr2;
7309
7310 /* Write to TIMx CCMR3 */
7311 TIMx->CCMR3 = tmpccmrx;
7312
7313 /* Set the Capture Compare Register value */
7314 TIMx->CCR5 = OC_Config->Pulse;
7315
7316 /* Write to TIMx CCER */
7317 TIMx->CCER = tmpccer;
7318 }
7319
7320 /**
7321 * @brief Timer Output Compare 6 configuration
7322 * @param TIMx to select the TIM peripheral
7323 * @param OC_Config The output configuration structure
7324 * @retval None
7325 */
TIM_OC6_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7326 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
7327 const TIM_OC_InitTypeDef *OC_Config)
7328 {
7329 uint32_t tmpccmrx;
7330 uint32_t tmpccer;
7331 uint32_t tmpcr2;
7332
7333 /* Get the TIMx CCER register value */
7334 tmpccer = TIMx->CCER;
7335
7336 /* Disable the output: Reset the CCxE Bit */
7337 TIMx->CCER &= ~TIM_CCER_CC6E;
7338
7339 /* Get the TIMx CR2 register value */
7340 tmpcr2 = TIMx->CR2;
7341 /* Get the TIMx CCMR1 register value */
7342 tmpccmrx = TIMx->CCMR3;
7343
7344 /* Reset the Output Compare Mode Bits */
7345 tmpccmrx &= ~(TIM_CCMR3_OC6M);
7346 /* Select the Output Compare Mode */
7347 tmpccmrx |= (OC_Config->OCMode << 8U);
7348
7349 /* Reset the Output Polarity level */
7350 tmpccer &= (uint32_t)~TIM_CCER_CC6P;
7351 /* Set the Output Compare Polarity */
7352 tmpccer |= (OC_Config->OCPolarity << 20U);
7353
7354 if (IS_TIM_BREAK_INSTANCE(TIMx))
7355 {
7356 /* Reset the Output Compare IDLE State */
7357 tmpcr2 &= ~TIM_CR2_OIS6;
7358 /* Set the Output Idle state */
7359 tmpcr2 |= (OC_Config->OCIdleState << 10U);
7360 }
7361
7362 /* Write to TIMx CR2 */
7363 TIMx->CR2 = tmpcr2;
7364
7365 /* Write to TIMx CCMR3 */
7366 TIMx->CCMR3 = tmpccmrx;
7367
7368 /* Set the Capture Compare Register value */
7369 TIMx->CCR6 = OC_Config->Pulse;
7370
7371 /* Write to TIMx CCER */
7372 TIMx->CCER = tmpccer;
7373 }
7374
7375 /**
7376 * @brief Slave Timer configuration function
7377 * @param htim TIM handle
7378 * @param sSlaveConfig Slave timer configuration
7379 * @retval None
7380 */
TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)7381 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
7382 const TIM_SlaveConfigTypeDef *sSlaveConfig)
7383 {
7384 HAL_StatusTypeDef status = HAL_OK;
7385 uint32_t tmpsmcr;
7386 uint32_t tmpccmr1;
7387 uint32_t tmpccer;
7388
7389 /* Get the TIMx SMCR register value */
7390 tmpsmcr = htim->Instance->SMCR;
7391
7392 /* Reset the Trigger Selection Bits */
7393 tmpsmcr &= ~TIM_SMCR_TS;
7394 /* Set the Input Trigger source */
7395 tmpsmcr |= sSlaveConfig->InputTrigger;
7396
7397 /* Reset the slave mode Bits */
7398 tmpsmcr &= ~TIM_SMCR_SMS;
7399 /* Set the slave mode */
7400 tmpsmcr |= sSlaveConfig->SlaveMode;
7401
7402 /* Write to TIMx SMCR */
7403 htim->Instance->SMCR = tmpsmcr;
7404
7405 /* Configure the trigger prescaler, filter, and polarity */
7406 switch (sSlaveConfig->InputTrigger)
7407 {
7408 case TIM_TS_ETRF:
7409 {
7410 /* Check the parameters */
7411 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
7412 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
7413 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7414 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7415 /* Configure the ETR Trigger source */
7416 TIM_ETR_SetConfig(htim->Instance,
7417 sSlaveConfig->TriggerPrescaler,
7418 sSlaveConfig->TriggerPolarity,
7419 sSlaveConfig->TriggerFilter);
7420 break;
7421 }
7422
7423 case TIM_TS_TI1F_ED:
7424 {
7425 /* Check the parameters */
7426 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7427 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7428
7429 if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
7430 {
7431 return HAL_ERROR;
7432 }
7433
7434 /* Disable the Channel 1: Reset the CC1E Bit */
7435 tmpccer = htim->Instance->CCER;
7436 htim->Instance->CCER &= ~TIM_CCER_CC1E;
7437 tmpccmr1 = htim->Instance->CCMR1;
7438
7439 /* Set the filter */
7440 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7441 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
7442
7443 /* Write to TIMx CCMR1 and CCER registers */
7444 htim->Instance->CCMR1 = tmpccmr1;
7445 htim->Instance->CCER = tmpccer;
7446 break;
7447 }
7448
7449 case TIM_TS_TI1FP1:
7450 {
7451 /* Check the parameters */
7452 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7453 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7454 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7455
7456 /* Configure TI1 Filter and Polarity */
7457 TIM_TI1_ConfigInputStage(htim->Instance,
7458 sSlaveConfig->TriggerPolarity,
7459 sSlaveConfig->TriggerFilter);
7460 break;
7461 }
7462
7463 case TIM_TS_TI2FP2:
7464 {
7465 /* Check the parameters */
7466 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
7467 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7468 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7469
7470 /* Configure TI2 Filter and Polarity */
7471 TIM_TI2_ConfigInputStage(htim->Instance,
7472 sSlaveConfig->TriggerPolarity,
7473 sSlaveConfig->TriggerFilter);
7474 break;
7475 }
7476
7477 case TIM_TS_ITR0:
7478 case TIM_TS_ITR1:
7479 case TIM_TS_ITR2:
7480 case TIM_TS_ITR3:
7481 {
7482 /* Check the parameter */
7483 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
7484 break;
7485 }
7486
7487 default:
7488 status = HAL_ERROR;
7489 break;
7490 }
7491
7492 return status;
7493 }
7494
7495 /**
7496 * @brief Configure the TI1 as Input.
7497 * @param TIMx to select the TIM peripheral.
7498 * @param TIM_ICPolarity The Input Polarity.
7499 * This parameter can be one of the following values:
7500 * @arg TIM_ICPOLARITY_RISING
7501 * @arg TIM_ICPOLARITY_FALLING
7502 * @arg TIM_ICPOLARITY_BOTHEDGE
7503 * @param TIM_ICSelection specifies the input to be used.
7504 * This parameter can be one of the following values:
7505 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
7506 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
7507 * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
7508 * @param TIM_ICFilter Specifies the Input Capture Filter.
7509 * This parameter must be a value between 0x00 and 0x0F.
7510 * @retval None
7511 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
7512 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
7513 * protected against un-initialized filter and polarity values.
7514 */
TIM_TI1_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7515 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7516 uint32_t TIM_ICFilter)
7517 {
7518 uint32_t tmpccmr1;
7519 uint32_t tmpccer;
7520
7521 /* Disable the Channel 1: Reset the CC1E Bit */
7522 tmpccer = TIMx->CCER;
7523 TIMx->CCER &= ~TIM_CCER_CC1E;
7524 tmpccmr1 = TIMx->CCMR1;
7525
7526 /* Select the Input */
7527 if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
7528 {
7529 tmpccmr1 &= ~TIM_CCMR1_CC1S;
7530 tmpccmr1 |= TIM_ICSelection;
7531 }
7532 else
7533 {
7534 tmpccmr1 |= TIM_CCMR1_CC1S_0;
7535 }
7536
7537 /* Set the filter */
7538 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7539 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
7540
7541 /* Select the Polarity and set the CC1E Bit */
7542 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7543 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
7544
7545 /* Write to TIMx CCMR1 and CCER registers */
7546 TIMx->CCMR1 = tmpccmr1;
7547 TIMx->CCER = tmpccer;
7548 }
7549
7550 /**
7551 * @brief Configure the Polarity and Filter for TI1.
7552 * @param TIMx to select the TIM peripheral.
7553 * @param TIM_ICPolarity The Input Polarity.
7554 * This parameter can be one of the following values:
7555 * @arg TIM_ICPOLARITY_RISING
7556 * @arg TIM_ICPOLARITY_FALLING
7557 * @arg TIM_ICPOLARITY_BOTHEDGE
7558 * @param TIM_ICFilter Specifies the Input Capture Filter.
7559 * This parameter must be a value between 0x00 and 0x0F.
7560 * @retval None
7561 */
TIM_TI1_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)7562 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7563 {
7564 uint32_t tmpccmr1;
7565 uint32_t tmpccer;
7566
7567 /* Disable the Channel 1: Reset the CC1E Bit */
7568 tmpccer = TIMx->CCER;
7569 TIMx->CCER &= ~TIM_CCER_CC1E;
7570 tmpccmr1 = TIMx->CCMR1;
7571
7572 /* Set the filter */
7573 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7574 tmpccmr1 |= (TIM_ICFilter << 4U);
7575
7576 /* Select the Polarity and set the CC1E Bit */
7577 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7578 tmpccer |= TIM_ICPolarity;
7579
7580 /* Write to TIMx CCMR1 and CCER registers */
7581 TIMx->CCMR1 = tmpccmr1;
7582 TIMx->CCER = tmpccer;
7583 }
7584
7585 /**
7586 * @brief Configure the TI2 as Input.
7587 * @param TIMx to select the TIM peripheral
7588 * @param TIM_ICPolarity The Input Polarity.
7589 * This parameter can be one of the following values:
7590 * @arg TIM_ICPOLARITY_RISING
7591 * @arg TIM_ICPOLARITY_FALLING
7592 * @arg TIM_ICPOLARITY_BOTHEDGE
7593 * @param TIM_ICSelection specifies the input to be used.
7594 * This parameter can be one of the following values:
7595 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
7596 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
7597 * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
7598 * @param TIM_ICFilter Specifies the Input Capture Filter.
7599 * This parameter must be a value between 0x00 and 0x0F.
7600 * @retval None
7601 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
7602 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
7603 * protected against un-initialized filter and polarity values.
7604 */
TIM_TI2_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7605 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7606 uint32_t TIM_ICFilter)
7607 {
7608 uint32_t tmpccmr1;
7609 uint32_t tmpccer;
7610
7611 /* Disable the Channel 2: Reset the CC2E Bit */
7612 tmpccer = TIMx->CCER;
7613 TIMx->CCER &= ~TIM_CCER_CC2E;
7614 tmpccmr1 = TIMx->CCMR1;
7615
7616 /* Select the Input */
7617 tmpccmr1 &= ~TIM_CCMR1_CC2S;
7618 tmpccmr1 |= (TIM_ICSelection << 8U);
7619
7620 /* Set the filter */
7621 tmpccmr1 &= ~TIM_CCMR1_IC2F;
7622 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
7623
7624 /* Select the Polarity and set the CC2E Bit */
7625 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7626 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
7627
7628 /* Write to TIMx CCMR1 and CCER registers */
7629 TIMx->CCMR1 = tmpccmr1 ;
7630 TIMx->CCER = tmpccer;
7631 }
7632
7633 /**
7634 * @brief Configure the Polarity and Filter for TI2.
7635 * @param TIMx to select the TIM peripheral.
7636 * @param TIM_ICPolarity The Input Polarity.
7637 * This parameter can be one of the following values:
7638 * @arg TIM_ICPOLARITY_RISING
7639 * @arg TIM_ICPOLARITY_FALLING
7640 * @arg TIM_ICPOLARITY_BOTHEDGE
7641 * @param TIM_ICFilter Specifies the Input Capture Filter.
7642 * This parameter must be a value between 0x00 and 0x0F.
7643 * @retval None
7644 */
TIM_TI2_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)7645 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7646 {
7647 uint32_t tmpccmr1;
7648 uint32_t tmpccer;
7649
7650 /* Disable the Channel 2: Reset the CC2E Bit */
7651 tmpccer = TIMx->CCER;
7652 TIMx->CCER &= ~TIM_CCER_CC2E;
7653 tmpccmr1 = TIMx->CCMR1;
7654
7655 /* Set the filter */
7656 tmpccmr1 &= ~TIM_CCMR1_IC2F;
7657 tmpccmr1 |= (TIM_ICFilter << 12U);
7658
7659 /* Select the Polarity and set the CC2E Bit */
7660 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7661 tmpccer |= (TIM_ICPolarity << 4U);
7662
7663 /* Write to TIMx CCMR1 and CCER registers */
7664 TIMx->CCMR1 = tmpccmr1 ;
7665 TIMx->CCER = tmpccer;
7666 }
7667
7668 /**
7669 * @brief Configure the TI3 as Input.
7670 * @param TIMx to select the TIM peripheral
7671 * @param TIM_ICPolarity The Input Polarity.
7672 * This parameter can be one of the following values:
7673 * @arg TIM_ICPOLARITY_RISING
7674 * @arg TIM_ICPOLARITY_FALLING
7675 * @arg TIM_ICPOLARITY_BOTHEDGE
7676 * @param TIM_ICSelection specifies the input to be used.
7677 * This parameter can be one of the following values:
7678 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
7679 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
7680 * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
7681 * @param TIM_ICFilter Specifies the Input Capture Filter.
7682 * This parameter must be a value between 0x00 and 0x0F.
7683 * @retval None
7684 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
7685 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
7686 * protected against un-initialized filter and polarity values.
7687 */
TIM_TI3_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7688 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7689 uint32_t TIM_ICFilter)
7690 {
7691 uint32_t tmpccmr2;
7692 uint32_t tmpccer;
7693
7694 /* Disable the Channel 3: Reset the CC3E Bit */
7695 tmpccer = TIMx->CCER;
7696 TIMx->CCER &= ~TIM_CCER_CC3E;
7697 tmpccmr2 = TIMx->CCMR2;
7698
7699 /* Select the Input */
7700 tmpccmr2 &= ~TIM_CCMR2_CC3S;
7701 tmpccmr2 |= TIM_ICSelection;
7702
7703 /* Set the filter */
7704 tmpccmr2 &= ~TIM_CCMR2_IC3F;
7705 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
7706
7707 /* Select the Polarity and set the CC3E Bit */
7708 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
7709 tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
7710
7711 /* Write to TIMx CCMR2 and CCER registers */
7712 TIMx->CCMR2 = tmpccmr2;
7713 TIMx->CCER = tmpccer;
7714 }
7715
7716 /**
7717 * @brief Configure the TI4 as Input.
7718 * @param TIMx to select the TIM peripheral
7719 * @param TIM_ICPolarity The Input Polarity.
7720 * This parameter can be one of the following values:
7721 * @arg TIM_ICPOLARITY_RISING
7722 * @arg TIM_ICPOLARITY_FALLING
7723 * @arg TIM_ICPOLARITY_BOTHEDGE
7724 * @param TIM_ICSelection specifies the input to be used.
7725 * This parameter can be one of the following values:
7726 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
7727 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
7728 * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
7729 * @param TIM_ICFilter Specifies the Input Capture Filter.
7730 * This parameter must be a value between 0x00 and 0x0F.
7731 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
7732 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
7733 * protected against un-initialized filter and polarity values.
7734 * @retval None
7735 */
TIM_TI4_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7736 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7737 uint32_t TIM_ICFilter)
7738 {
7739 uint32_t tmpccmr2;
7740 uint32_t tmpccer;
7741
7742 /* Disable the Channel 4: Reset the CC4E Bit */
7743 tmpccer = TIMx->CCER;
7744 TIMx->CCER &= ~TIM_CCER_CC4E;
7745 tmpccmr2 = TIMx->CCMR2;
7746
7747 /* Select the Input */
7748 tmpccmr2 &= ~TIM_CCMR2_CC4S;
7749 tmpccmr2 |= (TIM_ICSelection << 8U);
7750
7751 /* Set the filter */
7752 tmpccmr2 &= ~TIM_CCMR2_IC4F;
7753 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
7754
7755 /* Select the Polarity and set the CC4E Bit */
7756 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
7757 tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
7758
7759 /* Write to TIMx CCMR2 and CCER registers */
7760 TIMx->CCMR2 = tmpccmr2;
7761 TIMx->CCER = tmpccer ;
7762 }
7763
7764 /**
7765 * @brief Selects the Input Trigger source
7766 * @param TIMx to select the TIM peripheral
7767 * @param InputTriggerSource The Input Trigger source.
7768 * This parameter can be one of the following values:
7769 * @arg TIM_TS_ITR0: Internal Trigger 0
7770 * @arg TIM_TS_ITR1: Internal Trigger 1
7771 * @arg TIM_TS_ITR2: Internal Trigger 2
7772 * @arg TIM_TS_ITR3: Internal Trigger 3
7773 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
7774 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
7775 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
7776 * @arg TIM_TS_ETRF: External Trigger input
7777 * @retval None
7778 */
TIM_ITRx_SetConfig(TIM_TypeDef * TIMx,uint32_t InputTriggerSource)7779 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
7780 {
7781 uint32_t tmpsmcr;
7782
7783 /* Get the TIMx SMCR register value */
7784 tmpsmcr = TIMx->SMCR;
7785 /* Reset the TS Bits */
7786 tmpsmcr &= ~TIM_SMCR_TS;
7787 /* Set the Input Trigger source and the slave mode*/
7788 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
7789 /* Write to TIMx SMCR */
7790 TIMx->SMCR = tmpsmcr;
7791 }
7792 /**
7793 * @brief Configures the TIMx External Trigger (ETR).
7794 * @param TIMx to select the TIM peripheral
7795 * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
7796 * This parameter can be one of the following values:
7797 * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
7798 * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
7799 * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
7800 * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
7801 * @param TIM_ExtTRGPolarity The external Trigger Polarity.
7802 * This parameter can be one of the following values:
7803 * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
7804 * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
7805 * @param ExtTRGFilter External Trigger Filter.
7806 * This parameter must be a value between 0x00 and 0x0F
7807 * @retval None
7808 */
TIM_ETR_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ExtTRGPrescaler,uint32_t TIM_ExtTRGPolarity,uint32_t ExtTRGFilter)7809 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
7810 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
7811 {
7812 uint32_t tmpsmcr;
7813
7814 tmpsmcr = TIMx->SMCR;
7815
7816 /* Reset the ETR Bits */
7817 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
7818
7819 /* Set the Prescaler, the Filter value and the Polarity */
7820 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
7821
7822 /* Write to TIMx SMCR */
7823 TIMx->SMCR = tmpsmcr;
7824 }
7825
7826 /**
7827 * @brief Enables or disables the TIM Capture Compare Channel x.
7828 * @param TIMx to select the TIM peripheral
7829 * @param Channel specifies the TIM Channel
7830 * This parameter can be one of the following values:
7831 * @arg TIM_CHANNEL_1: TIM Channel 1
7832 * @arg TIM_CHANNEL_2: TIM Channel 2
7833 * @arg TIM_CHANNEL_3: TIM Channel 3
7834 * @arg TIM_CHANNEL_4: TIM Channel 4
7835 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
7836 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
7837 * @param ChannelState specifies the TIM Channel CCxE bit new state.
7838 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
7839 * @retval None
7840 */
TIM_CCxChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelState)7841 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
7842 {
7843 uint32_t tmp;
7844
7845 /* Check the parameters */
7846 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
7847 assert_param(IS_TIM_CHANNELS(Channel));
7848
7849 tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
7850
7851 /* Reset the CCxE Bit */
7852 TIMx->CCER &= ~tmp;
7853
7854 /* Set or reset the CCxE Bit */
7855 TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
7856 }
7857
7858 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7859 /**
7860 * @brief Reset interrupt callbacks to the legacy weak callbacks.
7861 * @param htim pointer to a TIM_HandleTypeDef structure that contains
7862 * the configuration information for TIM module.
7863 * @retval None
7864 */
TIM_ResetCallback(TIM_HandleTypeDef * htim)7865 void TIM_ResetCallback(TIM_HandleTypeDef *htim)
7866 {
7867 /* Reset the TIM callback to the legacy weak callbacks */
7868 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
7869 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
7870 htim->TriggerCallback = HAL_TIM_TriggerCallback;
7871 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
7872 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
7873 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
7874 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
7875 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
7876 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
7877 htim->ErrorCallback = HAL_TIM_ErrorCallback;
7878 htim->CommutationCallback = HAL_TIMEx_CommutCallback;
7879 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
7880 htim->BreakCallback = HAL_TIMEx_BreakCallback;
7881 htim->Break2Callback = HAL_TIMEx_Break2Callback;
7882 }
7883 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7884
7885 /**
7886 * @}
7887 */
7888
7889 #endif /* HAL_TIM_MODULE_ENABLED */
7890 /**
7891 * @}
7892 */
7893
7894 /**
7895 * @}
7896 */
7897
