1 /**
2 ******************************************************************************
3 * @file stm32c0xx_hal_cortex.c
4 * @author MCD Application Team
5 * @brief CORTEX HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the CORTEX:
8 * + Initialization and Configuration functions
9 * + Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * Copyright (c) 2022 STMicroelectronics.
15 * All rights reserved.
16 *
17 * This software is licensed under terms that can be found in the LICENSE file
18 * in the root directory of this software component.
19 * If no LICENSE file comes with this software, it is provided AS-IS.
20 *
21 ******************************************************************************
22 @verbatim
23 ==============================================================================
24 ##### How to use this driver #####
25 ==============================================================================
26 [..]
27 *** How to configure Interrupts using CORTEX HAL driver ***
28 ===========================================================
29 [..]
30 This section provides functions allowing to configure the NVIC interrupts (IRQ).
31 The Cortex M0+ exceptions are managed by CMSIS functions.
32 (#) Enable and Configure the priority of the selected IRQ Channels.
33 The priority can be 0..3.
34
35 -@- Lower priority values gives higher priority.
36 -@- Priority Order:
37 (#@) Lowest priority.
38 (#@) Lowest hardware priority (IRQn position).
39
40 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
41
42 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
43
44 -@- Negative value of IRQn_Type are not allowed.
45
46 *** How to configure Systick using CORTEX HAL driver ***
47 ========================================================
48 [..]
49 Setup SysTick Timer for time base.
50
51 (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
52 is a CMSIS function that:
53 (++) Configures the SysTick Reload register with value passed as function parameter.
54 (++) Configures the SysTick IRQ priority to the lowest value (0x03).
55 (++) Resets the SysTick Counter register.
56 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
57 (++) Enables the SysTick Interrupt.
58 (++) Starts the SysTick Counter.
59
60 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
61 __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
62 HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
63 inside the stm32c0xx_hal_cortex.h file.
64
65 (+) You can change the SysTick IRQ priority by calling the
66 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
67 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
68
69 (+) To adjust the SysTick time base, use the following formula:
70
71 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
72 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
73 (++) Reload Value should not exceed 0xFFFFFF
74
75 @endverbatim
76 ******************************************************************************
77 */
78
79 /* Includes ------------------------------------------------------------------*/
80 #include "stm32c0xx_hal.h"
81
82 /** @addtogroup STM32C0xx_HAL_Driver
83 * @{
84 */
85
86 /** @addtogroup CORTEX
87 * @{
88 */
89
90 #ifdef HAL_CORTEX_MODULE_ENABLED
91
92 /* Private types -------------------------------------------------------------*/
93 /* Private variables ---------------------------------------------------------*/
94 /* Private constants ---------------------------------------------------------*/
95 /* Private macros ------------------------------------------------------------*/
96 /* Private function prototypes -----------------------------------------------*/
97 /* Exported functions --------------------------------------------------------*/
98
99 /** @addtogroup CORTEX_Exported_Functions
100 * @{
101 */
102
103
104 /** @addtogroup CORTEX_Exported_Functions_Group1
105 * @brief Initialization and Configuration functions
106 *
107 @verbatim
108 ==============================================================================
109 ##### Initialization and Configuration functions #####
110 ==============================================================================
111 [..]
112 This section provides the CORTEX HAL driver functions allowing to configure Interrupts
113 Systick functionalities
114
115 @endverbatim
116 * @{
117 */
118
119 /**
120 * @brief Sets the priority of an interrupt.
121 * @param IRQn External interrupt number .
122 * This parameter can be an enumerator of IRQn_Type enumeration
123 * (For the complete STM32 Devices IRQ Channels list, please refer to stm32c0xx.h file)
124 * @param PreemptPriority The preemption priority for the IRQn channel.
125 * This parameter can be a value between 0 and 3.
126 * A lower priority value indicates a higher priority
127 * @param SubPriority the subpriority level for the IRQ channel.
128 * with stm32c0xx devices, this parameter is a dummy value and it is ignored, because
129 * no subpriority supported in Cortex M0+ based products.
130 * @retval None
131 */
HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority,uint32_t SubPriority)132 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
133 {
134 /* Prevent unused argument(s) compilation warning */
135 UNUSED(SubPriority);
136 /* Check the parameters */
137 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
138 NVIC_SetPriority(IRQn, PreemptPriority);
139 }
140
141 /**
142 * @brief Enable a device specific interrupt in the NVIC interrupt controller.
143 * @param IRQn External interrupt number.
144 * This parameter can be an enumerator of IRQn_Type enumeration
145 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
146 * CMSIS device file (stm32c0xxxx.h))
147 * @retval None
148 */
HAL_NVIC_EnableIRQ(IRQn_Type IRQn)149 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
150 {
151 /* Check the parameters */
152 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
153
154 /* Enable interrupt */
155 NVIC_EnableIRQ(IRQn);
156 }
157
158 /**
159 * @brief Disable a device specific interrupt in the NVIC interrupt controller.
160 * @param IRQn External interrupt number.
161 * This parameter can be an enumerator of IRQn_Type enumeration
162 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
163 * CMSIS device file (stm32c0xxxx.h))
164 * @retval None
165 */
HAL_NVIC_DisableIRQ(IRQn_Type IRQn)166 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
167 {
168 /* Check the parameters */
169 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
170
171 /* Disable interrupt */
172 NVIC_DisableIRQ(IRQn);
173 }
174
175 /**
176 * @brief Initiate a system reset request to reset the MCU.
177 * @retval None
178 */
HAL_NVIC_SystemReset(void)179 void HAL_NVIC_SystemReset(void)
180 {
181 /* System Reset */
182 NVIC_SystemReset();
183 }
184
185 /**
186 * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
187 * Counter is in free running mode to generate periodic interrupts.
188 * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
189 * @retval status: - 0 Function succeeded.
190 * - 1 Function failed.
191 */
HAL_SYSTICK_Config(uint32_t TicksNumb)192 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
193 {
194 return SysTick_Config(TicksNumb);
195 }
196 /**
197 * @}
198 */
199
200 /** @addtogroup CORTEX_Exported_Functions_Group2
201 * @brief Cortex control functions
202 *
203 @verbatim
204 ==============================================================================
205 ##### Peripheral Control functions #####
206 ==============================================================================
207 [..]
208 This subsection provides a set of functions allowing to control the CORTEX
209 (NVIC, SYSTICK, MPU) functionalities.
210
211
212 @endverbatim
213 * @{
214 */
215
216 /**
217 * @brief Get the priority of an interrupt.
218 * @param IRQn External interrupt number.
219 * This parameter can be an enumerator of IRQn_Type enumeration
220 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
221 * CMSIS device file (stm32c0xxxx.h))
222 * @retval None
223 */
HAL_NVIC_GetPriority(IRQn_Type IRQn)224 uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn)
225 {
226 /* Get priority for Cortex-M system or device specific interrupts */
227 return NVIC_GetPriority(IRQn);
228 }
229
230 /**
231 * @brief Set Pending bit of an external interrupt.
232 * @param IRQn External interrupt number
233 * This parameter can be an enumerator of IRQn_Type enumeration
234 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
235 * CMSIS device file (stm32c0xxxx.h))
236 * @retval None
237 */
HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)238 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
239 {
240 /* Check the parameters */
241 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
242
243 /* Set interrupt pending */
244 NVIC_SetPendingIRQ(IRQn);
245 }
246
247 /**
248 * @brief Get Pending Interrupt (read the pending register in the NVIC
249 * and return the pending bit for the specified interrupt).
250 * @param IRQn External interrupt number.
251 * This parameter can be an enumerator of IRQn_Type enumeration
252 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
253 * CMSIS device file (stm32c0xxxx.h))
254 * @retval status: - 0 Interrupt status is not pending.
255 * - 1 Interrupt status is pending.
256 */
HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)257 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
258 {
259 /* Check the parameters */
260 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
261
262 /* Return 1 if pending else 0 */
263 return NVIC_GetPendingIRQ(IRQn);
264 }
265
266 /**
267 * @brief Clear the pending bit of an external interrupt.
268 * @param IRQn External interrupt number.
269 * This parameter can be an enumerator of IRQn_Type enumeration
270 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
271 * CMSIS device file (stm32c0xxxx.h))
272 * @retval None
273 */
HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)274 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
275 {
276 /* Check the parameters */
277 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
278
279 /* Clear pending interrupt */
280 NVIC_ClearPendingIRQ(IRQn);
281 }
282
283 /**
284 * @brief Configure the SysTick clock source.
285 * @param CLKSource specifies the SysTick clock source.
286 * This parameter can be one of the following values:
287 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
288 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
289 * @retval None
290 */
HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)291 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
292 {
293 /* Check the parameters */
294 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
295 if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
296 {
297 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
298 }
299 else
300 {
301 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
302 }
303 }
304
305 /**
306 * @brief Handle SYSTICK interrupt request.
307 * @retval None
308 */
HAL_SYSTICK_IRQHandler(void)309 void HAL_SYSTICK_IRQHandler(void)
310 {
311 HAL_SYSTICK_Callback();
312 }
313
314 /**
315 * @brief SYSTICK callback.
316 * @retval None
317 */
HAL_SYSTICK_Callback(void)318 __weak void HAL_SYSTICK_Callback(void)
319 {
320 /* NOTE : This function should not be modified, when the callback is needed,
321 the HAL_SYSTICK_Callback could be implemented in the user file
322 */
323 }
324
325 #if (__MPU_PRESENT == 1U)
326 /**
327 * @brief Enable the MPU.
328 * @param MPU_Control Specifies the control mode of the MPU during hard fault,
329 * NMI, FAULTMASK and privileged access to the default memory
330 * This parameter can be one of the following values:
331 * @arg MPU_HFNMI_PRIVDEF_NONE
332 * @arg MPU_HARDFAULT_NMI
333 * @arg MPU_PRIVILEGED_DEFAULT
334 * @arg MPU_HFNMI_PRIVDEF
335 * @retval None
336 */
HAL_MPU_Enable(uint32_t MPU_Control)337 void HAL_MPU_Enable(uint32_t MPU_Control)
338 {
339 /* Enable the MPU */
340 MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk);
341
342 /* Ensure MPU setting take effects */
343 __DSB();
344 __ISB();
345 }
346
347
348 /**
349 * @brief Disable the MPU.
350 * @retval None
351 */
HAL_MPU_Disable(void)352 void HAL_MPU_Disable(void)
353 {
354 /* Make sure outstanding transfers are done */
355 __DMB();
356
357 /* Disable the MPU and clear the control register*/
358 MPU->CTRL = 0;
359 }
360
361
362 /**
363 * @brief Initialize and configure the Region and the memory to be protected.
364 * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
365 * the initialization and configuration information.
366 * @retval None
367 */
HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef * MPU_Init)368 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
369 {
370 /* Check the parameters */
371 assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
372 assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
373
374 /* Set the Region number */
375 MPU->RNR = MPU_Init->Number;
376
377 if ((MPU_Init->Enable) != 0U)
378 {
379 /* Check the parameters */
380 assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
381 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
382 assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
383 assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
384 assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
385 assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
386 assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
387 assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
388
389 MPU->RBAR = MPU_Init->BaseAddress;
390 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
391 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
392 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
393 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
394 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
395 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
396 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
397 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
398 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
399 }
400 else
401 {
402 MPU->RBAR = 0x00U;
403 MPU->RASR = 0x00U;
404 }
405 }
406 #endif /* __MPU_PRESENT */
407
408 /**
409 * @}
410 */
411
412 /**
413 * @}
414 */
415
416 #endif /* HAL_CORTEX_MODULE_ENABLED */
417 /**
418 * @}
419 */
420
421 /**
422 * @}
423 */
424