1 /**
2 ******************************************************************************
3 * @file stm32c0xx_ll_wwdg.h
4 * @author MCD Application Team
5 * @brief Header file of WWDG LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32C0xx_LL_WWDG_H
21 #define STM32C0xx_LL_WWDG_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32c0xx.h"
29
30 /** @addtogroup STM32C0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (WWDG)
35
36 /** @defgroup WWDG_LL WWDG
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /* Exported types ------------------------------------------------------------*/
45 /* Exported constants --------------------------------------------------------*/
46 /** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
47 * @{
48 */
49
50 /** @defgroup WWDG_LL_EC_IT IT Defines
51 * @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
52 * @{
53 */
54 #define LL_WWDG_CFR_EWI WWDG_CFR_EWI
55 /**
56 * @}
57 */
58
59 /** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
60 * @{
61 */
62 #define LL_WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
63 #define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
64 #define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
65 #define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
66 #define LL_WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2 /*!< WWDG counter clock = (PCLK1/4096)/16 */
67 #define LL_WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/32 */
68 #define LL_WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/64 */
69 #define LL_WWDG_PRESCALER_128 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/128 */
70 /**
71 * @}
72 */
73
74 /**
75 * @}
76 */
77
78 /* Exported macro ------------------------------------------------------------*/
79 /** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
80 * @{
81 */
82 /** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
83 * @{
84 */
85 /**
86 * @brief Write a value in WWDG register
87 * @param __INSTANCE__ WWDG Instance
88 * @param __REG__ Register to be written
89 * @param __VALUE__ Value to be written in the register
90 * @retval None
91 */
92 #define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
93
94 /**
95 * @brief Read a value in WWDG register
96 * @param __INSTANCE__ WWDG Instance
97 * @param __REG__ Register to be read
98 * @retval Register value
99 */
100 #define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
101 /**
102 * @}
103 */
104
105 /**
106 * @}
107 */
108
109 /* Exported functions --------------------------------------------------------*/
110 /** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
111 * @{
112 */
113
114 /** @defgroup WWDG_LL_EF_Configuration Configuration
115 * @{
116 */
117 /**
118 * @brief Enable Window Watchdog. The watchdog is always disabled after a reset.
119 * @note It is enabled by setting the WDGA bit in the WWDG_CR register,
120 * then it cannot be disabled again except by a reset.
121 * This bit is set by software and only cleared by hardware after a reset.
122 * When WDGA = 1, the watchdog can generate a reset.
123 * @rmtoll CR WDGA LL_WWDG_Enable
124 * @param WWDGx WWDG Instance
125 * @retval None
126 */
LL_WWDG_Enable(WWDG_TypeDef * WWDGx)127 __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
128 {
129 SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
130 }
131
132 /**
133 * @brief Checks if Window Watchdog is enabled
134 * @rmtoll CR WDGA LL_WWDG_IsEnabled
135 * @param WWDGx WWDG Instance
136 * @retval State of bit (1 or 0).
137 */
LL_WWDG_IsEnabled(WWDG_TypeDef * WWDGx)138 __STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
139 {
140 return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL);
141 }
142
143 /**
144 * @brief Set the Watchdog counter value to provided value (7-bits T[6:0])
145 * @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
146 * This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
147 * A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
148 * Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
149 * @rmtoll CR T LL_WWDG_SetCounter
150 * @param WWDGx WWDG Instance
151 * @param Counter 0..0x7F (7 bit counter value)
152 * @retval None
153 */
LL_WWDG_SetCounter(WWDG_TypeDef * WWDGx,uint32_t Counter)154 __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
155 {
156 MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
157 }
158
159 /**
160 * @brief Return current Watchdog Counter Value (7 bits counter value)
161 * @rmtoll CR T LL_WWDG_GetCounter
162 * @param WWDGx WWDG Instance
163 * @retval 7 bit Watchdog Counter value
164 */
LL_WWDG_GetCounter(WWDG_TypeDef * WWDGx)165 __STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
166 {
167 return (READ_BIT(WWDGx->CR, WWDG_CR_T));
168 }
169
170 /**
171 * @brief Set the time base of the prescaler (WDGTB).
172 * @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
173 * is decremented every (4096 x 2expWDGTB) PCLK cycles
174 * @rmtoll CFR WDGTB LL_WWDG_SetPrescaler
175 * @param WWDGx WWDG Instance
176 * @param Prescaler This parameter can be one of the following values:
177 * @arg @ref LL_WWDG_PRESCALER_1
178 * @arg @ref LL_WWDG_PRESCALER_2
179 * @arg @ref LL_WWDG_PRESCALER_4
180 * @arg @ref LL_WWDG_PRESCALER_8
181 * @arg @ref LL_WWDG_PRESCALER_16
182 * @arg @ref LL_WWDG_PRESCALER_32
183 * @arg @ref LL_WWDG_PRESCALER_64
184 * @arg @ref LL_WWDG_PRESCALER_128
185 * @retval None
186 */
LL_WWDG_SetPrescaler(WWDG_TypeDef * WWDGx,uint32_t Prescaler)187 __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
188 {
189 MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
190 }
191
192 /**
193 * @brief Return current Watchdog Prescaler Value
194 * @rmtoll CFR WDGTB LL_WWDG_GetPrescaler
195 * @param WWDGx WWDG Instance
196 * @retval Returned value can be one of the following values:
197 * @arg @ref LL_WWDG_PRESCALER_1
198 * @arg @ref LL_WWDG_PRESCALER_2
199 * @arg @ref LL_WWDG_PRESCALER_4
200 * @arg @ref LL_WWDG_PRESCALER_8
201 * @arg @ref LL_WWDG_PRESCALER_16
202 * @arg @ref LL_WWDG_PRESCALER_32
203 * @arg @ref LL_WWDG_PRESCALER_64
204 * @arg @ref LL_WWDG_PRESCALER_128
205 */
LL_WWDG_GetPrescaler(WWDG_TypeDef * WWDGx)206 __STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
207 {
208 return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
209 }
210
211 /**
212 * @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
213 * @note This window value defines when write in the WWDG_CR register
214 * to program Watchdog counter is allowed.
215 * Watchdog counter value update must occur only when the counter value
216 * is lower than the Watchdog window register value.
217 * Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
218 * (in the control register) is refreshed before the downcounter has reached
219 * the watchdog window register value.
220 * Physically is possible to set the Window lower then 0x40 but it is not recommended.
221 * To generate an immediate reset, it is possible to set the Counter lower than 0x40.
222 * @rmtoll CFR W LL_WWDG_SetWindow
223 * @param WWDGx WWDG Instance
224 * @param Window 0x00..0x7F (7 bit Window value)
225 * @retval None
226 */
LL_WWDG_SetWindow(WWDG_TypeDef * WWDGx,uint32_t Window)227 __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
228 {
229 MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
230 }
231
232 /**
233 * @brief Return current Watchdog Window Value (7 bits value)
234 * @rmtoll CFR W LL_WWDG_GetWindow
235 * @param WWDGx WWDG Instance
236 * @retval 7 bit Watchdog Window value
237 */
LL_WWDG_GetWindow(WWDG_TypeDef * WWDGx)238 __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
239 {
240 return (READ_BIT(WWDGx->CFR, WWDG_CFR_W));
241 }
242
243 /**
244 * @}
245 */
246
247 /** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
248 * @{
249 */
250 /**
251 * @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
252 * @note This bit is set by hardware when the counter has reached the value 0x40.
253 * It must be cleared by software by writing 0.
254 * A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
255 * @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP
256 * @param WWDGx WWDG Instance
257 * @retval State of bit (1 or 0).
258 */
LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef * WWDGx)259 __STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
260 {
261 return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL);
262 }
263
264 /**
265 * @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF)
266 * @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP
267 * @param WWDGx WWDG Instance
268 * @retval None
269 */
LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef * WWDGx)270 __STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
271 {
272 WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
273 }
274
275 /**
276 * @}
277 */
278
279 /** @defgroup WWDG_LL_EF_IT_Management IT_Management
280 * @{
281 */
282 /**
283 * @brief Enable the Early Wakeup Interrupt.
284 * @note When set, an interrupt occurs whenever the counter reaches value 0x40.
285 * This interrupt is only cleared by hardware after a reset
286 * @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP
287 * @param WWDGx WWDG Instance
288 * @retval None
289 */
LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef * WWDGx)290 __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
291 {
292 SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
293 }
294
295 /**
296 * @brief Check if Early Wakeup Interrupt is enabled
297 * @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP
298 * @param WWDGx WWDG Instance
299 * @retval State of bit (1 or 0).
300 */
LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef * WWDGx)301 __STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
302 {
303 return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL);
304 }
305
306 /**
307 * @}
308 */
309
310 /**
311 * @}
312 */
313
314 /**
315 * @}
316 */
317
318 #endif /* WWDG */
319
320 /**
321 * @}
322 */
323
324 #ifdef __cplusplus
325 }
326 #endif
327
328 #endif /* STM32C0xx_LL_WWDG_H */
329
330
