1 /** 2 ****************************************************************************** 3 * @file stm32c0xx_ll_utils.h 4 * @author MCD Application Team 5 * @brief Header file of UTILS LL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 @verbatim 18 ============================================================================== 19 ##### How to use this driver ##### 20 ============================================================================== 21 [..] 22 The LL UTILS driver contains a set of generic APIs that can be 23 used by user: 24 (+) Device electronic signature 25 (+) Timing functions 26 27 @endverbatim 28 */ 29 30 /* Define to prevent recursive inclusion -------------------------------------*/ 31 #ifndef STM32C0xx_LL_UTILS_H 32 #define STM32C0xx_LL_UTILS_H 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 /* Includes ------------------------------------------------------------------*/ 39 #include "stm32c0xx.h" 40 41 /** @addtogroup STM32C0xx_LL_Driver 42 * @{ 43 */ 44 45 /** @defgroup UTILS_LL UTILS 46 * @{ 47 */ 48 49 /* Private types -------------------------------------------------------------*/ 50 /* Private variables ---------------------------------------------------------*/ 51 52 /* Private constants ---------------------------------------------------------*/ 53 /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants 54 * @{ 55 */ 56 57 /* Max delay can be used in LL_mDelay */ 58 #define LL_MAX_DELAY 0xFFFFFFFFU 59 60 /** 61 * @brief Unique device ID register base address 62 */ 63 #define UID_BASE_ADDRESS UID_BASE 64 65 /** 66 * @brief Flash size data register base address 67 */ 68 #define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE 69 70 /** 71 * @brief Package data register base address 72 */ 73 #define PACKAGE_BASE_ADDRESS PACKAGE_BASE 74 75 /** 76 * @} 77 */ 78 79 /* Private macros ------------------------------------------------------------*/ 80 /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros 81 * @{ 82 */ 83 /** 84 * @} 85 */ 86 /* Exported types ------------------------------------------------------------*/ 87 /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures 88 * @{ 89 */ 90 91 /** 92 * @brief UTILS System, AHB and APB buses clock configuration structure definition 93 */ 94 typedef struct 95 { 96 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 97 This parameter can be a value of @ref RCC_HCLK_Clock_Source 98 99 This feature can be modified afterwards using unitary function 100 @ref LL_RCC_SetAHBPrescaler(). */ 101 102 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 103 This parameter can be a value of @ref RCC_LL_EC_APB1_DIV 104 105 This feature can be modified afterwards using unitary function 106 @ref LL_RCC_SetAPB1Prescaler(). */ 107 } LL_UTILS_ClkInitTypeDef; 108 109 /** 110 * @} 111 */ 112 113 /* Exported constants --------------------------------------------------------*/ 114 /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants 115 * @{ 116 */ 117 118 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation 119 * @{ 120 */ 121 #define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ 122 #define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ 123 /** 124 * @} 125 */ 126 127 /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE 128 * @{ 129 */ 130 #define LL_UTILS_PACKAGETYPE_QFN28_GP 0x00000000U /*!< UFQFPN28 general purpose (GP) package type */ 131 #define LL_UTILS_PACKAGETYPE_QFN28_PD 0x00000001U /*!< UFQFPN28 Power Delivery (PD) */ 132 #define LL_UTILS_PACKAGETYPE_QFN32_GP 0x00000004U /*!< UFQFPN32 / LQFP32 general purpose (GP) package type */ 133 #define LL_UTILS_PACKAGETYPE_QFN32_PD 0x00000005U /*!< UFQFPN32 / LQFP32 Power Delivery (PD) package type */ 134 #define LL_UTILS_PACKAGETYPE_QFN48 0x00000008U /*!< UFQFPN48 / LQFP488 package type */ 135 #define LL_UTILS_PACKAGETYPE_QFP48 0x0000000CU /*!< LQPF48 package type */ 136 /** 137 * @} 138 */ 139 140 /** 141 * @} 142 */ 143 144 /* Exported macro ------------------------------------------------------------*/ 145 146 /* Exported functions --------------------------------------------------------*/ 147 /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions 148 * @{ 149 */ 150 151 /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE 152 * @{ 153 */ 154 155 /** 156 * @brief Get Word0 of the unique device identifier (UID based on 96 bits) 157 * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format 158 */ LL_GetUID_Word0(void)159__STATIC_INLINE uint32_t LL_GetUID_Word0(void) 160 { 161 return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); 162 } 163 164 /** 165 * @brief Get Word1 of the unique device identifier (UID based on 96 bits) 166 * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40]) 167 */ LL_GetUID_Word1(void)168__STATIC_INLINE uint32_t LL_GetUID_Word1(void) 169 { 170 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); 171 } 172 173 /** 174 * @brief Get Word2 of the unique device identifier (UID based on 96 bits) 175 * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24] 176 */ LL_GetUID_Word2(void)177__STATIC_INLINE uint32_t LL_GetUID_Word2(void) 178 { 179 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); 180 } 181 182 /** 183 * @brief Get Flash memory size 184 * @note This bitfield indicates the size of the device Flash memory expressed in 185 * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. 186 * @retval FLASH_SIZE[15:0]: Flash memory size 187 */ LL_GetFlashSize(void)188__STATIC_INLINE uint32_t LL_GetFlashSize(void) 189 { 190 return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0x0000FFFFUL); 191 } 192 193 /** 194 * @brief Get Package type 195 * @retval Returned value can be one of the following values: 196 * @arg @ref LL_UTILS_PACKAGETYPE_QFN28_GP 197 * @arg @ref LL_UTILS_PACKAGETYPE_QFN28_PD 198 * @arg @ref LL_UTILS_PACKAGETYPE_QFN32_GP 199 * @arg @ref LL_UTILS_PACKAGETYPE_QFN32_PD 200 * @arg @ref LL_UTILS_PACKAGETYPE_QFN48 201 * @arg @ref LL_UTILS_PACKAGETYPE_QFP48 202 */ LL_GetPackageType(void)203__STATIC_INLINE uint32_t LL_GetPackageType(void) 204 { 205 return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0xFU); 206 } 207 208 /** 209 * @} 210 */ 211 212 /** @defgroup UTILS_LL_EF_DELAY DELAY 213 * @{ 214 */ 215 216 /** 217 * @brief This function configures the Cortex-M SysTick source of the time base. 218 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) 219 * @note When a RTOS is used, it is recommended to avoid changing the SysTick 220 * configuration by calling this function, for a delay use rather osDelay RTOS service. 221 * @param Ticks Number of ticks 222 * @retval None 223 */ LL_InitTick(uint32_t HCLKFrequency,uint32_t Ticks)224__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) 225 { 226 /* Configure the SysTick to have interrupt in 1ms time base */ 227 SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ 228 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 229 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 230 SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ 231 } 232 233 void LL_Init1msTick(uint32_t HCLKFrequency); 234 void LL_mDelay(uint32_t Delay); 235 236 /** 237 * @} 238 */ 239 240 /** @defgroup UTILS_EF_SYSTEM SYSTEM 241 * @{ 242 */ 243 void LL_SetSystemCoreClock(uint32_t HCLKFrequency); 244 ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency); 245 /* alias for backward compatibility */ 246 #define UTILS_SetFlashLatency LL_SetFlashLatency 247 248 /** 249 * @} 250 */ 251 252 /** 253 * @} 254 */ 255 256 /** 257 * @} 258 */ 259 260 /** 261 * @} 262 */ 263 264 #ifdef __cplusplus 265 } 266 #endif 267 268 #endif /* STM32C0xx_LL_UTILS_H */ 269 270
