1 /**
2 ******************************************************************************
3 * @file stm32c0xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32C0xx_LL_TIM_H
21 #define __STM32C0xx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32c0xx.h"
29
30 /** @addtogroup STM32C0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM14) || defined (TIM16) || defined (TIM17)
35
36 /** @defgroup TIM_LL TIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
43 * @{
44 */
45 static const uint8_t OFFSET_TAB_CCMRx[] =
46 {
47 0x00U, /* 0: TIMx_CH1 */
48 0x00U, /* 1: TIMx_CH1N */
49 0x00U, /* 2: TIMx_CH2 */
50 0x00U, /* 3: TIMx_CH2N */
51 0x04U, /* 4: TIMx_CH3 */
52 0x04U, /* 5: TIMx_CH3N */
53 0x04U, /* 6: TIMx_CH4 */
54 0x3CU, /* 7: TIMx_CH5 */
55 0x3CU /* 8: TIMx_CH6 */
56 };
57
58 static const uint8_t SHIFT_TAB_OCxx[] =
59 {
60 0U, /* 0: OC1M, OC1FE, OC1PE */
61 0U, /* 1: - NA */
62 8U, /* 2: OC2M, OC2FE, OC2PE */
63 0U, /* 3: - NA */
64 0U, /* 4: OC3M, OC3FE, OC3PE */
65 0U, /* 5: - NA */
66 8U, /* 6: OC4M, OC4FE, OC4PE */
67 0U, /* 7: OC5M, OC5FE, OC5PE */
68 8U /* 8: OC6M, OC6FE, OC6PE */
69 };
70
71 static const uint8_t SHIFT_TAB_ICxx[] =
72 {
73 0U, /* 0: CC1S, IC1PSC, IC1F */
74 0U, /* 1: - NA */
75 8U, /* 2: CC2S, IC2PSC, IC2F */
76 0U, /* 3: - NA */
77 0U, /* 4: CC3S, IC3PSC, IC3F */
78 0U, /* 5: - NA */
79 8U, /* 6: CC4S, IC4PSC, IC4F */
80 0U, /* 7: - NA */
81 0U /* 8: - NA */
82 };
83
84 static const uint8_t SHIFT_TAB_CCxP[] =
85 {
86 0U, /* 0: CC1P */
87 2U, /* 1: CC1NP */
88 4U, /* 2: CC2P */
89 6U, /* 3: CC2NP */
90 8U, /* 4: CC3P */
91 10U, /* 5: CC3NP */
92 12U, /* 6: CC4P */
93 16U, /* 7: CC5P */
94 20U /* 8: CC6P */
95 };
96
97 static const uint8_t SHIFT_TAB_OISx[] =
98 {
99 0U, /* 0: OIS1 */
100 1U, /* 1: OIS1N */
101 2U, /* 2: OIS2 */
102 3U, /* 3: OIS2N */
103 4U, /* 4: OIS3 */
104 5U, /* 5: OIS3N */
105 6U, /* 6: OIS4 */
106 8U, /* 7: OIS5 */
107 10U /* 8: OIS6 */
108 };
109 /**
110 * @}
111 */
112
113 /* Private constants ---------------------------------------------------------*/
114 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
115 * @{
116 */
117
118 /* Defines used for the bit position in the register and perform offsets */
119 #define TIM_POSITION_BRK_SOURCE ((Source >> 1U) & 0x1FUL)
120
121 /* Generic bit definitions for TIMx_AF1 register */
122 #define TIMx_AF1_BKINP TIM_AF1_BKINP /*!< BRK BKIN input polarity */
123 #define TIMx_AF1_ETRSEL TIM_AF1_ETRSEL /*!< TIMx ETR source selection */
124
125
126 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
127 #define DT_DELAY_1 ((uint8_t)0x7F)
128 #define DT_DELAY_2 ((uint8_t)0x3F)
129 #define DT_DELAY_3 ((uint8_t)0x1F)
130 #define DT_DELAY_4 ((uint8_t)0x1F)
131
132 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
133 #define DT_RANGE_1 ((uint8_t)0x00)
134 #define DT_RANGE_2 ((uint8_t)0x80)
135 #define DT_RANGE_3 ((uint8_t)0xC0)
136 #define DT_RANGE_4 ((uint8_t)0xE0)
137
138 /** Legacy definitions for compatibility purpose
139 @cond 0
140 */
141 /**
142 @endcond
143 */
144
145 #define OCREF_CLEAR_SELECT_POS (16U)
146 #define OCREF_CLEAR_SELECT_MSK (0x1U << OCREF_CLEAR_SELECT_POS) /*!< 0x00010000 */
147 /**
148 * @}
149 */
150
151 /* Private macros ------------------------------------------------------------*/
152 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
153 * @{
154 */
155 /** @brief Convert channel id into channel index.
156 * @param __CHANNEL__ This parameter can be one of the following values:
157 * @arg @ref LL_TIM_CHANNEL_CH1
158 * @arg @ref LL_TIM_CHANNEL_CH1N
159 * @arg @ref LL_TIM_CHANNEL_CH2
160 * @arg @ref LL_TIM_CHANNEL_CH2N
161 * @arg @ref LL_TIM_CHANNEL_CH3
162 * @arg @ref LL_TIM_CHANNEL_CH3N
163 * @arg @ref LL_TIM_CHANNEL_CH4
164 * @arg @ref LL_TIM_CHANNEL_CH5
165 * @arg @ref LL_TIM_CHANNEL_CH6
166 * @retval none
167 */
168 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
169 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
170 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
171 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
172 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
173 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
174 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
175 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
176 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
177
178 /** @brief Calculate the deadtime sampling period(in ps).
179 * @param __TIMCLK__ timer input clock frequency (in Hz).
180 * @param __CKD__ This parameter can be one of the following values:
181 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
182 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
183 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
184 * @retval none
185 */
186 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
187 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
188 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
189 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
190 /**
191 * @}
192 */
193
194
195 /* Exported types ------------------------------------------------------------*/
196 #if defined(USE_FULL_LL_DRIVER)
197 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
198 * @{
199 */
200
201 /**
202 * @brief TIM Time Base configuration structure definition.
203 */
204 typedef struct
205 {
206 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
207 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
208
209 This feature can be modified afterwards using unitary function
210 @ref LL_TIM_SetPrescaler().*/
211
212 uint32_t CounterMode; /*!< Specifies the counter mode.
213 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
214
215 This feature can be modified afterwards using unitary function
216 @ref LL_TIM_SetCounterMode().*/
217
218 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
219 Auto-Reload Register at the next update event.
220 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
221 Some timer instances may support 32 bits counters. In that case this parameter must
222 be a number between 0x0000 and 0xFFFFFFFF.
223
224 This feature can be modified afterwards using unitary function
225 @ref LL_TIM_SetAutoReload().*/
226
227 uint32_t ClockDivision; /*!< Specifies the clock division.
228 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
229
230 This feature can be modified afterwards using unitary function
231 @ref LL_TIM_SetClockDivision().*/
232
233 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
234 reaches zero, an update event is generated and counting restarts
235 from the RCR value (N).
236 This means in PWM mode that (N+1) corresponds to:
237 - the number of PWM periods in edge-aligned mode
238 - the number of half PWM period in center-aligned mode
239 GP timers: this parameter must be a number between Min_Data = 0x00 and
240 Max_Data = 0xFF.
241 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
242 Max_Data = 0xFFFF.
243
244 This feature can be modified afterwards using unitary function
245 @ref LL_TIM_SetRepetitionCounter().*/
246 } LL_TIM_InitTypeDef;
247
248 /**
249 * @brief TIM Output Compare configuration structure definition.
250 */
251 typedef struct
252 {
253 uint32_t OCMode; /*!< Specifies the output mode.
254 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
255
256 This feature can be modified afterwards using unitary function
257 @ref LL_TIM_OC_SetMode().*/
258
259 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
260 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
261
262 This feature can be modified afterwards using unitary functions
263 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
264
265 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
266 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
267
268 This feature can be modified afterwards using unitary functions
269 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
270
271 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
272 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
273
274 This feature can be modified afterwards using unitary function
275 LL_TIM_OC_SetCompareCHx (x=1..6).*/
276
277 uint32_t OCPolarity; /*!< Specifies the output polarity.
278 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
279
280 This feature can be modified afterwards using unitary function
281 @ref LL_TIM_OC_SetPolarity().*/
282
283 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
284 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
285
286 This feature can be modified afterwards using unitary function
287 @ref LL_TIM_OC_SetPolarity().*/
288
289
290 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
291 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
292
293 This feature can be modified afterwards using unitary function
294 @ref LL_TIM_OC_SetIdleState().*/
295
296 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
297 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
298
299 This feature can be modified afterwards using unitary function
300 @ref LL_TIM_OC_SetIdleState().*/
301 } LL_TIM_OC_InitTypeDef;
302
303 /**
304 * @brief TIM Input Capture configuration structure definition.
305 */
306
307 typedef struct
308 {
309
310 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
311 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
312
313 This feature can be modified afterwards using unitary function
314 @ref LL_TIM_IC_SetPolarity().*/
315
316 uint32_t ICActiveInput; /*!< Specifies the input.
317 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
318
319 This feature can be modified afterwards using unitary function
320 @ref LL_TIM_IC_SetActiveInput().*/
321
322 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
323 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
324
325 This feature can be modified afterwards using unitary function
326 @ref LL_TIM_IC_SetPrescaler().*/
327
328 uint32_t ICFilter; /*!< Specifies the input capture filter.
329 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
330
331 This feature can be modified afterwards using unitary function
332 @ref LL_TIM_IC_SetFilter().*/
333 } LL_TIM_IC_InitTypeDef;
334
335
336 /**
337 * @brief TIM Encoder interface configuration structure definition.
338 */
339 typedef struct
340 {
341 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
342 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
343
344 This feature can be modified afterwards using unitary function
345 @ref LL_TIM_SetEncoderMode().*/
346
347 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
348 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
349
350 This feature can be modified afterwards using unitary function
351 @ref LL_TIM_IC_SetPolarity().*/
352
353 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
354 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
355
356 This feature can be modified afterwards using unitary function
357 @ref LL_TIM_IC_SetActiveInput().*/
358
359 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
360 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
361
362 This feature can be modified afterwards using unitary function
363 @ref LL_TIM_IC_SetPrescaler().*/
364
365 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
366 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
367
368 This feature can be modified afterwards using unitary function
369 @ref LL_TIM_IC_SetFilter().*/
370
371 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
372 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
373
374 This feature can be modified afterwards using unitary function
375 @ref LL_TIM_IC_SetPolarity().*/
376
377 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
378 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
379
380 This feature can be modified afterwards using unitary function
381 @ref LL_TIM_IC_SetActiveInput().*/
382
383 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
384 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
385
386 This feature can be modified afterwards using unitary function
387 @ref LL_TIM_IC_SetPrescaler().*/
388
389 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
390 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
391
392 This feature can be modified afterwards using unitary function
393 @ref LL_TIM_IC_SetFilter().*/
394
395 } LL_TIM_ENCODER_InitTypeDef;
396
397 /**
398 * @brief TIM Hall sensor interface configuration structure definition.
399 */
400 typedef struct
401 {
402
403 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
404 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
405
406 This feature can be modified afterwards using unitary function
407 @ref LL_TIM_IC_SetPolarity().*/
408
409 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
410 Prescaler must be set to get a maximum counter period longer than the
411 time interval between 2 consecutive changes on the Hall inputs.
412 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
413
414 This feature can be modified afterwards using unitary function
415 @ref LL_TIM_IC_SetPrescaler().*/
416
417 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
418 This parameter can be a value of
419 @ref TIM_LL_EC_IC_FILTER.
420
421 This feature can be modified afterwards using unitary function
422 @ref LL_TIM_IC_SetFilter().*/
423
424 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
425 A positive pulse (TRGO event) is generated with a programmable delay every time
426 a change occurs on the Hall inputs.
427 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
428
429 This feature can be modified afterwards using unitary function
430 @ref LL_TIM_OC_SetCompareCH2().*/
431 } LL_TIM_HALLSENSOR_InitTypeDef;
432
433 /**
434 * @brief BDTR (Break and Dead Time) structure definition
435 */
436 typedef struct
437 {
438 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
439 This parameter can be a value of @ref TIM_LL_EC_OSSR
440
441 This feature can be modified afterwards using unitary function
442 @ref LL_TIM_SetOffStates()
443
444 @note This bit-field cannot be modified as long as LOCK level 2 has been
445 programmed. */
446
447 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
448 This parameter can be a value of @ref TIM_LL_EC_OSSI
449
450 This feature can be modified afterwards using unitary function
451 @ref LL_TIM_SetOffStates()
452
453 @note This bit-field cannot be modified as long as LOCK level 2 has been
454 programmed. */
455
456 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
457 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
458
459 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
460 register has been written, their content is frozen until the next reset.*/
461
462 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
463 switching-on of the outputs.
464 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
465
466 This feature can be modified afterwards using unitary function
467 @ref LL_TIM_OC_SetDeadTime()
468
469 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
470 programmed. */
471
472 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
473 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
474
475 This feature can be modified afterwards using unitary functions
476 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
477
478 @note This bit-field can not be modified as long as LOCK level 1 has been
479 programmed. */
480
481 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
482 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
483
484 This feature can be modified afterwards using unitary function
485 @ref LL_TIM_ConfigBRK()
486
487 @note This bit-field can not be modified as long as LOCK level 1 has been
488 programmed. */
489
490 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
491 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
492
493 This feature can be modified afterwards using unitary function
494 @ref LL_TIM_ConfigBRK()
495
496 @note This bit-field can not be modified as long as LOCK level 1 has been
497 programmed. */
498
499 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.
500 This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
501
502 This feature can be modified afterwards using unitary functions
503 @ref LL_TIM_ConfigBRK()
504
505 @note Bidirectional break input is only supported by advanced timers instances.
506
507 @note This bit-field can not be modified as long as LOCK level 1 has been
508 programmed. */
509
510 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
511 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
512
513 This feature can be modified afterwards using unitary functions
514 @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
515
516 @note This bit-field can not be modified as long as LOCK level 1 has been
517 programmed. */
518
519 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
520 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
521
522 This feature can be modified afterwards using unitary function
523 @ref LL_TIM_ConfigBRK2()
524
525 @note This bit-field can not be modified as long as LOCK level 1 has been
526 programmed. */
527
528 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
529 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
530
531 This feature can be modified afterwards using unitary function
532 @ref LL_TIM_ConfigBRK2()
533
534 @note This bit-field can not be modified as long as LOCK level 1 has been
535 programmed. */
536
537 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.
538 This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
539
540 This feature can be modified afterwards using unitary functions
541 @ref LL_TIM_ConfigBRK2()
542
543 @note Bidirectional break input is only supported by advanced timers instances.
544
545 @note This bit-field can not be modified as long as LOCK level 1 has been
546 programmed. */
547
548 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
549 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
550
551 This feature can be modified afterwards using unitary functions
552 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
553
554 @note This bit-field can not be modified as long as LOCK level 1 has been
555 programmed. */
556 } LL_TIM_BDTR_InitTypeDef;
557
558 /**
559 * @}
560 */
561 #endif /* USE_FULL_LL_DRIVER */
562
563 /* Exported constants --------------------------------------------------------*/
564 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
565 * @{
566 */
567
568 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
569 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
570 * @{
571 */
572 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
573 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
574 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
575 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
576 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
577 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
578 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
579 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
580 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
581 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
582 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
583 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
584 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
585 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
586 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
587 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
588 /**
589 * @}
590 */
591
592 #if defined(USE_FULL_LL_DRIVER)
593 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
594 * @{
595 */
596 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
597 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
598 /**
599 * @}
600 */
601
602 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
603 * @{
604 */
605 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
606 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
607 /**
608 * @}
609 */
610
611 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
612 * @{
613 */
614 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
615 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
616 /**
617 * @}
618 */
619 #endif /* USE_FULL_LL_DRIVER */
620
621 /** @defgroup TIM_LL_EC_IT IT Defines
622 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
623 * @{
624 */
625 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
626 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
627 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
628 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
629 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
630 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
631 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
632 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
633 /**
634 * @}
635 */
636
637 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
638 * @{
639 */
640 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
641 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
642 /**
643 * @}
644 */
645
646 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
647 * @{
648 */
649 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
650 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
651 /**
652 * @}
653 */
654
655 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
656 * @{
657 */
658 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
659 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
660 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
661 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
662 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
663 /**
664 * @}
665 */
666
667 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
668 * @{
669 */
670 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
671 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
672 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
673 /**
674 * @}
675 */
676
677 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
678 * @{
679 */
680 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
681 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
682 /**
683 * @}
684 */
685
686 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
687 * @{
688 */
689 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
690 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
691 /**
692 * @}
693 */
694
695 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
696 * @{
697 */
698 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
699 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
700 /**
701 * @}
702 */
703
704 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
705 * @{
706 */
707 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
708 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
709 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
710 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
711 /**
712 * @}
713 */
714
715 /** @defgroup TIM_LL_EC_CHANNEL Channel
716 * @{
717 */
718 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
719 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
720 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
721 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
722 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
723 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
724 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
725 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
726 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
727 /**
728 * @}
729 */
730
731 #if defined(USE_FULL_LL_DRIVER)
732 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
733 * @{
734 */
735 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
736 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
737 /**
738 * @}
739 */
740 #endif /* USE_FULL_LL_DRIVER */
741
742 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
743 * @{
744 */
745 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
746 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
747 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
748 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
749 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
750 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
751 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
752 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
753 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
754 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
755 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
756 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
757 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
758 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
759 /**
760 * @}
761 */
762
763 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
764 * @{
765 */
766 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
767 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
768 /**
769 * @}
770 */
771
772 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
773 * @{
774 */
775 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
776 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
777 /**
778 * @}
779 */
780
781 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
782 * @{
783 */
784 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
785 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
786 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
787 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
788 /**
789 * @}
790 */
791
792 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
793 * @{
794 */
795 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
796 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
797 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
798 /**
799 * @}
800 */
801
802 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
803 * @{
804 */
805 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
806 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
807 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
808 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
809 /**
810 * @}
811 */
812
813 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
814 * @{
815 */
816 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
817 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
818 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
819 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
820 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
821 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
822 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
823 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
824 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
825 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
826 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
827 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
828 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
829 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
830 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
831 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
832 /**
833 * @}
834 */
835
836 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
837 * @{
838 */
839 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
840 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
841 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
842 /**
843 * @}
844 */
845
846 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
847 * @{
848 */
849 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
850 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
851 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
852 /**
853 * @}
854 */
855
856 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
857 * @{
858 */
859 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
860 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
861 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
862 /**
863 * @}
864 */
865
866 /** @defgroup TIM_LL_EC_TRGO Trigger Output
867 * @{
868 */
869 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
870 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
871 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
872 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
873 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
874 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
875 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
876 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
877 /**
878 * @}
879 */
880
881 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
882 * @{
883 */
884 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
885 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
886 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
887 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
888 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
889 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
890 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
891 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
892 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
893 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
894 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
895 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
896 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
897 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
898 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
899 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
900 /**
901 * @}
902 */
903
904 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
905 * @{
906 */
907 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
908 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
909 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
910 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
911 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
912 /**
913 * @}
914 */
915
916 /** @defgroup TIM_LL_EC_TS Trigger Selection
917 * @{
918 */
919 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
920 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
921 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
922 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
923 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
924 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
925 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
926 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
927 /**
928 * @}
929 */
930
931 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
932 * @{
933 */
934 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
935 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
936 /**
937 * @}
938 */
939
940 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
941 * @{
942 */
943 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
944 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
945 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
946 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
947 /**
948 * @}
949 */
950
951 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
952 * @{
953 */
954 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
955 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
956 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
957 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
958 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
959 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
960 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
961 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
962 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */
963 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
964 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
965 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
966 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
967 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
968 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
969 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
970 /**
971 * @}
972 */
973
974 /** @defgroup TIM_LL_EC_ETRSOURCE External Trigger Source
975 * @{
976 */
977 #define LL_TIM_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
978 #define LL_TIM_ETRSOURCE_ADC1_AWD1 (TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< ETR input is connected to ADC1 analog watchdog 1 */
979 #define LL_TIM_ETRSOURCE_ADC1_AWD2 TIM_AF1_ETRSEL_2 /*!< ETR input is connected to ADC1 analog watchdog 2 */
980 #define LL_TIM_ETRSOURCE_ADC1_AWD3 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< ETR input is connected to ADC1 analog watchdog 3 */
981 #if defined(TIM2)
982 #define LL_TIM_ETRSOURCE_LSE (TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< ETR input is connected to LSE */
983 #define LL_TIM_ETRSOURCE_MCO TIM_AF1_ETRSEL_2 /*!< ETR input is connected to MCO */
984 #define LL_TIM_ETRSOURCE_MCO2 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< ETR input is connected to MCO2 */
985 #endif /* TIM2 */
986 /**
987 * @}
988 */
989
990 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
991 * @{
992 */
993 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
994 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
995 /**
996 * @}
997 */
998
999 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
1000 * @{
1001 */
1002 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1003 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
1004 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
1005 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
1006 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
1007 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
1008 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
1009 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
1010 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
1011 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
1012 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
1013 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
1014 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
1015 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
1016 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
1017 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
1018 /**
1019 * @}
1020 */
1021
1022 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
1023 * @{
1024 */
1025 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
1026 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
1027 /**
1028 * @}
1029 */
1030
1031 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
1032 * @{
1033 */
1034 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1035 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
1036 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
1037 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
1038 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
1039 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
1040 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
1041 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1042 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1043 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1044 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1045 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1046 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1047 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1048 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1049 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1050 /**
1051 * @}
1052 */
1053
1054 /** @defgroup TIM_LL_EC_OSSI OSSI
1055 * @{
1056 */
1057 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1058 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1059 /**
1060 * @}
1061 */
1062
1063 /** @defgroup TIM_LL_EC_OSSR OSSR
1064 * @{
1065 */
1066 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1067 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1068 /**
1069 * @}
1070 */
1071
1072 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1073 * @{
1074 */
1075 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1076 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1077 /**
1078 * @}
1079 */
1080
1081 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1082 * @{
1083 */
1084 #define LL_TIM_BKIN_SOURCE_BKIN TIM_AF1_BKINE /*!< BKIN input from AF controller */
1085 /**
1086 * @}
1087 */
1088
1089 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1090 * @{
1091 */
1092 #define LL_TIM_BKIN_POLARITY_LOW TIM_AF1_BKINP /*!< BRK BKIN input is active low */
1093 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1094 /**
1095 * @}
1096 */
1097
1098 /** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
1099 * @{
1100 */
1101 #define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
1102 #define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
1103 /**
1104 * @}
1105 */
1106
1107 /** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
1108 * @{
1109 */
1110 #define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */
1111 #define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
1112 /**
1113 * @}
1114 */
1115
1116 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1117 * @{
1118 */
1119 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1120 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1121 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1122 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1123 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1124 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1125 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1126 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1127 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1128 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1129 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1130 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1131 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1132 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1133 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1134 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1135 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1136 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1137 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1138 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1139 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1140 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
1141 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
1142 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_TISEL register is the DMA base address for DMA burst */
1143 /**
1144 * @}
1145 */
1146
1147 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1148 * @{
1149 */
1150 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1151 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1152 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1153 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1154 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1155 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1156 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1157 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1158 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1159 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1160 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1161 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1162 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1163 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1164 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1165 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1166 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1167 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1168 /**
1169 * @}
1170 */
1171
1172 /** @defgroup TIM_LL_EC_TIM14_TI1_RMP TIM14 Timer Input Ch1 Remap
1173 * @{
1174 */
1175 #define LL_TIM_TIM14_TI1_RMP_GPIO 0x00000000U /*!< TIM14 input 1 is connected to GPIO */
1176 #define LL_TIM_TIM14_TI1_RMP_RTC_CLK TIM_TISEL_TI1SEL_0 /*!< TIM14 input 1 is connected to RTC clock */
1177 #define LL_TIM_TIM14_TI1_RMP_HSE_32 TIM_TISEL_TI1SEL_1 /*!< TIM14 input 1 is connected to HSE/32 clock */
1178 #define LL_TIM_TIM14_TI1_RMP_MCO (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM14 input 1 is connected to MCO */
1179 #define LL_TIM_TIM14_TI1_RMP_MCO2 TIM_TISEL_TI1SEL_2 /*!< TIM14 input 1 is connected to MCO2 */
1180 /**
1181 * @}
1182 */
1183
1184 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 Timer Input Ch1 Remap
1185 * @{
1186 */
1187 #define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U /*!< TIM16 input 1 is connected to GPIO */
1188 #define LL_TIM_TIM16_TI1_RMP_LSI TIM_TISEL_TI1SEL_0 /*!< TIM16 input 1 is connected to LSI */
1189 #define LL_TIM_TIM16_TI1_RMP_LSE TIM_TISEL_TI1SEL_1 /*!< TIM16 input 1 is connected to LSE */
1190 #define LL_TIM_TIM16_TI1_RMP_MCO2 TIM_TISEL_TI1SEL_2 /*!< TIM16 input 1 is connected to MCO2 */
1191 /**
1192 * @}
1193 */
1194
1195 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap
1196 * @{
1197 */
1198 #define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000U /*!< TIM17 input 1 is connected to GPIO */
1199 #define LL_TIM_TIM17_TI1_RMP_HSE_32 TIM_TISEL_TI1SEL_1 /*!< TIM17 input 1 is connected to HSE/32 clock */
1200 #define LL_TIM_TIM17_TI1_RMP_MCO (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM17 input 1 is connected to MCO */
1201 #define LL_TIM_TIM17_TI1_RMP_MCO2 TIM_TISEL_TI1SEL_2 /*!< TIM17 input 1 is connected to MCO2 */
1202 /**
1203 * @}
1204 */
1205
1206 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
1207 * @{
1208 */
1209 #define LL_TIM_OCREF_CLR_INT_ETR OCREF_CLEAR_SELECT_MSK /*!< OCREF_CLR_INT is connected to ETRF */
1210 /**
1211 * @}
1212 */
1213
1214 /** Legacy definitions for compatibility purpose
1215 @cond 0
1216 */
1217 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
1218 /**
1219 @endcond
1220 */
1221
1222 /**
1223 * @}
1224 */
1225
1226 /* Exported macro ------------------------------------------------------------*/
1227 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1228 * @{
1229 */
1230
1231 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1232 * @{
1233 */
1234 /**
1235 * @brief Write a value in TIM register.
1236 * @param __INSTANCE__ TIM Instance
1237 * @param __REG__ Register to be written
1238 * @param __VALUE__ Value to be written in the register
1239 * @retval None
1240 */
1241 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1242
1243 /**
1244 * @brief Read a value in TIM register.
1245 * @param __INSTANCE__ TIM Instance
1246 * @param __REG__ Register to be read
1247 * @retval Register value
1248 */
1249 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1250 /**
1251 * @}
1252 */
1253
1254 /**
1255 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1256 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1257 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1258 * to TIMx_CNT register bit 31)
1259 * @param __CNT__ Counter value
1260 * @retval UIF status bit
1261 */
1262 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1263 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1264
1265 /**
1266 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1267 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1268 * @param __TIMCLK__ timer input clock frequency (in Hz)
1269 * @param __CKD__ This parameter can be one of the following values:
1270 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1271 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1272 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1273 * @param __DT__ deadtime duration (in ns)
1274 * @retval DTG[0:7]
1275 */
1276 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1277 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1278 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1279 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1280 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1281 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1282 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1283 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1284 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1285 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1286 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1287 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1288 0U)
1289
1290 /**
1291 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1292 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1293 * @param __TIMCLK__ timer input clock frequency (in Hz)
1294 * @param __CNTCLK__ counter clock frequency (in Hz)
1295 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1296 */
1297 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1298 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
1299
1300 /**
1301 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1302 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1303 * @param __TIMCLK__ timer input clock frequency (in Hz)
1304 * @param __PSC__ prescaler
1305 * @param __FREQ__ output signal frequency (in Hz)
1306 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1307 */
1308 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1309 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1310
1311 /**
1312 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1313 * active/inactive delay.
1314 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1315 * @param __TIMCLK__ timer input clock frequency (in Hz)
1316 * @param __PSC__ prescaler
1317 * @param __DELAY__ timer output compare active/inactive delay (in us)
1318 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1319 */
1320 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1321 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1322 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1323
1324 /**
1325 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1326 * (when the timer operates in one pulse mode).
1327 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1328 * @param __TIMCLK__ timer input clock frequency (in Hz)
1329 * @param __PSC__ prescaler
1330 * @param __DELAY__ timer output compare active/inactive delay (in us)
1331 * @param __PULSE__ pulse duration (in us)
1332 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1333 */
1334 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1335 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1336 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1337
1338 /**
1339 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1340 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1341 * @param __ICPSC__ This parameter can be one of the following values:
1342 * @arg @ref LL_TIM_ICPSC_DIV1
1343 * @arg @ref LL_TIM_ICPSC_DIV2
1344 * @arg @ref LL_TIM_ICPSC_DIV4
1345 * @arg @ref LL_TIM_ICPSC_DIV8
1346 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1347 */
1348 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1349 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1350
1351
1352 /**
1353 * @}
1354 */
1355
1356 /* Exported functions --------------------------------------------------------*/
1357 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1358 * @{
1359 */
1360
1361 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1362 * @{
1363 */
1364 /**
1365 * @brief Enable timer counter.
1366 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1367 * @param TIMx Timer instance
1368 * @retval None
1369 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1370 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1371 {
1372 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1373 }
1374
1375 /**
1376 * @brief Disable timer counter.
1377 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1378 * @param TIMx Timer instance
1379 * @retval None
1380 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1381 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1382 {
1383 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1384 }
1385
1386 /**
1387 * @brief Indicates whether the timer counter is enabled.
1388 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1389 * @param TIMx Timer instance
1390 * @retval State of bit (1 or 0).
1391 */
LL_TIM_IsEnabledCounter(const TIM_TypeDef * TIMx)1392 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
1393 {
1394 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1395 }
1396
1397 /**
1398 * @brief Enable update event generation.
1399 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1400 * @param TIMx Timer instance
1401 * @retval None
1402 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1403 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1404 {
1405 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1406 }
1407
1408 /**
1409 * @brief Disable update event generation.
1410 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1411 * @param TIMx Timer instance
1412 * @retval None
1413 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1414 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1415 {
1416 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1417 }
1418
1419 /**
1420 * @brief Indicates whether update event generation is enabled.
1421 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1422 * @param TIMx Timer instance
1423 * @retval Inverted state of bit (0 or 1).
1424 */
LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef * TIMx)1425 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
1426 {
1427 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1428 }
1429
1430 /**
1431 * @brief Set update event source
1432 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1433 * generate an update interrupt or DMA request if enabled:
1434 * - Counter overflow/underflow
1435 * - Setting the UG bit
1436 * - Update generation through the slave mode controller
1437 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1438 * overflow/underflow generates an update interrupt or DMA request if enabled.
1439 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1440 * @param TIMx Timer instance
1441 * @param UpdateSource This parameter can be one of the following values:
1442 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1443 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1444 * @retval None
1445 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1446 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1447 {
1448 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1449 }
1450
1451 /**
1452 * @brief Get actual event update source
1453 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1454 * @param TIMx Timer instance
1455 * @retval Returned value can be one of the following values:
1456 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1457 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1458 */
LL_TIM_GetUpdateSource(const TIM_TypeDef * TIMx)1459 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
1460 {
1461 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1462 }
1463
1464 /**
1465 * @brief Set one pulse mode (one shot v.s. repetitive).
1466 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1467 * @param TIMx Timer instance
1468 * @param OnePulseMode This parameter can be one of the following values:
1469 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1470 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1471 * @retval None
1472 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1473 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1474 {
1475 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1476 }
1477
1478 /**
1479 * @brief Get actual one pulse mode.
1480 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1481 * @param TIMx Timer instance
1482 * @retval Returned value can be one of the following values:
1483 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1484 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1485 */
LL_TIM_GetOnePulseMode(const TIM_TypeDef * TIMx)1486 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
1487 {
1488 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1489 }
1490
1491 /**
1492 * @brief Set the timer counter counting mode.
1493 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1494 * check whether or not the counter mode selection feature is supported
1495 * by a timer instance.
1496 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1497 * requires a timer reset to avoid unexpected direction
1498 * due to DIR bit readonly in center aligned mode.
1499 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1500 * CR1 CMS LL_TIM_SetCounterMode
1501 * @param TIMx Timer instance
1502 * @param CounterMode This parameter can be one of the following values:
1503 * @arg @ref LL_TIM_COUNTERMODE_UP
1504 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1505 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1506 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1507 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1508 * @retval None
1509 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1510 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1511 {
1512 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1513 }
1514
1515 /**
1516 * @brief Get actual counter mode.
1517 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1518 * check whether or not the counter mode selection feature is supported
1519 * by a timer instance.
1520 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1521 * CR1 CMS LL_TIM_GetCounterMode
1522 * @param TIMx Timer instance
1523 * @retval Returned value can be one of the following values:
1524 * @arg @ref LL_TIM_COUNTERMODE_UP
1525 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1526 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1527 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1528 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1529 */
LL_TIM_GetCounterMode(const TIM_TypeDef * TIMx)1530 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
1531 {
1532 uint32_t counter_mode;
1533
1534 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1535
1536 if (counter_mode == 0U)
1537 {
1538 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1539 }
1540
1541 return counter_mode;
1542 }
1543
1544 /**
1545 * @brief Enable auto-reload (ARR) preload.
1546 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1547 * @param TIMx Timer instance
1548 * @retval None
1549 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1550 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1551 {
1552 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1553 }
1554
1555 /**
1556 * @brief Disable auto-reload (ARR) preload.
1557 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1558 * @param TIMx Timer instance
1559 * @retval None
1560 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1561 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1562 {
1563 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1564 }
1565
1566 /**
1567 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1568 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1569 * @param TIMx Timer instance
1570 * @retval State of bit (1 or 0).
1571 */
LL_TIM_IsEnabledARRPreload(const TIM_TypeDef * TIMx)1572 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
1573 {
1574 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1575 }
1576
1577 /**
1578 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
1579 * (when supported) and the digital filters.
1580 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1581 * whether or not the clock division feature is supported by the timer
1582 * instance.
1583 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1584 * @param TIMx Timer instance
1585 * @param ClockDivision This parameter can be one of the following values:
1586 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1587 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1588 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1589 * @retval None
1590 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1591 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1592 {
1593 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1594 }
1595
1596 /**
1597 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
1598 * generators (when supported) and the digital filters.
1599 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1600 * whether or not the clock division feature is supported by the timer
1601 * instance.
1602 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1603 * @param TIMx Timer instance
1604 * @retval Returned value can be one of the following values:
1605 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1606 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1607 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1608 */
LL_TIM_GetClockDivision(const TIM_TypeDef * TIMx)1609 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
1610 {
1611 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1612 }
1613
1614 /**
1615 * @brief Set the counter value.
1616 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1617 * whether or not a timer instance supports a 32 bits counter.
1618 * @rmtoll CNT CNT LL_TIM_SetCounter
1619 * @param TIMx Timer instance
1620 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1621 * @retval None
1622 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1623 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1624 {
1625 WRITE_REG(TIMx->CNT, Counter);
1626 }
1627
1628 /**
1629 * @brief Get the counter value.
1630 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1631 * whether or not a timer instance supports a 32 bits counter.
1632 * @rmtoll CNT CNT LL_TIM_GetCounter
1633 * @param TIMx Timer instance
1634 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1635 */
LL_TIM_GetCounter(const TIM_TypeDef * TIMx)1636 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
1637 {
1638 return (uint32_t)(READ_REG(TIMx->CNT));
1639 }
1640
1641 /**
1642 * @brief Get the current direction of the counter
1643 * @rmtoll CR1 DIR LL_TIM_GetDirection
1644 * @param TIMx Timer instance
1645 * @retval Returned value can be one of the following values:
1646 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1647 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1648 */
LL_TIM_GetDirection(const TIM_TypeDef * TIMx)1649 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
1650 {
1651 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1652 }
1653
1654 /**
1655 * @brief Set the prescaler value.
1656 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1657 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1658 * prescaler ratio is taken into account at the next update event.
1659 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1660 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1661 * @param TIMx Timer instance
1662 * @param Prescaler between Min_Data=0 and Max_Data=65535
1663 * @retval None
1664 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1665 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1666 {
1667 WRITE_REG(TIMx->PSC, Prescaler);
1668 }
1669
1670 /**
1671 * @brief Get the prescaler value.
1672 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1673 * @param TIMx Timer instance
1674 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1675 */
LL_TIM_GetPrescaler(const TIM_TypeDef * TIMx)1676 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
1677 {
1678 return (uint32_t)(READ_REG(TIMx->PSC));
1679 }
1680
1681 /**
1682 * @brief Set the auto-reload value.
1683 * @note The counter is blocked while the auto-reload value is null.
1684 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1685 * whether or not a timer instance supports a 32 bits counter.
1686 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1687 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1688 * @param TIMx Timer instance
1689 * @param AutoReload between Min_Data=0 and Max_Data=65535
1690 * @retval None
1691 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1692 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1693 {
1694 WRITE_REG(TIMx->ARR, AutoReload);
1695 }
1696
1697 /**
1698 * @brief Get the auto-reload value.
1699 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1700 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1701 * whether or not a timer instance supports a 32 bits counter.
1702 * @param TIMx Timer instance
1703 * @retval Auto-reload value
1704 */
LL_TIM_GetAutoReload(const TIM_TypeDef * TIMx)1705 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
1706 {
1707 return (uint32_t)(READ_REG(TIMx->ARR));
1708 }
1709
1710 /**
1711 * @brief Set the repetition counter value.
1712 * @note For advanced timer instances RepetitionCounter can be up to 65535.
1713 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1714 * whether or not a timer instance supports a repetition counter.
1715 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1716 * @param TIMx Timer instance
1717 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
1718 * @retval None
1719 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)1720 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1721 {
1722 WRITE_REG(TIMx->RCR, RepetitionCounter);
1723 }
1724
1725 /**
1726 * @brief Get the repetition counter value.
1727 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1728 * whether or not a timer instance supports a repetition counter.
1729 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1730 * @param TIMx Timer instance
1731 * @retval Repetition counter value
1732 */
LL_TIM_GetRepetitionCounter(const TIM_TypeDef * TIMx)1733 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
1734 {
1735 return (uint32_t)(READ_REG(TIMx->RCR));
1736 }
1737
1738 /**
1739 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
1740 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
1741 * in an atomic way.
1742 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
1743 * @param TIMx Timer instance
1744 * @retval None
1745 */
LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)1746 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
1747 {
1748 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1749 }
1750
1751 /**
1752 * @brief Disable update interrupt flag (UIF) remapping.
1753 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
1754 * @param TIMx Timer instance
1755 * @retval None
1756 */
LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)1757 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
1758 {
1759 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1760 }
1761
1762 /**
1763 * @brief Indicate whether update interrupt flag (UIF) copy is set.
1764 * @param Counter Counter value
1765 * @retval State of bit (1 or 0).
1766 */
LL_TIM_IsActiveUIFCPY(const uint32_t Counter)1767 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
1768 {
1769 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
1770 }
1771
1772 /**
1773 * @}
1774 */
1775
1776 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1777 * @{
1778 */
1779 /**
1780 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1781 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1782 * they are updated only when a commutation event (COM) occurs.
1783 * @note Only on channels that have a complementary output.
1784 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1785 * whether or not a timer instance is able to generate a commutation event.
1786 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1787 * @param TIMx Timer instance
1788 * @retval None
1789 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)1790 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1791 {
1792 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1793 }
1794
1795 /**
1796 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1797 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1798 * whether or not a timer instance is able to generate a commutation event.
1799 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1800 * @param TIMx Timer instance
1801 * @retval None
1802 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)1803 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1804 {
1805 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1806 }
1807
1808 /**
1809 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1810 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1811 * whether or not a timer instance is able to generate a commutation event.
1812 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1813 * @param TIMx Timer instance
1814 * @param CCUpdateSource This parameter can be one of the following values:
1815 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1816 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1817 * @retval None
1818 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)1819 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1820 {
1821 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1822 }
1823
1824 /**
1825 * @brief Set the trigger of the capture/compare DMA request.
1826 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1827 * @param TIMx Timer instance
1828 * @param DMAReqTrigger This parameter can be one of the following values:
1829 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1830 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1831 * @retval None
1832 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)1833 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1834 {
1835 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1836 }
1837
1838 /**
1839 * @brief Get actual trigger of the capture/compare DMA request.
1840 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1841 * @param TIMx Timer instance
1842 * @retval Returned value can be one of the following values:
1843 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1844 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1845 */
LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef * TIMx)1846 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
1847 {
1848 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1849 }
1850
1851 /**
1852 * @brief Set the lock level to freeze the
1853 * configuration of several capture/compare parameters.
1854 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1855 * the lock mechanism is supported by a timer instance.
1856 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
1857 * @param TIMx Timer instance
1858 * @param LockLevel This parameter can be one of the following values:
1859 * @arg @ref LL_TIM_LOCKLEVEL_OFF
1860 * @arg @ref LL_TIM_LOCKLEVEL_1
1861 * @arg @ref LL_TIM_LOCKLEVEL_2
1862 * @arg @ref LL_TIM_LOCKLEVEL_3
1863 * @retval None
1864 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)1865 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
1866 {
1867 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
1868 }
1869
1870 /**
1871 * @brief Enable capture/compare channels.
1872 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1873 * CCER CC1NE LL_TIM_CC_EnableChannel\n
1874 * CCER CC2E LL_TIM_CC_EnableChannel\n
1875 * CCER CC2NE LL_TIM_CC_EnableChannel\n
1876 * CCER CC3E LL_TIM_CC_EnableChannel\n
1877 * CCER CC3NE LL_TIM_CC_EnableChannel\n
1878 * CCER CC4E LL_TIM_CC_EnableChannel\n
1879 * CCER CC5E LL_TIM_CC_EnableChannel\n
1880 * CCER CC6E LL_TIM_CC_EnableChannel
1881 * @param TIMx Timer instance
1882 * @param Channels This parameter can be a combination of the following values:
1883 * @arg @ref LL_TIM_CHANNEL_CH1
1884 * @arg @ref LL_TIM_CHANNEL_CH1N
1885 * @arg @ref LL_TIM_CHANNEL_CH2
1886 * @arg @ref LL_TIM_CHANNEL_CH2N
1887 * @arg @ref LL_TIM_CHANNEL_CH3
1888 * @arg @ref LL_TIM_CHANNEL_CH3N
1889 * @arg @ref LL_TIM_CHANNEL_CH4
1890 * @arg @ref LL_TIM_CHANNEL_CH5
1891 * @arg @ref LL_TIM_CHANNEL_CH6
1892 * @retval None
1893 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1894 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1895 {
1896 SET_BIT(TIMx->CCER, Channels);
1897 }
1898
1899 /**
1900 * @brief Disable capture/compare channels.
1901 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
1902 * CCER CC1NE LL_TIM_CC_DisableChannel\n
1903 * CCER CC2E LL_TIM_CC_DisableChannel\n
1904 * CCER CC2NE LL_TIM_CC_DisableChannel\n
1905 * CCER CC3E LL_TIM_CC_DisableChannel\n
1906 * CCER CC3NE LL_TIM_CC_DisableChannel\n
1907 * CCER CC4E LL_TIM_CC_DisableChannel\n
1908 * CCER CC5E LL_TIM_CC_DisableChannel\n
1909 * CCER CC6E LL_TIM_CC_DisableChannel
1910 * @param TIMx Timer instance
1911 * @param Channels This parameter can be a combination of the following values:
1912 * @arg @ref LL_TIM_CHANNEL_CH1
1913 * @arg @ref LL_TIM_CHANNEL_CH1N
1914 * @arg @ref LL_TIM_CHANNEL_CH2
1915 * @arg @ref LL_TIM_CHANNEL_CH2N
1916 * @arg @ref LL_TIM_CHANNEL_CH3
1917 * @arg @ref LL_TIM_CHANNEL_CH3N
1918 * @arg @ref LL_TIM_CHANNEL_CH4
1919 * @arg @ref LL_TIM_CHANNEL_CH5
1920 * @arg @ref LL_TIM_CHANNEL_CH6
1921 * @retval None
1922 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1923 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1924 {
1925 CLEAR_BIT(TIMx->CCER, Channels);
1926 }
1927
1928 /**
1929 * @brief Indicate whether channel(s) is(are) enabled.
1930 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
1931 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
1932 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
1933 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
1934 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
1935 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
1936 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
1937 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
1938 * CCER CC6E LL_TIM_CC_IsEnabledChannel
1939 * @param TIMx Timer instance
1940 * @param Channels This parameter can be a combination of the following values:
1941 * @arg @ref LL_TIM_CHANNEL_CH1
1942 * @arg @ref LL_TIM_CHANNEL_CH1N
1943 * @arg @ref LL_TIM_CHANNEL_CH2
1944 * @arg @ref LL_TIM_CHANNEL_CH2N
1945 * @arg @ref LL_TIM_CHANNEL_CH3
1946 * @arg @ref LL_TIM_CHANNEL_CH3N
1947 * @arg @ref LL_TIM_CHANNEL_CH4
1948 * @arg @ref LL_TIM_CHANNEL_CH5
1949 * @arg @ref LL_TIM_CHANNEL_CH6
1950 * @retval State of bit (1 or 0).
1951 */
LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef * TIMx,uint32_t Channels)1952 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
1953 {
1954 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
1955 }
1956
1957 /**
1958 * @}
1959 */
1960
1961 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
1962 * @{
1963 */
1964 /**
1965 * @brief Configure an output channel.
1966 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
1967 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
1968 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
1969 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
1970 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
1971 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
1972 * CCER CC1P LL_TIM_OC_ConfigOutput\n
1973 * CCER CC2P LL_TIM_OC_ConfigOutput\n
1974 * CCER CC3P LL_TIM_OC_ConfigOutput\n
1975 * CCER CC4P LL_TIM_OC_ConfigOutput\n
1976 * CCER CC5P LL_TIM_OC_ConfigOutput\n
1977 * CCER CC6P LL_TIM_OC_ConfigOutput\n
1978 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
1979 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
1980 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
1981 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
1982 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
1983 * CR2 OIS6 LL_TIM_OC_ConfigOutput
1984 * @param TIMx Timer instance
1985 * @param Channel This parameter can be one of the following values:
1986 * @arg @ref LL_TIM_CHANNEL_CH1
1987 * @arg @ref LL_TIM_CHANNEL_CH2
1988 * @arg @ref LL_TIM_CHANNEL_CH3
1989 * @arg @ref LL_TIM_CHANNEL_CH4
1990 * @arg @ref LL_TIM_CHANNEL_CH5
1991 * @arg @ref LL_TIM_CHANNEL_CH6
1992 * @param Configuration This parameter must be a combination of all the following values:
1993 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
1994 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
1995 * @retval None
1996 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)1997 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
1998 {
1999 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2000 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2001 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
2002 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
2003 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
2004 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
2005 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
2006 }
2007
2008 /**
2009 * @brief Define the behavior of the output reference signal OCxREF from which
2010 * OCx and OCxN (when relevant) are derived.
2011 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
2012 * CCMR1 OC2M LL_TIM_OC_SetMode\n
2013 * CCMR2 OC3M LL_TIM_OC_SetMode\n
2014 * CCMR2 OC4M LL_TIM_OC_SetMode\n
2015 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2016 * CCMR3 OC6M LL_TIM_OC_SetMode
2017 * @param TIMx Timer instance
2018 * @param Channel This parameter can be one of the following values:
2019 * @arg @ref LL_TIM_CHANNEL_CH1
2020 * @arg @ref LL_TIM_CHANNEL_CH2
2021 * @arg @ref LL_TIM_CHANNEL_CH3
2022 * @arg @ref LL_TIM_CHANNEL_CH4
2023 * @arg @ref LL_TIM_CHANNEL_CH5
2024 * @arg @ref LL_TIM_CHANNEL_CH6
2025 * @param Mode This parameter can be one of the following values:
2026 * @arg @ref LL_TIM_OCMODE_FROZEN
2027 * @arg @ref LL_TIM_OCMODE_ACTIVE
2028 * @arg @ref LL_TIM_OCMODE_INACTIVE
2029 * @arg @ref LL_TIM_OCMODE_TOGGLE
2030 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2031 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2032 * @arg @ref LL_TIM_OCMODE_PWM1
2033 * @arg @ref LL_TIM_OCMODE_PWM2
2034 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2035 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2036 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2037 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2038 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2039 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2040 * @retval None
2041 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)2042 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2043 {
2044 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2045 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2046 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2047 }
2048
2049 /**
2050 * @brief Get the output compare mode of an output channel.
2051 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2052 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2053 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2054 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2055 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2056 * CCMR3 OC6M LL_TIM_OC_GetMode
2057 * @param TIMx Timer instance
2058 * @param Channel This parameter can be one of the following values:
2059 * @arg @ref LL_TIM_CHANNEL_CH1
2060 * @arg @ref LL_TIM_CHANNEL_CH2
2061 * @arg @ref LL_TIM_CHANNEL_CH3
2062 * @arg @ref LL_TIM_CHANNEL_CH4
2063 * @arg @ref LL_TIM_CHANNEL_CH5
2064 * @arg @ref LL_TIM_CHANNEL_CH6
2065 * @retval Returned value can be one of the following values:
2066 * @arg @ref LL_TIM_OCMODE_FROZEN
2067 * @arg @ref LL_TIM_OCMODE_ACTIVE
2068 * @arg @ref LL_TIM_OCMODE_INACTIVE
2069 * @arg @ref LL_TIM_OCMODE_TOGGLE
2070 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2071 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2072 * @arg @ref LL_TIM_OCMODE_PWM1
2073 * @arg @ref LL_TIM_OCMODE_PWM2
2074 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2075 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2076 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2077 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2078 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2079 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2080 */
LL_TIM_OC_GetMode(const TIM_TypeDef * TIMx,uint32_t Channel)2081 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
2082 {
2083 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2084 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2085 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2086 }
2087
2088 /**
2089 * @brief Set the polarity of an output channel.
2090 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2091 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2092 * CCER CC2P LL_TIM_OC_SetPolarity\n
2093 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2094 * CCER CC3P LL_TIM_OC_SetPolarity\n
2095 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2096 * CCER CC4P LL_TIM_OC_SetPolarity\n
2097 * CCER CC5P LL_TIM_OC_SetPolarity\n
2098 * CCER CC6P LL_TIM_OC_SetPolarity
2099 * @param TIMx Timer instance
2100 * @param Channel This parameter can be one of the following values:
2101 * @arg @ref LL_TIM_CHANNEL_CH1
2102 * @arg @ref LL_TIM_CHANNEL_CH1N
2103 * @arg @ref LL_TIM_CHANNEL_CH2
2104 * @arg @ref LL_TIM_CHANNEL_CH2N
2105 * @arg @ref LL_TIM_CHANNEL_CH3
2106 * @arg @ref LL_TIM_CHANNEL_CH3N
2107 * @arg @ref LL_TIM_CHANNEL_CH4
2108 * @arg @ref LL_TIM_CHANNEL_CH5
2109 * @arg @ref LL_TIM_CHANNEL_CH6
2110 * @param Polarity This parameter can be one of the following values:
2111 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2112 * @arg @ref LL_TIM_OCPOLARITY_LOW
2113 * @retval None
2114 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)2115 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2116 {
2117 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2118 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2119 }
2120
2121 /**
2122 * @brief Get the polarity of an output channel.
2123 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2124 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2125 * CCER CC2P LL_TIM_OC_GetPolarity\n
2126 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2127 * CCER CC3P LL_TIM_OC_GetPolarity\n
2128 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2129 * CCER CC4P LL_TIM_OC_GetPolarity\n
2130 * CCER CC5P LL_TIM_OC_GetPolarity\n
2131 * CCER CC6P LL_TIM_OC_GetPolarity
2132 * @param TIMx Timer instance
2133 * @param Channel This parameter can be one of the following values:
2134 * @arg @ref LL_TIM_CHANNEL_CH1
2135 * @arg @ref LL_TIM_CHANNEL_CH1N
2136 * @arg @ref LL_TIM_CHANNEL_CH2
2137 * @arg @ref LL_TIM_CHANNEL_CH2N
2138 * @arg @ref LL_TIM_CHANNEL_CH3
2139 * @arg @ref LL_TIM_CHANNEL_CH3N
2140 * @arg @ref LL_TIM_CHANNEL_CH4
2141 * @arg @ref LL_TIM_CHANNEL_CH5
2142 * @arg @ref LL_TIM_CHANNEL_CH6
2143 * @retval Returned value can be one of the following values:
2144 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2145 * @arg @ref LL_TIM_OCPOLARITY_LOW
2146 */
LL_TIM_OC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2147 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2148 {
2149 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2150 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2151 }
2152
2153 /**
2154 * @brief Set the IDLE state of an output channel
2155 * @note This function is significant only for the timer instances
2156 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2157 * can be used to check whether or not a timer instance provides
2158 * a break input.
2159 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2160 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2161 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2162 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2163 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2164 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2165 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2166 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2167 * CR2 OIS6 LL_TIM_OC_SetIdleState
2168 * @param TIMx Timer instance
2169 * @param Channel This parameter can be one of the following values:
2170 * @arg @ref LL_TIM_CHANNEL_CH1
2171 * @arg @ref LL_TIM_CHANNEL_CH1N
2172 * @arg @ref LL_TIM_CHANNEL_CH2
2173 * @arg @ref LL_TIM_CHANNEL_CH2N
2174 * @arg @ref LL_TIM_CHANNEL_CH3
2175 * @arg @ref LL_TIM_CHANNEL_CH3N
2176 * @arg @ref LL_TIM_CHANNEL_CH4
2177 * @arg @ref LL_TIM_CHANNEL_CH5
2178 * @arg @ref LL_TIM_CHANNEL_CH6
2179 * @param IdleState This parameter can be one of the following values:
2180 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2181 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2182 * @retval None
2183 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)2184 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2185 {
2186 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2187 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2188 }
2189
2190 /**
2191 * @brief Get the IDLE state of an output channel
2192 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2193 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2194 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2195 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2196 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2197 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2198 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2199 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2200 * CR2 OIS6 LL_TIM_OC_GetIdleState
2201 * @param TIMx Timer instance
2202 * @param Channel This parameter can be one of the following values:
2203 * @arg @ref LL_TIM_CHANNEL_CH1
2204 * @arg @ref LL_TIM_CHANNEL_CH1N
2205 * @arg @ref LL_TIM_CHANNEL_CH2
2206 * @arg @ref LL_TIM_CHANNEL_CH2N
2207 * @arg @ref LL_TIM_CHANNEL_CH3
2208 * @arg @ref LL_TIM_CHANNEL_CH3N
2209 * @arg @ref LL_TIM_CHANNEL_CH4
2210 * @arg @ref LL_TIM_CHANNEL_CH5
2211 * @arg @ref LL_TIM_CHANNEL_CH6
2212 * @retval Returned value can be one of the following values:
2213 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2214 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2215 */
LL_TIM_OC_GetIdleState(const TIM_TypeDef * TIMx,uint32_t Channel)2216 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
2217 {
2218 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2219 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2220 }
2221
2222 /**
2223 * @brief Enable fast mode for the output channel.
2224 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2225 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2226 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2227 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2228 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2229 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2230 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2231 * @param TIMx Timer instance
2232 * @param Channel This parameter can be one of the following values:
2233 * @arg @ref LL_TIM_CHANNEL_CH1
2234 * @arg @ref LL_TIM_CHANNEL_CH2
2235 * @arg @ref LL_TIM_CHANNEL_CH3
2236 * @arg @ref LL_TIM_CHANNEL_CH4
2237 * @arg @ref LL_TIM_CHANNEL_CH5
2238 * @arg @ref LL_TIM_CHANNEL_CH6
2239 * @retval None
2240 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)2241 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2242 {
2243 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2244 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2245 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2246
2247 }
2248
2249 /**
2250 * @brief Disable fast mode for the output channel.
2251 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2252 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2253 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2254 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2255 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2256 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2257 * @param TIMx Timer instance
2258 * @param Channel This parameter can be one of the following values:
2259 * @arg @ref LL_TIM_CHANNEL_CH1
2260 * @arg @ref LL_TIM_CHANNEL_CH2
2261 * @arg @ref LL_TIM_CHANNEL_CH3
2262 * @arg @ref LL_TIM_CHANNEL_CH4
2263 * @arg @ref LL_TIM_CHANNEL_CH5
2264 * @arg @ref LL_TIM_CHANNEL_CH6
2265 * @retval None
2266 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)2267 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2268 {
2269 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2270 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2271 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2272
2273 }
2274
2275 /**
2276 * @brief Indicates whether fast mode is enabled for the output channel.
2277 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2278 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2279 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2280 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2281 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2282 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2283 * @param TIMx Timer instance
2284 * @param Channel This parameter can be one of the following values:
2285 * @arg @ref LL_TIM_CHANNEL_CH1
2286 * @arg @ref LL_TIM_CHANNEL_CH2
2287 * @arg @ref LL_TIM_CHANNEL_CH3
2288 * @arg @ref LL_TIM_CHANNEL_CH4
2289 * @arg @ref LL_TIM_CHANNEL_CH5
2290 * @arg @ref LL_TIM_CHANNEL_CH6
2291 * @retval State of bit (1 or 0).
2292 */
LL_TIM_OC_IsEnabledFast(const TIM_TypeDef * TIMx,uint32_t Channel)2293 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
2294 {
2295 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2296 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2297 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2298 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2299 }
2300
2301 /**
2302 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2303 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2304 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2305 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2306 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2307 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2308 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2309 * @param TIMx Timer instance
2310 * @param Channel This parameter can be one of the following values:
2311 * @arg @ref LL_TIM_CHANNEL_CH1
2312 * @arg @ref LL_TIM_CHANNEL_CH2
2313 * @arg @ref LL_TIM_CHANNEL_CH3
2314 * @arg @ref LL_TIM_CHANNEL_CH4
2315 * @arg @ref LL_TIM_CHANNEL_CH5
2316 * @arg @ref LL_TIM_CHANNEL_CH6
2317 * @retval None
2318 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2319 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2320 {
2321 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2322 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2323 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2324 }
2325
2326 /**
2327 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2328 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2329 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2330 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2331 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2332 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2333 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2334 * @param TIMx Timer instance
2335 * @param Channel This parameter can be one of the following values:
2336 * @arg @ref LL_TIM_CHANNEL_CH1
2337 * @arg @ref LL_TIM_CHANNEL_CH2
2338 * @arg @ref LL_TIM_CHANNEL_CH3
2339 * @arg @ref LL_TIM_CHANNEL_CH4
2340 * @arg @ref LL_TIM_CHANNEL_CH5
2341 * @arg @ref LL_TIM_CHANNEL_CH6
2342 * @retval None
2343 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2344 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2345 {
2346 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2347 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2348 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2349 }
2350
2351 /**
2352 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2353 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2354 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2355 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2356 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2357 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2358 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2359 * @param TIMx Timer instance
2360 * @param Channel This parameter can be one of the following values:
2361 * @arg @ref LL_TIM_CHANNEL_CH1
2362 * @arg @ref LL_TIM_CHANNEL_CH2
2363 * @arg @ref LL_TIM_CHANNEL_CH3
2364 * @arg @ref LL_TIM_CHANNEL_CH4
2365 * @arg @ref LL_TIM_CHANNEL_CH5
2366 * @arg @ref LL_TIM_CHANNEL_CH6
2367 * @retval State of bit (1 or 0).
2368 */
LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef * TIMx,uint32_t Channel)2369 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
2370 {
2371 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2372 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2373 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2374 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2375 }
2376
2377 /**
2378 * @brief Enable clearing the output channel on an external event.
2379 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2380 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2381 * or not a timer instance can clear the OCxREF signal on an external event.
2382 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2383 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2384 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2385 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2386 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2387 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2388 * @param TIMx Timer instance
2389 * @param Channel This parameter can be one of the following values:
2390 * @arg @ref LL_TIM_CHANNEL_CH1
2391 * @arg @ref LL_TIM_CHANNEL_CH2
2392 * @arg @ref LL_TIM_CHANNEL_CH3
2393 * @arg @ref LL_TIM_CHANNEL_CH4
2394 * @arg @ref LL_TIM_CHANNEL_CH5
2395 * @arg @ref LL_TIM_CHANNEL_CH6
2396 * @retval None
2397 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)2398 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2399 {
2400 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2401 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2402 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2403 }
2404
2405 /**
2406 * @brief Disable clearing the output channel on an external event.
2407 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2408 * or not a timer instance can clear the OCxREF signal on an external event.
2409 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2410 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2411 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2412 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
2413 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2414 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2415 * @param TIMx Timer instance
2416 * @param Channel This parameter can be one of the following values:
2417 * @arg @ref LL_TIM_CHANNEL_CH1
2418 * @arg @ref LL_TIM_CHANNEL_CH2
2419 * @arg @ref LL_TIM_CHANNEL_CH3
2420 * @arg @ref LL_TIM_CHANNEL_CH4
2421 * @arg @ref LL_TIM_CHANNEL_CH5
2422 * @arg @ref LL_TIM_CHANNEL_CH6
2423 * @retval None
2424 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)2425 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2426 {
2427 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2428 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2429 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2430 }
2431
2432 /**
2433 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2434 * @note This function enables clearing the output channel on an external event.
2435 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2436 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2437 * or not a timer instance can clear the OCxREF signal on an external event.
2438 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2439 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2440 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2441 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2442 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2443 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2444 * @param TIMx Timer instance
2445 * @param Channel This parameter can be one of the following values:
2446 * @arg @ref LL_TIM_CHANNEL_CH1
2447 * @arg @ref LL_TIM_CHANNEL_CH2
2448 * @arg @ref LL_TIM_CHANNEL_CH3
2449 * @arg @ref LL_TIM_CHANNEL_CH4
2450 * @arg @ref LL_TIM_CHANNEL_CH5
2451 * @arg @ref LL_TIM_CHANNEL_CH6
2452 * @retval State of bit (1 or 0).
2453 */
LL_TIM_OC_IsEnabledClear(const TIM_TypeDef * TIMx,uint32_t Channel)2454 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
2455 {
2456 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2457 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2458 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2459 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2460 }
2461
2462 /**
2463 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
2464 * the Ocx and OCxN signals).
2465 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2466 * dead-time insertion feature is supported by a timer instance.
2467 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2468 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2469 * @param TIMx Timer instance
2470 * @param DeadTime between Min_Data=0 and Max_Data=255
2471 * @retval None
2472 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2473 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2474 {
2475 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2476 }
2477
2478 /**
2479 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2480 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2481 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2482 * whether or not a timer instance supports a 32 bits counter.
2483 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2484 * output channel 1 is supported by a timer instance.
2485 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2486 * @param TIMx Timer instance
2487 * @param CompareValue between Min_Data=0 and Max_Data=65535
2488 * @retval None
2489 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2490 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2491 {
2492 WRITE_REG(TIMx->CCR1, CompareValue);
2493 }
2494
2495 /**
2496 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2497 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2498 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2499 * whether or not a timer instance supports a 32 bits counter.
2500 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2501 * output channel 2 is supported by a timer instance.
2502 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2503 * @param TIMx Timer instance
2504 * @param CompareValue between Min_Data=0 and Max_Data=65535
2505 * @retval None
2506 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2507 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2508 {
2509 WRITE_REG(TIMx->CCR2, CompareValue);
2510 }
2511
2512 /**
2513 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2514 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2515 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2516 * whether or not a timer instance supports a 32 bits counter.
2517 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2518 * output channel is supported by a timer instance.
2519 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2520 * @param TIMx Timer instance
2521 * @param CompareValue between Min_Data=0 and Max_Data=65535
2522 * @retval None
2523 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2524 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2525 {
2526 WRITE_REG(TIMx->CCR3, CompareValue);
2527 }
2528
2529 /**
2530 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2531 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2532 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2533 * whether or not a timer instance supports a 32 bits counter.
2534 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2535 * output channel 4 is supported by a timer instance.
2536 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2537 * @param TIMx Timer instance
2538 * @param CompareValue between Min_Data=0 and Max_Data=65535
2539 * @retval None
2540 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2541 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2542 {
2543 WRITE_REG(TIMx->CCR4, CompareValue);
2544 }
2545
2546 /**
2547 * @brief Set compare value for output channel 5 (TIMx_CCR5).
2548 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2549 * output channel 5 is supported by a timer instance.
2550 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2551 * @param TIMx Timer instance
2552 * @param CompareValue between Min_Data=0 and Max_Data=65535
2553 * @retval None
2554 */
LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx,uint32_t CompareValue)2555 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
2556 {
2557 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
2558 }
2559
2560 /**
2561 * @brief Set compare value for output channel 6 (TIMx_CCR6).
2562 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2563 * output channel 6 is supported by a timer instance.
2564 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2565 * @param TIMx Timer instance
2566 * @param CompareValue between Min_Data=0 and Max_Data=65535
2567 * @retval None
2568 */
LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx,uint32_t CompareValue)2569 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
2570 {
2571 WRITE_REG(TIMx->CCR6, CompareValue);
2572 }
2573
2574 /**
2575 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2576 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2577 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2578 * whether or not a timer instance supports a 32 bits counter.
2579 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2580 * output channel 1 is supported by a timer instance.
2581 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2582 * @param TIMx Timer instance
2583 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2584 */
LL_TIM_OC_GetCompareCH1(const TIM_TypeDef * TIMx)2585 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
2586 {
2587 return (uint32_t)(READ_REG(TIMx->CCR1));
2588 }
2589
2590 /**
2591 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2592 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2593 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2594 * whether or not a timer instance supports a 32 bits counter.
2595 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2596 * output channel 2 is supported by a timer instance.
2597 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2598 * @param TIMx Timer instance
2599 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2600 */
LL_TIM_OC_GetCompareCH2(const TIM_TypeDef * TIMx)2601 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
2602 {
2603 return (uint32_t)(READ_REG(TIMx->CCR2));
2604 }
2605
2606 /**
2607 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2608 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2609 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2610 * whether or not a timer instance supports a 32 bits counter.
2611 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2612 * output channel 3 is supported by a timer instance.
2613 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2614 * @param TIMx Timer instance
2615 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2616 */
LL_TIM_OC_GetCompareCH3(const TIM_TypeDef * TIMx)2617 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
2618 {
2619 return (uint32_t)(READ_REG(TIMx->CCR3));
2620 }
2621
2622 /**
2623 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2624 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2625 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2626 * whether or not a timer instance supports a 32 bits counter.
2627 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2628 * output channel 4 is supported by a timer instance.
2629 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2630 * @param TIMx Timer instance
2631 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2632 */
LL_TIM_OC_GetCompareCH4(const TIM_TypeDef * TIMx)2633 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
2634 {
2635 return (uint32_t)(READ_REG(TIMx->CCR4));
2636 }
2637
2638 /**
2639 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
2640 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2641 * output channel 5 is supported by a timer instance.
2642 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2643 * @param TIMx Timer instance
2644 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2645 */
LL_TIM_OC_GetCompareCH5(const TIM_TypeDef * TIMx)2646 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
2647 {
2648 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
2649 }
2650
2651 /**
2652 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
2653 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2654 * output channel 6 is supported by a timer instance.
2655 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2656 * @param TIMx Timer instance
2657 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2658 */
LL_TIM_OC_GetCompareCH6(const TIM_TypeDef * TIMx)2659 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
2660 {
2661 return (uint32_t)(READ_REG(TIMx->CCR6));
2662 }
2663
2664 /**
2665 * @brief Select on which reference signal the OC5REF is combined to.
2666 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
2667 * whether or not a timer instance supports the combined 3-phase PWM mode.
2668 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
2669 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
2670 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
2671 * @param TIMx Timer instance
2672 * @param GroupCH5 This parameter can be a combination of the following values:
2673 * @arg @ref LL_TIM_GROUPCH5_NONE
2674 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
2675 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
2676 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
2677 * @retval None
2678 */
LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx,uint32_t GroupCH5)2679 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
2680 {
2681 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
2682 }
2683
2684 /**
2685 * @}
2686 */
2687
2688 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2689 * @{
2690 */
2691 /**
2692 * @brief Configure input channel.
2693 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2694 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2695 * CCMR1 IC1F LL_TIM_IC_Config\n
2696 * CCMR1 CC2S LL_TIM_IC_Config\n
2697 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2698 * CCMR1 IC2F LL_TIM_IC_Config\n
2699 * CCMR2 CC3S LL_TIM_IC_Config\n
2700 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2701 * CCMR2 IC3F LL_TIM_IC_Config\n
2702 * CCMR2 CC4S LL_TIM_IC_Config\n
2703 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2704 * CCMR2 IC4F LL_TIM_IC_Config\n
2705 * CCER CC1P LL_TIM_IC_Config\n
2706 * CCER CC1NP LL_TIM_IC_Config\n
2707 * CCER CC2P LL_TIM_IC_Config\n
2708 * CCER CC2NP LL_TIM_IC_Config\n
2709 * CCER CC3P LL_TIM_IC_Config\n
2710 * CCER CC3NP LL_TIM_IC_Config\n
2711 * CCER CC4P LL_TIM_IC_Config\n
2712 * CCER CC4NP LL_TIM_IC_Config
2713 * @param TIMx Timer instance
2714 * @param Channel This parameter can be one of the following values:
2715 * @arg @ref LL_TIM_CHANNEL_CH1
2716 * @arg @ref LL_TIM_CHANNEL_CH2
2717 * @arg @ref LL_TIM_CHANNEL_CH3
2718 * @arg @ref LL_TIM_CHANNEL_CH4
2719 * @param Configuration This parameter must be a combination of all the following values:
2720 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2721 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2722 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2723 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2724 * @retval None
2725 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2726 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2727 {
2728 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2729 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2730 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2731 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
2732 << SHIFT_TAB_ICxx[iChannel]);
2733 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2734 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2735 }
2736
2737 /**
2738 * @brief Set the active input.
2739 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2740 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2741 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2742 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2743 * @param TIMx Timer instance
2744 * @param Channel This parameter can be one of the following values:
2745 * @arg @ref LL_TIM_CHANNEL_CH1
2746 * @arg @ref LL_TIM_CHANNEL_CH2
2747 * @arg @ref LL_TIM_CHANNEL_CH3
2748 * @arg @ref LL_TIM_CHANNEL_CH4
2749 * @param ICActiveInput This parameter can be one of the following values:
2750 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2751 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2752 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2753 * @retval None
2754 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)2755 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2756 {
2757 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2758 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2759 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2760 }
2761
2762 /**
2763 * @brief Get the current active input.
2764 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2765 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2766 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2767 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
2768 * @param TIMx Timer instance
2769 * @param Channel This parameter can be one of the following values:
2770 * @arg @ref LL_TIM_CHANNEL_CH1
2771 * @arg @ref LL_TIM_CHANNEL_CH2
2772 * @arg @ref LL_TIM_CHANNEL_CH3
2773 * @arg @ref LL_TIM_CHANNEL_CH4
2774 * @retval Returned value can be one of the following values:
2775 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2776 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2777 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2778 */
LL_TIM_IC_GetActiveInput(const TIM_TypeDef * TIMx,uint32_t Channel)2779 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
2780 {
2781 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2782 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2783 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2784 }
2785
2786 /**
2787 * @brief Set the prescaler of input channel.
2788 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
2789 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
2790 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
2791 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
2792 * @param TIMx Timer instance
2793 * @param Channel This parameter can be one of the following values:
2794 * @arg @ref LL_TIM_CHANNEL_CH1
2795 * @arg @ref LL_TIM_CHANNEL_CH2
2796 * @arg @ref LL_TIM_CHANNEL_CH3
2797 * @arg @ref LL_TIM_CHANNEL_CH4
2798 * @param ICPrescaler This parameter can be one of the following values:
2799 * @arg @ref LL_TIM_ICPSC_DIV1
2800 * @arg @ref LL_TIM_ICPSC_DIV2
2801 * @arg @ref LL_TIM_ICPSC_DIV4
2802 * @arg @ref LL_TIM_ICPSC_DIV8
2803 * @retval None
2804 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)2805 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
2806 {
2807 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2808 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2809 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2810 }
2811
2812 /**
2813 * @brief Get the current prescaler value acting on an input channel.
2814 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
2815 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
2816 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
2817 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
2818 * @param TIMx Timer instance
2819 * @param Channel This parameter can be one of the following values:
2820 * @arg @ref LL_TIM_CHANNEL_CH1
2821 * @arg @ref LL_TIM_CHANNEL_CH2
2822 * @arg @ref LL_TIM_CHANNEL_CH3
2823 * @arg @ref LL_TIM_CHANNEL_CH4
2824 * @retval Returned value can be one of the following values:
2825 * @arg @ref LL_TIM_ICPSC_DIV1
2826 * @arg @ref LL_TIM_ICPSC_DIV2
2827 * @arg @ref LL_TIM_ICPSC_DIV4
2828 * @arg @ref LL_TIM_ICPSC_DIV8
2829 */
LL_TIM_IC_GetPrescaler(const TIM_TypeDef * TIMx,uint32_t Channel)2830 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
2831 {
2832 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2833 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2834 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2835 }
2836
2837 /**
2838 * @brief Set the input filter duration.
2839 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
2840 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
2841 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
2842 * CCMR2 IC4F LL_TIM_IC_SetFilter
2843 * @param TIMx Timer instance
2844 * @param Channel This parameter can be one of the following values:
2845 * @arg @ref LL_TIM_CHANNEL_CH1
2846 * @arg @ref LL_TIM_CHANNEL_CH2
2847 * @arg @ref LL_TIM_CHANNEL_CH3
2848 * @arg @ref LL_TIM_CHANNEL_CH4
2849 * @param ICFilter This parameter can be one of the following values:
2850 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2851 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2852 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2853 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2854 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2855 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2856 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2857 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2858 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2859 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2860 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2861 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2862 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2863 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2864 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2865 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2866 * @retval None
2867 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)2868 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
2869 {
2870 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2871 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2872 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2873 }
2874
2875 /**
2876 * @brief Get the input filter duration.
2877 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
2878 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
2879 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
2880 * CCMR2 IC4F LL_TIM_IC_GetFilter
2881 * @param TIMx Timer instance
2882 * @param Channel This parameter can be one of the following values:
2883 * @arg @ref LL_TIM_CHANNEL_CH1
2884 * @arg @ref LL_TIM_CHANNEL_CH2
2885 * @arg @ref LL_TIM_CHANNEL_CH3
2886 * @arg @ref LL_TIM_CHANNEL_CH4
2887 * @retval Returned value can be one of the following values:
2888 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2889 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2890 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2891 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2892 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2893 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2894 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2895 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2896 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2897 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2898 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2899 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2900 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2901 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2902 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2903 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2904 */
LL_TIM_IC_GetFilter(const TIM_TypeDef * TIMx,uint32_t Channel)2905 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
2906 {
2907 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2908 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2909 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2910 }
2911
2912 /**
2913 * @brief Set the input channel polarity.
2914 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
2915 * CCER CC1NP LL_TIM_IC_SetPolarity\n
2916 * CCER CC2P LL_TIM_IC_SetPolarity\n
2917 * CCER CC2NP LL_TIM_IC_SetPolarity\n
2918 * CCER CC3P LL_TIM_IC_SetPolarity\n
2919 * CCER CC3NP LL_TIM_IC_SetPolarity\n
2920 * CCER CC4P LL_TIM_IC_SetPolarity\n
2921 * CCER CC4NP LL_TIM_IC_SetPolarity
2922 * @param TIMx Timer instance
2923 * @param Channel This parameter can be one of the following values:
2924 * @arg @ref LL_TIM_CHANNEL_CH1
2925 * @arg @ref LL_TIM_CHANNEL_CH2
2926 * @arg @ref LL_TIM_CHANNEL_CH3
2927 * @arg @ref LL_TIM_CHANNEL_CH4
2928 * @param ICPolarity This parameter can be one of the following values:
2929 * @arg @ref LL_TIM_IC_POLARITY_RISING
2930 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2931 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2932 * @retval None
2933 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)2934 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
2935 {
2936 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2937 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2938 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
2939 }
2940
2941 /**
2942 * @brief Get the current input channel polarity.
2943 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
2944 * CCER CC1NP LL_TIM_IC_GetPolarity\n
2945 * CCER CC2P LL_TIM_IC_GetPolarity\n
2946 * CCER CC2NP LL_TIM_IC_GetPolarity\n
2947 * CCER CC3P LL_TIM_IC_GetPolarity\n
2948 * CCER CC3NP LL_TIM_IC_GetPolarity\n
2949 * CCER CC4P LL_TIM_IC_GetPolarity\n
2950 * CCER CC4NP LL_TIM_IC_GetPolarity
2951 * @param TIMx Timer instance
2952 * @param Channel This parameter can be one of the following values:
2953 * @arg @ref LL_TIM_CHANNEL_CH1
2954 * @arg @ref LL_TIM_CHANNEL_CH2
2955 * @arg @ref LL_TIM_CHANNEL_CH3
2956 * @arg @ref LL_TIM_CHANNEL_CH4
2957 * @retval Returned value can be one of the following values:
2958 * @arg @ref LL_TIM_IC_POLARITY_RISING
2959 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2960 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2961 */
LL_TIM_IC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2962 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2963 {
2964 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2965 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
2966 SHIFT_TAB_CCxP[iChannel]);
2967 }
2968
2969 /**
2970 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
2971 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2972 * a timer instance provides an XOR input.
2973 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
2974 * @param TIMx Timer instance
2975 * @retval None
2976 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)2977 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
2978 {
2979 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
2980 }
2981
2982 /**
2983 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
2984 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2985 * a timer instance provides an XOR input.
2986 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
2987 * @param TIMx Timer instance
2988 * @retval None
2989 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)2990 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
2991 {
2992 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
2993 }
2994
2995 /**
2996 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
2997 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2998 * a timer instance provides an XOR input.
2999 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3000 * @param TIMx Timer instance
3001 * @retval State of bit (1 or 0).
3002 */
LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef * TIMx)3003 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
3004 {
3005 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
3006 }
3007
3008 /**
3009 * @brief Get captured value for input channel 1.
3010 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3011 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3012 * whether or not a timer instance supports a 32 bits counter.
3013 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3014 * input channel 1 is supported by a timer instance.
3015 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3016 * @param TIMx Timer instance
3017 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3018 */
LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef * TIMx)3019 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
3020 {
3021 return (uint32_t)(READ_REG(TIMx->CCR1));
3022 }
3023
3024 /**
3025 * @brief Get captured value for input channel 2.
3026 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3027 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3028 * whether or not a timer instance supports a 32 bits counter.
3029 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3030 * input channel 2 is supported by a timer instance.
3031 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3032 * @param TIMx Timer instance
3033 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3034 */
LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef * TIMx)3035 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
3036 {
3037 return (uint32_t)(READ_REG(TIMx->CCR2));
3038 }
3039
3040 /**
3041 * @brief Get captured value for input channel 3.
3042 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3043 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3044 * whether or not a timer instance supports a 32 bits counter.
3045 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3046 * input channel 3 is supported by a timer instance.
3047 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3048 * @param TIMx Timer instance
3049 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3050 */
LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef * TIMx)3051 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
3052 {
3053 return (uint32_t)(READ_REG(TIMx->CCR3));
3054 }
3055
3056 /**
3057 * @brief Get captured value for input channel 4.
3058 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3059 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3060 * whether or not a timer instance supports a 32 bits counter.
3061 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3062 * input channel 4 is supported by a timer instance.
3063 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3064 * @param TIMx Timer instance
3065 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3066 */
LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef * TIMx)3067 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
3068 {
3069 return (uint32_t)(READ_REG(TIMx->CCR4));
3070 }
3071
3072 /**
3073 * @}
3074 */
3075
3076 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3077 * @{
3078 */
3079 /**
3080 * @brief Enable external clock mode 2.
3081 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3082 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3083 * whether or not a timer instance supports external clock mode2.
3084 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3085 * @param TIMx Timer instance
3086 * @retval None
3087 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)3088 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3089 {
3090 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3091 }
3092
3093 /**
3094 * @brief Disable external clock mode 2.
3095 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3096 * whether or not a timer instance supports external clock mode2.
3097 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3098 * @param TIMx Timer instance
3099 * @retval None
3100 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)3101 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3102 {
3103 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3104 }
3105
3106 /**
3107 * @brief Indicate whether external clock mode 2 is enabled.
3108 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3109 * whether or not a timer instance supports external clock mode2.
3110 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3111 * @param TIMx Timer instance
3112 * @retval State of bit (1 or 0).
3113 */
LL_TIM_IsEnabledExternalClock(const TIM_TypeDef * TIMx)3114 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
3115 {
3116 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3117 }
3118
3119 /**
3120 * @brief Set the clock source of the counter clock.
3121 * @note when selected clock source is external clock mode 1, the timer input
3122 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3123 * function. This timer input must be configured by calling
3124 * the @ref LL_TIM_IC_Config() function.
3125 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3126 * whether or not a timer instance supports external clock mode1.
3127 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3128 * whether or not a timer instance supports external clock mode2.
3129 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3130 * SMCR ECE LL_TIM_SetClockSource
3131 * @param TIMx Timer instance
3132 * @param ClockSource This parameter can be one of the following values:
3133 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3134 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3135 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3136 * @retval None
3137 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)3138 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3139 {
3140 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3141 }
3142
3143 /**
3144 * @brief Set the encoder interface mode.
3145 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3146 * whether or not a timer instance supports the encoder mode.
3147 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3148 * @param TIMx Timer instance
3149 * @param EncoderMode This parameter can be one of the following values:
3150 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3151 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3152 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3153 * @retval None
3154 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)3155 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3156 {
3157 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3158 }
3159
3160 /**
3161 * @}
3162 */
3163
3164 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3165 * @{
3166 */
3167 /**
3168 * @brief Set the trigger output (TRGO) used for timer synchronization .
3169 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3170 * whether or not a timer instance can operate as a master timer.
3171 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3172 * @param TIMx Timer instance
3173 * @param TimerSynchronization This parameter can be one of the following values:
3174 * @arg @ref LL_TIM_TRGO_RESET
3175 * @arg @ref LL_TIM_TRGO_ENABLE
3176 * @arg @ref LL_TIM_TRGO_UPDATE
3177 * @arg @ref LL_TIM_TRGO_CC1IF
3178 * @arg @ref LL_TIM_TRGO_OC1REF
3179 * @arg @ref LL_TIM_TRGO_OC2REF
3180 * @arg @ref LL_TIM_TRGO_OC3REF
3181 * @arg @ref LL_TIM_TRGO_OC4REF
3182 * @retval None
3183 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)3184 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3185 {
3186 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3187 }
3188
3189 /**
3190 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3191 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3192 * whether or not a timer instance can be used for ADC synchronization.
3193 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3194 * @param TIMx Timer Instance
3195 * @param ADCSynchronization This parameter can be one of the following values:
3196 * @arg @ref LL_TIM_TRGO2_RESET
3197 * @arg @ref LL_TIM_TRGO2_ENABLE
3198 * @arg @ref LL_TIM_TRGO2_UPDATE
3199 * @arg @ref LL_TIM_TRGO2_CC1F
3200 * @arg @ref LL_TIM_TRGO2_OC1
3201 * @arg @ref LL_TIM_TRGO2_OC2
3202 * @arg @ref LL_TIM_TRGO2_OC3
3203 * @arg @ref LL_TIM_TRGO2_OC4
3204 * @arg @ref LL_TIM_TRGO2_OC5
3205 * @arg @ref LL_TIM_TRGO2_OC6
3206 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3207 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3208 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3209 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3210 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3211 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3212 * @retval None
3213 */
LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx,uint32_t ADCSynchronization)3214 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3215 {
3216 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3217 }
3218
3219 /**
3220 * @brief Set the synchronization mode of a slave timer.
3221 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3222 * a timer instance can operate as a slave timer.
3223 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3224 * @param TIMx Timer instance
3225 * @param SlaveMode This parameter can be one of the following values:
3226 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3227 * @arg @ref LL_TIM_SLAVEMODE_RESET
3228 * @arg @ref LL_TIM_SLAVEMODE_GATED
3229 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3230 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3231 * @retval None
3232 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)3233 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3234 {
3235 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3236 }
3237
3238 /**
3239 * @brief Set the selects the trigger input to be used to synchronize the counter.
3240 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3241 * a timer instance can operate as a slave timer.
3242 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3243 * @param TIMx Timer instance
3244 * @param TriggerInput This parameter can be one of the following values:
3245 * @arg @ref LL_TIM_TS_ITR0
3246 * @arg @ref LL_TIM_TS_ITR1
3247 * @arg @ref LL_TIM_TS_ITR2
3248 * @arg @ref LL_TIM_TS_ITR3
3249 * @arg @ref LL_TIM_TS_ITR7 (*)
3250 * @arg @ref LL_TIM_TS_TI1F_ED
3251 * @arg @ref LL_TIM_TS_TI1FP1
3252 * @arg @ref LL_TIM_TS_TI2FP2
3253 * @arg @ref LL_TIM_TS_ETRF
3254 *
3255 * (*) Value not defined in all devices.
3256 * @retval None
3257 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)3258 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3259 {
3260 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3261 }
3262
3263 /**
3264 * @brief Enable the Master/Slave mode.
3265 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3266 * a timer instance can operate as a slave timer.
3267 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
3268 * @param TIMx Timer instance
3269 * @retval None
3270 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)3271 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
3272 {
3273 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3274 }
3275
3276 /**
3277 * @brief Disable the Master/Slave mode.
3278 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3279 * a timer instance can operate as a slave timer.
3280 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
3281 * @param TIMx Timer instance
3282 * @retval None
3283 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)3284 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
3285 {
3286 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3287 }
3288
3289 /**
3290 * @brief Indicates whether the Master/Slave mode is enabled.
3291 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3292 * a timer instance can operate as a slave timer.
3293 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
3294 * @param TIMx Timer instance
3295 * @retval State of bit (1 or 0).
3296 */
LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef * TIMx)3297 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
3298 {
3299 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
3300 }
3301
3302 /**
3303 * @brief Configure the external trigger (ETR) input.
3304 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3305 * a timer instance provides an external trigger input.
3306 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
3307 * SMCR ETPS LL_TIM_ConfigETR\n
3308 * SMCR ETF LL_TIM_ConfigETR
3309 * @param TIMx Timer instance
3310 * @param ETRPolarity This parameter can be one of the following values:
3311 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
3312 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
3313 * @param ETRPrescaler This parameter can be one of the following values:
3314 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
3315 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
3316 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
3317 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
3318 * @param ETRFilter This parameter can be one of the following values:
3319 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
3320 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
3321 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
3322 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
3323 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
3324 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
3325 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
3326 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
3327 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
3328 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
3329 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
3330 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
3331 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
3332 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
3333 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
3334 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
3335 * @retval None
3336 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)3337 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
3338 uint32_t ETRFilter)
3339 {
3340 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
3341 }
3342
3343 /**
3344 * @brief Select the external trigger (ETR) input source.
3345 * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
3346 * not a timer instance supports ETR source selection.
3347 * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
3348 * @param TIMx Timer instance
3349 * @param ETRSource This parameter can be one of the following values:
3350 * TIM1
3351 *
3352 * @arg @ref LL_TIM_ETRSOURCE_GPIO
3353 * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD1
3354 * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD2
3355 * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD3
3356 *
3357 * TIM2 (*)
3358 *
3359 * @arg @ref LL_TIM_ETRSOURCE_GPIO
3360 * @arg @ref LL_TIM_ETRSOURCE_LSE
3361 * @arg @ref LL_TIM_ETRSOURCE_MCO
3362 * @arg @ref LL_TIM_ETRSOURCE_MCO2
3363 *
3364 * (*) Timer instance not available on all devices \n
3365 * @retval None
3366 */
LL_TIM_SetETRSource(TIM_TypeDef * TIMx,uint32_t ETRSource)3367 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
3368 {
3369 MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
3370 }
3371
3372 /**
3373 * @}
3374 */
3375
3376 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
3377 * @{
3378 */
3379 /**
3380 * @brief Enable the break function.
3381 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3382 * a timer instance provides a break input.
3383 * @rmtoll BDTR BKE LL_TIM_EnableBRK
3384 * @param TIMx Timer instance
3385 * @retval None
3386 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)3387 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
3388 {
3389 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3390 }
3391
3392 /**
3393 * @brief Disable the break function.
3394 * @rmtoll BDTR BKE LL_TIM_DisableBRK
3395 * @param TIMx Timer instance
3396 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3397 * a timer instance provides a break input.
3398 * @retval None
3399 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)3400 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
3401 {
3402 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3403 }
3404
3405 /**
3406 * @brief Configure the break input.
3407 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3408 * a timer instance provides a break input.
3409 * @note Bidirectional mode is only supported by advanced timer instances.
3410 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
3411 * a timer instance is an advanced-control timer.
3412 * @note In bidirectional mode (BKBID bit set), the Break input is configured both
3413 * in input mode and in open drain output mode. Any active Break event will
3414 * assert a low logic level on the Break input to indicate an internal break
3415 * event to external devices.
3416 * @note When bidirectional mode isn't supported, BreakAFMode must be set to
3417 * LL_TIM_BREAK_AFMODE_INPUT.
3418 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
3419 * BDTR BKF LL_TIM_ConfigBRK\n
3420 * BDTR BKBID LL_TIM_ConfigBRK
3421 * @param TIMx Timer instance
3422 * @param BreakPolarity This parameter can be one of the following values:
3423 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
3424 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
3425 * @param BreakFilter This parameter can be one of the following values:
3426 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
3427 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
3428 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
3429 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
3430 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
3431 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
3432 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
3433 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
3434 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
3435 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
3436 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
3437 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
3438 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
3439 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
3440 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
3441 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
3442 * @param BreakAFMode This parameter can be one of the following values:
3443 * @arg @ref LL_TIM_BREAK_AFMODE_INPUT
3444 * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
3445 * @retval None
3446 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity,uint32_t BreakFilter,uint32_t BreakAFMode)3447 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
3448 uint32_t BreakAFMode)
3449 {
3450 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
3451 }
3452
3453 /**
3454 * @brief Disarm the break input (when it operates in bidirectional mode).
3455 * @note The break input can be disarmed only when it is configured in
3456 * bidirectional mode and when when MOE is reset.
3457 * @note Purpose is to be able to have the input voltage back to high-state,
3458 * whatever the time constant on the output .
3459 * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK
3460 * @param TIMx Timer instance
3461 * @retval None
3462 */
LL_TIM_DisarmBRK(TIM_TypeDef * TIMx)3463 __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
3464 {
3465 SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
3466 }
3467
3468 /**
3469 * @brief Re-arm the break input (when it operates in bidirectional mode).
3470 * @note The Break input is automatically armed as soon as MOE bit is set.
3471 * @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK
3472 * @param TIMx Timer instance
3473 * @retval None
3474 */
LL_TIM_ReArmBRK(TIM_TypeDef * TIMx)3475 __STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx)
3476 {
3477 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
3478 }
3479
3480 /**
3481 * @brief Enable the break 2 function.
3482 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3483 * a timer instance provides a second break input.
3484 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
3485 * @param TIMx Timer instance
3486 * @retval None
3487 */
LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)3488 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
3489 {
3490 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3491 }
3492
3493 /**
3494 * @brief Disable the break 2 function.
3495 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3496 * a timer instance provides a second break input.
3497 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
3498 * @param TIMx Timer instance
3499 * @retval None
3500 */
LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)3501 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
3502 {
3503 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3504 }
3505
3506 /**
3507 * @brief Configure the break 2 input.
3508 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3509 * a timer instance provides a second break input.
3510 * @note Bidirectional mode is only supported by advanced timer instances.
3511 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
3512 * a timer instance is an advanced-control timer.
3513 * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
3514 * in input mode and in open drain output mode. Any active Break event will
3515 * assert a low logic level on the Break 2 input to indicate an internal break
3516 * event to external devices.
3517 * @note When bidirectional mode isn't supported, Break2AFMode must be set to
3518 * LL_TIM_BREAK2_AFMODE_INPUT.
3519 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
3520 * BDTR BK2F LL_TIM_ConfigBRK2\n
3521 * BDTR BK2BID LL_TIM_ConfigBRK2
3522 * @param TIMx Timer instance
3523 * @param Break2Polarity This parameter can be one of the following values:
3524 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
3525 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
3526 * @param Break2Filter This parameter can be one of the following values:
3527 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
3528 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
3529 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
3530 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
3531 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
3532 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
3533 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
3534 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
3535 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
3536 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
3537 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
3538 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
3539 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
3540 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
3541 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
3542 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
3543 * @param Break2AFMode This parameter can be one of the following values:
3544 * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
3545 * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
3546 * @retval None
3547 */
LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx,uint32_t Break2Polarity,uint32_t Break2Filter,uint32_t Break2AFMode)3548 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
3549 uint32_t Break2AFMode)
3550 {
3551 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
3552 }
3553
3554 /**
3555 * @brief Disarm the break 2 input (when it operates in bidirectional mode).
3556 * @note The break 2 input can be disarmed only when it is configured in
3557 * bidirectional mode and when when MOE is reset.
3558 * @note Purpose is to be able to have the input voltage back to high-state,
3559 * whatever the time constant on the output.
3560 * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2
3561 * @param TIMx Timer instance
3562 * @retval None
3563 */
LL_TIM_DisarmBRK2(TIM_TypeDef * TIMx)3564 __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
3565 {
3566 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
3567 }
3568
3569 /**
3570 * @brief Re-arm the break 2 input (when it operates in bidirectional mode).
3571 * @note The Break 2 input is automatically armed as soon as MOE bit is set.
3572 * @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2
3573 * @param TIMx Timer instance
3574 * @retval None
3575 */
LL_TIM_ReArmBRK2(TIM_TypeDef * TIMx)3576 __STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx)
3577 {
3578 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
3579 }
3580
3581 /**
3582 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
3583 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3584 * a timer instance provides a break input.
3585 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
3586 * BDTR OSSR LL_TIM_SetOffStates
3587 * @param TIMx Timer instance
3588 * @param OffStateIdle This parameter can be one of the following values:
3589 * @arg @ref LL_TIM_OSSI_DISABLE
3590 * @arg @ref LL_TIM_OSSI_ENABLE
3591 * @param OffStateRun This parameter can be one of the following values:
3592 * @arg @ref LL_TIM_OSSR_DISABLE
3593 * @arg @ref LL_TIM_OSSR_ENABLE
3594 * @retval None
3595 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)3596 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
3597 {
3598 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
3599 }
3600
3601 /**
3602 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
3603 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3604 * a timer instance provides a break input.
3605 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
3606 * @param TIMx Timer instance
3607 * @retval None
3608 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)3609 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
3610 {
3611 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3612 }
3613
3614 /**
3615 * @brief Disable automatic output (MOE can be set only by software).
3616 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3617 * a timer instance provides a break input.
3618 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
3619 * @param TIMx Timer instance
3620 * @retval None
3621 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)3622 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
3623 {
3624 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3625 }
3626
3627 /**
3628 * @brief Indicate whether automatic output is enabled.
3629 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3630 * a timer instance provides a break input.
3631 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
3632 * @param TIMx Timer instance
3633 * @retval State of bit (1 or 0).
3634 */
LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef * TIMx)3635 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
3636 {
3637 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
3638 }
3639
3640 /**
3641 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
3642 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3643 * software and is reset in case of break or break2 event
3644 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3645 * a timer instance provides a break input.
3646 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
3647 * @param TIMx Timer instance
3648 * @retval None
3649 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)3650 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
3651 {
3652 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3653 }
3654
3655 /**
3656 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
3657 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3658 * software and is reset in case of break or break2 event.
3659 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3660 * a timer instance provides a break input.
3661 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
3662 * @param TIMx Timer instance
3663 * @retval None
3664 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)3665 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
3666 {
3667 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3668 }
3669
3670 /**
3671 * @brief Indicates whether outputs are enabled.
3672 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3673 * a timer instance provides a break input.
3674 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
3675 * @param TIMx Timer instance
3676 * @retval State of bit (1 or 0).
3677 */
LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef * TIMx)3678 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
3679 {
3680 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
3681 }
3682
3683 /**
3684 * @brief Enable the signals connected to the designated timer break input.
3685 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3686 * or not a timer instance allows for break input selection.
3687 * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
3688 * AF2 BK2INE LL_TIM_EnableBreakInputSource\n
3689 * @param TIMx Timer instance
3690 * @param BreakInput This parameter can be one of the following values:
3691 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3692 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3693 * @param Source This parameter can be one of the following values:
3694 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3695 *
3696 * @retval None
3697 */
LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3698 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3699 {
3700 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3701 SET_BIT(*pReg, Source);
3702 }
3703
3704 /**
3705 * @brief Disable the signals connected to the designated timer break input.
3706 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3707 * or not a timer instance allows for break input selection.
3708 * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
3709 * AF2 BK2INE LL_TIM_DisableBreakInputSource\n
3710 * @param TIMx Timer instance
3711 * @param BreakInput This parameter can be one of the following values:
3712 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3713 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3714 * @param Source This parameter can be one of the following values:
3715 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3716 *
3717 * @retval None
3718 */
LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3719 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3720 {
3721 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3722 CLEAR_BIT(*pReg, Source);
3723 }
3724
3725 /**
3726 * @brief Set the polarity of the break signal for the timer break input.
3727 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3728 * or not a timer instance allows for break input selection.
3729 * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
3730 * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
3731 * @param TIMx Timer instance
3732 * @param BreakInput This parameter can be one of the following values:
3733 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3734 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3735 * @param Source This parameter can be one of the following values:
3736 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3737 * @param Polarity This parameter can be one of the following values:
3738 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
3739 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
3740 * @retval None
3741 */
LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source,uint32_t Polarity)3742 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
3743 uint32_t Polarity)
3744 {
3745 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3746 MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
3747 }
3748 /**
3749 * @}
3750 */
3751
3752 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
3753 * @{
3754 */
3755 /**
3756 * @brief Configures the timer DMA burst feature.
3757 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
3758 * not a timer instance supports the DMA burst mode.
3759 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
3760 * DCR DBA LL_TIM_ConfigDMABurst
3761 * @param TIMx Timer instance
3762 * @param DMABurstBaseAddress This parameter can be one of the following values:
3763 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
3764 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
3765 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
3766 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
3767 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
3768 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
3769 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
3770 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
3771 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
3772 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
3773 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
3774 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
3775 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
3776 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
3777 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
3778 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
3779 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
3780 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
3781 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
3782 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
3783 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
3784 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
3785 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
3786 * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
3787 * @param DMABurstLength This parameter can be one of the following values:
3788 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
3789 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
3790 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
3791 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
3792 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
3793 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
3794 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
3795 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
3796 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
3797 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
3798 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
3799 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
3800 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
3801 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
3802 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
3803 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
3804 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
3805 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
3806 * @retval None
3807 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength)3808 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
3809 {
3810 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
3811 }
3812
3813 /**
3814 * @}
3815 */
3816
3817 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
3818 * @{
3819 */
3820 /**
3821 * @brief Remap TIM inputs (input channel, internal/external triggers).
3822 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
3823 * a some timer inputs can be remapped.
3824 * @rmtoll TIM1_TISEL TI1SEL LL_TIM_SetRemap\n
3825 * TIM1_TISEL TI2SEL LL_TIM_SetRemap\n
3826 * TIM1_TISEL TI3SEL LL_TIM_SetRemap\n
3827 * TIM1_TISEL TI4SEL LL_TIM_SetRemap\n
3828 * TIM2_TISEL TI1SEL LL_TIM_SetRemap\n
3829 * TIM2_TISEL TI2SEL LL_TIM_SetRemap\n
3830 * TIM2_TISEL TI3SEL LL_TIM_SetRemap\n
3831 * TIM2_TISEL TI4SEL LL_TIM_SetRemap\n
3832 * TIM3_TISEL TI1SEL LL_TIM_SetRemap\n
3833 * TIM3_TISEL TI2SEL LL_TIM_SetRemap\n
3834 * TIM3_TISEL TI3SEL LL_TIM_SetRemap\n
3835 * TIM3_TISEL TI4SEL LL_TIM_SetRemap\n
3836 * TIM14_TISEL TI1SEL LL_TIM_SetRemap\n
3837 * TIM16_TISEL TI1SEL LL_TIM_SetRemap\n
3838 * TIM17_TISEL TI1SEL LL_TIM_SetRemap
3839 * @param TIMx Timer instance
3840 * @param Remap Remap param depends on the TIMx. Description available only
3841 * in CHM version of the User Manual (not in .pdf).
3842 * Otherwise see Reference Manual description of TISEL registers.
3843 *
3844 * Below description summarizes "Timer Instance" and "Remap" param combinations:
3845 *
3846 * TIM14: one of the following values
3847 *
3848 * @arg @ref LL_TIM_TIM14_TI1_RMP_GPIO
3849 * @arg @ref LL_TIM_TIM14_TI1_RMP_RTC_CLK
3850 * @arg @ref LL_TIM_TIM14_TI1_RMP_HSE_32
3851 * @arg @ref LL_TIM_TIM14_TI1_RMP_MCO
3852 * @arg @ref LL_TIM_TIM14_TI1_RMP_MCO2
3853 *
3854 * TIM16: one of the following values
3855 *
3856 * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
3857 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
3858 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
3859 * @arg @ref LL_TIM_TIM16_TI1_RMP_MCO2
3860 *
3861 * TIM17: one of the following values
3862 *
3863 * @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
3864 * @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32
3865 * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
3866 * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO2
3867 * @retval None
3868 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)3869 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
3870 {
3871 MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
3872 }
3873
3874 /**
3875 * @}
3876 */
3877
3878 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
3879 * @{
3880 */
3881 /**
3882 * @brief Set the OCREF clear input source
3883 * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
3884 * @note This function can only be used in Output compare and PWM modes.
3885 * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
3886 * @param TIMx Timer instance
3887 * @param OCRefClearInputSource This parameter can be one of the following values:
3888 * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
3889 * @retval None
3890 */
LL_TIM_SetOCRefClearInputSource(TIM_TypeDef * TIMx,uint32_t OCRefClearInputSource)3891 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
3892 {
3893 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS,
3894 ((OCRefClearInputSource & OCREF_CLEAR_SELECT_MSK) >> OCREF_CLEAR_SELECT_POS) << TIM_SMCR_OCCS_Pos);
3895 }
3896 /**
3897 * @}
3898 */
3899
3900 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
3901 * @{
3902 */
3903 /**
3904 * @brief Clear the update interrupt flag (UIF).
3905 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
3906 * @param TIMx Timer instance
3907 * @retval None
3908 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)3909 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
3910 {
3911 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
3912 }
3913
3914 /**
3915 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
3916 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
3917 * @param TIMx Timer instance
3918 * @retval State of bit (1 or 0).
3919 */
LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef * TIMx)3920 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
3921 {
3922 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
3923 }
3924
3925 /**
3926 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
3927 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
3928 * @param TIMx Timer instance
3929 * @retval None
3930 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)3931 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
3932 {
3933 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
3934 }
3935
3936 /**
3937 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
3938 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
3939 * @param TIMx Timer instance
3940 * @retval State of bit (1 or 0).
3941 */
LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef * TIMx)3942 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
3943 {
3944 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
3945 }
3946
3947 /**
3948 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
3949 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
3950 * @param TIMx Timer instance
3951 * @retval None
3952 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)3953 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
3954 {
3955 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
3956 }
3957
3958 /**
3959 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
3960 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
3961 * @param TIMx Timer instance
3962 * @retval State of bit (1 or 0).
3963 */
LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef * TIMx)3964 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
3965 {
3966 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
3967 }
3968
3969 /**
3970 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
3971 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
3972 * @param TIMx Timer instance
3973 * @retval None
3974 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)3975 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
3976 {
3977 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
3978 }
3979
3980 /**
3981 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
3982 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
3983 * @param TIMx Timer instance
3984 * @retval State of bit (1 or 0).
3985 */
LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef * TIMx)3986 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
3987 {
3988 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
3989 }
3990
3991 /**
3992 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
3993 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
3994 * @param TIMx Timer instance
3995 * @retval None
3996 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)3997 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
3998 {
3999 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
4000 }
4001
4002 /**
4003 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
4004 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
4005 * @param TIMx Timer instance
4006 * @retval State of bit (1 or 0).
4007 */
LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef * TIMx)4008 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
4009 {
4010 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
4011 }
4012
4013 /**
4014 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
4015 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
4016 * @param TIMx Timer instance
4017 * @retval None
4018 */
LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)4019 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
4020 {
4021 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
4022 }
4023
4024 /**
4025 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
4026 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
4027 * @param TIMx Timer instance
4028 * @retval State of bit (1 or 0).
4029 */
LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef * TIMx)4030 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
4031 {
4032 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
4033 }
4034
4035 /**
4036 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
4037 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
4038 * @param TIMx Timer instance
4039 * @retval None
4040 */
LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)4041 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
4042 {
4043 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
4044 }
4045
4046 /**
4047 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
4048 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
4049 * @param TIMx Timer instance
4050 * @retval State of bit (1 or 0).
4051 */
LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef * TIMx)4052 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
4053 {
4054 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
4055 }
4056
4057 /**
4058 * @brief Clear the commutation interrupt flag (COMIF).
4059 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
4060 * @param TIMx Timer instance
4061 * @retval None
4062 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)4063 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
4064 {
4065 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
4066 }
4067
4068 /**
4069 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
4070 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
4071 * @param TIMx Timer instance
4072 * @retval State of bit (1 or 0).
4073 */
LL_TIM_IsActiveFlag_COM(const TIM_TypeDef * TIMx)4074 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
4075 {
4076 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
4077 }
4078
4079 /**
4080 * @brief Clear the trigger interrupt flag (TIF).
4081 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
4082 * @param TIMx Timer instance
4083 * @retval None
4084 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)4085 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
4086 {
4087 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
4088 }
4089
4090 /**
4091 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
4092 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
4093 * @param TIMx Timer instance
4094 * @retval State of bit (1 or 0).
4095 */
LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef * TIMx)4096 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
4097 {
4098 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
4099 }
4100
4101 /**
4102 * @brief Clear the break interrupt flag (BIF).
4103 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
4104 * @param TIMx Timer instance
4105 * @retval None
4106 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)4107 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
4108 {
4109 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
4110 }
4111
4112 /**
4113 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
4114 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
4115 * @param TIMx Timer instance
4116 * @retval State of bit (1 or 0).
4117 */
LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef * TIMx)4118 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
4119 {
4120 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
4121 }
4122
4123 /**
4124 * @brief Clear the break 2 interrupt flag (B2IF).
4125 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
4126 * @param TIMx Timer instance
4127 * @retval None
4128 */
LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)4129 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
4130 {
4131 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
4132 }
4133
4134 /**
4135 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
4136 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
4137 * @param TIMx Timer instance
4138 * @retval State of bit (1 or 0).
4139 */
LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef * TIMx)4140 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
4141 {
4142 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
4143 }
4144
4145 /**
4146 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
4147 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
4148 * @param TIMx Timer instance
4149 * @retval None
4150 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)4151 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
4152 {
4153 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
4154 }
4155
4156 /**
4157 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
4158 * (Capture/Compare 1 interrupt is pending).
4159 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
4160 * @param TIMx Timer instance
4161 * @retval State of bit (1 or 0).
4162 */
LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef * TIMx)4163 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
4164 {
4165 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
4166 }
4167
4168 /**
4169 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
4170 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
4171 * @param TIMx Timer instance
4172 * @retval None
4173 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)4174 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
4175 {
4176 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
4177 }
4178
4179 /**
4180 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
4181 * (Capture/Compare 2 over-capture interrupt is pending).
4182 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
4183 * @param TIMx Timer instance
4184 * @retval State of bit (1 or 0).
4185 */
LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef * TIMx)4186 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
4187 {
4188 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
4189 }
4190
4191 /**
4192 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
4193 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
4194 * @param TIMx Timer instance
4195 * @retval None
4196 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)4197 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
4198 {
4199 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
4200 }
4201
4202 /**
4203 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
4204 * (Capture/Compare 3 over-capture interrupt is pending).
4205 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
4206 * @param TIMx Timer instance
4207 * @retval State of bit (1 or 0).
4208 */
LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef * TIMx)4209 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
4210 {
4211 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
4212 }
4213
4214 /**
4215 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
4216 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
4217 * @param TIMx Timer instance
4218 * @retval None
4219 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)4220 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
4221 {
4222 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
4223 }
4224
4225 /**
4226 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
4227 * (Capture/Compare 4 over-capture interrupt is pending).
4228 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
4229 * @param TIMx Timer instance
4230 * @retval State of bit (1 or 0).
4231 */
LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef * TIMx)4232 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
4233 {
4234 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
4235 }
4236
4237 /**
4238 * @brief Clear the system break interrupt flag (SBIF).
4239 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
4240 * @param TIMx Timer instance
4241 * @retval None
4242 */
LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef * TIMx)4243 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
4244 {
4245 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
4246 }
4247
4248 /**
4249 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
4250 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
4251 * @param TIMx Timer instance
4252 * @retval State of bit (1 or 0).
4253 */
LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef * TIMx)4254 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
4255 {
4256 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
4257 }
4258
4259 /**
4260 * @}
4261 */
4262
4263 /** @defgroup TIM_LL_EF_IT_Management IT-Management
4264 * @{
4265 */
4266 /**
4267 * @brief Enable update interrupt (UIE).
4268 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
4269 * @param TIMx Timer instance
4270 * @retval None
4271 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)4272 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
4273 {
4274 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
4275 }
4276
4277 /**
4278 * @brief Disable update interrupt (UIE).
4279 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
4280 * @param TIMx Timer instance
4281 * @retval None
4282 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)4283 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
4284 {
4285 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
4286 }
4287
4288 /**
4289 * @brief Indicates whether the update interrupt (UIE) is enabled.
4290 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
4291 * @param TIMx Timer instance
4292 * @retval State of bit (1 or 0).
4293 */
LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef * TIMx)4294 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
4295 {
4296 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
4297 }
4298
4299 /**
4300 * @brief Enable capture/compare 1 interrupt (CC1IE).
4301 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
4302 * @param TIMx Timer instance
4303 * @retval None
4304 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)4305 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
4306 {
4307 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4308 }
4309
4310 /**
4311 * @brief Disable capture/compare 1 interrupt (CC1IE).
4312 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
4313 * @param TIMx Timer instance
4314 * @retval None
4315 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)4316 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
4317 {
4318 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4319 }
4320
4321 /**
4322 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
4323 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
4324 * @param TIMx Timer instance
4325 * @retval State of bit (1 or 0).
4326 */
LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef * TIMx)4327 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
4328 {
4329 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
4330 }
4331
4332 /**
4333 * @brief Enable capture/compare 2 interrupt (CC2IE).
4334 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
4335 * @param TIMx Timer instance
4336 * @retval None
4337 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)4338 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
4339 {
4340 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4341 }
4342
4343 /**
4344 * @brief Disable capture/compare 2 interrupt (CC2IE).
4345 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
4346 * @param TIMx Timer instance
4347 * @retval None
4348 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)4349 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
4350 {
4351 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4352 }
4353
4354 /**
4355 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
4356 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
4357 * @param TIMx Timer instance
4358 * @retval State of bit (1 or 0).
4359 */
LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef * TIMx)4360 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
4361 {
4362 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
4363 }
4364
4365 /**
4366 * @brief Enable capture/compare 3 interrupt (CC3IE).
4367 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
4368 * @param TIMx Timer instance
4369 * @retval None
4370 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)4371 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
4372 {
4373 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4374 }
4375
4376 /**
4377 * @brief Disable capture/compare 3 interrupt (CC3IE).
4378 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
4379 * @param TIMx Timer instance
4380 * @retval None
4381 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)4382 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
4383 {
4384 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4385 }
4386
4387 /**
4388 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
4389 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
4390 * @param TIMx Timer instance
4391 * @retval State of bit (1 or 0).
4392 */
LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef * TIMx)4393 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
4394 {
4395 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
4396 }
4397
4398 /**
4399 * @brief Enable capture/compare 4 interrupt (CC4IE).
4400 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
4401 * @param TIMx Timer instance
4402 * @retval None
4403 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)4404 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
4405 {
4406 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4407 }
4408
4409 /**
4410 * @brief Disable capture/compare 4 interrupt (CC4IE).
4411 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
4412 * @param TIMx Timer instance
4413 * @retval None
4414 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)4415 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
4416 {
4417 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4418 }
4419
4420 /**
4421 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
4422 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
4423 * @param TIMx Timer instance
4424 * @retval State of bit (1 or 0).
4425 */
LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef * TIMx)4426 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
4427 {
4428 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
4429 }
4430
4431 /**
4432 * @brief Enable commutation interrupt (COMIE).
4433 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
4434 * @param TIMx Timer instance
4435 * @retval None
4436 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)4437 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
4438 {
4439 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
4440 }
4441
4442 /**
4443 * @brief Disable commutation interrupt (COMIE).
4444 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
4445 * @param TIMx Timer instance
4446 * @retval None
4447 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)4448 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
4449 {
4450 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
4451 }
4452
4453 /**
4454 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
4455 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
4456 * @param TIMx Timer instance
4457 * @retval State of bit (1 or 0).
4458 */
LL_TIM_IsEnabledIT_COM(const TIM_TypeDef * TIMx)4459 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
4460 {
4461 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
4462 }
4463
4464 /**
4465 * @brief Enable trigger interrupt (TIE).
4466 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
4467 * @param TIMx Timer instance
4468 * @retval None
4469 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)4470 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
4471 {
4472 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
4473 }
4474
4475 /**
4476 * @brief Disable trigger interrupt (TIE).
4477 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
4478 * @param TIMx Timer instance
4479 * @retval None
4480 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)4481 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
4482 {
4483 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
4484 }
4485
4486 /**
4487 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
4488 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
4489 * @param TIMx Timer instance
4490 * @retval State of bit (1 or 0).
4491 */
LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef * TIMx)4492 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
4493 {
4494 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
4495 }
4496
4497 /**
4498 * @brief Enable break interrupt (BIE).
4499 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
4500 * @param TIMx Timer instance
4501 * @retval None
4502 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)4503 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
4504 {
4505 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
4506 }
4507
4508 /**
4509 * @brief Disable break interrupt (BIE).
4510 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
4511 * @param TIMx Timer instance
4512 * @retval None
4513 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)4514 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
4515 {
4516 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
4517 }
4518
4519 /**
4520 * @brief Indicates whether the break interrupt (BIE) is enabled.
4521 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
4522 * @param TIMx Timer instance
4523 * @retval State of bit (1 or 0).
4524 */
LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef * TIMx)4525 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
4526 {
4527 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
4528 }
4529
4530 /**
4531 * @}
4532 */
4533
4534 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
4535 * @{
4536 */
4537 /**
4538 * @brief Enable update DMA request (UDE).
4539 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
4540 * @param TIMx Timer instance
4541 * @retval None
4542 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)4543 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4544 {
4545 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
4546 }
4547
4548 /**
4549 * @brief Disable update DMA request (UDE).
4550 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
4551 * @param TIMx Timer instance
4552 * @retval None
4553 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)4554 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4555 {
4556 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
4557 }
4558
4559 /**
4560 * @brief Indicates whether the update DMA request (UDE) is enabled.
4561 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
4562 * @param TIMx Timer instance
4563 * @retval State of bit (1 or 0).
4564 */
LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef * TIMx)4565 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
4566 {
4567 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
4568 }
4569
4570 /**
4571 * @brief Enable capture/compare 1 DMA request (CC1DE).
4572 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
4573 * @param TIMx Timer instance
4574 * @retval None
4575 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)4576 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
4577 {
4578 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4579 }
4580
4581 /**
4582 * @brief Disable capture/compare 1 DMA request (CC1DE).
4583 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
4584 * @param TIMx Timer instance
4585 * @retval None
4586 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)4587 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
4588 {
4589 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4590 }
4591
4592 /**
4593 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
4594 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
4595 * @param TIMx Timer instance
4596 * @retval State of bit (1 or 0).
4597 */
LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef * TIMx)4598 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
4599 {
4600 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
4601 }
4602
4603 /**
4604 * @brief Enable capture/compare 2 DMA request (CC2DE).
4605 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
4606 * @param TIMx Timer instance
4607 * @retval None
4608 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)4609 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
4610 {
4611 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4612 }
4613
4614 /**
4615 * @brief Disable capture/compare 2 DMA request (CC2DE).
4616 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
4617 * @param TIMx Timer instance
4618 * @retval None
4619 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)4620 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
4621 {
4622 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4623 }
4624
4625 /**
4626 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
4627 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
4628 * @param TIMx Timer instance
4629 * @retval State of bit (1 or 0).
4630 */
LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef * TIMx)4631 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
4632 {
4633 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
4634 }
4635
4636 /**
4637 * @brief Enable capture/compare 3 DMA request (CC3DE).
4638 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
4639 * @param TIMx Timer instance
4640 * @retval None
4641 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)4642 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
4643 {
4644 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4645 }
4646
4647 /**
4648 * @brief Disable capture/compare 3 DMA request (CC3DE).
4649 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
4650 * @param TIMx Timer instance
4651 * @retval None
4652 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)4653 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
4654 {
4655 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4656 }
4657
4658 /**
4659 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
4660 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
4661 * @param TIMx Timer instance
4662 * @retval State of bit (1 or 0).
4663 */
LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef * TIMx)4664 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
4665 {
4666 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
4667 }
4668
4669 /**
4670 * @brief Enable capture/compare 4 DMA request (CC4DE).
4671 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
4672 * @param TIMx Timer instance
4673 * @retval None
4674 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)4675 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
4676 {
4677 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4678 }
4679
4680 /**
4681 * @brief Disable capture/compare 4 DMA request (CC4DE).
4682 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
4683 * @param TIMx Timer instance
4684 * @retval None
4685 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)4686 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
4687 {
4688 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4689 }
4690
4691 /**
4692 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
4693 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
4694 * @param TIMx Timer instance
4695 * @retval State of bit (1 or 0).
4696 */
LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef * TIMx)4697 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
4698 {
4699 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
4700 }
4701
4702 /**
4703 * @brief Enable commutation DMA request (COMDE).
4704 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
4705 * @param TIMx Timer instance
4706 * @retval None
4707 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)4708 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
4709 {
4710 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
4711 }
4712
4713 /**
4714 * @brief Disable commutation DMA request (COMDE).
4715 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
4716 * @param TIMx Timer instance
4717 * @retval None
4718 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)4719 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
4720 {
4721 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
4722 }
4723
4724 /**
4725 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
4726 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
4727 * @param TIMx Timer instance
4728 * @retval State of bit (1 or 0).
4729 */
LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef * TIMx)4730 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
4731 {
4732 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
4733 }
4734
4735 /**
4736 * @brief Enable trigger interrupt (TDE).
4737 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
4738 * @param TIMx Timer instance
4739 * @retval None
4740 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)4741 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
4742 {
4743 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
4744 }
4745
4746 /**
4747 * @brief Disable trigger interrupt (TDE).
4748 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
4749 * @param TIMx Timer instance
4750 * @retval None
4751 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)4752 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
4753 {
4754 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
4755 }
4756
4757 /**
4758 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
4759 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
4760 * @param TIMx Timer instance
4761 * @retval State of bit (1 or 0).
4762 */
LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef * TIMx)4763 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
4764 {
4765 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
4766 }
4767
4768 /**
4769 * @}
4770 */
4771
4772 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
4773 * @{
4774 */
4775 /**
4776 * @brief Generate an update event.
4777 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
4778 * @param TIMx Timer instance
4779 * @retval None
4780 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)4781 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
4782 {
4783 SET_BIT(TIMx->EGR, TIM_EGR_UG);
4784 }
4785
4786 /**
4787 * @brief Generate Capture/Compare 1 event.
4788 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
4789 * @param TIMx Timer instance
4790 * @retval None
4791 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)4792 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
4793 {
4794 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
4795 }
4796
4797 /**
4798 * @brief Generate Capture/Compare 2 event.
4799 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
4800 * @param TIMx Timer instance
4801 * @retval None
4802 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)4803 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
4804 {
4805 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
4806 }
4807
4808 /**
4809 * @brief Generate Capture/Compare 3 event.
4810 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
4811 * @param TIMx Timer instance
4812 * @retval None
4813 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)4814 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
4815 {
4816 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
4817 }
4818
4819 /**
4820 * @brief Generate Capture/Compare 4 event.
4821 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
4822 * @param TIMx Timer instance
4823 * @retval None
4824 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)4825 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
4826 {
4827 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
4828 }
4829
4830 /**
4831 * @brief Generate commutation event.
4832 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
4833 * @param TIMx Timer instance
4834 * @retval None
4835 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)4836 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
4837 {
4838 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
4839 }
4840
4841 /**
4842 * @brief Generate trigger event.
4843 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
4844 * @param TIMx Timer instance
4845 * @retval None
4846 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)4847 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
4848 {
4849 SET_BIT(TIMx->EGR, TIM_EGR_TG);
4850 }
4851
4852 /**
4853 * @brief Generate break event.
4854 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
4855 * @param TIMx Timer instance
4856 * @retval None
4857 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)4858 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
4859 {
4860 SET_BIT(TIMx->EGR, TIM_EGR_BG);
4861 }
4862
4863 /**
4864 * @brief Generate break 2 event.
4865 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
4866 * @param TIMx Timer instance
4867 * @retval None
4868 */
LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)4869 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
4870 {
4871 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
4872 }
4873
4874 /**
4875 * @}
4876 */
4877
4878 #if defined(USE_FULL_LL_DRIVER)
4879 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
4880 * @{
4881 */
4882
4883 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
4884 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
4885 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
4886 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4887 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4888 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
4889 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
4890 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4891 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4892 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4893 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4894 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4895 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4896 /**
4897 * @}
4898 */
4899 #endif /* USE_FULL_LL_DRIVER */
4900
4901 /**
4902 * @}
4903 */
4904
4905 /**
4906 * @}
4907 */
4908
4909 #endif /* TIM1 || TIM2 || TIM3 || TIM14 || TIM16 || TIM17 */
4910
4911 /**
4912 * @}
4913 */
4914
4915 #ifdef __cplusplus
4916 }
4917 #endif
4918
4919 #endif /* __STM32C0xx_LL_TIM_H */
4920
