1 /**
2 ******************************************************************************
3 * @file stm32c0xx_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32C0xx_LL_PWR_H
21 #define STM32C0xx_LL_PWR_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32c0xx.h"
29
30 /** @addtogroup STM32C0xx_LL_Driver
31 * @{
32 */
33
34 #if defined(PWR)
35
36 /** @defgroup PWR_LL PWR
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44
45 /* Private macros ------------------------------------------------------------*/
46
47 /* Exported types ------------------------------------------------------------*/
48 /* Exported constants --------------------------------------------------------*/
49 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
50 * @{
51 */
52
53 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
54 * @brief Flags defines which can be used with LL_PWR_WriteReg function
55 * @{
56 */
57 #define LL_PWR_SCR_CSBF PWR_SCR_CSBF
58 #define LL_PWR_SCR_CWUF PWR_SCR_CWUF
59 #define LL_PWR_SCR_CWUF6 PWR_SCR_CWUF6
60 #define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4
61 #define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3
62 #define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2
63 #define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1
64 /**
65 * @}
66 */
67
68 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
69 * @brief Flags defines which can be used with LL_PWR_ReadReg function
70 * @{
71 */
72 #define LL_PWR_SR1_WUFI PWR_SR1_WUFI
73 #define LL_PWR_SR1_SBF PWR_SR1_SBF
74 #define LL_PWR_SR1_WUF6 PWR_SR1_WUF6
75 #define LL_PWR_SR1_WUF4 PWR_SR1_WUF4
76 #define LL_PWR_SR1_WUF3 PWR_SR1_WUF3
77 #define LL_PWR_SR1_WUF2 PWR_SR1_WUF2
78 #define LL_PWR_SR1_WUF1 PWR_SR1_WUF1
79 /**
80 * @}
81 */
82
83
84 /** @defgroup PWR_LL_EC_MODE_PWR MODE PWR
85 * @{
86 */
87 #define LL_PWR_MODE_STOP0 (0x00000000UL)
88 #define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_1|PWR_CR1_LPMS_0)
89 #define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_2)
90 /**
91 * @}
92 */
93
94
95 /** @defgroup PWR_LL_EC_WAKEUP WAKEUP
96 * @{
97 */
98 #define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1)
99 #define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2)
100 #define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3)
101 #define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4)
102 #define LL_PWR_WAKEUP_PIN6 (PWR_CR3_EWUP6)
103 /**
104 * @}
105 */
106
107
108 /** @defgroup PWR_LL_EC_GPIO GPIO
109 * @{
110 */
111 #define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
112 #define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
113 #define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
114 #if defined(STM32C031xx)
115 #define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))
116 #endif /* STM32C031xx */
117 #define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF)))
118 /**
119 * @}
120 */
121
122 /** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT
123 * @{
124 */
125 #define LL_PWR_GPIO_BIT_0 0x00000001u
126 #define LL_PWR_GPIO_BIT_1 0x00000002u
127 #define LL_PWR_GPIO_BIT_2 0x00000004u
128 #define LL_PWR_GPIO_BIT_3 0x00000008u
129 #define LL_PWR_GPIO_BIT_4 0x00000010u
130 #define LL_PWR_GPIO_BIT_5 0x00000020u
131 #define LL_PWR_GPIO_BIT_6 0x00000040u
132 #define LL_PWR_GPIO_BIT_7 0x00000080u
133 #define LL_PWR_GPIO_BIT_8 0x00000100u
134 #define LL_PWR_GPIO_BIT_9 0x00000200u
135 #define LL_PWR_GPIO_BIT_10 0x00000400u
136 #define LL_PWR_GPIO_BIT_11 0x00000800u
137 #define LL_PWR_GPIO_BIT_12 0x00001000u
138 #define LL_PWR_GPIO_BIT_13 0x00002000u
139 #define LL_PWR_GPIO_BIT_14 0x00004000u
140 #define LL_PWR_GPIO_BIT_15 0x00008000u
141 /**
142 * @}
143 */
144
145 /** @defgroup PWR_LL_EC_BKP BACKUP
146 * @{
147 */
148 #define LL_PWR_BKP_NUMBER 4U
149 #define LL_PWR_BKP_DR0 0U
150 #define LL_PWR_BKP_DR1 1U
151 #define LL_PWR_BKP_DR2 2U
152 #define LL_PWR_BKP_DR3 3U
153
154 /**
155 * @}
156 */
157
158 /**
159 * @}
160 */
161
162 /* Exported macro ------------------------------------------------------------*/
163 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
164 * @{
165 */
166
167 /** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros
168 * @{
169 */
170
171 /**
172 * @brief Write a value in PWR register
173 * @param __REG__ Register to be written
174 * @param __VALUE__ Value to be written in the register
175 * @retval None
176 */
177 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
178
179 /**
180 * @brief Read a value in PWR register
181 * @param __REG__ Register to be read
182 * @retval Register value
183 */
184 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
185 /**
186 * @}
187 */
188
189 /**
190 * @}
191 */
192
193
194 /* Exported functions --------------------------------------------------------*/
195 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
196 * @{
197 */
198
199 /** @defgroup PWR_LL_EF_Configuration Configuration
200 * @{
201 */
202
203 /**
204 * @brief Enable Flash Power-down mode during sleep mode
205 * @rmtoll CR1 CFIPD_SLP LL_PWR_EnableFlashPowerDownInSleep
206 * @retval None
207 */
LL_PWR_EnableFlashPowerDownInSleep(void)208 __STATIC_INLINE void LL_PWR_EnableFlashPowerDownInSleep(void)
209 {
210 SET_BIT(PWR->CR1, PWR_CR1_FPD_SLP);
211 }
212
213 /**
214 * @brief Disable Flash Power-down mode during sleep mode
215 * @rmtoll CR1 CFIPD_SLP LL_PWR_DisableFlashPowerDownInSleep
216 * @retval None
217 */
LL_PWR_DisableFlashPowerDownInSleep(void)218 __STATIC_INLINE void LL_PWR_DisableFlashPowerDownInSleep(void)
219 {
220 CLEAR_BIT(PWR->CR1, PWR_CR1_FPD_SLP);
221 }
222
223 /**
224 * @brief Check if flash power-down mode during sleep mode domain is enabled
225 * @rmtoll CR1 CFIPD_SLP LL_PWR_IsEnableFlashPowerDownInSleep
226 * @retval State of bit (1 or 0).
227 */
LL_PWR_IsEnableFlashPowerDownInSleep(void)228 __STATIC_INLINE uint32_t LL_PWR_IsEnableFlashPowerDownInSleep(void)
229 {
230 return ((READ_BIT(PWR->CR1, PWR_CR1_FPD_SLP) == (PWR_CR1_FPD_SLP)) ? 1UL : 0UL);
231 }
232
233 /**
234 * @brief Enable Flash Power-down mode during stop mode
235 * @rmtoll CR1 CFIPD_STOP LL_PWR_EnableFlashPowerDownInStop
236 * @retval None
237 */
LL_PWR_EnableFlashPowerDownInStop(void)238 __STATIC_INLINE void LL_PWR_EnableFlashPowerDownInStop(void)
239 {
240 SET_BIT(PWR->CR1, PWR_CR1_FPD_STOP);
241 }
242
243 /**
244 * @brief Disable Flash Power-down mode during stop mode
245 * @rmtoll CR1 CFIPD_STOP LL_PWR_DisableFlashPowerDownInStop
246 * @retval None
247 */
LL_PWR_DisableFlashPowerDownInStop(void)248 __STATIC_INLINE void LL_PWR_DisableFlashPowerDownInStop(void)
249 {
250 CLEAR_BIT(PWR->CR1, PWR_CR1_FPD_STOP);
251 }
252
253 /**
254 * @brief Check if flash power-down mode during stop mode domain is enabled
255 * @rmtoll CR1 CFIPD_STOP LL_PWR_IsEnableFlashPowerDownInStop
256 * @retval State of bit (1 or 0).
257 */
LL_PWR_IsEnableFlashPowerDownInStop(void)258 __STATIC_INLINE uint32_t LL_PWR_IsEnableFlashPowerDownInStop(void)
259 {
260 return ((READ_BIT(PWR->CR1, PWR_CR1_FPD_STOP) == (PWR_CR1_FPD_STOP)) ? 1UL : 0UL);
261 }
262
263 /**
264 * @brief Set Low-Power mode
265 * @rmtoll CR1 LPMS LL_PWR_SetPowerMode
266 * @param LowPowerMode This parameter can be one of the following values:
267 * @arg @ref LL_PWR_MODE_STOP0
268 * @arg @ref LL_PWR_MODE_STANDBY
269 * @arg @ref LL_PWR_MODE_SHUTDOWN
270 * @retval None
271 */
LL_PWR_SetPowerMode(uint32_t LowPowerMode)272 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode)
273 {
274 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode);
275 }
276
277 /**
278 * @brief Get Low-Power mode
279 * @rmtoll CR1 LPMS LL_PWR_GetPowerMode
280 * @retval Returned value can be one of the following values:
281 * @arg @ref LL_PWR_MODE_STOP0
282 * @arg @ref LL_PWR_MODE_STANDBY
283 * @arg @ref LL_PWR_MODE_SHUTDOWN
284 */
LL_PWR_GetPowerMode(void)285 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
286 {
287 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS));
288 }
289
290 /**
291 * @brief Enable Internal Wake-up line
292 * @rmtoll CR3 EIWF LL_PWR_EnableInternWU
293 * @retval None
294 */
LL_PWR_EnableInternWU(void)295 __STATIC_INLINE void LL_PWR_EnableInternWU(void)
296 {
297 SET_BIT(PWR->CR3, PWR_CR3_EIWUL);
298 }
299
300 /**
301 * @brief Disable Internal Wake-up line
302 * @rmtoll CR3 EIWF LL_PWR_DisableInternWU
303 * @retval None
304 */
LL_PWR_DisableInternWU(void)305 __STATIC_INLINE void LL_PWR_DisableInternWU(void)
306 {
307 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWUL);
308 }
309
310 /**
311 * @brief Check if Internal Wake-up line is enabled
312 * @rmtoll CR3 EIWF LL_PWR_IsEnabledInternWU
313 * @retval State of bit (1 or 0).
314 */
LL_PWR_IsEnabledInternWU(void)315 __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void)
316 {
317 return ((READ_BIT(PWR->CR3, PWR_CR3_EIWUL) == (PWR_CR3_EIWUL)) ? 1UL : 0UL);
318 }
319
320 /**
321 * @brief Enable pull-up and pull-down configuration
322 * @rmtoll CR3 APC LL_PWR_EnablePUPDCfg
323 * @retval None
324 */
LL_PWR_EnablePUPDCfg(void)325 __STATIC_INLINE void LL_PWR_EnablePUPDCfg(void)
326 {
327 SET_BIT(PWR->CR3, PWR_CR3_APC);
328 }
329
330 /**
331 * @brief Disable pull-up and pull-down configuration
332 * @rmtoll CR3 APC LL_PWR_DisablePUPDCfg
333 * @retval None
334 */
LL_PWR_DisablePUPDCfg(void)335 __STATIC_INLINE void LL_PWR_DisablePUPDCfg(void)
336 {
337 CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
338 }
339
340 /**
341 * @brief Check if pull-up and pull-down configuration is enabled
342 * @rmtoll CR3 APC LL_PWR_IsEnabledPUPDCfg
343 * @retval State of bit (1 or 0).
344 */
LL_PWR_IsEnabledPUPDCfg(void)345 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void)
346 {
347 return ((READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)) ? 1UL : 0UL);
348 }
349
350 /**
351 * @brief Enable the WakeUp PINx functionality
352 * @rmtoll CR3 EWUP1 LL_PWR_EnableWakeUpPin\n
353 * CR3 EWUP2 LL_PWR_EnableWakeUpPin\n
354 * CR3 EWUP3 LL_PWR_EnableWakeUpPin\n
355 * CR3 EWUP4 LL_PWR_EnableWakeUpPin\n
356 * CR3 EWUP6 LL_PWR_EnableWakeUpPin
357 * @param WakeUpPin This parameter can be one of the following values:
358 * @arg @ref LL_PWR_WAKEUP_PIN1
359 * @arg @ref LL_PWR_WAKEUP_PIN2
360 * @arg @ref LL_PWR_WAKEUP_PIN3
361 * @arg @ref LL_PWR_WAKEUP_PIN4
362 * @arg @ref LL_PWR_WAKEUP_PIN6
363 * @retval None
364 */
LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)365 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
366 {
367 SET_BIT(PWR->CR3, WakeUpPin);
368 }
369
370 /**
371 * @brief Disable the WakeUp PINx functionality
372 * @rmtoll CR3 EWUP1 LL_PWR_DisableWakeUpPin\n
373 * CR3 EWUP2 LL_PWR_DisableWakeUpPin\n
374 * CR3 EWUP3 LL_PWR_DisableWakeUpPin\n
375 * CR3 EWUP4 LL_PWR_DisableWakeUpPin\n
376 * CR3 EWUP6 LL_PWR_DisableWakeUpPin
377 * @param WakeUpPin This parameter can be one of the following values:
378 * @arg @ref LL_PWR_WAKEUP_PIN1
379 * @arg @ref LL_PWR_WAKEUP_PIN2
380 * @arg @ref LL_PWR_WAKEUP_PIN3
381 * @arg @ref LL_PWR_WAKEUP_PIN4
382 * @arg @ref LL_PWR_WAKEUP_PIN6
383 * @retval None
384 */
LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)385 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
386 {
387 CLEAR_BIT(PWR->CR3, WakeUpPin);
388 }
389
390 /**
391 * @brief Check if the WakeUp PINx functionality is enabled
392 * @rmtoll CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin\n
393 * CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin\n
394 * CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin\n
395 * CR3 EWUP4 LL_PWR_IsEnabledWakeUpPin\n
396 * CR3 EWUP6 LL_PWR_IsEnabledWakeUpPin
397 * @param WakeUpPin This parameter can be one of the following values:
398 * @arg @ref LL_PWR_WAKEUP_PIN1
399 * @arg @ref LL_PWR_WAKEUP_PIN2
400 * @arg @ref LL_PWR_WAKEUP_PIN3
401 * @arg @ref LL_PWR_WAKEUP_PIN4
402 * @arg @ref LL_PWR_WAKEUP_PIN6
403 * @retval State of bit (1 or 0).
404 */
LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)405 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
406 {
407 return ((READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
408 }
409
410
411 /**
412 * @brief Set the Wake-Up pin polarity low for the event detection
413 * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityLow\n
414 * CR4 WP2 LL_PWR_SetWakeUpPinPolarityLow\n
415 * CR4 WP3 LL_PWR_SetWakeUpPinPolarityLow\n
416 * CR4 WP4 LL_PWR_SetWakeUpPinPolarityLow\n
417 * CR4 WP6 LL_PWR_SetWakeUpPinPolarityLow\n
418 * @param WakeUpPin This parameter can be one of the following values:
419 * @arg @ref LL_PWR_WAKEUP_PIN1
420 * @arg @ref LL_PWR_WAKEUP_PIN2
421 * @arg @ref LL_PWR_WAKEUP_PIN3
422 * @arg @ref LL_PWR_WAKEUP_PIN4
423 * @arg @ref LL_PWR_WAKEUP_PIN6
424 * @retval None
425 */
LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)426 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
427 {
428 SET_BIT(PWR->CR4, WakeUpPin);
429 }
430
431 /**
432 * @brief Set the Wake-Up pin polarity high for the event detection
433 * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityHigh\n
434 * CR4 WP2 LL_PWR_SetWakeUpPinPolarityHigh\n
435 * CR4 WP3 LL_PWR_SetWakeUpPinPolarityHigh\n
436 * CR4 WP4 LL_PWR_SetWakeUpPinPolarityHigh\n
437 * CR4 WP6 LL_PWR_SetWakeUpPinPolarityHigh
438 * @param WakeUpPin This parameter can be one of the following values:
439 * @arg @ref LL_PWR_WAKEUP_PIN1
440 * @arg @ref LL_PWR_WAKEUP_PIN2
441 * @arg @ref LL_PWR_WAKEUP_PIN3
442 * @arg @ref LL_PWR_WAKEUP_PIN4
443 * @arg @ref LL_PWR_WAKEUP_PIN6
444 * @retval None
445 */
LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)446 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
447 {
448 CLEAR_BIT(PWR->CR4, WakeUpPin);
449 }
450
451 /**
452 * @brief Get the Wake-Up pin polarity for the event detection
453 * @rmtoll CR4 WP1 LL_PWR_IsWakeUpPinPolarityLow\n
454 * CR4 WP2 LL_PWR_IsWakeUpPinPolarityLow\n
455 * CR4 WP3 LL_PWR_IsWakeUpPinPolarityLow\n
456 * CR4 WP4 LL_PWR_IsWakeUpPinPolarityLow\n
457 * CR4 WP6 LL_PWR_IsWakeUpPinPolarityLow
458 * @param WakeUpPin This parameter can be one of the following values:
459 * @arg @ref LL_PWR_WAKEUP_PIN1
460 * @arg @ref LL_PWR_WAKEUP_PIN2
461 * @arg @ref LL_PWR_WAKEUP_PIN3
462 * @arg @ref LL_PWR_WAKEUP_PIN4
463 * @arg @ref LL_PWR_WAKEUP_PIN6
464 * @retval State of bit (1 or 0).
465 */
LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)466 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
467 {
468 return ((READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
469 }
470
471 /**
472 * @brief Enable GPIO pull-up state in Standby and Shutdown modes
473 * @rmtoll PUCRA PU0-15 LL_PWR_EnableGPIOPullUp\n
474 * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n
475 * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n
476 * PUCRD PU0-15 LL_PWR_EnableGPIOPullUp\n
477 * (+) Port D is available only for STM32C031xx devices.
478 * PUCRF PU0-15 LL_PWR_EnableGPIOPullUp
479 * @param GPIO This parameter can be one of the following values:
480 * @arg @ref LL_PWR_GPIO_A
481 * @arg @ref LL_PWR_GPIO_B
482 * @arg @ref LL_PWR_GPIO_C
483 * @arg @ref LL_PWR_GPIO_D
484 * (+) Port D is available only for STM32C031xx devices.
485 * @arg @ref LL_PWR_GPIO_F
486 * @param GPIONumber This parameter can be one of the following values:
487 * @arg @ref LL_PWR_GPIO_BIT_0
488 * @arg @ref LL_PWR_GPIO_BIT_1
489 * @arg @ref LL_PWR_GPIO_BIT_2
490 * @arg @ref LL_PWR_GPIO_BIT_3
491 * @arg @ref LL_PWR_GPIO_BIT_4
492 * @arg @ref LL_PWR_GPIO_BIT_5
493 * @arg @ref LL_PWR_GPIO_BIT_6
494 * @arg @ref LL_PWR_GPIO_BIT_7
495 * @arg @ref LL_PWR_GPIO_BIT_8
496 * @arg @ref LL_PWR_GPIO_BIT_9
497 * @arg @ref LL_PWR_GPIO_BIT_10
498 * @arg @ref LL_PWR_GPIO_BIT_11
499 * @arg @ref LL_PWR_GPIO_BIT_12
500 * @arg @ref LL_PWR_GPIO_BIT_13
501 * @arg @ref LL_PWR_GPIO_BIT_14
502 * @arg @ref LL_PWR_GPIO_BIT_15
503 * @retval None
504 */
LL_PWR_EnableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)505 __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
506 {
507 SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
508 }
509
510 /**
511 * @brief Disable GPIO pull-up state in Standby and Shutdown modes
512 * @rmtoll PUCRA PU0-15 LL_PWR_DisableGPIOPullUp\n
513 * PUCRB PU0-15 LL_PWR_DisableGPIOPullUp\n
514 * PUCRC PU0-15 LL_PWR_DisableGPIOPullUp\n
515 * PUCRD PU0-15 LL_PWR_DisableGPIOPullUp\n
516 * (+) Port D is available only for STM32C031xx devices.
517 * PUCRF PU0-15 LL_PWR_DisableGPIOPullUp
518 * @param GPIO This parameter can be one of the following values:
519 * @arg @ref LL_PWR_GPIO_A
520 * @arg @ref LL_PWR_GPIO_B
521 * @arg @ref LL_PWR_GPIO_C
522 * @arg @ref LL_PWR_GPIO_D
523 * (+) Port D is available only for STM32C031xx devices.
524 * @arg @ref LL_PWR_GPIO_F
525 * @param GPIONumber This parameter can be one of the following values:
526 * @arg @ref LL_PWR_GPIO_BIT_0
527 * @arg @ref LL_PWR_GPIO_BIT_1
528 * @arg @ref LL_PWR_GPIO_BIT_2
529 * @arg @ref LL_PWR_GPIO_BIT_3
530 * @arg @ref LL_PWR_GPIO_BIT_4
531 * @arg @ref LL_PWR_GPIO_BIT_5
532 * @arg @ref LL_PWR_GPIO_BIT_6
533 * @arg @ref LL_PWR_GPIO_BIT_7
534 * @arg @ref LL_PWR_GPIO_BIT_8
535 * @arg @ref LL_PWR_GPIO_BIT_9
536 * @arg @ref LL_PWR_GPIO_BIT_10
537 * @arg @ref LL_PWR_GPIO_BIT_11
538 * @arg @ref LL_PWR_GPIO_BIT_12
539 * @arg @ref LL_PWR_GPIO_BIT_13
540 * @arg @ref LL_PWR_GPIO_BIT_14
541 * @arg @ref LL_PWR_GPIO_BIT_15
542 * @retval None
543 */
LL_PWR_DisableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)544 __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
545 {
546 CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
547 }
548
549 /**
550 * @brief Check if GPIO pull-up state is enabled
551 * @rmtoll PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
552 * PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
553 * PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
554 * PUCRD PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
555 * (+) Port D is available only for STM32C031xx devices.
556 * PUCRF PU0-15 LL_PWR_IsEnabledGPIOPullUp
557 * @param GPIO This parameter can be one of the following values:
558 * @arg @ref LL_PWR_GPIO_A
559 * @arg @ref LL_PWR_GPIO_B
560 * @arg @ref LL_PWR_GPIO_C
561 * @arg @ref LL_PWR_GPIO_D
562 * (+) Port D is available only for STM32C031xx devices.
563 * @arg @ref LL_PWR_GPIO_F
564 * @param GPIONumber This parameter can be one of the following values:
565 * @arg @ref LL_PWR_GPIO_BIT_0
566 * @arg @ref LL_PWR_GPIO_BIT_1
567 * @arg @ref LL_PWR_GPIO_BIT_2
568 * @arg @ref LL_PWR_GPIO_BIT_3
569 * @arg @ref LL_PWR_GPIO_BIT_4
570 * @arg @ref LL_PWR_GPIO_BIT_5
571 * @arg @ref LL_PWR_GPIO_BIT_6
572 * @arg @ref LL_PWR_GPIO_BIT_7
573 * @arg @ref LL_PWR_GPIO_BIT_8
574 * @arg @ref LL_PWR_GPIO_BIT_9
575 * @arg @ref LL_PWR_GPIO_BIT_10
576 * @arg @ref LL_PWR_GPIO_BIT_11
577 * @arg @ref LL_PWR_GPIO_BIT_12
578 * @arg @ref LL_PWR_GPIO_BIT_13
579 * @arg @ref LL_PWR_GPIO_BIT_14
580 * @arg @ref LL_PWR_GPIO_BIT_15
581 * @retval State of bit (1 or 0).
582 */
LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)583 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
584 {
585 return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
586 }
587
588 /**
589 * @brief Enable GPIO pull-down state in Standby and Shutdown modes
590 * @rmtoll PDCRA PD0-15 LL_PWR_EnableGPIOPullDown\n
591 * PDCRB PD0-15 LL_PWR_EnableGPIOPullDown\n
592 * PDCRC PD0-15 LL_PWR_EnableGPIOPullDown\n
593 * PDCRD PD0-15 LL_PWR_EnableGPIOPullDown\n
594 * (+) Port D is available only for STM32C031xx devices.
595 * PDCRF PD0-15 LL_PWR_EnableGPIOPullDown
596 * @param GPIO This parameter can be one of the following values:
597 * @arg @ref LL_PWR_GPIO_A
598 * @arg @ref LL_PWR_GPIO_B
599 * @arg @ref LL_PWR_GPIO_C
600 * @arg @ref LL_PWR_GPIO_D
601 * (+) Port D is available only for STM32C031xx devices.
602 * @arg @ref LL_PWR_GPIO_F
603 * @param GPIONumber This parameter can be one of the following values:
604 * @arg @ref LL_PWR_GPIO_BIT_0
605 * @arg @ref LL_PWR_GPIO_BIT_1
606 * @arg @ref LL_PWR_GPIO_BIT_2
607 * @arg @ref LL_PWR_GPIO_BIT_3
608 * @arg @ref LL_PWR_GPIO_BIT_4
609 * @arg @ref LL_PWR_GPIO_BIT_5
610 * @arg @ref LL_PWR_GPIO_BIT_6
611 * @arg @ref LL_PWR_GPIO_BIT_7
612 * @arg @ref LL_PWR_GPIO_BIT_8
613 * @arg @ref LL_PWR_GPIO_BIT_9
614 * @arg @ref LL_PWR_GPIO_BIT_10
615 * @arg @ref LL_PWR_GPIO_BIT_11
616 * @arg @ref LL_PWR_GPIO_BIT_12
617 * @arg @ref LL_PWR_GPIO_BIT_13
618 * @arg @ref LL_PWR_GPIO_BIT_14
619 * @arg @ref LL_PWR_GPIO_BIT_15
620 * @retval None
621 */
LL_PWR_EnableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)622 __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
623 {
624 SET_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
625 }
626
627 /**
628 * @brief Disable GPIO pull-down state in Standby and Shutdown modes
629 * @rmtoll PDCRA PD0-15 LL_PWR_DisableGPIOPullDown\n
630 * PDCRB PD0-15 LL_PWR_DisableGPIOPullDown\n
631 * PDCRC PD0-15 LL_PWR_DisableGPIOPullDown\n
632 * PDCRD PD0-15 LL_PWR_DisableGPIOPullDown\n
633 * (+) Port D is available only for STM32C031xx devices.
634 * PDCRF PD0-15 LL_PWR_DisableGPIOPullDown
635 * @param GPIO This parameter can be one of the following values:
636 * @arg @ref LL_PWR_GPIO_A
637 * @arg @ref LL_PWR_GPIO_B
638 * @arg @ref LL_PWR_GPIO_C
639 * @arg @ref LL_PWR_GPIO_D
640 * (+) Port D is available only for STM32C031xx devices.
641 * @arg @ref LL_PWR_GPIO_F
642 * @param GPIONumber This parameter can be one of the following values:
643 * @arg @ref LL_PWR_GPIO_BIT_0
644 * @arg @ref LL_PWR_GPIO_BIT_1
645 * @arg @ref LL_PWR_GPIO_BIT_2
646 * @arg @ref LL_PWR_GPIO_BIT_3
647 * @arg @ref LL_PWR_GPIO_BIT_4
648 * @arg @ref LL_PWR_GPIO_BIT_5
649 * @arg @ref LL_PWR_GPIO_BIT_6
650 * @arg @ref LL_PWR_GPIO_BIT_7
651 * @arg @ref LL_PWR_GPIO_BIT_8
652 * @arg @ref LL_PWR_GPIO_BIT_9
653 * @arg @ref LL_PWR_GPIO_BIT_10
654 * @arg @ref LL_PWR_GPIO_BIT_11
655 * @arg @ref LL_PWR_GPIO_BIT_12
656 * @arg @ref LL_PWR_GPIO_BIT_13
657 * @arg @ref LL_PWR_GPIO_BIT_14
658 * @arg @ref LL_PWR_GPIO_BIT_15
659 * @retval None
660 */
LL_PWR_DisableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)661 __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
662 {
663 CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
664 }
665
666 /**
667 * @brief Check if GPIO pull-down state is enabled
668 * @rmtoll PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
669 * PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
670 * PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
671 * PDCRD PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
672 * (+) Port D is available only for STM32C031xx devices.
673 * PDCRF PD0-15 LL_PWR_IsEnabledGPIOPullDown
674 * @param GPIO This parameter can be one of the following values:
675 * @arg @ref LL_PWR_GPIO_A
676 * @arg @ref LL_PWR_GPIO_B
677 * @arg @ref LL_PWR_GPIO_C
678 * @arg @ref LL_PWR_GPIO_D
679 * (+) Port D is available only for STM32C031xx devices.
680 * @arg @ref LL_PWR_GPIO_F
681 * @param GPIONumber This parameter can be one of the following values:
682 * @arg @ref LL_PWR_GPIO_BIT_0
683 * @arg @ref LL_PWR_GPIO_BIT_1
684 * @arg @ref LL_PWR_GPIO_BIT_2
685 * @arg @ref LL_PWR_GPIO_BIT_3
686 * @arg @ref LL_PWR_GPIO_BIT_4
687 * @arg @ref LL_PWR_GPIO_BIT_5
688 * @arg @ref LL_PWR_GPIO_BIT_6
689 * @arg @ref LL_PWR_GPIO_BIT_7
690 * @arg @ref LL_PWR_GPIO_BIT_8
691 * @arg @ref LL_PWR_GPIO_BIT_9
692 * @arg @ref LL_PWR_GPIO_BIT_10
693 * @arg @ref LL_PWR_GPIO_BIT_11
694 * @arg @ref LL_PWR_GPIO_BIT_12
695 * @arg @ref LL_PWR_GPIO_BIT_13
696 * @arg @ref LL_PWR_GPIO_BIT_14
697 * @arg @ref LL_PWR_GPIO_BIT_15
698 * @retval State of bit (1 or 0).
699 */
LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)700 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
701 {
702 return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
703 }
704
705 /**
706 * @}
707 */
708
709 /** @defgroup PWR_LL_EF_Backup_Registers Backup_Registers
710 * @{
711 */
712
713 /**
714 * @brief Writes a data in a specified Backup data register.
715 * @rmtoll PWR_BKPREGx BKP LL_PWR_BKP_SetRegister
716 * @param BackupRegister This parameter can be one of the following values:
717 * @arg @ref LL_PWR_BKP_DR0
718 * @arg @ref LL_PWR_BKP_DR1
719 * @arg @ref LL_PWR_BKP_DR2
720 * @arg @ref LL_PWR_BKP_DR3
721 * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFF
722 * @retval None
723 */
LL_PWR_BKP_SetRegister(uint32_t BackupRegister,uint16_t Data)724 __STATIC_INLINE void LL_PWR_BKP_SetRegister(uint32_t BackupRegister, uint16_t Data)
725 {
726 __IO uint32_t tmp;
727
728 tmp = (uint32_t)(&(PWR->BKP0R));
729 tmp += (BackupRegister * 4U);
730
731 /* Write the specified register */
732 *(__IO uint32_t *)tmp = (uint16_t)Data;
733 }
734
735 /**
736 * @brief Reads data from the specified Backup data Register.
737 * @rmtoll PWR_BKPREGx BKP LL_PWR_BKP_GetRegister
738 * @param BackupRegister This parameter can be one of the following values:
739 * @arg @ref LL_PWR_BKP_DR0
740 * @arg @ref LL_PWR_BKP_DR1
741 * @arg @ref LL_PWR_BKP_DR2
742 * @arg @ref LL_PWR_BKP_DR3
743 * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
744 */
LL_PWR_BKP_GetRegister(uint32_t BackupRegister)745 __STATIC_INLINE uint32_t LL_PWR_BKP_GetRegister(uint32_t BackupRegister)
746 {
747 uint32_t tmp;
748
749 tmp = (uint32_t)(&(PWR->BKP0R));
750 tmp += (BackupRegister * 4U);
751
752 /* Read the specified register */
753 return (*(__IO uint32_t *)tmp);
754 }
755
756 /**
757 * @}
758 */
759
760 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
761 * @{
762 */
763
764 /**
765 * @brief Get Internal Wake-up line Flag
766 * @rmtoll SR1 WUFI LL_PWR_IsActiveFlag_InternWU
767 * @retval State of bit (1 or 0).
768 */
LL_PWR_IsActiveFlag_InternWU(void)769 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void)
770 {
771 return ((READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)) ? 1UL : 0UL);
772 }
773
774 /**
775 * @brief Get Stand-By Flag
776 * @rmtoll SR1 SBF LL_PWR_IsActiveFlag_SB
777 * @retval State of bit (1 or 0).
778 */
LL_PWR_IsActiveFlag_SB(void)779 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
780 {
781 return ((READ_BIT(PWR->SR1, PWR_SR1_SBF) == (PWR_SR1_SBF)) ? 1UL : 0UL);
782 }
783
784 /**
785 * @brief Get Wake-up Flag 6
786 * @rmtoll SR1 WUF6 LL_PWR_IsActiveFlag_WU6
787 * @retval State of bit (1 or 0).
788 */
LL_PWR_IsActiveFlag_WU6(void)789 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)
790 {
791 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF6) == (PWR_SR1_WUF6)) ? 1UL : 0UL);
792 }
793
794
795 /**
796 * @brief Get Wake-up Flag 4
797 * @rmtoll SR1 WUF4 LL_PWR_IsActiveFlag_WU4
798 * @retval State of bit (1 or 0).
799 */
LL_PWR_IsActiveFlag_WU4(void)800 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
801 {
802 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)) ? 1UL : 0UL);
803 }
804
805 /**
806 * @brief Get Wake-up Flag 3
807 * @rmtoll SR1 WUF3 LL_PWR_IsActiveFlag_WU3
808 * @retval State of bit (1 or 0).
809 */
LL_PWR_IsActiveFlag_WU3(void)810 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
811 {
812 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL);
813 }
814
815
816 /**
817 * @brief Get Wake-up Flag 2
818 * @rmtoll SR1 WUF2 LL_PWR_IsActiveFlag_WU2
819 * @retval State of bit (1 or 0).
820 */
LL_PWR_IsActiveFlag_WU2(void)821 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
822 {
823 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)) ? 1UL : 0UL);
824 }
825
826 /**
827 * @brief Get Wake-up Flag 1
828 * @rmtoll SR1 WUF1 LL_PWR_IsActiveFlag_WU1
829 * @retval State of bit (1 or 0).
830 */
LL_PWR_IsActiveFlag_WU1(void)831 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
832 {
833 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)) ? 1UL : 0UL);
834 }
835
836 /**
837 * @brief Clear Stand-By Flag
838 * @rmtoll SCR CSBF LL_PWR_ClearFlag_SB
839 * @retval None
840 */
LL_PWR_ClearFlag_SB(void)841 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
842 {
843 WRITE_REG(PWR->SCR, PWR_SCR_CSBF);
844 }
845
846 /**
847 * @brief Clear Wake-up Flags
848 * @rmtoll SCR CWUF LL_PWR_ClearFlag_WU
849 * @retval None
850 */
LL_PWR_ClearFlag_WU(void)851 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
852 {
853 WRITE_REG(PWR->SCR, PWR_SCR_CWUF);
854 }
855
856 /**
857 * @brief Clear Wake-up Flag 6
858 * @rmtoll SCR CWUF6 LL_PWR_ClearFlag_WU6
859 * @retval None
860 */
LL_PWR_ClearFlag_WU6(void)861 __STATIC_INLINE void LL_PWR_ClearFlag_WU6(void)
862 {
863 WRITE_REG(PWR->SCR, PWR_SCR_CWUF6);
864 }
865
866 /**
867 * @brief Clear Wake-up Flag 4
868 * @rmtoll SCR CWUF4 LL_PWR_ClearFlag_WU4
869 * @retval None
870 */
LL_PWR_ClearFlag_WU4(void)871 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
872 {
873 WRITE_REG(PWR->SCR, PWR_SCR_CWUF4);
874 }
875
876 /**
877 * @brief Clear Wake-up Flag 3
878 * @rmtoll SCR CWUF3 LL_PWR_ClearFlag_WU3
879 * @retval None
880 */
LL_PWR_ClearFlag_WU3(void)881 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
882 {
883 WRITE_REG(PWR->SCR, PWR_SCR_CWUF3);
884 }
885
886 /**
887 * @brief Clear Wake-up Flag 2
888 * @rmtoll SCR CWUF2 LL_PWR_ClearFlag_WU2
889 * @retval None
890 */
LL_PWR_ClearFlag_WU2(void)891 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
892 {
893 WRITE_REG(PWR->SCR, PWR_SCR_CWUF2);
894 }
895
896 /**
897 * @brief Clear Wake-up Flag 1
898 * @rmtoll SCR CWUF1 LL_PWR_ClearFlag_WU1
899 * @retval None
900 */
LL_PWR_ClearFlag_WU1(void)901 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
902 {
903 WRITE_REG(PWR->SCR, PWR_SCR_CWUF1);
904 }
905
906 /**
907 * @brief Indicate whether or not the flash is ready to be accessed
908 * @rmtoll SR2 FLASH_RDY LL_PWR_IsActiveFlag_FLASH_RDY
909 * @retval State of bit (1 or 0).
910 */
LL_PWR_IsActiveFlag_FLASH_RDY(void)911 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_FLASH_RDY(void)
912 {
913 return ((READ_BIT(PWR->SR2, PWR_SR2_FLASH_RDY) == (PWR_SR2_FLASH_RDY)) ? 1UL : 0UL);
914 }
915
916
917 /**
918 * @}
919 */
920
921 #if defined(USE_FULL_LL_DRIVER)
922 /** @defgroup PWR_LL_EF_Init De-initialization function
923 * @{
924 */
925 ErrorStatus LL_PWR_DeInit(void);
926 /**
927 * @}
928 */
929 #endif /* USE_FULL_LL_DRIVER */
930
931 /**
932 * @}
933 */
934
935 /**
936 * @}
937 */
938
939 #endif /* defined(PWR) */
940
941 /**
942 * @}
943 */
944
945 #ifdef __cplusplus
946 }
947 #endif
948
949 #endif /* STM32C0xx_LL_PWR_H */
950
