1 /**
2 ******************************************************************************
3 * @file stm32c0xx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32C0xx_LL_DMA_H
21 #define STM32C0xx_LL_DMA_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32c0xx.h"
29 #include "stm32c0xx_ll_dmamux.h"
30
31 /** @addtogroup STM32C0xx_LL_Driver
32 * @{
33 */
34
35 #if defined (DMA1)
36
37 /** @defgroup DMA_LL DMA
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
44 * @{
45 */
46 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
47 static const uint8_t CHANNEL_OFFSET_TAB[] =
48 {
49 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
50 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
51 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE)
52 };
53 /**
54 * @}
55 */
56
57 /* Private constants ---------------------------------------------------------*/
58 /* Private macros ------------------------------------------------------------*/
59 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
60 * @{
61 */
62 /**
63 * @}
64 */
65
66 /* Exported types ------------------------------------------------------------*/
67 #if defined(USE_FULL_LL_DRIVER)
68 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
69 * @{
70 */
71 typedef struct
72 {
73 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
74 or as Source base address in case of memory to memory transfer direction.
75
76 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF */
77
78 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
79 or as Destination base address in case of memory to memory transfer direction.
80
81 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF */
82
83 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
84 from memory to memory or from peripheral to memory.
85 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
86
87 This feature can be modified afterwards using unitary function
88 @ref LL_DMA_SetDataTransferDirection(). */
89
90 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
91 This parameter can be a value of @ref DMA_LL_EC_MODE
92 @note: The circular buffer mode cannot be used if the memory to memory
93 data transfer direction is configured on the selected Channel
94
95 This feature can be modified afterwards using unitary function
96 @ref LL_DMA_SetMode(). */
97
98 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to
99 memory transfer directionis incremented or not.
100 This parameter can be a value of @ref DMA_LL_EC_PERIPH
101
102 This feature can be modified afterwards using unitary function
103 @ref LL_DMA_SetPeriphIncMode(). */
104
105 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to
106 memory transfer direction is incremented or not.
107 This parameter can be a value of @ref DMA_LL_EC_MEMORY
108
109 This feature can be modified afterwards using unitary function
110 @ref LL_DMA_SetMemoryIncMode(). */
111
112 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment
113 (byte, half word, word)in case of memory to memory transfer direction.
114 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
115
116 This feature can be modified afterwards using unitary function
117 @ref LL_DMA_SetPeriphSize(). */
118
119 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment
120 (byte, half word, word) in case of memory to memory transfer direction.
121 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
122
123 This feature can be modified afterwards using unitary function
124 @ref LL_DMA_SetMemorySize(). */
125
126 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
127 The data unit is equal to the source buffer configuration set in PeripheralSize
128 or MemorySize parameters depending in the transfer direction.
129 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
130
131 This feature can be modified afterwards using unitary function
132 @ref LL_DMA_SetDataLength(). */
133
134 uint32_t PeriphRequest; /*!< Specifies the peripheral request.
135 This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
136
137 This feature can be modified afterwards using unitary function
138 @ref LL_DMA_SetPeriphRequest(). */
139
140 uint32_t Priority; /*!< Specifies the channel priority level.
141 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
142
143 This feature can be modified afterwards using unitary function
144 @ref LL_DMA_SetChannelPriorityLevel(). */
145
146 } LL_DMA_InitTypeDef;
147 /**
148 * @}
149 */
150 #endif /*USE_FULL_LL_DRIVER*/
151
152 /* Exported constants --------------------------------------------------------*/
153 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
154 * @{
155 */
156 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
157 * @brief Flags defines which can be used with LL_DMA_WriteReg function
158 * @{
159 */
160 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
161 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
162 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
163 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
164 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
165 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
166 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
167 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
168 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
169 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
170 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
171 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
172 /**
173 * @}
174 */
175
176 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
177 * @brief Flags defines which can be used with LL_DMA_ReadReg function
178 * @{
179 */
180 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
181 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
182 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
183 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
184 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
185 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
186 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
187 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
188 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
189 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
190 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
191 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
192 /**
193 * @}
194 */
195
196 /** @defgroup DMA_LL_EC_IT IT Defines
197 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
198 * @{
199 */
200 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
201 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
202 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
203 /**
204 * @}
205 */
206
207 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
208 * @{
209 */
210 #define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */
211 #define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */
212 #define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */
213 #if defined(USE_FULL_LL_DRIVER)
214 #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function
215 @ref LL_DMA_DeInit(). */
216 #endif /*USE_FULL_LL_DRIVER*/
217 /**
218 * @}
219 */
220
221 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
222 * @{
223 */
224 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
225 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
226 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
227 /**
228 * @}
229 */
230
231 /** @defgroup DMA_LL_EC_MODE Transfer mode
232 * @{
233 */
234 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
235 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
236 /**
237 * @}
238 */
239
240 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
241 * @{
242 */
243 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
244 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
245 /**
246 * @}
247 */
248
249 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
250 * @{
251 */
252 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
253 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
254 /**
255 * @}
256 */
257
258 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
259 * @{
260 */
261 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
262 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
263 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
264 /**
265 * @}
266 */
267
268 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
269 * @{
270 */
271 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
272 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
273 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
274 /**
275 * @}
276 */
277
278 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
279 * @{
280 */
281 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
282 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
283 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
284 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
285 /**
286 * @}
287 */
288
289 /**
290 * @}
291 */
292
293 /* Exported macro ------------------------------------------------------------*/
294 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
295 * @{
296 */
297
298 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
299 * @{
300 */
301 /**
302 * @brief Write a value in DMA register
303 * @param __INSTANCE__ DMA Instance
304 * @param __REG__ Register to be written
305 * @param __VALUE__ Value to be written in the register
306 * @retval None
307 */
308 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
309
310 /**
311 * @brief Read a value in DMA register
312 * @param __INSTANCE__ DMA Instance
313 * @param __REG__ Register to be read
314 * @retval Register value
315 */
316 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
317 /**
318 * @}
319 */
320
321 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
322 * @{
323 */
324 /**
325 * @brief Convert DMAx_Channely into DMAx
326 * @param __CHANNEL_INSTANCE__ DMAx_Channely
327 * @retval DMAx
328 */
329 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
330
331 /**
332 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
333 * @param __CHANNEL_INSTANCE__ DMAx_Channely
334 * @retval LL_DMA_CHANNEL_y
335 */
336 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
337 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
338 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
339 LL_DMA_CHANNEL_3)
340
341 /**
342 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
343 * @param __DMA_INSTANCE__ DMAx
344 * @param __CHANNEL__ LL_DMA_CHANNEL_y
345 * @retval DMAx_Channely
346 */
347
348 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
349 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == \
350 ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
351 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == \
352 ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
353 DMA1_Channel3)
354
355
356 /**
357 * @}
358 */
359
360 /**
361 * @}
362 */
363
364 /* Exported functions --------------------------------------------------------*/
365 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
366 * @{
367 */
368
369 /** @defgroup DMA_LL_EF_Configuration Configuration
370 * @{
371 */
372 /**
373 * @brief Enable DMA channel.
374 * @rmtoll CCR EN LL_DMA_EnableChannel
375 * @param DMAx DMAx Instance
376 * @param Channel This parameter can be one of the following values:
377 * @arg @ref LL_DMA_CHANNEL_1
378 * @arg @ref LL_DMA_CHANNEL_2
379 * @arg @ref LL_DMA_CHANNEL_3
380 * @retval None
381 */
LL_DMA_EnableChannel(DMA_TypeDef * DMAx,uint32_t Channel)382 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
383 {
384 uint32_t dma_base_addr = (uint32_t)DMAx;
385 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_EN);
386 }
387
388 /**
389 * @brief Disable DMA channel.
390 * @rmtoll CCR EN LL_DMA_DisableChannel
391 * @param DMAx DMAx Instance
392 * @param Channel This parameter can be one of the following values:
393 * @arg @ref LL_DMA_CHANNEL_1
394 * @arg @ref LL_DMA_CHANNEL_2
395 * @arg @ref LL_DMA_CHANNEL_3
396 * @retval None
397 */
LL_DMA_DisableChannel(DMA_TypeDef * DMAx,uint32_t Channel)398 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
399 {
400 uint32_t dma_base_addr = (uint32_t)DMAx;
401 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_EN);
402 }
403
404 /**
405 * @brief Check if DMA channel is enabled or disabled.
406 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
407 * @param DMAx DMAx Instance
408 * @param Channel This parameter can be one of the following values:
409 * @arg @ref LL_DMA_CHANNEL_1
410 * @arg @ref LL_DMA_CHANNEL_2
411 * @arg @ref LL_DMA_CHANNEL_3
412 * @retval State of bit (1 or 0).
413 */
LL_DMA_IsEnabledChannel(DMA_TypeDef * DMAx,uint32_t Channel)414 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
415 {
416 uint32_t dma_base_addr = (uint32_t)DMAx;
417 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR,
418 DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL);
419 }
420
421 /**
422 * @brief Configure all parameters link to DMA transfer.
423 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
424 * CCR MEM2MEM LL_DMA_ConfigTransfer\n
425 * CCR CIRC LL_DMA_ConfigTransfer\n
426 * CCR PINC LL_DMA_ConfigTransfer\n
427 * CCR MINC LL_DMA_ConfigTransfer\n
428 * CCR PSIZE LL_DMA_ConfigTransfer\n
429 * CCR MSIZE LL_DMA_ConfigTransfer\n
430 * CCR PL LL_DMA_ConfigTransfer
431 * @param DMAx DMAx Instance
432 * @param Channel This parameter can be one of the following values:
433 * @arg @ref LL_DMA_CHANNEL_1
434 * @arg @ref LL_DMA_CHANNEL_2
435 * @arg @ref LL_DMA_CHANNEL_3
436 * @param Configuration This parameter must be a combination of all the following values:
437 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or
438 @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
439 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
440 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
441 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
442 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
443 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
444 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or
445 @ref LL_DMA_PRIORITY_VERYHIGH
446 * @retval None
447 */
LL_DMA_ConfigTransfer(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)448 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
449 {
450 uint32_t dma_base_addr = (uint32_t)DMAx;
451 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR,
452 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | \
453 DMA_CCR_MSIZE | DMA_CCR_PL, Configuration);
454 }
455
456 /**
457 * @brief Set Data transfer direction (read from peripheral or from memory).
458 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
459 * CCR MEM2MEM LL_DMA_SetDataTransferDirection
460 * @param DMAx DMAx Instance
461 * @param Channel This parameter can be one of the following values:
462 * @arg @ref LL_DMA_CHANNEL_1
463 * @arg @ref LL_DMA_CHANNEL_2
464 * @arg @ref LL_DMA_CHANNEL_3
465 * @param Direction This parameter can be one of the following values:
466 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
467 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
468 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
469 * @retval None
470 */
LL_DMA_SetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Direction)471 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
472 {
473 uint32_t dma_base_addr = (uint32_t)DMAx;
474 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR,
475 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
476 }
477
478 /**
479 * @brief Get Data transfer direction (read from peripheral or from memory).
480 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
481 * CCR MEM2MEM LL_DMA_GetDataTransferDirection
482 * @param DMAx DMAx Instance
483 * @param Channel This parameter can be one of the following values:
484 * @arg @ref LL_DMA_CHANNEL_1
485 * @arg @ref LL_DMA_CHANNEL_2
486 * @arg @ref LL_DMA_CHANNEL_3
487 * @retval Returned value can be one of the following values:
488 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
489 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
490 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
491 */
LL_DMA_GetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel)492 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
493 {
494 uint32_t dma_base_addr = (uint32_t)DMAx;
495 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR,
496 DMA_CCR_DIR | DMA_CCR_MEM2MEM));
497 }
498
499 /**
500 * @brief Set DMA mode circular or normal.
501 * @note The circular buffer mode cannot be used if the memory-to-memory
502 * data transfer is configured on the selected Channel.
503 * @rmtoll CCR CIRC LL_DMA_SetMode
504 * @param DMAx DMAx Instance
505 * @param Channel This parameter can be one of the following values:
506 * @arg @ref LL_DMA_CHANNEL_1
507 * @arg @ref LL_DMA_CHANNEL_2
508 * @arg @ref LL_DMA_CHANNEL_3
509 * @param Mode This parameter can be one of the following values:
510 * @arg @ref LL_DMA_MODE_NORMAL
511 * @arg @ref LL_DMA_MODE_CIRCULAR
512 * @retval None
513 */
LL_DMA_SetMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Mode)514 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
515 {
516 uint32_t dma_base_addr = (uint32_t)DMAx;
517 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_CIRC,
518 Mode);
519 }
520
521 /**
522 * @brief Get DMA mode circular or normal.
523 * @rmtoll CCR CIRC LL_DMA_GetMode
524 * @param DMAx DMAx Instance
525 * @param Channel This parameter can be one of the following values:
526 * @arg @ref LL_DMA_CHANNEL_1
527 * @arg @ref LL_DMA_CHANNEL_2
528 * @arg @ref LL_DMA_CHANNEL_3
529 * @retval Returned value can be one of the following values:
530 * @arg @ref LL_DMA_MODE_NORMAL
531 * @arg @ref LL_DMA_MODE_CIRCULAR
532 */
LL_DMA_GetMode(DMA_TypeDef * DMAx,uint32_t Channel)533 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
534 {
535 uint32_t dma_base_addr = (uint32_t)DMAx;
536 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR,
537 DMA_CCR_CIRC));
538 }
539
540 /**
541 * @brief Set Peripheral increment mode.
542 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
543 * @param DMAx DMAx Instance
544 * @param Channel This parameter can be one of the following values:
545 * @arg @ref LL_DMA_CHANNEL_1
546 * @arg @ref LL_DMA_CHANNEL_2
547 * @arg @ref LL_DMA_CHANNEL_3
548 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
549 * @arg @ref LL_DMA_PERIPH_INCREMENT
550 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
551 * @retval None
552 */
LL_DMA_SetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcIncMode)553 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
554 {
555 uint32_t dma_base_addr = (uint32_t)DMAx;
556 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_PINC,
557 PeriphOrM2MSrcIncMode);
558 }
559
560 /**
561 * @brief Get Peripheral increment mode.
562 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
563 * @param DMAx DMAx Instance
564 * @param Channel This parameter can be one of the following values:
565 * @arg @ref LL_DMA_CHANNEL_1
566 * @arg @ref LL_DMA_CHANNEL_2
567 * @arg @ref LL_DMA_CHANNEL_3
568 * @retval Returned value can be one of the following values:
569 * @arg @ref LL_DMA_PERIPH_INCREMENT
570 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
571 */
LL_DMA_GetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel)572 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
573 {
574 uint32_t dma_base_addr = (uint32_t)DMAx;
575 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR,
576 DMA_CCR_PINC));
577 }
578
579 /**
580 * @brief Set Memory increment mode.
581 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
582 * @param DMAx DMAx Instance
583 * @param Channel This parameter can be one of the following values:
584 * @arg @ref LL_DMA_CHANNEL_1
585 * @arg @ref LL_DMA_CHANNEL_2
586 * @arg @ref LL_DMA_CHANNEL_3
587 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
588 * @arg @ref LL_DMA_MEMORY_INCREMENT
589 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
590 * @retval None
591 */
LL_DMA_SetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstIncMode)592 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
593 {
594 uint32_t dma_base_addr = (uint32_t)DMAx;
595 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_MINC,
596 MemoryOrM2MDstIncMode);
597 }
598
599 /**
600 * @brief Get Memory increment mode.
601 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
602 * @param DMAx DMAx Instance
603 * @param Channel This parameter can be one of the following values:
604 * @arg @ref LL_DMA_CHANNEL_1
605 * @arg @ref LL_DMA_CHANNEL_2
606 * @arg @ref LL_DMA_CHANNEL_3
607 * @retval Returned value can be one of the following values:
608 * @arg @ref LL_DMA_MEMORY_INCREMENT
609 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
610 */
LL_DMA_GetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel)611 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
612 {
613 uint32_t dma_base_addr = (uint32_t)DMAx;
614 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR,
615 DMA_CCR_MINC));
616 }
617
618 /**
619 * @brief Set Peripheral size.
620 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
621 * @param DMAx DMAx Instance
622 * @param Channel This parameter can be one of the following values:
623 * @arg @ref LL_DMA_CHANNEL_1
624 * @arg @ref LL_DMA_CHANNEL_2
625 * @arg @ref LL_DMA_CHANNEL_3
626 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
627 * @arg @ref LL_DMA_PDATAALIGN_BYTE
628 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
629 * @arg @ref LL_DMA_PDATAALIGN_WORD
630 * @retval None
631 */
LL_DMA_SetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcDataSize)632 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
633 {
634 uint32_t dma_base_addr = (uint32_t)DMAx;
635 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_PSIZE,
636 PeriphOrM2MSrcDataSize);
637 }
638
639 /**
640 * @brief Get Peripheral size.
641 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
642 * @param DMAx DMAx Instance
643 * @param Channel This parameter can be one of the following values:
644 * @arg @ref LL_DMA_CHANNEL_1
645 * @arg @ref LL_DMA_CHANNEL_2
646 * @arg @ref LL_DMA_CHANNEL_3
647 * @retval Returned value can be one of the following values:
648 * @arg @ref LL_DMA_PDATAALIGN_BYTE
649 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
650 * @arg @ref LL_DMA_PDATAALIGN_WORD
651 */
LL_DMA_GetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel)652 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
653 {
654 uint32_t dma_base_addr = (uint32_t)DMAx;
655 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR,
656 DMA_CCR_PSIZE));
657 }
658
659 /**
660 * @brief Set Memory size.
661 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
662 * @param DMAx DMAx Instance
663 * @param Channel This parameter can be one of the following values:
664 * @arg @ref LL_DMA_CHANNEL_1
665 * @arg @ref LL_DMA_CHANNEL_2
666 * @arg @ref LL_DMA_CHANNEL_3
667 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
668 * @arg @ref LL_DMA_MDATAALIGN_BYTE
669 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
670 * @arg @ref LL_DMA_MDATAALIGN_WORD
671 * @retval None
672 */
LL_DMA_SetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstDataSize)673 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
674 {
675 uint32_t dma_base_addr = (uint32_t)DMAx;
676 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_MSIZE,
677 MemoryOrM2MDstDataSize);
678 }
679
680 /**
681 * @brief Get Memory size.
682 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
683 * @param DMAx DMAx Instance
684 * @param Channel This parameter can be one of the following values:
685 * @arg @ref LL_DMA_CHANNEL_1
686 * @arg @ref LL_DMA_CHANNEL_2
687 * @arg @ref LL_DMA_CHANNEL_3
688 * @retval Returned value can be one of the following values:
689 * @arg @ref LL_DMA_MDATAALIGN_BYTE
690 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
691 * @arg @ref LL_DMA_MDATAALIGN_WORD
692 */
LL_DMA_GetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel)693 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
694 {
695 uint32_t dma_base_addr = (uint32_t)DMAx;
696 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR,
697 DMA_CCR_MSIZE));
698 }
699
700 /**
701 * @brief Set Channel priority level.
702 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
703 * @param DMAx DMAx Instance
704 * @param Channel This parameter can be one of the following values:
705 * @arg @ref LL_DMA_CHANNEL_1
706 * @arg @ref LL_DMA_CHANNEL_2
707 * @arg @ref LL_DMA_CHANNEL_3
708 * @param Priority This parameter can be one of the following values:
709 * @arg @ref LL_DMA_PRIORITY_LOW
710 * @arg @ref LL_DMA_PRIORITY_MEDIUM
711 * @arg @ref LL_DMA_PRIORITY_HIGH
712 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
713 * @retval None
714 */
LL_DMA_SetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Priority)715 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
716 {
717 uint32_t dma_base_addr = (uint32_t)DMAx;
718 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_PL,
719 Priority);
720 }
721
722 /**
723 * @brief Get Channel priority level.
724 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
725 * @param DMAx DMAx Instance
726 * @param Channel This parameter can be one of the following values:
727 * @arg @ref LL_DMA_CHANNEL_1
728 * @arg @ref LL_DMA_CHANNEL_2
729 * @arg @ref LL_DMA_CHANNEL_3
730 * @retval Returned value can be one of the following values:
731 * @arg @ref LL_DMA_PRIORITY_LOW
732 * @arg @ref LL_DMA_PRIORITY_MEDIUM
733 * @arg @ref LL_DMA_PRIORITY_HIGH
734 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
735 */
LL_DMA_GetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel)736 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
737 {
738 uint32_t dma_base_addr = (uint32_t)DMAx;
739 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR,
740 DMA_CCR_PL));
741 }
742
743 /**
744 * @brief Set Number of data to transfer.
745 * @note This action has no effect if
746 * channel is enabled.
747 * @rmtoll CNDTR NDT LL_DMA_SetDataLength
748 * @param DMAx DMAx Instance
749 * @param Channel This parameter can be one of the following values:
750 * @arg @ref LL_DMA_CHANNEL_1
751 * @arg @ref LL_DMA_CHANNEL_2
752 * @arg @ref LL_DMA_CHANNEL_3
753 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
754 * @retval None
755 */
LL_DMA_SetDataLength(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t NbData)756 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
757 {
758 uint32_t dma_base_addr = (uint32_t)DMAx;
759 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CNDTR,
760 DMA_CNDTR_NDT, NbData);
761 }
762
763 /**
764 * @brief Get Number of data to transfer.
765 * @note Once the channel is enabled, the return value indicate the
766 * remaining bytes to be transmitted.
767 * @rmtoll CNDTR NDT LL_DMA_GetDataLength
768 * @param DMAx DMAx Instance
769 * @param Channel This parameter can be one of the following values:
770 * @arg @ref LL_DMA_CHANNEL_1
771 * @arg @ref LL_DMA_CHANNEL_2
772 * @arg @ref LL_DMA_CHANNEL_3
773 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
774 */
LL_DMA_GetDataLength(DMA_TypeDef * DMAx,uint32_t Channel)775 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
776 {
777 uint32_t dma_base_addr = (uint32_t)DMAx;
778 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CNDTR,
779 DMA_CNDTR_NDT));
780 }
781
782 /**
783 * @brief Configure the Source and Destination addresses.
784 * @note This API must not be called when the DMA channel is enabled.
785 * @note Each peripheral using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr).
786 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
787 * CMAR MA LL_DMA_ConfigAddresses
788 * @param DMAx DMAx Instance
789 * @param Channel This parameter can be one of the following values:
790 * @arg @ref LL_DMA_CHANNEL_1
791 * @arg @ref LL_DMA_CHANNEL_2
792 * @arg @ref LL_DMA_CHANNEL_3
793 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
794 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
795 * @param Direction This parameter can be one of the following values:
796 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
797 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
798 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
799 * @retval None
800 */
LL_DMA_ConfigAddresses(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddress,uint32_t DstAddress,uint32_t Direction)801 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
802 uint32_t DstAddress, uint32_t Direction)
803 {
804 uint32_t dma_base_addr = (uint32_t)DMAx;
805 /* Direction Memory to Periph */
806 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
807 {
808 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CMAR, SrcAddress);
809 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CPAR, DstAddress);
810 }
811 /* Direction Periph to Memory and Memory to Memory */
812 else
813 {
814 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CPAR, SrcAddress);
815 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CMAR, DstAddress);
816 }
817 }
818
819 /**
820 * @brief Set the Memory address.
821 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
822 * @note This API must not be called when the DMA channel is enabled.
823 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
824 * @param DMAx DMAx Instance
825 * @param Channel This parameter can be one of the following values:
826 * @arg @ref LL_DMA_CHANNEL_1
827 * @arg @ref LL_DMA_CHANNEL_2
828 * @arg @ref LL_DMA_CHANNEL_3
829 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
830 * @retval None
831 */
LL_DMA_SetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)832 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
833 {
834 uint32_t dma_base_addr = (uint32_t)DMAx;
835 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CMAR, MemoryAddress);
836 }
837
838 /**
839 * @brief Set the Peripheral address.
840 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
841 * @note This API must not be called when the DMA channel is enabled.
842 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
843 * @param DMAx DMAx Instance
844 * @param Channel This parameter can be one of the following values:
845 * @arg @ref LL_DMA_CHANNEL_1
846 * @arg @ref LL_DMA_CHANNEL_2
847 * @arg @ref LL_DMA_CHANNEL_3
848 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
849 * @retval None
850 */
LL_DMA_SetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphAddress)851 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
852 {
853 uint32_t dma_base_addr = (uint32_t)DMAx;
854 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CPAR, PeriphAddress);
855 }
856
857 /**
858 * @brief Get Memory address.
859 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
860 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
861 * @param DMAx DMAx Instance
862 * @param Channel This parameter can be one of the following values:
863 * @arg @ref LL_DMA_CHANNEL_1
864 * @arg @ref LL_DMA_CHANNEL_2
865 * @arg @ref LL_DMA_CHANNEL_3
866 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
867 */
LL_DMA_GetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel)868 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
869 {
870 uint32_t dma_base_addr = (uint32_t)DMAx;
871 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CMAR));
872 }
873
874 /**
875 * @brief Get Peripheral address.
876 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
877 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
878 * @param DMAx DMAx Instance
879 * @param Channel This parameter can be one of the following values:
880 * @arg @ref LL_DMA_CHANNEL_1
881 * @arg @ref LL_DMA_CHANNEL_2
882 * @arg @ref LL_DMA_CHANNEL_3
883 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
884 */
LL_DMA_GetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel)885 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
886 {
887 uint32_t dma_base_addr = (uint32_t)DMAx;
888 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CPAR));
889 }
890
891 /**
892 * @brief Set the Memory to Memory Source address.
893 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
894 * @note This API must not be called when the DMA channel is enabled.
895 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
896 * @param DMAx DMAx Instance
897 * @param Channel This parameter can be one of the following values:
898 * @arg @ref LL_DMA_CHANNEL_1
899 * @arg @ref LL_DMA_CHANNEL_2
900 * @arg @ref LL_DMA_CHANNEL_3
901 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
902 * @retval None
903 */
LL_DMA_SetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)904 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
905 {
906 uint32_t dma_base_addr = (uint32_t)DMAx;
907 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CPAR, MemoryAddress);
908 }
909
910 /**
911 * @brief Set the Memory to Memory Destination address.
912 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
913 * @note This API must not be called when the DMA channel is enabled.
914 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
915 * @param DMAx DMAx Instance
916 * @param Channel This parameter can be one of the following values:
917 * @arg @ref LL_DMA_CHANNEL_1
918 * @arg @ref LL_DMA_CHANNEL_2
919 * @arg @ref LL_DMA_CHANNEL_3
920 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
921 * @retval None
922 */
LL_DMA_SetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)923 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
924 {
925 uint32_t dma_base_addr = (uint32_t)DMAx;
926 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CMAR, MemoryAddress);
927 }
928
929 /**
930 * @brief Get the Memory to Memory Source address.
931 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
932 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
933 * @param DMAx DMAx Instance
934 * @param Channel This parameter can be one of the following values:
935 * @arg @ref LL_DMA_CHANNEL_1
936 * @arg @ref LL_DMA_CHANNEL_2
937 * @arg @ref LL_DMA_CHANNEL_3
938 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
939 */
LL_DMA_GetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel)940 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
941 {
942 uint32_t dma_base_addr = (uint32_t)DMAx;
943 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CPAR));
944 }
945
946 /**
947 * @brief Get the Memory to Memory Destination address.
948 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
949 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
950 * @param DMAx DMAx Instance
951 * @param Channel This parameter can be one of the following values:
952 * @arg @ref LL_DMA_CHANNEL_1
953 * @arg @ref LL_DMA_CHANNEL_2
954 * @arg @ref LL_DMA_CHANNEL_3
955 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
956 */
LL_DMA_GetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel)957 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
958 {
959 uint32_t dma_base_addr = (uint32_t)DMAx;
960 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CMAR));
961 }
962
963 /**
964 * @brief Set DMA request for DMA Channels on DMAMUX Channel x.
965 * @note DMAMUX channel 0 to 2 are mapped to DMA1 channel 1 to 3.
966 * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest
967 * @param DMAx DMAx Instance
968 * @param Channel This parameter can be one of the following values:
969 * @arg @ref LL_DMA_CHANNEL_1
970 * @arg @ref LL_DMA_CHANNEL_2
971 * @arg @ref LL_DMA_CHANNEL_3
972 * @param Request This parameter can be one of the following values:
973 * @arg @ref LL_DMAMUX_REQ_MEM2MEM
974 * @arg @ref LL_DMAMUX_REQ_GENERATOR0
975 * @arg @ref LL_DMAMUX_REQ_GENERATOR1
976 * @arg @ref LL_DMAMUX_REQ_GENERATOR2
977 * @arg @ref LL_DMAMUX_REQ_GENERATOR3
978 * @arg @ref LL_DMAMUX_REQ_ADC1
979 * @arg @ref LL_DMAMUX_REQ_I2C1_RX
980 * @arg @ref LL_DMAMUX_REQ_I2C1_TX
981 * @arg @ref LL_DMAMUX_REQ_SPI1_RX
982 * @arg @ref LL_DMAMUX_REQ_SPI1_TX
983 * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
984 * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
985 * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
986 * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
987 * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM
988 * @arg @ref LL_DMAMUX_REQ_TIM1_UP
989 * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
990 * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
991 * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
992 * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
993 * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
994 * @arg @ref LL_DMAMUX_REQ_TIM3_UP
995 * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
996 * @arg @ref LL_DMAMUX_REQ_TIM16_TRIG_COM
997 * @arg @ref LL_DMAMUX_REQ_TIM16_UP
998 * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
999 * @arg @ref LL_DMAMUX_REQ_TIM17_TRIG_COM
1000 * @arg @ref LL_DMAMUX_REQ_TIM17_UP
1001 * @arg @ref LL_DMAMUX_REQ_USART1_RX
1002 * @arg @ref LL_DMAMUX_REQ_USART1_TX
1003 * @arg @ref LL_DMAMUX_REQ_USART2_RX
1004 * @arg @ref LL_DMAMUX_REQ_USART2_TX
1005 * @retval None
1006 */
LL_DMA_SetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Request)1007 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
1008 {
1009 (void)(DMAx);
1010 MODIFY_REG(((DMAMUX_Channel_TypeDef *)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Channel - 1UL))))->CCR,
1011 DMAMUX_CxCR_DMAREQ_ID, Request);
1012 }
1013
1014 /**
1015 * @brief Get DMA request for DMA Channels on DMAMUX Channel x.
1016 * @note DMAMUX channel 0 to 2 are mapped to DMA1 channel 1 to 3.
1017 * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest
1018 * @param DMAx DMAx Instance
1019 * @param Channel This parameter can be one of the following values:
1020 * @arg @ref LL_DMA_CHANNEL_1
1021 * @arg @ref LL_DMA_CHANNEL_2
1022 * @arg @ref LL_DMA_CHANNEL_3
1023 * @retval Returned value can be one of the following values:
1024 * @arg @ref LL_DMAMUX_REQ_MEM2MEM
1025 * @arg @ref LL_DMAMUX_REQ_GENERATOR0
1026 * @arg @ref LL_DMAMUX_REQ_GENERATOR1
1027 * @arg @ref LL_DMAMUX_REQ_GENERATOR2
1028 * @arg @ref LL_DMAMUX_REQ_GENERATOR3
1029 * @arg @ref LL_DMAMUX_REQ_ADC1
1030 * @arg @ref LL_DMAMUX_REQ_I2C1_RX
1031 * @arg @ref LL_DMAMUX_REQ_I2C1_TX
1032 * @arg @ref LL_DMAMUX_REQ_SPI1_RX
1033 * @arg @ref LL_DMAMUX_REQ_SPI1_TX
1034 * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
1035 * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
1036 * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
1037 * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
1038 * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM
1039 * @arg @ref LL_DMAMUX_REQ_TIM1_UP
1040 * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
1041 * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
1042 * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
1043 * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
1044 * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
1045 * @arg @ref LL_DMAMUX_REQ_TIM3_UP
1046 * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
1047 * @arg @ref LL_DMAMUX_REQ_TIM16_TRIG_COM
1048 * @arg @ref LL_DMAMUX_REQ_TIM16_UP
1049 * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
1050 * @arg @ref LL_DMAMUX_REQ_TIM17_TRIG_COM
1051 * @arg @ref LL_DMAMUX_REQ_TIM17_UP
1052 * @arg @ref LL_DMAMUX_REQ_USART1_RX
1053 * @arg @ref LL_DMAMUX_REQ_USART1_TX
1054 * @arg @ref LL_DMAMUX_REQ_USART2_RX
1055 * @arg @ref LL_DMAMUX_REQ_USART2_TX
1056 */
LL_DMA_GetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Channel)1057 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
1058 {
1059 (void)(DMAx);
1060 return (READ_BIT(((DMAMUX_Channel_TypeDef *)(((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * \
1061 (Channel - 1UL)))))->CCR,
1062 DMAMUX_CxCR_DMAREQ_ID));
1063 }
1064
1065 /**
1066 * @}
1067 */
1068
1069 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1070 * @{
1071 */
1072
1073 /**
1074 * @brief Get Channel 1 global interrupt flag.
1075 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
1076 * @param DMAx DMAx Instance
1077 * @retval State of bit (1 or 0).
1078 */
LL_DMA_IsActiveFlag_GI1(DMA_TypeDef * DMAx)1079 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
1080 {
1081 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL);
1082 }
1083
1084 /**
1085 * @brief Get Channel 2 global interrupt flag.
1086 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
1087 * @param DMAx DMAx Instance
1088 * @retval State of bit (1 or 0).
1089 */
LL_DMA_IsActiveFlag_GI2(DMA_TypeDef * DMAx)1090 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
1091 {
1092 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL);
1093 }
1094
1095 /**
1096 * @brief Get Channel 3 global interrupt flag.
1097 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
1098 * @param DMAx DMAx Instance
1099 * @retval State of bit (1 or 0).
1100 */
LL_DMA_IsActiveFlag_GI3(DMA_TypeDef * DMAx)1101 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
1102 {
1103 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL);
1104 }
1105
1106 /**
1107 * @brief Get Channel 1 transfer complete flag.
1108 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
1109 * @param DMAx DMAx Instance
1110 * @retval State of bit (1 or 0).
1111 */
LL_DMA_IsActiveFlag_TC1(DMA_TypeDef * DMAx)1112 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
1113 {
1114 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL);
1115 }
1116
1117 /**
1118 * @brief Get Channel 2 transfer complete flag.
1119 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
1120 * @param DMAx DMAx Instance
1121 * @retval State of bit (1 or 0).
1122 */
LL_DMA_IsActiveFlag_TC2(DMA_TypeDef * DMAx)1123 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
1124 {
1125 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL);
1126 }
1127
1128 /**
1129 * @brief Get Channel 3 transfer complete flag.
1130 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
1131 * @param DMAx DMAx Instance
1132 * @retval State of bit (1 or 0).
1133 */
LL_DMA_IsActiveFlag_TC3(DMA_TypeDef * DMAx)1134 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
1135 {
1136 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL);
1137 }
1138
1139
1140 /**
1141 * @brief Get Channel 1 half transfer flag.
1142 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
1143 * @param DMAx DMAx Instance
1144 * @retval State of bit (1 or 0).
1145 */
LL_DMA_IsActiveFlag_HT1(DMA_TypeDef * DMAx)1146 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
1147 {
1148 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL);
1149 }
1150
1151 /**
1152 * @brief Get Channel 2 half transfer flag.
1153 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
1154 * @param DMAx DMAx Instance
1155 * @retval State of bit (1 or 0).
1156 */
LL_DMA_IsActiveFlag_HT2(DMA_TypeDef * DMAx)1157 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
1158 {
1159 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL);
1160 }
1161
1162 /**
1163 * @brief Get Channel 3 half transfer flag.
1164 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
1165 * @param DMAx DMAx Instance
1166 * @retval State of bit (1 or 0).
1167 */
LL_DMA_IsActiveFlag_HT3(DMA_TypeDef * DMAx)1168 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
1169 {
1170 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL);
1171 }
1172
1173 /**
1174 * @brief Get Channel 1 transfer error flag.
1175 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
1176 * @param DMAx DMAx Instance
1177 * @retval State of bit (1 or 0).
1178 */
LL_DMA_IsActiveFlag_TE1(DMA_TypeDef * DMAx)1179 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
1180 {
1181 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL);
1182 }
1183
1184 /**
1185 * @brief Get Channel 2 transfer error flag.
1186 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
1187 * @param DMAx DMAx Instance
1188 * @retval State of bit (1 or 0).
1189 */
LL_DMA_IsActiveFlag_TE2(DMA_TypeDef * DMAx)1190 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
1191 {
1192 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL);
1193 }
1194
1195 /**
1196 * @brief Get Channel 3 transfer error flag.
1197 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
1198 * @param DMAx DMAx Instance
1199 * @retval State of bit (1 or 0).
1200 */
LL_DMA_IsActiveFlag_TE3(DMA_TypeDef * DMAx)1201 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
1202 {
1203 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL);
1204 }
1205
1206 /**
1207 * @brief Clear Channel 1 global interrupt flag.
1208 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
1209 * @param DMAx DMAx Instance
1210 * @retval None
1211 */
LL_DMA_ClearFlag_GI1(DMA_TypeDef * DMAx)1212 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
1213 {
1214 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
1215 }
1216
1217 /**
1218 * @brief Clear Channel 2 global interrupt flag.
1219 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
1220 * @param DMAx DMAx Instance
1221 * @retval None
1222 */
LL_DMA_ClearFlag_GI2(DMA_TypeDef * DMAx)1223 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
1224 {
1225 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
1226 }
1227
1228 /**
1229 * @brief Clear Channel 3 global interrupt flag.
1230 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
1231 * @param DMAx DMAx Instance
1232 * @retval None
1233 */
LL_DMA_ClearFlag_GI3(DMA_TypeDef * DMAx)1234 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
1235 {
1236 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
1237 }
1238
1239 /**
1240 * @brief Clear Channel 1 transfer complete flag.
1241 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
1242 * @param DMAx DMAx Instance
1243 * @retval None
1244 */
LL_DMA_ClearFlag_TC1(DMA_TypeDef * DMAx)1245 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
1246 {
1247 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
1248 }
1249
1250 /**
1251 * @brief Clear Channel 2 transfer complete flag.
1252 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
1253 * @param DMAx DMAx Instance
1254 * @retval None
1255 */
LL_DMA_ClearFlag_TC2(DMA_TypeDef * DMAx)1256 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
1257 {
1258 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
1259 }
1260
1261 /**
1262 * @brief Clear Channel 3 transfer complete flag.
1263 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
1264 * @param DMAx DMAx Instance
1265 * @retval None
1266 */
LL_DMA_ClearFlag_TC3(DMA_TypeDef * DMAx)1267 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
1268 {
1269 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
1270 }
1271
1272 /**
1273 * @brief Clear Channel 1 half transfer flag.
1274 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
1275 * @param DMAx DMAx Instance
1276 * @retval None
1277 */
LL_DMA_ClearFlag_HT1(DMA_TypeDef * DMAx)1278 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
1279 {
1280 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
1281 }
1282
1283 /**
1284 * @brief Clear Channel 2 half transfer flag.
1285 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
1286 * @param DMAx DMAx Instance
1287 * @retval None
1288 */
LL_DMA_ClearFlag_HT2(DMA_TypeDef * DMAx)1289 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
1290 {
1291 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
1292 }
1293
1294 /**
1295 * @brief Clear Channel 3 half transfer flag.
1296 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
1297 * @param DMAx DMAx Instance
1298 * @retval None
1299 */
LL_DMA_ClearFlag_HT3(DMA_TypeDef * DMAx)1300 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
1301 {
1302 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
1303 }
1304
1305 /**
1306 * @brief Clear Channel 1 transfer error flag.
1307 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
1308 * @param DMAx DMAx Instance
1309 * @retval None
1310 */
LL_DMA_ClearFlag_TE1(DMA_TypeDef * DMAx)1311 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
1312 {
1313 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
1314 }
1315
1316 /**
1317 * @brief Clear Channel 2 transfer error flag.
1318 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
1319 * @param DMAx DMAx Instance
1320 * @retval None
1321 */
LL_DMA_ClearFlag_TE2(DMA_TypeDef * DMAx)1322 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
1323 {
1324 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
1325 }
1326
1327 /**
1328 * @brief Clear Channel 3 transfer error flag.
1329 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
1330 * @param DMAx DMAx Instance
1331 * @retval None
1332 */
LL_DMA_ClearFlag_TE3(DMA_TypeDef * DMAx)1333 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
1334 {
1335 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
1336 }
1337
1338 /**
1339 * @}
1340 */
1341
1342 /** @defgroup DMA_LL_EF_IT_Management IT_Management
1343 * @{
1344 */
1345 /**
1346 * @brief Enable Transfer complete interrupt.
1347 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
1348 * @param DMAx DMAx Instance
1349 * @param Channel This parameter can be one of the following values:
1350 * @arg @ref LL_DMA_CHANNEL_1
1351 * @arg @ref LL_DMA_CHANNEL_2
1352 * @arg @ref LL_DMA_CHANNEL_3
1353 * @retval None
1354 */
LL_DMA_EnableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)1355 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1356 {
1357 uint32_t dma_base_addr = (uint32_t)DMAx;
1358 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_TCIE);
1359 }
1360
1361 /**
1362 * @brief Enable Half transfer interrupt.
1363 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
1364 * @param DMAx DMAx Instance
1365 * @param Channel This parameter can be one of the following values:
1366 * @arg @ref LL_DMA_CHANNEL_1
1367 * @arg @ref LL_DMA_CHANNEL_2
1368 * @arg @ref LL_DMA_CHANNEL_3
1369 * @retval None
1370 */
LL_DMA_EnableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)1371 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
1372 {
1373 uint32_t dma_base_addr = (uint32_t)DMAx;
1374 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_HTIE);
1375 }
1376
1377 /**
1378 * @brief Enable Transfer error interrupt.
1379 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
1380 * @param DMAx DMAx Instance
1381 * @param Channel This parameter can be one of the following values:
1382 * @arg @ref LL_DMA_CHANNEL_1
1383 * @arg @ref LL_DMA_CHANNEL_2
1384 * @arg @ref LL_DMA_CHANNEL_3
1385 * @retval None
1386 */
LL_DMA_EnableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)1387 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
1388 {
1389 uint32_t dma_base_addr = (uint32_t)DMAx;
1390 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_TEIE);
1391 }
1392
1393 /**
1394 * @brief Disable Transfer complete interrupt.
1395 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
1396 * @param DMAx DMAx Instance
1397 * @param Channel This parameter can be one of the following values:
1398 * @arg @ref LL_DMA_CHANNEL_1
1399 * @arg @ref LL_DMA_CHANNEL_2
1400 * @arg @ref LL_DMA_CHANNEL_3
1401 * @retval None
1402 */
LL_DMA_DisableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)1403 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1404 {
1405 uint32_t dma_base_addr = (uint32_t)DMAx;
1406 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_TCIE);
1407 }
1408
1409 /**
1410 * @brief Disable Half transfer interrupt.
1411 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
1412 * @param DMAx DMAx Instance
1413 * @param Channel This parameter can be one of the following values:
1414 * @arg @ref LL_DMA_CHANNEL_1
1415 * @arg @ref LL_DMA_CHANNEL_2
1416 * @arg @ref LL_DMA_CHANNEL_3
1417 * @retval None
1418 */
LL_DMA_DisableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)1419 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
1420 {
1421 uint32_t dma_base_addr = (uint32_t)DMAx;
1422 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_HTIE);
1423 }
1424
1425 /**
1426 * @brief Disable Transfer error interrupt.
1427 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
1428 * @param DMAx DMAx Instance
1429 * @param Channel This parameter can be one of the following values:
1430 * @arg @ref LL_DMA_CHANNEL_1
1431 * @arg @ref LL_DMA_CHANNEL_2
1432 * @arg @ref LL_DMA_CHANNEL_3
1433 * @retval None
1434 */
LL_DMA_DisableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)1435 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
1436 {
1437 uint32_t dma_base_addr = (uint32_t)DMAx;
1438 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_TEIE);
1439 }
1440
1441 /**
1442 * @brief Check if Transfer complete Interrupt is enabled.
1443 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
1444 * @param DMAx DMAx Instance
1445 * @param Channel This parameter can be one of the following values:
1446 * @arg @ref LL_DMA_CHANNEL_1
1447 * @arg @ref LL_DMA_CHANNEL_2
1448 * @arg @ref LL_DMA_CHANNEL_3
1449 * @retval State of bit (1 or 0).
1450 */
LL_DMA_IsEnabledIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)1451 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1452 {
1453 uint32_t dma_base_addr = (uint32_t)DMAx;
1454 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR,
1455 DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL);
1456 }
1457
1458 /**
1459 * @brief Check if Half transfer Interrupt is enabled.
1460 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
1461 * @param DMAx DMAx Instance
1462 * @param Channel This parameter can be one of the following values:
1463 * @arg @ref LL_DMA_CHANNEL_1
1464 * @arg @ref LL_DMA_CHANNEL_2
1465 * @arg @ref LL_DMA_CHANNEL_3
1466 * @retval State of bit (1 or 0).
1467 */
LL_DMA_IsEnabledIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)1468 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
1469 {
1470 uint32_t dma_base_addr = (uint32_t)DMAx;
1471 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR,
1472 DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL);
1473 }
1474
1475 /**
1476 * @brief Check if Transfer error Interrupt is enabled.
1477 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
1478 * @param DMAx DMAx Instance
1479 * @param Channel This parameter can be one of the following values:
1480 * @arg @ref LL_DMA_CHANNEL_1
1481 * @arg @ref LL_DMA_CHANNEL_2
1482 * @arg @ref LL_DMA_CHANNEL_3
1483 * @retval State of bit (1 or 0).
1484 */
LL_DMA_IsEnabledIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)1485 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
1486 {
1487 uint32_t dma_base_addr = (uint32_t)DMAx;
1488 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR,
1489 DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL);
1490 }
1491
1492 /**
1493 * @}
1494 */
1495
1496 #if defined(USE_FULL_LL_DRIVER)
1497 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
1498 * @{
1499 */
1500
1501 ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
1502 ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
1503 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
1504
1505 /**
1506 * @}
1507 */
1508 #endif /* USE_FULL_LL_DRIVER */
1509
1510 /**
1511 * @}
1512 */
1513
1514 /**
1515 * @}
1516 */
1517
1518 #endif /* DMA1 */
1519
1520 /**
1521 * @}
1522 */
1523
1524 #ifdef __cplusplus
1525 }
1526 #endif
1527
1528 #endif /* STM32C0xx_LL_DMA_H */
1529
