1 /**
2 ******************************************************************************
3 * @file stm32c0xx_ll_cortex.h
4 * @author MCD Application Team
5 * @brief Header file of CORTEX LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### How to use this driver #####
20 ==============================================================================
21 [..]
22 The LL CORTEX driver contains a set of generic APIs that can be
23 used by user:
24 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
25 functions
26 (+) Low power mode configuration (SCB register of Cortex-MCU)
27 (+) MPU API to configure and enable regions
28 (+) API to access to MCU info (CPUID register)
29
30 @endverbatim
31 */
32
33 /* Define to prevent recursive inclusion -------------------------------------*/
34 #ifndef STM32C0xx_LL_CORTEX_H
35 #define STM32C0xx_LL_CORTEX_H
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 /* Includes ------------------------------------------------------------------*/
42 #include "stm32c0xx.h"
43
44 /** @addtogroup STM32C0xx_LL_Driver
45 * @{
46 */
47
48 /** @defgroup CORTEX_LL CORTEX
49 * @{
50 */
51
52 /* Private types -------------------------------------------------------------*/
53 /* Private variables ---------------------------------------------------------*/
54
55 /* Private constants ---------------------------------------------------------*/
56
57 /* Private macros ------------------------------------------------------------*/
58
59 /* Exported types ------------------------------------------------------------*/
60 /* Exported constants --------------------------------------------------------*/
61 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
62 * @{
63 */
64
65 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
66 * @{
67 */
68 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected
69 as SysTick clock source.*/
70 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick
71 clock source. */
72 /**
73 * @}
74 */
75
76 #if __MPU_PRESENT
77
78 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
79 * @{
80 */
81 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
82 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during
83 hard fault, NMI, and FAULTMASK handlers */
84 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access
85 to default memory map */
86 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI
87 and privileged SW access */
88 /**
89 * @}
90 */
91
92 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
93 * @{
94 */
95 #define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
96 #define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
97 #define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
98 #define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
99 #define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
100 #define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
101 #define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
102 #define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
103 /**
104 * @}
105 */
106
107 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
108 * @{
109 */
110 #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
111 #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
112 #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
113 #define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
114 #define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
115 #define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
116 #define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
117 #define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
118 #define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
119 #define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
120 #define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
121 #define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
122 #define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
123 #define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
124 #define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
125 #define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
126 #define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
127 #define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
128 #define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
129 #define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
130 #define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
131 #define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
132 #define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
133 #define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
134 #define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
135 /**
136 * @}
137 */
138
139 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
140 * @{
141 */
142 #define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
143 #define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
144 #define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user
145 program generates a fault) */
146 #define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
147 #define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
148 #define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
149 /**
150 * @}
151 */
152
153 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
154 * @{
155 */
156 #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
157 #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
158 #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
159 #define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
160 /**
161 * @}
162 */
163
164 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
165 * @{
166 */
167 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
168 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
169 /**
170 * @}
171 */
172
173 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
174 * @{
175 */
176 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
177 #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
178 /**
179 * @}
180 */
181
182 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
183 * @{
184 */
185 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
186 #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
187 /**
188 * @}
189 */
190
191 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
192 * @{
193 */
194 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
195 #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
196 /**
197 * @}
198 */
199 #endif /* __MPU_PRESENT */
200 /**
201 * @}
202 */
203
204 /* Exported macro ------------------------------------------------------------*/
205
206 /* Exported functions --------------------------------------------------------*/
207 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
208 * @{
209 */
210
211 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
212 * @{
213 */
214
215 /**
216 * @brief This function checks if the Systick counter flag is active or not.
217 * @note It can be used in timeout function on application side.
218 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
219 * @retval State of bit (1 or 0).
220 */
LL_SYSTICK_IsActiveCounterFlag(void)221 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
222 {
223 return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
224 }
225
226 /**
227 * @brief Configures the SysTick clock source
228 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
229 * @param Source This parameter can be one of the following values:
230 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
231 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
232 * @retval None
233 */
LL_SYSTICK_SetClkSource(uint32_t Source)234 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
235 {
236 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
237 {
238 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
239 }
240 else
241 {
242 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
243 }
244 }
245
246 /**
247 * @brief Get the SysTick clock source
248 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
249 * @retval Returned value can be one of the following values:
250 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
251 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
252 */
LL_SYSTICK_GetClkSource(void)253 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
254 {
255 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
256 }
257
258 /**
259 * @brief Enable SysTick exception request
260 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
261 * @retval None
262 */
LL_SYSTICK_EnableIT(void)263 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
264 {
265 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
266 }
267
268 /**
269 * @brief Disable SysTick exception request
270 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
271 * @retval None
272 */
LL_SYSTICK_DisableIT(void)273 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
274 {
275 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
276 }
277
278 /**
279 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
280 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
281 * @retval State of bit (1 or 0).
282 */
LL_SYSTICK_IsEnabledIT(void)283 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
284 {
285 return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
286 }
287
288 /**
289 * @}
290 */
291
292 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
293 * @{
294 */
295
296 /**
297 * @brief Processor uses sleep as its low power mode
298 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
299 * @retval None
300 */
LL_LPM_EnableSleep(void)301 __STATIC_INLINE void LL_LPM_EnableSleep(void)
302 {
303 /* Clear SLEEPDEEP bit of Cortex System Control Register */
304 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
305 }
306
307 /**
308 * @brief Processor uses deep sleep as its low power mode
309 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
310 * @retval None
311 */
LL_LPM_EnableDeepSleep(void)312 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
313 {
314 /* Set SLEEPDEEP bit of Cortex System Control Register */
315 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
316 }
317
318 /**
319 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
320 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
321 * empty main application.
322 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
323 * @retval None
324 */
LL_LPM_EnableSleepOnExit(void)325 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
326 {
327 /* Set SLEEPONEXIT bit of Cortex System Control Register */
328 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
329 }
330
331 /**
332 * @brief Do not sleep when returning to Thread mode.
333 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
334 * @retval None
335 */
LL_LPM_DisableSleepOnExit(void)336 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
337 {
338 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
339 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
340 }
341
342 /**
343 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
344 * processor.
345 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
346 * @retval None
347 */
LL_LPM_EnableEventOnPend(void)348 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
349 {
350 /* Set SEVEONPEND bit of Cortex System Control Register */
351 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
352 }
353
354 /**
355 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
356 * excluded
357 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
358 * @retval None
359 */
LL_LPM_DisableEventOnPend(void)360 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
361 {
362 /* Clear SEVEONPEND bit of Cortex System Control Register */
363 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
364 }
365
366 /**
367 * @}
368 */
369
370 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
371 * @{
372 */
373
374 /**
375 * @brief Get Implementer code
376 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
377 * @retval Value should be equal to 0x41 for ARM
378 */
LL_CPUID_GetImplementer(void)379 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
380 {
381 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
382 }
383
384 /**
385 * @brief Get Variant number (The r value in the rnpn product revision identifier)
386 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
387 * @retval Value between 0 and 255 (0x0: revision 0)
388 */
LL_CPUID_GetVariant(void)389 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
390 {
391 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
392 }
393
394 /**
395 * @brief Get Architecture number
396 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture
397 * @retval Value should be equal to 0xC for Cortex-M0+ devices
398 */
LL_CPUID_GetArchitecture(void)399 __STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
400 {
401 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
402 }
403
404 /**
405 * @brief Get Part number
406 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
407 * @retval Value should be equal to 0xC60 for Cortex-M0+
408 */
LL_CPUID_GetParNo(void)409 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
410 {
411 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
412 }
413
414 /**
415 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
416 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
417 * @retval Value between 0 and 255 (0x1: patch 1)
418 */
LL_CPUID_GetRevision(void)419 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
420 {
421 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
422 }
423
424 /**
425 * @}
426 */
427
428 #if __MPU_PRESENT
429 /** @defgroup CORTEX_LL_EF_MPU MPU
430 * @{
431 */
432
433 /**
434 * @brief Enable MPU with input options
435 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
436 * @param Options This parameter can be one of the following values:
437 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
438 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
439 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
440 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
441 * @retval None
442 */
LL_MPU_Enable(uint32_t Options)443 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
444 {
445 /* Enable the MPU*/
446 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
447 /* Ensure MPU settings take effects */
448 __DSB();
449 /* Sequence instruction fetches using update settings */
450 __ISB();
451 }
452
453 /**
454 * @brief Disable MPU
455 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
456 * @retval None
457 */
LL_MPU_Disable(void)458 __STATIC_INLINE void LL_MPU_Disable(void)
459 {
460 /* Make sure outstanding transfers are done */
461 __DMB();
462 /* Disable MPU*/
463 WRITE_REG(MPU->CTRL, 0U);
464 }
465
466 /**
467 * @brief Check if MPU is enabled or not
468 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
469 * @retval State of bit (1 or 0).
470 */
LL_MPU_IsEnabled(void)471 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
472 {
473 return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
474 }
475
476 /**
477 * @brief Enable a MPU region
478 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
479 * @param Region This parameter can be one of the following values:
480 * @arg @ref LL_MPU_REGION_NUMBER0
481 * @arg @ref LL_MPU_REGION_NUMBER1
482 * @arg @ref LL_MPU_REGION_NUMBER2
483 * @arg @ref LL_MPU_REGION_NUMBER3
484 * @arg @ref LL_MPU_REGION_NUMBER4
485 * @arg @ref LL_MPU_REGION_NUMBER5
486 * @arg @ref LL_MPU_REGION_NUMBER6
487 * @arg @ref LL_MPU_REGION_NUMBER7
488 * @retval None
489 */
LL_MPU_EnableRegion(uint32_t Region)490 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
491 {
492 /* Set Region number */
493 WRITE_REG(MPU->RNR, Region);
494 /* Enable the MPU region */
495 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
496 }
497
498 /**
499 * @brief Configure and enable a region
500 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
501 * MPU_RBAR REGION LL_MPU_ConfigRegion\n
502 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
503 * MPU_RASR XN LL_MPU_ConfigRegion\n
504 * MPU_RASR AP LL_MPU_ConfigRegion\n
505 * MPU_RASR S LL_MPU_ConfigRegion\n
506 * MPU_RASR C LL_MPU_ConfigRegion\n
507 * MPU_RASR B LL_MPU_ConfigRegion\n
508 * MPU_RASR SIZE LL_MPU_ConfigRegion
509 * @param Region This parameter can be one of the following values:
510 * @arg @ref LL_MPU_REGION_NUMBER0
511 * @arg @ref LL_MPU_REGION_NUMBER1
512 * @arg @ref LL_MPU_REGION_NUMBER2
513 * @arg @ref LL_MPU_REGION_NUMBER3
514 * @arg @ref LL_MPU_REGION_NUMBER4
515 * @arg @ref LL_MPU_REGION_NUMBER5
516 * @arg @ref LL_MPU_REGION_NUMBER6
517 * @arg @ref LL_MPU_REGION_NUMBER7
518 * @param Address Value of region base address
519 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
520 * @param Attributes This parameter can be a combination of the following values:
521 * @arg @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
522 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB
523 * or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB or @ref LL_MPU_REGION_SIZE_32KB
524 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO
525 * or @ref LL_MPU_REGION_FULL_ACCESS or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
526 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
527 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
528 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
529 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
530 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
531 * @retval None
532 */
LL_MPU_ConfigRegion(uint32_t Region,uint32_t SubRegionDisable,uint32_t Address,uint32_t Attributes)533 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address,
534 uint32_t Attributes)
535 {
536 /* Set Region number */
537 WRITE_REG(MPU->RNR, Region);
538 /* Set base address */
539 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
540 /* Configure MPU */
541 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));
542 }
543
544 /**
545 * @brief Disable a region
546 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
547 * MPU_RASR ENABLE LL_MPU_DisableRegion
548 * @param Region This parameter can be one of the following values:
549 * @arg @ref LL_MPU_REGION_NUMBER0
550 * @arg @ref LL_MPU_REGION_NUMBER1
551 * @arg @ref LL_MPU_REGION_NUMBER2
552 * @arg @ref LL_MPU_REGION_NUMBER3
553 * @arg @ref LL_MPU_REGION_NUMBER4
554 * @arg @ref LL_MPU_REGION_NUMBER5
555 * @arg @ref LL_MPU_REGION_NUMBER6
556 * @arg @ref LL_MPU_REGION_NUMBER7
557 * @retval None
558 */
LL_MPU_DisableRegion(uint32_t Region)559 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
560 {
561 /* Set Region number */
562 WRITE_REG(MPU->RNR, Region);
563 /* Disable the MPU region */
564 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
565 }
566
567 /**
568 * @}
569 */
570
571 #endif /* __MPU_PRESENT */
572 /**
573 * @}
574 */
575
576 /**
577 * @}
578 */
579
580 /**
581 * @}
582 */
583
584 #ifdef __cplusplus
585 }
586 #endif
587
588 #endif /* STM32C0xx_LL_CORTEX_H */
589
