1 /**
2 ******************************************************************************
3 * @file stm32c0xx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.g
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32C0xx_LL_ADC_H
21 #define STM32C0xx_LL_ADC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32c0xx.h"
29
30 /** @addtogroup STM32C0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1)
35
36 /** @defgroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
45 * @{
46 */
47
48 /* Internal mask for ADC group regular sequencer: */
49 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
50 /* - sequencer rank bits position into the selected register */
51
52 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
53
54 /* Definition of ADC group regular sequencer bits information to be inserted */
55 /* into ADC group regular sequencer ranks literals definition. */
56 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ1" position in register */
57 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 4UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ2" position in register */
58 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ( 8UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ3" position in register */
59 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ4" position in register */
60 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ5" position in register */
61 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ6" position in register */
62 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ7" position in register */
63 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (28UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ8" position in register */
64
65
66
67 /* Internal mask for ADC group regular trigger: */
68 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
69 /* - regular trigger source */
70 /* - regular trigger edge */
71 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
72
73 /* Mask containing trigger source masks for each of possible */
74 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
75 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
76 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0UL)) | \
77 ((ADC_CFGR1_EXTSEL) << (4U * 1UL)) | \
78 ((ADC_CFGR1_EXTSEL) << (4U * 2UL)) | \
79 ((ADC_CFGR1_EXTSEL) << (4U * 3UL)) )
80
81 /* Mask containing trigger edge masks for each of possible */
82 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
83 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
84 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0UL)) | \
85 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
86 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
87 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
88
89 /* Definition of ADC group regular trigger bits information. */
90 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CFGR1_EXTSEL" position in register */
91 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CFGR1_EXTEN" position in register */
92
93
94
95 /* Internal mask for ADC channel: */
96 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
97 /* - channel identifier defined by number */
98 /* - channel identifier defined by bitfield */
99 /* - channel differentiation between external channels (connected to */
100 /* GPIO pins) and internal channels (connected to internal paths) */
101 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWD1CH)
102 #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL)
103 #define ADC_CHANNEL_ID_NUMBER_MASK_SEQ (ADC_CHSELR_SQ1 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Value equivalent to ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer, if set to mode "fully configurable", can contain channels with a restricted channel number. Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */
104 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */
105 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | \
106 ADC_CHANNEL_ID_INTERNAL_CH_MASK)
107 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
108 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FUL) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
109
110 /* Channel differentiation between external and internal channels */
111 #define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
112 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH)
113
114 /* Definition of channels ID number information to be inserted into */
115 /* channels literals definition. */
116 #define ADC_CHANNEL_0_NUMBER (0x00000000UL)
117 #define ADC_CHANNEL_1_NUMBER (ADC_CFGR1_AWD1CH_0)
118 #define ADC_CHANNEL_2_NUMBER (ADC_CFGR1_AWD1CH_1)
119 #define ADC_CHANNEL_3_NUMBER (ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
120 #define ADC_CHANNEL_4_NUMBER (ADC_CFGR1_AWD1CH_2)
121 #define ADC_CHANNEL_5_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
122 #define ADC_CHANNEL_6_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
123 #define ADC_CHANNEL_7_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
124 #define ADC_CHANNEL_8_NUMBER (ADC_CFGR1_AWD1CH_3)
125 #define ADC_CHANNEL_9_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_0)
126 #define ADC_CHANNEL_10_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1)
127 #define ADC_CHANNEL_11_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
128 #define ADC_CHANNEL_12_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2)
129 #define ADC_CHANNEL_13_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
130 #define ADC_CHANNEL_14_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
131 #define ADC_CHANNEL_15_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | \
132 ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
133 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR1_AWD1CH_4)
134 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_0)
135 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1)
136
137 #define ADC_CHANNEL_19_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
138 #define ADC_CHANNEL_20_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_2 )
139 #define ADC_CHANNEL_21_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
140 #define ADC_CHANNEL_22_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
141
142 /* Definition of channels ID bitfield information to be inserted into */
143 /* channels literals definition. */
144 #define ADC_CHANNEL_0_BITFIELD (ADC_CHSELR_CHSEL0)
145 #define ADC_CHANNEL_1_BITFIELD (ADC_CHSELR_CHSEL1)
146 #define ADC_CHANNEL_2_BITFIELD (ADC_CHSELR_CHSEL2)
147 #define ADC_CHANNEL_3_BITFIELD (ADC_CHSELR_CHSEL3)
148 #define ADC_CHANNEL_4_BITFIELD (ADC_CHSELR_CHSEL4)
149 #define ADC_CHANNEL_5_BITFIELD (ADC_CHSELR_CHSEL5)
150 #define ADC_CHANNEL_6_BITFIELD (ADC_CHSELR_CHSEL6)
151 #define ADC_CHANNEL_7_BITFIELD (ADC_CHSELR_CHSEL7)
152 #define ADC_CHANNEL_8_BITFIELD (ADC_CHSELR_CHSEL8)
153 #define ADC_CHANNEL_9_BITFIELD (ADC_CHSELR_CHSEL9)
154 #define ADC_CHANNEL_10_BITFIELD (ADC_CHSELR_CHSEL10)
155 #define ADC_CHANNEL_11_BITFIELD (ADC_CHSELR_CHSEL11)
156 #define ADC_CHANNEL_12_BITFIELD (ADC_CHSELR_CHSEL12)
157 #define ADC_CHANNEL_13_BITFIELD (ADC_CHSELR_CHSEL13)
158 #define ADC_CHANNEL_14_BITFIELD (ADC_CHSELR_CHSEL14)
159 #define ADC_CHANNEL_15_BITFIELD (ADC_CHSELR_CHSEL15)
160 #define ADC_CHANNEL_16_BITFIELD (ADC_CHSELR_CHSEL16)
161 #define ADC_CHANNEL_17_BITFIELD (ADC_CHSELR_CHSEL17)
162 #define ADC_CHANNEL_18_BITFIELD (ADC_CHSELR_CHSEL18)
163 #define ADC_CHANNEL_19_BITFIELD (ADC_CHSELR_CHSEL19)
164 #define ADC_CHANNEL_20_BITFIELD (ADC_CHSELR_CHSEL20)
165 #define ADC_CHANNEL_21_BITFIELD (ADC_CHSELR_CHSEL21)
166 #define ADC_CHANNEL_22_BITFIELD (ADC_CHSELR_CHSEL22)
167
168 /* Internal mask for ADC channel sampling time: */
169 /* To select into literals LL_ADC_SAMPLINGTIME_x */
170 /* the relevant bits for: */
171 /* (concatenation of multiple bits used in register SMPR) */
172 /* - ADC channels sampling time: setting channel wise, to map each channel */
173 /* on one of the common sampling time available. */
174 /* - ADC channels common sampling time: set a sampling time into one of the */
175 /* common sampling time available. */
176 #define ADC_SAMPLING_TIME_CH_MASK (ADC_CHANNEL_ID_BITFIELD_MASK << ADC_SMPR_SMPSEL0_BITOFFSET_POS)
177 #define ADC_SAMPLING_TIME_SMP_MASK (ADC_SMPR_SMP2 | ADC_SMPR_SMP1)
178 #define ADC_SAMPLING_TIME_SMP_SHIFT_MASK (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SMPR_SMP1_BITOFFSET_POS)
179
180 /* Internal mask for ADC analog watchdog: */
181 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
182 /* (concatenation of multiple bits used in different analog watchdogs, */
183 /* (feature of several watchdogs not available on all STM32 families)). */
184 /* - analog watchdog 1: monitored channel defined by number, */
185 /* selection of ADC group (ADC group regular). */
186 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
187 /* selection on groups. */
188
189 /* Internal register offset for ADC analog watchdog channel configuration */
190 #define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
191 #define ADC_AWD_CR2_REGOFFSET (0x00100000UL)
192 #define ADC_AWD_CR3_REGOFFSET (0x00200000UL)
193
194 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
195 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
196 #define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
197 #define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
198
199 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
200 #define ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS (20UL)
201
202 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
203 #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
204 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
205
206 #define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
207
208 /* Internal register offset for ADC analog watchdog threshold configuration */
209 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
210 #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
211 #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET + (1UL << ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS))
212 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
213 #define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */
214 #define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */
215 #define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */
216 #define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */
217 #define ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS (20UL)
218
219
220
221 /* ADC registers bits positions */
222 #define ADC_CFGR1_RES_BITOFFSET_POS ( 3UL) /* Value equivalent to bitfield "ADC_CFGR1_RES" position in register */
223 #define ADC_CFGR1_AWDSGL_BITOFFSET_POS (22UL) /* Value equivalent to bitfield "ADC_CFGR1_AWDSGL" position in register */
224 #define ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_TR1_HT1" position in register */
225 #define ADC_CHSELR_CHSEL0_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL0" position in register */
226 #define ADC_CHSELR_CHSEL1_BITOFFSET_POS ( 1UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL1" position in register */
227 #define ADC_CHSELR_CHSEL2_BITOFFSET_POS ( 2UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL2" position in register */
228 #define ADC_CHSELR_CHSEL3_BITOFFSET_POS ( 3UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL3" position in register */
229 #define ADC_CHSELR_CHSEL4_BITOFFSET_POS ( 4UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL4" position in register */
230 #define ADC_CHSELR_CHSEL5_BITOFFSET_POS ( 5UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL5" position in register */
231 #define ADC_CHSELR_CHSEL6_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL6" position in register */
232 #define ADC_CHSELR_CHSEL7_BITOFFSET_POS ( 7UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL7" position in register */
233 #define ADC_CHSELR_CHSEL8_BITOFFSET_POS ( 8UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL8" position in register */
234 #define ADC_CHSELR_CHSEL9_BITOFFSET_POS ( 9UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL9" position in register */
235 #define ADC_CHSELR_CHSEL10_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL10" position in register */
236 #define ADC_CHSELR_CHSEL11_BITOFFSET_POS (11UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL11" position in register */
237 #define ADC_CHSELR_CHSEL12_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL12" position in register */
238 #define ADC_CHSELR_CHSEL13_BITOFFSET_POS (13UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL13" position in register */
239 #define ADC_CHSELR_CHSEL14_BITOFFSET_POS (14UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL14" position in register */
240 #define ADC_CHSELR_CHSEL15_BITOFFSET_POS (15UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL15" position in register */
241 #define ADC_CHSELR_CHSEL16_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL16" position in register */
242 #define ADC_CHSELR_CHSEL17_BITOFFSET_POS (17UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL17" position in register */
243 #define ADC_CHSELR_CHSEL18_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL18" position in register */
244 #define ADC_CHSELR_CHSEL19_BITOFFSET_POS (19UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL19" position in register */
245 #define ADC_CHSELR_CHSEL20_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL20" position in register */
246 #define ADC_CHSELR_CHSEL21_BITOFFSET_POS (21UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL21" position in register */
247 #define ADC_CHSELR_CHSEL22_BITOFFSET_POS (22UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL22" position in register */
248 #define ADC_SMPR_SMP1_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SMPR_SMP1" position in register */
249 #define ADC_SMPR_SMP2_BITOFFSET_POS ( 4UL) /* Value equivalent to bitfield "ADC_SMPR_SMP2" position in register */
250 #define ADC_SMPR_SMPSEL0_BITOFFSET_POS ( 8UL) /* Value equivalent to bitfield "ADC_SMPR_SMPSEL0" position in register */
251
252
253 /* ADC registers bits groups */
254 #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
255
256
257 /* ADC internal channels related definitions */
258 /* Internal voltage reference VrefInt */
259 #define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF756AUL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
260 #define VREFINT_CAL_VREF ( 3000UL) /* Analog voltage reference (Vref+) voltage with which VrefInt has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
261 /* Temperature sensor */
262 /* Note: On all devices of series STM32C0, calibration parameter TS_CAL2 is not available.
263 Therefore, macro "__LL_ADC_CALC_TEMPERATURE()" is not available,
264 macro "__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS()" must be used and parameter TS_CAL1 can improve accuracy: replace
265 datasheet parameter of temperature offset (macro argument __TEMPSENSOR_TYP_CALX_V__) by TEMPSENSOR_CAL1_ADDR
266 (with taking into account conversion from digital value resolution 12 bit, analog voltage reference ratio
267 between calibration and application environments) */
268 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF7568UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32C0, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
269 #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
270 #define TEMPSENSOR_CAL_VREFANALOG ( 3000UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
271
272 /**
273 * @}
274 */
275
276
277 /* Private macros ------------------------------------------------------------*/
278 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
279 * @{
280 */
281
282 /**
283 * @brief Driver macro reserved for internal use: set a pointer to
284 * a register from a register basis from which an offset
285 * is applied.
286 * @param __REG__ Register basis from which the offset is applied.
287 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
288 * @retval Pointer to register address
289 */
290 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
291 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
292
293 /**
294 * @}
295 */
296
297
298 /* Exported types ------------------------------------------------------------*/
299 #if defined(USE_FULL_LL_DRIVER)
300 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
301 * @{
302 */
303
304 /**
305 * @brief Structure definition of some features of ADC common parameters
306 * and multimode
307 * (all ADC instances belonging to the same ADC common instance).
308 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
309 * is conditioned to ADC instances state (all ADC instances
310 * sharing the same ADC common instance):
311 * All ADC instances sharing the same ADC common instance must be
312 * disabled.
313 */
314 typedef struct
315 {
316 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
317 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
318
319 This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
320
321 } LL_ADC_CommonInitTypeDef;
322
323 /**
324 * @brief Structure definition of some features of ADC instance.
325 * @note These parameters have an impact on ADC scope: ADC instance.
326 * Refer to corresponding unitary functions into
327 * @ref ADC_LL_EF_Configuration_ADC_Instance .
328 * @note The setting of these parameters by function @ref LL_ADC_Init()
329 * is conditioned to ADC state:
330 * ADC instance must be disabled.
331 * This condition is applied to all ADC features, for efficiency
332 * and compatibility over all STM32 families. However, the different
333 * features can be set under different ADC state conditions
334 * (setting possible with ADC enabled without conversion on going,
335 * ADC enabled with conversion on going, ...)
336 * Each feature can be updated afterwards with a unitary function
337 * and potentially with ADC in a different state than disabled,
338 * refer to description of each function for setting
339 * conditioned to ADC state.
340 */
341 typedef struct
342 {
343 uint32_t Clock; /*!< Set ADC instance clock source and prescaler.
344 This parameter can be a value of @ref ADC_LL_EC_CLOCK_SOURCE
345 @note On this STM32 series, this parameter has some clock ratio constraints:
346 ADC clock synchronous (from PCLK) with prescaler 1 must be enabled only if PCLK has a 50% duty clock cycle
347 (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle).
348
349 This feature can be modified afterwards using unitary function @ref LL_ADC_SetClock().
350 For more details, refer to description of this function. */
351
352 uint32_t Resolution; /*!< Set ADC resolution.
353 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
354
355 This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
356
357 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
358 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
359
360 This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
361
362 uint32_t LowPowerMode; /*!< Set ADC low power mode.
363 This parameter can be a value of @ref ADC_LL_EC_LP_MODE
364
365 This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
366
367 } LL_ADC_InitTypeDef;
368
369 /**
370 * @brief Structure definition of some features of ADC group regular.
371 * @note These parameters have an impact on ADC scope: ADC group regular.
372 * Refer to corresponding unitary functions into
373 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
374 * (functions with prefix "REG").
375 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
376 * is conditioned to ADC state:
377 * ADC instance must be disabled.
378 * This condition is applied to all ADC features, for efficiency
379 * and compatibility over all STM32 families. However, the different
380 * features can be set under different ADC state conditions
381 * (setting possible with ADC enabled without conversion on going,
382 * ADC enabled with conversion on going, ...)
383 * Each feature can be updated afterwards with a unitary function
384 * and potentially with ADC in a different state than disabled,
385 * refer to description of each function for setting
386 * conditioned to ADC state.
387 */
388 typedef struct
389 {
390 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
391 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
392 @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge
393 (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
394 In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
395
396 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
397
398 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
399 @note This parameter has an effect only if group regular sequencer is set to mode "fully configurable". Refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
400 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
401
402 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
403
404 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
405 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
406 @note This parameter has an effect only if group regular sequencer is enabled
407 (depending on the sequencer mode: scan length of 2 ranks or more, or several ADC channels enabled in group regular sequencer. Refer to function @ref LL_ADC_REG_SetSequencerConfigurable() ).
408
409 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
410
411 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
412 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
413 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
414
415 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
416
417 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
418 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
419
420 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
421
422 uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
423 data preserved or overwritten.
424 This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
425
426 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
427
428 } LL_ADC_REG_InitTypeDef;
429
430 /**
431 * @}
432 */
433 #endif /* USE_FULL_LL_DRIVER */
434
435 /* Exported constants --------------------------------------------------------*/
436 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
437 * @{
438 */
439
440 /** @defgroup ADC_LL_EC_FLAG ADC flags
441 * @brief Flags defines which can be used with LL_ADC_ReadReg function
442 * @{
443 */
444 #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
445 #define LL_ADC_FLAG_CCRDY ADC_ISR_CCRDY /*!< ADC flag ADC channel configuration ready */
446 #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */
447 #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */
448 #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
449 #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
450 #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
451 #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
452 #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
453 #define LL_ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC flag end of calibration */
454 /**
455 * @}
456 */
457
458 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
459 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
460 * @{
461 */
462 #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
463 #define LL_ADC_IT_CCRDY ADC_IER_CCRDYIE /*!< ADC interruption channel configuration ready */
464 #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */
465 #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */
466 #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
467 #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */
468 #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
469 #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
470 #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
471 #define LL_ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC interruption ADC end of calibration */
472 /**
473 * @}
474 */
475
476 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
477 * @{
478 */
479 /* List of ADC registers intended to be used (most commonly) with */
480 /* DMA transfer. */
481 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
482 #define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
483 /**
484 * @}
485 */
486
487 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
488 * @{
489 */
490 #define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without prescaler */
491 #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 2. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
492 #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 4. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
493 #define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 6. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
494 #define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 ) /*!< ADC asynchronous clock with prescaler division by 8. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
495 #define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
496 #define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 12. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
497 #define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
498 #define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with prescaler division by 32. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
499 #define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 64. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
500 #define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division by 128. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
501 #define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
502 /**
503 * @}
504 */
505
506 /** @defgroup ADC_LL_EC_COMMON_CLOCK_FREQ_MODE ADC common - Clock frequency mode
507 * @{
508 */
509 #define LL_ADC_CLOCK_FREQ_MODE_HIGH (0x00000000UL) /*!< ADC clock mode to high frequency. On STM32C0, ADC clock frequency above 3.5MHz. */
510 #define LL_ADC_CLOCK_FREQ_MODE_LOW (ADC_CCR_LFMEN) /*!< ADC clock mode to low frequency. On STM32C0, ADC clock frequency below 3.5MHz. */
511 /**
512 * @}
513 */
514
515 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
516 * @{
517 */
518 /* Note: Other measurement paths to internal channels may be available */
519 /* (connections to other peripherals). */
520 /* If they are not listed below, they do not require any specific */
521 /* path enable. In this case, Access to measurement path is done */
522 /* only by selecting the corresponding ADC internal channel. */
523 #define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */
524 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
525 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */
526 /**
527 * @}
528 */
529
530 /** @defgroup ADC_LL_EC_CLOCK_SOURCE ADC instance - Clock source
531 * @{
532 */
533 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by 4 */
534 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock divided by 2 */
535 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CFGR2_CKMODE_1 | ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock not divided */
536 #define LL_ADC_CLOCK_ASYNC (0x00000000UL) /*!< ADC asynchronous clock. Asynchronous clock prescaler can be configured using function @ref LL_ADC_SetCommonClock(). */
537 /**
538 * @}
539 */
540
541 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
542 * @{
543 */
544 #define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bits */
545 #define LL_ADC_RESOLUTION_10B ( ADC_CFGR1_RES_0) /*!< ADC resolution 10 bits */
546 #define LL_ADC_RESOLUTION_8B (ADC_CFGR1_RES_1 ) /*!< ADC resolution 8 bits */
547 #define LL_ADC_RESOLUTION_6B (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution 6 bits */
548 /**
549 * @}
550 */
551
552 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
553 * @{
554 */
555 #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
556 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR1_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
557 /**
558 * @}
559 */
560
561 /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
562 * @{
563 */
564 #define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */
565 #define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_WAIT) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
566 #define LL_ADC_LP_AUTOPOWEROFF (ADC_CFGR1_AUTOFF) /*!< ADC low power mode auto power-off: the ADC automatically powers-off after a ADC conversion and automatically wakes up when a new ADC conversion is triggered (with startup time between trigger and start of sampling). See description with function @ref LL_ADC_SetLowPowerMode(). */
567 #define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF) /*!< ADC low power modes auto wait and auto power-off combined. See description with function @ref LL_ADC_SetLowPowerMode(). */
568 /**
569 * @}
570 */
571
572 /** @defgroup ADC_LL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode
573 * @{
574 */
575 #define LL_ADC_TRIGGER_FREQ_HIGH (0x00000000UL) /*!< ADC trigger frequency mode set to high frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
576 #define LL_ADC_TRIGGER_FREQ_LOW (ADC_CFGR2_LFTRIG) /*!< ADC trigger frequency mode set to low frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
577 /**
578 * @}
579 */
580
581 /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels
582 * @{
583 */
584 #define LL_ADC_SAMPLINGTIME_COMMON_1 (ADC_SMPR_SMP1_BITOFFSET_POS) /*!< Set sampling time common to a group of channels: sampling time nb 1 */
585 #define LL_ADC_SAMPLINGTIME_COMMON_2 (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SAMPLING_TIME_CH_MASK) /*!< Set sampling time common to a group of channels: sampling time nb 2 */
586 /**
587 * @}
588 */
589
590 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
591 * @{
592 */
593 #define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
594 /**
595 * @}
596 */
597
598 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
599 * @{
600 */
601 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
602 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
603 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
604 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
605 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
606 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
607 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
608 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
609 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
610 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
611 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
612 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
613 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
614 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
615 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
616 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
617 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
618 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
619 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
620 #define LL_ADC_CHANNEL_19 (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19 */
621 #define LL_ADC_CHANNEL_20 (ADC_CHANNEL_20_NUMBER | ADC_CHANNEL_20_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN20 */
622 #define LL_ADC_CHANNEL_21 (ADC_CHANNEL_21_NUMBER | ADC_CHANNEL_21_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN21 */
623 #define LL_ADC_CHANNEL_22 (ADC_CHANNEL_22_NUMBER | ADC_CHANNEL_22_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN22 */
624 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_10 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */
625 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_9 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */
626 #define LL_ADC_CHANNEL_VDDA (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VDDA. */
627 #define LL_ADC_CHANNEL_VSSA (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VSSA. */
628 /**
629 * @}
630 */
631
632 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
633 * @{
634 */
635 #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start. */
636 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 ( ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
637 #define LL_ADC_REG_TRIG_EXT_TIM1_CH4 ( ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
638 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO ( ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
639 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
640 /**
641 * @}
642 */
643
644 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
645 * @{
646 */
647 #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
648 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
649 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
650 /**
651 * @}
652 */
653
654 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
655 * @{
656 */
657 #define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions are performed in single mode: one conversion per trigger */
658 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
659 /**
660 * @}
661 */
662
663 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
664 * @{
665 */
666 #define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */
667 #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
668 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
669 /**
670 * @}
671 */
672
673 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
674 * @{
675 */
676 #define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: data preserved */
677 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */
678 /**
679 * @}
680 */
681
682 /** @defgroup ADC_LL_EC_REG_SEQ_MODE ADC group regular - Sequencer configuration flexibility
683 * @{
684 */
685 #define LL_ADC_REG_SEQ_FIXED (0x00000000UL) /*!< Sequencer configured to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number. Refer to description of function @ref LL_ADC_REG_SetSequencerChannels(). */
686 #define LL_ADC_REG_SEQ_CONFIGURABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer configured to fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). */
687 /**
688 * @}
689 */
690
691 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
692 * @{
693 */
694 #define LL_ADC_REG_SEQ_SCAN_DISABLE (ADC_CHSELR_SQ2) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
695 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_CHSELR_SQ3) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
696 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_CHSELR_SQ4) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
697 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
698 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_CHSELR_SQ6) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
699 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_CHSELR_SQ7) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
700 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_CHSELR_SQ8) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
701 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS (0x00000000UL) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
702 /**
703 * @}
704 */
705
706 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION ADC group regular - Sequencer scan direction
707 * @{
708 */
709 #define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000UL) /*!< On this STM32 series, parameter relevant only is sequencer set to mode not fully configurable, refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other STM32 families, this setting is not available and the default scan direction is forward. */
710 #define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR) /*!< On this STM32 series, parameter relevant only is sequencer set to mode not fully configurable, refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan direction backward: from highest channel number to lowest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer) */
711 /**
712 * @}
713 */
714
715 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
716 * @{
717 */
718 #define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer discontinuous mode disable */
719 #define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
720 /**
721 * @}
722 */
723
724 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
725 * @{
726 */
727 #define LL_ADC_REG_RANK_1 (ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
728 #define LL_ADC_REG_RANK_2 (ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
729 #define LL_ADC_REG_RANK_3 (ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
730 #define LL_ADC_REG_RANK_4 (ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
731 #define LL_ADC_REG_RANK_5 (ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
732 #define LL_ADC_REG_RANK_6 (ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
733 #define LL_ADC_REG_RANK_7 (ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
734 #define LL_ADC_REG_RANK_8 (ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
735 /**
736 * @}
737 */
738
739 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
740 * @{
741 */
742 #define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL) /*!< Sampling time 1.5 ADC clock cycle */
743 #define LL_ADC_SAMPLINGTIME_3CYCLES_5 (ADC_SMPR_SMP1_0) /*!< Sampling time 3.5 ADC clock cycles */
744 #define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP1_1) /*!< Sampling time 7.5 ADC clock cycles */
745 #define LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR_SMP1_1 | ADC_SMPR_SMP1_0) /*!< Sampling time 12.5 ADC clock cycles */
746 #define LL_ADC_SAMPLINGTIME_19CYCLES_5 (ADC_SMPR_SMP1_2) /*!< Sampling time 19.5 ADC clock cycles */
747 #define LL_ADC_SAMPLINGTIME_39CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_0) /*!< Sampling time 39.5 ADC clock cycles */
748 #define LL_ADC_SAMPLINGTIME_79CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_1) /*!< Sampling time 79.5 ADC clock cycles */
749 #define LL_ADC_SAMPLINGTIME_160CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_1 | ADC_SMPR_SMP1_0) /*!< Sampling time 160.5 ADC clock cycles */
750 /**
751 * @}
752 */
753
754 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
755 * @{
756 */
757 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
758 #define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
759 #define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
760 /**
761 * @}
762 */
763
764 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
765 * @{
766 */
767 #define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */
768 #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR1_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
769 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
770 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
771 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
772 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
773 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
774 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
775 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
776 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
777 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
778 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
779 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
780 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
781 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
782 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
783 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
784 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
785 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
786 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
787 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
788 #define LL_ADC_AWD_CHANNEL_19_REG ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
789 #define LL_ADC_AWD_CHANNEL_20_REG ((LL_ADC_CHANNEL_20 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
790 #define LL_ADC_AWD_CHANNEL_21_REG ((LL_ADC_CHANNEL_21 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
791 #define LL_ADC_AWD_CHANNEL_22_REG ((LL_ADC_CHANNEL_22 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
792 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
793 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
794 #define LL_ADC_AWD_CH_VSSA_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VSSA : internal analog supply ground, converted by group regular only */
795 #define LL_ADC_AWD_CH_VDDA_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VDDA : internal analog power supply, converted by group regular only */
796 /**
797 * @}
798 */
799
800 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
801 * @{
802 */
803 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD1TR_HT1 ) /*!< ADC analog watchdog threshold high */
804 #define LL_ADC_AWD_THRESHOLD_LOW ( ADC_AWD1TR_LT1) /*!< ADC analog watchdog threshold low */
805 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */
806 /**
807 * @}
808 */
809
810 /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
811 * @{
812 */
813 #define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
814 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_OVSE) /*!< ADC oversampling on conversions of ADC group regular. Literal suffix "continued" is kept for compatibility with other STM32 devices featuring ADC group injected, in this case other oversampling scope parameters are available. */
815 /**
816 * @}
817 */
818
819 /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
820 * @{
821 */
822 #define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
823 #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TOVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
824 /**
825 * @}
826 */
827
828 /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio
829 * @{
830 */
831 #define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
832 #define LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
833 #define LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
834 #define LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
835 #define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2 ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
836 #define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
837 #define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
838 #define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
839 /**
840 * @}
841 */
842
843 /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift
844 * @{
845 */
846 #define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
847 #define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
848 #define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
849 #define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
850 #define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
851 #define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
852 #define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
853 #define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
854 #define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
855 /**
856 * @}
857 */
858
859 /** @defgroup ADC_LL_EC_HELPER_MACRO Definitions of constants used by helper macro
860 * @{
861 */
862 #define LL_ADC_TEMPERATURE_CALC_ERROR ((int16_t)0x7FFF) /* Temperature calculation error using helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(), due to issue on calibration parameters. This value is coded on 16 bits (to fit on signed word or double word) and corresponds to an inconsistent temperature value. */
863 /**
864 * @}
865 */
866
867 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
868 * @note Only ADC peripheral HW delays are defined in ADC LL driver driver,
869 * not timeout values.
870 * For details on delays values, refer to descriptions in source code
871 * above each literal definition.
872 * @{
873 */
874
875 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
876 /* not timeout values. */
877 /* Timeout values for ADC operations are dependent to device clock */
878 /* configuration (system clock versus ADC clock), */
879 /* and therefore must be defined in user application. */
880 /* Indications for estimation of ADC timeout delays, for this */
881 /* STM32 series: */
882 /* - ADC calibration time: maximum delay is 82/fADC. */
883 /* (refer to device datasheet, parameter "tCAL") */
884 /* - ADC enable time: maximum delay is 1 conversion cycle. */
885 /* (refer to device datasheet, parameter "tSTAB") */
886 /* - ADC disable time: maximum delay should be a few ADC clock cycles */
887 /* - ADC stop conversion time: maximum delay should be a few ADC clock */
888 /* cycles */
889 /* - ADC conversion time: duration depending on ADC clock and ADC */
890 /* configuration. */
891 /* (refer to device reference manual, section "Timing") */
892
893 /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
894 /* Delay set to maximum value (refer to device datasheet, */
895 /* parameter "tADCVREG_STUP"). */
896 /* Unit: us */
897 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
898
899 /* Delay for internal voltage reference stabilization time. */
900 /* Delay set to maximum value (refer to device datasheet, */
901 /* parameter "tstart_vrefint"). */
902 /* Unit: us */
903 #define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization time */
904
905 /* Delay for temperature sensor stabilization time. */
906 /* Literal set to maximum value (refer to device datasheet, */
907 /* parameter "tSTART"). */
908 /* Unit: us */
909 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time (starting from temperature sensor enable, refer to @ref LL_ADC_SetCommonPathInternalCh()) */
910 #define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL) /*!< Delay for temperature sensor buffer stabilization time (starting from ADC enable, refer to @ref LL_ADC_Enable()) */
911
912 /* Delay required between ADC end of calibration and ADC enable. */
913 /* Note: On this STM32 series, a minimum number of ADC clock cycles */
914 /* are required between ADC end of calibration and ADC enable. */
915 /* Wait time can be computed in user application by waiting for the */
916 /* equivalent number of CPU cycles, by taking into account */
917 /* ratio of CPU clock versus ADC clock prescalers. */
918 /* Unit: ADC clock cycles. */
919 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 2UL) /*!< Delay required between ADC end of calibration and ADC enable */
920
921 /**
922 * @}
923 */
924
925 /**
926 * @}
927 */
928
929
930 /* Exported macro ------------------------------------------------------------*/
931 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
932 * @{
933 */
934
935 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
936 * @{
937 */
938
939 /**
940 * @brief Write a value in ADC register
941 * @param __INSTANCE__ ADC Instance
942 * @param __REG__ Register to be written
943 * @param __VALUE__ Value to be written in the register
944 * @retval None
945 */
946 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
947
948 /**
949 * @brief Read a value in ADC register
950 * @param __INSTANCE__ ADC Instance
951 * @param __REG__ Register to be read
952 * @retval Register value
953 */
954 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
955 /**
956 * @}
957 */
958
959 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
960 * @{
961 */
962
963 /**
964 * @brief Helper macro to get ADC channel number in decimal format
965 * from literals LL_ADC_CHANNEL_x.
966 * @note Example:
967 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
968 * will return decimal number "4".
969 * @note The input can be a value from functions where a channel
970 * number is returned, either defined with number
971 * or with bitfield (only one bit must be set).
972 * @param __CHANNEL__ This parameter can be one of the following values:
973 * @arg @ref ADC_CHANNEL_0
974 * @arg @ref ADC_CHANNEL_1
975 * @arg @ref ADC_CHANNEL_2
976 * @arg @ref ADC_CHANNEL_3
977 * @arg @ref ADC_CHANNEL_4
978 * @arg @ref ADC_CHANNEL_5
979 * @arg @ref ADC_CHANNEL_6
980 * @arg @ref ADC_CHANNEL_7
981 * @arg @ref ADC_CHANNEL_8 (1)
982 * @arg @ref ADC_CHANNEL_9 (1)
983 * @arg @ref ADC_CHANNEL_10
984 * @arg @ref ADC_CHANNEL_11
985 * @arg @ref ADC_CHANNEL_12
986 * @arg @ref ADC_CHANNEL_13
987 * @arg @ref ADC_CHANNEL_14
988 * @arg @ref ADC_CHANNEL_15 (1)
989 * @arg @ref ADC_CHANNEL_16 (1)
990 * @arg @ref ADC_CHANNEL_17 (3)
991 * @arg @ref ADC_CHANNEL_18 (3)
992 * @arg @ref ADC_CHANNEL_19 (3)
993 * @arg @ref ADC_CHANNEL_20 (3)
994 * @arg @ref ADC_CHANNEL_21 (3)
995 * @arg @ref ADC_CHANNEL_22 (3)
996 * @arg @ref ADC_CHANNEL_VREFINT (2)
997 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
998 * @arg @ref ADC_CHANNEL_VDDA (2)
999 * @arg @ref ADC_CHANNEL_VSSA (2)
1000 *
1001 * (1) On STM32C0, parameter can be set in ADC group sequencer
1002 * only if sequencer is set in mode "not fully configurable",
1003 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
1004 * (2) For ADC channel read back from ADC register,
1005 * comparison with internal channel parameter to be done
1006 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1007 * (3) ADC channels available on STM32C031xx device only.
1008 * @retval Value between Min_Data=0 and Max_Data=18
1009 */
1010 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1011 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ? \
1012 ( \
1013 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
1014 ) \
1015 : \
1016 ((((__CHANNEL__) & ADC_CHANNEL_0_BITFIELD) == ADC_CHANNEL_0_BITFIELD) ? (0UL) : \
1017 ((((__CHANNEL__) & ADC_CHANNEL_1_BITFIELD) == ADC_CHANNEL_1_BITFIELD) ? (1UL) : \
1018 ((((__CHANNEL__) & ADC_CHANNEL_2_BITFIELD) == ADC_CHANNEL_2_BITFIELD) ? (2UL) : \
1019 ((((__CHANNEL__) & ADC_CHANNEL_3_BITFIELD) == ADC_CHANNEL_3_BITFIELD) ? (3UL) : \
1020 ((((__CHANNEL__) & ADC_CHANNEL_4_BITFIELD) == ADC_CHANNEL_4_BITFIELD) ? (4UL) : \
1021 ((((__CHANNEL__) & ADC_CHANNEL_5_BITFIELD) == ADC_CHANNEL_5_BITFIELD) ? (5UL) : \
1022 ((((__CHANNEL__) & ADC_CHANNEL_6_BITFIELD) == ADC_CHANNEL_6_BITFIELD) ? (6UL) : \
1023 ((((__CHANNEL__) & ADC_CHANNEL_7_BITFIELD) == ADC_CHANNEL_7_BITFIELD) ? (7UL) : \
1024 ((((__CHANNEL__) & ADC_CHANNEL_8_BITFIELD) == ADC_CHANNEL_8_BITFIELD) ? (8UL) : \
1025 ((((__CHANNEL__) & ADC_CHANNEL_9_BITFIELD) == ADC_CHANNEL_9_BITFIELD) ? (9UL) : \
1026 ((((__CHANNEL__) & ADC_CHANNEL_10_BITFIELD) == ADC_CHANNEL_10_BITFIELD) ? (10UL) : \
1027 ((((__CHANNEL__) & ADC_CHANNEL_11_BITFIELD) == ADC_CHANNEL_11_BITFIELD) ? (11UL) : \
1028 ((((__CHANNEL__) & ADC_CHANNEL_12_BITFIELD) == ADC_CHANNEL_12_BITFIELD) ? (12UL) : \
1029 ((((__CHANNEL__) & ADC_CHANNEL_13_BITFIELD) == ADC_CHANNEL_13_BITFIELD) ? (13UL) : \
1030 ((((__CHANNEL__) & ADC_CHANNEL_14_BITFIELD) == ADC_CHANNEL_14_BITFIELD) ? (14UL) : \
1031 ((((__CHANNEL__) & ADC_CHANNEL_15_BITFIELD) == ADC_CHANNEL_15_BITFIELD) ? (15UL) : \
1032 ((((__CHANNEL__) & ADC_CHANNEL_16_BITFIELD) == ADC_CHANNEL_16_BITFIELD) ? (16UL) : \
1033 ((((__CHANNEL__) & ADC_CHANNEL_17_BITFIELD) == ADC_CHANNEL_17_BITFIELD) ? (17UL) : \
1034 ((((__CHANNEL__) & ADC_CHANNEL_18_BITFIELD) == ADC_CHANNEL_18_BITFIELD) ? (18UL) : \
1035 ((((__CHANNEL__) & ADC_CHANNEL_19_BITFIELD) == ADC_CHANNEL_19_BITFIELD) ? (19UL) : \
1036 ((((__CHANNEL__) & ADC_CHANNEL_20_BITFIELD) == ADC_CHANNEL_20_BITFIELD) ? (20UL) : \
1037 ((((__CHANNEL__) & ADC_CHANNEL_21_BITFIELD) == ADC_CHANNEL_21_BITFIELD) ? (21UL) : \
1038 ((((__CHANNEL__) & ADC_CHANNEL_22_BITFIELD) == ADC_CHANNEL_22_BITFIELD) ? (22UL) : \
1039 (0UL)))))))))))))))))))))))))
1040
1041 /**
1042 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
1043 * from number in decimal format.
1044 * @note Example:
1045 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
1046 * will return a data equivalent to "LL_ADC_CHANNEL_4".
1047 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
1048 * @retval Returned value can be one of the following values:
1049 * @arg @ref ADC_CHANNEL_0
1050 * @arg @ref ADC_CHANNEL_1
1051 * @arg @ref ADC_CHANNEL_2
1052 * @arg @ref ADC_CHANNEL_3
1053 * @arg @ref ADC_CHANNEL_4
1054 * @arg @ref ADC_CHANNEL_5
1055 * @arg @ref ADC_CHANNEL_6
1056 * @arg @ref ADC_CHANNEL_7
1057 * @arg @ref ADC_CHANNEL_8 (1)
1058 * @arg @ref ADC_CHANNEL_9 (1)
1059 * @arg @ref ADC_CHANNEL_10
1060 * @arg @ref ADC_CHANNEL_11
1061 * @arg @ref ADC_CHANNEL_12
1062 * @arg @ref ADC_CHANNEL_13
1063 * @arg @ref ADC_CHANNEL_14
1064 * @arg @ref ADC_CHANNEL_15 (1)
1065 * @arg @ref ADC_CHANNEL_16 (1)
1066 * @arg @ref ADC_CHANNEL_17 (3)
1067 * @arg @ref ADC_CHANNEL_18 (3)
1068 * @arg @ref ADC_CHANNEL_19 (3)
1069 * @arg @ref ADC_CHANNEL_20 (3)
1070 * @arg @ref ADC_CHANNEL_21 (3)
1071 * @arg @ref ADC_CHANNEL_22 (3)
1072 * @arg @ref ADC_CHANNEL_VREFINT (2)
1073 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
1074 * @arg @ref ADC_CHANNEL_VDDA (2)
1075 * @arg @ref ADC_CHANNEL_VSSA (2)
1076 *
1077 * (1) On STM32C0, parameter can be set in ADC group sequencer
1078 * only if sequencer is set in mode "not fully configurable",
1079 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
1080 * (2) For ADC channel read back from ADC register,
1081 * comparison with internal channel parameter to be done
1082 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1083 * (3) ADC channels available on STM32C031xx device only.
1084 */
1085 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1086 (((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1087 (ADC_CHSELR_CHSEL0 << (__DECIMAL_NB__)))
1088
1089 /**
1090 * @brief Helper macro to determine whether the selected channel
1091 * corresponds to literal definitions of driver.
1092 * @note The different literal definitions of ADC channels are:
1093 * - ADC internal channel:
1094 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
1095 * - ADC external channel (channel connected to a GPIO pin):
1096 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
1097 * @note The channel parameter must be a value defined from literal
1098 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1099 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1100 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
1101 * must not be a value from functions where a channel number is
1102 * returned from ADC registers,
1103 * because internal and external channels share the same channel
1104 * number in ADC registers. The differentiation is made only with
1105 * parameters definitions of driver.
1106 * @param __CHANNEL__ This parameter can be one of the following values:
1107 * @arg @ref ADC_CHANNEL_0
1108 * @arg @ref ADC_CHANNEL_1
1109 * @arg @ref ADC_CHANNEL_2
1110 * @arg @ref ADC_CHANNEL_3
1111 * @arg @ref ADC_CHANNEL_4
1112 * @arg @ref ADC_CHANNEL_5
1113 * @arg @ref ADC_CHANNEL_6
1114 * @arg @ref ADC_CHANNEL_7
1115 * @arg @ref ADC_CHANNEL_8 (1)
1116 * @arg @ref ADC_CHANNEL_9 (1)
1117 * @arg @ref ADC_CHANNEL_10
1118 * @arg @ref ADC_CHANNEL_11
1119 * @arg @ref ADC_CHANNEL_12
1120 * @arg @ref ADC_CHANNEL_13
1121 * @arg @ref ADC_CHANNEL_14
1122 * @arg @ref ADC_CHANNEL_15 (1)
1123 * @arg @ref ADC_CHANNEL_16 (1)
1124 * @arg @ref ADC_CHANNEL_17 (3)
1125 * @arg @ref ADC_CHANNEL_18 (3)
1126 * @arg @ref ADC_CHANNEL_19 (3)
1127 * @arg @ref ADC_CHANNEL_20 (3)
1128 * @arg @ref ADC_CHANNEL_21 (3)
1129 * @arg @ref ADC_CHANNEL_22 (3)
1130 * @arg @ref ADC_CHANNEL_VREFINT (2)
1131 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
1132 * @arg @ref ADC_CHANNEL_VDDA (2)
1133 * @arg @ref ADC_CHANNEL_VSSA (2)
1134 *
1135 * (1) On STM32C0, parameter can be set in ADC group sequencer
1136 * only if sequencer is set in mode "not fully configurable",
1137 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
1138 * (2) For ADC channel read back from ADC register,
1139 * comparison with internal channel parameter to be done
1140 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1141 * (3) ADC channels available on STM32C031xx device only.
1142 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
1143 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
1144 */
1145 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1146 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
1147
1148 /**
1149 * @brief Helper macro to convert a channel defined from parameter
1150 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1151 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1152 * to its equivalent parameter definition of a ADC external channel
1153 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
1154 * @note The channel parameter can be, additionally to a value
1155 * defined from parameter definition of a ADC internal channel
1156 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
1157 * a value defined from parameter definition of
1158 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1159 * or a value from functions where a channel number is returned
1160 * from ADC registers.
1161 * @param __CHANNEL__ This parameter can be one of the following values:
1162 * @arg @ref ADC_CHANNEL_0
1163 * @arg @ref ADC_CHANNEL_1
1164 * @arg @ref ADC_CHANNEL_2
1165 * @arg @ref ADC_CHANNEL_3
1166 * @arg @ref ADC_CHANNEL_4
1167 * @arg @ref ADC_CHANNEL_5
1168 * @arg @ref ADC_CHANNEL_6
1169 * @arg @ref ADC_CHANNEL_7
1170 * @arg @ref ADC_CHANNEL_8 (1)
1171 * @arg @ref ADC_CHANNEL_9 (1)
1172 * @arg @ref ADC_CHANNEL_10
1173 * @arg @ref ADC_CHANNEL_11
1174 * @arg @ref ADC_CHANNEL_12
1175 * @arg @ref ADC_CHANNEL_13
1176 * @arg @ref ADC_CHANNEL_14
1177 * @arg @ref ADC_CHANNEL_15 (1)
1178 * @arg @ref ADC_CHANNEL_16 (1)
1179 * @arg @ref ADC_CHANNEL_17 (3)
1180 * @arg @ref ADC_CHANNEL_18 (3)
1181 * @arg @ref ADC_CHANNEL_19 (3)
1182 * @arg @ref ADC_CHANNEL_20 (3)
1183 * @arg @ref ADC_CHANNEL_21 (3)
1184 * @arg @ref ADC_CHANNEL_22 (3)
1185 * @arg @ref ADC_CHANNEL_VREFINT (2)
1186 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
1187 * @arg @ref ADC_CHANNEL_VDDA (2)
1188 * @arg @ref ADC_CHANNEL_VSSA (2)
1189 *
1190 * (1) On STM32C0, parameter can be set in ADC group sequencer
1191 * only if sequencer is set in mode "not fully configurable",
1192 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
1193 * (2) For ADC channel read back from ADC register,
1194 * comparison with internal channel parameter to be done
1195 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1196 * (3) ADC channels available on STM32C031xx device only.
1197 * @retval Returned value can be one of the following values:
1198 * @arg @ref LL_ADC_CHANNEL_0
1199 * @arg @ref LL_ADC_CHANNEL_1
1200 * @arg @ref LL_ADC_CHANNEL_2
1201 * @arg @ref LL_ADC_CHANNEL_3
1202 * @arg @ref LL_ADC_CHANNEL_4
1203 * @arg @ref LL_ADC_CHANNEL_5
1204 * @arg @ref LL_ADC_CHANNEL_6
1205 * @arg @ref LL_ADC_CHANNEL_7
1206 * @arg @ref LL_ADC_CHANNEL_8
1207 * @arg @ref LL_ADC_CHANNEL_9
1208 * @arg @ref LL_ADC_CHANNEL_10
1209 * @arg @ref LL_ADC_CHANNEL_11
1210 * @arg @ref LL_ADC_CHANNEL_12
1211 * @arg @ref LL_ADC_CHANNEL_13
1212 * @arg @ref LL_ADC_CHANNEL_14
1213 * @arg @ref LL_ADC_CHANNEL_15
1214 * @arg @ref LL_ADC_CHANNEL_16
1215 * @arg @ref LL_ADC_CHANNEL_17
1216 * @arg @ref LL_ADC_CHANNEL_18
1217 * @arg @ref LL_ADC_CHANNEL_19
1218 * @arg @ref LL_ADC_CHANNEL_20
1219 * @arg @ref LL_ADC_CHANNEL_21
1220 * @arg @ref LL_ADC_CHANNEL_22
1221 */
1222 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1223 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1224
1225 /**
1226 * @brief Helper macro to determine whether the internal channel
1227 * selected is available on the ADC instance selected.
1228 * @note The channel parameter must be a value defined from parameter
1229 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1230 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1231 * must not be a value defined from parameter definition of
1232 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1233 * or a value from functions where a channel number is
1234 * returned from ADC registers,
1235 * because internal and external channels share the same channel
1236 * number in ADC registers. The differentiation is made only with
1237 * parameters definitions of driver.
1238 * @param __ADC_INSTANCE__ ADC instance
1239 * @param __CHANNEL__ This parameter can be one of the following values:
1240 * @arg @ref ADC_CHANNEL_VREFINT
1241 * @arg @ref ADC_CHANNEL_TEMPSENSOR
1242 * @arg @ref ADC_CHANNEL_VDDA
1243 * @arg @ref ADC_CHANNEL_VSSA
1244 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
1245 * Value "1" if the internal channel selected is available on the ADC instance selected.
1246 */
1247 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1248 (((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1249 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1250 ((__CHANNEL__) == LL_ADC_CHANNEL_VDDA) || \
1251 ((__CHANNEL__) == LL_ADC_CHANNEL_VSSA))
1252
1253 /**
1254 * @brief Helper macro to define ADC analog watchdog parameter:
1255 * define a single channel to monitor with analog watchdog
1256 * from sequencer channel and groups definition.
1257 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
1258 * Example:
1259 * LL_ADC_SetAnalogWDMonitChannels(
1260 * ADC1, LL_ADC_AWD1,
1261 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
1262 * @param __CHANNEL__ This parameter can be one of the following values:
1263 * @arg @ref ADC_CHANNEL_0
1264 * @arg @ref ADC_CHANNEL_1
1265 * @arg @ref ADC_CHANNEL_2
1266 * @arg @ref ADC_CHANNEL_3
1267 * @arg @ref ADC_CHANNEL_4
1268 * @arg @ref ADC_CHANNEL_5
1269 * @arg @ref ADC_CHANNEL_6
1270 * @arg @ref ADC_CHANNEL_7
1271 * @arg @ref ADC_CHANNEL_8 (1)
1272 * @arg @ref ADC_CHANNEL_9 (1)
1273 * @arg @ref ADC_CHANNEL_10
1274 * @arg @ref ADC_CHANNEL_11
1275 * @arg @ref ADC_CHANNEL_12
1276 * @arg @ref ADC_CHANNEL_13
1277 * @arg @ref ADC_CHANNEL_14
1278 * @arg @ref ADC_CHANNEL_15 (1)
1279 * @arg @ref ADC_CHANNEL_16 (1)
1280 * @arg @ref ADC_CHANNEL_17 (3)
1281 * @arg @ref ADC_CHANNEL_18 (3)
1282 * @arg @ref ADC_CHANNEL_19 (3)
1283 * @arg @ref ADC_CHANNEL_20 (3)
1284 * @arg @ref ADC_CHANNEL_21 (3)
1285 * @arg @ref ADC_CHANNEL_22 (3)
1286 * @arg @ref ADC_CHANNEL_VREFINT (2)
1287 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
1288 * @arg @ref ADC_CHANNEL_VDDA (2)
1289 * @arg @ref ADC_CHANNEL_VSSA (2)
1290 *
1291 * (1) On STM32C0, parameter can be set in ADC group sequencer
1292 * only if sequencer is set in mode "not fully configurable",
1293 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
1294 * (2) For ADC channel read back from ADC register,
1295 * comparison with internal channel parameter to be done
1296 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1297 * (3) ADC channels available on STM32C031xx device only.
1298 * @param __GROUP__ This parameter can be one of the following values:
1299 * @arg @ref LL_ADC_GROUP_REGULAR
1300 * @retval Returned value can be one of the following values:
1301 * @arg @ref LL_ADC_AWD_DISABLE
1302 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
1303 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
1304 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
1305 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
1306 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
1307 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
1308 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
1309 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
1310 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
1311 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
1312 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
1313 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
1314 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
1315 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
1316 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
1317 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
1318 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
1319 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
1320 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
1321 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (1)
1322 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (1)
1323 * @arg @ref LL_ADC_AWD_CHANNEL_20_REG (1)
1324 * @arg @ref LL_ADC_AWD_CHANNEL_21_REG (1)
1325 * @arg @ref LL_ADC_AWD_CHANNEL_22_REG (1)
1326 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG
1327 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
1328 * @arg @ref LL_ADC_AWD_CH_VDDA_REG
1329 * @arg @ref LL_ADC_AWD_CH_VSSA_REG
1330 * (1) On STM32C0, parameter not available on all devices: only on STM32C031xx.
1331 */
1332 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
1333 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
1334
1335 /**
1336 * @brief Helper macro to set the value of ADC analog watchdog threshold high
1337 * or low in function of ADC resolution, when ADC resolution is
1338 * different of 12 bits.
1339 * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
1340 * or @ref LL_ADC_SetAnalogWDThresholds().
1341 * Example, with a ADC resolution of 8 bits, to set the value of
1342 * analog watchdog threshold high (on 8 bits):
1343 * LL_ADC_SetAnalogWDThresholds
1344 * (< ADCx param >,
1345 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
1346 * );
1347 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1348 * @arg @ref LL_ADC_RESOLUTION_12B
1349 * @arg @ref LL_ADC_RESOLUTION_10B
1350 * @arg @ref LL_ADC_RESOLUTION_8B
1351 * @arg @ref LL_ADC_RESOLUTION_6B
1352 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
1353 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1354 */
1355 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
1356 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
1357
1358 /**
1359 * @brief Helper macro to get the value of ADC analog watchdog threshold high
1360 * or low in function of ADC resolution, when ADC resolution is
1361 * different of 12 bits.
1362 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1363 * Example, with a ADC resolution of 8 bits, to get the value of
1364 * analog watchdog threshold high (on 8 bits):
1365 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
1366 * (LL_ADC_RESOLUTION_8B,
1367 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
1368 * );
1369 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1370 * @arg @ref LL_ADC_RESOLUTION_12B
1371 * @arg @ref LL_ADC_RESOLUTION_10B
1372 * @arg @ref LL_ADC_RESOLUTION_8B
1373 * @arg @ref LL_ADC_RESOLUTION_6B
1374 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
1375 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1376 */
1377 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
1378 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
1379
1380 /**
1381 * @brief Helper macro to get the ADC analog watchdog threshold high
1382 * or low from raw value containing both thresholds concatenated.
1383 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1384 * Example, to get analog watchdog threshold high from the register raw value:
1385 * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
1386 * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
1387 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
1388 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
1389 * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1390 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1391 */
1392 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
1393 (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & LL_ADC_AWD_THRESHOLD_LOW)
1394
1395 /**
1396 * @brief Helper macro to select the ADC common instance
1397 * to which is belonging the selected ADC instance.
1398 * @note ADC common register instance can be used for:
1399 * - Set parameters common to several ADC instances
1400 * - Multimode (for devices with several ADC instances)
1401 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1402 * @param __ADCx__ ADC instance
1403 * @retval ADC common register instance
1404 */
1405 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1406 (ADC1_COMMON)
1407
1408 /**
1409 * @brief Helper macro to check if all ADC instances sharing the same
1410 * ADC common instance are disabled.
1411 * @note This check is required by functions with setting conditioned to
1412 * ADC state:
1413 * All ADC instances of the ADC common group must be disabled.
1414 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1415 * @note On devices with only 1 ADC common instance, parameter of this macro
1416 * is useless and can be ignored (parameter kept for compatibility
1417 * with devices featuring several ADC common instances).
1418 * @param __ADCXY_COMMON__ ADC common instance
1419 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1420 * @retval Value "0" if all ADC instances sharing the same ADC common instance
1421 * are disabled.
1422 * Value "1" if at least one ADC instance sharing the same ADC common instance
1423 * is enabled.
1424 */
1425 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1426 LL_ADC_IsEnabled(ADC1)
1427
1428 /**
1429 * @brief Helper macro to define the ADC conversion data full-scale digital
1430 * value corresponding to the selected ADC resolution.
1431 * @note ADC conversion data full-scale corresponds to voltage range
1432 * determined by analog voltage references Vref+ and Vref-
1433 * (refer to reference manual).
1434 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1435 * @arg @ref LL_ADC_RESOLUTION_12B
1436 * @arg @ref LL_ADC_RESOLUTION_10B
1437 * @arg @ref LL_ADC_RESOLUTION_8B
1438 * @arg @ref LL_ADC_RESOLUTION_6B
1439 * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
1440 */
1441 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1442 (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL)))
1443
1444 /**
1445 * @brief Helper macro to convert the ADC conversion data from
1446 * a resolution to another resolution.
1447 * @param __DATA__ ADC conversion data to be converted
1448 * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
1449 * This parameter can be one of the following values:
1450 * @arg @ref LL_ADC_RESOLUTION_12B
1451 * @arg @ref LL_ADC_RESOLUTION_10B
1452 * @arg @ref LL_ADC_RESOLUTION_8B
1453 * @arg @ref LL_ADC_RESOLUTION_6B
1454 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
1455 * This parameter can be one of the following values:
1456 * @arg @ref LL_ADC_RESOLUTION_12B
1457 * @arg @ref LL_ADC_RESOLUTION_10B
1458 * @arg @ref LL_ADC_RESOLUTION_8B
1459 * @arg @ref LL_ADC_RESOLUTION_6B
1460 * @retval ADC conversion data to the requested resolution
1461 */
1462 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
1463 __ADC_RESOLUTION_CURRENT__,\
1464 __ADC_RESOLUTION_TARGET__) \
1465 (((__DATA__) \
1466 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL))) \
1467 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL)) \
1468 )
1469
1470 /**
1471 * @brief Helper macro to calculate the voltage (unit: mVolt)
1472 * corresponding to a ADC conversion data (unit: digital value).
1473 * @note Analog reference voltage (Vref+) must be either known from
1474 * user board environment or can be calculated using ADC measurement
1475 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1476 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
1477 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
1478 * (unit: digital value).
1479 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1480 * @arg @ref LL_ADC_RESOLUTION_12B
1481 * @arg @ref LL_ADC_RESOLUTION_10B
1482 * @arg @ref LL_ADC_RESOLUTION_8B
1483 * @arg @ref LL_ADC_RESOLUTION_6B
1484 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1485 */
1486 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
1487 __ADC_DATA__,\
1488 __ADC_RESOLUTION__) \
1489 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
1490 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1491 )
1492
1493 /**
1494 * @brief Helper macro to calculate analog reference voltage (Vref+)
1495 * (unit: mVolt) from ADC conversion data of internal voltage
1496 * reference VrefInt.
1497 * @note Computation is using VrefInt calibration value
1498 * stored in system memory for each device during production.
1499 * @note This voltage depends on user board environment: voltage level
1500 * connected to pin Vref+.
1501 * On devices with small package, the pin Vref+ is not present
1502 * and internally bonded to pin Vdda.
1503 * @note On this STM32 series, calibration data of internal voltage reference
1504 * VrefInt corresponds to a resolution of 12 bits,
1505 * this is the recommended ADC resolution to convert voltage of
1506 * internal voltage reference VrefInt.
1507 * Otherwise, this macro performs the processing to scale
1508 * ADC conversion data to 12 bits.
1509 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
1510 * of internal voltage reference VrefInt (unit: digital value).
1511 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1512 * @arg @ref LL_ADC_RESOLUTION_12B
1513 * @arg @ref LL_ADC_RESOLUTION_10B
1514 * @arg @ref LL_ADC_RESOLUTION_8B
1515 * @arg @ref LL_ADC_RESOLUTION_6B
1516 * @retval Analog reference voltage (unit: mV)
1517 */
1518 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
1519 __ADC_RESOLUTION__) \
1520 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
1521 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
1522 (__ADC_RESOLUTION__), \
1523 LL_ADC_RESOLUTION_12B) \
1524 )
1525
1526 /**
1527 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1528 * from ADC conversion data of internal temperature sensor.
1529 * @note Computation is using temperature sensor typical values
1530 * (refer to device datasheet).
1531 * @note Calculation formula:
1532 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
1533 * / Avg_Slope + CALx_TEMP
1534 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1535 * (unit: digital value)
1536 * Avg_Slope = temperature sensor slope
1537 * (unit: uV/Degree Celsius)
1538 * TS_TYP_CALx_VOLT = temperature sensor digital value at
1539 * temperature CALx_TEMP (unit: mV)
1540 * Caution: Calculation relevancy under reserve the temperature sensor
1541 * of the current device has characteristics in line with
1542 * datasheet typical values.
1543 * @note: On this STM32 series, calibtation parameter TS_CAL1 can be used
1544 * to improve calculation accuracy.
1545 * Refer to @ref TEMPSENSOR_CAL1_ADDR.
1546 * @note As calculation input, the analog reference voltage (Vref+) must be
1547 * defined as it impacts the ADC LSB equivalent voltage.
1548 * @note Analog reference voltage (Vref+) must be either known from
1549 * user board environment or can be calculated using ADC measurement
1550 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1551 * @note ADC measurement data must correspond to a resolution of 12 bits
1552 * (full scale digital value 4095). If not the case, the data must be
1553 * preliminarily rescaled to an equivalent resolution of 12 bits.
1554 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
1555 * On STM32C0, refer to device datasheet parameter "Avg_Slope".
1556 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
1557 * On STM32C0, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
1558 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
1559 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
1560 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
1561 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
1562 * This parameter can be one of the following values:
1563 * @arg @ref LL_ADC_RESOLUTION_12B
1564 * @arg @ref LL_ADC_RESOLUTION_10B
1565 * @arg @ref LL_ADC_RESOLUTION_8B
1566 * @arg @ref LL_ADC_RESOLUTION_6B
1567 * @retval Temperature (unit: degree Celsius)
1568 */
1569 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
1570 __TEMPSENSOR_TYP_CALX_V__,\
1571 __TEMPSENSOR_CALX_TEMP__,\
1572 __VREFANALOG_VOLTAGE__,\
1573 __TEMPSENSOR_ADC_DATA__,\
1574 __ADC_RESOLUTION__) \
1575 (((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
1576 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
1577 * 1000UL) \
1578 - \
1579 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
1580 * 1000UL) \
1581 ) \
1582 ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
1583 ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
1584 )
1585
1586 /**
1587 * @}
1588 */
1589
1590 /**
1591 * @}
1592 */
1593
1594
1595 /* Exported functions --------------------------------------------------------*/
1596 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
1597 * @{
1598 */
1599
1600 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
1601 * @{
1602 */
1603 /* Note: LL ADC functions to set DMA transfer are located into sections of */
1604 /* configuration of ADC instance, groups and multimode (if available): */
1605 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
1606
1607 /**
1608 * @brief Function to help to configure DMA transfer from ADC: retrieve the
1609 * ADC register address from ADC instance and a list of ADC registers
1610 * intended to be used (most commonly) with DMA transfer.
1611 * @note These ADC registers are data registers:
1612 * when ADC conversion data is available in ADC data registers,
1613 * ADC generates a DMA transfer request.
1614 * @note This macro is intended to be used with LL DMA driver, refer to
1615 * function "LL_DMA_ConfigAddresses()".
1616 * Example:
1617 * LL_DMA_ConfigAddresses(DMA1,
1618 * LL_DMA_CHANNEL_1,
1619 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
1620 * (uint32_t)&< array or variable >,
1621 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
1622 * @note For devices with several ADC: in multimode, some devices
1623 * use a different data register outside of ADC instance scope
1624 * (common data register). This macro manages this register difference,
1625 * only ADC instance has to be set as parameter.
1626 * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr
1627 * @param ADCx ADC instance
1628 * @param Register This parameter can be one of the following values:
1629 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
1630 * @retval ADC register address
1631 */
LL_ADC_DMA_GetRegAddr(ADC_TypeDef * ADCx,uint32_t Register)1632 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
1633 {
1634 /* Prevent unused argument(s) compilation warning */
1635 (void)(Register);
1636
1637 /* Retrieve address of register DR */
1638 return (uint32_t) &(ADCx->DR);
1639 }
1640
1641 /**
1642 * @}
1643 */
1644
1645 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
1646 * @{
1647 */
1648
1649 /**
1650 * @brief Set parameter common to several ADC: Clock source and prescaler.
1651 * @note On this STM32 series, setting of this feature is conditioned to
1652 * ADC state:
1653 * All ADC instances of the ADC common group must be disabled.
1654 * This check can be done with function @ref LL_ADC_IsEnabled() for each
1655 * ADC instance or by using helper macro helper macro
1656 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
1657 * @rmtoll CCR PRESC LL_ADC_SetCommonClock
1658 * @param ADCxy_COMMON ADC common instance
1659 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1660 * @param CommonClock This parameter can be one of the following values:
1661 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 (1)
1662 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 (1)
1663 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 (1)
1664 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 (1)
1665 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 (1)
1666 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 (1)
1667 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 (1)
1668 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 (1)
1669 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 (1)
1670 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 (1)
1671 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1)
1672 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1)
1673 *
1674 * (1) ADC common clock asynchronous prescaler is applied to
1675 * each ADC instance if the corresponding ADC instance clock
1676 * is set to clock source asynchronous.
1677 * (refer to function @ref LL_ADC_SetClock() ).
1678 * @retval None
1679 */
LL_ADC_SetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t CommonClock)1680 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
1681 {
1682 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_PRESC, CommonClock);
1683 }
1684
1685 /**
1686 * @brief Get parameter common to several ADC: Clock source and prescaler.
1687 * @rmtoll CCR PRESC LL_ADC_GetCommonClock
1688 * @param ADCxy_COMMON ADC common instance
1689 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1690 * @retval Returned value can be one of the following values:
1691 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 (1)
1692 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 (1)
1693 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 (1)
1694 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 (1)
1695 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 (1)
1696 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 (1)
1697 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 (1)
1698 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 (1)
1699 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 (1)
1700 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 (1)
1701 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1)
1702 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1)
1703 *
1704 * (1) ADC common clock asynchronous prescaler is applied to
1705 * each ADC instance if the corresponding ADC instance clock
1706 * is set to clock source asynchronous.
1707 * (refer to function @ref LL_ADC_SetClock() ).
1708 */
LL_ADC_GetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON)1709 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
1710 {
1711 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC));
1712 }
1713
1714 /**
1715 * @brief Set parameter common to several ADC: measurement path to
1716 * internal channels (VrefInt, temperature sensor, ...).
1717 * Configure all paths (overwrite current configuration).
1718 * @note One or several values can be selected.
1719 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1720 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1721 * The values not selected are removed from configuration.
1722 * @note Stabilization time of measurement path to internal channel:
1723 * After enabling internal paths, before starting ADC conversion,
1724 * a delay is required for internal voltage reference and
1725 * temperature sensor stabilization time.
1726 * Refer to device datasheet.
1727 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
1728 * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
1729 * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
1730 * @note ADC internal channel sampling time constraint:
1731 * For ADC conversion of internal channels,
1732 * a sampling time minimum value is required.
1733 * Refer to device datasheet.
1734 * @note On this STM32 series, setting of this feature is conditioned to
1735 * ADC state:
1736 * All ADC instances of the ADC common group must be disabled.
1737 * This check can be done with function @ref LL_ADC_IsEnabled() for each
1738 * ADC instance or by using helper macro helper macro
1739 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
1740 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
1741 * CCR TSEN LL_ADC_SetCommonPathInternalCh\n
1742 * CCR VBATEN LL_ADC_SetCommonPathInternalCh
1743 * @param ADCxy_COMMON ADC common instance
1744 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1745 * @param PathInternal This parameter can be a combination of the following values:
1746 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1747 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1748 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1749 * @retval None
1750 */
LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)1751 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
1752 {
1753 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN, PathInternal);
1754 }
1755
1756 /**
1757 * @brief Set parameter common to several ADC: measurement path to
1758 * internal channels (VrefInt, temperature sensor, ...).
1759 * Add paths to the current configuration.
1760 * @note One or several values can be selected.
1761 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1762 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1763 * @note Stabilization time of measurement path to internal channel:
1764 * After enabling internal paths, before starting ADC conversion,
1765 * a delay is required for internal voltage reference and
1766 * temperature sensor stabilization time.
1767 * Refer to device datasheet.
1768 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
1769 * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
1770 * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
1771 * @note ADC internal channel sampling time constraint:
1772 * For ADC conversion of internal channels,
1773 * a sampling time minimum value is required.
1774 * Refer to device datasheet.
1775 * @note On this STM32 series, setting of this feature is conditioned to
1776 * ADC state:
1777 * All ADC instances of the ADC common group must be disabled.
1778 * This check can be done with function @ref LL_ADC_IsEnabled() for each
1779 * ADC instance or by using helper macro helper macro
1780 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
1781 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n
1782 * CCR TSEN LL_ADC_SetCommonPathInternalChAdd\n
1783 * @param ADCxy_COMMON ADC common instance
1784 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1785 * @param PathInternal This parameter can be a combination of the following values:
1786 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1787 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1788 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1789 * @retval None
1790 */
LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)1791 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
1792 {
1793 SET_BIT(ADCxy_COMMON->CCR, PathInternal);
1794 }
1795
1796 /**
1797 * @brief Set parameter common to several ADC: measurement path to
1798 * internal channels (VrefInt, temperature sensor, ...).
1799 * Remove paths to the current configuration.
1800 * @note One or several values can be selected.
1801 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1802 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1803 * @note On this STM32 series, setting of this feature is conditioned to
1804 * ADC state:
1805 * All ADC instances of the ADC common group must be disabled.
1806 * This check can be done with function @ref LL_ADC_IsEnabled() for each
1807 * ADC instance or by using helper macro helper macro
1808 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
1809 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n
1810 * CCR TSEN LL_ADC_SetCommonPathInternalChRem\n
1811 * @param ADCxy_COMMON ADC common instance
1812 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1813 * @param PathInternal This parameter can be a combination of the following values:
1814 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1815 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1816 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1817 * @retval None
1818 */
LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)1819 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
1820 {
1821 CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
1822 }
1823
1824 /**
1825 * @brief Get parameter common to several ADC: measurement path to internal
1826 * channels (VrefInt, temperature sensor, ...).
1827 * @note One or several values can be selected.
1828 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1829 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1830 * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
1831 * CCR TSEN LL_ADC_GetCommonPathInternalCh\n
1832 * CCR VBATEN LL_ADC_GetCommonPathInternalCh
1833 * @param ADCxy_COMMON ADC common instance
1834 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1835 * @retval Returned value can be a combination of the following values:
1836 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1837 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1838 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1839 */
LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON)1840 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
1841 {
1842 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN));
1843 }
1844
1845 /**
1846 * @}
1847 */
1848
1849 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
1850 * @{
1851 */
1852
1853 /**
1854 * @brief Set ADC instance clock source and prescaler.
1855 * @note On this STM32 series, setting of this feature is conditioned to
1856 * ADC state:
1857 * ADC must be disabled.
1858 * @rmtoll CFGR2 CKMODE LL_ADC_SetClock
1859 * @param ADCx ADC instance
1860 * @param ClockSource This parameter can be one of the following values:
1861 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
1862 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
1863 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2)
1864 * @arg @ref LL_ADC_CLOCK_ASYNC (1)
1865 *
1866 * (1) Asynchronous clock prescaler can be configured using
1867 * function @ref LL_ADC_SetCommonClock().\n
1868 * (2) Caution: This parameter has some clock ratio constraints:
1869 * This configuration must be enabled only if PCLK has a 50%
1870 * duty clock cycle (APB prescaler configured inside the RCC
1871 * must be bypassed and the system clock must by 50% duty
1872 * cycle).
1873 * Refer to reference manual.
1874 * @retval None
1875 */
LL_ADC_SetClock(ADC_TypeDef * ADCx,uint32_t ClockSource)1876 __STATIC_INLINE void LL_ADC_SetClock(ADC_TypeDef *ADCx, uint32_t ClockSource)
1877 {
1878 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource);
1879 }
1880
1881 /**
1882 * @brief Get ADC instance clock source and prescaler.
1883 * @rmtoll CFGR2 CKMODE LL_ADC_GetClock
1884 * @param ADCx ADC instance
1885 * @retval Returned value can be one of the following values:
1886 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
1887 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
1888 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2)
1889 * @arg @ref LL_ADC_CLOCK_ASYNC (1)
1890 *
1891 * (1) Asynchronous clock prescaler can be retrieved using
1892 * function @ref LL_ADC_GetCommonClock().\n
1893 * (2) Caution: This parameter has some clock ratio constraints:
1894 * This configuration must be enabled only if PCLK has a 50%
1895 * duty clock cycle (APB prescaler configured inside the RCC
1896 * must be bypassed and the system clock must by 50% duty
1897 * cycle).
1898 * Refer to reference manual.
1899 */
LL_ADC_GetClock(ADC_TypeDef * ADCx)1900 __STATIC_INLINE uint32_t LL_ADC_GetClock(ADC_TypeDef *ADCx)
1901 {
1902 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE));
1903 }
1904
1905 /**
1906 * @brief Set ADC calibration factor in the mode single-ended
1907 * or differential (for devices with differential mode available).
1908 * @note This function is intended to set calibration parameters
1909 * without having to perform a new calibration using
1910 * @ref LL_ADC_StartCalibration().
1911 * @note On this STM32 series, setting of this feature is conditioned to
1912 * ADC state:
1913 * ADC must be enabled, without calibration on going, without conversion
1914 * on going on group regular.
1915 * @rmtoll CALFACT CALFACT LL_ADC_SetCalibrationFactor
1916 * @param ADCx ADC instance
1917 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
1918 * @retval None
1919 */
LL_ADC_SetCalibrationFactor(ADC_TypeDef * ADCx,uint32_t CalibrationFactor)1920 __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t CalibrationFactor)
1921 {
1922 MODIFY_REG(ADCx->CALFACT,
1923 ADC_CALFACT_CALFACT,
1924 CalibrationFactor);
1925 }
1926
1927 /**
1928 * @brief Get ADC calibration factor in the mode single-ended
1929 * or differential (for devices with differential mode available).
1930 * @note Calibration factors are set by hardware after performing
1931 * a calibration run using function @ref LL_ADC_StartCalibration().
1932 * @rmtoll CALFACT CALFACT LL_ADC_GetCalibrationFactor
1933 * @param ADCx ADC instance
1934 * @retval Value between Min_Data=0x00 and Max_Data=0x7F
1935 */
LL_ADC_GetCalibrationFactor(ADC_TypeDef * ADCx)1936 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx)
1937 {
1938 return (uint32_t)(READ_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT));
1939 }
1940
1941 /**
1942 * @brief Set ADC resolution.
1943 * Refer to reference manual for alignments formats
1944 * dependencies to ADC resolutions.
1945 * @note On this STM32 series, setting of this feature is conditioned to
1946 * ADC state:
1947 * ADC must be disabled.
1948 * @rmtoll CFGR1 RES LL_ADC_SetResolution
1949 * @param ADCx ADC instance
1950 * @param Resolution This parameter can be one of the following values:
1951 * @arg @ref LL_ADC_RESOLUTION_12B
1952 * @arg @ref LL_ADC_RESOLUTION_10B
1953 * @arg @ref LL_ADC_RESOLUTION_8B
1954 * @arg @ref LL_ADC_RESOLUTION_6B
1955 * @retval None
1956 */
LL_ADC_SetResolution(ADC_TypeDef * ADCx,uint32_t Resolution)1957 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
1958 {
1959 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution);
1960 }
1961
1962 /**
1963 * @brief Get ADC resolution.
1964 * Refer to reference manual for alignments formats
1965 * dependencies to ADC resolutions.
1966 * @rmtoll CFGR1 RES LL_ADC_GetResolution
1967 * @param ADCx ADC instance
1968 * @retval Returned value can be one of the following values:
1969 * @arg @ref LL_ADC_RESOLUTION_12B
1970 * @arg @ref LL_ADC_RESOLUTION_10B
1971 * @arg @ref LL_ADC_RESOLUTION_8B
1972 * @arg @ref LL_ADC_RESOLUTION_6B
1973 */
LL_ADC_GetResolution(ADC_TypeDef * ADCx)1974 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
1975 {
1976 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES));
1977 }
1978
1979 /**
1980 * @brief Set ADC conversion data alignment.
1981 * @note Refer to reference manual for alignments formats
1982 * dependencies to ADC resolutions.
1983 * @note On this STM32 series, setting of this feature is conditioned to
1984 * ADC state:
1985 * ADC must be disabled.
1986 * @rmtoll CFGR1 ALIGN LL_ADC_SetDataAlignment
1987 * @param ADCx ADC instance
1988 * @param DataAlignment This parameter can be one of the following values:
1989 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
1990 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
1991 * @retval None
1992 */
LL_ADC_SetDataAlignment(ADC_TypeDef * ADCx,uint32_t DataAlignment)1993 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
1994 {
1995 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_ALIGN, DataAlignment);
1996 }
1997
1998 /**
1999 * @brief Get ADC conversion data alignment.
2000 * @note Refer to reference manual for alignments formats
2001 * dependencies to ADC resolutions.
2002 * @rmtoll CFGR1 ALIGN LL_ADC_GetDataAlignment
2003 * @param ADCx ADC instance
2004 * @retval Returned value can be one of the following values:
2005 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2006 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2007 */
LL_ADC_GetDataAlignment(ADC_TypeDef * ADCx)2008 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
2009 {
2010 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN));
2011 }
2012
2013 /**
2014 * @brief Set ADC low power mode.
2015 * @note Description of ADC low power modes:
2016 * - ADC low power mode "auto wait": Dynamic low power mode,
2017 * ADC conversions occurrences are limited to the minimum necessary
2018 * in order to reduce power consumption.
2019 * New ADC conversion starts only when the previous
2020 * unitary conversion data (for ADC group regular)
2021 * has been retrieved by user software.
2022 * In the meantime, ADC remains idle: does not performs any
2023 * other conversion.
2024 * This mode allows to automatically adapt the ADC conversions
2025 * triggers to the speed of the software that reads the data.
2026 * Moreover, this avoids risk of overrun for low frequency
2027 * applications.
2028 * How to use this low power mode:
2029 * - It is not recommended to use with interruption or DMA
2030 * since these modes have to clear immediately the EOC flag
2031 * (by CPU to free the IRQ pending event or by DMA).
2032 * Auto wait will work but fort a very short time, discarding
2033 * its intended benefit (except specific case of high load of CPU
2034 * or DMA transfers which can justify usage of auto wait).
2035 * - Do use with polling: 1. Start conversion,
2036 * 2. Later on, when conversion data is needed: poll for end of
2037 * conversion to ensure that conversion is completed and
2038 * retrieve ADC conversion data. This will trig another
2039 * ADC conversion start.
2040 * - ADC low power mode "auto power-off" (feature available on
2041 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
2042 * the ADC automatically powers-off after a conversion and
2043 * automatically wakes up when a new conversion is triggered
2044 * (with startup time between trigger and start of sampling).
2045 * This feature can be combined with low power mode "auto wait".
2046 * @note With ADC low power mode "auto wait", the ADC conversion data read
2047 * is corresponding to previous ADC conversion start, independently
2048 * of delay during which ADC was idle.
2049 * Therefore, the ADC conversion data may be outdated: does not
2050 * correspond to the current voltage level on the selected
2051 * ADC channel.
2052 * @note On this STM32 series, setting of this feature is conditioned to
2053 * ADC state:
2054 * ADC must be disabled.
2055 * @rmtoll CFGR1 WAIT LL_ADC_SetLowPowerMode\n
2056 * CFGR1 AUTOFF LL_ADC_SetLowPowerMode
2057 * @param ADCx ADC instance
2058 * @param LowPowerMode This parameter can be one of the following values:
2059 * @arg @ref LL_ADC_LP_MODE_NONE
2060 * @arg @ref LL_ADC_LP_AUTOWAIT
2061 * @arg @ref LL_ADC_LP_AUTOPOWEROFF
2062 * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF
2063 * @retval None
2064 */
LL_ADC_SetLowPowerMode(ADC_TypeDef * ADCx,uint32_t LowPowerMode)2065 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
2066 {
2067 MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF), LowPowerMode);
2068 }
2069
2070 /**
2071 * @brief Get ADC low power mode:
2072 * @note Description of ADC low power modes:
2073 * - ADC low power mode "auto wait": Dynamic low power mode,
2074 * ADC conversions occurrences are limited to the minimum necessary
2075 * in order to reduce power consumption.
2076 * New ADC conversion starts only when the previous
2077 * unitary conversion data (for ADC group regular)
2078 * has been retrieved by user software.
2079 * In the meantime, ADC remains idle: does not performs any
2080 * other conversion.
2081 * This mode allows to automatically adapt the ADC conversions
2082 * triggers to the speed of the software that reads the data.
2083 * Moreover, this avoids risk of overrun for low frequency
2084 * applications.
2085 * How to use this low power mode:
2086 * - It is not recommended to use with interruption or DMA
2087 * since these modes have to clear immediately the EOC flag
2088 * (by CPU to free the IRQ pending event or by DMA).
2089 * Auto wait will work but fort a very short time, discarding
2090 * its intended benefit (except specific case of high load of CPU
2091 * or DMA transfers which can justify usage of auto wait).
2092 * - Do use with polling: 1. Start conversion,
2093 * 2. Later on, when conversion data is needed: poll for end of
2094 * conversion to ensure that conversion is completed and
2095 * retrieve ADC conversion data. This will trig another
2096 * ADC conversion start.
2097 * - ADC low power mode "auto power-off" (feature available on
2098 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
2099 * the ADC automatically powers-off after a conversion and
2100 * automatically wakes up when a new conversion is triggered
2101 * (with startup time between trigger and start of sampling).
2102 * This feature can be combined with low power mode "auto wait".
2103 * @note With ADC low power mode "auto wait", the ADC conversion data read
2104 * is corresponding to previous ADC conversion start, independently
2105 * of delay during which ADC was idle.
2106 * Therefore, the ADC conversion data may be outdated: does not
2107 * correspond to the current voltage level on the selected
2108 * ADC channel.
2109 * @rmtoll CFGR1 WAIT LL_ADC_GetLowPowerMode\n
2110 * CFGR1 AUTOFF LL_ADC_GetLowPowerMode
2111 * @param ADCx ADC instance
2112 * @retval Returned value can be one of the following values:
2113 * @arg @ref LL_ADC_LP_MODE_NONE
2114 * @arg @ref LL_ADC_LP_AUTOWAIT
2115 * @arg @ref LL_ADC_LP_AUTOPOWEROFF
2116 * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF
2117 */
LL_ADC_GetLowPowerMode(ADC_TypeDef * ADCx)2118 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
2119 {
2120 return (uint32_t)(READ_BIT(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF)));
2121 }
2122
2123 /**
2124 * @brief Set ADC trigger frequency mode.
2125 * @note ADC trigger frequency mode must be set to low frequency when
2126 * a duration is exceeded before ADC conversion start trigger event
2127 * (between ADC enable and ADC conversion start trigger event
2128 * or between two ADC conversion start trigger event).
2129 * Duration value: Refer to device datasheet, parameter "tIdle".
2130 * @note When ADC trigger frequency mode is set to low frequency,
2131 * some rearm cycles are inserted before performing ADC conversion
2132 * start, inducing a delay of 2 ADC clock cycles.
2133 * @note Usage of ADC trigger frequency mode with ADC low power mode:
2134 * - Low power mode auto wait: Only the first ADC conversion
2135 * start trigger inserts the rearm delay.
2136 * - Low power mode auto power-off: ADC trigger frequency mode
2137 * is discarded.
2138 * @note On this STM32 series, setting of this feature is conditioned to
2139 * ADC state:
2140 * ADC must be disabled.
2141 * @rmtoll CFGR2 LFTRIG LL_ADC_SetTriggerFrequencyMode
2142 * @param ADCx ADC instance
2143 * @param TriggerFrequencyMode This parameter can be one of the following values:
2144 * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH
2145 * @arg @ref LL_ADC_TRIGGER_FREQ_LOW
2146 * @retval None
2147 */
LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef * ADCx,uint32_t TriggerFrequencyMode)2148 __STATIC_INLINE void LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef *ADCx, uint32_t TriggerFrequencyMode)
2149 {
2150 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LFTRIG, TriggerFrequencyMode);
2151 }
2152
2153 /**
2154 * @brief Get ADC trigger frequency mode.
2155 * @rmtoll CFGR2 LFTRIG LL_ADC_GetTriggerFrequencyMode
2156 * @param ADCx ADC instance
2157 * @retval Returned value can be one of the following values:
2158 * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH
2159 * @arg @ref LL_ADC_TRIGGER_FREQ_LOW
2160 */
LL_ADC_GetTriggerFrequencyMode(ADC_TypeDef * ADCx)2161 __STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(ADC_TypeDef *ADCx)
2162 {
2163 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG));
2164 }
2165
2166 /**
2167 * @brief Set sampling time common to a group of channels.
2168 * @note Unit: ADC clock cycles.
2169 * @note On this STM32 series, sampling time scope is on ADC instance:
2170 * Sampling time common to all channels.
2171 * (on some other STM32 families, sampling time is channel wise)
2172 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
2173 * converted:
2174 * sampling time constraints must be respected (sampling time can be
2175 * adjusted in function of ADC clock frequency and sampling time
2176 * setting).
2177 * Refer to device datasheet for timings values (parameters TS_vrefint,
2178 * TS_temp, ...).
2179 * @note Conversion time is the addition of sampling time and processing time.
2180 * On this STM32 series, ADC processing time is:
2181 * - 12.5 ADC clock cycles at ADC resolution 12 bits
2182 * - 10.5 ADC clock cycles at ADC resolution 10 bits
2183 * - 8.5 ADC clock cycles at ADC resolution 8 bits
2184 * - 6.5 ADC clock cycles at ADC resolution 6 bits
2185 * @note In case of ADC conversion of internal channel (VrefInt,
2186 * temperature sensor, ...), a sampling time minimum value
2187 * is required.
2188 * Refer to device datasheet.
2189 * @note On this STM32 series, setting of this feature is conditioned to
2190 * ADC state:
2191 * ADC must be disabled or enabled without conversion on going
2192 * on group regular.
2193 * @rmtoll SMPR SMP1 LL_ADC_SetSamplingTimeCommonChannels\n
2194 * @rmtoll SMPR SMP2 LL_ADC_SetSamplingTimeCommonChannels
2195 * @param ADCx ADC instance
2196 * @param SamplingTimeY This parameter can be one of the following values:
2197 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
2198 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
2199 * @param SamplingTime This parameter can be one of the following values:
2200 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
2201 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5
2202 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
2203 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
2204 * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
2205 * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5
2206 * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5
2207 * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5
2208 * @retval None
2209 */
LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef * ADCx,uint32_t SamplingTimeY,uint32_t SamplingTime)2210 __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY,
2211 uint32_t SamplingTime)
2212 {
2213 MODIFY_REG(ADCx->SMPR,
2214 ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK),
2215 SamplingTime << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK));
2216 }
2217
2218 /**
2219 * @brief Get sampling time common to a group of channels.
2220 * @note Unit: ADC clock cycles.
2221 * @note On this STM32 series, sampling time scope is on ADC instance:
2222 * Sampling time common to all channels.
2223 * (on some other STM32 families, sampling time is channel wise)
2224 * @note Conversion time is the addition of sampling time and processing time.
2225 * Refer to reference manual for ADC processing time of
2226 * this STM32 series.
2227 * @rmtoll SMPR SMP1 LL_ADC_GetSamplingTimeCommonChannels\n
2228 * @rmtoll SMPR SMP2 LL_ADC_GetSamplingTimeCommonChannels
2229 * @param ADCx ADC instance
2230 * @param SamplingTimeY This parameter can be one of the following values:
2231 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
2232 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
2233 * @retval Returned value can be one of the following values:
2234 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
2235 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5
2236 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
2237 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
2238 * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
2239 * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5
2240 * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5
2241 * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5
2242 */
LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef * ADCx,uint32_t SamplingTimeY)2243 __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY)
2244 {
2245 return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)))
2246 >> (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK));
2247 }
2248
2249 /**
2250 * @}
2251 */
2252
2253 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
2254 * @{
2255 */
2256
2257 /**
2258 * @brief Set ADC group regular conversion trigger source:
2259 * internal (SW start) or from external peripheral (timer event,
2260 * external interrupt line).
2261 * @note On this STM32 series, setting trigger source to external trigger
2262 * also set trigger polarity to rising edge
2263 * (default setting for compatibility with some ADC on other
2264 * STM32 families having this setting set by HW default value).
2265 * In case of need to modify trigger edge, use
2266 * function @ref LL_ADC_REG_SetTriggerEdge().
2267 * @note On this STM32 series, ADC trigger frequency mode must be set
2268 * in function of frequency of ADC group regular conversion trigger.
2269 * Refer to description of function
2270 * @ref LL_ADC_SetTriggerFrequencyMode().
2271 * @note Availability of parameters of trigger sources from timer
2272 * depends on timers availability on the selected device.
2273 * @note On this STM32 series, setting of this feature is conditioned to
2274 * ADC state:
2275 * ADC must be disabled.
2276 * @rmtoll CFGR1 EXTSEL LL_ADC_REG_SetTriggerSource\n
2277 * CFGR1 EXTEN LL_ADC_REG_SetTriggerSource
2278 * @param ADCx ADC instance
2279 * @param TriggerSource This parameter can be one of the following values:
2280 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2281 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
2282 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4
2283 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
2284 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
2285 * @retval None
2286 */
LL_ADC_REG_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)2287 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
2288 {
2289 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource);
2290 }
2291
2292 /**
2293 * @brief Get ADC group regular conversion trigger source:
2294 * internal (SW start) or from external peripheral (timer event,
2295 * external interrupt line).
2296 * @note To determine whether group regular trigger source is
2297 * internal (SW start) or external, without detail
2298 * of which peripheral is selected as external trigger,
2299 * (equivalent to
2300 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
2301 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
2302 * @note Availability of parameters of trigger sources from timer
2303 * depends on timers availability on the selected device.
2304 * @rmtoll CFGR1 EXTSEL LL_ADC_REG_GetTriggerSource\n
2305 * CFGR1 EXTEN LL_ADC_REG_GetTriggerSource
2306 * @param ADCx ADC instance
2307 * @retval Returned value can be one of the following values:
2308 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2309 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
2310 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4
2311 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
2312 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
2313 */
LL_ADC_REG_GetTriggerSource(ADC_TypeDef * ADCx)2314 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
2315 {
2316 __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN);
2317
2318 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
2319 /* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}. */
2320 uint32_t ShiftExten = ((TriggerSource & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
2321
2322 /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL */
2323 /* to match with triggers literals definition. */
2324 return ((TriggerSource
2325 & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR1_EXTSEL)
2326 | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR1_EXTEN)
2327 );
2328 }
2329
2330 /**
2331 * @brief Get ADC group regular conversion trigger source internal (SW start)
2332 * or external.
2333 * @note In case of group regular trigger source set to external trigger,
2334 * to determine which peripheral is selected as external trigger,
2335 * use function @ref LL_ADC_REG_GetTriggerSource().
2336 * @rmtoll CFGR1 EXTEN LL_ADC_REG_IsTriggerSourceSWStart
2337 * @param ADCx ADC instance
2338 * @retval Value "0" if trigger source external trigger
2339 * Value "1" if trigger source SW start.
2340 */
LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef * ADCx)2341 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
2342 {
2343 return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ? 1UL : 0UL);
2344 }
2345
2346 /**
2347 * @brief Set ADC group regular conversion trigger polarity.
2348 * @note Applicable only for trigger source set to external trigger.
2349 * @note On this STM32 series, setting of this feature is conditioned to
2350 * ADC state:
2351 * ADC must be disabled or enabled without conversion on going
2352 * on group regular.
2353 * @rmtoll CFGR1 EXTEN LL_ADC_REG_SetTriggerEdge
2354 * @param ADCx ADC instance
2355 * @param ExternalTriggerEdge This parameter can be one of the following values:
2356 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
2357 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
2358 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
2359 * @retval None
2360 */
LL_ADC_REG_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)2361 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
2362 {
2363 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge);
2364 }
2365
2366 /**
2367 * @brief Get ADC group regular conversion trigger polarity.
2368 * @note Applicable only for trigger source set to external trigger.
2369 * @rmtoll CFGR1 EXTEN LL_ADC_REG_GetTriggerEdge
2370 * @param ADCx ADC instance
2371 * @retval Returned value can be one of the following values:
2372 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
2373 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
2374 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
2375 */
LL_ADC_REG_GetTriggerEdge(ADC_TypeDef * ADCx)2376 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
2377 {
2378 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN));
2379 }
2380
2381 /**
2382 * @brief Set ADC group regular sequencer configuration flexibility.
2383 * @note On this STM32 series, ADC group regular sequencer both modes
2384 * "fully configurable" or "not fully configurable" are
2385 * available:
2386 * - sequencer configured to fully configurable:
2387 * sequencer length and each rank
2388 * affectation to a channel are configurable.
2389 * Refer to description of function
2390 * @ref LL_ADC_REG_SetSequencerLength().
2391 * - sequencer configured to not fully configurable:
2392 * sequencer length and each rank affectation to a channel
2393 * are fixed by channel HW number.
2394 * Refer to description of function
2395 * @ref LL_ADC_REG_SetSequencerChannels().
2396 * @note On this STM32 series, after modifying sequencer (functions
2397 * @ref LL_ADC_REG_SetSequencerLength()
2398 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
2399 * it is mandatory to wait for the assertion of CCRDY flag
2400 * Otherwise, some actions may be ignored.
2401 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
2402 * for more details.
2403 * @note On this STM32 series, setting of this feature is conditioned to
2404 * ADC state:
2405 * ADC must be disabled.
2406 * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable
2407 * @param ADCx ADC instance
2408 * @param Configurability This parameter can be one of the following values:
2409 * @arg @ref LL_ADC_REG_SEQ_FIXED
2410 * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE
2411 * @retval None
2412 */
LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef * ADCx,uint32_t Configurability)2413 __STATIC_INLINE void LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef *ADCx, uint32_t Configurability)
2414 {
2415 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD, Configurability);
2416 }
2417
2418 /**
2419 * @brief Get ADC group regular sequencer configuration flexibility.
2420 * @note On this STM32 series, ADC group regular sequencer both modes
2421 * "fully configurable" or "not fully configurable" are
2422 * available:
2423 * - sequencer configured to fully configurable:
2424 * sequencer length and each rank
2425 * affectation to a channel are configurable.
2426 * Refer to description of function
2427 * @ref LL_ADC_REG_SetSequencerLength().
2428 * - sequencer configured to not fully configurable:
2429 * sequencer length and each rank affectation to a channel
2430 * are fixed by channel HW number.
2431 * Refer to description of function
2432 * @ref LL_ADC_REG_SetSequencerChannels().
2433 * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable
2434 * @param ADCx ADC instance
2435 * @retval Returned value can be one of the following values:
2436 * @arg @ref LL_ADC_REG_SEQ_FIXED
2437 * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE
2438 */
LL_ADC_REG_GetSequencerConfigurable(ADC_TypeDef * ADCx)2439 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerConfigurable(ADC_TypeDef *ADCx)
2440 {
2441 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD));
2442 }
2443
2444 /**
2445 * @brief Set ADC group regular sequencer length and scan direction.
2446 * @note Description of ADC group regular sequencer features:
2447 * - For devices with sequencer fully configurable
2448 * (function "LL_ADC_REG_SetSequencerRanks()" available):
2449 * sequencer length and each rank affectation to a channel
2450 * are configurable.
2451 * This function performs configuration of:
2452 * - Sequence length: Number of ranks in the scan sequence.
2453 * - Sequence direction: Unless specified in parameters, sequencer
2454 * scan direction is forward (from rank 1 to rank n).
2455 * Sequencer ranks are selected using
2456 * function "LL_ADC_REG_SetSequencerRanks()".
2457 * - For devices with sequencer not fully configurable
2458 * (function "LL_ADC_REG_SetSequencerChannels()" available):
2459 * sequencer length and each rank affectation to a channel
2460 * are defined by channel number.
2461 * This function performs configuration of:
2462 * - Sequence length: Number of ranks in the scan sequence is
2463 * defined by number of channels set in the sequence,
2464 * rank of each channel is fixed by channel HW number.
2465 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2466 * - Sequence direction: Unless specified in parameters, sequencer
2467 * scan direction is forward (from lowest channel number to
2468 * highest channel number).
2469 * Sequencer ranks are selected using
2470 * function "LL_ADC_REG_SetSequencerChannels()".
2471 * To set scan direction differently, refer to function
2472 * @ref LL_ADC_REG_SetSequencerScanDirection().
2473 * @note On this STM32 series, ADC group regular sequencer both modes
2474 * "fully configurable" or "not fully configurable"
2475 * are available, they can be chosen using
2476 * function @ref LL_ADC_REG_SetSequencerConfigurable().
2477 * @note On this STM32 series, after modifying sequencer (functions
2478 * @ref LL_ADC_REG_SetSequencerLength()
2479 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
2480 * it is mandatory to wait for the assertion of CCRDY flag
2481 * using @ref LL_ADC_IsActiveFlag_CCRDY().
2482 * Otherwise, some actions may be ignored.
2483 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
2484 * for more details.
2485 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2486 * ADC conversion on only 1 channel.
2487 * @note On this STM32 series, setting of this feature is conditioned to
2488 * ADC state:
2489 * ADC must be disabled or enabled without conversion on going
2490 * on group regular.
2491 * @rmtoll CHSELR SQ1 LL_ADC_REG_SetSequencerLength\n
2492 * CHSELR SQ2 LL_ADC_REG_SetSequencerLength\n
2493 * CHSELR SQ3 LL_ADC_REG_SetSequencerLength\n
2494 * CHSELR SQ4 LL_ADC_REG_SetSequencerLength\n
2495 * CHSELR SQ5 LL_ADC_REG_SetSequencerLength\n
2496 * CHSELR SQ6 LL_ADC_REG_SetSequencerLength\n
2497 * CHSELR SQ7 LL_ADC_REG_SetSequencerLength\n
2498 * CHSELR SQ8 LL_ADC_REG_SetSequencerLength
2499 * @param ADCx ADC instance
2500 * @param SequencerNbRanks This parameter can be one of the following values:
2501 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
2502 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
2503 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
2504 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
2505 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
2506 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
2507 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
2508 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
2509 * @retval None
2510 */
LL_ADC_REG_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)2511 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
2512 {
2513 SET_BIT(ADCx->CHSELR, SequencerNbRanks);
2514 }
2515
2516 /**
2517 * @brief Get ADC group regular sequencer length and scan direction.
2518 * @note Description of ADC group regular sequencer features:
2519 * - For devices with sequencer fully configurable
2520 * (function "LL_ADC_REG_SetSequencerRanks()" available):
2521 * sequencer length and each rank affectation to a channel
2522 * are configurable.
2523 * This function retrieves:
2524 * - Sequence length: Number of ranks in the scan sequence.
2525 * - Sequence direction: Unless specified in parameters, sequencer
2526 * scan direction is forward (from rank 1 to rank n).
2527 * Sequencer ranks are selected using
2528 * function "LL_ADC_REG_SetSequencerRanks()".
2529 * - For devices with sequencer not fully configurable
2530 * (function "LL_ADC_REG_SetSequencerChannels()" available):
2531 * sequencer length and each rank affectation to a channel
2532 * are defined by channel number.
2533 * This function retrieves:
2534 * - Sequence length: Number of ranks in the scan sequence is
2535 * defined by number of channels set in the sequence,
2536 * rank of each channel is fixed by channel HW number.
2537 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2538 * - Sequence direction: Unless specified in parameters, sequencer
2539 * scan direction is forward (from lowest channel number to
2540 * highest channel number).
2541 * Sequencer ranks are selected using
2542 * function "LL_ADC_REG_SetSequencerChannels()".
2543 * To set scan direction differently, refer to function
2544 * @ref LL_ADC_REG_SetSequencerScanDirection().
2545 * @note On this STM32 series, ADC group regular sequencer both modes
2546 * "fully configurable" or "not fully configurable"
2547 * are available, they can be chosen using
2548 * function @ref LL_ADC_REG_SetSequencerConfigurable().
2549 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2550 * ADC conversion on only 1 channel.
2551 * @rmtoll CHSELR SQ1 LL_ADC_REG_GetSequencerLength\n
2552 * CHSELR SQ2 LL_ADC_REG_GetSequencerLength\n
2553 * CHSELR SQ3 LL_ADC_REG_GetSequencerLength\n
2554 * CHSELR SQ4 LL_ADC_REG_GetSequencerLength\n
2555 * CHSELR SQ5 LL_ADC_REG_GetSequencerLength\n
2556 * CHSELR SQ6 LL_ADC_REG_GetSequencerLength\n
2557 * CHSELR SQ7 LL_ADC_REG_GetSequencerLength\n
2558 * CHSELR SQ8 LL_ADC_REG_GetSequencerLength
2559 * @param ADCx ADC instance
2560 * @retval Returned value can be one of the following values:
2561 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
2562 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
2563 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
2564 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
2565 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
2566 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
2567 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
2568 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
2569 */
LL_ADC_REG_GetSequencerLength(ADC_TypeDef * ADCx)2570 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
2571 {
2572 __IO uint32_t ChannelsRanks = READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ_ALL);
2573 uint32_t SequencerLength = LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS;
2574 uint32_t RankIndex;
2575
2576 /* Parse register for end of sequence identifier */
2577 for (RankIndex = 0UL; RankIndex < (32U - 4U); RankIndex += 4U)
2578 {
2579 if ((ChannelsRanks & (ADC_CHSELR_SQ2 << RankIndex)) == (ADC_CHSELR_SQ2 << RankIndex))
2580 {
2581 SequencerLength = (ADC_CHSELR_SQ2 << RankIndex);
2582 break;
2583 }
2584 }
2585
2586 return SequencerLength;
2587 }
2588
2589 /**
2590 * @brief Set ADC group regular sequencer scan direction.
2591 * @note On this STM32 series, parameter relevant only is sequencer is set
2592 * to mode not fully configurable,
2593 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
2594 * @note On some other STM32 series, this setting is not available and
2595 * the default scan direction is forward.
2596 * @note On this STM32 series, after modifying sequencer (functions
2597 * @ref LL_ADC_REG_SetSequencerLength()
2598 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
2599 * it is mandatory to wait for the assertion of CCRDY flag
2600 * using @ref LL_ADC_IsActiveFlag_CCRDY().
2601 * Otherwise, some actions may be ignored.
2602 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
2603 * for more details.
2604 * @note On this STM32 series, setting of this feature is conditioned to
2605 * ADC state:
2606 * ADC must be disabled.
2607 * @rmtoll CFGR1 SCANDIR LL_ADC_REG_SetSequencerScanDirection
2608 * @param ADCx ADC instance
2609 * @param ScanDirection This parameter can be one of the following values:
2610 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
2611 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
2612 * @retval None
2613 */
LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef * ADCx,uint32_t ScanDirection)2614 __STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uint32_t ScanDirection)
2615 {
2616 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_SCANDIR, ScanDirection);
2617 }
2618
2619 /**
2620 * @brief Get ADC group regular sequencer scan direction.
2621 * @note On this STM32 series, parameter relevant only is sequencer is set
2622 * to mode not fully configurable,
2623 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
2624 * @note On some other STM32 families, this setting is not available and
2625 * the default scan direction is forward.
2626 * @rmtoll CFGR1 SCANDIR LL_ADC_REG_GetSequencerScanDirection
2627 * @param ADCx ADC instance
2628 * @retval Returned value can be one of the following values:
2629 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
2630 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
2631 */
LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef * ADCx)2632 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef *ADCx)
2633 {
2634 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR));
2635 }
2636
2637 /**
2638 * @brief Set ADC group regular sequencer discontinuous mode:
2639 * sequence subdivided and scan conversions interrupted every selected
2640 * number of ranks.
2641 * @note It is not possible to enable both ADC group regular
2642 * continuous mode and sequencer discontinuous mode.
2643 * @note On this STM32 series, setting of this feature is conditioned to
2644 * ADC state:
2645 * ADC must be disabled.
2646 * @rmtoll CFGR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
2647 * @param ADCx ADC instance
2648 * @param SeqDiscont This parameter can be one of the following values:
2649 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2650 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2651 * @retval None
2652 */
LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)2653 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
2654 {
2655 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN, SeqDiscont);
2656 }
2657
2658 /**
2659 * @brief Get ADC group regular sequencer discontinuous mode:
2660 * sequence subdivided and scan conversions interrupted every selected
2661 * number of ranks.
2662 * @rmtoll CFGR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
2663 * @param ADCx ADC instance
2664 * @retval Returned value can be one of the following values:
2665 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2666 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2667 */
LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef * ADCx)2668 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
2669 {
2670 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN));
2671 }
2672
2673 /**
2674 * @brief Set ADC group regular sequence: channel on the selected
2675 * scan sequence rank.
2676 * @note This function performs configuration of:
2677 * - Channels ordering into each rank of scan sequence:
2678 * whatever channel can be placed into whatever rank.
2679 * @note On this STM32 series, ADC group regular sequencer is
2680 * fully configurable: sequencer length and each rank
2681 * affectation to a channel are configurable.
2682 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
2683 * @note Depending on devices and packages, some channels may not be available.
2684 * Refer to device datasheet for channels availability.
2685 * @note On this STM32 series, to measure internal channels (VrefInt,
2686 * TempSensor, ...), measurement paths to internal channels must be
2687 * enabled separately.
2688 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2689 * @note On this STM32 series, after modifying sequencer (functions
2690 * @ref LL_ADC_REG_SetSequencerLength()
2691 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
2692 * it is mandatory to wait for the assertion of CCRDY flag
2693 * using @ref LL_ADC_IsActiveFlag_CCRDY().
2694 * Otherwise, some actions may be ignored.
2695 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
2696 * for more details.
2697 * @note On this STM32 series, setting of this feature is conditioned to
2698 * ADC state:
2699 * ADC must be disabled or enabled without conversion on going
2700 * on group regular.
2701 * @rmtoll CHSELR SQ1 LL_ADC_REG_SetSequencerRanks\n
2702 * CHSELR SQ2 LL_ADC_REG_SetSequencerRanks\n
2703 * CHSELR SQ3 LL_ADC_REG_SetSequencerRanks\n
2704 * CHSELR SQ4 LL_ADC_REG_SetSequencerRanks\n
2705 * CHSELR SQ5 LL_ADC_REG_SetSequencerRanks\n
2706 * CHSELR SQ6 LL_ADC_REG_SetSequencerRanks\n
2707 * CHSELR SQ7 LL_ADC_REG_SetSequencerRanks\n
2708 * CHSELR SQ8 LL_ADC_REG_SetSequencerRanks
2709 * @param ADCx ADC instance
2710 * @param Rank This parameter can be one of the following values:
2711 * @arg @ref LL_ADC_REG_RANK_1
2712 * @arg @ref LL_ADC_REG_RANK_2
2713 * @arg @ref LL_ADC_REG_RANK_3
2714 * @arg @ref LL_ADC_REG_RANK_4
2715 * @arg @ref LL_ADC_REG_RANK_5
2716 * @arg @ref LL_ADC_REG_RANK_6
2717 * @arg @ref LL_ADC_REG_RANK_7
2718 * @arg @ref LL_ADC_REG_RANK_8
2719 * @param Channel This parameter can be one of the following values:
2720 * @arg @ref ADC_CHANNEL_0
2721 * @arg @ref ADC_CHANNEL_1
2722 * @arg @ref ADC_CHANNEL_2
2723 * @arg @ref ADC_CHANNEL_3
2724 * @arg @ref ADC_CHANNEL_4
2725 * @arg @ref ADC_CHANNEL_5
2726 * @arg @ref ADC_CHANNEL_6
2727 * @arg @ref ADC_CHANNEL_7
2728 * @arg @ref ADC_CHANNEL_8 (1)
2729 * @arg @ref ADC_CHANNEL_9 (1)
2730 * @arg @ref ADC_CHANNEL_10
2731 * @arg @ref ADC_CHANNEL_11
2732 * @arg @ref ADC_CHANNEL_12
2733 * @arg @ref ADC_CHANNEL_13
2734 * @arg @ref ADC_CHANNEL_14
2735 * @arg @ref ADC_CHANNEL_15 (1)
2736 * @arg @ref ADC_CHANNEL_16 (1)
2737 * @arg @ref ADC_CHANNEL_17 (3)
2738 * @arg @ref ADC_CHANNEL_18 (3)
2739 * @arg @ref ADC_CHANNEL_19 (3)
2740 * @arg @ref ADC_CHANNEL_20 (3)
2741 * @arg @ref ADC_CHANNEL_21 (3)
2742 * @arg @ref ADC_CHANNEL_22 (3)
2743 * @arg @ref ADC_CHANNEL_VREFINT (2)
2744 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
2745 * @arg @ref ADC_CHANNEL_VDDA (2)
2746 * @arg @ref ADC_CHANNEL_VSSA (2)
2747 *
2748 * (1) On STM32C0, parameter can be set in ADC group sequencer
2749 * only if sequencer is set in mode "not fully configurable",
2750 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
2751 * (2) For ADC channel read back from ADC register,
2752 * comparison with internal channel parameter to be done
2753 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2754 * (3) ADC channels available on STM32C031xx device only.
2755 * @retval None
2756 */
LL_ADC_REG_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)2757 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
2758 {
2759 /* Set bits with content of parameter "Channel" with bits position */
2760 /* in register depending on parameter "Rank". */
2761 /* Parameters "Rank" and "Channel" are used with masks because containing */
2762 /* other bits reserved for other purpose. */
2763 MODIFY_REG(ADCx->CHSELR,
2764 ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
2765 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK_SEQ) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
2766 }
2767
2768 /**
2769 * @brief Get ADC group regular sequence: channel on the selected
2770 * scan sequence rank.
2771 * @note On this STM32 series, ADC group regular sequencer is
2772 * fully configurable: sequencer length and each rank
2773 * affectation to a channel are configurable.
2774 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
2775 * @note Depending on devices and packages, some channels may not be available.
2776 * Refer to device datasheet for channels availability.
2777 * @note Usage of the returned channel number:
2778 * - To reinject this channel into another function LL_ADC_xxx:
2779 * the returned channel number is only partly formatted on definition
2780 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
2781 * with parts of literals LL_ADC_CHANNEL_x or using
2782 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2783 * Then the selected literal LL_ADC_CHANNEL_x can be used
2784 * as parameter for another function.
2785 * - To get the channel number in decimal format:
2786 * process the returned value with the helper macro
2787 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2788 * @rmtoll CHSELR SQ1 LL_ADC_REG_GetSequencerRanks\n
2789 * CHSELR SQ2 LL_ADC_REG_GetSequencerRanks\n
2790 * CHSELR SQ3 LL_ADC_REG_GetSequencerRanks\n
2791 * CHSELR SQ4 LL_ADC_REG_GetSequencerRanks\n
2792 * CHSELR SQ5 LL_ADC_REG_GetSequencerRanks\n
2793 * CHSELR SQ6 LL_ADC_REG_GetSequencerRanks\n
2794 * CHSELR SQ7 LL_ADC_REG_GetSequencerRanks\n
2795 * CHSELR SQ8 LL_ADC_REG_GetSequencerRanks
2796 * @param ADCx ADC instance
2797 * @param Rank This parameter can be one of the following values:
2798 * @arg @ref LL_ADC_REG_RANK_1
2799 * @arg @ref LL_ADC_REG_RANK_2
2800 * @arg @ref LL_ADC_REG_RANK_3
2801 * @arg @ref LL_ADC_REG_RANK_4
2802 * @arg @ref LL_ADC_REG_RANK_5
2803 * @arg @ref LL_ADC_REG_RANK_6
2804 * @arg @ref LL_ADC_REG_RANK_7
2805 * @arg @ref LL_ADC_REG_RANK_8
2806 * @retval Returned value can be one of the following values:
2807 * @arg @ref ADC_CHANNEL_0
2808 * @arg @ref ADC_CHANNEL_1
2809 * @arg @ref ADC_CHANNEL_2
2810 * @arg @ref ADC_CHANNEL_3
2811 * @arg @ref ADC_CHANNEL_4
2812 * @arg @ref ADC_CHANNEL_5
2813 * @arg @ref ADC_CHANNEL_6
2814 * @arg @ref ADC_CHANNEL_7
2815 * @arg @ref ADC_CHANNEL_8 (1)
2816 * @arg @ref ADC_CHANNEL_9 (1)
2817 * @arg @ref ADC_CHANNEL_10
2818 * @arg @ref ADC_CHANNEL_11
2819 * @arg @ref ADC_CHANNEL_12
2820 * @arg @ref ADC_CHANNEL_13
2821 * @arg @ref ADC_CHANNEL_14
2822 * @arg @ref ADC_CHANNEL_15 (1)
2823 * @arg @ref ADC_CHANNEL_16 (1)
2824 * @arg @ref ADC_CHANNEL_17 (3)
2825 * @arg @ref ADC_CHANNEL_18 (3)
2826 * @arg @ref ADC_CHANNEL_19 (3)
2827 * @arg @ref ADC_CHANNEL_20 (3)
2828 * @arg @ref ADC_CHANNEL_21 (3)
2829 * @arg @ref ADC_CHANNEL_22 (3)
2830 * @arg @ref ADC_CHANNEL_VREFINT (2)
2831 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
2832 * @arg @ref ADC_CHANNEL_VDDA (2)
2833 * @arg @ref ADC_CHANNEL_VSSA (2)
2834 *
2835 * (1) On STM32C0, parameter can be set in ADC group sequencer
2836 * only if sequencer is set in mode "not fully configurable",
2837 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
2838 * (2) For ADC channel read back from ADC register,
2839 * comparison with internal channel parameter to be done
2840 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2841 * (3) ADC channels available on STM32C031xx device only.
2842 */
LL_ADC_REG_GetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank)2843 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
2844 {
2845 return (uint32_t)((READ_BIT(ADCx->CHSELR,
2846 ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
2847 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
2848 ) << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
2849 );
2850 }
2851
2852 /**
2853 * @brief Set ADC group regular sequence: channel on rank corresponding to
2854 * channel number.
2855 * @note This function performs:
2856 * - Channels ordering into each rank of scan sequence:
2857 * rank of each channel is fixed by channel HW number
2858 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2859 * - Set channels selected by overwriting the current sequencer
2860 * configuration.
2861 * @note On this STM32 series, ADC group regular sequencer both modes
2862 * "fully configurable" or "not fully configurable"
2863 * are available, they can be chosen using
2864 * function @ref LL_ADC_REG_SetSequencerConfigurable().
2865 * This function can be used with setting "not fully configurable".
2866 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
2867 * and @ref LL_ADC_REG_SetSequencerLength().
2868 * @note On this STM32 series, after modifying sequencer (functions
2869 * @ref LL_ADC_REG_SetSequencerLength()
2870 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
2871 * it is mandatory to wait for the assertion of CCRDY flag
2872 * using @ref LL_ADC_IsActiveFlag_CCRDY().
2873 * Otherwise, some actions may be ignored.
2874 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
2875 * for more details.
2876 * @note Depending on devices and packages, some channels may not be available.
2877 * Refer to device datasheet for channels availability.
2878 * @note On this STM32 series, to measure internal channels (VrefInt,
2879 * TempSensor, ...), measurement paths to internal channels must be
2880 * enabled separately.
2881 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2882 * @note On this STM32 series, setting of this feature is conditioned to
2883 * ADC state:
2884 * ADC must be disabled or enabled without conversion on going
2885 * on group regular.
2886 * @note One or several values can be selected.
2887 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
2888 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChannels\n
2889 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChannels\n
2890 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChannels\n
2891 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChannels\n
2892 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChannels\n
2893 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChannels\n
2894 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChannels\n
2895 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChannels\n
2896 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChannels\n
2897 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChannels\n
2898 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChannels\n
2899 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChannels\n
2900 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChannels\n
2901 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChannels\n
2902 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChannels\n
2903 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChannels\n
2904 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChannels\n
2905 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChannels\n
2906 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChannels
2907 * @param ADCx ADC instance
2908 * @param Channel This parameter can be a combination of the following values:
2909 * @arg @ref ADC_CHANNEL_0
2910 * @arg @ref ADC_CHANNEL_1
2911 * @arg @ref ADC_CHANNEL_2
2912 * @arg @ref ADC_CHANNEL_3
2913 * @arg @ref ADC_CHANNEL_4
2914 * @arg @ref ADC_CHANNEL_5
2915 * @arg @ref ADC_CHANNEL_6
2916 * @arg @ref ADC_CHANNEL_7
2917 * @arg @ref ADC_CHANNEL_8 (1)
2918 * @arg @ref ADC_CHANNEL_9 (1)
2919 * @arg @ref ADC_CHANNEL_10
2920 * @arg @ref ADC_CHANNEL_11
2921 * @arg @ref ADC_CHANNEL_12
2922 * @arg @ref ADC_CHANNEL_13
2923 * @arg @ref ADC_CHANNEL_14
2924 * @arg @ref ADC_CHANNEL_15 (1)
2925 * @arg @ref ADC_CHANNEL_16 (1)
2926 * @arg @ref ADC_CHANNEL_17 (3)
2927 * @arg @ref ADC_CHANNEL_18 (3)
2928 * @arg @ref ADC_CHANNEL_19 (3)
2929 * @arg @ref ADC_CHANNEL_20 (3)
2930 * @arg @ref ADC_CHANNEL_21 (3)
2931 * @arg @ref ADC_CHANNEL_22 (3)
2932 * @arg @ref ADC_CHANNEL_VREFINT (2)
2933 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
2934 * @arg @ref ADC_CHANNEL_VDDA (2)
2935 * @arg @ref ADC_CHANNEL_VSSA (2)
2936 *
2937 * (1) On STM32C0, parameter can be set in ADC group sequencer
2938 * only if sequencer is set in mode "not fully configurable",
2939 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
2940 * (2) For ADC channel read back from ADC register,
2941 * comparison with internal channel parameter to be done
2942 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2943 * (3) ADC channels available on STM32C031xx device only.
2944 * @retval None
2945 */
LL_ADC_REG_SetSequencerChannels(ADC_TypeDef * ADCx,uint32_t Channel)2946 __STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel)
2947 {
2948 /* Parameter "Channel" is used with masks because containing */
2949 /* other bits reserved for other purpose. */
2950 WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
2951 }
2952
2953 /**
2954 * @brief Add channel to ADC group regular sequence: channel on rank corresponding to
2955 * channel number.
2956 * @note This function performs:
2957 * - Channels ordering into each rank of scan sequence:
2958 * rank of each channel is fixed by channel HW number
2959 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2960 * - Set channels selected by adding them to the current sequencer
2961 * configuration.
2962 * @note On this STM32 series, ADC group regular sequencer both modes
2963 * "fully configurable" or "not fully configurable"
2964 * are available, they can be chosen using
2965 * function @ref LL_ADC_REG_SetSequencerConfigurable().
2966 * This function can be used with setting "not fully configurable".
2967 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
2968 * and @ref LL_ADC_REG_SetSequencerLength().
2969 * @note On this STM32 series, after modifying sequencer (functions
2970 * @ref LL_ADC_REG_SetSequencerLength()
2971 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
2972 * it is mandatory to wait for the assertion of CCRDY flag
2973 * using @ref LL_ADC_IsActiveFlag_CCRDY().
2974 * Otherwise, some actions may be ignored.
2975 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
2976 * for more details.
2977 * @note Depending on devices and packages, some channels may not be available.
2978 * Refer to device datasheet for channels availability.
2979 * @note On this STM32 series, to measure internal channels (VrefInt,
2980 * TempSensor, ...), measurement paths to internal channels must be
2981 * enabled separately.
2982 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2983 * @note On this STM32 series, setting of this feature is conditioned to
2984 * ADC state:
2985 * ADC must be disabled or enabled without conversion on going
2986 * on group regular.
2987 * @note One or several values can be selected.
2988 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
2989 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChAdd\n
2990 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChAdd\n
2991 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChAdd\n
2992 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChAdd\n
2993 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChAdd\n
2994 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChAdd\n
2995 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChAdd\n
2996 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChAdd\n
2997 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChAdd\n
2998 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChAdd\n
2999 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChAdd\n
3000 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChAdd\n
3001 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChAdd\n
3002 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChAdd\n
3003 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChAdd\n
3004 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChAdd\n
3005 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChAdd\n
3006 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChAdd\n
3007 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChAdd
3008 * @param ADCx ADC instance
3009 * @param Channel This parameter can be a combination of the following values:
3010 * @arg @ref ADC_CHANNEL_0
3011 * @arg @ref ADC_CHANNEL_1
3012 * @arg @ref ADC_CHANNEL_2
3013 * @arg @ref ADC_CHANNEL_3
3014 * @arg @ref ADC_CHANNEL_4
3015 * @arg @ref ADC_CHANNEL_5
3016 * @arg @ref ADC_CHANNEL_6
3017 * @arg @ref ADC_CHANNEL_7
3018 * @arg @ref ADC_CHANNEL_8 (1)
3019 * @arg @ref ADC_CHANNEL_9 (1)
3020 * @arg @ref ADC_CHANNEL_10
3021 * @arg @ref ADC_CHANNEL_11
3022 * @arg @ref ADC_CHANNEL_12
3023 * @arg @ref ADC_CHANNEL_13
3024 * @arg @ref ADC_CHANNEL_14
3025 * @arg @ref ADC_CHANNEL_15 (1)
3026 * @arg @ref ADC_CHANNEL_16 (1)
3027 * @arg @ref ADC_CHANNEL_17 (3)
3028 * @arg @ref ADC_CHANNEL_18 (3)
3029 * @arg @ref ADC_CHANNEL_19 (3)
3030 * @arg @ref ADC_CHANNEL_20 (3)
3031 * @arg @ref ADC_CHANNEL_21 (3)
3032 * @arg @ref ADC_CHANNEL_22 (3)
3033 * @arg @ref ADC_CHANNEL_VREFINT (2)
3034 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
3035 * @arg @ref ADC_CHANNEL_VDDA (2)
3036 * @arg @ref ADC_CHANNEL_VSSA (2)
3037 *
3038 * (1) On STM32C0, parameter can be set in ADC group sequencer
3039 * only if sequencer is set in mode "not fully configurable",
3040 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
3041 * (2) For ADC channel read back from ADC register,
3042 * comparison with internal channel parameter to be done
3043 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3044 * (3) ADC channels available on STM32C031xx device only.
3045 * @retval None
3046 */
LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef * ADCx,uint32_t Channel)3047 __STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel)
3048 {
3049 /* Parameter "Channel" is used with masks because containing */
3050 /* other bits reserved for other purpose. */
3051 SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
3052 }
3053
3054 /**
3055 * @brief Remove channel to ADC group regular sequence: channel on rank corresponding to
3056 * channel number.
3057 * @note This function performs:
3058 * - Channels ordering into each rank of scan sequence:
3059 * rank of each channel is fixed by channel HW number
3060 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3061 * - Set channels selected by removing them to the current sequencer
3062 * configuration.
3063 * @note On this STM32 series, ADC group regular sequencer both modes
3064 * "fully configurable" or "not fully configurable"
3065 * are available, they can be chosen using
3066 * function @ref LL_ADC_REG_SetSequencerConfigurable().
3067 * This function can be used with setting "not fully configurable".
3068 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
3069 * and @ref LL_ADC_REG_SetSequencerLength().
3070 * @note On this STM32 series, after modifying sequencer (functions
3071 * @ref LL_ADC_REG_SetSequencerLength()
3072 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
3073 * it is mandatory to wait for the assertion of CCRDY flag
3074 * using @ref LL_ADC_IsActiveFlag_CCRDY().
3075 * Otherwise, some actions may be ignored.
3076 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
3077 * for more details.
3078 * @note Depending on devices and packages, some channels may not be available.
3079 * Refer to device datasheet for channels availability.
3080 * @note On this STM32 series, to measure internal channels (VrefInt,
3081 * TempSensor, ...), measurement paths to internal channels must be
3082 * enabled separately.
3083 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3084 * @note On this STM32 series, setting of this feature is conditioned to
3085 * ADC state:
3086 * ADC must be disabled or enabled without conversion on going
3087 * on group regular.
3088 * @note One or several values can be selected.
3089 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
3090 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChRem\n
3091 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChRem\n
3092 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChRem\n
3093 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChRem\n
3094 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChRem\n
3095 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChRem\n
3096 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChRem\n
3097 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChRem\n
3098 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChRem\n
3099 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChRem\n
3100 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChRem\n
3101 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChRem\n
3102 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChRem\n
3103 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChRem\n
3104 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChRem\n
3105 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChRem\n
3106 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChRem\n
3107 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChRem\n
3108 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChRem
3109 * @param ADCx ADC instance
3110 * @param Channel This parameter can be a combination of the following values:
3111 * @arg @ref ADC_CHANNEL_0
3112 * @arg @ref ADC_CHANNEL_1
3113 * @arg @ref ADC_CHANNEL_2
3114 * @arg @ref ADC_CHANNEL_3
3115 * @arg @ref ADC_CHANNEL_4
3116 * @arg @ref ADC_CHANNEL_5
3117 * @arg @ref ADC_CHANNEL_6
3118 * @arg @ref ADC_CHANNEL_7
3119 * @arg @ref ADC_CHANNEL_8 (1)
3120 * @arg @ref ADC_CHANNEL_9 (1)
3121 * @arg @ref ADC_CHANNEL_10
3122 * @arg @ref ADC_CHANNEL_11
3123 * @arg @ref ADC_CHANNEL_12
3124 * @arg @ref ADC_CHANNEL_13
3125 * @arg @ref ADC_CHANNEL_14
3126 * @arg @ref ADC_CHANNEL_15 (1)
3127 * @arg @ref ADC_CHANNEL_16 (1)
3128 * @arg @ref ADC_CHANNEL_17 (3)
3129 * @arg @ref ADC_CHANNEL_18 (3)
3130 * @arg @ref ADC_CHANNEL_19 (3)
3131 * @arg @ref ADC_CHANNEL_20 (3)
3132 * @arg @ref ADC_CHANNEL_21 (3)
3133 * @arg @ref ADC_CHANNEL_22 (3)
3134 * @arg @ref ADC_CHANNEL_VREFINT (2)
3135 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
3136 * @arg @ref ADC_CHANNEL_VDDA (2)
3137 * @arg @ref ADC_CHANNEL_VSSA (2)
3138 *
3139 * (1) On STM32C0, parameter can be set in ADC group sequencer
3140 * only if sequencer is set in mode "not fully configurable",
3141 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
3142 * (2) For ADC channel read back from ADC register,
3143 * comparison with internal channel parameter to be done
3144 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3145 * (3) ADC channels available on STM32C031xx device only.
3146 * @retval None
3147 */
LL_ADC_REG_SetSequencerChRem(ADC_TypeDef * ADCx,uint32_t Channel)3148 __STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel)
3149 {
3150 /* Parameter "Channel" is used with masks because containing */
3151 /* other bits reserved for other purpose. */
3152 CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
3153 }
3154
3155 /**
3156 * @brief Get ADC group regular sequence: channel on rank corresponding to
3157 * channel number.
3158 * @note This function performs:
3159 * - Channels order reading into each rank of scan sequence:
3160 * rank of each channel is fixed by channel HW number
3161 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3162 * @note On this STM32 series, ADC group regular sequencer both modes
3163 * "fully configurable" or "not fully configurable"
3164 * are available, they can be chosen using
3165 * function @ref LL_ADC_REG_SetSequencerConfigurable().
3166 * This function can be used with setting "not fully configurable".
3167 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
3168 * and @ref LL_ADC_REG_SetSequencerLength().
3169 * @note Depending on devices and packages, some channels may not be available.
3170 * Refer to device datasheet for channels availability.
3171 * @note On this STM32 series, to measure internal channels (VrefInt,
3172 * TempSensor, ...), measurement paths to internal channels must be
3173 * enabled separately.
3174 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3175 * @note On this STM32 series, setting of this feature is conditioned to
3176 * ADC state:
3177 * ADC must be disabled or enabled without conversion on going
3178 * on group regular.
3179 * @note One or several values can be retrieved.
3180 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
3181 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_GetSequencerChannels\n
3182 * CHSELR CHSEL1 LL_ADC_REG_GetSequencerChannels\n
3183 * CHSELR CHSEL2 LL_ADC_REG_GetSequencerChannels\n
3184 * CHSELR CHSEL3 LL_ADC_REG_GetSequencerChannels\n
3185 * CHSELR CHSEL4 LL_ADC_REG_GetSequencerChannels\n
3186 * CHSELR CHSEL5 LL_ADC_REG_GetSequencerChannels\n
3187 * CHSELR CHSEL6 LL_ADC_REG_GetSequencerChannels\n
3188 * CHSELR CHSEL7 LL_ADC_REG_GetSequencerChannels\n
3189 * CHSELR CHSEL8 LL_ADC_REG_GetSequencerChannels\n
3190 * CHSELR CHSEL9 LL_ADC_REG_GetSequencerChannels\n
3191 * CHSELR CHSEL10 LL_ADC_REG_GetSequencerChannels\n
3192 * CHSELR CHSEL11 LL_ADC_REG_GetSequencerChannels\n
3193 * CHSELR CHSEL12 LL_ADC_REG_GetSequencerChannels\n
3194 * CHSELR CHSEL13 LL_ADC_REG_GetSequencerChannels\n
3195 * CHSELR CHSEL14 LL_ADC_REG_GetSequencerChannels\n
3196 * CHSELR CHSEL15 LL_ADC_REG_GetSequencerChannels\n
3197 * CHSELR CHSEL16 LL_ADC_REG_GetSequencerChannels\n
3198 * CHSELR CHSEL17 LL_ADC_REG_GetSequencerChannels\n
3199 * CHSELR CHSEL18 LL_ADC_REG_GetSequencerChannels
3200 * @param ADCx ADC instance
3201 * @retval Returned value can be a combination of the following values:
3202 * @arg @ref ADC_CHANNEL_0
3203 * @arg @ref ADC_CHANNEL_1
3204 * @arg @ref ADC_CHANNEL_2
3205 * @arg @ref ADC_CHANNEL_3
3206 * @arg @ref ADC_CHANNEL_4
3207 * @arg @ref ADC_CHANNEL_5
3208 * @arg @ref ADC_CHANNEL_6
3209 * @arg @ref ADC_CHANNEL_7
3210 * @arg @ref ADC_CHANNEL_8 (1)
3211 * @arg @ref ADC_CHANNEL_9 (1)
3212 * @arg @ref ADC_CHANNEL_10
3213 * @arg @ref ADC_CHANNEL_11
3214 * @arg @ref ADC_CHANNEL_12
3215 * @arg @ref ADC_CHANNEL_13
3216 * @arg @ref ADC_CHANNEL_14
3217 * @arg @ref ADC_CHANNEL_15 (1)
3218 * @arg @ref ADC_CHANNEL_16 (1)
3219 * @arg @ref ADC_CHANNEL_17 (3)
3220 * @arg @ref ADC_CHANNEL_18 (3)
3221 * @arg @ref ADC_CHANNEL_19 (3)
3222 * @arg @ref ADC_CHANNEL_20 (3)
3223 * @arg @ref ADC_CHANNEL_21 (3)
3224 * @arg @ref ADC_CHANNEL_22 (3)
3225 * @arg @ref ADC_CHANNEL_VREFINT (2)
3226 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
3227 * @arg @ref ADC_CHANNEL_VDDA (2)
3228 * @arg @ref ADC_CHANNEL_VSSA (2)
3229 *
3230 * (1) On STM32C0, parameter can be set in ADC group sequencer
3231 * only if sequencer is set in mode "not fully configurable",
3232 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
3233 * (2) For ADC channel read back from ADC register,
3234 * comparison with internal channel parameter to be done
3235 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3236 * (3) ADC channels available on STM32C031xx device only.
3237 */
LL_ADC_REG_GetSequencerChannels(ADC_TypeDef * ADCx)3238 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx)
3239 {
3240 uint32_t ChannelsBitfield = (uint32_t)READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL);
3241
3242 return ((((ChannelsBitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0)
3243 | (((ChannelsBitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1)
3244 | (((ChannelsBitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2)
3245 | (((ChannelsBitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3)
3246 | (((ChannelsBitfield & ADC_CHSELR_CHSEL4) >> ADC_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4)
3247 | (((ChannelsBitfield & ADC_CHSELR_CHSEL5) >> ADC_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5)
3248 | (((ChannelsBitfield & ADC_CHSELR_CHSEL6) >> ADC_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6)
3249 | (((ChannelsBitfield & ADC_CHSELR_CHSEL7) >> ADC_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7)
3250 | (((ChannelsBitfield & ADC_CHSELR_CHSEL8) >> ADC_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_CHANNEL_8)
3251 | (((ChannelsBitfield & ADC_CHSELR_CHSEL9) >> ADC_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_CHANNEL_9)
3252 | (((ChannelsBitfield & ADC_CHSELR_CHSEL10) >> ADC_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10)
3253 | (((ChannelsBitfield & ADC_CHSELR_CHSEL11) >> ADC_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11)
3254 | (((ChannelsBitfield & ADC_CHSELR_CHSEL12) >> ADC_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12)
3255 | (((ChannelsBitfield & ADC_CHSELR_CHSEL13) >> ADC_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13)
3256 | (((ChannelsBitfield & ADC_CHSELR_CHSEL14) >> ADC_CHSELR_CHSEL14_BITOFFSET_POS) * LL_ADC_CHANNEL_14)
3257 | (((ChannelsBitfield & ADC_CHSELR_CHSEL15) >> ADC_CHSELR_CHSEL15_BITOFFSET_POS) * LL_ADC_CHANNEL_15)
3258 | (((ChannelsBitfield & ADC_CHSELR_CHSEL16) >> ADC_CHSELR_CHSEL16_BITOFFSET_POS) * LL_ADC_CHANNEL_16)
3259 | (((ChannelsBitfield & ADC_CHSELR_CHSEL17) >> ADC_CHSELR_CHSEL17_BITOFFSET_POS) * LL_ADC_CHANNEL_17)
3260 | (((ChannelsBitfield & ADC_CHSELR_CHSEL18) >> ADC_CHSELR_CHSEL18_BITOFFSET_POS) * LL_ADC_CHANNEL_18)
3261 | (((ChannelsBitfield & ADC_CHSELR_CHSEL19) >> ADC_CHSELR_CHSEL19_BITOFFSET_POS) * LL_ADC_CHANNEL_19)
3262 | (((ChannelsBitfield & ADC_CHSELR_CHSEL20) >> ADC_CHSELR_CHSEL20_BITOFFSET_POS) * LL_ADC_CHANNEL_20)
3263 | (((ChannelsBitfield & ADC_CHSELR_CHSEL21) >> ADC_CHSELR_CHSEL21_BITOFFSET_POS) * LL_ADC_CHANNEL_21)
3264 | (((ChannelsBitfield & ADC_CHSELR_CHSEL22) >> ADC_CHSELR_CHSEL22_BITOFFSET_POS) * LL_ADC_CHANNEL_22)
3265 );
3266 }
3267
3268 /**
3269 * @brief Set ADC continuous conversion mode on ADC group regular.
3270 * @note Description of ADC continuous conversion mode:
3271 * - single mode: one conversion per trigger
3272 * - continuous mode: after the first trigger, following
3273 * conversions launched successively automatically.
3274 * @note It is not possible to enable both ADC group regular
3275 * continuous mode and sequencer discontinuous mode.
3276 * @note On this STM32 series, setting of this feature is conditioned to
3277 * ADC state:
3278 * ADC must be disabled.
3279 * @rmtoll CFGR1 CONT LL_ADC_REG_SetContinuousMode
3280 * @param ADCx ADC instance
3281 * @param Continuous This parameter can be one of the following values:
3282 * @arg @ref LL_ADC_REG_CONV_SINGLE
3283 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
3284 * @retval None
3285 */
LL_ADC_REG_SetContinuousMode(ADC_TypeDef * ADCx,uint32_t Continuous)3286 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
3287 {
3288 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous);
3289 }
3290
3291 /**
3292 * @brief Get ADC continuous conversion mode on ADC group regular.
3293 * @note Description of ADC continuous conversion mode:
3294 * - single mode: one conversion per trigger
3295 * - continuous mode: after the first trigger, following
3296 * conversions launched successively automatically.
3297 * @rmtoll CFGR1 CONT LL_ADC_REG_GetContinuousMode
3298 * @param ADCx ADC instance
3299 * @retval Returned value can be one of the following values:
3300 * @arg @ref LL_ADC_REG_CONV_SINGLE
3301 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
3302 */
LL_ADC_REG_GetContinuousMode(ADC_TypeDef * ADCx)3303 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
3304 {
3305 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT));
3306 }
3307
3308 /**
3309 * @brief Set ADC group regular conversion data transfer: no transfer or
3310 * transfer by DMA, and DMA requests mode.
3311 * @note If transfer by DMA selected, specifies the DMA requests
3312 * mode:
3313 * - Limited mode (One shot mode): DMA transfer requests are stopped
3314 * when number of DMA data transfers (number of
3315 * ADC conversions) is reached.
3316 * This ADC mode is intended to be used with DMA mode non-circular.
3317 * - Unlimited mode: DMA transfer requests are unlimited,
3318 * whatever number of DMA data transfers (number of
3319 * ADC conversions).
3320 * This ADC mode is intended to be used with DMA mode circular.
3321 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3322 * mode non-circular:
3323 * when DMA transfers size will be reached, DMA will stop transfers of
3324 * ADC conversions data ADC will raise an overrun error
3325 * (overrun flag and interruption if enabled).
3326 * @note To configure DMA source address (peripheral address),
3327 * use function @ref LL_ADC_DMA_GetRegAddr().
3328 * @note On this STM32 series, setting of this feature is conditioned to
3329 * ADC state:
3330 * ADC must be disabled.
3331 * @rmtoll CFGR1 DMAEN LL_ADC_REG_SetDMATransfer\n
3332 * CFGR1 DMACFG LL_ADC_REG_SetDMATransfer
3333 * @param ADCx ADC instance
3334 * @param DMATransfer This parameter can be one of the following values:
3335 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
3336 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
3337 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
3338 * @retval None
3339 */
LL_ADC_REG_SetDMATransfer(ADC_TypeDef * ADCx,uint32_t DMATransfer)3340 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
3341 {
3342 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG, DMATransfer);
3343 }
3344
3345 /**
3346 * @brief Get ADC group regular conversion data transfer: no transfer or
3347 * transfer by DMA, and DMA requests mode.
3348 * @note If transfer by DMA selected, specifies the DMA requests
3349 * mode:
3350 * - Limited mode (One shot mode): DMA transfer requests are stopped
3351 * when number of DMA data transfers (number of
3352 * ADC conversions) is reached.
3353 * This ADC mode is intended to be used with DMA mode non-circular.
3354 * - Unlimited mode: DMA transfer requests are unlimited,
3355 * whatever number of DMA data transfers (number of
3356 * ADC conversions).
3357 * This ADC mode is intended to be used with DMA mode circular.
3358 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3359 * mode non-circular:
3360 * when DMA transfers size will be reached, DMA will stop transfers of
3361 * ADC conversions data ADC will raise an overrun error
3362 * (overrun flag and interruption if enabled).
3363 * @note To configure DMA source address (peripheral address),
3364 * use function @ref LL_ADC_DMA_GetRegAddr().
3365 * @rmtoll CFGR1 DMAEN LL_ADC_REG_GetDMATransfer\n
3366 * CFGR1 DMACFG LL_ADC_REG_GetDMATransfer
3367 * @param ADCx ADC instance
3368 * @retval Returned value can be one of the following values:
3369 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
3370 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
3371 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
3372 */
LL_ADC_REG_GetDMATransfer(ADC_TypeDef * ADCx)3373 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
3374 {
3375 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG));
3376 }
3377
3378 /**
3379 * @brief Set ADC group regular behavior in case of overrun:
3380 * data preserved or overwritten.
3381 * @note Compatibility with devices without feature overrun:
3382 * other devices without this feature have a behavior
3383 * equivalent to data overwritten.
3384 * The default setting of overrun is data preserved.
3385 * Therefore, for compatibility with all devices, parameter
3386 * overrun should be set to data overwritten.
3387 * @note On this STM32 series, setting of this feature is conditioned to
3388 * ADC state:
3389 * ADC must be disabled.
3390 * @rmtoll CFGR1 OVRMOD LL_ADC_REG_SetOverrun
3391 * @param ADCx ADC instance
3392 * @param Overrun This parameter can be one of the following values:
3393 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
3394 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
3395 * @retval None
3396 */
LL_ADC_REG_SetOverrun(ADC_TypeDef * ADCx,uint32_t Overrun)3397 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
3398 {
3399 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun);
3400 }
3401
3402 /**
3403 * @brief Get ADC group regular behavior in case of overrun:
3404 * data preserved or overwritten.
3405 * @rmtoll CFGR1 OVRMOD LL_ADC_REG_GetOverrun
3406 * @param ADCx ADC instance
3407 * @retval Returned value can be one of the following values:
3408 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
3409 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
3410 */
LL_ADC_REG_GetOverrun(ADC_TypeDef * ADCx)3411 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
3412 {
3413 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD));
3414 }
3415
3416 /**
3417 * @}
3418 */
3419
3420 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
3421 * @{
3422 */
3423
3424 /**
3425 * @brief Set sampling time of the selected ADC channel
3426 * Unit: ADC clock cycles.
3427 * @note On this device, sampling time is on channel scope: independently
3428 * of channel mapped on ADC group regular or injected.
3429 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
3430 * converted:
3431 * sampling time constraints must be respected (sampling time can be
3432 * adjusted in function of ADC clock frequency and sampling time
3433 * setting).
3434 * Refer to device datasheet for timings values (parameters TS_vrefint,
3435 * TS_temp, ...).
3436 * @note Conversion time is the addition of sampling time and processing time.
3437 * Refer to reference manual for ADC processing time of
3438 * this STM32 series.
3439 * @note In case of ADC conversion of internal channel (VrefInt,
3440 * temperature sensor, ...), a sampling time minimum value
3441 * is required.
3442 * Refer to device datasheet.
3443 * @note On this STM32 series, setting of this feature is conditioned to
3444 * ADC state:
3445 * ADC must be disabled or enabled without conversion on going
3446 * on group regular.
3447 * @rmtoll SMPR SMPSEL0 LL_ADC_SetChannelSamplingTime\n
3448 * SMPR SMPSEL1 LL_ADC_SetChannelSamplingTime\n
3449 * SMPR SMPSEL2 LL_ADC_SetChannelSamplingTime\n
3450 * SMPR SMPSEL3 LL_ADC_SetChannelSamplingTime\n
3451 * SMPR SMPSEL4 LL_ADC_SetChannelSamplingTime\n
3452 * SMPR SMPSEL5 LL_ADC_SetChannelSamplingTime\n
3453 * SMPR SMPSEL6 LL_ADC_SetChannelSamplingTime\n
3454 * SMPR SMPSEL7 LL_ADC_SetChannelSamplingTime\n
3455 * SMPR SMPSEL8 LL_ADC_SetChannelSamplingTime\n
3456 * SMPR SMPSEL9 LL_ADC_SetChannelSamplingTime\n
3457 * SMPR SMPSEL10 LL_ADC_SetChannelSamplingTime\n
3458 * SMPR SMPSEL11 LL_ADC_SetChannelSamplingTime\n
3459 * SMPR SMPSEL12 LL_ADC_SetChannelSamplingTime\n
3460 * SMPR SMPSEL13 LL_ADC_SetChannelSamplingTime\n
3461 * SMPR SMPSEL14 LL_ADC_SetChannelSamplingTime\n
3462 * SMPR SMPSEL15 LL_ADC_SetChannelSamplingTime\n
3463 * SMPR SMPSEL16 LL_ADC_SetChannelSamplingTime\n
3464 * SMPR SMPSEL17 LL_ADC_SetChannelSamplingTime\n
3465 * SMPR SMPSEL18 LL_ADC_SetChannelSamplingTime
3466 * @param ADCx ADC instance
3467 * @param Channel This parameter can be a combination of the following values:
3468 * @arg @ref ADC_CHANNEL_0
3469 * @arg @ref ADC_CHANNEL_1
3470 * @arg @ref ADC_CHANNEL_2
3471 * @arg @ref ADC_CHANNEL_3
3472 * @arg @ref ADC_CHANNEL_4
3473 * @arg @ref ADC_CHANNEL_5
3474 * @arg @ref ADC_CHANNEL_6
3475 * @arg @ref ADC_CHANNEL_7
3476 * @arg @ref ADC_CHANNEL_8 (1)
3477 * @arg @ref ADC_CHANNEL_9 (1)
3478 * @arg @ref ADC_CHANNEL_10
3479 * @arg @ref ADC_CHANNEL_11
3480 * @arg @ref ADC_CHANNEL_12
3481 * @arg @ref ADC_CHANNEL_13
3482 * @arg @ref ADC_CHANNEL_14
3483 * @arg @ref ADC_CHANNEL_15 (1)
3484 * @arg @ref ADC_CHANNEL_16 (1)
3485 * @arg @ref ADC_CHANNEL_17 (3)
3486 * @arg @ref ADC_CHANNEL_18 (3)
3487 * @arg @ref ADC_CHANNEL_19 (3)
3488 * @arg @ref ADC_CHANNEL_20 (3)
3489 * @arg @ref ADC_CHANNEL_21 (3)
3490 * @arg @ref ADC_CHANNEL_22 (3)
3491 * @arg @ref ADC_CHANNEL_VREFINT (2)
3492 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
3493 * @arg @ref ADC_CHANNEL_VDDA (2)
3494 * @arg @ref ADC_CHANNEL_VSSA (2)
3495 *
3496 * (1) On STM32C0, parameter can be set in ADC group sequencer
3497 * only if sequencer is set in mode "not fully configurable",
3498 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
3499 * (2) For ADC channel read back from ADC register,
3500 * comparison with internal channel parameter to be done
3501 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3502 * (3) ADC channels available on STM32C031xx device only.
3503 * @param SamplingTimeY This parameter can be one of the following values:
3504 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
3505 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
3506 * @retval None
3507 */
LL_ADC_SetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SamplingTimeY)3508 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTimeY)
3509 {
3510 /* Parameter "Channel" is used with masks because containing */
3511 /* other bits reserved for other purpose. */
3512 MODIFY_REG(ADCx->SMPR,
3513 (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS),
3514 (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS) & (SamplingTimeY & ADC_SAMPLING_TIME_CH_MASK)
3515 );
3516 }
3517
3518 /**
3519 * @brief Get sampling time of the selected ADC channel
3520 * Unit: ADC clock cycles.
3521 * @note On this device, sampling time is on channel scope: independently
3522 * of channel mapped on ADC group regular or injected.
3523 * @note Conversion time is the addition of sampling time and processing time.
3524 * Refer to reference manual for ADC processing time of
3525 * this STM32 series.
3526 * @rmtoll SMPR SMPSEL0 LL_ADC_GetChannelSamplingTime\n
3527 * SMPR SMPSEL1 LL_ADC_GetChannelSamplingTime\n
3528 * SMPR SMPSEL2 LL_ADC_GetChannelSamplingTime\n
3529 * SMPR SMPSEL3 LL_ADC_GetChannelSamplingTime\n
3530 * SMPR SMPSEL4 LL_ADC_GetChannelSamplingTime\n
3531 * SMPR SMPSEL5 LL_ADC_GetChannelSamplingTime\n
3532 * SMPR SMPSEL6 LL_ADC_GetChannelSamplingTime\n
3533 * SMPR SMPSEL7 LL_ADC_GetChannelSamplingTime\n
3534 * SMPR SMPSEL8 LL_ADC_GetChannelSamplingTime\n
3535 * SMPR SMPSEL9 LL_ADC_GetChannelSamplingTime\n
3536 * SMPR SMPSEL10 LL_ADC_GetChannelSamplingTime\n
3537 * SMPR SMPSEL11 LL_ADC_GetChannelSamplingTime\n
3538 * SMPR SMPSEL12 LL_ADC_GetChannelSamplingTime\n
3539 * SMPR SMPSEL13 LL_ADC_GetChannelSamplingTime\n
3540 * SMPR SMPSEL14 LL_ADC_GetChannelSamplingTime\n
3541 * SMPR SMPSEL15 LL_ADC_GetChannelSamplingTime\n
3542 * SMPR SMPSEL16 LL_ADC_GetChannelSamplingTime\n
3543 * SMPR SMPSEL17 LL_ADC_GetChannelSamplingTime\n
3544 * SMPR SMPSEL18 LL_ADC_GetChannelSamplingTime
3545 * @param ADCx ADC instance
3546 * @param Channel This parameter can be one of the following values:
3547 * @arg @ref ADC_CHANNEL_0
3548 * @arg @ref ADC_CHANNEL_1
3549 * @arg @ref ADC_CHANNEL_2
3550 * @arg @ref ADC_CHANNEL_3
3551 * @arg @ref ADC_CHANNEL_4
3552 * @arg @ref ADC_CHANNEL_5
3553 * @arg @ref ADC_CHANNEL_6
3554 * @arg @ref ADC_CHANNEL_7
3555 * @arg @ref ADC_CHANNEL_8 (1)
3556 * @arg @ref ADC_CHANNEL_9 (1)
3557 * @arg @ref ADC_CHANNEL_10
3558 * @arg @ref ADC_CHANNEL_11
3559 * @arg @ref ADC_CHANNEL_12
3560 * @arg @ref ADC_CHANNEL_13
3561 * @arg @ref ADC_CHANNEL_14
3562 * @arg @ref ADC_CHANNEL_15 (1)
3563 * @arg @ref ADC_CHANNEL_16 (1)
3564 * @arg @ref ADC_CHANNEL_17 (3)
3565 * @arg @ref ADC_CHANNEL_18 (3)
3566 * @arg @ref ADC_CHANNEL_19 (3)
3567 * @arg @ref ADC_CHANNEL_20 (3)
3568 * @arg @ref ADC_CHANNEL_21 (3)
3569 * @arg @ref ADC_CHANNEL_22 (3)
3570 * @arg @ref ADC_CHANNEL_VREFINT (2)
3571 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
3572 * @arg @ref ADC_CHANNEL_VDDA (2)
3573 * @arg @ref ADC_CHANNEL_VSSA (2)
3574 *
3575 * (1) On STM32C0, parameter can be set in ADC group sequencer
3576 * only if sequencer is set in mode "not fully configurable",
3577 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
3578 * (2) For ADC channel read back from ADC register,
3579 * comparison with internal channel parameter to be done
3580 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3581 * (3) ADC channels available on STM32C031xx device only.
3582 * @retval Returned value can be one of the following values:
3583 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
3584 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
3585 */
LL_ADC_GetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel)3586 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
3587 {
3588 __IO uint32_t smpr = READ_REG(ADCx->SMPR);
3589
3590 /* Retrieve sampling time bit corresponding to the selected channel */
3591 /* and shift it to position 0. */
3592 uint32_t smp_channel_posbit0 = ((smpr & ADC_SAMPLING_TIME_CH_MASK)
3593 >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + ADC_SMPR_SMPSEL0_BITOFFSET_POS) &
3594 0x1FUL));
3595
3596 /* Select sampling time bitfield depending on sampling time bit value 0 or 1. */
3597 return ((~(smp_channel_posbit0) * LL_ADC_SAMPLINGTIME_COMMON_1)
3598 | (smp_channel_posbit0 * LL_ADC_SAMPLINGTIME_COMMON_2));
3599 }
3600
3601 /**
3602 * @}
3603 */
3604
3605 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
3606 * @{
3607 */
3608
3609 /**
3610 * @brief Set ADC analog watchdog monitored channels:
3611 * a single channel or all channels,
3612 * on ADC group regular.
3613 * @note Once monitored channels are selected, analog watchdog
3614 * is enabled.
3615 * @note In case of need to define a single channel to monitor
3616 * with analog watchdog from sequencer channel definition,
3617 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
3618 * @note On this STM32 series, there is only 1 kind of analog watchdog
3619 * instance:
3620 * - AWD standard (instance AWD1):
3621 * - channels monitored: can monitor 1 channel or all channels.
3622 * - groups monitored: ADC group regular.
3623 * - resolution: resolution is not limited (corresponds to
3624 * ADC resolution configured).
3625 * @note On this STM32 series, setting of this feature is conditioned to
3626 * ADC state:
3627 * ADC must be disabled.
3628 * @rmtoll CFGR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
3629 * CFGR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
3630 * CFGR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
3631 * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
3632 * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
3633 * @param ADCx ADC instance
3634 * @param AWDy This parameter can be one of the following values:
3635 * @arg @ref LL_ADC_AWD1
3636 * @arg @ref LL_ADC_AWD2
3637 * @arg @ref LL_ADC_AWD3
3638 * @param AWDChannelGroup This parameter can be one of the following values:
3639 * @arg @ref LL_ADC_AWD_DISABLE
3640 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
3641 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
3642 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
3643 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
3644 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
3645 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
3646 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
3647 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
3648 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
3649 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
3650 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
3651 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
3652 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
3653 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
3654 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
3655 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
3656 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
3657 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
3658 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
3659 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (1)
3660 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (1)
3661 * @arg @ref LL_ADC_AWD_CHANNEL_20_REG (1)
3662 * @arg @ref LL_ADC_AWD_CHANNEL_21_REG (1)
3663 * @arg @ref LL_ADC_AWD_CHANNEL_22_REG (1)
3664 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG
3665 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
3666 * @arg @ref LL_ADC_AWD_CH_VDDA_REG
3667 * @arg @ref LL_ADC_AWD_CH_VSSA_REG
3668 * (1) On STM32C0, parameter not available on all devices: only on STM32C031xx.
3669 * @retval None
3670 */
LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDChannelGroup)3671 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
3672 {
3673 /* Set bits with content of parameter "AWDChannelGroup" with bits position */
3674 /* in register and register position depending on parameter "AWDy". */
3675 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
3676 /* containing other bits reserved for other purpose. */
3677 register __IO uint32_t *preg;
3678
3679 if (AWDy == LL_ADC_AWD1)
3680 {
3681 preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, 0UL);
3682 }
3683 else
3684 {
3685 preg = __ADC_PTR_REG_OFFSET(ADCx->AWD2CR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK)) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL));
3686 }
3687
3688 MODIFY_REG(*preg,
3689 (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
3690 AWDChannelGroup & AWDy);
3691 }
3692
3693 /**
3694 * @brief Get ADC analog watchdog monitored channel.
3695 * @note Usage of the returned channel number:
3696 * - To reinject this channel into another function LL_ADC_xxx:
3697 * the returned channel number is only partly formatted on definition
3698 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3699 * with parts of literals LL_ADC_CHANNEL_x or using
3700 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3701 * Then the selected literal LL_ADC_CHANNEL_x can be used
3702 * as parameter for another function.
3703 * - To get the channel number in decimal format:
3704 * process the returned value with the helper macro
3705 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3706 * Applicable only when the analog watchdog is set to monitor
3707 * one channel.
3708 * @note On this STM32 series, there is only 1 kind of analog watchdog
3709 * instance:
3710 * - AWD standard (instance AWD1):
3711 * - channels monitored: can monitor 1 channel or all channels.
3712 * - groups monitored: ADC group regular.
3713 * - resolution: resolution is not limited (corresponds to
3714 * ADC resolution configured).
3715 * - AWD flexible (instances AWD2, AWD3):
3716 * - channels monitored: flexible on channels monitored, selection is
3717 * channel wise, from from 1 to all channels.
3718 * Specificity of this analog watchdog: Multiple channels can
3719 * be selected. For example:
3720 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
3721 * - groups monitored: not selection possible (monitoring on both
3722 * groups regular and injected).
3723 * Channels selected are monitored on groups regular and injected:
3724 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
3725 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
3726 * - resolution: resolution is not limited (corresponds to
3727 * ADC resolution configured).
3728 * @note On this STM32 series, setting of this feature is conditioned to
3729 * ADC state:
3730 * ADC must be disabled or enabled without conversion on going
3731 * on group regular.
3732 * @rmtoll CFGR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
3733 * CFGR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
3734 * CFGR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
3735 * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
3736 * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
3737 * @param ADCx ADC instance
3738 * @param AWDy This parameter can be one of the following values:
3739 * @arg @ref LL_ADC_AWD1
3740 * @arg @ref LL_ADC_AWD2 (1)
3741 * @arg @ref LL_ADC_AWD3 (1)
3742 *
3743 * (1) On this AWD number, monitored channel can be retrieved
3744 * if only 1 channel is programmed (or none or all channels).
3745 * This function cannot retrieve monitored channel if
3746 * multiple channels are programmed simultaneously
3747 * by bitfield.
3748 * @retval Returned value can be one of the following values:
3749 * @arg @ref LL_ADC_AWD_DISABLE
3750 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
3751 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
3752 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
3753 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
3754 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
3755 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
3756 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
3757 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
3758 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
3759 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
3760 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
3761 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
3762 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
3763 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
3764 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
3765 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
3766 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
3767 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
3768 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
3769 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (1)
3770 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (1)
3771 * @arg @ref LL_ADC_AWD_CHANNEL_20_REG (1)
3772 * @arg @ref LL_ADC_AWD_CHANNEL_21_REG (1)
3773 * @arg @ref LL_ADC_AWD_CHANNEL_22_REG (1)
3774 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG
3775 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
3776 * @arg @ref LL_ADC_AWD_CH_VDDA_REG
3777 * @arg @ref LL_ADC_AWD_CH_VSSA_REG
3778 * (1) On STM32C0, parameter not available on all devices: only on STM32C031xx.
LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDy)3779 */__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
3780 {
3781 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
3782 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
3783
3784 register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
3785
3786 /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */
3787 /* (parameter value LL_ADC_AWD_DISABLE). */
3788 /* Else, the selected AWD is enabled and is monitoring a group of channels */
3789 /* or a single channel. */
3790 if (AnalogWDMonitChannels != 0UL)
3791 {
3792 if (AWDy == LL_ADC_AWD1)
3793 {
3794 if ((AnalogWDMonitChannels & ADC_CFGR1_AWD1SGL) == 0UL)
3795 {
3796 /* AWD monitoring a group of channels */
3797 AnalogWDMonitChannels = ((AnalogWDMonitChannels
3798 | (ADC_AWD_CR23_CHANNEL_MASK)
3799 )
3800 & (~(ADC_CFGR1_AWD1CH))
3801 );
3802 }
3803 else
3804 {
3805 /* AWD monitoring a single channel */
3806 AnalogWDMonitChannels = (AnalogWDMonitChannels
3807 | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR1_AWD1CH_Pos))
3808 );
3809 }
3810 }
3811 else
3812 {
3813 if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
3814 {
3815 /* AWD monitoring a group of channels */
3816 AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK
3817 | (ADC_CFGR1_AWD1EN)
3818 );
3819 }
3820 else
3821 {
3822 /* AWD monitoring a single channel */
3823 /* AWD monitoring a group of channels */
3824 AnalogWDMonitChannels = (AnalogWDMonitChannels
3825 | (ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
3826 | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR1_AWD1CH_Pos)
3827 );
3828 }
3829 }
3830 }
3831
3832 return AnalogWDMonitChannels;
3833 }
3834 /**
3835 * @brief Set ADC analog watchdog thresholds value of both thresholds
3836 * high and low.
3837 * @note If value of only one threshold high or low must be set,
3838 * use function @ref LL_ADC_SetAnalogWDThresholds().
3839 * @note In case of ADC resolution different of 12 bits,
3840 * analog watchdog thresholds data require a specific shift.
3841 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
3842 * @note On this STM32 series, there is only 2 kind of analog watchdog
3843 * instance:
3844 * - AWD standard (instance AWD1):
3845 * - channels monitored: can monitor 1 channel or all channels.
3846 * - groups monitored: ADC group regular.
3847 * - resolution: resolution is not limited (corresponds to
3848 * ADC resolution configured).
3849 * - AWD flexible (instances AWD2, AWD3):
3850 * - channels monitored: flexible on channels monitored, selection is
3851 * channel wise, from from 1 to all channels.
3852 * Specificity of this analog watchdog: Multiple channels can
3853 * be selected. For example:
3854 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
3855 * - groups monitored: not selection possible (monitoring on both
3856 * groups regular and injected).
3857 * Channels selected are monitored on groups regular and injected:
3858 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
3859 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
3860 * - resolution: resolution is not limited (corresponds to
3861 * ADC resolution configured).
3862 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
3863 * impacted: the comparison of analog watchdog thresholds is done on
3864 * oversampling final computation (after ratio and shift application):
3865 * ADC data register bitfield [15:4] (12 most significant bits).
3866 * Examples:
3867 * - Oversampling ratio and shift selected to have ADC conversion data
3868 * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
3869 * ADC analog watchdog thresholds must be divided by 16.
3870 * - Oversampling ratio and shift selected to have ADC conversion data
3871 * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
3872 * ADC analog watchdog thresholds must be divided by 4.
3873 * - Oversampling ratio and shift selected to have ADC conversion data
3874 * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
3875 * ADC analog watchdog thresholds match directly to ADC data register.
3876 * @note On this STM32 series, setting of this feature is conditioned to
3877 * ADC state:
3878 * ADC must be disabled or enabled without conversion on going
3879 * on group regular.
3880 * @rmtoll AWD1TR HT1 LL_ADC_ConfigAnalogWDThresholds\n
3881 * AWD2TR HT2 LL_ADC_ConfigAnalogWDThresholds\n
3882 * AWD3TR HT3 LL_ADC_ConfigAnalogWDThresholds\n
3883 * AWD1TR LT1 LL_ADC_ConfigAnalogWDThresholds\n
3884 * AWD2TR LT2 LL_ADC_ConfigAnalogWDThresholds\n
3885 * AWD3TR LT3 LL_ADC_ConfigAnalogWDThresholds
3886 * @param ADCx ADC instance
3887 * @param AWDy This parameter can be one of the following values:
3888 * @arg @ref LL_ADC_AWD1
3889 * @arg @ref LL_ADC_AWD2
3890 * @arg @ref LL_ADC_AWD3
3891 * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
3892 * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
3893 * @retval None
3894 */
LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdHighValue,uint32_t AWDThresholdLowValue)3895 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
3896 uint32_t AWDThresholdLowValue)
3897 {
3898 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
3899 /* position in register and register position depending on parameter */
3900 /* "AWDy". */
3901 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
3902 /* containing other bits reserved for other purpose. */
3903 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)));
3904
3905 MODIFY_REG(*preg,
3906 ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1,
3907 (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
3908 }
3909 /**
3910 * @brief Set ADC analog watchdog threshold value of threshold
3911 * high or low.
3912 * @note If values of both thresholds high or low must be set,
3913 * use function @ref LL_ADC_ConfigAnalogWDThresholds().
3914 * @note In case of ADC resolution different of 12 bits,
3915 * analog watchdog thresholds data require a specific shift.
3916 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
3917 * @note On this STM32 series, there is only 2 kinds of analog watchdog
3918 * instance:
3919 * - AWD standard (instance AWD1):
3920 * - channels monitored: can monitor 1 channel or all channels.
3921 * - groups monitored: ADC group regular.
3922 * - resolution: resolution is not limited (corresponds to
3923 * ADC resolution configured).
3924 * - AWD flexible (instances AWD2, AWD3):
3925 * - channels monitored: flexible on channels monitored, selection is
3926 * channel wise, from from 1 to all channels.
3927 * Specificity of this analog watchdog: Multiple channels can
3928 * be selected. For example:
3929 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
3930 * - groups monitored: not selection possible (monitoring on both
3931 * groups regular and injected).
3932 * Channels selected are monitored on groups regular and injected:
3933 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
3934 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
3935 * - resolution: resolution is not limited (corresponds to
3936 * ADC resolution configured).
3937 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
3938 * impacted: the comparison of analog watchdog thresholds is done on
3939 * oversampling final computation (after ratio and shift application):
3940 * ADC data register bitfield [15:4] (12 most significant bits).
3941 * Examples:
3942 * - Oversampling ratio and shift selected to have ADC conversion data
3943 * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
3944 * ADC analog watchdog thresholds must be divided by 16.
3945 * - Oversampling ratio and shift selected to have ADC conversion data
3946 * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
3947 * ADC analog watchdog thresholds must be divided by 4.
3948 * - Oversampling ratio and shift selected to have ADC conversion data
3949 * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
3950 * ADC analog watchdog thresholds match directly to ADC data register.
3951 * @note On this STM32 series, setting of this feature is not conditioned to
3952 * ADC state:
3953 * ADC can be disabled, enabled with or without conversion on going
3954 * on ADC group regular.
3955 * @rmtoll AWD1TR HT1 LL_ADC_SetAnalogWDThresholds\n
3956 * AWD2TR HT2 LL_ADC_SetAnalogWDThresholds\n
3957 * AWD3TR HT3 LL_ADC_SetAnalogWDThresholds\n
3958 * AWD1TR LT1 LL_ADC_SetAnalogWDThresholds\n
3959 * AWD2TR LT2 LL_ADC_SetAnalogWDThresholds\n
3960 * AWD3TR LT3 LL_ADC_SetAnalogWDThresholds
3961 * @param ADCx ADC instance
3962 * @param AWDy This parameter can be one of the following values:
3963 * @arg @ref LL_ADC_AWD1
3964 * @arg @ref LL_ADC_AWD2
3965 * @arg @ref LL_ADC_AWD3
3966 * @param AWDThresholdsHighLow This parameter can be one of the following values:
3967 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
3968 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
3969 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
3970 * @retval None
3971 */
LL_ADC_SetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow,uint32_t AWDThresholdValue)3972 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
3973 uint32_t AWDThresholdValue)
3974 {
3975 /* Set bits with content of parameter "AWDThresholdValue" with bits */
3976 /* position in register and register position depending on parameters */
3977 /* "AWDThresholdsHighLow" and "AWDy". */
3978 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
3979 /* containing other bits reserved for other purpose. */
3980 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)));
3981
3982 MODIFY_REG(*preg,
3983 AWDThresholdsHighLow,
3984 AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
3985 }
3986
3987 /**
3988 * @brief Get ADC analog watchdog threshold value of threshold high,
3989 * threshold low or raw data with ADC thresholds high and low
3990 * concatenated.
3991 * @note If raw data with ADC thresholds high and low is retrieved,
3992 * the data of each threshold high or low can be isolated
3993 * using helper macro:
3994 * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
3995 * @note In case of ADC resolution different of 12 bits,
3996 * analog watchdog thresholds data require a specific shift.
3997 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
3998 * @rmtoll AWD1TR HT1 LL_ADC_GetAnalogWDThresholds\n
3999 * AWD2TR HT2 LL_ADC_GetAnalogWDThresholds\n
4000 * AWD3TR HT3 LL_ADC_GetAnalogWDThresholds\n
4001 * AWD1TR LT1 LL_ADC_GetAnalogWDThresholds\n
4002 * AWD2TR LT2 LL_ADC_GetAnalogWDThresholds\n
4003 * AWD3TR LT3 LL_ADC_GetAnalogWDThresholds
4004 * @param ADCx ADC instance
4005 * @param AWDy This parameter can be one of the following values:
4006 * @arg @ref LL_ADC_AWD1
4007 * @arg @ref LL_ADC_AWD2
4008 * @arg @ref LL_ADC_AWD3
4009 * @param AWDThresholdsHighLow This parameter can be one of the following values:
4010 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
4011 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
4012 * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
4013 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
4014 */
LL_ADC_GetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow)4015 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
4016 {
4017 /* Set bits with content of parameter "AWDThresholdValue" with bits */
4018 /* position in register and register position depending on parameters */
4019 /* "AWDThresholdsHighLow" and "AWDy". */
4020 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
4021 /* containing other bits reserved for other purpose. */
4022 register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)));
4023
4024 return (uint32_t)(READ_BIT(*preg,
4025 (AWDThresholdsHighLow | ADC_AWD1TR_LT1))
4026 >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~
4027 (AWDThresholdsHighLow & ADC_AWD1TR_LT1))
4028 );
4029 }
4030
4031 /**
4032 * @}
4033 */
4034
4035 /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
4036 * @{
4037 */
4038
4039 /**
4040 * @brief Set ADC oversampling scope.
4041 * @note On this STM32 series, setting of this feature is conditioned to
4042 * ADC state:
4043 * ADC must be disabled.
4044 * @rmtoll CFGR2 OVSE LL_ADC_SetOverSamplingScope
4045 * @param ADCx ADC instance
4046 * @param OvsScope This parameter can be one of the following values:
4047 * @arg @ref LL_ADC_OVS_DISABLE
4048 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
4049 * @retval None
4050 */
LL_ADC_SetOverSamplingScope(ADC_TypeDef * ADCx,uint32_t OvsScope)4051 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
4052 {
4053 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_OVSE, OvsScope);
4054 }
4055
4056 /**
4057 * @brief Get ADC oversampling scope.
4058 * @rmtoll CFGR2 OVSE LL_ADC_GetOverSamplingScope
4059 * @param ADCx ADC instance
4060 * @retval Returned value can be one of the following values:
4061 * @arg @ref LL_ADC_OVS_DISABLE
4062 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
4063 */
LL_ADC_GetOverSamplingScope(ADC_TypeDef * ADCx)4064 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
4065 {
4066 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE));
4067 }
4068
4069 /**
4070 * @brief Set ADC oversampling discontinuous mode (triggered mode)
4071 * on the selected ADC group.
4072 * @note Number of oversampled conversions are done either in:
4073 * - continuous mode (all conversions of oversampling ratio
4074 * are done from 1 trigger)
4075 * - discontinuous mode (each conversion of oversampling ratio
4076 * needs a trigger)
4077 * @note On this STM32 series, setting of this feature is conditioned to
4078 * ADC state:
4079 * ADC must be disabled.
4080 * @rmtoll CFGR2 TOVS LL_ADC_SetOverSamplingDiscont
4081 * @param ADCx ADC instance
4082 * @param OverSamplingDiscont This parameter can be one of the following values:
4083 * @arg @ref LL_ADC_OVS_REG_CONT
4084 * @arg @ref LL_ADC_OVS_REG_DISCONT
4085 * @retval None
4086 */
LL_ADC_SetOverSamplingDiscont(ADC_TypeDef * ADCx,uint32_t OverSamplingDiscont)4087 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
4088 {
4089 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TOVS, OverSamplingDiscont);
4090 }
4091
4092 /**
4093 * @brief Get ADC oversampling discontinuous mode (triggered mode)
4094 * on the selected ADC group.
4095 * @note Number of oversampled conversions are done either in:
4096 * - continuous mode (all conversions of oversampling ratio
4097 * are done from 1 trigger)
4098 * - discontinuous mode (each conversion of oversampling ratio
4099 * needs a trigger)
4100 * @rmtoll CFGR2 TOVS LL_ADC_GetOverSamplingDiscont
4101 * @param ADCx ADC instance
4102 * @retval Returned value can be one of the following values:
4103 * @arg @ref LL_ADC_OVS_REG_CONT
4104 * @arg @ref LL_ADC_OVS_REG_DISCONT
4105 */
LL_ADC_GetOverSamplingDiscont(ADC_TypeDef * ADCx)4106 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
4107 {
4108 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS));
4109 }
4110
4111 /**
4112 * @brief Set ADC oversampling
4113 * @note This function set the 2 items of oversampling configuration:
4114 * - ratio
4115 * - shift
4116 * @note On this STM32 series, setting of this feature is conditioned to
4117 * ADC state:
4118 * ADC must be disabled.
4119 * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n
4120 * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
4121 * @param ADCx ADC instance
4122 * @param Ratio This parameter can be one of the following values:
4123 * @arg @ref LL_ADC_OVS_RATIO_2
4124 * @arg @ref LL_ADC_OVS_RATIO_4
4125 * @arg @ref LL_ADC_OVS_RATIO_8
4126 * @arg @ref LL_ADC_OVS_RATIO_16
4127 * @arg @ref LL_ADC_OVS_RATIO_32
4128 * @arg @ref LL_ADC_OVS_RATIO_64
4129 * @arg @ref LL_ADC_OVS_RATIO_128
4130 * @arg @ref LL_ADC_OVS_RATIO_256
4131 * @param Shift This parameter can be one of the following values:
4132 * @arg @ref LL_ADC_OVS_SHIFT_NONE
4133 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
4134 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
4135 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
4136 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
4137 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
4138 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
4139 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
4140 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
4141 * @retval None
4142 */
LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef * ADCx,uint32_t Ratio,uint32_t Shift)4143 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
4144 {
4145 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
4146 }
4147
4148 /**
4149 * @brief Get ADC oversampling ratio
4150 * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
4151 * @param ADCx ADC instance
4152 * @retval Ratio This parameter can be one of the following values:
4153 * @arg @ref LL_ADC_OVS_RATIO_2
4154 * @arg @ref LL_ADC_OVS_RATIO_4
4155 * @arg @ref LL_ADC_OVS_RATIO_8
4156 * @arg @ref LL_ADC_OVS_RATIO_16
4157 * @arg @ref LL_ADC_OVS_RATIO_32
4158 * @arg @ref LL_ADC_OVS_RATIO_64
4159 * @arg @ref LL_ADC_OVS_RATIO_128
4160 * @arg @ref LL_ADC_OVS_RATIO_256
4161 */
LL_ADC_GetOverSamplingRatio(ADC_TypeDef * ADCx)4162 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
4163 {
4164 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
4165 }
4166
4167 /**
4168 * @brief Get ADC oversampling shift
4169 * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
4170 * @param ADCx ADC instance
4171 * @retval Shift This parameter can be one of the following values:
4172 * @arg @ref LL_ADC_OVS_SHIFT_NONE
4173 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
4174 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
4175 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
4176 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
4177 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
4178 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
4179 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
4180 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
4181 */
LL_ADC_GetOverSamplingShift(ADC_TypeDef * ADCx)4182 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
4183 {
4184 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
4185 }
4186
4187 /**
4188 * @}
4189 */
4190
4191 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
4192 * @{
4193 */
4194
4195 /**
4196 * @brief Enable ADC instance internal voltage regulator.
4197 * @note On this STM32 series, there are three possibilities to enable
4198 * the voltage regulator:
4199 * - by enabling it manually
4200 * using function @ref LL_ADC_EnableInternalRegulator().
4201 * - by launching a calibration
4202 * using function @ref LL_ADC_StartCalibration().
4203 * - by enabling the ADC
4204 * using function @ref LL_ADC_Enable().
4205 * @note On this STM32 series, after ADC internal voltage regulator enable,
4206 * a delay for ADC internal voltage regulator stabilization
4207 * is required before performing a ADC calibration or ADC enable.
4208 * Refer to device datasheet, parameter "tADCVREG_STUP".
4209 * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
4210 * @note On this STM32 series, setting of this feature is conditioned to
4211 * ADC state:
4212 * ADC must be ADC disabled.
4213 * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
4214 * @param ADCx ADC instance
4215 * @retval None
4216 */
LL_ADC_EnableInternalRegulator(ADC_TypeDef * ADCx)4217 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
4218 {
4219 /* Note: Write register with some additional bits forced to state reset */
4220 /* instead of modifying only the selected bit for this function, */
4221 /* to not interfere with bits with HW property "rs". */
4222 MODIFY_REG(ADCx->CR,
4223 ADC_CR_BITS_PROPERTY_RS,
4224 ADC_CR_ADVREGEN);
4225 }
4226
4227 /**
4228 * @brief Disable ADC internal voltage regulator.
4229 * @note On this STM32 series, setting of this feature is conditioned to
4230 * ADC state:
4231 * ADC must be ADC disabled.
4232 * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
4233 * @param ADCx ADC instance
4234 * @retval None
4235 */
LL_ADC_DisableInternalRegulator(ADC_TypeDef * ADCx)4236 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
4237 {
4238 CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
4239 }
4240
4241 /**
4242 * @brief Get the selected ADC instance internal voltage regulator state.
4243 * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
4244 * @param ADCx ADC instance
4245 * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
4246 */
LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef * ADCx)4247 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
4248 {
4249 return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
4250 }
4251
4252 /**
4253 * @brief Enable the selected ADC instance.
4254 * @note On this STM32 series, after ADC enable, a delay for
4255 * ADC internal analog stabilization is required before performing a
4256 * ADC conversion start.
4257 * Refer to device datasheet, parameter tSTAB.
4258 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
4259 * is enabled and when conversion clock is active.
4260 * (not only core clock: this ADC has a dual clock domain)
4261 * @note On this STM32 series, setting of this feature is conditioned to
4262 * ADC state:
4263 * ADC must be ADC disabled and ADC internal voltage regulator enabled.
4264 * @rmtoll CR ADEN LL_ADC_Enable
4265 * @param ADCx ADC instance
4266 * @retval None
4267 */
LL_ADC_Enable(ADC_TypeDef * ADCx)4268 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
4269 {
4270 /* Note: Write register with some additional bits forced to state reset */
4271 /* instead of modifying only the selected bit for this function, */
4272 /* to not interfere with bits with HW property "rs". */
4273 MODIFY_REG(ADCx->CR,
4274 ADC_CR_BITS_PROPERTY_RS,
4275 ADC_CR_ADEN);
4276 }
4277
4278 /**
4279 * @brief Disable the selected ADC instance.
4280 * @note On this STM32 series, setting of this feature is conditioned to
4281 * ADC state:
4282 * ADC must be not disabled. Must be enabled without conversion on going
4283 * on group regular.
4284 * @rmtoll CR ADDIS LL_ADC_Disable
4285 * @param ADCx ADC instance
4286 * @retval None
4287 */
LL_ADC_Disable(ADC_TypeDef * ADCx)4288 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
4289 {
4290 /* Note: Write register with some additional bits forced to state reset */
4291 /* instead of modifying only the selected bit for this function, */
4292 /* to not interfere with bits with HW property "rs". */
4293 MODIFY_REG(ADCx->CR,
4294 ADC_CR_BITS_PROPERTY_RS,
4295 ADC_CR_ADDIS);
4296 }
4297
4298 /**
4299 * @brief Get the selected ADC instance enable state.
4300 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
4301 * is enabled and when conversion clock is active.
4302 * (not only core clock: this ADC has a dual clock domain)
4303 * @rmtoll CR ADEN LL_ADC_IsEnabled
4304 * @param ADCx ADC instance
4305 * @retval 0: ADC is disabled, 1: ADC is enabled.
4306 */
LL_ADC_IsEnabled(ADC_TypeDef * ADCx)4307 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
4308 {
4309 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
4310 }
4311
4312 /**
4313 * @brief Get the selected ADC instance disable state.
4314 * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
4315 * @param ADCx ADC instance
4316 * @retval 0: no ADC disable command on going.
4317 */
LL_ADC_IsDisableOngoing(ADC_TypeDef * ADCx)4318 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
4319 {
4320 return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
4321 }
4322
4323 /**
4324 * @brief Start ADC calibration in the mode single-ended
4325 * or differential (for devices with differential mode available).
4326 * @note On this STM32 series, a minimum number of ADC clock cycles
4327 * are required between ADC end of calibration and ADC enable.
4328 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
4329 * @note In case of usage of ADC with DMA transfer:
4330 * On this STM32 series, ADC DMA transfer request should be disabled
4331 * during calibration:
4332 * Calibration factor is available in data register
4333 * and also transferred by DMA.
4334 * To not insert ADC calibration factor among ADC conversion data
4335 * in array variable, DMA transfer must be disabled during
4336 * calibration.
4337 * (DMA transfer setting backup and disable before calibration,
4338 * DMA transfer setting restore after calibration.
4339 * Refer to functions @ref LL_ADC_REG_GetDMATransfer(),
4340 * @ref LL_ADC_REG_SetDMATransfer() ).
4341 * @note In case of usage of feature auto power-off:
4342 * This mode must be disabled during calibration
4343 * Refer to function @ref LL_ADC_SetLowPowerMode().
4344 * @note On this STM32 series, setting of this feature is conditioned to
4345 * ADC state:
4346 * ADC must be ADC disabled.
4347 * @rmtoll CR ADCAL LL_ADC_StartCalibration
4348 * @param ADCx ADC instance
4349 * @retval None
4350 */
LL_ADC_StartCalibration(ADC_TypeDef * ADCx)4351 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx)
4352 {
4353 /* Note: Write register with some additional bits forced to state reset */
4354 /* instead of modifying only the selected bit for this function, */
4355 /* to not interfere with bits with HW property "rs". */
4356 MODIFY_REG(ADCx->CR,
4357 ADC_CR_BITS_PROPERTY_RS,
4358 ADC_CR_ADCAL);
4359 }
4360
4361 /**
4362 * @brief Get ADC calibration state.
4363 * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
4364 * @param ADCx ADC instance
4365 * @retval 0: calibration complete, 1: calibration in progress.
4366 */
LL_ADC_IsCalibrationOnGoing(ADC_TypeDef * ADCx)4367 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
4368 {
4369 return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
4370 }
4371
4372 /**
4373 * @}
4374 */
4375
4376 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
4377 * @{
4378 */
4379
4380 /**
4381 * @brief Start ADC group regular conversion.
4382 * @note On this STM32 series, this function is relevant for both
4383 * internal trigger (SW start) and external trigger:
4384 * - If ADC trigger has been set to software start, ADC conversion
4385 * starts immediately.
4386 * - If ADC trigger has been set to external trigger, ADC conversion
4387 * will start at next trigger event (on the selected trigger edge)
4388 * following the ADC start conversion command.
4389 * @note On this STM32 series, setting of this feature is conditioned to
4390 * ADC state:
4391 * ADC must be enabled without conversion on going on group regular,
4392 * without conversion stop command on going on group regular,
4393 * without ADC disable command on going.
4394 * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
4395 * @param ADCx ADC instance
4396 * @retval None
4397 */
LL_ADC_REG_StartConversion(ADC_TypeDef * ADCx)4398 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
4399 {
4400 /* Note: Write register with some additional bits forced to state reset */
4401 /* instead of modifying only the selected bit for this function, */
4402 /* to not interfere with bits with HW property "rs". */
4403 MODIFY_REG(ADCx->CR,
4404 ADC_CR_BITS_PROPERTY_RS,
4405 ADC_CR_ADSTART);
4406 }
4407
4408 /**
4409 * @brief Stop ADC group regular conversion.
4410 * @note On this STM32 series, setting of this feature is conditioned to
4411 * ADC state:
4412 * ADC must be enabled with conversion on going on group regular,
4413 * without ADC disable command on going.
4414 * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
4415 * @param ADCx ADC instance
4416 * @retval None
4417 */
LL_ADC_REG_StopConversion(ADC_TypeDef * ADCx)4418 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
4419 {
4420 /* Note: Write register with some additional bits forced to state reset */
4421 /* instead of modifying only the selected bit for this function, */
4422 /* to not interfere with bits with HW property "rs". */
4423 MODIFY_REG(ADCx->CR,
4424 ADC_CR_BITS_PROPERTY_RS,
4425 ADC_CR_ADSTP);
4426 }
4427
4428 /**
4429 * @brief Get ADC group regular conversion state.
4430 * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
4431 * @param ADCx ADC instance
4432 * @retval 0: no conversion is on going on ADC group regular.
4433 */
LL_ADC_REG_IsConversionOngoing(ADC_TypeDef * ADCx)4434 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
4435 {
4436 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
4437 }
4438
4439 /**
4440 * @brief Get ADC group regular command of conversion stop state
4441 * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
4442 * @param ADCx ADC instance
4443 * @retval 0: no command of conversion stop is on going on ADC group regular.
4444 */
LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef * ADCx)4445 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
4446 {
4447 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
4448 }
4449
4450 /**
4451 * @brief Get ADC group regular conversion data, range fit for
4452 * all ADC configurations: all ADC resolutions and
4453 * all oversampling increased data width (for devices
4454 * with feature oversampling).
4455 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData32
4456 * @param ADCx ADC instance
4457 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
4458 */
LL_ADC_REG_ReadConversionData32(ADC_TypeDef * ADCx)4459 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
4460 {
4461 return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4462 }
4463
4464 /**
4465 * @brief Get ADC group regular conversion data, range fit for
4466 * ADC resolution 12 bits.
4467 * @note For devices with feature oversampling: Oversampling
4468 * can increase data width, function for extended range
4469 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4470 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData12
4471 * @param ADCx ADC instance
4472 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
4473 */
LL_ADC_REG_ReadConversionData12(ADC_TypeDef * ADCx)4474 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
4475 {
4476 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4477 }
4478
4479 /**
4480 * @brief Get ADC group regular conversion data, range fit for
4481 * ADC resolution 10 bits.
4482 * @note For devices with feature oversampling: Oversampling
4483 * can increase data width, function for extended range
4484 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4485 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData10
4486 * @param ADCx ADC instance
4487 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
4488 */
LL_ADC_REG_ReadConversionData10(ADC_TypeDef * ADCx)4489 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
4490 {
4491 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4492 }
4493
4494 /**
4495 * @brief Get ADC group regular conversion data, range fit for
4496 * ADC resolution 8 bits.
4497 * @note For devices with feature oversampling: Oversampling
4498 * can increase data width, function for extended range
4499 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4500 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData8
4501 * @param ADCx ADC instance
4502 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
4503 */
LL_ADC_REG_ReadConversionData8(ADC_TypeDef * ADCx)4504 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
4505 {
4506 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4507 }
4508
4509 /**
4510 * @brief Get ADC group regular conversion data, range fit for
4511 * ADC resolution 6 bits.
4512 * @note For devices with feature oversampling: Oversampling
4513 * can increase data width, function for extended range
4514 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4515 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData6
4516 * @param ADCx ADC instance
4517 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
4518 */
LL_ADC_REG_ReadConversionData6(ADC_TypeDef * ADCx)4519 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
4520 {
4521 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4522 }
4523
4524 /**
4525 * @}
4526 */
4527
4528 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
4529 * @{
4530 */
4531
4532 /**
4533 * @brief Get flag ADC ready.
4534 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
4535 * is enabled and when conversion clock is active.
4536 * (not only core clock: this ADC has a dual clock domain)
4537 * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
4538 * @param ADCx ADC instance
4539 * @retval State of bit (1 or 0).
4540 */
LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef * ADCx)4541 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
4542 {
4543 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
4544 }
4545
4546 /**
4547 * @brief Get flag ADC channel configuration ready.
4548 * @note On this STM32 series, after modifying sequencer
4549 * it is mandatory to wait for the assertion of CCRDY flag
4550 * using @ref LL_ADC_IsActiveFlag_CCRDY().
4551 * Otherwise, performing some actions (configuration update,
4552 * ADC conversion start, ... ) will be ignored.
4553 * Functions requiring wait for CCRDY flag are:
4554 * @ref LL_ADC_REG_SetSequencerLength()
4555 * @ref LL_ADC_REG_SetSequencerRanks()
4556 * @ref LL_ADC_REG_SetSequencerChannels()
4557 * @ref LL_ADC_REG_SetSequencerChAdd()
4558 * @ref LL_ADC_REG_SetSequencerChRem()
4559 * @ref LL_ADC_REG_SetSequencerScanDirection()
4560 * @ref LL_ADC_REG_SetSequencerConfigurable()
4561 * @note Duration of ADC channel configuration ready: CCRDY handshake
4562 * requires 1APB + 2 ADC + 3 APB cycles after the channel configuration
4563 * has been changed.
4564 * @rmtoll ISR CCRDY LL_ADC_IsActiveFlag_CCRDY
4565 * @param ADCx ADC instance
4566 * @retval State of bit (1 or 0).
4567 */
LL_ADC_IsActiveFlag_CCRDY(ADC_TypeDef * ADCx)4568 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_CCRDY(ADC_TypeDef *ADCx)
4569 {
4570 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL);
4571 }
4572
4573 /**
4574 * @brief Get flag ADC group regular end of unitary conversion.
4575 * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
4576 * @param ADCx ADC instance
4577 * @retval State of bit (1 or 0).
4578 */
LL_ADC_IsActiveFlag_EOC(ADC_TypeDef * ADCx)4579 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
4580 {
4581 return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
4582 }
4583
4584 /**
4585 * @brief Get flag ADC group regular end of sequence conversions.
4586 * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
4587 * @param ADCx ADC instance
4588 * @retval State of bit (1 or 0).
4589 */
LL_ADC_IsActiveFlag_EOS(ADC_TypeDef * ADCx)4590 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
4591 {
4592 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
4593 }
4594
4595 /**
4596 * @brief Get flag ADC group regular overrun.
4597 * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
4598 * @param ADCx ADC instance
4599 * @retval State of bit (1 or 0).
4600 */
LL_ADC_IsActiveFlag_OVR(ADC_TypeDef * ADCx)4601 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
4602 {
4603 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
4604 }
4605
4606 /**
4607 * @brief Get flag ADC group regular end of sampling phase.
4608 * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
4609 * @param ADCx ADC instance
4610 * @retval State of bit (1 or 0).
4611 */
LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef * ADCx)4612 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
4613 {
4614 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
4615 }
4616
4617 /**
4618 * @brief Get flag ADC analog watchdog 1 flag
4619 * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
4620 * @param ADCx ADC instance
4621 * @retval State of bit (1 or 0).
4622 */
LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef * ADCx)4623 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
4624 {
4625 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
4626 }
4627
4628 /**
4629 * @brief Get flag ADC analog watchdog 2.
4630 * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
4631 * @param ADCx ADC instance
4632 * @retval State of bit (1 or 0).
4633 */
LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef * ADCx)4634 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
4635 {
4636 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
4637 }
4638
4639 /**
4640 * @brief Get flag ADC analog watchdog 3.
4641 * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
4642 * @param ADCx ADC instance
4643 * @retval State of bit (1 or 0).
4644 */
LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef * ADCx)4645 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
4646 {
4647 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
4648 }
4649
4650 /**
4651 * @brief Get flag ADC end of calibration.
4652 * @rmtoll ISR EOCAL LL_ADC_IsActiveFlag_EOCAL
4653 * @param ADCx ADC instance
4654 * @retval State of bit (1 or 0).
4655 */
LL_ADC_IsActiveFlag_EOCAL(ADC_TypeDef * ADCx)4656 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCAL(ADC_TypeDef *ADCx)
4657 {
4658 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOCAL) == (LL_ADC_FLAG_EOCAL)) ? 1UL : 0UL);
4659 }
4660
4661 /**
4662 * @brief Clear flag ADC ready.
4663 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
4664 * is enabled and when conversion clock is active.
4665 * (not only core clock: this ADC has a dual clock domain)
4666 * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
4667 * @param ADCx ADC instance
4668 * @retval None
4669 */
LL_ADC_ClearFlag_ADRDY(ADC_TypeDef * ADCx)4670 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
4671 {
4672 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
4673 }
4674
4675 /**
4676 * @brief Clear flag ADC channel configuration ready.
4677 * @rmtoll ISR CCRDY LL_ADC_ClearFlag_CCRDY
4678 * @param ADCx ADC instance
4679 * @retval State of bit (1 or 0).
4680 */
LL_ADC_ClearFlag_CCRDY(ADC_TypeDef * ADCx)4681 __STATIC_INLINE void LL_ADC_ClearFlag_CCRDY(ADC_TypeDef *ADCx)
4682 {
4683 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_CCRDY);
4684 }
4685
4686 /**
4687 * @brief Clear flag ADC group regular end of unitary conversion.
4688 * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
4689 * @param ADCx ADC instance
4690 * @retval None
4691 */
LL_ADC_ClearFlag_EOC(ADC_TypeDef * ADCx)4692 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
4693 {
4694 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
4695 }
4696
4697 /**
4698 * @brief Clear flag ADC group regular end of sequence conversions.
4699 * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
4700 * @param ADCx ADC instance
4701 * @retval None
4702 */
LL_ADC_ClearFlag_EOS(ADC_TypeDef * ADCx)4703 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
4704 {
4705 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
4706 }
4707
4708 /**
4709 * @brief Clear flag ADC group regular overrun.
4710 * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
4711 * @param ADCx ADC instance
4712 * @retval None
4713 */
LL_ADC_ClearFlag_OVR(ADC_TypeDef * ADCx)4714 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
4715 {
4716 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
4717 }
4718
4719 /**
4720 * @brief Clear flag ADC group regular end of sampling phase.
4721 * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
4722 * @param ADCx ADC instance
4723 * @retval None
4724 */
LL_ADC_ClearFlag_EOSMP(ADC_TypeDef * ADCx)4725 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
4726 {
4727 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
4728 }
4729
4730 /**
4731 * @brief Clear flag ADC analog watchdog 1.
4732 * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
4733 * @param ADCx ADC instance
4734 * @retval None
4735 */
LL_ADC_ClearFlag_AWD1(ADC_TypeDef * ADCx)4736 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
4737 {
4738 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
4739 }
4740
4741 /**
4742 * @brief Clear flag ADC analog watchdog 2.
4743 * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
4744 * @param ADCx ADC instance
4745 * @retval None
4746 */
LL_ADC_ClearFlag_AWD2(ADC_TypeDef * ADCx)4747 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
4748 {
4749 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
4750 }
4751
4752 /**
4753 * @brief Clear flag ADC analog watchdog 3.
4754 * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
4755 * @param ADCx ADC instance
4756 * @retval None
4757 */
LL_ADC_ClearFlag_AWD3(ADC_TypeDef * ADCx)4758 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
4759 {
4760 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
4761 }
4762
4763 /**
4764 * @brief Clear flag ADC end of calibration.
4765 * @rmtoll ISR EOCAL LL_ADC_ClearFlag_EOCAL
4766 * @param ADCx ADC instance
4767 * @retval None
4768 */
LL_ADC_ClearFlag_EOCAL(ADC_TypeDef * ADCx)4769 __STATIC_INLINE void LL_ADC_ClearFlag_EOCAL(ADC_TypeDef *ADCx)
4770 {
4771 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOCAL);
4772 }
4773
4774 /**
4775 * @}
4776 */
4777
4778 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
4779 * @{
4780 */
4781
4782 /**
4783 * @brief Enable ADC ready.
4784 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
4785 * @param ADCx ADC instance
4786 * @retval None
4787 */
LL_ADC_EnableIT_ADRDY(ADC_TypeDef * ADCx)4788 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
4789 {
4790 SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
4791 }
4792
4793 /**
4794 * @brief Enable interruption ADC channel configuration ready.
4795 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_CCRDY
4796 * @param ADCx ADC instance
4797 * @retval State of bit (1 or 0).
4798 */
LL_ADC_EnableIT_CCRDY(ADC_TypeDef * ADCx)4799 __STATIC_INLINE void LL_ADC_EnableIT_CCRDY(ADC_TypeDef *ADCx)
4800 {
4801 SET_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY);
4802 }
4803
4804 /**
4805 * @brief Enable interruption ADC group regular end of unitary conversion.
4806 * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
4807 * @param ADCx ADC instance
4808 * @retval None
4809 */
LL_ADC_EnableIT_EOC(ADC_TypeDef * ADCx)4810 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
4811 {
4812 SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
4813 }
4814
4815 /**
4816 * @brief Enable interruption ADC group regular end of sequence conversions.
4817 * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
4818 * @param ADCx ADC instance
4819 * @retval None
4820 */
LL_ADC_EnableIT_EOS(ADC_TypeDef * ADCx)4821 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
4822 {
4823 SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
4824 }
4825
4826 /**
4827 * @brief Enable ADC group regular interruption overrun.
4828 * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
4829 * @param ADCx ADC instance
4830 * @retval None
4831 */
LL_ADC_EnableIT_OVR(ADC_TypeDef * ADCx)4832 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
4833 {
4834 SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
4835 }
4836
4837 /**
4838 * @brief Enable interruption ADC group regular end of sampling.
4839 * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
4840 * @param ADCx ADC instance
4841 * @retval None
4842 */
LL_ADC_EnableIT_EOSMP(ADC_TypeDef * ADCx)4843 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
4844 {
4845 SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
4846 }
4847
4848 /**
4849 * @brief Enable interruption ADC analog watchdog 1.
4850 * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
4851 * @param ADCx ADC instance
4852 * @retval None
4853 */
LL_ADC_EnableIT_AWD1(ADC_TypeDef * ADCx)4854 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
4855 {
4856 SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
4857 }
4858
4859 /**
4860 * @brief Enable interruption ADC analog watchdog 2.
4861 * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
4862 * @param ADCx ADC instance
4863 * @retval None
4864 */
LL_ADC_EnableIT_AWD2(ADC_TypeDef * ADCx)4865 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
4866 {
4867 SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
4868 }
4869
4870 /**
4871 * @brief Enable interruption ADC analog watchdog 3.
4872 * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
4873 * @param ADCx ADC instance
4874 * @retval None
4875 */
LL_ADC_EnableIT_AWD3(ADC_TypeDef * ADCx)4876 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
4877 {
4878 SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
4879 }
4880 /**
4881 * @brief Enable interruption ADC end of calibration.
4882 * @rmtoll IER EOCALIE LL_ADC_EnableIT_EOCAL
4883 * @param ADCx ADC instance
4884 * @retval None
4885 */
LL_ADC_EnableIT_EOCAL(ADC_TypeDef * ADCx)4886 __STATIC_INLINE void LL_ADC_EnableIT_EOCAL(ADC_TypeDef *ADCx)
4887 {
4888 SET_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
4889 }
4890
4891 /**
4892 * @brief Disable interruption ADC ready.
4893 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
4894 * @param ADCx ADC instance
4895 * @retval None
4896 */
LL_ADC_DisableIT_ADRDY(ADC_TypeDef * ADCx)4897 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
4898 {
4899 CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
4900 }
4901
4902 /**
4903 * @brief Disable interruption ADC channel configuration ready.
4904 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_CCRDY
4905 * @param ADCx ADC instance
4906 * @retval State of bit (1 or 0).
4907 */
LL_ADC_DisableIT_CCRDY(ADC_TypeDef * ADCx)4908 __STATIC_INLINE void LL_ADC_DisableIT_CCRDY(ADC_TypeDef *ADCx)
4909 {
4910 CLEAR_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY);
4911 }
4912
4913 /**
4914 * @brief Disable interruption ADC group regular end of unitary conversion.
4915 * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
4916 * @param ADCx ADC instance
4917 * @retval None
4918 */
LL_ADC_DisableIT_EOC(ADC_TypeDef * ADCx)4919 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
4920 {
4921 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
4922 }
4923
4924 /**
4925 * @brief Disable interruption ADC group regular end of sequence conversions.
4926 * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
4927 * @param ADCx ADC instance
4928 * @retval None
4929 */
LL_ADC_DisableIT_EOS(ADC_TypeDef * ADCx)4930 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
4931 {
4932 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
4933 }
4934
4935 /**
4936 * @brief Disable interruption ADC group regular overrun.
4937 * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
4938 * @param ADCx ADC instance
4939 * @retval None
4940 */
LL_ADC_DisableIT_OVR(ADC_TypeDef * ADCx)4941 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
4942 {
4943 CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
4944 }
4945
4946 /**
4947 * @brief Disable interruption ADC group regular end of sampling.
4948 * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
4949 * @param ADCx ADC instance
4950 * @retval None
4951 */
LL_ADC_DisableIT_EOSMP(ADC_TypeDef * ADCx)4952 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
4953 {
4954 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
4955 }
4956
4957 /**
4958 * @brief Disable interruption ADC analog watchdog 1.
4959 * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
4960 * @param ADCx ADC instance
4961 * @retval None
4962 */
LL_ADC_DisableIT_AWD1(ADC_TypeDef * ADCx)4963 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
4964 {
4965 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
4966 }
4967
4968 /**
4969 * @brief Disable interruption ADC analog watchdog 2.
4970 * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
4971 * @param ADCx ADC instance
4972 * @retval None
4973 */
LL_ADC_DisableIT_AWD2(ADC_TypeDef * ADCx)4974 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
4975 {
4976 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
4977 }
4978
4979 /**
4980 * @brief Disable interruption ADC analog watchdog 3.
4981 * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
4982 * @param ADCx ADC instance
4983 * @retval None
4984 */
LL_ADC_DisableIT_AWD3(ADC_TypeDef * ADCx)4985 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
4986 {
4987 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
4988 }
4989
4990 /**
4991 * @brief Disable interruption ADC end of calibration.
4992 * @rmtoll IER EOCALIE LL_ADC_DisableIT_EOCAL
4993 * @param ADCx ADC instance
4994 * @retval None
4995 */
LL_ADC_DisableIT_EOCAL(ADC_TypeDef * ADCx)4996 __STATIC_INLINE void LL_ADC_DisableIT_EOCAL(ADC_TypeDef *ADCx)
4997 {
4998 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
4999 }
5000
5001 /**
5002 * @brief Get state of interruption ADC ready
5003 * (0: interrupt disabled, 1: interrupt enabled).
5004 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
5005 * @param ADCx ADC instance
5006 * @retval State of bit (1 or 0).
5007 */
LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef * ADCx)5008 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
5009 {
5010 return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
5011 }
5012
5013 /**
5014 * @brief Get state of interruption ADC channel configuration ready.
5015 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_CCRDY
5016 * @param ADCx ADC instance
5017 * @retval State of bit (1 or 0).
5018 */
LL_ADC_IsEnabledIT_CCRDY(ADC_TypeDef * ADCx)5019 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_CCRDY(ADC_TypeDef *ADCx)
5020 {
5021 return ((READ_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL);
5022 }
5023
5024 /**
5025 * @brief Get state of interruption ADC group regular end of unitary conversion
5026 * (0: interrupt disabled, 1: interrupt enabled).
5027 * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
5028 * @param ADCx ADC instance
5029 * @retval State of bit (1 or 0).
5030 */
LL_ADC_IsEnabledIT_EOC(ADC_TypeDef * ADCx)5031 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
5032 {
5033 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
5034 }
5035
5036 /**
5037 * @brief Get state of interruption ADC group regular end of sequence conversions
5038 * (0: interrupt disabled, 1: interrupt enabled).
5039 * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
5040 * @param ADCx ADC instance
5041 * @retval State of bit (1 or 0).
5042 */
LL_ADC_IsEnabledIT_EOS(ADC_TypeDef * ADCx)5043 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
5044 {
5045 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
5046 }
5047
5048 /**
5049 * @brief Get state of interruption ADC group regular overrun
5050 * (0: interrupt disabled, 1: interrupt enabled).
5051 * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
5052 * @param ADCx ADC instance
5053 * @retval State of bit (1 or 0).
5054 */
LL_ADC_IsEnabledIT_OVR(ADC_TypeDef * ADCx)5055 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
5056 {
5057 return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
5058 }
5059
5060 /**
5061 * @brief Get state of interruption ADC group regular end of sampling
5062 * (0: interrupt disabled, 1: interrupt enabled).
5063 * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
5064 * @param ADCx ADC instance
5065 * @retval State of bit (1 or 0).
5066 */
LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef * ADCx)5067 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
5068 {
5069 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
5070 }
5071
5072 /**
5073 * @brief Get state of interruption ADC analog watchdog 1
5074 * (0: interrupt disabled, 1: interrupt enabled).
5075 * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
5076 * @param ADCx ADC instance
5077 * @retval State of bit (1 or 0).
5078 */
LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef * ADCx)5079 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
5080 {
5081 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
5082 }
5083
5084 /**
5085 * @brief Get state of interruption Get ADC analog watchdog 2
5086 * (0: interrupt disabled, 1: interrupt enabled).
5087 * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
5088 * @param ADCx ADC instance
5089 * @retval State of bit (1 or 0).
5090 */
LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef * ADCx)5091 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
5092 {
5093 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
5094 }
5095
5096 /**
5097 * @brief Get state of interruption Get ADC analog watchdog 3
5098 * (0: interrupt disabled, 1: interrupt enabled).
5099 * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
5100 * @param ADCx ADC instance
5101 * @retval State of bit (1 or 0).
5102 */
LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef * ADCx)5103 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
5104 {
5105 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
5106 }
5107
5108 /**
5109 * @brief Get state of interruption ADC end of calibration
5110 * (0: interrupt disabled, 1: interrupt enabled).
5111 * @rmtoll IER EOCALIE LL_ADC_IsEnabledIT_EOCAL
5112 * @param ADCx ADC instance
5113 * @retval State of bit (1 or 0).
5114 */
LL_ADC_IsEnabledIT_EOCAL(ADC_TypeDef * ADCx)5115 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(ADC_TypeDef *ADCx)
5116 {
5117 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOCAL) == (LL_ADC_IT_EOCAL)) ? 1UL : 0UL);
5118 }
5119
5120 /**
5121 * @}
5122 */
5123
5124 #if defined(USE_FULL_LL_DRIVER)
5125 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
5126 * @{
5127 */
5128
5129 /* Initialization of some features of ADC common parameters and multimode */
5130 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
5131 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
5132 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
5133
5134 /* De-initialization of ADC instance */
5135 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
5136
5137 /* Initialization of some features of ADC instance */
5138 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
5139 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
5140
5141 /* Initialization of some features of ADC instance and ADC group regular */
5142 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
5143 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
5144
5145 /**
5146 * @}
5147 */
5148 #endif /* USE_FULL_LL_DRIVER */
5149
5150 /**
5151 * @}
5152 */
5153
5154 /**
5155 * @}
5156 */
5157
5158 #endif /* ADC1 */
5159
5160 /**
5161 * @}
5162 */
5163
5164 #ifdef __cplusplus
5165 }
5166 #endif
5167
5168 #endif /* STM32C0xx_LL_ADC_H */
5169
