1  /**
2    ******************************************************************************
3    * @file    stm32c0xx_hal_tim.h
4    * @author  MCD Application Team
5    * @brief   Header file of TIM HAL module.
6    ******************************************************************************
7    * @attention
8    *
9    * Copyright (c) 2022 STMicroelectronics.
10    * All rights reserved.
11    *
12    * This software is licensed under terms that can be found in the LICENSE file
13    * in the root directory of this software component.
14    * If no LICENSE file comes with this software, it is provided AS-IS.
15    *
16    ******************************************************************************
17    */
18  
19  /* Define to prevent recursive inclusion -------------------------------------*/
20  #ifndef STM32C0xx_HAL_TIM_H
21  #define STM32C0xx_HAL_TIM_H
22  
23  #ifdef __cplusplus
24  extern "C" {
25  #endif
26  
27  /* Includes ------------------------------------------------------------------*/
28  #include "stm32c0xx_hal_def.h"
29  
30  /** @addtogroup STM32C0xx_HAL_Driver
31    * @{
32    */
33  
34  /** @addtogroup TIM
35    * @{
36    */
37  
38  /* Exported types ------------------------------------------------------------*/
39  /** @defgroup TIM_Exported_Types TIM Exported Types
40    * @{
41    */
42  
43  /**
44    * @brief  TIM Time base Configuration Structure definition
45    */
46  typedef struct
47  {
48    uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
49                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
50  
51    uint32_t CounterMode;       /*!< Specifies the counter mode.
52                                     This parameter can be a value of @ref TIM_Counter_Mode */
53  
54    uint32_t Period;            /*!< Specifies the period value to be loaded into the active
55                                     Auto-Reload Register at the next update event.
56                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */
57  
58    uint32_t ClockDivision;     /*!< Specifies the clock division.
59                                     This parameter can be a value of @ref TIM_ClockDivision */
60  
61    uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
62                                      reaches zero, an update event is generated and counting restarts
63                                      from the RCR value (N).
64                                      This means in PWM mode that (N+1) corresponds to:
65                                          - the number of PWM periods in edge-aligned mode
66                                          - the number of half PWM period in center-aligned mode
67                                       GP timers: this parameter must be a number between Min_Data = 0x00 and
68                                       Max_Data = 0xFF.
69                                       Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
70                                       Max_Data = 0xFFFF. */
71  
72    uint32_t AutoReloadPreload;  /*!< Specifies the auto-reload preload.
73                                     This parameter can be a value of @ref TIM_AutoReloadPreload */
74  } TIM_Base_InitTypeDef;
75  
76  /**
77    * @brief  TIM Output Compare Configuration Structure definition
78    */
79  typedef struct
80  {
81    uint32_t OCMode;        /*!< Specifies the TIM mode.
82                                 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
83  
84    uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
85                                 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
86  
87    uint32_t OCPolarity;    /*!< Specifies the output polarity.
88                                 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
89  
90    uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
91                                 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
92                                 @note This parameter is valid only for timer instances supporting break feature. */
93  
94    uint32_t OCFastMode;    /*!< Specifies the Fast mode state.
95                                 This parameter can be a value of @ref TIM_Output_Fast_State
96                                 @note This parameter is valid only in PWM1 and PWM2 mode. */
97  
98  
99    uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
100                                 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
101                                 @note This parameter is valid only for timer instances supporting break feature. */
102  
103    uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
104                                 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
105                                 @note This parameter is valid only for timer instances supporting break feature. */
106  } TIM_OC_InitTypeDef;
107  
108  /**
109    * @brief  TIM One Pulse Mode Configuration Structure definition
110    */
111  typedef struct
112  {
113    uint32_t OCMode;        /*!< Specifies the TIM mode.
114                                 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
115  
116    uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
117                                 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
118  
119    uint32_t OCPolarity;    /*!< Specifies the output polarity.
120                                 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
121  
122    uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
123                                 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
124                                 @note This parameter is valid only for timer instances supporting break feature. */
125  
126    uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
127                                 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
128                                 @note This parameter is valid only for timer instances supporting break feature. */
129  
130    uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
131                                 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
132                                 @note This parameter is valid only for timer instances supporting break feature. */
133  
134    uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
135                                 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
136  
137    uint32_t ICSelection;   /*!< Specifies the input.
138                                This parameter can be a value of @ref TIM_Input_Capture_Selection */
139  
140    uint32_t ICFilter;      /*!< Specifies the input capture filter.
141                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
142  } TIM_OnePulse_InitTypeDef;
143  
144  /**
145    * @brief  TIM Input Capture Configuration Structure definition
146    */
147  typedef struct
148  {
149    uint32_t  ICPolarity;  /*!< Specifies the active edge of the input signal.
150                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
151  
152    uint32_t ICSelection;  /*!< Specifies the input.
153                                This parameter can be a value of @ref TIM_Input_Capture_Selection */
154  
155    uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
156                                This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
157  
158    uint32_t ICFilter;     /*!< Specifies the input capture filter.
159                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
160  } TIM_IC_InitTypeDef;
161  
162  /**
163    * @brief  TIM Encoder Configuration Structure definition
164    */
165  typedef struct
166  {
167    uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
168                                 This parameter can be a value of @ref TIM_Encoder_Mode */
169  
170    uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
171                                 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
172  
173    uint32_t IC1Selection;  /*!< Specifies the input.
174                                 This parameter can be a value of @ref TIM_Input_Capture_Selection */
175  
176    uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
177                                 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
178  
179    uint32_t IC1Filter;     /*!< Specifies the input capture filter.
180                                 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
181  
182    uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
183                                 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
184  
185    uint32_t IC2Selection;  /*!< Specifies the input.
186                                This parameter can be a value of @ref TIM_Input_Capture_Selection */
187  
188    uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
189                                 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
190  
191    uint32_t IC2Filter;     /*!< Specifies the input capture filter.
192                                 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
193  } TIM_Encoder_InitTypeDef;
194  
195  /**
196    * @brief  Clock Configuration Handle Structure definition
197    */
198  typedef struct
199  {
200    uint32_t ClockSource;     /*!< TIM clock sources
201                                   This parameter can be a value of @ref TIM_Clock_Source */
202    uint32_t ClockPolarity;   /*!< TIM clock polarity
203                                   This parameter can be a value of @ref TIM_Clock_Polarity */
204    uint32_t ClockPrescaler;  /*!< TIM clock prescaler
205                                   This parameter can be a value of @ref TIM_Clock_Prescaler */
206    uint32_t ClockFilter;     /*!< TIM clock filter
207                                   This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
208  } TIM_ClockConfigTypeDef;
209  
210  /**
211    * @brief  TIM Clear Input Configuration Handle Structure definition
212    */
213  typedef struct
214  {
215    uint32_t ClearInputState;      /*!< TIM clear Input state
216                                        This parameter can be ENABLE or DISABLE */
217    uint32_t ClearInputSource;     /*!< TIM clear Input sources
218                                        This parameter can be a value of @ref TIM_ClearInput_Source */
219    uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity
220                                        This parameter can be a value of @ref TIM_ClearInput_Polarity */
221    uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler
222                                        This parameter must be 0: When OCRef clear feature is used with ETR source,
223                                        ETR prescaler must be off */
224    uint32_t ClearInputFilter;     /*!< TIM Clear Input filter
225                                        This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
226  } TIM_ClearInputConfigTypeDef;
227  
228  /**
229    * @brief  TIM Master configuration Structure definition
230    * @note   Advanced timers provide TRGO2 internal line which is redirected
231    *         to the ADC
232    */
233  typedef struct
234  {
235    uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection
236                                          This parameter can be a value of @ref TIM_Master_Mode_Selection */
237    uint32_t  MasterOutputTrigger2;  /*!< Trigger output2 (TRGO2) selection
238                                          This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
239    uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection
240                                          This parameter can be a value of @ref TIM_Master_Slave_Mode
241                                          @note When the Master/slave mode is enabled, the effect of
242                                          an event on the trigger input (TRGI) is delayed to allow a
243                                          perfect synchronization between the current timer and its
244                                          slaves (through TRGO). It is not mandatory in case of timer
245                                          synchronization mode. */
246  } TIM_MasterConfigTypeDef;
247  
248  /**
249    * @brief  TIM Slave configuration Structure definition
250    */
251  typedef struct
252  {
253    uint32_t  SlaveMode;         /*!< Slave mode selection
254                                      This parameter can be a value of @ref TIM_Slave_Mode */
255    uint32_t  InputTrigger;      /*!< Input Trigger source
256                                      This parameter can be a value of @ref TIM_Trigger_Selection */
257    uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
258                                      This parameter can be a value of @ref TIM_Trigger_Polarity */
259    uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
260                                      This parameter can be a value of @ref TIM_Trigger_Prescaler */
261    uint32_t  TriggerFilter;     /*!< Input trigger filter
262                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF  */
263  
264  } TIM_SlaveConfigTypeDef;
265  
266  /**
267    * @brief  TIM Break input(s) and Dead time configuration Structure definition
268    * @note   2 break inputs can be configured (BKIN and BKIN2) with configurable
269    *        filter and polarity.
270    */
271  typedef struct
272  {
273    uint32_t OffStateRunMode;      /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
274  
275    uint32_t OffStateIDLEMode;     /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
276  
277    uint32_t LockLevel;            /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */
278  
279    uint32_t DeadTime;             /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
280  
281    uint32_t BreakState;           /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */
282  
283    uint32_t BreakPolarity;        /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */
284  
285    uint32_t BreakFilter;          /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
286  
287    uint32_t BreakAFMode;          /*!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode */
288  
289    uint32_t Break2State;          /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
290  
291    uint32_t Break2Polarity;       /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */
292  
293    uint32_t Break2Filter;         /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
294  
295    uint32_t Break2AFMode;         /*!< Specifies the alternate function mode of the break2 input.This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */
296  
297    uint32_t AutomaticOutput;      /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
298  
299  } TIM_BreakDeadTimeConfigTypeDef;
300  
301  /**
302    * @brief  HAL State structures definition
303    */
304  typedef enum
305  {
306    HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
307    HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
308    HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
309    HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
310    HAL_TIM_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                */
311  } HAL_TIM_StateTypeDef;
312  
313  /**
314    * @brief  TIM Channel States definition
315    */
316  typedef enum
317  {
318    HAL_TIM_CHANNEL_STATE_RESET             = 0x00U,    /*!< TIM Channel initial state                         */
319    HAL_TIM_CHANNEL_STATE_READY             = 0x01U,    /*!< TIM Channel ready for use                         */
320    HAL_TIM_CHANNEL_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing on the TIM channel */
321  } HAL_TIM_ChannelStateTypeDef;
322  
323  /**
324    * @brief  DMA Burst States definition
325    */
326  typedef enum
327  {
328    HAL_DMA_BURST_STATE_RESET             = 0x00U,    /*!< DMA Burst initial state */
329    HAL_DMA_BURST_STATE_READY             = 0x01U,    /*!< DMA Burst ready for use */
330    HAL_DMA_BURST_STATE_BUSY              = 0x02U,    /*!< Ongoing DMA Burst       */
331  } HAL_TIM_DMABurstStateTypeDef;
332  
333  /**
334    * @brief  HAL Active channel structures definition
335    */
336  typedef enum
337  {
338    HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */
339    HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */
340    HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */
341    HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */
342    HAL_TIM_ACTIVE_CHANNEL_5        = 0x10U,    /*!< The active channel is 5     */
343    HAL_TIM_ACTIVE_CHANNEL_6        = 0x20U,    /*!< The active channel is 6     */
344    HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U     /*!< All active channels cleared */
345  } HAL_TIM_ActiveChannel;
346  
347  /**
348    * @brief  TIM Time Base Handle Structure definition
349    */
350  #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
351  typedef struct __TIM_HandleTypeDef
352  #else
353  typedef struct
354  #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
355  {
356    TIM_TypeDef                        *Instance;         /*!< Register base address                             */
357    TIM_Base_InitTypeDef               Init;              /*!< TIM Time Base required parameters                 */
358    HAL_TIM_ActiveChannel              Channel;           /*!< Active channel                                    */
359    DMA_HandleTypeDef                  *hdma[7];          /*!< DMA Handlers array
360                                                               This array is accessed by a @ref DMA_Handle_index */
361    HAL_LockTypeDef                    Lock;              /*!< Locking object                                    */
362    __IO HAL_TIM_StateTypeDef          State;             /*!< TIM operation state                               */
363    __IO HAL_TIM_ChannelStateTypeDef   ChannelState[6];   /*!< TIM channel operation state                       */
364    __IO HAL_TIM_ChannelStateTypeDef   ChannelNState[4];  /*!< TIM complementary channel operation state         */
365    __IO HAL_TIM_DMABurstStateTypeDef  DMABurstState;     /*!< DMA burst operation state                         */
366  
367  #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
368    void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM Base Msp Init Callback                              */
369    void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);            /*!< TIM Base Msp DeInit Callback                            */
370    void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM IC Msp Init Callback                                */
371    void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM IC Msp DeInit Callback                              */
372    void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM OC Msp Init Callback                                */
373    void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM OC Msp DeInit Callback                              */
374    void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM PWM Msp Init Callback                               */
375    void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM PWM Msp DeInit Callback                             */
376    void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim);          /*!< TIM One Pulse Msp Init Callback                         */
377    void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM One Pulse Msp DeInit Callback                       */
378    void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Encoder Msp Init Callback                           */
379    void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM Encoder Msp DeInit Callback                         */
380    void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Hall Sensor Msp Init Callback                       */
381    void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);      /*!< TIM Hall Sensor Msp DeInit Callback                     */
382    void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM Period Elapsed Callback                             */
383    void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);     /*!< TIM Period Elapsed half complete Callback               */
384    void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim);                   /*!< TIM Trigger Callback                                    */
385    void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Trigger half complete Callback                      */
386    void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM Input Capture Callback                              */
387    void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Input Capture half complete Callback                */
388    void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Output Compare Delay Elapsed Callback               */
389    void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM PWM Pulse Finished Callback                         */
390    void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback           */
391    void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Error Callback                                      */
392    void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM Commutation Callback                                */
393    void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);       /*!< TIM Commutation half complete Callback                  */
394    void (* BreakCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Break Callback                                      */
395    void (* Break2Callback)(struct __TIM_HandleTypeDef *htim);                    /*!< TIM Break2 Callback                                     */
396  #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
397  } TIM_HandleTypeDef;
398  
399  #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
400  /**
401    * @brief  HAL TIM Callback ID enumeration definition
402    */
403  typedef enum
404  {
405    HAL_TIM_BASE_MSPINIT_CB_ID              = 0x00U   /*!< TIM Base MspInit Callback ID                              */
406    , HAL_TIM_BASE_MSPDEINIT_CB_ID          = 0x01U   /*!< TIM Base MspDeInit Callback ID                            */
407    , HAL_TIM_IC_MSPINIT_CB_ID              = 0x02U   /*!< TIM IC MspInit Callback ID                                */
408    , HAL_TIM_IC_MSPDEINIT_CB_ID            = 0x03U   /*!< TIM IC MspDeInit Callback ID                              */
409    , HAL_TIM_OC_MSPINIT_CB_ID              = 0x04U   /*!< TIM OC MspInit Callback ID                                */
410    , HAL_TIM_OC_MSPDEINIT_CB_ID            = 0x05U   /*!< TIM OC MspDeInit Callback ID                              */
411    , HAL_TIM_PWM_MSPINIT_CB_ID             = 0x06U   /*!< TIM PWM MspInit Callback ID                               */
412    , HAL_TIM_PWM_MSPDEINIT_CB_ID           = 0x07U   /*!< TIM PWM MspDeInit Callback ID                             */
413    , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID       = 0x08U   /*!< TIM One Pulse MspInit Callback ID                         */
414    , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID     = 0x09U   /*!< TIM One Pulse MspDeInit Callback ID                       */
415    , HAL_TIM_ENCODER_MSPINIT_CB_ID         = 0x0AU   /*!< TIM Encoder MspInit Callback ID                           */
416    , HAL_TIM_ENCODER_MSPDEINIT_CB_ID       = 0x0BU   /*!< TIM Encoder MspDeInit Callback ID                         */
417    , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID     = 0x0CU   /*!< TIM Hall Sensor MspDeInit Callback ID                     */
418    , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID   = 0x0DU   /*!< TIM Hall Sensor MspDeInit Callback ID                     */
419    , HAL_TIM_PERIOD_ELAPSED_CB_ID          = 0x0EU   /*!< TIM Period Elapsed Callback ID                             */
420    , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID     = 0x0FU   /*!< TIM Period Elapsed half complete Callback ID               */
421    , HAL_TIM_TRIGGER_CB_ID                 = 0x10U   /*!< TIM Trigger Callback ID                                    */
422    , HAL_TIM_TRIGGER_HALF_CB_ID            = 0x11U   /*!< TIM Trigger half complete Callback ID                      */
423  
424    , HAL_TIM_IC_CAPTURE_CB_ID              = 0x12U   /*!< TIM Input Capture Callback ID                              */
425    , HAL_TIM_IC_CAPTURE_HALF_CB_ID         = 0x13U   /*!< TIM Input Capture half complete Callback ID                */
426    , HAL_TIM_OC_DELAY_ELAPSED_CB_ID        = 0x14U   /*!< TIM Output Compare Delay Elapsed Callback ID               */
427    , HAL_TIM_PWM_PULSE_FINISHED_CB_ID      = 0x15U   /*!< TIM PWM Pulse Finished Callback ID           */
428    , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U   /*!< TIM PWM Pulse Finished half complete Callback ID           */
429    , HAL_TIM_ERROR_CB_ID                   = 0x17U   /*!< TIM Error Callback ID                                      */
430    , HAL_TIM_COMMUTATION_CB_ID             = 0x18U   /*!< TIM Commutation Callback ID                                */
431    , HAL_TIM_COMMUTATION_HALF_CB_ID        = 0x19U   /*!< TIM Commutation half complete Callback ID                  */
432    , HAL_TIM_BREAK_CB_ID                   = 0x1AU   /*!< TIM Break Callback ID                                      */
433    , HAL_TIM_BREAK2_CB_ID                  = 0x1BU   /*!< TIM Break2 Callback ID                                     */
434  } HAL_TIM_CallbackIDTypeDef;
435  
436  /**
437    * @brief  HAL TIM Callback pointer definition
438    */
439  typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to the TIM callback function */
440  
441  #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
442  
443  /**
444    * @}
445    */
446  /* End of exported types -----------------------------------------------------*/
447  
448  /* Exported constants --------------------------------------------------------*/
449  /** @defgroup TIM_Exported_Constants TIM Exported Constants
450    * @{
451    */
452  
453  /** @defgroup TIM_ClearInput_Source TIM Clear Input Source
454    * @{
455    */
456  #define TIM_CLEARINPUTSOURCE_NONE           0x10000000U           /*!< OCREF_CLR is disabled */
457  #define TIM_CLEARINPUTSOURCE_ETR            0x20000000U           /*!< OCREF_CLR is connected to ETRF input */
458  /**
459    * @}
460    */
461  
462  /** @defgroup TIM_DMA_Base_address TIM DMA Base Address
463    * @{
464    */
465  #define TIM_DMABASE_CR1                    0x00000000U
466  #define TIM_DMABASE_CR2                    0x00000001U
467  #define TIM_DMABASE_SMCR                   0x00000002U
468  #define TIM_DMABASE_DIER                   0x00000003U
469  #define TIM_DMABASE_SR                     0x00000004U
470  #define TIM_DMABASE_EGR                    0x00000005U
471  #define TIM_DMABASE_CCMR1                  0x00000006U
472  #define TIM_DMABASE_CCMR2                  0x00000007U
473  #define TIM_DMABASE_CCER                   0x00000008U
474  #define TIM_DMABASE_CNT                    0x00000009U
475  #define TIM_DMABASE_PSC                    0x0000000AU
476  #define TIM_DMABASE_ARR                    0x0000000BU
477  #define TIM_DMABASE_RCR                    0x0000000CU
478  #define TIM_DMABASE_CCR1                   0x0000000DU
479  #define TIM_DMABASE_CCR2                   0x0000000EU
480  #define TIM_DMABASE_CCR3                   0x0000000FU
481  #define TIM_DMABASE_CCR4                   0x00000010U
482  #define TIM_DMABASE_BDTR                   0x00000011U
483  #define TIM_DMABASE_DCR                    0x00000012U
484  #define TIM_DMABASE_DMAR                   0x00000013U
485  #define TIM_DMABASE_CCMR3                  0x00000015U
486  #define TIM_DMABASE_CCR5                   0x00000016U
487  #define TIM_DMABASE_CCR6                   0x00000017U
488  #define TIM_DMABASE_AF1                    0x00000018U
489  #define TIM_DMABASE_AF2                    0x00000019U
490  #define TIM_DMABASE_TISEL                  0x0000001AU
491  /**
492    * @}
493    */
494  
495  /** @defgroup TIM_Event_Source TIM Event Source
496    * @{
497    */
498  #define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG     /*!< Reinitialize the counter and generates an update of the registers */
499  #define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G   /*!< A capture/compare event is generated on channel 1 */
500  #define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G   /*!< A capture/compare event is generated on channel 2 */
501  #define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G   /*!< A capture/compare event is generated on channel 3 */
502  #define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G   /*!< A capture/compare event is generated on channel 4 */
503  #define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG   /*!< A commutation event is generated */
504  #define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG     /*!< A trigger event is generated */
505  #define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG     /*!< A break event is generated */
506  #define TIM_EVENTSOURCE_BREAK2              TIM_EGR_B2G    /*!< A break 2 event is generated */
507  /**
508    * @}
509    */
510  
511  /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
512    * @{
513    */
514  #define  TIM_INPUTCHANNELPOLARITY_RISING      0x00000000U                       /*!< Polarity for TIx source */
515  #define  TIM_INPUTCHANNELPOLARITY_FALLING     TIM_CCER_CC1P                     /*!< Polarity for TIx source */
516  #define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
517  /**
518    * @}
519    */
520  
521  /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
522    * @{
523    */
524  #define TIM_ETRPOLARITY_INVERTED              TIM_SMCR_ETP                      /*!< Polarity for ETR source */
525  #define TIM_ETRPOLARITY_NONINVERTED           0x00000000U                       /*!< Polarity for ETR source */
526  /**
527    * @}
528    */
529  
530  /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
531    * @{
532    */
533  #define TIM_ETRPRESCALER_DIV1                 0x00000000U                       /*!< No prescaler is used */
534  #define TIM_ETRPRESCALER_DIV2                 TIM_SMCR_ETPS_0                   /*!< ETR input source is divided by 2 */
535  #define TIM_ETRPRESCALER_DIV4                 TIM_SMCR_ETPS_1                   /*!< ETR input source is divided by 4 */
536  #define TIM_ETRPRESCALER_DIV8                 TIM_SMCR_ETPS                     /*!< ETR input source is divided by 8 */
537  /**
538    * @}
539    */
540  
541  /** @defgroup TIM_Counter_Mode TIM Counter Mode
542    * @{
543    */
544  #define TIM_COUNTERMODE_UP                 0x00000000U                          /*!< Counter used as up-counter   */
545  #define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR                          /*!< Counter used as down-counter */
546  #define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0                        /*!< Center-aligned mode 1        */
547  #define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1                        /*!< Center-aligned mode 2        */
548  #define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS                          /*!< Center-aligned mode 3        */
549  /**
550    * @}
551    */
552  
553  /** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap
554    * @{
555    */
556  #define TIM_UIFREMAP_DISABLE               0x00000000U                          /*!< Update interrupt flag remap disabled */
557  #define TIM_UIFREMAP_ENABLE                TIM_CR1_UIFREMAP                     /*!< Update interrupt flag remap enabled */
558  /**
559    * @}
560    */
561  
562  /** @defgroup TIM_ClockDivision TIM Clock Division
563    * @{
564    */
565  #define TIM_CLOCKDIVISION_DIV1             0x00000000U                          /*!< Clock division: tDTS=tCK_INT   */
566  #define TIM_CLOCKDIVISION_DIV2             TIM_CR1_CKD_0                        /*!< Clock division: tDTS=2*tCK_INT */
567  #define TIM_CLOCKDIVISION_DIV4             TIM_CR1_CKD_1                        /*!< Clock division: tDTS=4*tCK_INT */
568  /**
569    * @}
570    */
571  
572  /** @defgroup TIM_Output_Compare_State TIM Output Compare State
573    * @{
574    */
575  #define TIM_OUTPUTSTATE_DISABLE            0x00000000U                          /*!< Capture/Compare 1 output disabled */
576  #define TIM_OUTPUTSTATE_ENABLE             TIM_CCER_CC1E                        /*!< Capture/Compare 1 output enabled */
577  /**
578    * @}
579    */
580  
581  /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
582    * @{
583    */
584  #define TIM_AUTORELOAD_PRELOAD_DISABLE                0x00000000U               /*!< TIMx_ARR register is not buffered */
585  #define TIM_AUTORELOAD_PRELOAD_ENABLE                 TIM_CR1_ARPE              /*!< TIMx_ARR register is buffered */
586  
587  /**
588    * @}
589    */
590  
591  /** @defgroup TIM_Output_Fast_State TIM Output Fast State
592    * @{
593    */
594  #define TIM_OCFAST_DISABLE                 0x00000000U                          /*!< Output Compare fast disable */
595  #define TIM_OCFAST_ENABLE                  TIM_CCMR1_OC1FE                      /*!< Output Compare fast enable  */
596  /**
597    * @}
598    */
599  
600  /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
601    * @{
602    */
603  #define TIM_OUTPUTNSTATE_DISABLE           0x00000000U                          /*!< OCxN is disabled  */
604  #define TIM_OUTPUTNSTATE_ENABLE            TIM_CCER_CC1NE                       /*!< OCxN is enabled   */
605  /**
606    * @}
607    */
608  
609  /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
610    * @{
611    */
612  #define TIM_OCPOLARITY_HIGH                0x00000000U                          /*!< Capture/Compare output polarity  */
613  #define TIM_OCPOLARITY_LOW                 TIM_CCER_CC1P                        /*!< Capture/Compare output polarity  */
614  /**
615    * @}
616    */
617  
618  /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
619    * @{
620    */
621  #define TIM_OCNPOLARITY_HIGH               0x00000000U                          /*!< Capture/Compare complementary output polarity */
622  #define TIM_OCNPOLARITY_LOW                TIM_CCER_CC1NP                       /*!< Capture/Compare complementary output polarity */
623  /**
624    * @}
625    */
626  
627  /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
628    * @{
629    */
630  #define TIM_OCIDLESTATE_SET                TIM_CR2_OIS1                         /*!< Output Idle state: OCx=1 when MOE=0 */
631  #define TIM_OCIDLESTATE_RESET              0x00000000U                          /*!< Output Idle state: OCx=0 when MOE=0 */
632  /**
633    * @}
634    */
635  
636  /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
637    * @{
638    */
639  #define TIM_OCNIDLESTATE_SET               TIM_CR2_OIS1N                        /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
640  #define TIM_OCNIDLESTATE_RESET             0x00000000U                          /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
641  /**
642    * @}
643    */
644  
645  /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
646    * @{
647    */
648  #define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING      /*!< Capture triggered by rising edge on timer input                  */
649  #define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Capture triggered by falling edge on timer input                 */
650  #define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE    /*!< Capture triggered by both rising and falling edges on timer input*/
651  /**
652    * @}
653    */
654  
655  /** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
656    * @{
657    */
658  #define  TIM_ENCODERINPUTPOLARITY_RISING   TIM_INPUTCHANNELPOLARITY_RISING      /*!< Encoder input with rising edge polarity  */
659  #define  TIM_ENCODERINPUTPOLARITY_FALLING  TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Encoder input with falling edge polarity */
660  /**
661    * @}
662    */
663  
664  /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
665    * @{
666    */
667  #define TIM_ICSELECTION_DIRECTTI           TIM_CCMR1_CC1S_0                     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */
668  #define TIM_ICSELECTION_INDIRECTTI         TIM_CCMR1_CC1S_1                     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */
669  #define TIM_ICSELECTION_TRC                TIM_CCMR1_CC1S                       /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
670  /**
671    * @}
672    */
673  
674  /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
675    * @{
676    */
677  #define TIM_ICPSC_DIV1                     0x00000000U                          /*!< Capture performed each time an edge is detected on the capture input */
678  #define TIM_ICPSC_DIV2                     TIM_CCMR1_IC1PSC_0                   /*!< Capture performed once every 2 events                                */
679  #define TIM_ICPSC_DIV4                     TIM_CCMR1_IC1PSC_1                   /*!< Capture performed once every 4 events                                */
680  #define TIM_ICPSC_DIV8                     TIM_CCMR1_IC1PSC                     /*!< Capture performed once every 8 events                                */
681  /**
682    * @}
683    */
684  
685  /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
686    * @{
687    */
688  #define TIM_OPMODE_SINGLE                  TIM_CR1_OPM                          /*!< Counter stops counting at the next update event */
689  #define TIM_OPMODE_REPETITIVE              0x00000000U                          /*!< Counter is not stopped at update event          */
690  /**
691    * @}
692    */
693  
694  /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
695    * @{
696    */
697  #define TIM_ENCODERMODE_TI1                      TIM_SMCR_SMS_0                                                      /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level  */
698  #define TIM_ENCODERMODE_TI2                      TIM_SMCR_SMS_1                                                      /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
699  #define TIM_ENCODERMODE_TI12                     (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
700  /**
701    * @}
702    */
703  
704  /** @defgroup TIM_Interrupt_definition TIM interrupt Definition
705    * @{
706    */
707  #define TIM_IT_UPDATE                      TIM_DIER_UIE                         /*!< Update interrupt            */
708  #define TIM_IT_CC1                         TIM_DIER_CC1IE                       /*!< Capture/Compare 1 interrupt */
709  #define TIM_IT_CC2                         TIM_DIER_CC2IE                       /*!< Capture/Compare 2 interrupt */
710  #define TIM_IT_CC3                         TIM_DIER_CC3IE                       /*!< Capture/Compare 3 interrupt */
711  #define TIM_IT_CC4                         TIM_DIER_CC4IE                       /*!< Capture/Compare 4 interrupt */
712  #define TIM_IT_COM                         TIM_DIER_COMIE                       /*!< Commutation interrupt       */
713  #define TIM_IT_TRIGGER                     TIM_DIER_TIE                         /*!< Trigger interrupt           */
714  #define TIM_IT_BREAK                       TIM_DIER_BIE                         /*!< Break interrupt             */
715  /**
716    * @}
717    */
718  
719  /** @defgroup TIM_Commutation_Source  TIM Commutation Source
720    * @{
721    */
722  #define TIM_COMMUTATION_TRGI              TIM_CR2_CCUS                          /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
723  #define TIM_COMMUTATION_SOFTWARE          0x00000000U                           /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
724  /**
725    * @}
726    */
727  
728  /** @defgroup TIM_DMA_sources TIM DMA Sources
729    * @{
730    */
731  #define TIM_DMA_UPDATE                     TIM_DIER_UDE                         /*!< DMA request is triggered by the update event */
732  #define TIM_DMA_CC1                        TIM_DIER_CC1DE                       /*!< DMA request is triggered by the capture/compare macth 1 event */
733  #define TIM_DMA_CC2                        TIM_DIER_CC2DE                       /*!< DMA request is triggered by the capture/compare macth 2 event event */
734  #define TIM_DMA_CC3                        TIM_DIER_CC3DE                       /*!< DMA request is triggered by the capture/compare macth 3 event event */
735  #define TIM_DMA_CC4                        TIM_DIER_CC4DE                       /*!< DMA request is triggered by the capture/compare macth 4 event event */
736  #define TIM_DMA_COM                        TIM_DIER_COMDE                       /*!< DMA request is triggered by the commutation event */
737  #define TIM_DMA_TRIGGER                    TIM_DIER_TDE                         /*!< DMA request is triggered by the trigger event */
738  /**
739    * @}
740    */
741  
742  /** @defgroup TIM_CC_DMA_Request CCx DMA request selection
743    * @{
744    */
745  #define TIM_CCDMAREQUEST_CC                 0x00000000U                         /*!< CCx DMA request sent when capture or compare match event occurs */
746  #define TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS                        /*!< CCx DMA requests sent when update event occurs */
747  /**
748    * @}
749    */
750  
751  /** @defgroup TIM_Flag_definition TIM Flag Definition
752    * @{
753    */
754  #define TIM_FLAG_UPDATE                    TIM_SR_UIF                           /*!< Update interrupt flag         */
755  #define TIM_FLAG_CC1                       TIM_SR_CC1IF                         /*!< Capture/Compare 1 interrupt flag */
756  #define TIM_FLAG_CC2                       TIM_SR_CC2IF                         /*!< Capture/Compare 2 interrupt flag */
757  #define TIM_FLAG_CC3                       TIM_SR_CC3IF                         /*!< Capture/Compare 3 interrupt flag */
758  #define TIM_FLAG_CC4                       TIM_SR_CC4IF                         /*!< Capture/Compare 4 interrupt flag */
759  #define TIM_FLAG_CC5                       TIM_SR_CC5IF                         /*!< Capture/Compare 5 interrupt flag */
760  #define TIM_FLAG_CC6                       TIM_SR_CC6IF                         /*!< Capture/Compare 6 interrupt flag */
761  #define TIM_FLAG_COM                       TIM_SR_COMIF                         /*!< Commutation interrupt flag    */
762  #define TIM_FLAG_TRIGGER                   TIM_SR_TIF                           /*!< Trigger interrupt flag        */
763  #define TIM_FLAG_BREAK                     TIM_SR_BIF                           /*!< Break interrupt flag          */
764  #define TIM_FLAG_BREAK2                    TIM_SR_B2IF                          /*!< Break 2 interrupt flag        */
765  #define TIM_FLAG_SYSTEM_BREAK              TIM_SR_SBIF                          /*!< System Break interrupt flag   */
766  #define TIM_FLAG_CC1OF                     TIM_SR_CC1OF                         /*!< Capture 1 overcapture flag    */
767  #define TIM_FLAG_CC2OF                     TIM_SR_CC2OF                         /*!< Capture 2 overcapture flag    */
768  #define TIM_FLAG_CC3OF                     TIM_SR_CC3OF                         /*!< Capture 3 overcapture flag    */
769  #define TIM_FLAG_CC4OF                     TIM_SR_CC4OF                         /*!< Capture 4 overcapture flag    */
770  /**
771    * @}
772    */
773  
774  /** @defgroup TIM_Channel TIM Channel
775    * @{
776    */
777  #define TIM_CHANNEL_1                      0x00000000U                          /*!< Capture/compare channel 1 identifier      */
778  #define TIM_CHANNEL_2                      0x00000004U                          /*!< Capture/compare channel 2 identifier      */
779  #define TIM_CHANNEL_3                      0x00000008U                          /*!< Capture/compare channel 3 identifier      */
780  #define TIM_CHANNEL_4                      0x0000000CU                          /*!< Capture/compare channel 4 identifier      */
781  #define TIM_CHANNEL_5                      0x00000010U                          /*!< Compare channel 5 identifier              */
782  #define TIM_CHANNEL_6                      0x00000014U                          /*!< Compare channel 6 identifier              */
783  #define TIM_CHANNEL_ALL                    0x0000003CU                          /*!< Global Capture/compare channel identifier  */
784  /**
785    * @}
786    */
787  
788  /** @defgroup TIM_Clock_Source TIM Clock Source
789    * @{
790    */
791  #define TIM_CLOCKSOURCE_INTERNAL    TIM_SMCR_ETPS_0      /*!< Internal clock source                                 */
792  #define TIM_CLOCKSOURCE_ETRMODE1    TIM_TS_ETRF          /*!< External clock source mode 1 (ETRF)                   */
793  #define TIM_CLOCKSOURCE_ETRMODE2    TIM_SMCR_ETPS_1      /*!< External clock source mode 2                          */
794  #define TIM_CLOCKSOURCE_TI1ED       TIM_TS_TI1F_ED       /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
795  #define TIM_CLOCKSOURCE_TI1         TIM_TS_TI1FP1        /*!< External clock source mode 1 (TTI1FP1)                */
796  #define TIM_CLOCKSOURCE_TI2         TIM_TS_TI2FP2        /*!< External clock source mode 1 (TTI2FP2)                */
797  #define TIM_CLOCKSOURCE_ITR0        TIM_TS_ITR0          /*!< External clock source mode 1 (ITR0)                   */
798  #define TIM_CLOCKSOURCE_ITR1        TIM_TS_ITR1          /*!< External clock source mode 1 (ITR1)                   */
799  #define TIM_CLOCKSOURCE_ITR2        TIM_TS_ITR2          /*!< External clock source mode 1 (ITR2)                   */
800  #define TIM_CLOCKSOURCE_ITR3        TIM_TS_ITR3          /*!< External clock source mode 1 (ITR3)                   */
801  #if defined(USB_BASE)
802  #define TIM_CLOCKSOURCE_ITR7        TIM_TS_ITR7          /*!< External clock source mode 1 (ITR7)                   */
803  #endif /* USB_BASE */
804  /**
805    * @}
806    */
807  
808  /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
809    * @{
810    */
811  #define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED           /*!< Polarity for ETRx clock sources */
812  #define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED        /*!< Polarity for ETRx clock sources */
813  #define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING    /*!< Polarity for TIx clock sources */
814  #define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
815  #define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
816  /**
817    * @}
818    */
819  
820  /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
821    * @{
822    */
823  #define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1           /*!< No prescaler is used                                                     */
824  #define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2           /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
825  #define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4           /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
826  #define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8           /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
827  /**
828    * @}
829    */
830  
831  /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
832    * @{
833    */
834  #define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx pin */
835  #define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx pin */
836  /**
837    * @}
838    */
839  
840  /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
841    * @{
842    */
843  #define TIM_CLEARINPUTPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1         /*!< No prescaler is used                                                   */
844  #define TIM_CLEARINPUTPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2         /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
845  #define TIM_CLEARINPUTPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4         /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
846  #define TIM_CLEARINPUTPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8         /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
847  /**
848    * @}
849    */
850  
851  /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
852    * @{
853    */
854  #define TIM_OSSR_ENABLE                          TIM_BDTR_OSSR                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
855  #define TIM_OSSR_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
856  /**
857    * @}
858    */
859  
860  /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
861    * @{
862    */
863  #define TIM_OSSI_ENABLE                          TIM_BDTR_OSSI                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
864  #define TIM_OSSI_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
865  /**
866    * @}
867    */
868  /** @defgroup TIM_Lock_level  TIM Lock level
869    * @{
870    */
871  #define TIM_LOCKLEVEL_OFF                  0x00000000U                          /*!< LOCK OFF     */
872  #define TIM_LOCKLEVEL_1                    TIM_BDTR_LOCK_0                      /*!< LOCK Level 1 */
873  #define TIM_LOCKLEVEL_2                    TIM_BDTR_LOCK_1                      /*!< LOCK Level 2 */
874  #define TIM_LOCKLEVEL_3                    TIM_BDTR_LOCK                        /*!< LOCK Level 3 */
875  /**
876    * @}
877    */
878  
879  /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
880    * @{
881    */
882  #define TIM_BREAK_ENABLE                   TIM_BDTR_BKE                         /*!< Break input BRK is enabled  */
883  #define TIM_BREAK_DISABLE                  0x00000000U                          /*!< Break input BRK is disabled */
884  /**
885    * @}
886    */
887  
888  /** @defgroup TIM_Break_Polarity TIM Break Input Polarity
889    * @{
890    */
891  #define TIM_BREAKPOLARITY_LOW              0x00000000U                          /*!< Break input BRK is active low  */
892  #define TIM_BREAKPOLARITY_HIGH             TIM_BDTR_BKP                         /*!< Break input BRK is active high */
893  /**
894    * @}
895    */
896  
897  /** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode
898    * @{
899    */
900  #define TIM_BREAK_AFMODE_INPUT             0x00000000U                          /*!< Break input BRK in input mode */
901  #define TIM_BREAK_AFMODE_BIDIRECTIONAL     TIM_BDTR_BKBID                       /*!< Break input BRK in bidirectional mode */
902  /**
903    * @}
904    */
905  
906  /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
907    * @{
908    */
909  #define TIM_BREAK2_DISABLE                 0x00000000U                          /*!< Break input BRK2 is disabled  */
910  #define TIM_BREAK2_ENABLE                  TIM_BDTR_BK2E                        /*!< Break input BRK2 is enabled  */
911  /**
912    * @}
913    */
914  
915  /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
916    * @{
917    */
918  #define TIM_BREAK2POLARITY_LOW             0x00000000U                          /*!< Break input BRK2 is active low   */
919  #define TIM_BREAK2POLARITY_HIGH            TIM_BDTR_BK2P                        /*!< Break input BRK2 is active high  */
920  /**
921    * @}
922    */
923  
924  /** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode
925    * @{
926    */
927  #define TIM_BREAK2_AFMODE_INPUT            0x00000000U                          /*!< Break2 input BRK2 in input mode */
928  #define TIM_BREAK2_AFMODE_BIDIRECTIONAL    TIM_BDTR_BK2BID                      /*!< Break2 input BRK2 in bidirectional mode */
929  /**
930    * @}
931    */
932  
933  /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
934    * @{
935    */
936  #define TIM_AUTOMATICOUTPUT_DISABLE        0x00000000U                          /*!< MOE can be set only by software */
937  #define TIM_AUTOMATICOUTPUT_ENABLE         TIM_BDTR_AOE                         /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */
938  /**
939    * @}
940    */
941  
942  /** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3
943    * @{
944    */
945  #define TIM_GROUPCH5_NONE                  0x00000000U                          /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
946  #define TIM_GROUPCH5_OC1REFC               TIM_CCR5_GC5C1                       /*!< OC1REFC is the logical AND of OC1REFC and OC5REF    */
947  #define TIM_GROUPCH5_OC2REFC               TIM_CCR5_GC5C2                       /*!< OC2REFC is the logical AND of OC2REFC and OC5REF    */
948  #define TIM_GROUPCH5_OC3REFC               TIM_CCR5_GC5C3                       /*!< OC3REFC is the logical AND of OC3REFC and OC5REF    */
949  /**
950    * @}
951    */
952  
953  /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
954    * @{
955    */
956  #define TIM_TRGO_RESET            0x00000000U                                      /*!< TIMx_EGR.UG bit is used as trigger output (TRGO)              */
957  #define TIM_TRGO_ENABLE           TIM_CR2_MMS_0                                    /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO)             */
958  #define TIM_TRGO_UPDATE           TIM_CR2_MMS_1                                    /*!< Update event is used as trigger output (TRGO)                 */
959  #define TIM_TRGO_OC1              (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                  /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
960  #define TIM_TRGO_OC1REF           TIM_CR2_MMS_2                                    /*!< OC1REF signal is used as trigger output (TRGO)                */
961  #define TIM_TRGO_OC2REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                  /*!< OC2REF signal is used as trigger output(TRGO)                 */
962  #define TIM_TRGO_OC3REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                  /*!< OC3REF signal is used as trigger output(TRGO)                 */
963  #define TIM_TRGO_OC4REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)  /*!< OC4REF signal is used as trigger output(TRGO)                 */
964  /**
965    * @}
966    */
967  
968  /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
969    * @{
970    */
971  #define TIM_TRGO2_RESET                          0x00000000U                                                         /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2)              */
972  #define TIM_TRGO2_ENABLE                         TIM_CR2_MMS2_0                                                      /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2)             */
973  #define TIM_TRGO2_UPDATE                         TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output (TRGO2)                 */
974  #define TIM_TRGO2_OC1                            (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */
975  #define TIM_TRGO2_OC1REF                         TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output (TRGO2)                */
976  #define TIM_TRGO2_OC2REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output (TRGO2)                */
977  #define TIM_TRGO2_OC3REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output (TRGO2)                */
978  #define TIM_TRGO2_OC4REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output (TRGO2)                */
979  #define TIM_TRGO2_OC5REF                         TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output (TRGO2)                */
980  #define TIM_TRGO2_OC6REF                         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output (TRGO2)                */
981  #define TIM_TRGO2_OC4REF_RISINGFALLING           (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges generate pulses on TRGO2        */
982  #define TIM_TRGO2_OC6REF_RISINGFALLING           (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges generate pulses on TRGO2        */
983  #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2         */
984  #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING   (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */
985  #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2         */
986  #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING   (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2         */
987  /**
988    * @}
989    */
990  
991  /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
992    * @{
993    */
994  #define TIM_MASTERSLAVEMODE_ENABLE         TIM_SMCR_MSM                         /*!< No action */
995  #define TIM_MASTERSLAVEMODE_DISABLE        0x00000000U                          /*!< Master/slave mode is selected */
996  /**
997    * @}
998    */
999  
1000  /** @defgroup TIM_Slave_Mode TIM Slave mode
1001    * @{
1002    */
1003  #define TIM_SLAVEMODE_DISABLE                0x00000000U                                        /*!< Slave mode disabled           */
1004  #define TIM_SLAVEMODE_RESET                  TIM_SMCR_SMS_2                                     /*!< Reset Mode                    */
1005  #define TIM_SLAVEMODE_GATED                  (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)                  /*!< Gated Mode                    */
1006  #define TIM_SLAVEMODE_TRIGGER                (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)                  /*!< Trigger Mode                  */
1007  #define TIM_SLAVEMODE_EXTERNAL1              (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1         */
1008  #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER  TIM_SMCR_SMS_3                                     /*!< Combined reset + trigger mode */
1009  /**
1010    * @}
1011    */
1012  
1013  /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
1014    * @{
1015    */
1016  #define TIM_OCMODE_TIMING                   0x00000000U                                              /*!< Frozen                                 */
1017  #define TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!< Set channel to active level on match   */
1018  #define TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!< Set channel to inactive level on match */
1019  #define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!< Toggle                                 */
1020  #define TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!< PWM mode 1                             */
1021  #define TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2                             */
1022  #define TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!< Force active level                     */
1023  #define TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!< Force inactive level                   */
1024  #define TIM_OCMODE_RETRIGERRABLE_OPM1      TIM_CCMR1_OC1M_3                                          /*!< Retrigerrable OPM mode 1               */
1025  #define TIM_OCMODE_RETRIGERRABLE_OPM2      (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                     /*!< Retrigerrable OPM mode 2               */
1026  #define TIM_OCMODE_COMBINED_PWM1           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                     /*!< Combined PWM mode 1                    */
1027  #define TIM_OCMODE_COMBINED_PWM2           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)  /*!< Combined PWM mode 2                    */
1028  #define TIM_OCMODE_ASSYMETRIC_PWM1         (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)  /*!< Asymmetric PWM mode 1                  */
1029  #define TIM_OCMODE_ASSYMETRIC_PWM2         TIM_CCMR1_OC1M                                            /*!< Asymmetric PWM mode 2                  */
1030  /**
1031    * @}
1032    */
1033  
1034  /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
1035    * @{
1036    */
1037  #define TIM_TS_ITR0          0x00000000U                                                       /*!< Internal Trigger 0 (ITR0)              */
1038  #define TIM_TS_ITR1          TIM_SMCR_TS_0                                                     /*!< Internal Trigger 1 (ITR1)              */
1039  #define TIM_TS_ITR2          TIM_SMCR_TS_1                                                     /*!< Internal Trigger 2 (ITR2)              */
1040  #define TIM_TS_ITR3          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                   /*!< Internal Trigger 3 (ITR3)              */
1041  #if defined(USB_BASE)
1042  #define TIM_TS_ITR7          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 7 (ITR7)              */
1043  #endif /* USB_BASE */
1044  #define TIM_TS_TI1F_ED       TIM_SMCR_TS_2                                                     /*!< TI1 Edge Detector (TI1F_ED)            */
1045  #define TIM_TS_TI1FP1        (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 1 (TI1FP1)        */
1046  #define TIM_TS_TI2FP2        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 2 (TI2FP2)        */
1047  #define TIM_TS_ETRF          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                   /*!< Filtered External Trigger input (ETRF) */
1048  #define TIM_TS_NONE          0x0000FFFFU                                                       /*!< No trigger selected                    */
1049  /**
1050    * @}
1051    */
1052  
1053  /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
1054    * @{
1055    */
1056  #define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED               /*!< Polarity for ETRx trigger sources             */
1057  #define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED            /*!< Polarity for ETRx trigger sources             */
1058  #define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */
1059  #define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */
1060  #define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */
1061  /**
1062    * @}
1063    */
1064  
1065  /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
1066    * @{
1067    */
1068  #define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1             /*!< No prescaler is used                                                       */
1069  #define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2             /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
1070  #define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4             /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
1071  #define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8             /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
1072  /**
1073    * @}
1074    */
1075  
1076  /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
1077    * @{
1078    */
1079  #define TIM_TI1SELECTION_CH1               0x00000000U                          /*!< The TIMx_CH1 pin is connected to TI1 input */
1080  #define TIM_TI1SELECTION_XORCOMBINATION    TIM_CR2_TI1S                         /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
1081  /**
1082    * @}
1083    */
1084  
1085  /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
1086    * @{
1087    */
1088  #define TIM_DMABURSTLENGTH_1TRANSFER       0x00000000U                          /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA   */
1089  #define TIM_DMABURSTLENGTH_2TRANSFERS      0x00000100U                          /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
1090  #define TIM_DMABURSTLENGTH_3TRANSFERS      0x00000200U                          /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
1091  #define TIM_DMABURSTLENGTH_4TRANSFERS      0x00000300U                          /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
1092  #define TIM_DMABURSTLENGTH_5TRANSFERS      0x00000400U                          /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
1093  #define TIM_DMABURSTLENGTH_6TRANSFERS      0x00000500U                          /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
1094  #define TIM_DMABURSTLENGTH_7TRANSFERS      0x00000600U                          /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
1095  #define TIM_DMABURSTLENGTH_8TRANSFERS      0x00000700U                          /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
1096  #define TIM_DMABURSTLENGTH_9TRANSFERS      0x00000800U                          /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
1097  #define TIM_DMABURSTLENGTH_10TRANSFERS     0x00000900U                          /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1098  #define TIM_DMABURSTLENGTH_11TRANSFERS     0x00000A00U                          /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1099  #define TIM_DMABURSTLENGTH_12TRANSFERS     0x00000B00U                          /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1100  #define TIM_DMABURSTLENGTH_13TRANSFERS     0x00000C00U                          /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1101  #define TIM_DMABURSTLENGTH_14TRANSFERS     0x00000D00U                          /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1102  #define TIM_DMABURSTLENGTH_15TRANSFERS     0x00000E00U                          /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1103  #define TIM_DMABURSTLENGTH_16TRANSFERS     0x00000F00U                          /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1104  #define TIM_DMABURSTLENGTH_17TRANSFERS     0x00001000U                          /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1105  #define TIM_DMABURSTLENGTH_18TRANSFERS     0x00001100U                          /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1106  /**
1107    * @}
1108    */
1109  
1110  /** @defgroup DMA_Handle_index TIM DMA Handle Index
1111    * @{
1112    */
1113  #define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0000)       /*!< Index of the DMA handle used for Update DMA requests */
1114  #define TIM_DMA_ID_CC1                   ((uint16_t) 0x0001)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
1115  #define TIM_DMA_ID_CC2                   ((uint16_t) 0x0002)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
1116  #define TIM_DMA_ID_CC3                   ((uint16_t) 0x0003)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
1117  #define TIM_DMA_ID_CC4                   ((uint16_t) 0x0004)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
1118  #define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x0005)       /*!< Index of the DMA handle used for Commutation DMA requests */
1119  #define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x0006)       /*!< Index of the DMA handle used for Trigger DMA requests */
1120  /**
1121    * @}
1122    */
1123  
1124  /** @defgroup Channel_CC_State TIM Capture/Compare Channel State
1125    * @{
1126    */
1127  #define TIM_CCx_ENABLE                   0x00000001U                            /*!< Input or output channel is enabled */
1128  #define TIM_CCx_DISABLE                  0x00000000U                            /*!< Input or output channel is disabled */
1129  #define TIM_CCxN_ENABLE                  0x00000004U                            /*!< Complementary output channel is enabled */
1130  #define TIM_CCxN_DISABLE                 0x00000000U                            /*!< Complementary output channel is enabled */
1131  /**
1132    * @}
1133    */
1134  
1135  /** @defgroup TIM_Break_System TIM Break System
1136    * @{
1137    */
1138  #define TIM_BREAK_SYSTEM_ECC                 SYSCFG_CFGR2_ECCL   /*!< Enables and locks the ECC error signal with Break Input of TIM1/15/16/17 */
1139  #define TIM_BREAK_SYSTEM_PVD                 SYSCFG_CFGR2_PVDL   /*!< Enables and locks the PVD connection with TIM1/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */
1140  #define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR   SYSCFG_CFGR2_SPL    /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/15/16/17 */
1141  #define TIM_BREAK_SYSTEM_LOCKUP              SYSCFG_CFGR2_CLL    /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/15/16/17 */
1142  /**
1143    * @}
1144    */
1145  
1146  /**
1147    * @}
1148    */
1149  /* End of exported constants -------------------------------------------------*/
1150  
1151  /* Exported macros -----------------------------------------------------------*/
1152  /** @defgroup TIM_Exported_Macros TIM Exported Macros
1153    * @{
1154    */
1155  
1156  /** @brief  Reset TIM handle state.
1157    * @param  __HANDLE__ TIM handle.
1158    * @retval None
1159    */
1160  #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1161  #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                               \
1162                                                        (__HANDLE__)->State            = HAL_TIM_STATE_RESET;         \
1163                                                        (__HANDLE__)->ChannelState[0]  = HAL_TIM_CHANNEL_STATE_RESET; \
1164                                                        (__HANDLE__)->ChannelState[1]  = HAL_TIM_CHANNEL_STATE_RESET; \
1165                                                        (__HANDLE__)->ChannelState[2]  = HAL_TIM_CHANNEL_STATE_RESET; \
1166                                                        (__HANDLE__)->ChannelState[3]  = HAL_TIM_CHANNEL_STATE_RESET; \
1167                                                        (__HANDLE__)->ChannelState[4]  = HAL_TIM_CHANNEL_STATE_RESET; \
1168                                                        (__HANDLE__)->ChannelState[5]  = HAL_TIM_CHANNEL_STATE_RESET; \
1169                                                        (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
1170                                                        (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
1171                                                        (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
1172                                                        (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
1173                                                        (__HANDLE__)->DMABurstState    = HAL_DMA_BURST_STATE_RESET;   \
1174                                                        (__HANDLE__)->Base_MspInitCallback         = NULL;            \
1175                                                        (__HANDLE__)->Base_MspDeInitCallback       = NULL;            \
1176                                                        (__HANDLE__)->IC_MspInitCallback           = NULL;            \
1177                                                        (__HANDLE__)->IC_MspDeInitCallback         = NULL;            \
1178                                                        (__HANDLE__)->OC_MspInitCallback           = NULL;            \
1179                                                        (__HANDLE__)->OC_MspDeInitCallback         = NULL;            \
1180                                                        (__HANDLE__)->PWM_MspInitCallback          = NULL;            \
1181                                                        (__HANDLE__)->PWM_MspDeInitCallback        = NULL;            \
1182                                                        (__HANDLE__)->OnePulse_MspInitCallback     = NULL;            \
1183                                                        (__HANDLE__)->OnePulse_MspDeInitCallback   = NULL;            \
1184                                                        (__HANDLE__)->Encoder_MspInitCallback      = NULL;            \
1185                                                        (__HANDLE__)->Encoder_MspDeInitCallback    = NULL;            \
1186                                                        (__HANDLE__)->HallSensor_MspInitCallback   = NULL;            \
1187                                                        (__HANDLE__)->HallSensor_MspDeInitCallback = NULL;            \
1188                                                       } while(0)
1189  #else
1190  #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                               \
1191                                                        (__HANDLE__)->State            = HAL_TIM_STATE_RESET;         \
1192                                                        (__HANDLE__)->ChannelState[0]  = HAL_TIM_CHANNEL_STATE_RESET; \
1193                                                        (__HANDLE__)->ChannelState[1]  = HAL_TIM_CHANNEL_STATE_RESET; \
1194                                                        (__HANDLE__)->ChannelState[2]  = HAL_TIM_CHANNEL_STATE_RESET; \
1195                                                        (__HANDLE__)->ChannelState[3]  = HAL_TIM_CHANNEL_STATE_RESET; \
1196                                                        (__HANDLE__)->ChannelState[4]  = HAL_TIM_CHANNEL_STATE_RESET; \
1197                                                        (__HANDLE__)->ChannelState[5]  = HAL_TIM_CHANNEL_STATE_RESET; \
1198                                                        (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
1199                                                        (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
1200                                                        (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
1201                                                        (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
1202                                                        (__HANDLE__)->DMABurstState    = HAL_DMA_BURST_STATE_RESET;   \
1203                                                       } while(0)
1204  #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1205  
1206  /**
1207    * @brief  Enable the TIM peripheral.
1208    * @param  __HANDLE__ TIM handle
1209    * @retval None
1210    */
1211  #define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
1212  
1213  /**
1214    * @brief  Enable the TIM main Output.
1215    * @param  __HANDLE__ TIM handle
1216    * @retval None
1217    */
1218  #define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
1219  
1220  /**
1221    * @brief  Disable the TIM peripheral.
1222    * @param  __HANDLE__ TIM handle
1223    * @retval None
1224    */
1225  #define __HAL_TIM_DISABLE(__HANDLE__) \
1226    do { \
1227      if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
1228      { \
1229        if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
1230        { \
1231          (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
1232        } \
1233      } \
1234    } while(0)
1235  
1236  /**
1237    * @brief  Disable the TIM main Output.
1238    * @param  __HANDLE__ TIM handle
1239    * @retval None
1240    * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been
1241    *       disabled
1242    */
1243  #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
1244    do { \
1245      if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
1246      { \
1247        if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
1248        { \
1249          (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
1250        } \
1251      } \
1252    } while(0)
1253  
1254  /**
1255    * @brief  Disable the TIM main Output.
1256    * @param  __HANDLE__ TIM handle
1257    * @retval None
1258    * @note The Main Output Enable of a timer instance is disabled unconditionally
1259    */
1260  #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__)  (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
1261  
1262  /** @brief  Enable the specified TIM interrupt.
1263    * @param  __HANDLE__ specifies the TIM Handle.
1264    * @param  __INTERRUPT__ specifies the TIM interrupt source to enable.
1265    *          This parameter can be one of the following values:
1266    *            @arg TIM_IT_UPDATE: Update interrupt
1267    *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
1268    *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
1269    *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
1270    *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
1271    *            @arg TIM_IT_COM:   Commutation interrupt
1272    *            @arg TIM_IT_TRIGGER: Trigger interrupt
1273    *            @arg TIM_IT_BREAK: Break interrupt
1274    * @retval None
1275    */
1276  #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
1277  
1278  /** @brief  Disable the specified TIM interrupt.
1279    * @param  __HANDLE__ specifies the TIM Handle.
1280    * @param  __INTERRUPT__ specifies the TIM interrupt source to disable.
1281    *          This parameter can be one of the following values:
1282    *            @arg TIM_IT_UPDATE: Update interrupt
1283    *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
1284    *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
1285    *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
1286    *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
1287    *            @arg TIM_IT_COM:   Commutation interrupt
1288    *            @arg TIM_IT_TRIGGER: Trigger interrupt
1289    *            @arg TIM_IT_BREAK: Break interrupt
1290    * @retval None
1291    */
1292  #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
1293  
1294  /** @brief  Enable the specified DMA request.
1295    * @param  __HANDLE__ specifies the TIM Handle.
1296    * @param  __DMA__ specifies the TIM DMA request to enable.
1297    *          This parameter can be one of the following values:
1298    *            @arg TIM_DMA_UPDATE: Update DMA request
1299    *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
1300    *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
1301    *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
1302    *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
1303    *            @arg TIM_DMA_COM:   Commutation DMA request
1304    *            @arg TIM_DMA_TRIGGER: Trigger DMA request
1305    * @retval None
1306    */
1307  #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
1308  
1309  /** @brief  Disable the specified DMA request.
1310    * @param  __HANDLE__ specifies the TIM Handle.
1311    * @param  __DMA__ specifies the TIM DMA request to disable.
1312    *          This parameter can be one of the following values:
1313    *            @arg TIM_DMA_UPDATE: Update DMA request
1314    *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
1315    *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
1316    *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
1317    *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
1318    *            @arg TIM_DMA_COM:   Commutation DMA request
1319    *            @arg TIM_DMA_TRIGGER: Trigger DMA request
1320    * @retval None
1321    */
1322  #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
1323  
1324  /** @brief  Check whether the specified TIM interrupt flag is set or not.
1325    * @param  __HANDLE__ specifies the TIM Handle.
1326    * @param  __FLAG__ specifies the TIM interrupt flag to check.
1327    *        This parameter can be one of the following values:
1328    *            @arg TIM_FLAG_UPDATE: Update interrupt flag
1329    *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
1330    *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
1331    *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
1332    *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
1333    *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
1334    *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag
1335    *            @arg TIM_FLAG_COM:  Commutation interrupt flag
1336    *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
1337    *            @arg TIM_FLAG_BREAK: Break interrupt flag
1338    *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
1339    *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
1340    *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
1341    *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
1342    *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
1343    *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
1344    * @retval The new state of __FLAG__ (TRUE or FALSE).
1345    */
1346  #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
1347  
1348  /** @brief  Clear the specified TIM interrupt flag.
1349    * @param  __HANDLE__ specifies the TIM Handle.
1350    * @param  __FLAG__ specifies the TIM interrupt flag to clear.
1351    *        This parameter can be one of the following values:
1352    *            @arg TIM_FLAG_UPDATE: Update interrupt flag
1353    *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
1354    *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
1355    *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
1356    *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
1357    *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
1358    *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag
1359    *            @arg TIM_FLAG_COM:  Commutation interrupt flag
1360    *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
1361    *            @arg TIM_FLAG_BREAK: Break interrupt flag
1362    *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
1363    *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
1364    *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
1365    *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
1366    *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
1367    *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
1368    * @retval The new state of __FLAG__ (TRUE or FALSE).
1369    */
1370  #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
1371  
1372  /**
1373    * @brief  Check whether the specified TIM interrupt source is enabled or not.
1374    * @param  __HANDLE__ TIM handle
1375    * @param  __INTERRUPT__ specifies the TIM interrupt source to check.
1376    *          This parameter can be one of the following values:
1377    *            @arg TIM_IT_UPDATE: Update interrupt
1378    *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
1379    *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
1380    *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
1381    *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
1382    *            @arg TIM_IT_COM:   Commutation interrupt
1383    *            @arg TIM_IT_TRIGGER: Trigger interrupt
1384    *            @arg TIM_IT_BREAK: Break interrupt
1385    * @retval The state of TIM_IT (SET or RESET).
1386    */
1387  #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
1388                                                               == (__INTERRUPT__)) ? SET : RESET)
1389  
1390  /** @brief Clear the TIM interrupt pending bits.
1391    * @param  __HANDLE__ TIM handle
1392    * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
1393    *          This parameter can be one of the following values:
1394    *            @arg TIM_IT_UPDATE: Update interrupt
1395    *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
1396    *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
1397    *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
1398    *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
1399    *            @arg TIM_IT_COM:   Commutation interrupt
1400    *            @arg TIM_IT_TRIGGER: Trigger interrupt
1401    *            @arg TIM_IT_BREAK: Break interrupt
1402    * @retval None
1403    */
1404  #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
1405  
1406  /**
1407    * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
1408    * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
1409    *       in an atomic way.
1410    * @param  __HANDLE__ TIM handle.
1411    * @retval None
1412  mode.
1413    */
1414  #define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__)    (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))
1415  
1416  /**
1417    * @brief  Disable update interrupt flag (UIF) remapping.
1418    * @param  __HANDLE__ TIM handle.
1419    * @retval None
1420  mode.
1421    */
1422  #define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
1423  
1424  /**
1425    * @brief  Get update interrupt flag (UIF) copy status.
1426    * @param  __COUNTER__ Counter value.
1427    * @retval The state of UIFCPY (TRUE or FALSE).
1428  mode.
1429    */
1430  #define __HAL_TIM_GET_UIFCPY(__COUNTER__)    (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
1431  
1432  /**
1433    * @brief  Indicates whether or not the TIM Counter is used as downcounter.
1434    * @param  __HANDLE__ TIM handle.
1435    * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
1436    * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode
1437    *       or Encoder mode.
1438    */
1439  #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
1440  
1441  /**
1442    * @brief  Set the TIM Prescaler on runtime.
1443    * @param  __HANDLE__ TIM handle.
1444    * @param  __PRESC__ specifies the Prescaler new value.
1445    * @retval None
1446    */
1447  #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
1448  
1449  /**
1450    * @brief  Set the TIM Counter Register value on runtime.
1451    * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in
1452    *      case of 32 bits counter TIM instance.
1453    *      Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.
1454    * @param  __HANDLE__ TIM handle.
1455    * @param  __COUNTER__ specifies the Counter register new value.
1456    * @retval None
1457    */
1458  #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))
1459  
1460  /**
1461    * @brief  Get the TIM Counter Register value on runtime.
1462    * @param  __HANDLE__ TIM handle.
1463    * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
1464    */
1465  #define __HAL_TIM_GET_COUNTER(__HANDLE__)  ((__HANDLE__)->Instance->CNT)
1466  
1467  /**
1468    * @brief  Set the TIM Autoreload Register value on runtime without calling another time any Init function.
1469    * @param  __HANDLE__ TIM handle.
1470    * @param  __AUTORELOAD__ specifies the Counter register new value.
1471    * @retval None
1472    */
1473  #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
1474    do{                                                    \
1475      (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
1476      (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
1477    } while(0)
1478  
1479  /**
1480    * @brief  Get the TIM Autoreload Register value on runtime.
1481    * @param  __HANDLE__ TIM handle.
1482    * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
1483    */
1484  #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__)  ((__HANDLE__)->Instance->ARR)
1485  
1486  /**
1487    * @brief  Set the TIM Clock Division value on runtime without calling another time any Init function.
1488    * @param  __HANDLE__ TIM handle.
1489    * @param  __CKD__ specifies the clock division value.
1490    *          This parameter can be one of the following value:
1491    *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
1492    *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
1493    *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
1494    * @retval None
1495    */
1496  #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
1497    do{                                                   \
1498      (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD);  \
1499      (__HANDLE__)->Instance->CR1 |= (__CKD__);       \
1500      (__HANDLE__)->Init.ClockDivision = (__CKD__);   \
1501    } while(0)
1502  
1503  /**
1504    * @brief  Get the TIM Clock Division value on runtime.
1505    * @param  __HANDLE__ TIM handle.
1506    * @retval The clock division can be one of the following values:
1507    *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
1508    *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
1509    *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
1510    */
1511  #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
1512  
1513  /**
1514    * @brief  Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel()
1515    *         function.
1516    * @param  __HANDLE__ TIM handle.
1517    * @param  __CHANNEL__ TIM Channels to be configured.
1518    *          This parameter can be one of the following values:
1519    *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1520    *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1521    *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1522    *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1523    * @param  __ICPSC__ specifies the Input Capture4 prescaler new value.
1524    *          This parameter can be one of the following values:
1525    *            @arg TIM_ICPSC_DIV1: no prescaler
1526    *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1527    *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1528    *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1529    * @retval None
1530    */
1531  #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
1532    do{                                                    \
1533      TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
1534      TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
1535    } while(0)
1536  
1537  /**
1538    * @brief  Get the TIM Input Capture prescaler on runtime.
1539    * @param  __HANDLE__ TIM handle.
1540    * @param  __CHANNEL__ TIM Channels to be configured.
1541    *          This parameter can be one of the following values:
1542    *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
1543    *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
1544    *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
1545    *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
1546    * @retval The input capture prescaler can be one of the following values:
1547    *            @arg TIM_ICPSC_DIV1: no prescaler
1548    *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1549    *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1550    *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1551    */
1552  #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
1553    (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
1554     ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
1555     ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
1556     (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
1557  
1558  /**
1559    * @brief  Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
1560    * @param  __HANDLE__ TIM handle.
1561    * @param  __CHANNEL__ TIM Channels to be configured.
1562    *          This parameter can be one of the following values:
1563    *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1564    *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1565    *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1566    *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1567    *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
1568    *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
1569    * @param  __COMPARE__ specifies the Capture Compare register new value.
1570    * @retval None
1571    */
1572  #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
1573    (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
1574     ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
1575     ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
1576     ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
1577     ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
1578     ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
1579  
1580  /**
1581    * @brief  Get the TIM Capture Compare Register value on runtime.
1582    * @param  __HANDLE__ TIM handle.
1583    * @param  __CHANNEL__ TIM Channel associated with the capture compare register
1584    *          This parameter can be one of the following values:
1585    *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
1586    *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
1587    *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
1588    *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
1589    *            @arg TIM_CHANNEL_5: get capture/compare 5 register value
1590    *            @arg TIM_CHANNEL_6: get capture/compare 6 register value
1591    * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
1592    */
1593  #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
1594    (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
1595     ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
1596     ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
1597     ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
1598     ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
1599     ((__HANDLE__)->Instance->CCR6))
1600  
1601  /**
1602    * @brief  Set the TIM Output compare preload.
1603    * @param  __HANDLE__ TIM handle.
1604    * @param  __CHANNEL__ TIM Channels to be configured.
1605    *          This parameter can be one of the following values:
1606    *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1607    *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1608    *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1609    *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1610    *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
1611    *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
1612    * @retval None
1613    */
1614  #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
1615    (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
1616     ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
1617     ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
1618     ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
1619     ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
1620     ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
1621  
1622  /**
1623    * @brief  Reset the TIM Output compare preload.
1624    * @param  __HANDLE__ TIM handle.
1625    * @param  __CHANNEL__ TIM Channels to be configured.
1626    *          This parameter can be one of the following values:
1627    *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1628    *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1629    *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1630    *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1631    *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
1632    *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
1633    * @retval None
1634    */
1635  #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
1636    (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
1637     ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
1638     ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
1639     ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\
1640     ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\
1641     ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))
1642  
1643  /**
1644    * @brief  Enable fast mode for a given channel.
1645    * @param  __HANDLE__ TIM handle.
1646    * @param  __CHANNEL__ TIM Channels to be configured.
1647    *          This parameter can be one of the following values:
1648    *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1649    *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1650    *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1651    *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1652    *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
1653    *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
1654    * @note  When fast mode is enabled an active edge on the trigger input acts
1655    *        like a compare match on CCx output. Delay to sample the trigger
1656    *        input and to activate CCx output is reduced to 3 clock cycles.
1657    * @note  Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
1658    * @retval None
1659    */
1660  #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
1661    (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
1662     ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
1663     ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
1664     ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\
1665     ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\
1666     ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))
1667  
1668  /**
1669    * @brief  Disable fast mode for a given channel.
1670    * @param  __HANDLE__ TIM handle.
1671    * @param  __CHANNEL__ TIM Channels to be configured.
1672    *          This parameter can be one of the following values:
1673    *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1674    *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1675    *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1676    *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1677    *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
1678    *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
1679    * @note  When fast mode is disabled CCx output behaves normally depending
1680    *        on counter and CCRx values even when the trigger is ON. The minimum
1681    *        delay to activate CCx output when an active edge occurs on the
1682    *        trigger input is 5 clock cycles.
1683    * @retval None
1684    */
1685  #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
1686    (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
1687     ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
1688     ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
1689     ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\
1690     ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\
1691     ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))
1692  
1693  /**
1694    * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register.
1695    * @param  __HANDLE__ TIM handle.
1696    * @note  When the URS bit of the TIMx_CR1 register is set, only counter
1697    *        overflow/underflow generates an update interrupt or DMA request (if
1698    *        enabled)
1699    * @retval None
1700    */
1701  #define __HAL_TIM_URS_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
1702  
1703  /**
1704    * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
1705    * @param  __HANDLE__ TIM handle.
1706    * @note  When the URS bit of the TIMx_CR1 register is reset, any of the
1707    *        following events generate an update interrupt or DMA request (if
1708    *        enabled):
1709    *           _ Counter overflow underflow
1710    *           _ Setting the UG bit
1711    *           _ Update generation through the slave mode controller
1712    * @retval None
1713    */
1714  #define __HAL_TIM_URS_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
1715  
1716  /**
1717    * @brief  Set the TIM Capture x input polarity on runtime.
1718    * @param  __HANDLE__ TIM handle.
1719    * @param  __CHANNEL__ TIM Channels to be configured.
1720    *          This parameter can be one of the following values:
1721    *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1722    *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1723    *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1724    *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1725    * @param  __POLARITY__ Polarity for TIx source
1726    *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
1727    *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
1728    *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
1729    * @retval None
1730    */
1731  #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \
1732    do{                                                                     \
1733      TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
1734      TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
1735    }while(0)
1736  
1737  /** @brief  Select the Capture/compare DMA request source.
1738    * @param  __HANDLE__ specifies the TIM Handle.
1739    * @param  __CCDMA__ specifies Capture/compare DMA request source
1740    *          This parameter can be one of the following values:
1741    *            @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event
1742    *            @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event
1743    * @retval None
1744    */
1745  #define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__)    \
1746    MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__))
1747  
1748  /**
1749    * @}
1750    */
1751  /* End of exported macros ----------------------------------------------------*/
1752  
1753  /* Private constants ---------------------------------------------------------*/
1754  /** @defgroup TIM_Private_Constants TIM Private Constants
1755    * @{
1756    */
1757  /* The counter of a timer instance is disabled only if all the CCx and CCxN
1758     channels have been disabled */
1759  #define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
1760  #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
1761  /**
1762    * @}
1763    */
1764  /* End of private constants --------------------------------------------------*/
1765  
1766  /* Private macros ------------------------------------------------------------*/
1767  /** @defgroup TIM_Private_Macros TIM Private Macros
1768    * @{
1769    */
1770  #define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)      || \
1771                                               ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
1772  
1773  #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1)   || \
1774                                     ((__BASE__) == TIM_DMABASE_CR2)   || \
1775                                     ((__BASE__) == TIM_DMABASE_SMCR)  || \
1776                                     ((__BASE__) == TIM_DMABASE_DIER)  || \
1777                                     ((__BASE__) == TIM_DMABASE_SR)    || \
1778                                     ((__BASE__) == TIM_DMABASE_EGR)   || \
1779                                     ((__BASE__) == TIM_DMABASE_CCMR1) || \
1780                                     ((__BASE__) == TIM_DMABASE_CCMR2) || \
1781                                     ((__BASE__) == TIM_DMABASE_CCER)  || \
1782                                     ((__BASE__) == TIM_DMABASE_CNT)   || \
1783                                     ((__BASE__) == TIM_DMABASE_PSC)   || \
1784                                     ((__BASE__) == TIM_DMABASE_ARR)   || \
1785                                     ((__BASE__) == TIM_DMABASE_RCR)   || \
1786                                     ((__BASE__) == TIM_DMABASE_CCR1)  || \
1787                                     ((__BASE__) == TIM_DMABASE_CCR2)  || \
1788                                     ((__BASE__) == TIM_DMABASE_CCR3)  || \
1789                                     ((__BASE__) == TIM_DMABASE_CCR4)  || \
1790                                     ((__BASE__) == TIM_DMABASE_BDTR)  || \
1791                                     ((__BASE__) == TIM_DMABASE_CCMR3) || \
1792                                     ((__BASE__) == TIM_DMABASE_CCR5)  || \
1793                                     ((__BASE__) == TIM_DMABASE_CCR6)  || \
1794                                     ((__BASE__) == TIM_DMABASE_AF1)   || \
1795                                     ((__BASE__) == TIM_DMABASE_AF2)   || \
1796                                     ((__BASE__) == TIM_DMABASE_TISEL))
1797  
1798  #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
1799  
1800  #define IS_TIM_COUNTER_MODE(__MODE__)      (((__MODE__) == TIM_COUNTERMODE_UP)              || \
1801                                              ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
1802                                              ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
1803                                              ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
1804                                              ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
1805  
1806  #define IS_TIM_UIFREMAP_MODE(__MODE__)     (((__MODE__) == TIM_UIFREMAP_DISABLE) || \
1807                                              ((__MODE__) == TIM_UIFREMAP_ENABLE))
1808  
1809  #define IS_TIM_CLOCKDIVISION_DIV(__DIV__)  (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
1810                                              ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
1811                                              ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
1812  
1813  #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
1814                                              ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
1815  
1816  #define IS_TIM_FAST_STATE(__STATE__)       (((__STATE__) == TIM_OCFAST_DISABLE) || \
1817                                              ((__STATE__) == TIM_OCFAST_ENABLE))
1818  
1819  #define IS_TIM_OC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
1820                                              ((__POLARITY__) == TIM_OCPOLARITY_LOW))
1821  
1822  #define IS_TIM_OCN_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
1823                                              ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
1824  
1825  #define IS_TIM_OCIDLE_STATE(__STATE__)     (((__STATE__) == TIM_OCIDLESTATE_SET) || \
1826                                              ((__STATE__) == TIM_OCIDLESTATE_RESET))
1827  
1828  #define IS_TIM_OCNIDLE_STATE(__STATE__)    (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
1829                                              ((__STATE__) == TIM_OCNIDLESTATE_RESET))
1830  
1831  #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING)   || \
1832                                                        ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
1833  
1834  #define IS_TIM_IC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
1835                                              ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
1836                                              ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
1837  
1838  #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
1839                                              ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
1840                                              ((__SELECTION__) == TIM_ICSELECTION_TRC))
1841  
1842  #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
1843                                              ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
1844                                              ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
1845                                              ((__PRESCALER__) == TIM_ICPSC_DIV8))
1846  
1847  #define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \
1848                                                         ((__CHANNEL__) != (TIM_CHANNEL_5)) && \
1849                                                         ((__CHANNEL__) != (TIM_CHANNEL_6)))
1850  
1851  #define IS_TIM_OPM_MODE(__MODE__)          (((__MODE__) == TIM_OPMODE_SINGLE) || \
1852                                              ((__MODE__) == TIM_OPMODE_REPETITIVE))
1853  
1854  #define IS_TIM_ENCODER_MODE(__MODE__)      (((__MODE__) == TIM_ENCODERMODE_TI1) || \
1855                                              ((__MODE__) == TIM_ENCODERMODE_TI2) || \
1856                                              ((__MODE__) == TIM_ENCODERMODE_TI12))
1857  
1858  #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
1859  
1860  #define IS_TIM_CHANNELS(__CHANNEL__)       (((__CHANNEL__) == TIM_CHANNEL_1) || \
1861                                              ((__CHANNEL__) == TIM_CHANNEL_2) || \
1862                                              ((__CHANNEL__) == TIM_CHANNEL_3) || \
1863                                              ((__CHANNEL__) == TIM_CHANNEL_4) || \
1864                                              ((__CHANNEL__) == TIM_CHANNEL_5) || \
1865                                              ((__CHANNEL__) == TIM_CHANNEL_6) || \
1866                                              ((__CHANNEL__) == TIM_CHANNEL_ALL))
1867  
1868  #define IS_TIM_OPM_CHANNELS(__CHANNEL__)   (((__CHANNEL__) == TIM_CHANNEL_1) || \
1869                                              ((__CHANNEL__) == TIM_CHANNEL_2))
1870  
1871  #define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \
1872    ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U))
1873  
1874  #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1875                                                      ((__CHANNEL__) == TIM_CHANNEL_2) || \
1876                                                      ((__CHANNEL__) == TIM_CHANNEL_3))
1877  
1878  #if defined(USB_BASE)
1879  #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
1880                                         ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
1881                                         ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
1882                                         ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
1883                                         ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
1884                                         ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
1885                                         ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
1886                                         ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
1887                                         ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
1888                                         ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
1889                                         ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7))
1890  #else
1891  #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
1892                                         ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
1893                                         ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
1894                                         ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
1895                                         ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
1896                                         ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
1897                                         ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
1898                                         ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
1899                                         ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
1900                                         ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3))
1901  #endif /* USB_BASE */
1902  
1903  #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
1904                                              ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
1905                                              ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
1906                                              ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
1907                                              ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
1908  
1909  #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
1910                                                ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
1911                                                ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
1912                                                ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
1913  
1914  #define IS_TIM_CLOCKFILTER(__ICFILTER__)      ((__ICFILTER__) <= 0xFU)
1915  
1916  #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
1917                                                    ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
1918  
1919  #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
1920                                                      ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
1921                                                      ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
1922                                                      ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
1923  
1924  #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1925  
1926  #define IS_TIM_OSSR_STATE(__STATE__)       (((__STATE__) == TIM_OSSR_ENABLE) || \
1927                                              ((__STATE__) == TIM_OSSR_DISABLE))
1928  
1929  #define IS_TIM_OSSI_STATE(__STATE__)       (((__STATE__) == TIM_OSSI_ENABLE) || \
1930                                              ((__STATE__) == TIM_OSSI_DISABLE))
1931  
1932  #define IS_TIM_LOCK_LEVEL(__LEVEL__)       (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
1933                                              ((__LEVEL__) == TIM_LOCKLEVEL_1)   || \
1934                                              ((__LEVEL__) == TIM_LOCKLEVEL_2)   || \
1935                                              ((__LEVEL__) == TIM_LOCKLEVEL_3))
1936  
1937  #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
1938  
1939  
1940  #define IS_TIM_BREAK_STATE(__STATE__)      (((__STATE__) == TIM_BREAK_ENABLE) || \
1941                                              ((__STATE__) == TIM_BREAK_DISABLE))
1942  
1943  #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
1944                                               ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
1945  
1946  #define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \
1947                                           ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL))
1948  
1949  
1950  #define IS_TIM_BREAK2_STATE(__STATE__)     (((__STATE__) == TIM_BREAK2_ENABLE) || \
1951                                              ((__STATE__) == TIM_BREAK2_DISABLE))
1952  
1953  #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
1954                                                ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
1955  
1956  #define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \
1957                                            ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL))
1958  
1959  
1960  #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
1961                                                    ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
1962  
1963  #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
1964  
1965  #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET)  || \
1966                                          ((__SOURCE__) == TIM_TRGO_ENABLE) || \
1967                                          ((__SOURCE__) == TIM_TRGO_UPDATE) || \
1968                                          ((__SOURCE__) == TIM_TRGO_OC1)    || \
1969                                          ((__SOURCE__) == TIM_TRGO_OC1REF) || \
1970                                          ((__SOURCE__) == TIM_TRGO_OC2REF) || \
1971                                          ((__SOURCE__) == TIM_TRGO_OC3REF) || \
1972                                          ((__SOURCE__) == TIM_TRGO_OC4REF))
1973  
1974  #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET)                        || \
1975                                           ((__SOURCE__) == TIM_TRGO2_ENABLE)                       || \
1976                                           ((__SOURCE__) == TIM_TRGO2_UPDATE)                       || \
1977                                           ((__SOURCE__) == TIM_TRGO2_OC1)                          || \
1978                                           ((__SOURCE__) == TIM_TRGO2_OC1REF)                       || \
1979                                           ((__SOURCE__) == TIM_TRGO2_OC2REF)                       || \
1980                                           ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
1981                                           ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
1982                                           ((__SOURCE__) == TIM_TRGO2_OC4REF)                       || \
1983                                           ((__SOURCE__) == TIM_TRGO2_OC5REF)                       || \
1984                                           ((__SOURCE__) == TIM_TRGO2_OC6REF)                       || \
1985                                           ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \
1986                                           ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \
1987                                           ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \
1988                                           ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
1989                                           ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \
1990                                           ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
1991  
1992  #define IS_TIM_MSM_STATE(__STATE__)      (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
1993                                            ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
1994  
1995  #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE)   || \
1996                                       ((__MODE__) == TIM_SLAVEMODE_RESET)     || \
1997                                       ((__MODE__) == TIM_SLAVEMODE_GATED)     || \
1998                                       ((__MODE__) == TIM_SLAVEMODE_TRIGGER)   || \
1999                                       ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
2000                                       ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
2001  
2002  #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1)               || \
2003                                     ((__MODE__) == TIM_OCMODE_PWM2)               || \
2004                                     ((__MODE__) == TIM_OCMODE_COMBINED_PWM1)      || \
2005                                     ((__MODE__) == TIM_OCMODE_COMBINED_PWM2)      || \
2006                                     ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1)    || \
2007                                     ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
2008  
2009  #define IS_TIM_OC_MODE(__MODE__)  (((__MODE__) == TIM_OCMODE_TIMING)             || \
2010                                     ((__MODE__) == TIM_OCMODE_ACTIVE)             || \
2011                                     ((__MODE__) == TIM_OCMODE_INACTIVE)           || \
2012                                     ((__MODE__) == TIM_OCMODE_TOGGLE)             || \
2013                                     ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \
2014                                     ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)    || \
2015                                     ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
2016                                     ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
2017  
2018  #if defined(USB_BASE)
2019  #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0)    || \
2020                                                   ((__SELECTION__) == TIM_TS_ITR1)    || \
2021                                                   ((__SELECTION__) == TIM_TS_ITR2)    || \
2022                                                   ((__SELECTION__) == TIM_TS_ITR3)    || \
2023                                                   ((__SELECTION__) == TIM_TS_ITR7)    || \
2024                                                   ((__SELECTION__) == TIM_TS_TI1F_ED) || \
2025                                                   ((__SELECTION__) == TIM_TS_TI1FP1)  || \
2026                                                   ((__SELECTION__) == TIM_TS_TI2FP2)  || \
2027                                                   ((__SELECTION__) == TIM_TS_ETRF))
2028  #else
2029  #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0)    || \
2030                                                   ((__SELECTION__) == TIM_TS_ITR1)    || \
2031                                                   ((__SELECTION__) == TIM_TS_ITR2)    || \
2032                                                   ((__SELECTION__) == TIM_TS_ITR3)    || \
2033                                                   ((__SELECTION__) == TIM_TS_TI1F_ED) || \
2034                                                   ((__SELECTION__) == TIM_TS_TI1FP1)  || \
2035                                                   ((__SELECTION__) == TIM_TS_TI2FP2)  || \
2036                                                   ((__SELECTION__) == TIM_TS_ETRF))
2037  #endif /* USB_BASE */
2038  
2039  #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
2040                                                                 ((__SELECTION__) == TIM_TS_ITR1) || \
2041                                                                 ((__SELECTION__) == TIM_TS_ITR2) || \
2042                                                                 ((__SELECTION__) == TIM_TS_ITR3) || \
2043                                                                 ((__SELECTION__) == TIM_TS_NONE))
2044  
2045  #define IS_TIM_TRIGGERPOLARITY(__POLARITY__)   (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
2046                                                  ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
2047                                                  ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
2048                                                  ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
2049                                                  ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
2050  
2051  #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
2052                                                  ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
2053                                                  ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
2054                                                  ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
2055  
2056  #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
2057  
2058  #define IS_TIM_TI1SELECTION(__TI1SELECTION__)  (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
2059                                                  ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
2060  
2061  #define IS_TIM_DMA_LENGTH(__LENGTH__)      (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER)   || \
2062                                              ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS)  || \
2063                                              ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS)  || \
2064                                              ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS)  || \
2065                                              ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS)  || \
2066                                              ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS)  || \
2067                                              ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS)  || \
2068                                              ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS)  || \
2069                                              ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS)  || \
2070                                              ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
2071                                              ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
2072                                              ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
2073                                              ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
2074                                              ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
2075                                              ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
2076                                              ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
2077                                              ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
2078                                              ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
2079  
2080  #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
2081  
2082  #define IS_TIM_IC_FILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xFU)
2083  
2084  #define IS_TIM_DEADTIME(__DEADTIME__)    ((__DEADTIME__) <= 0xFFU)
2085  
2086  #define IS_TIM_BREAK_SYSTEM(__CONFIG__)    (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC)                  || \
2087                                              ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD)                  || \
2088                                              ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR)    || \
2089                                              ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
2090  
2091  #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
2092                                                         ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
2093  
2094  #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
2095    (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
2096     ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
2097     ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
2098     ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
2099  
2100  #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
2101    (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
2102     ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
2103     ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
2104     ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
2105  
2106  #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
2107    (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
2108     ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
2109     ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
2110     ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
2111  
2112  #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
2113    (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
2114     ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
2115     ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
2116     ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
2117  
2118  #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
2119    (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
2120     ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
2121     ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
2122     ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\
2123     ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\
2124     (__HANDLE__)->ChannelState[5])
2125  
2126  #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
2127    (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
2128     ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
2129     ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
2130     ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\
2131     ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\
2132     ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__)))
2133  
2134  #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__,  __CHANNEL_STATE__) do { \
2135                                                                         (__HANDLE__)->ChannelState[0]  = \
2136                                                                         (__CHANNEL_STATE__);  \
2137                                                                         (__HANDLE__)->ChannelState[1]  = \
2138                                                                         (__CHANNEL_STATE__);  \
2139                                                                         (__HANDLE__)->ChannelState[2]  = \
2140                                                                         (__CHANNEL_STATE__);  \
2141                                                                         (__HANDLE__)->ChannelState[3]  = \
2142                                                                         (__CHANNEL_STATE__);  \
2143                                                                         (__HANDLE__)->ChannelState[4]  = \
2144                                                                         (__CHANNEL_STATE__);  \
2145                                                                         (__HANDLE__)->ChannelState[5]  = \
2146                                                                         (__CHANNEL_STATE__);  \
2147                                                                       } while(0)
2148  
2149  #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
2150    (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
2151     ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
2152     ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
2153     (__HANDLE__)->ChannelNState[3])
2154  
2155  #define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
2156    (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
2157     ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
2158     ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
2159     ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
2160  
2161  #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__,  __CHANNEL_STATE__) do { \
2162                                                                           (__HANDLE__)->ChannelNState[0] = \
2163                                                                           (__CHANNEL_STATE__);  \
2164                                                                           (__HANDLE__)->ChannelNState[1] = \
2165                                                                           (__CHANNEL_STATE__);  \
2166                                                                           (__HANDLE__)->ChannelNState[2] = \
2167                                                                           (__CHANNEL_STATE__);  \
2168                                                                           (__HANDLE__)->ChannelNState[3] = \
2169                                                                           (__CHANNEL_STATE__);  \
2170                                                                         } while(0)
2171  
2172  /**
2173    * @}
2174    */
2175  /* End of private macros -----------------------------------------------------*/
2176  
2177  /* Include TIM HAL Extended module */
2178  #include "stm32c0xx_hal_tim_ex.h"
2179  
2180  /* Exported functions --------------------------------------------------------*/
2181  /** @addtogroup TIM_Exported_Functions TIM Exported Functions
2182    * @{
2183    */
2184  
2185  /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
2186    *  @brief   Time Base functions
2187    * @{
2188    */
2189  /* Time Base functions ********************************************************/
2190  HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
2191  HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
2192  void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
2193  void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
2194  /* Blocking mode: Polling */
2195  HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
2196  HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
2197  /* Non-Blocking mode: Interrupt */
2198  HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
2199  HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
2200  /* Non-Blocking mode: DMA */
2201  HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length);
2202  HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
2203  /**
2204    * @}
2205    */
2206  
2207  /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
2208    *  @brief   TIM Output Compare functions
2209    * @{
2210    */
2211  /* Timer Output Compare functions *********************************************/
2212  HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
2213  HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
2214  void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
2215  void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
2216  /* Blocking mode: Polling */
2217  HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
2218  HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
2219  /* Non-Blocking mode: Interrupt */
2220  HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2221  HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2222  /* Non-Blocking mode: DMA */
2223  HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
2224                                         uint16_t Length);
2225  HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
2226  /**
2227    * @}
2228    */
2229  
2230  /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
2231    *  @brief   TIM PWM functions
2232    * @{
2233    */
2234  /* Timer PWM functions ********************************************************/
2235  HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
2236  HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
2237  void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
2238  void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
2239  /* Blocking mode: Polling */
2240  HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
2241  HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
2242  /* Non-Blocking mode: Interrupt */
2243  HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2244  HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2245  /* Non-Blocking mode: DMA */
2246  HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
2247                                          uint16_t Length);
2248  HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
2249  /**
2250    * @}
2251    */
2252  
2253  /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
2254    *  @brief   TIM Input Capture functions
2255    * @{
2256    */
2257  /* Timer Input Capture functions **********************************************/
2258  HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
2259  HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
2260  void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
2261  void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
2262  /* Blocking mode: Polling */
2263  HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
2264  HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
2265  /* Non-Blocking mode: Interrupt */
2266  HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2267  HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2268  /* Non-Blocking mode: DMA */
2269  HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
2270  HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
2271  /**
2272    * @}
2273    */
2274  
2275  /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
2276    *  @brief   TIM One Pulse functions
2277    * @{
2278    */
2279  /* Timer One Pulse functions **************************************************/
2280  HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
2281  HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
2282  void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
2283  void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
2284  /* Blocking mode: Polling */
2285  HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
2286  HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
2287  /* Non-Blocking mode: Interrupt */
2288  HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
2289  HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
2290  /**
2291    * @}
2292    */
2293  
2294  /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
2295    *  @brief   TIM Encoder functions
2296    * @{
2297    */
2298  /* Timer Encoder functions ****************************************************/
2299  HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig);
2300  HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
2301  void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
2302  void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
2303  /* Blocking mode: Polling */
2304  HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
2305  HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
2306  /* Non-Blocking mode: Interrupt */
2307  HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2308  HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2309  /* Non-Blocking mode: DMA */
2310  HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
2311                                              uint32_t *pData2, uint16_t Length);
2312  HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
2313  /**
2314    * @}
2315    */
2316  
2317  /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
2318    *  @brief   IRQ handler management
2319    * @{
2320    */
2321  /* Interrupt Handler functions  ***********************************************/
2322  void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
2323  /**
2324    * @}
2325    */
2326  
2327  /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
2328    *  @brief   Peripheral Control functions
2329    * @{
2330    */
2331  /* Control functions  *********************************************************/
2332  HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig,
2333                                             uint32_t Channel);
2334  HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig,
2335                                              uint32_t Channel);
2336  HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig,
2337                                             uint32_t Channel);
2338  HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
2339                                                   uint32_t OutputChannel,  uint32_t InputChannel);
2340  HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
2341                                             const TIM_ClearInputConfigTypeDef *sClearInputConfig,
2342                                             uint32_t Channel);
2343  HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig);
2344  HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
2345  HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
2346  HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
2347  HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2348                                                uint32_t BurstRequestSrc, const uint32_t  *BurstBuffer, uint32_t  BurstLength);
2349  HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2350                                                     uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
2351                                                     uint32_t BurstLength,  uint32_t DataLength);
2352  HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
2353  HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2354                                               uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
2355  HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2356                                                    uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
2357                                                    uint32_t  BurstLength, uint32_t  DataLength);
2358  HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
2359  HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
2360  uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel);
2361  /**
2362    * @}
2363    */
2364  
2365  /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
2366    *  @brief   TIM Callbacks functions
2367    * @{
2368    */
2369  /* Callback in non blocking modes (Interrupt and DMA) *************************/
2370  void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
2371  void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
2372  void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
2373  void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
2374  void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
2375  void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
2376  void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
2377  void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
2378  void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
2379  void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
2380  
2381  /* Callbacks Register/UnRegister functions  ***********************************/
2382  #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2383  HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
2384                                             pTIM_CallbackTypeDef pCallback);
2385  HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
2386  #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2387  
2388  /**
2389    * @}
2390    */
2391  
2392  /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
2393    *  @brief  Peripheral State functions
2394    * @{
2395    */
2396  /* Peripheral State functions  ************************************************/
2397  HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim);
2398  HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim);
2399  HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim);
2400  HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim);
2401  HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim);
2402  HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim);
2403  
2404  /* Peripheral Channel state functions  ************************************************/
2405  HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim);
2406  HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim,  uint32_t Channel);
2407  HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim);
2408  /**
2409    * @}
2410    */
2411  
2412  /**
2413    * @}
2414    */
2415  /* End of exported functions -------------------------------------------------*/
2416  
2417  /* Private functions----------------------------------------------------------*/
2418  /** @defgroup TIM_Private_Functions TIM Private Functions
2419    * @{
2420    */
2421  void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure);
2422  void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
2423  void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
2424  void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
2425                         uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
2426  
2427  void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
2428  void TIM_DMAError(DMA_HandleTypeDef *hdma);
2429  void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
2430  void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
2431  void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
2432  
2433  #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2434  void TIM_ResetCallback(TIM_HandleTypeDef *htim);
2435  #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2436  
2437  /**
2438    * @}
2439    */
2440  /* End of private functions --------------------------------------------------*/
2441  
2442  /**
2443    * @}
2444    */
2445  
2446  /**
2447    * @}
2448    */
2449  
2450  #ifdef __cplusplus
2451  }
2452  #endif
2453  
2454  #endif /* STM32C0xx_HAL_TIM_H */
2455