1 /** 2 ****************************************************************************** 3 * @file stm32c0xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32C0xx_HAL_RCC_EX_H 21 #define STM32C0xx_HAL_RCC_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32c0xx_hal_def.h" 29 30 /** @addtogroup STM32C0xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup RCCEx 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 40 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief RCC extended clocks structure definition 46 */ 47 typedef struct 48 { 49 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 50 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 51 52 uint32_t HSIKerClockDivider; /*!< Specifies HSI Kernel divider. 53 This parameter can be a value of @ref RCCEx_HSIKER_Div */ 54 55 uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. 56 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 57 58 uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source 59 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ 60 61 uint32_t I2s1ClockSelection; /*!< Specifies I2S1 clock source 62 This parameter can be a value of @ref RCCEx_I2S1_Clock_Source */ 63 64 uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source 65 This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ 66 67 uint32_t RTCClockSelection; /*!< Specifies RTC clock source. 68 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 69 } RCC_PeriphCLKInitTypeDef; 70 71 /** 72 * @} 73 */ 74 75 /* Exported constants --------------------------------------------------------*/ 76 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 77 * @{ 78 */ 79 80 /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source 81 * @{ 82 */ 83 #define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */ 84 #define RCC_LSCOSOURCE_LSE RCC_CSR1_LSCOSEL /*!< LSE selection for low speed clock output */ 85 /** 86 * @} 87 */ 88 89 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection 90 * @{ 91 */ 92 #define RCC_PERIPHCLK_USART1 0x00000001U 93 #define RCC_PERIPHCLK_I2C1 0x00000040U 94 #define RCC_PERIPHCLK_I2S1 0x00000800U 95 #define RCC_PERIPHCLK_ADC 0x00004000U 96 #define RCC_PERIPHCLK_RTC 0x00020000U 97 #define RCC_PERIPHCLK_HSIKER 0x80000000U 98 99 /** 100 * @} 101 */ 102 103 104 /** @defgroup RCCEx_USART1_Clock_Source RCC USART1 Clock Source 105 * @{ 106 */ 107 #define RCC_USART1CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as USART 1 clock */ 108 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 /*!< SYSCLK clock selected as USART 1 clock */ 109 #define RCC_USART1CLKSOURCE_HSIKER RCC_CCIPR_USART1SEL_1 /*!< HSI Kernel clock selected as USART 1 clock */ 110 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1) /*!< LSE clock selected as USART 1 clock */ 111 /** 112 * @} 113 */ 114 115 116 /** @defgroup RCCEx_I2C1_Clock_Source RCC I2C1 Clock Source 117 * @{ 118 */ 119 #define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as I2C1 clock */ 120 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 /*!< SYSCLK clock selected as I2C1 clock */ 121 #define RCC_I2C1CLKSOURCE_HSIKER RCC_CCIPR_I2C1SEL_1 /*!< HSI Kernel clock selected as I2C1 clock */ 122 /** 123 * @} 124 */ 125 126 /** @defgroup RCCEx_I2S1_Clock_Source RCC I2S1 Clock Source 127 * @{ 128 */ 129 #define RCC_I2S1CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK clock selected as I2S1 clock */ 130 #define RCC_I2S1CLKSOURCE_HSIKER RCC_CCIPR_I2S1SEL_1 /*!< HSI Kernel clock selected as I2S1 clock */ 131 #define RCC_I2S1CLKSOURCE_EXT RCC_CCIPR_I2S1SEL /*!< External I2S clock source selected as I2S1 clock */ 132 133 /** 134 * @} 135 */ 136 137 138 /** @defgroup RCCEx_ADC_Clock_Source RCC ADC Clock Source 139 * @{ 140 */ 141 142 #define RCC_ADCCLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK used as ADC clock */ 143 #define RCC_ADCCLKSOURCE_HSIKER RCC_CCIPR_ADCSEL_1 /*!< HSI kernel used as ADC clock */ 144 /** 145 * @} 146 */ 147 148 /** @defgroup RCCEx_HSIKER_Div HSIKER Div 149 * @{ 150 */ 151 #define RCC_HSIKER_DIV1 0x00000000U /*!< HSI Kernek clock is not divided */ 152 #define RCC_HSIKER_DIV2 RCC_CR_HSIKERDIV_0 /*!< HSI Kernel clock is divided by 2 */ 153 #define RCC_HSIKER_DIV3 RCC_CR_HSIKERDIV_1 /*!< HSI Kernel clock is divided by 3 */ 154 #define RCC_HSIKER_DIV4 (RCC_CR_HSIKERDIV_1|RCC_CR_HSIKERDIV_0) /*!< HSI Kernel clock is divided by 4 */ 155 #define RCC_HSIKER_DIV5 RCC_CR_HSIKERDIV_2 /*!< HSI Kernel clock is divided by 5 */ 156 #define RCC_HSIKER_DIV6 (RCC_CR_HSIKERDIV_2|RCC_CR_HSIKERDIV_0) /*!< HSI Kernel clock is divided by 6 */ 157 #define RCC_HSIKER_DIV7 (RCC_CR_HSIKERDIV_2|RCC_CR_HSIKERDIV_1) /*!< HSI Kernel clock is divided by 7 */ 158 #define RCC_HSIKER_DIV8 (RCC_CR_HSIKERDIV_2|RCC_CR_HSIKERDIV_1|RCC_CR_HSIKERDIV_0) /*!< HSI Kernel clock is divided by 8 */ 159 /** 160 * @} 161 */ 162 163 /** 164 * @} 165 */ 166 167 /* Exported macros -----------------------------------------------------------*/ 168 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 169 * @{ 170 */ 171 172 173 /** @brief Macro to configure the I2C1 clock (I2C1CLK). 174 * 175 * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. 176 * This parameter can be one of the following values: 177 * @arg @ref RCC_I2C1CLKSOURCE_HSIKER HSI Kernel selected as I2C1 clock 178 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 179 */ 180 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ 181 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) 182 183 /** @brief Macro to get the I2C1 clock source. 184 * @retval The clock source can be one of the following values: 185 * @arg @ref RCC_I2C1CLKSOURCE_HSIKER HSI Kernel selected as I2C1 clock 186 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 187 */ 188 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))) 189 190 /** @brief Macro to configure the I2S1 clock (I2S1CLK). 191 * 192 * @param __I2S1_CLKSOURCE__ specifies the I2S1 clock source. 193 * This parameter can be one of the following values: 194 * @arg @ref RCC_I2S1CLKSOURCE_SYSCLK System Clock selected as I2S1 clock 195 * @arg @ref RCC_I2S1CLKSOURCE_HSIKER HSI Kernel Clock selected as I2S1 clock 196 * @arg @ref RCC_I2S1CLKSOURCE_EXT External clock selected as I2S1 clock 197 */ 198 #define __HAL_RCC_I2S1_CONFIG(__I2S1_CLKSOURCE__) \ 199 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S1SEL, (uint32_t)(__I2S1_CLKSOURCE__)) 200 201 /** @brief Macro to get the I2S1 clock source. 202 * @retval The clock source can be one of the following values: 203 * @arg @ref RCC_I2S1CLKSOURCE_SYSCLK System Clock selected as I2S1 clock 204 * @arg @ref RCC_I2S1CLKSOURCE_HSIKER HSI Kernel Clock selected as I2S1 clock 205 * @arg @ref RCC_I2S1CLKSOURCE_EXT External clock selected as I2S1 clock 206 */ 207 #define __HAL_RCC_GET_I2S1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2S1SEL))) 208 209 210 /** @brief Macro to configure the USART1 clock (USART1CLK). 211 * 212 * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. 213 * This parameter can be one of the following values: 214 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock 215 * @arg @ref RCC_USART1CLKSOURCE_HSIKER HSI Kernel selected as USART1 clock 216 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 217 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 218 */ 219 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ 220 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) 221 222 /** @brief Macro to get the USART1 clock source. 223 * @retval The clock source can be one of the following values: 224 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock 225 * @arg @ref RCC_USART1CLKSOURCE_HSIKER HSI Kernel selected as USART1 clock 226 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 227 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 228 */ 229 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))) 230 231 /** @brief Macro to configure the ADC interface clock 232 * @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source. 233 * This parameter can be one of the following values: 234 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock 235 * @arg @ref RCC_ADCCLKSOURCE_HSIKER HSI Kernel Clock selected as ADC clock 236 */ 237 #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \ 238 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__)) 239 240 /** @brief Macro to get the ADC clock source. 241 * @retval The clock source can be one of the following values: 242 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock 243 * @arg @ref RCC_ADCCLKSOURCE_HSIKER HSI Kernel Clock selected as ADC clock 244 */ 245 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL))) 246 247 /** @brief Macro to configure the HSIKER clock. 248 * @param __HSIKERDIV__ specifies the HSI Kernel division factor. 249 * This parameter can be one of the following values: 250 * @arg @ref RCC_HSIKER_DIV1 HSI clock source is divided by 1 251 * @arg @ref RCC_HSIKER_DIV2 HSI clock source is divided by 2 252 * @arg @ref RCC_HSIKER_DIV3 HSI clock source is divided by 3 253 * @arg @ref RCC_HSIKER_DIV4 HSI clock source is divided by 4 254 * @arg @ref RCC_HSIKER_DIV5 HSI clock source is divided by 5 255 * @arg @ref RCC_HSIKER_DIV6 HSI clock source is divided by 6 256 * @arg @ref RCC_HSIKER_DIV7 HSI clock source is divided by 7 257 * @arg @ref RCC_HSIKER_DIV8 HSI clock source is divided by 8 258 */ 259 #define __HAL_RCC_HSIKER_CONFIG(__HSIKERDIV__) \ 260 MODIFY_REG(RCC->CR, RCC_CR_HSIKERDIV, (__HSIKERDIV__)) 261 262 /** @brief Macro to get the HSIKER divider. 263 * @retval The HSI Kernel divider. The returned value can be one 264 * of the following: 265 * - RCC_HSIKER_DIV1 HSI oscillator divided by 1 266 * - RCC_HSIKER_DIV2 HSI oscillator divided by 2 267 * - RCC_HSIKER_DIV3 HSI oscillator divided by 3 (default after reset) 268 * - RCC_HSIKER_DIV4 HSI oscillator divided by 4 269 * - RCC_HSIKER_DIV5 HSI oscillator divided by 5 270 * - RCC_HSIKER_DIV6 HSI oscillator divided by 6 271 * - RCC_HSIKER_DIV7 HSI oscillator divided by 7 272 * - RCC_HSIKER_DIV8 HSI oscillator divided by 8 273 */ 274 #define __HAL_RCC_GET_HSIKER_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIKERDIV))) 275 276 /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management 277 * @brief macros to manage the specified RCC Flags and interrupts. 278 * @{ 279 */ 280 281 282 283 /** 284 * @} 285 */ 286 287 288 /** 289 * @} 290 */ 291 292 /* Exported functions --------------------------------------------------------*/ 293 /** @addtogroup RCCEx_Exported_Functions 294 * @{ 295 */ 296 297 /** @addtogroup RCCEx_Exported_Functions_Group1 298 * @{ 299 */ 300 301 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *PeriphClkInit); 302 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 303 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 304 305 /** 306 * @} 307 */ 308 309 /** @addtogroup RCCEx_Exported_Functions_Group2 310 * @{ 311 */ 312 313 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); 314 void HAL_RCCEx_DisableLSCO(void); 315 316 /** 317 * @} 318 */ 319 320 321 /** 322 * @} 323 */ 324 325 /* Private macros ------------------------------------------------------------*/ 326 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros 327 * @{ 328 */ 329 330 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ 331 ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) 332 333 334 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 335 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 336 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 337 (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ 338 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 339 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 340 (((__SELECTION__) & RCC_PERIPHCLK_HSIKER) == RCC_PERIPHCLK_HSIKER)) 341 342 343 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ 344 (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1) || \ 345 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ 346 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ 347 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSIKER)) 348 349 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ 350 (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ 351 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK) || \ 352 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSIKER)) 353 354 #define IS_RCC_I2S1CLKSOURCE(__SOURCE__) \ 355 (((__SOURCE__) == RCC_I2S1CLKSOURCE_SYSCLK)|| \ 356 ((__SOURCE__) == RCC_I2S1CLKSOURCE_HSIKER) || \ 357 ((__SOURCE__) == RCC_I2S1CLKSOURCE_EXT)) 358 359 360 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ 361 (((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK) || \ 362 ((__SOURCE__) == RCC_ADCCLKSOURCE_HSIKER)) 363 364 #define IS_RCC_HSIKERDIV(__DIV__) (((__DIV__) == RCC_HSIKER_DIV1) || ((__DIV__) == RCC_HSIKER_DIV2) || \ 365 ((__DIV__) == RCC_HSIKER_DIV3) || ((__DIV__) == RCC_HSIKER_DIV4) || \ 366 ((__DIV__) == RCC_HSIKER_DIV5) || ((__DIV__) == RCC_HSIKER_DIV6) || \ 367 ((__DIV__) == RCC_HSIKER_DIV7) || ((__DIV__) == RCC_HSIKER_DIV8)) 368 /** 369 * @} 370 */ 371 372 /** 373 * @} 374 */ 375 376 /** 377 * @} 378 */ 379 380 #ifdef __cplusplus 381 } 382 #endif 383 384 #endif /* STM32C0xx_HAL_RCC_EX_H */ 385 386
