1 /** 2 ****************************************************************************** 3 * @file stm32c0xx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32C0xx_HAL_DMA_H 21 #define STM32C0xx_HAL_DMA_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32c0xx_hal_def.h" 29 30 /** @addtogroup STM32C0xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup DMA 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup DMA_Exported_Types DMA Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief DMA Configuration Structure definition 45 */ 46 typedef struct 47 { 48 uint32_t Request; /*!< Specifies the request selected for the specified channel. 49 This parameter can be a value of @ref DMA_request */ 50 51 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 52 from memory to memory or from peripheral to memory. 53 This parameter can be a value of @ref DMA_Data_transfer_direction */ 54 55 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 56 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 57 58 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 59 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 60 61 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 62 This parameter can be a value of @ref DMA_Peripheral_data_size */ 63 64 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 65 This parameter can be a value of @ref DMA_Memory_data_size */ 66 67 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. 68 This parameter can be a value of @ref DMA_mode 69 @note The circular buffer mode cannot be used if the memory-to-memory 70 data transfer is configured on the selected Channel */ 71 72 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. 73 This parameter can be a value of @ref DMA_Priority_level */ 74 } DMA_InitTypeDef; 75 76 /** 77 * @brief HAL DMA State structures definition 78 */ 79 typedef enum 80 { 81 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 82 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 83 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 84 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ 85 } HAL_DMA_StateTypeDef; 86 87 /** 88 * @brief HAL DMA Error Code structure definition 89 */ 90 typedef enum 91 { 92 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 93 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ 94 } HAL_DMA_LevelCompleteTypeDef; 95 96 /** 97 * @brief HAL DMA Callback ID structure definition 98 */ 99 typedef enum 100 { 101 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 102 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ 103 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ 104 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ 105 HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ 106 107 } HAL_DMA_CallbackIDTypeDef; 108 109 /** 110 * @brief DMA handle Structure definition 111 */ 112 typedef struct __DMA_HandleTypeDef 113 { 114 DMA_Channel_TypeDef *Instance; /*!< Register base address */ 115 116 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 117 118 HAL_LockTypeDef Lock; /*!< DMA locking object */ 119 120 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 121 122 void *Parent; /*!< Parent object state */ 123 124 void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ 125 126 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */ 127 128 void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ 129 130 void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */ 131 132 __IO uint32_t ErrorCode; /*!< DMA Error code */ 133 134 uint32_t ChannelIndex; /*!< DMA Channel Index */ 135 136 DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */ 137 138 DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ 139 140 uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ 141 142 DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ 143 144 DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */ 145 146 uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ 147 } DMA_HandleTypeDef; 148 /** 149 * @} 150 */ 151 152 /* Exported constants --------------------------------------------------------*/ 153 154 /** @defgroup DMA_Exported_Constants DMA Exported Constants 155 * @{ 156 */ 157 158 /** @defgroup DMA_Error_Code DMA Error Code 159 * @{ 160 */ 161 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ 162 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ 163 #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */ 164 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 165 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ 166 #define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */ 167 #define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */ 168 169 /** 170 * @} 171 */ 172 173 /** @defgroup DMA_request DMA request 174 * @{ 175 */ 176 #define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */ 177 178 179 #define DMA_REQUEST_GENERATOR0 1U /*!< DMAMUX request generator 0 */ 180 #define DMA_REQUEST_GENERATOR1 2U /*!< DMAMUX request generator 1 */ 181 #define DMA_REQUEST_GENERATOR2 3U /*!< DMAMUX request generator 2 */ 182 #define DMA_REQUEST_GENERATOR3 4U /*!< DMAMUX request generator 3 */ 183 #define DMA_REQUEST_ADC1 5U /*!< DMAMUX ADC1 request */ 184 #define DMA_REQUEST_I2C1_RX 10U /*!< DMAMUX I2C1 RX request */ 185 #define DMA_REQUEST_I2C1_TX 11U /*!< DMAMUX I2C1 TX request */ 186 #define DMA_REQUEST_SPI1_RX 16U /*!< DMAMUX SPI1 RX request */ 187 #define DMA_REQUEST_SPI1_TX 17U /*!< DMAMUX SPI1 TX request */ 188 #define DMA_REQUEST_TIM1_CH1 20U /*!< DMAMUX TIM1 CH1 request */ 189 #define DMA_REQUEST_TIM1_CH2 21U /*!< DMAMUX TIM1 CH2 request */ 190 #define DMA_REQUEST_TIM1_CH3 22U /*!< DMAMUX TIM1 CH3 request */ 191 #define DMA_REQUEST_TIM1_CH4 23U /*!< DMAMUX TIM1 CH4 request */ 192 #define DMA_REQUEST_TIM1_TRIG_COM 24U /*!< DMAMUX TIM1 TRIG COM request */ 193 #define DMA_REQUEST_TIM1_UP 25U /*!< DMAMUX TIM1 UP request */ 194 #define DMA_REQUEST_TIM3_CH1 32U /*!< DMAMUX TIM3 CH1 request */ 195 #define DMA_REQUEST_TIM3_CH2 33U /*!< DMAMUX TIM3 CH2 request */ 196 #define DMA_REQUEST_TIM3_CH3 34U /*!< DMAMUX TIM3 CH3 request */ 197 #define DMA_REQUEST_TIM3_CH4 35U /*!< DMAMUX TIM3 CH4 request */ 198 #define DMA_REQUEST_TIM3_TRIG 36U /*!< DMAMUX TIM3 TRIG request */ 199 #define DMA_REQUEST_TIM3_UP 37U /*!< DMAMUX TIM3 UP request */ 200 #define DMA_REQUEST_TIM16_CH1 44U /*!< DMAMUX TIM16 CH1 request */ 201 #define DMA_REQUEST_TIM16_TRIG_COM 45U /*!< DMAMUX TIM16 TRIG COM request */ 202 #define DMA_REQUEST_TIM16_UP 46U /*!< DMAMUX TIM16 UP request */ 203 #define DMA_REQUEST_TIM17_CH1 47U /*!< DMAMUX TIM17 CH2 request */ 204 #define DMA_REQUEST_TIM17_TRIG_COM 48U /*!< DMAMUX TIM17 TRIG COM request */ 205 #define DMA_REQUEST_TIM17_UP 49U /*!< DMAMUX TIM17 UP request */ 206 #define DMA_REQUEST_USART1_RX 50U /*!< DMAMUX USART1 RX request */ 207 #define DMA_REQUEST_USART1_TX 51U /*!< DMAMUX USART1 TX request */ 208 #define DMA_REQUEST_USART2_RX 52U /*!< DMAMUX USART2 RX request */ 209 #define DMA_REQUEST_USART2_TX 53U /*!< DMAMUX USART2 TX request */ 210 211 /** 212 * @} 213 */ 214 215 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 216 * @{ 217 */ 218 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 219 #define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ 220 #define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ 221 222 /** 223 * @} 224 */ 225 226 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 227 * @{ 228 */ 229 #define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */ 230 #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ 231 /** 232 * @} 233 */ 234 235 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 236 * @{ 237 */ 238 #define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */ 239 #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ 240 /** 241 * @} 242 */ 243 244 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 245 * @{ 246 */ 247 #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ 248 #define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ 249 #define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ 250 /** 251 * @} 252 */ 253 254 /** @defgroup DMA_Memory_data_size DMA Memory data size 255 * @{ 256 */ 257 #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ 258 #define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ 259 #define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ 260 /** 261 * @} 262 */ 263 264 /** @defgroup DMA_mode DMA mode 265 * @{ 266 */ 267 #define DMA_NORMAL 0x00000000U /*!< Normal mode */ 268 #define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */ 269 /** 270 * @} 271 */ 272 273 /** @defgroup DMA_Priority_level DMA Priority level 274 * @{ 275 */ 276 #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ 277 #define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ 278 #define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ 279 #define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */ 280 /** 281 * @} 282 */ 283 284 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 285 * @{ 286 */ 287 #define DMA_IT_TC DMA_CCR_TCIE 288 #define DMA_IT_HT DMA_CCR_HTIE 289 #define DMA_IT_TE DMA_CCR_TEIE 290 /** 291 * @} 292 */ 293 294 /** @defgroup DMA_flag_definitions DMA flag definitions 295 * @{ 296 */ 297 298 #define DMA_FLAG_GI1 DMA_ISR_GIF1 299 #define DMA_FLAG_TC1 DMA_ISR_TCIF1 300 #define DMA_FLAG_HT1 DMA_ISR_HTIF1 301 #define DMA_FLAG_TE1 DMA_ISR_TEIF1 302 #define DMA_FLAG_GI2 DMA_ISR_GIF2 303 #define DMA_FLAG_TC2 DMA_ISR_TCIF2 304 #define DMA_FLAG_HT2 DMA_ISR_HTIF2 305 #define DMA_FLAG_TE2 DMA_ISR_TEIF2 306 #define DMA_FLAG_GI3 DMA_ISR_GIF3 307 #define DMA_FLAG_TC3 DMA_ISR_TCIF3 308 #define DMA_FLAG_HT3 DMA_ISR_HTIF3 309 #define DMA_FLAG_TE3 DMA_ISR_TEIF3 310 311 /** 312 * @} 313 */ 314 315 /** 316 * @} 317 */ 318 319 /* Exported macros -----------------------------------------------------------*/ 320 /** @defgroup DMA_Exported_Macros DMA Exported Macros 321 * @{ 322 */ 323 324 /** @brief Reset DMA handle state 325 * @param __HANDLE__ DMA handle 326 * @retval None 327 */ 328 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 329 330 /** 331 * @brief Enable the specified DMA Channel. 332 * @param __HANDLE__ DMA handle 333 * @retval None 334 */ 335 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) 336 337 /** 338 * @brief Disable the specified DMA Channel. 339 * @param __HANDLE__ DMA handle 340 * @retval None 341 */ 342 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) 343 344 /* Interrupt & Flag management */ 345 346 /** 347 * @brief Return the current DMA Channel transfer complete flag. 348 * @param __HANDLE__ DMA handle 349 * @retval The specified transfer complete flag index. 350 */ 351 352 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 353 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 354 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 355 DMA_FLAG_TC3) 356 357 /** 358 * @brief Return the current DMA Channel half transfer complete flag. 359 * @param __HANDLE__ DMA handle 360 * @retval The specified half transfer complete flag index. 361 */ 362 363 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 364 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 365 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 366 DMA_FLAG_HT3) 367 368 369 /** 370 * @brief Return the current DMA Channel transfer error flag. 371 * @param __HANDLE__ DMA handle 372 * @retval The specified transfer error flag index. 373 */ 374 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 375 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 376 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 377 DMA_FLAG_TE3) 378 379 /** 380 * @brief Return the current DMA Channel Global interrupt flag. 381 * @param __HANDLE__ DMA handle 382 * @retval The specified transfer error flag index. 383 */ 384 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 385 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\ 386 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\ 387 DMA_ISR_GIF3) 388 389 /** 390 * @brief Get the DMA Channel pending flags. 391 * @param __HANDLE__ DMA handle 392 * @param __FLAG__ Get the specified flag. 393 * This parameter can be any combination of the following values: 394 * @arg DMA_FLAG_TCIFx: Transfer complete flag 395 * @arg DMA_FLAG_HTIFx: Half transfer complete flag 396 * @arg DMA_FLAG_TEIFx: Transfer error flag 397 * @arg DMA_FLAG_GIFx: Global interrupt flag 398 * Where x can be 1_3 to select the DMA Channel flag. 399 * @retval The state of FLAG (SET or RESET). 400 */ 401 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) 402 403 /** 404 * @brief Clear the DMA Channel pending flags. 405 * @param __HANDLE__ DMA handle 406 * @param __FLAG__ specifies the flag to clear. 407 * This parameter can be any combination of the following values: 408 * @arg DMA_FLAG_TCIFx: Transfer complete flag 409 * @arg DMA_FLAG_HTIFx: Half transfer complete flag 410 * @arg DMA_FLAG_TEIFx: Transfer error flag 411 * @arg DMA_FLAG_GIFx: Global interrupt flag 412 * Where x can be 1_3 to select the DMA Channel flag. 413 * @retval None 414 */ 415 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR |= (__FLAG__)) 416 417 /** 418 * @brief Enable the specified DMA Channel interrupts. 419 * @param __HANDLE__ DMA handle 420 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 421 * This parameter can be any combination of the following values: 422 * @arg DMA_IT_TC: Transfer complete interrupt mask 423 * @arg DMA_IT_HT: Half transfer complete interrupt mask 424 * @arg DMA_IT_TE: Transfer error interrupt mask 425 * @retval None 426 */ 427 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) 428 429 /** 430 * @brief Disable the specified DMA Channel interrupts. 431 * @param __HANDLE__ DMA handle 432 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 433 * This parameter can be any combination of the following values: 434 * @arg DMA_IT_TC: Transfer complete interrupt mask 435 * @arg DMA_IT_HT: Half transfer complete interrupt mask 436 * @arg DMA_IT_TE: Transfer error interrupt mask 437 * @retval None 438 */ 439 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) 440 441 /** 442 * @brief Check whether the specified DMA Channel interrupt is enabled or disabled. 443 * @param __HANDLE__ DMA handle 444 * @param __INTERRUPT__ specifies the DMA interrupt source to check. 445 * This parameter can be one of the following values: 446 * @arg DMA_IT_TC: Transfer complete interrupt mask 447 * @arg DMA_IT_HT: Half transfer complete interrupt mask 448 * @arg DMA_IT_TE: Transfer error interrupt mask 449 * @retval The state of DMA_IT (SET or RESET). 450 */ 451 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) 452 453 /** 454 * @brief Returns the number of remaining data units in the current DMA Channel transfer. 455 * @param __HANDLE__ DMA handle 456 * @retval The number of remaining data units in the current DMA Channel transfer. 457 */ 458 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) 459 460 /** 461 * @} 462 */ 463 464 /* Include DMA HAL Extension module */ 465 #include "stm32c0xx_hal_dma_ex.h" 466 467 /* Exported functions --------------------------------------------------------*/ 468 469 /** @addtogroup DMA_Exported_Functions 470 * @{ 471 */ 472 473 /** @addtogroup DMA_Exported_Functions_Group1 474 * @{ 475 */ 476 /* Initialization and de-initialization functions *****************************/ 477 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 478 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); 479 /** 480 * @} 481 */ 482 483 /** @addtogroup DMA_Exported_Functions_Group2 484 * @{ 485 */ 486 /* IO operation functions *****************************************************/ 487 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 488 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, 489 uint32_t DataLength); 490 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 491 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 492 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, 493 uint32_t Timeout); 494 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 495 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, 496 void (* pCallback)(DMA_HandleTypeDef *_hdma)); 497 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 498 499 /** 500 * @} 501 */ 502 503 /** @addtogroup DMA_Exported_Functions_Group3 504 * @{ 505 */ 506 /* Peripheral State and Error functions ***************************************/ 507 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 508 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 509 /** 510 * @} 511 */ 512 513 /** 514 * @} 515 */ 516 517 /* Private macros ------------------------------------------------------------*/ 518 /** @defgroup DMA_Private_Macros DMA Private Macros 519 * @{ 520 */ 521 522 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 523 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 524 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 525 526 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) 527 528 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 529 ((STATE) == DMA_PINC_DISABLE)) 530 531 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 532 ((STATE) == DMA_MINC_DISABLE)) 533 534 #define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_USART2_TX) 535 536 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 537 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 538 ((SIZE) == DMA_PDATAALIGN_WORD)) 539 540 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 541 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 542 ((SIZE) == DMA_MDATAALIGN_WORD )) 543 544 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 545 ((MODE) == DMA_CIRCULAR)) 546 547 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 548 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 549 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 550 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 551 552 /** 553 * @} 554 */ 555 556 /* Private functions ---------------------------------------------------------*/ 557 558 /** 559 * @} 560 */ 561 562 /** 563 * @} 564 */ 565 566 #ifdef __cplusplus 567 } 568 #endif 569 570 #endif /* STM32C0xx_HAL_DMA_H */ 571
