1 /** 2 ****************************************************************************** 3 * @file stm32c0xx_hal_adc.h 4 * @author MCD Application Team 5 * @brief Header file of ADC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32C0xx_HAL_ADC_H 21 #define STM32C0xx_HAL_ADC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32c0xx_hal_def.h" 29 30 /* Include low level driver */ 31 #include "stm32c0xx_ll_adc.h" 32 33 /** @addtogroup STM32C0xx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup ADC 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup ADC_Exported_Types ADC Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief ADC group regular oversampling structure definition 48 */ 49 typedef struct 50 { 51 uint32_t Ratio; /*!< Configures the oversampling ratio. 52 This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ 53 54 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 55 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 56 57 uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. 58 This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */ 59 60 } ADC_OversamplingTypeDef; 61 62 /** 63 * @brief Structure definition of ADC instance and ADC group regular. 64 * @note Parameters of this structure are shared within 2 scopes: 65 * - Scope entire ADC (differentiation done for compatibility with some other STM32 series featuring ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign, 66 * ScanConvMode, EOCSelection, LowPowerAutoWait. 67 * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, 68 * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling. 69 * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. 70 * ADC state can be either: 71 * - For all parameters: ADC disabled 72 * - For all parameters except 'ClockPrescaler' and 'Resolution': ADC enabled without conversion on going on group regular. 73 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 74 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter 75 * (which fulfills the ADC state condition) on the fly). 76 */ 77 typedef struct 78 { 79 uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler. 80 This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. 81 Note: The ADC clock configuration is common to all ADC instances. 82 Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only 83 if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC 84 must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details. 85 Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level. 86 Note: This parameter can be modified only if all ADC instances are disabled. */ 87 88 uint32_t Resolution; /*!< Configure the ADC resolution. 89 This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ 90 91 uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). 92 Refer to reference manual for alignments formats versus resolutions. 93 This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */ 94 95 uint32_t ScanConvMode; /*!< Configure the sequencer of ADC group regular. 96 On this STM32 series, ADC group regular sequencer both modes "fully configurable" or "not fully configurable" are 97 available: 98 - sequencer configured to fully configurable: 99 sequencer length and each rank affectation to a channel are configurable. 100 - Sequence length: Set number of ranks in the scan sequence. 101 - Sequence direction: Unless specified in parameters, sequencer 102 scan direction is forward (from rank 1 to rank n). 103 - sequencer configured to not fully configurable: 104 sequencer length and each rank affectation to a channel are fixed by channel HW number. 105 - Sequence length: Number of ranks in the scan sequence is 106 defined by number of channels set in the sequence, 107 rank of each channel is fixed by channel HW number. 108 (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). 109 - Sequence direction: Unless specified in parameters, sequencer 110 scan direction is forward (from lowest channel number to 111 highest channel number). 112 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. 113 Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other STM32 devices): 114 If only 1 channel is set: Conversion is performed in single mode. 115 If several channels are set: Conversions are performed in sequence mode. 116 This parameter can be a value of @ref ADC_Scan_mode */ 117 118 uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions. 119 This parameter can be a value of @ref ADC_EOCSelection. */ 120 121 FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous 122 conversion (for ADC group regular) has been retrieved by user software, 123 using function HAL_ADC_GetValue(). 124 This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun 125 for low frequency applications. 126 This parameter can be set to ENABLE or DISABLE. 127 Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA). 128 Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait). 129 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: 130 use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. */ 131 132 FunctionalState LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling). 133 This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait'). 134 This parameter can be set to ENABLE or DISABLE. 135 Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */ 136 137 FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, 138 after the first ADC conversion start trigger occurred (software start or external trigger). 139 This parameter can be set to ENABLE or DISABLE. */ 140 141 uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer. 142 This parameter is dependent on ScanConvMode: 143 - sequencer configured to fully configurable: 144 Number of ranks in the scan sequence is configurable using this parameter. 145 Note: After the first call of 'HAL_ADC_Init()', each rank corresponding to parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'. 146 Afterwards, when all needed sequencer ranks are set, parameter 'NbrOfConversion' can be updated without modifying configuration of sequencer ranks 147 (sequencer ranks above 'NbrOfConversion' are discarded). 148 - sequencer configured to not fully configurable: 149 Number of ranks in the scan sequence is defined by number of channels set in the sequence. This parameter is discarded. 150 This parameter must be a number between Min_Data = 1 and Max_Data = 8. 151 Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ 152 153 FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence 154 (main sequence subdivided in successive parts). 155 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 156 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. 157 This parameter can be set to ENABLE or DISABLE. 158 Note: On this STM32 series, ADC group regular number of discontinuous ranks increment is fixed to one-by-one. */ 159 160 uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start. 161 If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead. 162 This parameter can be a value of @ref ADC_regular_external_trigger_source. 163 Caution: external trigger source is common to all ADC instances. */ 164 165 uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start. 166 If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. 167 This parameter can be a value of @ref ADC_regular_external_trigger_edge */ 168 169 FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached) 170 or in continuous mode (DMA transfer unlimited, whatever number of conversions). 171 This parameter can be set to ENABLE or DISABLE. 172 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */ 173 174 uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). 175 This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. 176 Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear 177 end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function 178 HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear). 179 Note: Error reporting with respect to the conversion mode: 180 - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data 181 overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case. 182 - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */ 183 184 uint32_t SamplingTimeCommon1; /*!< Set sampling time common to a group of channels. 185 Unit: ADC clock cycles 186 Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 187 Note: On this STM32 family, two different sampling time settings are available, each channel can use one of these two settings. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure. 188 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME 189 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 190 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 191 Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: few tens of microseconds). */ 192 193 uint32_t SamplingTimeCommon2; /*!< Set sampling time common to a group of channels, second common setting possible. 194 Unit: ADC clock cycles 195 Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 196 Note: On this STM32 family, two different sampling time settings are available, each channel can use one of these two settings. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure. 197 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME 198 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 199 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 200 Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: few tens of microseconds). */ 201 202 FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. 203 This parameter can be set to ENABLE or DISABLE. 204 Note: This parameter can be modified only if there is no conversion is ongoing on ADC group regular. */ 205 206 ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. 207 Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */ 208 209 uint32_t TriggerFrequencyMode; /*!< Set ADC trigger frequency mode. 210 This parameter can be a value of @ref ADC_HAL_EC_REG_TRIGGER_FREQ. 211 Note: ADC trigger frequency mode must be set to low frequency when 212 a duration is exceeded before ADC conversion start trigger event 213 (between ADC enable and ADC conversion start trigger event 214 or between two ADC conversion start trigger event). 215 Duration value: Refer to device datasheet, parameter "tIdle". 216 Note: When ADC trigger frequency mode is set to low frequency, 217 some rearm cycles are inserted before performing ADC conversion 218 start, inducing a delay of 2 ADC clock cycles. */ 219 220 } ADC_InitTypeDef; 221 222 /** 223 * @brief Structure definition of ADC channel for regular group 224 * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. 225 * ADC state can be either: 226 * - For all parameters: ADC disabled or enabled without conversion on going on regular group. 227 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 228 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) 229 * on the fly). 230 */ 231 typedef struct 232 { 233 uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. 234 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 235 Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ 236 237 uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer and specify its conversion rank. 238 This parameter is dependent on ScanConvMode: 239 - sequencer configured to fully configurable: 240 Channels ordering into each rank of scan sequence: 241 whatever channel can be placed into whatever rank. 242 - sequencer configured to not fully configurable: 243 rank of each channel is fixed by channel HW number. 244 (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). 245 Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer. 246 This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS */ 247 248 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 249 Unit: ADC clock cycles 250 Conversion time is the addition of sampling time and processing time 251 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 252 This parameter can be a value of @ref ADC_HAL_EC_SAMPLINGTIME_COMMON 253 Note: On this STM32 family, two different sampling time settings are available (refer to parameters "SamplingTimeCommon1" and "SamplingTimeCommon2"), each channel can use one of these two settings. 254 255 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 256 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 257 Refer to device datasheet for timings values. */ 258 259 } ADC_ChannelConfTypeDef; 260 261 /** 262 * @brief Structure definition of ADC analog watchdog 263 * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. 264 * ADC state can be either: 265 * - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion on going on ADC groups regular. 266 * - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular. 267 */ 268 typedef struct 269 { 270 uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. 271 For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode') 272 For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel) 273 This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */ 274 275 uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. 276 For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC group regular. 277 For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. 278 This parameter can be a value of @ref ADC_analog_watchdog_mode. */ 279 280 uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. 281 For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored). 282 For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE'). 283 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ 284 285 FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. 286 This parameter can be set to ENABLE or DISABLE */ 287 288 uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. 289 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number 290 between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. 291 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits 292 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. 293 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 294 impacted: the comparison of analog watchdog thresholds is done on 295 oversampling final computation (after ratio and shift application): 296 ADC data register bitfield [15:4] (12 most significant bits). */ 297 298 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. 299 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number 300 between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. 301 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits 302 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. 303 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 304 impacted: the comparison of analog watchdog thresholds is done on 305 oversampling final computation (after ratio and shift application): 306 ADC data register bitfield [15:4] (12 most significant bits). */ 307 } ADC_AnalogWDGConfTypeDef; 308 309 /** @defgroup ADC_States ADC States 310 * @{ 311 */ 312 313 /** 314 * @brief HAL ADC state machine: ADC states definition (bitfields) 315 * @note ADC state machine is managed by bitfields, state must be compared 316 * with bit by bit. 317 * For example: 318 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " 319 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " 320 */ 321 /* States of ADC global scope */ 322 #define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */ 323 #define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */ 324 #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, calibration) */ 325 #define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */ 326 327 /* States of ADC errors */ 328 #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */ 329 #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */ 330 #define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */ 331 332 /* States of ADC group regular */ 333 #define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode, 334 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 335 #define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ 336 #define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ 337 #define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag raised */ 338 339 /* States of ADC group injected */ 340 #define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< Not available on this STM32 series: A conversion on group injected is ongoing or can occur (either by auto-injection mode, 341 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available))*/ 342 #define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Not available on this STM32 series: Conversion data available on group injected */ 343 #define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Not available on this STM32 series: Injected queue overflow occurrence */ 344 345 /* States of ADC analog watchdogs */ 346 #define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ 347 #define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Not available on this STM32 series: Out-of-window occurrence of ADC analog watchdog 2 */ 348 #define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Not available on this STM32 series: Out-of-window occurrence of ADC analog watchdog 3 */ 349 350 /* States of ADC multi-mode */ 351 #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< Not available on this STM32 series: ADC in multimode slave state, controlled by another ADC master (when feature available) */ 352 353 354 /** 355 * @} 356 */ 357 358 /** 359 * @brief ADC handle Structure definition 360 */ 361 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 362 typedef struct __ADC_HandleTypeDef 363 #else 364 typedef struct 365 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 366 { 367 ADC_TypeDef *Instance; /*!< Register base address */ 368 ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ 369 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 370 HAL_LockTypeDef Lock; /*!< ADC locking object */ 371 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ 372 __IO uint32_t ErrorCode; /*!< ADC Error code */ 373 374 uint32_t ADCGroupRegularSequencerRanks; /*!< ADC group regular sequencer memorization of ranks setting, used in mode "fully configurable" (refer to parameter 'ScanConvMode') */ 375 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 376 void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ 377 void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ 378 void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ 379 void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ 380 void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ 381 void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */ 382 void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */ 383 void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ 384 void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ 385 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 386 } ADC_HandleTypeDef; 387 388 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 389 /** 390 * @brief HAL ADC Callback ID enumeration definition 391 */ 392 typedef enum 393 { 394 HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ 395 HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ 396 HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ 397 HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ 398 HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */ 399 HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */ 400 HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */ 401 HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ 402 HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ 403 } HAL_ADC_CallbackIDTypeDef; 404 405 /** 406 * @brief HAL ADC Callback pointer definition 407 */ 408 typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ 409 410 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 411 412 /** 413 * @} 414 */ 415 416 417 /* Exported constants --------------------------------------------------------*/ 418 419 /** @defgroup ADC_Exported_Constants ADC Exported Constants 420 * @{ 421 */ 422 423 /** @defgroup ADC_Error_Code ADC Error Code 424 * @{ 425 */ 426 #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ 427 #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking, 428 enable/disable, erroneous state, ...) */ 429 #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ 430 #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ 431 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 432 #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ 433 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 434 /** 435 * @} 436 */ 437 438 /** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source 439 * @{ 440 */ 441 #define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock derived from AHB clock without prescaler. This configuration must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle) */ 442 #define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ 443 #define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ 444 445 #define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */ 446 #define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */ 447 #define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */ 448 #define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */ 449 #define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */ 450 #define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */ 451 #define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */ 452 #define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */ 453 #define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */ 454 #define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */ 455 #define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */ 456 #define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */ 457 /** 458 * @} 459 */ 460 461 /** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution 462 * @{ 463 */ 464 #define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */ 465 #define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */ 466 #define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */ 467 #define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits */ 468 /** 469 * @} 470 */ 471 472 /** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment 473 * @{ 474 */ 475 #define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ 476 #define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ 477 /** 478 * @} 479 */ 480 481 /** @defgroup ADC_Scan_mode ADC sequencer scan mode 482 * @{ 483 */ 484 /* Note: On this STM32 family, ADC group regular sequencer both modes */ 485 /* "fully configurable" or "not fully configurable" are */ 486 /* available. */ 487 /* Scan mode values must be compatible with other STM32 devices having */ 488 /* a configurable sequencer. */ 489 /* Scan direction setting values are defined by taking in account */ 490 /* already defined values for other STM32 devices: */ 491 /* ADC_SCAN_DISABLE (0x00000000UL) */ 492 /* ADC_SCAN_ENABLE (0x00000001UL) */ 493 /* Sequencer fully configurable with only rank 1 enabled is considered */ 494 /* as default setting equivalent to scan enable. */ 495 /* In case of migration from another STM32 device, the user will be */ 496 /* warned of change of setting choices with assert check. */ 497 #define ADC_SCAN_DISABLE (0x00000000UL) /*!< Sequencer set to fully configurable: only the rank 1 is enabled (no scan sequence on several ranks) */ 498 #define ADC_SCAN_ENABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer set to fully configurable: sequencer length and each rank affectation to a channel are configurable. */ 499 500 #define ADC_SCAN_SEQ_FIXED (ADC_SCAN_SEQ_FIXED_INT) /*!< Sequencer set to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). Scan direction forward: from channel 0 to channel 18 */ 501 #define ADC_SCAN_SEQ_FIXED_BACKWARD (ADC_SCAN_SEQ_FIXED_INT | ADC_CFGR1_SCANDIR) /*!< Sequencer set to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). Scan direction backward: from channel 18 to channel 0 */ 502 503 #define ADC_SCAN_DIRECTION_FORWARD (ADC_SCAN_SEQ_FIXED) /* For compatibility with other STM32 devices */ 504 #define ADC_SCAN_DIRECTION_BACKWARD (ADC_SCAN_SEQ_FIXED_BACKWARD) /* For compatibility with other STM32 devices */ 505 /** 506 * @} 507 */ 508 509 /** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source 510 * @{ 511 */ 512 /* ADC group regular trigger sources for all ADC instances */ 513 #define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */ 514 #define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ 515 #define ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 516 #if defined(TIM2) 517 #define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ 518 #endif 519 #define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ 520 #if defined(TIM4) 521 #define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ 522 #endif 523 #if defined(TIM6) 524 #define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ 525 #endif 526 #if defined(TIM15) 527 #define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ 528 #endif 529 #define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */ 530 /** 531 * @} 532 */ 533 534 /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) 535 * @{ 536 */ 537 #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< Regular conversions hardware trigger detection disabled */ 538 #define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion trigger polarity set to rising edge */ 539 #define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion trigger polarity set to falling edge */ 540 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ 541 /** 542 * @} 543 */ 544 545 /** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions 546 * @{ 547 */ 548 #define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */ 549 #define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */ 550 /** 551 * @} 552 */ 553 554 /** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data 555 * @{ 556 */ 557 #define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */ 558 #define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */ 559 /** 560 * @} 561 */ 562 563 /** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks 564 * @{ 565 */ 566 #define ADC_RANK_CHANNEL_NUMBER (0x00000001U) /*!< Setting relevant if parameter "ScanConvMode" is set to sequencer not fully configurable: Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */ 567 #define ADC_RANK_NONE (0x00000002U) /*!< Setting relevant if parameter "ScanConvMode" is set to sequencer not fully configurable: Disable the selected rank (selected channel) from sequencer */ 568 569 #define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ 570 #define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ 571 #define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ 572 #define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ 573 #define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ 574 #define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ 575 #define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ 576 #define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ 577 /** 578 * @} 579 */ 580 581 /** @defgroup ADC_HAL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels 582 * @{ 583 */ 584 #define ADC_SAMPLINGTIME_COMMON_1 (LL_ADC_SAMPLINGTIME_COMMON_1) /*!< Set sampling time common to a group of channels: sampling time nb 1 */ 585 #define ADC_SAMPLINGTIME_COMMON_2 (LL_ADC_SAMPLINGTIME_COMMON_2) /*!< Set sampling time common to a group of channels: sampling time nb 2 */ 586 /** 587 * @} 588 */ 589 590 /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time 591 * @{ 592 */ 593 #define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycle */ 594 #define ADC_SAMPLETIME_3CYCLES_5 (LL_ADC_SAMPLINGTIME_3CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles */ 595 #define ADC_SAMPLETIME_7CYCLES_5 (LL_ADC_SAMPLINGTIME_7CYCLES_5) /*!< Sampling time 7.5 ADC clock cycles */ 596 #define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */ 597 #define ADC_SAMPLETIME_19CYCLES_5 (LL_ADC_SAMPLINGTIME_19CYCLES_5) /*!< Sampling time 19.5 ADC clock cycles */ 598 #define ADC_SAMPLETIME_39CYCLES_5 (LL_ADC_SAMPLINGTIME_39CYCLES_5) /*!< Sampling time 39.5 ADC clock cycles */ 599 #define ADC_SAMPLETIME_79CYCLES_5 (LL_ADC_SAMPLINGTIME_79CYCLES_5) /*!< Sampling time 79.5 ADC clock cycles */ 600 #define ADC_SAMPLETIME_160CYCLES_5 (LL_ADC_SAMPLINGTIME_160CYCLES_5) /*!< Sampling time 160.5 ADC clock cycles */ 601 /** 602 * @} 603 */ 604 605 /** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number 606 * @{ 607 */ 608 #define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ 609 #define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ 610 #define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ 611 #define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ 612 #define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ 613 #define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ 614 #define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ 615 #define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ 616 #define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ 617 #define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ 618 #define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ 619 #define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ 620 #define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ 621 #define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ 622 #define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ 623 #define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ 624 #define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ 625 #define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ 626 #define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ 627 #define ADC_CHANNEL_19 (LL_ADC_CHANNEL_19) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19 */ 628 #define ADC_CHANNEL_20 (LL_ADC_CHANNEL_20) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN20 */ 629 #define ADC_CHANNEL_21 (LL_ADC_CHANNEL_21) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN21 */ 630 #define ADC_CHANNEL_22 (LL_ADC_CHANNEL_22) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN22 */ 631 #define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */ 632 #define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< ADC internal channel connected to Temperature sensor. */ 633 #define ADC_CHANNEL_VDDA (LL_ADC_CHANNEL_VDDA) /*!< ADC internal channel connected to VDDA */ 634 #define ADC_CHANNEL_VSSA (LL_ADC_CHANNEL_VSSA) /*!< ADC internal channel connected to VSSA */ 635 /** 636 * @} 637 */ 638 639 /** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number 640 * @{ 641 */ 642 #define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ 643 #define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */ 644 #define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */ 645 /** 646 * @} 647 */ 648 649 /** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode 650 * @{ 651 */ 652 #define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */ 653 #define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */ 654 #define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR1_AWD1EN) /*!< Analog watchdog applied to regular group all channels */ 655 /** 656 * @} 657 */ 658 659 /** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio 660 * @{ 661 */ 662 #define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 663 #define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 664 #define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 665 #define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 666 #define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 667 #define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 668 #define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 669 #define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 670 /** 671 * @} 672 */ 673 674 /** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift 675 * @{ 676 */ 677 #define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ 678 #define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */ 679 #define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */ 680 #define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */ 681 #define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */ 682 #define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */ 683 #define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */ 684 #define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */ 685 #define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */ 686 /** 687 * @} 688 */ 689 690 /** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode 691 * @{ 692 */ 693 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ 694 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ 695 /** 696 * @} 697 */ 698 699 /** @defgroup ADC_HAL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode 700 * @{ 701 */ 702 #define ADC_TRIGGER_FREQ_HIGH (LL_ADC_TRIGGER_FREQ_HIGH) /*!< ADC trigger frequency mode set to high frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */ 703 #define ADC_TRIGGER_FREQ_LOW (LL_ADC_TRIGGER_FREQ_LOW) /*!< ADC trigger frequency mode set to low frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */ 704 /** 705 * @} 706 */ 707 708 709 /** @defgroup ADC_Event_type ADC Event type 710 * @{ 711 */ 712 #define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ 713 #define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */ 714 #define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */ 715 #define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */ 716 #define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ 717 /** 718 * @} 719 */ 720 #define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */ 721 722 /** @defgroup ADC_interrupts_definition ADC interrupts definition 723 * @{ 724 */ 725 #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ 726 #define ADC_IT_CCRDY ADC_IER_CCRDYIE /*!< ADC channel configuration ready interrupt source */ 727 #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ 728 #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ 729 #define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ 730 #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ 731 #define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ 732 #define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */ 733 #define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */ 734 /** 735 * @} 736 */ 737 738 /** @defgroup ADC_flags_definition ADC flags definition 739 * @{ 740 */ 741 #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ 742 #define ADC_FLAG_CCRDY ADC_ISR_CCRDY /*!< ADC channel configuration ready flag */ 743 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ 744 #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ 745 #define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ 746 #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ 747 #define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag */ 748 #define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag */ 749 #define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag */ 750 /** 751 * @} 752 */ 753 754 /** 755 * @} 756 */ 757 758 /* Private macro -------------------------------------------------------------*/ 759 760 /** @defgroup ADC_Private_Macros ADC Private Macros 761 * @{ 762 */ 763 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 764 /* code of final user. */ 765 766 /** 767 * @brief Test if conversion trigger of regular group is software start 768 * or external trigger. 769 * @param __HANDLE__ ADC handle 770 * @retval SET (software start) or RESET (external trigger) 771 */ 772 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ 773 (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == 0UL) 774 775 /** 776 * @brief Return resolution bits in CFGR1 register RES[1:0] field. 777 * @param __HANDLE__ ADC handle 778 * @retval Value of bitfield RES in CFGR1 register. 779 */ 780 #define ADC_GET_RESOLUTION(__HANDLE__) \ 781 (LL_ADC_GetResolution((__HANDLE__)->Instance)) 782 783 /** 784 * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE"). 785 * @param __HANDLE__ ADC handle 786 * @retval None 787 */ 788 #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 789 790 /** 791 * @brief Simultaneously clear and set specific bits of the handle State. 792 * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 793 * the first parameter is the ADC handle State, the second parameter is the 794 * bit field to clear, the third and last parameter is the bit field to set. 795 * @retval None 796 */ 797 #define ADC_STATE_CLR_SET MODIFY_REG 798 799 /** 800 * @brief Enable ADC discontinuous conversion mode for regular group 801 * @param _REG_DISCONTINUOUS_MODE_: Regular discontinuous mode. 802 * @retval None 803 */ 804 #define ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) \ 805 ((_REG_DISCONTINUOUS_MODE_) << 16U) 806 807 /** 808 * @brief Enable the ADC auto off mode. 809 * @param _AUTOOFF_ Auto off bit enable or disable. 810 * @retval None 811 */ 812 #define ADC_CFGR1_AUTOOFF(_AUTOOFF_) \ 813 ((_AUTOOFF_) << 15U) 814 815 /** 816 * @brief Enable the ADC auto delay mode. 817 * @param _AUTOWAIT_ Auto delay bit enable or disable. 818 * @retval None 819 */ 820 #define ADC_CFGR1_AUTOWAIT(_AUTOWAIT_) \ 821 ((_AUTOWAIT_) << 14U) 822 823 /** 824 * @brief Enable ADC continuous conversion mode. 825 * @param _CONTINUOUS_MODE_ Continuous mode. 826 * @retval None 827 */ 828 #define ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) \ 829 ((_CONTINUOUS_MODE_) << 13U) 830 831 /** 832 * @brief Enable ADC overrun mode. 833 * @param _OVERRUN_MODE_ Overrun mode. 834 * @retval Overrun bit setting to be programmed into CFGR register 835 */ 836 /* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */ 837 /* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it */ 838 /* as the default case to be compliant with other STM32 devices. */ 839 #define ADC_CFGR1_OVERRUN(_OVERRUN_MODE_) \ 840 ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \ 841 )? (ADC_CFGR1_OVRMOD) : (0x00000000UL) \ 842 ) 843 844 /** 845 * @brief Set ADC scan mode with differentiation of sequencer setting 846 * fixed or configurable 847 * @param _SCAN_MODE_ Scan conversion mode. 848 * @retval None 849 */ 850 /* Note: Scan mode set using this macro (instead of parameter direct set) */ 851 /* due to different modes on other STM32 devices: */ 852 /* if scan mode is disabled, sequencer is set to fully configurable */ 853 /* with setting of only rank 1 enabled afterwards. */ 854 #define ADC_SCAN_SEQ_MODE(_SCAN_MODE_) \ 855 ( (((_SCAN_MODE_) & ADC_SCAN_SEQ_FIXED_INT) != 0UL \ 856 )? \ 857 ((_SCAN_MODE_) & (~ADC_SCAN_SEQ_FIXED_INT)) \ 858 : \ 859 (ADC_CFGR1_CHSELRMOD) \ 860 ) 861 862 /** 863 * @brief Enable the ADC DMA continuous request. 864 * @param _DMACONTREQ_MODE_: DMA continuous request mode. 865 * @retval None 866 */ 867 #define ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_) \ 868 ((_DMACONTREQ_MODE_) << 1U) 869 870 /** 871 * @brief Shift the AWD threshold in function of the selected ADC resolution. 872 * Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. 873 * If resolution 12 bits, no shift. 874 * If resolution 10 bits, shift of 2 ranks on the left. 875 * If resolution 8 bits, shift of 4 ranks on the left. 876 * If resolution 6 bits, shift of 6 ranks on the left. 877 * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)) 878 * @param __HANDLE__ ADC handle 879 * @param _Threshold_ Value to be shifted 880 * @retval None 881 */ 882 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \ 883 ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2U)) 884 885 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) ||\ 886 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) ||\ 887 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ||\ 888 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1 ) ||\ 889 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2 ) ||\ 890 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4 ) ||\ 891 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6 ) ||\ 892 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8 ) ||\ 893 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 ) ||\ 894 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 ) ||\ 895 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 ) ||\ 896 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 ) ||\ 897 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 ) ||\ 898 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 ) ||\ 899 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256)) 900 901 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ 902 ((RESOLUTION) == ADC_RESOLUTION_10B) || \ 903 ((RESOLUTION) == ADC_RESOLUTION_8B) || \ 904 ((RESOLUTION) == ADC_RESOLUTION_6B) ) 905 906 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ 907 ((ALIGN) == ADC_DATAALIGN_LEFT) ) 908 909 #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \ 910 ((SCAN_MODE) == ADC_SCAN_ENABLE) || \ 911 ((SCAN_MODE) == ADC_SCAN_SEQ_FIXED) || \ 912 ((SCAN_MODE) == ADC_SCAN_SEQ_FIXED_BACKWARD) ) 913 914 #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 915 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ 916 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ 917 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) 918 919 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO2) || \ 920 ((REGTRIG) == ADC_EXTERNALTRIG_T1_CC4) || \ 921 ((REGTRIG) == ADC_EXTERNALTRIG_T3_TRGO) || \ 922 ((REGTRIG) == ADC_EXTERNALTRIG_EXT_IT11) || \ 923 ((REGTRIG) == ADC_SOFTWARE_START)) 924 925 #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \ 926 ((EOC_SELECTION) == ADC_EOC_SEQ_CONV)) 927 928 #define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \ 929 ((OVR) == ADC_OVR_DATA_OVERWRITTEN) ) 930 931 #define IS_ADC_REGULAR_RANK_SEQ_FIXED(RANK) (((RANK) == ADC_RANK_CHANNEL_NUMBER) || \ 932 ((RANK) == ADC_RANK_NONE) ) 933 934 #define IS_ADC_REGULAR_RANK(RANK) (((RANK) == ADC_REGULAR_RANK_1 ) || \ 935 ((RANK) == ADC_REGULAR_RANK_2 ) || \ 936 ((RANK) == ADC_REGULAR_RANK_3 ) || \ 937 ((RANK) == ADC_REGULAR_RANK_4 ) || \ 938 ((RANK) == ADC_REGULAR_RANK_5 ) || \ 939 ((RANK) == ADC_REGULAR_RANK_6 ) || \ 940 ((RANK) == ADC_REGULAR_RANK_7 ) || \ 941 ((RANK) == ADC_REGULAR_RANK_8 ) ) 942 943 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ 944 ((CHANNEL) == ADC_CHANNEL_1) || \ 945 ((CHANNEL) == ADC_CHANNEL_2) || \ 946 ((CHANNEL) == ADC_CHANNEL_3) || \ 947 ((CHANNEL) == ADC_CHANNEL_4) || \ 948 ((CHANNEL) == ADC_CHANNEL_5) || \ 949 ((CHANNEL) == ADC_CHANNEL_6) || \ 950 ((CHANNEL) == ADC_CHANNEL_7) || \ 951 ((CHANNEL) == ADC_CHANNEL_8) || \ 952 ((CHANNEL) == ADC_CHANNEL_9) || \ 953 ((CHANNEL) == ADC_CHANNEL_10) || \ 954 ((CHANNEL) == ADC_CHANNEL_11) || \ 955 ((CHANNEL) == ADC_CHANNEL_12) || \ 956 ((CHANNEL) == ADC_CHANNEL_13) || \ 957 ((CHANNEL) == ADC_CHANNEL_14) || \ 958 ((CHANNEL) == ADC_CHANNEL_15) || \ 959 ((CHANNEL) == ADC_CHANNEL_16) || \ 960 ((CHANNEL) == ADC_CHANNEL_17) || \ 961 ((CHANNEL) == ADC_CHANNEL_18) || \ 962 ((CHANNEL) == ADC_CHANNEL_19) || \ 963 ((CHANNEL) == ADC_CHANNEL_20) || \ 964 ((CHANNEL) == ADC_CHANNEL_21) || \ 965 ((CHANNEL) == ADC_CHANNEL_22) || \ 966 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \ 967 ((CHANNEL) == ADC_CHANNEL_VREFINT) || \ 968 ((CHANNEL) == ADC_CHANNEL_VDDA) || \ 969 ((CHANNEL) == ADC_CHANNEL_VSSA) ) 970 971 #define IS_ADC_SAMPLING_TIME_COMMON(SAMPLING_TIME_COMMON) (((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_1) || \ 972 ((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_2) ) 973 974 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \ 975 ((TIME) == ADC_SAMPLETIME_3CYCLES_5) || \ 976 ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \ 977 ((TIME) == ADC_SAMPLETIME_12CYCLES_5) || \ 978 ((TIME) == ADC_SAMPLETIME_19CYCLES_5) || \ 979 ((TIME) == ADC_SAMPLETIME_39CYCLES_5) || \ 980 ((TIME) == ADC_SAMPLETIME_79CYCLES_5) || \ 981 ((TIME) == ADC_SAMPLETIME_160CYCLES_5) ) 982 983 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_1) || \ 984 ((WATCHDOG) == ADC_ANALOGWATCHDOG_2) || \ 985 ((WATCHDOG) == ADC_ANALOGWATCHDOG_3) ) 986 987 #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ 988 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 989 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) ) 990 991 #define IS_ADC_TRIGGER_FREQ(TRIGGER_FREQ) (((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_HIGH) || \ 992 ((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_LOW) ) 993 994 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_EOSMP_EVENT) || \ 995 ((EVENT) == ADC_AWD1_EVENT) || \ 996 ((EVENT) == ADC_AWD2_EVENT) || \ 997 ((EVENT) == ADC_AWD3_EVENT) || \ 998 ((EVENT) == ADC_OVR_EVENT) ) 999 1000 /** 1001 * @brief Verify that a given value is aligned with the ADC resolution range. 1002 * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits). 1003 * @param __ADC_VALUE__ value checked against the resolution. 1004 * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) 1005 */ 1006 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ 1007 ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__)) 1008 1009 /** @defgroup ADC_regular_nb_conv_verification ADC Regular Conversion Number Verification 1010 * @{ 1011 */ 1012 #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1UL) && ((LENGTH) <= 8UL)) 1013 /** 1014 * @} 1015 */ 1016 1017 1018 /* Private constants ---------------------------------------------------------*/ 1019 1020 /** @defgroup ADC_Private_Constants ADC Private Constants 1021 * @{ 1022 */ 1023 1024 /* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */ 1025 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC) 1026 1027 #define ADC_SCAN_SEQ_FIXED_INT 0x80000000U /* Internal definition to differentiate sequencer setting fixed or configurable */ 1028 1029 /** 1030 * @} 1031 */ 1032 1033 /* Exported macro ------------------------------------------------------------*/ 1034 1035 /** @defgroup ADC_Exported_Macros ADC Exported Macros 1036 * @{ 1037 */ 1038 /* Macro for internal HAL driver usage, and possibly can be used into code of */ 1039 /* final user. */ 1040 1041 /** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags. 1042 * @{ 1043 */ 1044 1045 /** @brief Reset ADC handle state. 1046 * @param __HANDLE__ ADC handle 1047 * @retval None 1048 */ 1049 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 1050 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 1051 do{ \ 1052 (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ 1053 (__HANDLE__)->MspInitCallback = NULL; \ 1054 (__HANDLE__)->MspDeInitCallback = NULL; \ 1055 } while(0) 1056 #else 1057 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 1058 ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 1059 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 1060 1061 /** 1062 * @brief Enable ADC interrupt. 1063 * @param __HANDLE__ ADC handle 1064 * @param __INTERRUPT__ ADC Interrupt 1065 * This parameter can be one of the following values: 1066 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1067 * @arg @ref ADC_IT_CCRDY ADC channel configuration ready interrupt source 1068 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1069 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1070 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1071 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1072 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1073 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1074 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1075 * @retval None 1076 */ 1077 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 1078 (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) 1079 1080 /** 1081 * @brief Disable ADC interrupt. 1082 * @param __HANDLE__ ADC handle 1083 * @param __INTERRUPT__ ADC Interrupt 1084 * This parameter can be one of the following values: 1085 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1086 * @arg @ref ADC_IT_CCRDY ADC channel configuration ready interrupt source 1087 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1088 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1089 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1090 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1091 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1092 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1093 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1094 * @retval None 1095 */ 1096 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 1097 (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) 1098 1099 /** @brief Checks if the specified ADC interrupt source is enabled or disabled. 1100 * @param __HANDLE__ ADC handle 1101 * @param __INTERRUPT__ ADC interrupt source to check 1102 * This parameter can be one of the following values: 1103 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1104 * @arg @ref ADC_IT_CCRDY ADC channel configuration ready interrupt source 1105 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1106 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1107 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1108 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1109 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1110 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1111 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1112 * @retval State of interruption (SET or RESET) 1113 */ 1114 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 1115 (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) 1116 1117 /** 1118 * @brief Check whether the specified ADC flag is set or not. 1119 * @param __HANDLE__ ADC handle 1120 * @param __FLAG__ ADC flag 1121 * This parameter can be one of the following values: 1122 * @arg @ref ADC_FLAG_RDY ADC Ready flag 1123 * @arg @ref ADC_FLAG_CCRDY ADC channel configuration ready flag 1124 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 1125 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 1126 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 1127 * @arg @ref ADC_FLAG_OVR ADC overrun flag 1128 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 1129 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 1130 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 1131 * @retval State of flag (TRUE or FALSE). 1132 */ 1133 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ 1134 ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) 1135 1136 /** 1137 * @brief Clear the specified ADC flag. 1138 * @param __HANDLE__ ADC handle 1139 * @param __FLAG__ ADC flag 1140 * This parameter can be one of the following values: 1141 * @arg @ref ADC_FLAG_RDY ADC Ready flag 1142 * @arg @ref ADC_FLAG_CCRDY ADC channel configuration ready flag 1143 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 1144 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 1145 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 1146 * @arg @ref ADC_FLAG_OVR ADC overrun flag 1147 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 1148 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 1149 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 1150 * @retval None 1151 */ 1152 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ 1153 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 1154 (((__HANDLE__)->Instance->ISR) = (__FLAG__)) 1155 1156 /** 1157 * @} 1158 */ 1159 1160 /** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro 1161 * @{ 1162 */ 1163 1164 /** 1165 * @brief Helper macro to get ADC channel number in decimal format 1166 * from literals ADC_CHANNEL_x. 1167 * @note Example: 1168 * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) 1169 * will return decimal number "4". 1170 * @note The input can be a value from functions where a channel 1171 * number is returned, either defined with number 1172 * or with bitfield (only one bit must be set). 1173 * @param __CHANNEL__ This parameter can be one of the following values: 1174 * @arg @ref ADC_CHANNEL_0 1175 * @arg @ref ADC_CHANNEL_1 1176 * @arg @ref ADC_CHANNEL_2 1177 * @arg @ref ADC_CHANNEL_3 1178 * @arg @ref ADC_CHANNEL_4 1179 * @arg @ref ADC_CHANNEL_5 1180 * @arg @ref ADC_CHANNEL_6 1181 * @arg @ref ADC_CHANNEL_7 1182 * @arg @ref ADC_CHANNEL_8 (1) 1183 * @arg @ref ADC_CHANNEL_9 (1) 1184 * @arg @ref ADC_CHANNEL_10 1185 * @arg @ref ADC_CHANNEL_11 1186 * @arg @ref ADC_CHANNEL_12 1187 * @arg @ref ADC_CHANNEL_13 1188 * @arg @ref ADC_CHANNEL_14 1189 * @arg @ref ADC_CHANNEL_15 (1) 1190 * @arg @ref ADC_CHANNEL_16 (1) 1191 * @arg @ref ADC_CHANNEL_17 (3) 1192 * @arg @ref ADC_CHANNEL_18 (3) 1193 * @arg @ref ADC_CHANNEL_19 (3) 1194 * @arg @ref ADC_CHANNEL_20 (3) 1195 * @arg @ref ADC_CHANNEL_21 (3) 1196 * @arg @ref ADC_CHANNEL_22 (3) 1197 * @arg @ref ADC_CHANNEL_VREFINT (2) 1198 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) 1199 * @arg @ref ADC_CHANNEL_VDDA (2) 1200 * @arg @ref ADC_CHANNEL_VSSA (2) 1201 * 1202 * (1) On STM32C0, parameter can be set in ADC group sequencer 1203 * only if sequencer is set in mode "not fully configurable", 1204 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n 1205 * (2) For ADC channel read back from ADC register, 1206 * comparison with internal channel parameter to be done 1207 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 1208 * (3) ADC channels available on STM32C031xx device only. 1209 * @retval Value between Min_Data=0 and Max_Data=18 1210 */ 1211 #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 1212 __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) 1213 1214 /** 1215 * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x 1216 * from number in decimal format. 1217 * @note Example: 1218 * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) 1219 * will return a data equivalent to "ADC_CHANNEL_4". 1220 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 1221 * @retval Returned value can be one of the following values: 1222 * @arg @ref ADC_CHANNEL_0 1223 * @arg @ref ADC_CHANNEL_1 1224 * @arg @ref ADC_CHANNEL_2 1225 * @arg @ref ADC_CHANNEL_3 1226 * @arg @ref ADC_CHANNEL_4 1227 * @arg @ref ADC_CHANNEL_5 1228 * @arg @ref ADC_CHANNEL_6 1229 * @arg @ref ADC_CHANNEL_7 1230 * @arg @ref ADC_CHANNEL_8 (1) 1231 * @arg @ref ADC_CHANNEL_9 (1) 1232 * @arg @ref ADC_CHANNEL_10 1233 * @arg @ref ADC_CHANNEL_11 1234 * @arg @ref ADC_CHANNEL_12 1235 * @arg @ref ADC_CHANNEL_13 1236 * @arg @ref ADC_CHANNEL_14 1237 * @arg @ref ADC_CHANNEL_15 (1) 1238 * @arg @ref ADC_CHANNEL_16 (1) 1239 * @arg @ref ADC_CHANNEL_17 (3) 1240 * @arg @ref ADC_CHANNEL_18 (3) 1241 * @arg @ref ADC_CHANNEL_19 (3) 1242 * @arg @ref ADC_CHANNEL_20 (3) 1243 * @arg @ref ADC_CHANNEL_21 (3) 1244 * @arg @ref ADC_CHANNEL_22 (3) 1245 * @arg @ref ADC_CHANNEL_VREFINT (2) 1246 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) 1247 * @arg @ref ADC_CHANNEL_VDDA (2) 1248 * @arg @ref ADC_CHANNEL_VSSA (2) 1249 * 1250 * (1) On STM32C0, parameter can be set in ADC group sequencer 1251 * only if sequencer is set in mode "not fully configurable", 1252 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n 1253 * (2) For ADC channel read back from ADC register, 1254 * comparison with internal channel parameter to be done 1255 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 1256 * (3) ADC channels available on STM32C031xx device only. 1257 */ 1258 #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 1259 __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) 1260 1261 /** 1262 * @brief Helper macro to determine whether the selected channel 1263 * corresponds to literal definitions of driver. 1264 * @note The different literal definitions of ADC channels are: 1265 * - ADC internal channel: 1266 * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ... 1267 * - ADC external channel (channel connected to a GPIO pin): 1268 * ADC_CHANNEL_1, ADC_CHANNEL_2, ... 1269 * @note The channel parameter must be a value defined from literal 1270 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1271 * ADC_CHANNEL_TEMPSENSOR, ...), 1272 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), 1273 * must not be a value from functions where a channel number is 1274 * returned from ADC registers, 1275 * because internal and external channels share the same channel 1276 * number in ADC registers. The differentiation is made only with 1277 * parameters definitions of driver. 1278 * @param __CHANNEL__ This parameter can be one of the following values: 1279 * @arg @ref ADC_CHANNEL_0 1280 * @arg @ref ADC_CHANNEL_1 1281 * @arg @ref ADC_CHANNEL_2 1282 * @arg @ref ADC_CHANNEL_3 1283 * @arg @ref ADC_CHANNEL_4 1284 * @arg @ref ADC_CHANNEL_5 1285 * @arg @ref ADC_CHANNEL_6 1286 * @arg @ref ADC_CHANNEL_7 1287 * @arg @ref ADC_CHANNEL_8 (1) 1288 * @arg @ref ADC_CHANNEL_9 (1) 1289 * @arg @ref ADC_CHANNEL_10 1290 * @arg @ref ADC_CHANNEL_11 1291 * @arg @ref ADC_CHANNEL_12 1292 * @arg @ref ADC_CHANNEL_13 1293 * @arg @ref ADC_CHANNEL_14 1294 * @arg @ref ADC_CHANNEL_15 (1) 1295 * @arg @ref ADC_CHANNEL_16 (1) 1296 * @arg @ref ADC_CHANNEL_17 (3) 1297 * @arg @ref ADC_CHANNEL_18 (3) 1298 * @arg @ref ADC_CHANNEL_19 (3) 1299 * @arg @ref ADC_CHANNEL_20 (3) 1300 * @arg @ref ADC_CHANNEL_21 (3) 1301 * @arg @ref ADC_CHANNEL_22 (3) 1302 * @arg @ref ADC_CHANNEL_VREFINT (2) 1303 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) 1304 * @arg @ref ADC_CHANNEL_VDDA (2) 1305 * @arg @ref ADC_CHANNEL_VSSA (2) 1306 * 1307 * (1) On STM32C0, parameter can be set in ADC group sequencer 1308 * only if sequencer is set in mode "not fully configurable", 1309 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n 1310 * (2) For ADC channel read back from ADC register, 1311 * comparison with internal channel parameter to be done 1312 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 1313 * (3) ADC channels available on STM32C031xx device only. 1314 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). 1315 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. 1316 */ 1317 #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ 1318 __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) 1319 1320 /** 1321 * @brief Helper macro to convert a channel defined from parameter 1322 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1323 * ADC_CHANNEL_TEMPSENSOR, ...), 1324 * to its equivalent parameter definition of a ADC external channel 1325 * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...). 1326 * @note The channel parameter can be, additionally to a value 1327 * defined from parameter definition of a ADC internal channel 1328 * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), 1329 * a value defined from parameter definition of 1330 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 1331 * or a value from functions where a channel number is returned 1332 * from ADC registers. 1333 * @param __CHANNEL__ This parameter can be one of the following values: 1334 * @arg @ref ADC_CHANNEL_0 1335 * @arg @ref ADC_CHANNEL_1 1336 * @arg @ref ADC_CHANNEL_2 1337 * @arg @ref ADC_CHANNEL_3 1338 * @arg @ref ADC_CHANNEL_4 1339 * @arg @ref ADC_CHANNEL_5 1340 * @arg @ref ADC_CHANNEL_6 1341 * @arg @ref ADC_CHANNEL_7 1342 * @arg @ref ADC_CHANNEL_8 (1) 1343 * @arg @ref ADC_CHANNEL_9 (1) 1344 * @arg @ref ADC_CHANNEL_10 1345 * @arg @ref ADC_CHANNEL_11 1346 * @arg @ref ADC_CHANNEL_12 1347 * @arg @ref ADC_CHANNEL_13 1348 * @arg @ref ADC_CHANNEL_14 1349 * @arg @ref ADC_CHANNEL_15 (1) 1350 * @arg @ref ADC_CHANNEL_16 (1) 1351 * @arg @ref ADC_CHANNEL_17 (3) 1352 * @arg @ref ADC_CHANNEL_18 (3) 1353 * @arg @ref ADC_CHANNEL_19 (3) 1354 * @arg @ref ADC_CHANNEL_20 (3) 1355 * @arg @ref ADC_CHANNEL_21 (3) 1356 * @arg @ref ADC_CHANNEL_22 (3) 1357 * @arg @ref ADC_CHANNEL_VREFINT (2) 1358 * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) 1359 * @arg @ref ADC_CHANNEL_VDDA (2) 1360 * @arg @ref ADC_CHANNEL_VSSA (2) 1361 * 1362 * (1) On STM32C0, parameter can be set in ADC group sequencer 1363 * only if sequencer is set in mode "not fully configurable", 1364 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n 1365 * (2) For ADC channel read back from ADC register, 1366 * comparison with internal channel parameter to be done 1367 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 1368 * (3) ADC channels available on STM32C031xx device only. 1369 * @retval Returned value can be one of the following values: 1370 * @arg @ref ADC_CHANNEL_0 1371 * @arg @ref ADC_CHANNEL_1 1372 * @arg @ref ADC_CHANNEL_2 1373 * @arg @ref ADC_CHANNEL_3 1374 * @arg @ref ADC_CHANNEL_4 1375 * @arg @ref ADC_CHANNEL_5 1376 * @arg @ref ADC_CHANNEL_6 1377 * @arg @ref ADC_CHANNEL_7 1378 * @arg @ref ADC_CHANNEL_8 1379 * @arg @ref ADC_CHANNEL_9 1380 * @arg @ref ADC_CHANNEL_10 1381 * @arg @ref ADC_CHANNEL_11 1382 * @arg @ref ADC_CHANNEL_12 1383 * @arg @ref ADC_CHANNEL_13 1384 * @arg @ref ADC_CHANNEL_14 1385 * @arg @ref ADC_CHANNEL_15 1386 * @arg @ref ADC_CHANNEL_16 1387 * @arg @ref ADC_CHANNEL_17 1388 * @arg @ref ADC_CHANNEL_18 1389 * @arg @ref ADC_CHANNEL_19 1390 * @arg @ref ADC_CHANNEL_20 1391 * @arg @ref ADC_CHANNEL_21 1392 * @arg @ref ADC_CHANNEL_22 1393 */ 1394 #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ 1395 __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) 1396 1397 /** 1398 * @brief Helper macro to determine whether the internal channel 1399 * selected is available on the ADC instance selected. 1400 * @note The channel parameter must be a value defined from parameter 1401 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1402 * ADC_CHANNEL_TEMPSENSOR, ...), 1403 * must not be a value defined from parameter definition of 1404 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 1405 * or a value from functions where a channel number is 1406 * returned from ADC registers, 1407 * because internal and external channels share the same channel 1408 * number in ADC registers. The differentiation is made only with 1409 * parameters definitions of driver. 1410 * @param __ADC_INSTANCE__ ADC instance 1411 * @param __CHANNEL__ This parameter can be one of the following values: 1412 * @arg @ref ADC_CHANNEL_VREFINT 1413 * @arg @ref ADC_CHANNEL_TEMPSENSOR 1414 * @arg @ref ADC_CHANNEL_VDDA 1415 * @arg @ref ADC_CHANNEL_VSSA 1416 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. 1417 * Value "1" if the internal channel selected is available on the ADC instance selected. 1418 */ 1419 #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ 1420 __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) 1421 1422 /** 1423 * @brief Helper macro to select the ADC common instance 1424 * to which is belonging the selected ADC instance. 1425 * @note ADC common register instance can be used for: 1426 * - Set parameters common to several ADC instances 1427 * - Multimode (for devices with several ADC instances) 1428 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1429 * @param __ADCx__ ADC instance 1430 * @retval ADC common register instance 1431 */ 1432 #define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ 1433 __LL_ADC_COMMON_INSTANCE((__ADCx__)) 1434 1435 /** 1436 * @brief Helper macro to check if all ADC instances sharing the same 1437 * ADC common instance are disabled. 1438 * @note This check is required by functions with setting conditioned to 1439 * ADC state: 1440 * All ADC instances of the ADC common group must be disabled. 1441 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1442 * @note On devices with only 1 ADC common instance, parameter of this macro 1443 * is useless and can be ignored (parameter kept for compatibility 1444 * with devices featuring several ADC common instances). 1445 * @param __ADCXY_COMMON__ ADC common instance 1446 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 1447 * @retval Value "0" if all ADC instances sharing the same ADC common instance 1448 * are disabled. 1449 * Value "1" if at least one ADC instance sharing the same ADC common instance 1450 * is enabled. 1451 */ 1452 #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 1453 __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) 1454 1455 /** 1456 * @brief Helper macro to define the ADC conversion data full-scale digital 1457 * value corresponding to the selected ADC resolution. 1458 * @note ADC conversion data full-scale corresponds to voltage range 1459 * determined by analog voltage references Vref+ and Vref- 1460 * (refer to reference manual). 1461 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1462 * @arg @ref ADC_RESOLUTION_12B 1463 * @arg @ref ADC_RESOLUTION_10B 1464 * @arg @ref ADC_RESOLUTION_8B 1465 * @arg @ref ADC_RESOLUTION_6B 1466 * @retval ADC conversion data full-scale digital value 1467 */ 1468 #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 1469 __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) 1470 1471 /** 1472 * @brief Helper macro to convert the ADC conversion data from 1473 * a resolution to another resolution. 1474 * @param __DATA__ ADC conversion data to be converted 1475 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted 1476 * This parameter can be one of the following values: 1477 * @arg @ref ADC_RESOLUTION_12B 1478 * @arg @ref ADC_RESOLUTION_10B 1479 * @arg @ref ADC_RESOLUTION_8B 1480 * @arg @ref ADC_RESOLUTION_6B 1481 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion 1482 * This parameter can be one of the following values: 1483 * @arg @ref ADC_RESOLUTION_12B 1484 * @arg @ref ADC_RESOLUTION_10B 1485 * @arg @ref ADC_RESOLUTION_8B 1486 * @arg @ref ADC_RESOLUTION_6B 1487 * @retval ADC conversion data to the requested resolution 1488 */ 1489 #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ 1490 __ADC_RESOLUTION_CURRENT__,\ 1491 __ADC_RESOLUTION_TARGET__) \ 1492 __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ 1493 (__ADC_RESOLUTION_CURRENT__),\ 1494 (__ADC_RESOLUTION_TARGET__)) 1495 1496 /** 1497 * @brief Helper macro to calculate the voltage (unit: mVolt) 1498 * corresponding to a ADC conversion data (unit: digital value). 1499 * @note Analog reference voltage (Vref+) must be either known from 1500 * user board environment or can be calculated using ADC measurement 1501 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1502 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 1503 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) 1504 * (unit: digital value). 1505 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1506 * @arg @ref ADC_RESOLUTION_12B 1507 * @arg @ref ADC_RESOLUTION_10B 1508 * @arg @ref ADC_RESOLUTION_8B 1509 * @arg @ref ADC_RESOLUTION_6B 1510 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 1511 */ 1512 #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ 1513 __ADC_DATA__,\ 1514 __ADC_RESOLUTION__) \ 1515 __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ 1516 (__ADC_DATA__),\ 1517 (__ADC_RESOLUTION__)) 1518 1519 /** 1520 * @brief Helper macro to calculate analog reference voltage (Vref+) 1521 * (unit: mVolt) from ADC conversion data of internal voltage 1522 * reference VrefInt. 1523 * @note Computation is using VrefInt calibration value 1524 * stored in system memory for each device during production. 1525 * @note This voltage depends on user board environment: voltage level 1526 * connected to pin Vref+. 1527 * On devices with small package, the pin Vref+ is not present 1528 * and internally bonded to pin Vdda. 1529 * @note On this STM32 series, calibration data of internal voltage reference 1530 * VrefInt corresponds to a resolution of 12 bits, 1531 * this is the recommended ADC resolution to convert voltage of 1532 * internal voltage reference VrefInt. 1533 * Otherwise, this macro performs the processing to scale 1534 * ADC conversion data to 12 bits. 1535 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) 1536 * of internal voltage reference VrefInt (unit: digital value). 1537 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1538 * @arg @ref ADC_RESOLUTION_12B 1539 * @arg @ref ADC_RESOLUTION_10B 1540 * @arg @ref ADC_RESOLUTION_8B 1541 * @arg @ref ADC_RESOLUTION_6B 1542 * @retval Analog reference voltage (unit: mV) 1543 */ 1544 #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ 1545 __ADC_RESOLUTION__) \ 1546 __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ 1547 (__ADC_RESOLUTION__)) 1548 1549 /** 1550 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 1551 * from ADC conversion data of internal temperature sensor. 1552 * @note Computation is using temperature sensor typical values 1553 * (refer to device datasheet). 1554 * @note Calculation formula: 1555 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) 1556 * / Avg_Slope + CALx_TEMP 1557 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 1558 * (unit: digital value) 1559 * Avg_Slope = temperature sensor slope 1560 * (unit: uV/Degree Celsius) 1561 * TS_TYP_CALx_VOLT = temperature sensor digital value at 1562 * temperature CALx_TEMP (unit: mV) 1563 * Caution: Calculation relevancy under reserve the temperature sensor 1564 * of the current device has characteristics in line with 1565 * datasheet typical values. 1566 * @note: On this STM32 series, calibtation parameter TS_CAL1 can be used 1567 * to improve calculation accuracy. 1568 * Refer to @ref TEMPSENSOR_CAL1_ADDR. 1569 * @note As calculation input, the analog reference voltage (Vref+) must be 1570 * defined as it impacts the ADC LSB equivalent voltage. 1571 * @note Analog reference voltage (Vref+) must be either known from 1572 * user board environment or can be calculated using ADC measurement 1573 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1574 * @note ADC measurement data must correspond to a resolution of 12bits 1575 * (full scale digital value 4095). If not the case, the data must be 1576 * preliminarily rescaled to an equivalent resolution of 12 bits. 1577 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). 1578 * On STM32C0, refer to device datasheet parameter "Avg_Slope". 1579 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). 1580 * On STM32C0, refer to device datasheet parameter "V30" (corresponding to TS_CAL1). 1581 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) 1582 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) 1583 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). 1584 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. 1585 * This parameter can be one of the following values: 1586 * @arg @ref ADC_RESOLUTION_12B 1587 * @arg @ref ADC_RESOLUTION_10B 1588 * @arg @ref ADC_RESOLUTION_8B 1589 * @arg @ref ADC_RESOLUTION_6B 1590 * @retval Temperature (unit: degree Celsius) 1591 */ 1592 #define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ 1593 __TEMPSENSOR_TYP_CALX_V__,\ 1594 __TEMPSENSOR_CALX_TEMP__,\ 1595 __VREFANALOG_VOLTAGE__,\ 1596 __TEMPSENSOR_ADC_DATA__,\ 1597 __ADC_RESOLUTION__) \ 1598 __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ 1599 (__TEMPSENSOR_TYP_CALX_V__),\ 1600 (__TEMPSENSOR_CALX_TEMP__),\ 1601 (__VREFANALOG_VOLTAGE__),\ 1602 (__TEMPSENSOR_ADC_DATA__),\ 1603 (__ADC_RESOLUTION__)) 1604 1605 /** 1606 * @} 1607 */ 1608 1609 /** 1610 * @} 1611 */ 1612 1613 /* Include ADC HAL Extended module */ 1614 #include "stm32c0xx_hal_adc_ex.h" 1615 1616 /* Exported functions --------------------------------------------------------*/ 1617 /** @addtogroup ADC_Exported_Functions 1618 * @{ 1619 */ 1620 1621 /** @addtogroup ADC_Exported_Functions_Group1 1622 * @brief Initialization and Configuration functions 1623 * @{ 1624 */ 1625 /* Initialization and de-initialization functions ****************************/ 1626 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); 1627 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 1628 void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); 1629 void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); 1630 1631 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 1632 /* Callbacks Register/UnRegister functions ***********************************/ 1633 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, 1634 pADC_CallbackTypeDef pCallback); 1635 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); 1636 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 1637 /** 1638 * @} 1639 */ 1640 1641 /** @addtogroup ADC_Exported_Functions_Group2 1642 * @brief IO operation functions 1643 * @{ 1644 */ 1645 /* IO operation functions *****************************************************/ 1646 1647 /* Blocking mode: Polling */ 1648 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); 1649 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); 1650 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); 1651 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); 1652 1653 /* Non-blocking mode: Interruption */ 1654 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); 1655 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); 1656 1657 /* Non-blocking mode: DMA */ 1658 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); 1659 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); 1660 1661 /* ADC retrieve conversion value intended to be used with polling or interruption */ 1662 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); 1663 1664 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ 1665 void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); 1666 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); 1667 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); 1668 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); 1669 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 1670 /** 1671 * @} 1672 */ 1673 1674 /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions 1675 * @brief Peripheral Control functions 1676 * @{ 1677 */ 1678 /* Peripheral Control functions ***********************************************/ 1679 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig); 1680 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig); 1681 1682 /** 1683 * @} 1684 */ 1685 1686 /* Peripheral State functions *************************************************/ 1687 /** @addtogroup ADC_Exported_Functions_Group4 1688 * @{ 1689 */ 1690 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc); 1691 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); 1692 1693 /** 1694 * @} 1695 */ 1696 1697 /** 1698 * @} 1699 */ 1700 1701 /* Private functions ---------------------------------------------------------*/ 1702 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc); 1703 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc); 1704 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc); 1705 1706 /** 1707 * @} 1708 */ 1709 1710 /** 1711 * @} 1712 */ 1713 1714 /** 1715 * @} 1716 */ 1717 1718 #ifdef __cplusplus 1719 } 1720 #endif 1721 1722 1723 #endif /* STM32C0xx_HAL_ADC_H */ 1724
