1 /** 2 ****************************************************************************** 3 * @file stm32c0xx_hal.h 4 * @author MCD Application Team 5 * @brief This file contains all the functions prototypes for the HAL 6 * module driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2022 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32C0xx_HAL_H 22 #define STM32C0xx_HAL_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32c0xx_ll_system.h" 30 #include "stm32c0xx_hal_conf.h" 31 32 /** @addtogroup STM32C0xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @defgroup HAL HAL 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /* Exported constants --------------------------------------------------------*/ 42 43 /** @defgroup HAL_Exported_Constants HAL Exported Constants 44 * @{ 45 */ 46 47 /** @defgroup HAL_TICK_FREQ Tick Frequency 48 * @{ 49 */ 50 51 typedef enum 52 { 53 HAL_TICK_FREQ_10HZ = 100U, 54 HAL_TICK_FREQ_100HZ = 10U, 55 HAL_TICK_FREQ_1KHZ = 1U, 56 HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ 57 } HAL_TickFreqTypeDef; 58 59 /** 60 * @} 61 */ 62 63 /** @defgroup HAL_BIND_CFG Bind Pin config 64 * @{ 65 */ 66 67 #if (DEV_ID == 0x443UL) 68 #define HAL_BIND_SO8_PIN1_PB7 LL_PINMUX_SO8_PIN1_PB7 /*!< STM32C011 SO8 package, Pin1 assigned to GPIO PB7 */ 69 #define HAL_BIND_SO8_PIN1_PC14 LL_PINMUX_SO8_PIN1_PC14 /*!< STM32C011 SO8 package, Pin1 assigned to GPIO PC14 */ 70 #define HAL_BIND_SO8_PIN4_PF2 LL_PINMUX_SO8_PIN4_PF2 /*!< STM32C011 SO8 package, Pin4 assigned to GPIO PF2 */ 71 #define HAL_BIND_SO8_PIN4_PA0 LL_PINMUX_SO8_PIN4_PA0 /*!< STM32C011 SO8 package, Pin4 assigned to GPIO PA0 */ 72 #define HAL_BIND_SO8_PIN4_PA1 LL_PINMUX_SO8_PIN4_PA1 /*!< STM32C011 SO8 package, Pin4 assigned to GPIO PA1 */ 73 #define HAL_BIND_SO8_PIN4_PA2 LL_PINMUX_SO8_PIN4_PA2 /*!< STM32C011 SO8 package, Pin4 assigned to GPIO PA2 */ 74 #define HAL_BIND_SO8_PIN5_PA8 LL_PINMUX_SO8_PIN5_PA8 /*!< STM32C011 SO8 package, Pin5 assigned to GPIO PA8*/ 75 #define HAL_BIND_SO8_PIN5_PA11 LL_PINMUX_SO8_PIN5_PA11 /*!< STM32C011 SO8 package, Pin5 assigned to GPIO PA11 */ 76 #define HAL_BIND_SO8_PIN8_PA14 LL_PINMUX_SO8_PIN8_PA14 /*!< STM32C011 SO8 package, Pin8 assigned to GPIO PA14 */ 77 #define HAL_BIND_SO8_PIN8_PB6 LL_PINMUX_SO8_PIN8_PB6 /*!< STM32C011 SO8 package, Pin8 assigned to GPIO PB6 */ 78 #define HAL_BIND_SO8_PIN8_PC15 LL_PINMUX_SO8_PIN8_PC15 /*!< STM32C011 SO8 package, Pin8 assigned to GPIO PC15 */ 79 #define HAL_BIND_WLCSP12_PINE2_PA7 LL_PINMUX_WLCSP12_PINE2_PA7 /*!< STM32C011 WLCSP12 package, PinE2 assigned to GPIO PA7 */ 80 #define HAL_BIND_WLCSP12_PINE2_PA12 LL_PINMUX_WLCSP12_PINE2_PA12 /*!< STM32C011 WLCSP12 package, PinE2 assigned to GPIO PA12*/ 81 #define HAL_BIND_WLCSP12_PINF1_PA3 LL_PINMUX_WLCSP12_PINF1_PA3 /*!< STM32C011 WLCSP12 package, PinF1 assigned to GPIO PA3 */ 82 #define HAL_BIND_WLCSP12_PINF1_PA4 LL_PINMUX_WLCSP12_PINF1_PA4 /*!< STM32C011 WLCSP12 package, PinF1 assigned to GPIO PA4 */ 83 #define HAL_BIND_WLCSP12_PINF1_PA5 LL_PINMUX_WLCSP12_PINF1_PA5 /*!< STM32C011 WLCSP12 package, PinF1 assigned to GPIO PA5 */ 84 #define HAL_BIND_WLCSP12_PINF1_PA6 LL_PINMUX_WLCSP12_PINF1_PA6 /*!< STM32C011 WLCSP12 package, PinF1 assigned to GPIO PA6 */ 85 #elif (DEV_ID == 0x453UL) 86 #define HAL_BIND_WLCSP14_PINF2_PA1 LL_PINMUX_WLCSP14_PINF2_PA1 /*!< STM32C031 WLCSP14 package, PinF2 assigned to GPIO PA1 */ 87 #define HAL_BIND_WLCSP14_PINF2_PA2 LL_PINMUX_WLCSP14_PINF2_PA2 /*!< STM32C031 WLCSP14 package, PinF2 assigned to GPIO PA2 */ 88 #define HAL_BIND_WLCSP14_PING3_PF2 LL_PINMUX_WLCSP14_PING3_PF2 /*!< STM32C031 WLCSP14 package, PinG3 assigned to GPIO PF2 */ 89 #define HAL_BIND_WLCSP14_PING3_PA0 LL_PINMUX_WLCSP14_PING3_PA0 /*!< STM32C031 WLCSP14 package, PinG3 assigned to GPIO PA0 */ 90 #define HAL_BIND_WLCSP14_PINJ1_PA8 LL_PINMUX_WLCSP14_PINJ1_PA8 /*!< STM32C031 WLCSP14 package, PinJ1 assigned to GPIO PA8 */ 91 #define HAL_BIND_WLCSP14_PINJ1_PA11 LL_PINMUX_WLCSP14_PINJ1_PA11 /*!< STM32C031 WLCSP14 package, PinJ1 assigned to GPIO PA11 */ 92 #define HAL_BIND_WLCSP14_PINH2_PA5 LL_PINMUX_WLCSP14_PINH2_PA5 /*!< STM32C031 WLCSP14 package, PinH2 assigned to GPIO PA5 */ 93 #define HAL_BIND_WLCSP14_PINH2_PA6 LL_PINMUX_WLCSP14_PINH2_PA6 /*!< STM32C031 WLCSP14 package, PinH2 assigned to GPIO PA6 */ 94 #define HAL_BIND_WLCSP14_PING1_PA7 LL_PINMUX_WLCSP14_PING1_PA7 /*!< STM32C031 WLCSP14 package, PinG1 assigned to GPIO PA7 */ 95 #define HAL_BIND_WLCSP14_PING1_PA12 LL_PINMUX_WLCSP14_PING1_PA12 /*!< STM32C031 WLCSP14 package, PinG1 assigned to GPIO PA12 */ 96 #define HAL_BIND_WLCSP14_PINJ3_PA3 LL_PINMUX_WLCSP14_PINJ3_PA3 /*!< STM32C031 WLCSP14 package, PinJ3 assigned to GPIO PA3 */ 97 #define HAL_BIND_WLCSP14_PINJ3_PA4 LL_PINMUX_WLCSP14_PINJ3_PA4 /*!< STM32C031 WLCSP14 package, PinJ3 assigned to GPIO PA4 */ 98 #endif /* DEV_ID == 0x443UL */ 99 100 /** 101 * @} 102 */ 103 104 /** @defgroup HAL_BIND_SCOURCE Bind Pin Source 105 * @{ 106 */ 107 #if (DEV_ID == 0x443UL) 108 #define HAL_BIND_SO8_PIN1 LL_PINMUX_SO8_PIN1 /*!< STM32C011 SO8 package, GPIO Pin1 multiplexer */ 109 #define HAL_BIND_SO8_PIN4 LL_PINMUX_SO8_PIN4 /*!< STM32C011 SO8 package, GPIO Pin4 multiplexer */ 110 #define HAL_BIND_SO8_PIN5 LL_PINMUX_SO8_PIN5 /*!< STM32C011 SO8 package, GPIO Pin5 multiplexer */ 111 #define HAL_BIND_SO8_PIN8 LL_PINMUX_SO8_PIN8 /*!< STM32C011 SO8 package, GPIO Pin8 multiplexer */ 112 #define HAL_BIND_WLCSP12_PINE2 LL_PINMUX_WLCSP12_PINE2 /*!< STM32C011 WLCSP12 package, GPIO PinE2 multiplexer */ 113 #define HAL_BIND_WLCSP12_PINF1 LL_PINMUX_WLCSP12_PINF1 /*!< STM32C011 WLCSP12 package, GPIO PinF1 multiplexer*/ 114 #elif (DEV_ID == 0x453UL) 115 #define HAL_BIND_WLCSP14_PINF2 LL_PINMUX_WLCSP14_PINF2 /*!< STM32C031 WLCSP14 package, GPIO PinF2 multiplexer */ 116 #define HAL_BIND_WLCSP14_PING3 LL_PINMUX_WLCSP14_PING3 /*!< STM32C031 WLCSP14 package, GPIO PinG3 multiplexer */ 117 #define HAL_BIND_WLCSP14_PINJ1 LL_PINMUX_WLCSP14_PINJ1 /*!< STM32C031 WLCSP14 package, GPIO PinJ1 multiplexer */ 118 #define HAL_BIND_WLCSP14_PINH2 LL_PINMUX_WLCSP14_PINH2 /*!< STM32C031 WLCSP14 package, GPIO PinH2 multiplexer */ 119 #define HAL_BIND_WLCSP14_PING1 LL_PINMUX_WLCSP14_PING1 /*!< STM32C031 WLCSP14 package, GPIO PinG1 multiplexer */ 120 #define HAL_BIND_WLCSP14_PINJ3 LL_PINMUX_WLCSP14_PINJ3 /*!< STM32C031 WLCSP14 package, GPIO PinJ3 multiplexer */ 121 #endif /* DEV_ID == 0x443UL */ 122 /** 123 * @} 124 */ 125 126 127 /** 128 * @} 129 */ 130 131 /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants 132 * @{ 133 */ 134 135 /** @defgroup SYSCFG_BootMode Boot Mode 136 * @{ 137 */ 138 #define SYSCFG_BOOT_MAINFLASH 0x00000000U /*!< Main Flash memory mapped at 0x0000 0000 */ 139 #define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /*!< System Flash memory mapped at 0x0000 0000 */ 140 #define SYSCFG_BOOT_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /*!< Embedded SRAM mapped at 0x0000 0000 */ 141 142 /** 143 * @} 144 */ 145 146 /** @defgroup SYSCFG_Break Break 147 * @{ 148 */ 149 #define SYSCFG_BREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM0+ with Break Input of TIM1/16/17 */ 150 /** 151 * @} 152 */ 153 154 /** @defgroup HAL_Pin_remapping Pin remapping 155 * @{ 156 */ 157 #define SYSCFG_REMAP_PA11 SYSCFG_CFGR1_PA11_RMP /*!< PA11 pad behaves digitally as PA9 GPIO pin */ 158 #define SYSCFG_REMAP_PA12 SYSCFG_CFGR1_PA12_RMP /*!< PA12 pad behaves digitally as PA10 GPIO pin */ 159 /** 160 * @} 161 */ 162 163 /** @defgroup HAL_IR_ENV_SEL IR Modulation Envelope signal selection 164 * @{ 165 */ 166 #define HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1) /*!< 00: Timer16 is selected as IR Modulation envelope source */ 167 #define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IR_MOD_0) /*!< 01: USART1 is selected as IR Modulation envelope source */ 168 #define HAL_SYSCFG_IRDA_ENV_SEL_USART2 (SYSCFG_CFGR1_IR_MOD_1) /*!< 10: USART2 is selected as IR Modulation envelope source */ 169 170 /** 171 * @} 172 */ 173 174 /** @defgroup HAL_IR_POL_SEL IR output polarity selection 175 * @{ 176 */ 177 #define HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED 0x00000000U /*!< 00: IR output polarity not inverted */ 178 #define HAL_SYSCFG_IRDA_POLARITY_INVERTED SYSCFG_CFGR1_IR_POL /*!< 01: IR output polarity inverted */ 179 180 /** 181 * @} 182 */ 183 /** @defgroup SYSCFG_FastModePlus_GPIO Fast mode Plus on GPIO 184 * @{ 185 */ 186 187 /** @brief Fast mode Plus driving capability on a specific GPIO 188 */ 189 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast mode Plus on PB6 */ 190 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast mode Plus on PB7 */ 191 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast mode Plus on PB8 */ 192 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast mode Plus on PB9 */ 193 #define SYSCFG_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_PA9_FMP /*!< Enable Fast mode Plus on PA9 */ 194 #define SYSCFG_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_PA10_FMP /*!< Enable Fast mode Plus on PA10 */ 195 #define SYSCFG_FASTMODEPLUS_PC14 SYSCFG_CFGR1_I2C_PC14_FMP /*!< Enable Fast mode Plus on PC14 */ 196 /** 197 * @} 198 */ 199 200 /** @defgroup SYSCFG_FastModePlus_I2Cx Fast mode Plus driving capability activation for I2Cx 201 * @{ 202 */ 203 204 /** @brief Fast mode Plus driving capability on a specific GPIO 205 */ 206 #define SYSCFG_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast mode Plus on I2C1 */ 207 208 /** 209 * @} 210 */ 211 212 /** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper 213 * @brief ISR Wrapper 214 * @{ 215 */ 216 #define HAL_SYSCFG_ITLINE0 0x00000000U /*!< Internal define for macro handling */ 217 #define HAL_SYSCFG_ITLINE2 0x00000002U /*!< Internal define for macro handling */ 218 #define HAL_SYSCFG_ITLINE3 0x00000003U /*!< Internal define for macro handling */ 219 #define HAL_SYSCFG_ITLINE4 0x00000004U /*!< Internal define for macro handling */ 220 #define HAL_SYSCFG_ITLINE5 0x00000005U /*!< Internal define for macro handling */ 221 #define HAL_SYSCFG_ITLINE6 0x00000006U /*!< Internal define for macro handling */ 222 #define HAL_SYSCFG_ITLINE7 0x00000007U /*!< Internal define for macro handling */ 223 #define HAL_SYSCFG_ITLINE9 0x00000009U /*!< Internal define for macro handling */ 224 #define HAL_SYSCFG_ITLINE10 0x0000000AU /*!< Internal define for macro handling */ 225 #define HAL_SYSCFG_ITLINE11 0x0000000BU /*!< Internal define for macro handling */ 226 #define HAL_SYSCFG_ITLINE12 0x0000000CU /*!< Internal define for macro handling */ 227 #define HAL_SYSCFG_ITLINE13 0x0000000DU /*!< Internal define for macro handling */ 228 #define HAL_SYSCFG_ITLINE14 0x0000000EU /*!< Internal define for macro handling */ 229 #define HAL_SYSCFG_ITLINE16 0x00000010U /*!< Internal define for macro handling */ 230 #define HAL_SYSCFG_ITLINE19 0x00000013U /*!< Internal define for macro handling */ 231 #define HAL_SYSCFG_ITLINE21 0x00000015U /*!< Internal define for macro handling */ 232 #define HAL_SYSCFG_ITLINE22 0x00000016U /*!< Internal define for macro handling */ 233 #define HAL_SYSCFG_ITLINE23 0x00000017U /*!< Internal define for macro handling */ 234 #define HAL_SYSCFG_ITLINE25 0x00000019U /*!< Internal define for macro handling */ 235 #define HAL_SYSCFG_ITLINE27 0x0000001BU /*!< Internal define for macro handling */ 236 #define HAL_SYSCFG_ITLINE28 0x0000001CU /*!< Internal define for macro handling */ 237 238 #define HAL_ITLINE_WWDG ((HAL_SYSCFG_ITLINE0 << 0x18U) | SYSCFG_ITLINE0_SR_WWDG) /*!< WWDG Interrupt */ 239 #define HAL_ITLINE_RTC ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC) /*!< RTC Interrupt */ 240 #define HAL_ITLINE_FLASH_ITF ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ITF) /*!< Flash ITF Interrupt */ 241 #define HAL_ITLINE_CLK_CTRL ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CLK_CTRL) /*!< CLK Control Interrupt */ 242 #define HAL_ITLINE_EXTI0 ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI0) /*!< External Interrupt 0 */ 243 #define HAL_ITLINE_EXTI1 ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI1) /*!< External Interrupt 1 */ 244 #define HAL_ITLINE_EXTI2 ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI2) /*!< External Interrupt 2 */ 245 #define HAL_ITLINE_EXTI3 ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI3) /*!< External Interrupt 3 */ 246 #define HAL_ITLINE_EXTI4 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI4) /*!< EXTI4 Interrupt */ 247 #define HAL_ITLINE_EXTI5 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI5) /*!< EXTI5 Interrupt */ 248 #define HAL_ITLINE_EXTI6 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI6) /*!< EXTI6 Interrupt */ 249 #define HAL_ITLINE_EXTI7 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI7) /*!< EXTI7 Interrupt */ 250 #define HAL_ITLINE_EXTI8 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI8) /*!< EXTI8 Interrupt */ 251 #define HAL_ITLINE_EXTI9 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI9) /*!< EXTI9 Interrupt */ 252 #define HAL_ITLINE_EXTI10 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI10) /*!< EXTI10 Interrupt */ 253 #define HAL_ITLINE_EXTI11 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI11) /*!< EXTI11 Interrupt */ 254 #define HAL_ITLINE_EXTI12 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI12) /*!< EXTI12 Interrupt */ 255 #define HAL_ITLINE_EXTI13 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI13) /*!< EXTI13 Interrupt */ 256 #define HAL_ITLINE_EXTI14 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI14) /*!< EXTI14 Interrupt */ 257 #define HAL_ITLINE_EXTI15 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI15) /*!< EXTI15 Interrupt */ 258 #define HAL_ITLINE_DMA1_CH1 ((HAL_SYSCFG_ITLINE9 << 0x18U) | SYSCFG_ITLINE9_SR_DMA1_CH1) /*!< DMA1 Channel 1 Interrupt */ 259 #define HAL_ITLINE_DMA1_CH2 ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH2) /*!< DMA1 Channel 2 Interrupt */ 260 #define HAL_ITLINE_DMA1_CH3 ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH3) /*!< DMA1 Channel 3 Interrupt */ 261 #define HAL_ITLINE_DMAMUX ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMAMUX) /*!< DMAMUX Interrupt */ 262 #define HAL_ITLINE_ADC ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_ADC) /*!< ADC Interrupt */ 263 #define HAL_ITLINE_TIM1_BRK ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_BRK) /*!< TIM1 BRK Interrupt */ 264 #define HAL_ITLINE_TIM1_UPD ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_UPD) /*!< TIM1 UPD Interrupt */ 265 #define HAL_ITLINE_TIM1_TRG ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_TRG) /*!< TIM1 TRG Interrupt */ 266 #define HAL_ITLINE_TIM1_CCU ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_CCU) /*!< TIM1 CCU Interrupt */ 267 #define HAL_ITLINE_TIM3 ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM3_GLB) /*!< TIM3 Interrupt */ 268 #define HAL_ITLINE_TIM14 ((HAL_SYSCFG_ITLINE19 << 0x18U) | SYSCFG_ITLINE19_SR_TIM14_GLB) /*!< TIM14 Interrupt */ 269 #define HAL_ITLINE_TIM16 ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_TIM16_GLB) /*!< TIM16 Interrupt */ 270 #define HAL_ITLINE_TIM17 ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_TIM17_GLB) /*!< TIM17 Interrupt */ 271 #define HAL_ITLINE_I2C1 ((HAL_SYSCFG_ITLINE23 << 0x18U) | SYSCFG_ITLINE23_SR_I2C1_GLB) /*!< I2C1 Interrupt */ 272 #define HAL_ITLINE_SPI1 ((HAL_SYSCFG_ITLINE25 << 0x18U) | SYSCFG_ITLINE25_SR_SPI1) /*!< SPI1 Interrupt */ 273 #define HAL_ITLINE_USART1 ((HAL_SYSCFG_ITLINE27 << 0x18U) | SYSCFG_ITLINE27_SR_USART1_GLB) /*!< USART1 GLB Interrupt */ 274 #define HAL_ITLINE_USART2 ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_USART2_GLB) /*!< USART2 GLB Interrupt */ 275 276 /** 277 * @} 278 */ 279 280 /** 281 * @} 282 */ 283 284 /* Exported macros -----------------------------------------------------------*/ 285 /** @defgroup HAL_Exported_Macros HAL Exported Macros 286 * @{ 287 */ 288 289 /** @defgroup DBG_Exported_Macros DBG Exported Macros 290 * @{ 291 */ 292 293 /** @brief Freeze and Unfreeze Peripherals in Debug mode 294 */ 295 296 #if defined(DBG_APB_FZ1_DBG_TIM3_STOP) 297 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM3_STOP) 298 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM3_STOP) 299 #endif 300 301 #if defined(DBG_APB_FZ1_DBG_RTC_STOP) 302 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_RTC_STOP) 303 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_RTC_STOP) 304 #endif 305 306 #if defined(DBG_APB_FZ1_DBG_WWDG_STOP) 307 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_WWDG_STOP) 308 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_WWDG_STOP) 309 #endif 310 311 #if defined(DBG_APB_FZ1_DBG_IWDG_STOP) 312 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP) 313 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP) 314 #endif 315 316 #if defined(DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP) 317 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP) 318 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP) 319 #endif 320 321 #if defined(DBG_APB_FZ2_DBG_TIM1_STOP) 322 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM1_STOP) 323 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM1_STOP) 324 #endif 325 326 #if defined(DBG_APB_FZ2_DBG_TIM14_STOP) 327 #define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP) 328 #define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP) 329 #endif 330 331 #if defined(DBG_APB_FZ2_DBG_TIM16_STOP) 332 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP) 333 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP) 334 #endif 335 336 #if defined(DBG_APB_FZ2_DBG_TIM17_STOP) 337 #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM17_STOP) 338 #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM17_STOP) 339 #endif 340 341 /** 342 * @} 343 */ 344 345 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros 346 * @{ 347 */ 348 349 /** 350 * @brief ISR wrapper check 351 * @note Allow to determine interrupt source per line. 352 */ 353 #define __HAL_GET_PENDING_IT(__SOURCE__) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFF)) 354 355 /** @brief Main Flash memory mapped at 0x00000000 356 */ 357 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE) 358 359 /** @brief System Flash memory mapped at 0x00000000 360 */ 361 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0) 362 363 /** @brief Embedded SRAM mapped at 0x00000000 364 */ 365 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() \ 366 MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, (SYSCFG_CFGR1_MEM_MODE_1|SYSCFG_CFGR1_MEM_MODE_0)) 367 368 /** 369 * @brief Return the boot mode as configured by user. 370 * @retval The boot mode as configured by user. The returned value can be one 371 * of the following values @ref SYSCFG_BootMode 372 */ 373 #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE) 374 375 /** @brief SYSCFG Break Cortex-M0+ Lockup lock. 376 * Enables and locks the connection of Cortex-M0+ LOCKUP (Hardfault) output to TIM1/16/17 Break input 377 * @note The selected configuration is locked and can be unlocked only by system reset. 378 */ 379 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL) 380 381 /** @brief Fast-mode Plus driving capability enable/disable macros 382 * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO 383 */ 384 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 385 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 386 }while(0U) 387 388 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 389 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 390 }while(0U) 391 392 393 /** @brief selection of the modulation envelope signal macro, using bits [7:6] of SYSCFG_CFGR1 register 394 * @param __SOURCE__ This parameter can be a value of @ref HAL_IR_ENV_SEL 395 */ 396 #define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__)));\ 397 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD);\ 398 SET_BIT(SYSCFG->CFGR1, (__SOURCE__));\ 399 }while(0U) 400 401 #define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION() ((SYSCFG->CFGR1) & 0x000000C0U) 402 403 /** @brief IROut Polarity Selection, using bit[5] of SYSCFG_CFGR1 register 404 * @param __SEL__ This parameter can be a value of @ref HAL_IR_POL_SEL 405 */ 406 #define __HAL_SYSCFG_IRDA_OUT_POLARITY_SELECTION(__SEL__) do { assert_param(IS_HAL_SYSCFG_IRDA_POL_SEL((__SEL__)));\ 407 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL);\ 408 SET_BIT(SYSCFG->CFGR1,(__SEL__));\ 409 }while(0U) 410 411 /** 412 * @brief Return the IROut Polarity mode as configured by user. 413 * @retval The IROut polarity as configured by user. The returned value can be one 414 * of @ref HAL_IR_POL_SEL 415 */ 416 #define __HAL_SYSCFG_GET_POLARITY() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL) 417 418 /** @brief Break input to TIM1/16/17 capability enable/disable macros 419 * @param __BREAK__ This parameter can be a value of @ref SYSCFG_Break 420 */ 421 #define __HAL_SYSCFG_BREAK_ENABLE(__BREAK__) do {assert_param(IS_SYSCFG_BREAK_CONFIG((__BREAK__)));\ 422 SET_BIT(SYSCFG->CFGR2, (__BREAK__));\ 423 }while(0U) 424 425 #define __HAL_SYSCFG_BREAK_DISABLE(__BREAK__) do {assert_param(IS_SYSCFG_BREAK_CONFIG((__BREAK__)));\ 426 CLEAR_BIT(SYSCFG->CFGR2, (__BREAK__));\ 427 }while(0U) 428 /** 429 * @} 430 */ 431 432 /* Private macros ------------------------------------------------------------*/ 433 /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros 434 * @{ 435 */ 436 437 #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) ((__CONFIG__) == SYSCFG_BREAK_LOCKUP) 438 439 #define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \ 440 ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \ 441 ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART2)) 442 443 #define IS_HAL_SYSCFG_IRDA_POL_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED) || \ 444 ((SEL) == HAL_SYSCFG_IRDA_POLARITY_INVERTED)) 445 446 447 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PC14) == SYSCFG_FASTMODEPLUS_PC14) || \ 448 (((__PIN__) & SYSCFG_FASTMODEPLUS_PA9) == SYSCFG_FASTMODEPLUS_PA9) || \ 449 (((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \ 450 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 451 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 452 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ 453 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) 454 455 #define IS_HAL_REMAP_PIN(RMP) (((RMP) == SYSCFG_REMAP_PA11) || \ 456 ((RMP) == SYSCFG_REMAP_PA12) || \ 457 ((RMP) == (SYSCFG_REMAP_PA11 | SYSCFG_REMAP_PA12))) 458 #if (DEV_ID == 0x443UL) 459 #define IS_HAL_SYSCFG_PINBINDING(PIN) (((PIN) == HAL_BIND_SO8_PIN1_PB7) || \ 460 ((PIN) == HAL_BIND_SO8_PIN1_PC14) || \ 461 ((PIN) == HAL_BIND_SO8_PIN4_PF2) || \ 462 ((PIN) == HAL_BIND_SO8_PIN4_PA0) || \ 463 ((PIN) == HAL_BIND_SO8_PIN4_PA1) || \ 464 ((PIN) == HAL_BIND_SO8_PIN4_PA2) || \ 465 ((PIN) == HAL_BIND_SO8_PIN5_PA8) || \ 466 ((PIN) == HAL_BIND_SO8_PIN5_PA11) || \ 467 ((PIN) == HAL_BIND_SO8_PIN8_PA14) || \ 468 ((PIN) == HAL_BIND_SO8_PIN8_PB6) || \ 469 ((PIN) == HAL_BIND_SO8_PIN8_PC15) || \ 470 ((PIN) == HAL_BIND_WLCSP12_PINE2_PA7) || \ 471 ((PIN) == HAL_BIND_WLCSP12_PINE2_PA12) || \ 472 ((PIN) == HAL_BIND_WLCSP12_PINF1_PA3) || \ 473 ((PIN) == HAL_BIND_WLCSP12_PINF1_PA4) || \ 474 ((PIN) == HAL_BIND_WLCSP12_PINF1_PA5) || \ 475 ((PIN) == HAL_BIND_WLCSP12_PINF1_PA6)) 476 #elif (DEV_ID == 0x453UL) 477 #define IS_HAL_SYSCFG_PINBINDING(PIN) (((PIN) == HAL_BIND_WLCSP14_PINF2_PA1) || \ 478 ((PIN) == HAL_BIND_WLCSP14_PINF2_PA2) || \ 479 ((PIN) == HAL_BIND_WLCSP14_PING3_PF2) || \ 480 ((PIN) == HAL_BIND_WLCSP14_PING3_PA0) || \ 481 ((PIN) == HAL_BIND_WLCSP14_PINJ1_PA8) || \ 482 ((PIN) == HAL_BIND_WLCSP14_PINJ1_PA11) || \ 483 ((PIN) == HAL_BIND_WLCSP14_PINH2_PA5) || \ 484 ((PIN) == HAL_BIND_WLCSP14_PINH2_PA6) || \ 485 ((PIN) == HAL_BIND_WLCSP14_PING1_PA7) || \ 486 ((PIN) == HAL_BIND_WLCSP14_PING1_PA12)|| \ 487 ((PIN) == HAL_BIND_WLCSP14_PINJ3_PA3) || \ 488 ((PIN) == HAL_BIND_WLCSP14_PINJ3_PA4)) 489 #endif 490 /** 491 * @} 492 */ 493 494 /** @defgroup HAL_Private_Macros HAL Private Macros 495 * @{ 496 */ 497 #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ 498 ((FREQ) == HAL_TICK_FREQ_100HZ) || \ 499 ((FREQ) == HAL_TICK_FREQ_1KHZ)) 500 /** 501 * @} 502 */ 503 /* Exported functions --------------------------------------------------------*/ 504 505 /** @defgroup HAL_Exported_Functions HAL Exported Functions 506 * @{ 507 */ 508 509 /** @defgroup HAL_Exported_Functions_Group1 HAL Initialization and Configuration functions 510 * @{ 511 */ 512 513 /* Initialization and Configuration functions ******************************/ 514 HAL_StatusTypeDef HAL_Init(void); 515 HAL_StatusTypeDef HAL_DeInit(void); 516 void HAL_MspInit(void); 517 void HAL_MspDeInit(void); 518 HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); 519 520 /** 521 * @} 522 */ 523 524 /** @defgroup HAL_Exported_Functions_Group2 HAL Control functions 525 * @{ 526 */ 527 528 /* Peripheral Control functions ************************************************/ 529 void HAL_IncTick(void); 530 void HAL_Delay(uint32_t Delay); 531 uint32_t HAL_GetTick(void); 532 uint32_t HAL_GetTickPrio(void); 533 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); 534 HAL_TickFreqTypeDef HAL_GetTickFreq(void); 535 void HAL_SuspendTick(void); 536 void HAL_ResumeTick(void); 537 uint32_t HAL_GetHalVersion(void); 538 uint32_t HAL_GetREVID(void); 539 uint32_t HAL_GetDEVID(void); 540 uint32_t HAL_GetUIDw0(void); 541 uint32_t HAL_GetUIDw1(void); 542 uint32_t HAL_GetUIDw2(void); 543 544 /** 545 * @} 546 */ 547 548 /** @defgroup HAL_Exported_Functions_Group3 DBGMCU Control functions 549 * @{ 550 */ 551 552 /* DBGMCU Peripheral Control functions *****************************************/ 553 void HAL_DBGMCU_EnableDBGStopMode(void); 554 void HAL_DBGMCU_DisableDBGStopMode(void); 555 void HAL_DBGMCU_EnableDBGStandbyMode(void); 556 void HAL_DBGMCU_DisableDBGStandbyMode(void); 557 558 /** 559 * @} 560 */ 561 562 /* Exported variables ---------------------------------------------------------*/ 563 /** @addtogroup HAL_Exported_Variables 564 * @{ 565 */ 566 extern __IO uint32_t uwTick; 567 extern uint32_t uwTickPrio; 568 extern HAL_TickFreqTypeDef uwTickFreq; 569 /** 570 * @} 571 */ 572 573 /** @defgroup HAL_Exported_Functions_Group4 SYSCFG configuration functions 574 * @{ 575 */ 576 577 /* SYSCFG Control functions ****************************************************/ 578 579 void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); 580 void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); 581 void HAL_SYSCFG_EnableRemap(uint32_t PinRemap); 582 void HAL_SYSCFG_DisableRemap(uint32_t PinRemap); 583 void HAL_SYSCFG_SetPinBinding(uint32_t pin_binding); 584 uint32_t HAL_SYSCFG_GetPinBinding(uint32_t pin_binding_source); 585 /** 586 * @} 587 */ 588 589 /** 590 * @} 591 */ 592 593 /** 594 * @} 595 */ 596 597 /** 598 * @} 599 */ 600 601 /** 602 * @} 603 */ 604 #ifdef __cplusplus 605 } 606 #endif 607 608 #endif /* STM32C0xx_HAL_H */ 609
