1# Configuration file for pinctrl generation (except F1 series).
2#
3# This file contains a list of pin configuration templates used to generate the
4# pinctrl files. Each entry can have the following fields:
5#
6#   - name (mandatory): This is the pin function name, e.g. UART_TX. It is used
7#     to group pin configurations alphabetically in the generated pinctrl files.
8#
9#   - match (mandatory): This is a regular expression used to match against
10#     STM32 xml database pin configuration names. The regular expression should
11#     be as precise as possible. Note that it needs to be escaped here in the
12#     configuration file.
13#     Note: Specific "ANALOG" value allows generation of analog pins
14#     configuration
15#
16#   - mode (optional): Mode setting (analog, alternate). Mode needs to
17#     be set according to the following rules:
18#       * Pin operates in analog configuration: analog
19#       * Pin operates in alternate function configuration: alternate
20#     In default case, mode could be infered from CubeMX SoC description files
21#     and can be omitted.
22#
23#   - bias (optional): Bias setting (disable, pull-up, pull-down). Equivalent to
24#     "disable" (a.k.a floating) if not set.
25#
26#   - drive (optional): Drive setting (push-pull, open-drain). Equivalent to
27#     "push-pull" if not set.
28#
29#   - slew-rate (optional): Slew rate setting (low-speed, medium-speed,
30#     high-speed, very-high-speed). Equivalent to "low-speed" if not set.
31#
32#   - variant (optional): Defines an alternative pin configuration. This is used
33#     to provide multiple configurations of a pin function (slave, master,
34#     low-power, ...).
35#
36
37---
38- name: Analog
39  match: "ANALOG"
40  mode: analog
41
42- name: ADC_IN / ADC_INN / ADC_INP
43  match: "^ADC(?:\\d+)?_IN[NP]?\\d+$"
44
45- name: CAN_RX
46  match: "^CAN\\d*_RX$"
47  bias: pull-up
48
49- name: CAN_TX
50  match: "^CAN\\d*_TX$"
51
52- name: DAC_OUT
53  match: "^DAC(?:\\d+)?_OUT\\d+$"
54
55- name: ETH_COL
56  match: "^ETH_COL$"
57  slew-rate: very-high-speed
58
59- name: ETH_CRS
60  match: "^ETH_CRS$"
61  slew-rate: very-high-speed
62
63- name: ETH_CRS_DV
64  match: "^ETH_CRS_DV$"
65  slew-rate: very-high-speed
66
67- name: ETH_MDC
68  match: "^ETH_MDC$"
69  slew-rate: very-high-speed
70
71- name: ETH_MDIO
72  match: "^ETH_MDIO$"
73  slew-rate: very-high-speed
74
75- name: ETH_PPS_OUT
76  match: "^ETH_PPS_OUT$"
77  slew-rate: very-high-speed
78
79- name: ETH_REF_CLK
80  match: "^ETH_REF_CLK$"
81  slew-rate: very-high-speed
82
83- name: ETH_RX_CLK
84  match: "^ETH_RX_CLK$"
85  slew-rate: very-high-speed
86
87- name: ETH_RX_DV
88  match: "^ETH_RX_DV$"
89  slew-rate: very-high-speed
90
91- name: ETH_RX_ER
92  match: "^ETH_RX_ER$"
93  slew-rate: very-high-speed
94
95- name: ETH_RXD0
96  match: "^ETH_RXD0$"
97  slew-rate: very-high-speed
98
99- name: ETH_RXD1
100  match: "^ETH_RXD1$"
101  slew-rate: very-high-speed
102
103- name: ETH_RXD2
104  match: "^ETH_RXD2$"
105  slew-rate: very-high-speed
106
107- name: ETH_RXD3
108  match: "^ETH_RXD3$"
109  slew-rate: very-high-speed
110
111- name: ETH_TX_CLK
112  match: "^ETH_TX_CLK$"
113  slew-rate: very-high-speed
114
115- name: ETH_TX_EN
116  match: "^ETH_TX_EN$"
117  slew-rate: very-high-speed
118
119- name: ETH_TXD0
120  match: "^ETH_TXD0$"
121  slew-rate: very-high-speed
122
123- name: ETH_TXD1
124  match: "^ETH_TXD1$"
125  slew-rate: very-high-speed
126
127- name: ETH_TXD2
128  match: "^ETH_TXD2$"
129  slew-rate: very-high-speed
130
131- name: ETH_TXD3
132  match: "^ETH_TXD3$"
133  slew-rate: very-high-speed
134
135- name: FDCAN_RX
136  match: "^FDCAN\\d+_RX$"
137
138- name: FDCAN_TX
139  match: "^FDCAN\\d+_TX$"
140
141- name: FMC
142  match: "^FMC_(?:NL|NADV|CLK|NBL[0-3]|A\\d+|D\\d+|NE[1-4]|NOE|NWE|NWAIT|NCE|INT|SDCLK|SDNWE|SDCKE[0-1]|SDNE[0-1]|SDNRAS|SDNCAS)$"
143  bias: pull-up
144  slew-rate: very-high-speed
145
146- name: HRTIM_CH
147  match: "^HRTIM\\d+_CH[A-F]\\d+$"
148
149- name: HRTIM_EEV
150  match: "^HRTIM\\d+_EEV\\d+$"
151
152- name: HRTIM_FLT
153  match: "^HRTIM\\d+_FLT[A-F]\\d+$"
154
155- name: HRTIM_SCIN / HRTIM_SCOUT
156  match: "^HRTIM\\d+_SC(IN|OUT)$"
157
158- name: I2C_SCL
159  match: "^I2C\\d+_SCL$"
160  drive: open-drain
161  bias: pull-up
162
163- name: I2C_SDA
164  match: "^I2C\\d+_SDA$"
165  drive: open-drain
166  bias: pull-up
167
168- name: I2S_MCK
169  match: "^I2S\\d+_MCK$"
170  slew-rate: very-high-speed
171
172- name: I2S_CK
173  match: "^I2S\\d+_CK$"
174  slew-rate: very-high-speed
175
176- name: I2S_WS
177  match: "^I2S\\d+_WS$"
178
179- name: I2S_SD
180  match: "^I2S\\d+_SD$"
181
182- name: LTDC
183  match: "^LTDC_(?:DE|CLK|HSYNC|VSYNC|R[0-7]|G[0-7]|B[0-7])$"
184
185- name: OCTOSPI
186  match: "^OCTOSPI(.*)(?:CLK|NCS|DQS|IO[0-7])$"
187  slew-rate: very-high-speed
188
189- name: QUADSPI
190  match: "^QUADSPI(\\d+)?_(?:CLK|NCS|BK1_NCS|BK1_IO[0-3]|BK2_NCS|BK2_IO[0-3])$"
191  slew-rate: very-high-speed
192
193- name: SDMMC
194  match: "^SDMMC\\d+_(?:CK)?(?:CKIN)?(?:CDIR)?(?:CMD)?(?:D\\d+)?(?:D0DIR)?(?:D123DIR)?$"
195  slew-rate: very-high-speed
196  bias: pull-up
197
198- name: SDIO
199  match: "^SDIO_(?:CK)?(?:CKIN)?(?:CDIR)?(?:CMD)?(?:D\\d+)?(?:D0DIR)?(?:D123DIR)?$"
200  slew-rate: very-high-speed
201  bias: pull-up
202
203- name: SPI_MISO
204  match: "^SPI\\d+_MISO$"
205  bias: pull-down
206
207- name: SPI_MOSI
208  match: "^SPI\\d+_MOSI$"
209  bias: pull-down
210
211# NOTE: The SPI_SCK pins speed must be set to very-high-speed to avoid last data
212# bit corruption which is a known issue on multiple STM32F4 series SPI
213# peripheral (ref. ES0182 Rev 12, 2.5.12, p. 22).
214- name: SPI_SCK
215  match: "^SPI\\d+_SCK$"
216  slew-rate: very-high-speed
217  bias: pull-down
218
219- name: SPI_NSS
220  match: "^SPI\\d+_NSS$"
221  bias: pull-up
222
223- name: TIM_BKIN
224  match: "^TIM\\d+_BKIN\\d?$"
225
226- name: TIM_CH / TIM_CHN
227  match: "^TIM\\d+_CH\\d+N?$"
228
229- name: UART_CTS / USART_CTS / LPUART_CTS
230  match: "^(?:LP)?US?ART\\d+_CTS$"
231  drive: open-drain
232  bias: pull-up
233
234- name: UART_RTS / USART_RTS / LPUART_RTS
235  match: "^(?:LP)?US?ART\\d+_RTS$"
236  drive: open-drain
237  bias: pull-up
238
239- name: UART_DE / USART_DE / LPUART_DE
240  match: "^(?:LP)?US?ART\\d+_DE$"
241  drive: push-pull
242
243- name: UART_TX / USART_TX / LPUART_TX
244  match: "^(?:LP)?US?ART\\d+_TX$"
245  bias: pull-up
246
247- name: UART_RX / USART_RX / LPUART_RX
248  match: "^(?:LP)?US?ART\\d+_RX$"
249
250- name: UCPD
251  match: "^UCPD\\d+_CC\\d+N?$"
252  mode: analog
253
254- name: USB_OTG_FS
255  match: "^USB_OTG_FS_(?:DM)?(?:DP)?(?:SOF)?(?:ID)?(?:VBUS)?$"
256
257- name: USB_OTG_HS
258  match: "^USB_OTG_HS_(?:DM)?(?:DP)?(?:SOF)?(?:ID)?(?:VBUS)?$"
259
260- name: USB_OTG_HS_ULPI
261  match: "^USB_OTG_HS_ULPI_(?:CK)?(?:DIR)?(?:STP)?(?:NXT)?(?:D\\d+)?$"
262  slew-rate: high-speed
263
264- name: USB
265  match: "^USB_(?:DM)?(?:DP)?(?:NOE)?$"
266