1 /** 2 ****************************************************************************** 3 * @file stm32wle5xx.h 4 * @author MCD Application Team 5 * @brief CMSIS Cortex Device Peripheral Access Layer Header File. 6 * This file contains all the peripheral register's definitions, bits 7 * definitions and memory mapping for stm32wle5xx devices. 8 * 9 * This file contains:selected 10 * - Data structures and the address mapping for all peripherals 11 * - Peripheral's registers declarations and bits definition 12 * - Macros to access peripheral's registers hardware 13 * 14 ****************************************************************************** 15 * @attention 16 * 17 * Copyright (c) 2020-2021 STMicroelectronics. 18 * All rights reserved. 19 * 20 * This software is licensed under terms that can be found in the LICENSE file 21 * in the root directory of this software component. 22 * If no LICENSE file comes with this software, it is provided AS-IS. 23 * 24 ****************************************************************************** 25 */ 26 27 /** @addtogroup CMSIS_Device 28 * @{ 29 */ 30 31 /** @addtogroup stm32wle5xx 32 * @{ 33 */ 34 35 #ifndef __STM32WLE5xx_H 36 #define __STM32WLE5xx_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif /* __cplusplus */ 41 42 43 44 /** @addtogroup Peripheral_interrupt_number_definition 45 * @{ 46 */ 47 48 /** 49 * @brief stm32wle5xx Interrupt Number Definition, according to the selected device 50 * in @ref Library_configuration_section 51 */ 52 /*!< Interrupt Number Definition for M4 */ 53 typedef enum 54 { 55 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ 56 NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt */ 57 HardFault_IRQn = -13, /*!< Cortex-M4 Hard Fault Interrupt */ 58 MemoryManagement_IRQn = -12, /*!< Cortex-M4 Memory Management Interrupt */ 59 BusFault_IRQn = -11, /*!< Cortex-M4 Bus Fault Interrupt */ 60 UsageFault_IRQn = -10, /*!< Cortex-M4 Usage Fault Interrupt */ 61 SVCall_IRQn = -5, /*!< Cortex-M4 SV Call Interrupt */ 62 DebugMonitor_IRQn = -4, /*!< Cortex-M4 Debug Monitor Interrupt */ 63 PendSV_IRQn = -2, /*!< Cortex-M4 Pend SV Interrupt */ 64 SysTick_IRQn = -1, /*!< Cortex-M4 System Tick Interrupt */ 65 66 /************* STM32WLxx specific Interrupt Numbers on M4 core ************************************************/ 67 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 68 PVD_PVM_IRQn = 1, /*!< PVD and PVM detector */ 69 TAMP_STAMP_LSECSS_SSRU_IRQn = 2, /*!< RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts */ 70 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Interrupt */ 71 FLASH_IRQn = 4, /*!< FLASH (CFI) global Interrupt */ 72 RCC_IRQn = 5, /*!< RCC Interrupt */ 73 EXTI0_IRQn = 6, /*!< EXTI Line 0 Interrupt */ 74 EXTI1_IRQn = 7, /*!< EXTI Line 1 Interrupt */ 75 EXTI2_IRQn = 8, /*!< EXTI Line 2 Interrupt */ 76 EXTI3_IRQn = 9, /*!< EXTI Line 3 Interrupt */ 77 EXTI4_IRQn = 10, /*!< EXTI Line 4 Interrupt */ 78 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ 79 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ 80 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ 81 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ 82 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ 83 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ 84 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ 85 ADC_IRQn = 18, /*!< ADC Interrupt */ 86 DAC_IRQn = 19, /*!< DAC Interrupt */ 87 COMP_IRQn = 21, /*!< COMP1 and COMP2 Interrupts */ 88 EXTI9_5_IRQn = 22, /*!< EXTI Lines [9:5] Interrupt */ 89 TIM1_BRK_IRQn = 23, /*!< TIM1 Break Interrupt */ 90 TIM1_UP_IRQn = 24, /*!< TIM1 Update Interrupt */ 91 TIM1_TRG_COM_IRQn = 25, /*!< TIM1 Trigger and Communication Interrupts */ 92 TIM1_CC_IRQn = 26, /*!< TIM1 Capture Compare Interrupt */ 93 TIM2_IRQn = 27, /*!< TIM2 Global Interrupt */ 94 TIM16_IRQn = 28, /*!< TIM16 Global Interrupt */ 95 TIM17_IRQn = 29, /*!< TIM17 Global Interrupt */ 96 I2C1_EV_IRQn = 30, /*!< I2C1 Event Interrupt */ 97 I2C1_ER_IRQn = 31, /*!< I2C1 Error Interrupt */ 98 I2C2_EV_IRQn = 32, /*!< I2C2 Event Interrupt */ 99 I2C2_ER_IRQn = 33, /*!< I2C2 Error Interrupt */ 100 SPI1_IRQn = 34, /*!< SPI1 Interrupt */ 101 SPI2_IRQn = 35, /*!< SPI2 Interrupt */ 102 USART1_IRQn = 36, /*!< USART1 Interrupt */ 103 USART2_IRQn = 37, /*!< USART2 Interrupt */ 104 LPUART1_IRQn = 38, /*!< LPUART1 Interrupt */ 105 LPTIM1_IRQn = 39, /*!< LPTIM1 Global Interrupt */ 106 LPTIM2_IRQn = 40, /*!< LPTIM2 Global Interrupt */ 107 EXTI15_10_IRQn = 41, /*!< EXTI Lines [15:10] Interrupt */ 108 RTC_Alarm_IRQn = 42, /*!< RTC Alarms (A and B) Interrupt */ 109 LPTIM3_IRQn = 43, /*!< LPTIM3 Global Interrupt */ 110 SUBGHZSPI_IRQn = 44, /*!< SUBGHZSPI Interrupt */ 111 HSEM_IRQn = 47, /*!< HSEM Interrupt */ 112 I2C3_EV_IRQn = 48, /*!< I2C3 Event Interrupt */ 113 I2C3_ER_IRQn = 49, /*!< I2C3 Error Interrupt */ 114 SUBGHZ_Radio_IRQn = 50, /*!< SUBGHZ Radio Interrupt */ 115 AES_IRQn = 51, /*!< AES Interrupt */ 116 RNG_IRQn = 52, /*!< RNG Interrupt */ 117 PKA_IRQn = 53, /*!< PKA Interrupt */ 118 DMA2_Channel1_IRQn = 54, /*!< DMA2 Channel 1 Interrupt */ 119 DMA2_Channel2_IRQn = 55, /*!< DMA2 Channel 2 Interrupt */ 120 DMA2_Channel3_IRQn = 56, /*!< DMA2 Channel 3 Interrupt */ 121 DMA2_Channel4_IRQn = 57, /*!< DMA2 Channel 4 Interrupt */ 122 DMA2_Channel5_IRQn = 58, /*!< DMA2 Channel 5 Interrupt */ 123 DMA2_Channel6_IRQn = 59, /*!< DMA2 Channel 6 Interrupt */ 124 DMA2_Channel7_IRQn = 60, /*!< DMA2 Channel 7 Interrupt */ 125 DMAMUX1_OVR_IRQn = 61 /*!< DMAMUX1 overrun Interrupt */ 126 } IRQn_Type; 127 /** 128 * @} 129 */ 130 131 /** @addtogroup Configuration_section_for_CMSIS 132 * @{ 133 */ 134 /** 135 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 136 */ 137 #define __CM4_REV 1U /*!< Core Revision r0p1 */ 138 #define __MPU_PRESENT 1U /*!< M4 provides an MPU */ 139 #define __VTOR_PRESENT 1U /*!< Vector Table Register supported */ 140 #define __NVIC_PRIO_BITS 4U /*!< STM32WLxx uses 4 Bits for the Priority Levels */ 141 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ 142 #define __FPU_PRESENT 0U /*!< FPU not present */ 143 144 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ 145 146 147 #include "system_stm32wlxx.h" 148 #include <stdint.h> 149 150 /** 151 * @} 152 */ 153 154 155 156 157 158 /** @addtogroup Peripheral_registers_structures 159 * @{ 160 */ 161 162 /** 163 * @brief Analog to Digital Converter 164 */ 165 typedef struct 166 { 167 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ 168 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ 169 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ 170 __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ 171 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ 172 __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ 173 uint32_t RESERVED1; /*!< Reserved, 0x18 */ 174 uint32_t RESERVED2; /*!< Reserved, 0x1C */ 175 __IO uint32_t AWD1TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ 176 __IO uint32_t AWD2TR; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ 177 __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ 178 __IO uint32_t AWD3TR; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */ 179 uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */ 180 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ 181 uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */ 182 __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ 183 __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ 184 uint32_t RESERVED5[3]; /*!< Reserved, 0xA8 - 0xB0 */ 185 __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xB4 */ 186 } ADC_TypeDef; 187 188 typedef struct 189 { 190 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC base address + 0x308 */ 191 } ADC_Common_TypeDef; 192 193 /* Legacy registers naming */ 194 #define TR1 AWD1TR 195 #define TR2 AWD2TR 196 #define TR3 AWD3TR 197 198 /** 199 * @brief AES hardware accelerator 200 */ 201 typedef struct 202 { 203 __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ 204 __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ 205 __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ 206 __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ 207 __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ 208 __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ 209 __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ 210 __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ 211 __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ 212 __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ 213 __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ 214 __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ 215 __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ 216 __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ 217 __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ 218 __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ 219 __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ 220 __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ 221 __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ 222 __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ 223 __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ 224 __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ 225 __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ 226 __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x6C */ 227 } AES_TypeDef; 228 229 /** 230 * @brief Comparator 231 */ 232 typedef struct 233 { 234 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ 235 } COMP_TypeDef; 236 237 typedef struct 238 { 239 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ 240 } COMP_Common_TypeDef; 241 242 /** 243 * @brief CRC calculation unit 244 */ 245 typedef struct 246 { 247 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ 248 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ 249 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ 250 uint32_t RESERVED2; /*!< Reserved, 0x0C */ 251 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ 252 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ 253 } CRC_TypeDef; 254 255 /** 256 * @brief Digital to Analog Converter 257 */ 258 typedef struct 259 { 260 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ 261 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ 262 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ 263 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ 264 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ 265 uint32_t RESERVED1; /*!< Reserved Address offset: 0x14 */ 266 uint32_t RESERVED2; /*!< Reserved Address offset: 0x18 */ 267 uint32_t RESERVED3; /*!< Reserved Address offset: 0x1C */ 268 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ 269 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ 270 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ 271 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ 272 uint32_t RESERVED4; /*!< Reserved Address offset: 0x30 */ 273 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ 274 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ 275 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ 276 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ 277 uint32_t RESERVED5; /*!< Reserved Address offset: 0x44 */ 278 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ 279 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ 280 } DAC_TypeDef; 281 282 /** 283 * @brief Debug MCU 284 */ 285 typedef struct 286 { 287 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ 288 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ 289 uint32_t RESERVED1[13]; /*!< Reserved, 0x08-0x38 */ 290 __IO uint32_t APB1FZR1; /*!< Debug MCU CPU1 APB1 freeze register, Address offset: 0x3C */ 291 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x40 */ 292 __IO uint32_t APB1FZR2; /*!< Debug MCU CPU1 APB1 freeze register, Address offset: 0x44 */ 293 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */ 294 __IO uint32_t APB2FZR; /*!< Debug MCU CPU1 APB2 freeze register, Address offset: 0x4C */ 295 } DBGMCU_TypeDef; 296 297 /** 298 * @brief DMA Controller 299 */ 300 typedef struct 301 { 302 __IO uint32_t CCR; /*!< DMA channel x configuration register */ 303 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ 304 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ 305 __IO uint32_t CMAR; /*!< DMA channel x memory address register */ 306 } DMA_Channel_TypeDef; 307 308 typedef struct 309 { 310 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ 311 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ 312 } DMA_TypeDef; 313 314 /** 315 * @brief DMA Multiplexer 316 */ 317 typedef struct 318 { 319 __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ 320 }DMAMUX_Channel_TypeDef; 321 322 typedef struct 323 { 324 __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ 325 __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ 326 }DMAMUX_ChannelStatus_TypeDef; 327 328 typedef struct 329 { 330 __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ 331 }DMAMUX_RequestGen_TypeDef; 332 333 typedef struct 334 { 335 __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ 336 __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ 337 }DMAMUX_RequestGenStatus_TypeDef; 338 339 /** 340 * @brief Async Interrupts and Events Controller 341 */ 342 typedef struct 343 { 344 __IO uint32_t RTSR1; /*!< EXTI rising trigger selection register [31:0], Address offset: 0x00 */ 345 __IO uint32_t FTSR1; /*!< EXTI falling trigger selection register [31:0], Address offset: 0x04 */ 346 __IO uint32_t SWIER1; /*!< EXTI software interrupt event register [31:0], Address offset: 0x08 */ 347 __IO uint32_t PR1; /*!< EXTI pending register [31:0], Address offset: 0x0C */ 348 __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x10 - 0x1C */ 349 __IO uint32_t RTSR2; /*!< EXTI rising trigger selection register [31:0], Address offset: 0x20 */ 350 __IO uint32_t FTSR2; /*!< EXTI falling trigger selection register [31:0], Address offset: 0x24 */ 351 __IO uint32_t SWIER2; /*!< EXTI software interrupt event register [31:0], Address offset: 0x28 */ 352 __IO uint32_t PR2; /*!< EXTI pending register [31:0], Address offset: 0x2C */ 353 __IO uint32_t RESERVED2[4]; /*!< Reserved, Address offset: 0x30 - 0x3C */ 354 __IO uint32_t RESERVED3[8]; /*!< Reserved, Address offset: 0x40 - 0x5C */ 355 __IO uint32_t RESERVED4[8]; /*!< Reserved, Address offset: 0x60 - 0x7C */ 356 __IO uint32_t IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ 357 __IO uint32_t EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ 358 __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ 359 __IO uint32_t IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ 360 __IO uint32_t EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ 361 }EXTI_TypeDef; 362 363 /** 364 * @brief FLASH Registers 365 */ 366 typedef struct 367 { 368 __IO uint32_t ACR; /*!< FLASH Access control register, Address offset: 0x00 */ 369 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x04 */ 370 __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ 371 __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ 372 __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ 373 __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */ 374 __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ 375 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ 376 __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */ 377 __IO uint32_t PCROP1ASR; /*!< FLASH Bank 1 PCROP area A Start address register, Address offset: 0x24 */ 378 __IO uint32_t PCROP1AER; /*!< FLASH Bank 1 PCROP area A End address register, Address offset: 0x28 */ 379 __IO uint32_t WRP1AR; /*!< FLASH Bank 1 WRP area A address register, Address offset: 0x2C */ 380 __IO uint32_t WRP1BR; /*!< FLASH Bank 1 WRP area B address register, Address offset: 0x30 */ 381 __IO uint32_t PCROP1BSR; /*!< FLASH Bank 1 PCROP area B Start address register, Address offset: 0x34 */ 382 __IO uint32_t PCROP1BER; /*!< FLASH Bank 1 PCROP area B End address register, Address offset: 0x38 */ 383 } FLASH_TypeDef; 384 385 /** 386 * @brief General Purpose I/O 387 */ 388 typedef struct 389 { 390 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ 391 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ 392 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ 393 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ 394 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ 395 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ 396 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ 397 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ 398 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ 399 __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ 400 } GPIO_TypeDef; 401 402 /** 403 * @brief HW Semaphore HSEM 404 */ 405 typedef struct 406 { 407 __IO uint32_t R[16]; /*!< HSEM 2-step write lock and read back registers, Address offset: 00h-3Ch */ 408 uint32_t Reserved1[16]; /*!< Reserved Address offset: 40h-7Ch */ 409 __IO uint32_t RLR[16]; /*!< HSEM 1-step read lock registers, Address offset: 80h-BCh */ 410 uint32_t Reserved2[16]; /*!< Reserved Address offset: C0h-FCh */ 411 __IO uint32_t C1IER; /*!< HSEM CPU1 interrupt enable register , Address offset: 100h */ 412 __IO uint32_t C1ICR; /*!< HSEM CPU1 interrupt clear register , Address offset: 104h */ 413 __IO uint32_t C1ISR; /*!< HSEM CPU1 interrupt status register , Address offset: 108h */ 414 __IO uint32_t C1MISR; /*!< HSEM CPU1 masked interrupt status register , Address offset: 10Ch */ 415 uint32_t Reserved[12]; /*!< Reserved Address offset: 110h-13Ch*/ 416 __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */ 417 __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */ 418 } HSEM_TypeDef; 419 420 typedef struct 421 { 422 __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */ 423 __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */ 424 __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */ 425 __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */ 426 } HSEM_Common_TypeDef; 427 428 /** 429 * @brief Inter-integrated Circuit Interface 430 */ 431 typedef struct 432 { 433 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ 434 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ 435 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ 436 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ 437 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ 438 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ 439 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ 440 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ 441 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ 442 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ 443 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ 444 } I2C_TypeDef; 445 446 /** 447 * @brief Independent WATCHDOG 448 */ 449 typedef struct 450 { 451 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ 452 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ 453 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ 454 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ 455 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ 456 } IWDG_TypeDef; 457 458 /** 459 * @brief LPTIMER 460 */ 461 typedef struct 462 { 463 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ 464 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ 465 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ 466 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ 467 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ 468 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ 469 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ 470 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ 471 __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ 472 __IO uint32_t RESERVED; /*!< Reserved, Address offset: 0x24 */ 473 __IO uint32_t RCR; /*!< LPTIM repetition register, Address offset: 0x28 */ 474 } LPTIM_TypeDef; 475 476 /** 477 * @brief Public Key Accelerator (PKA) 478 */ 479 typedef struct 480 { 481 __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ 482 __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ 483 __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ 484 uint32_t Reserved1[253]; /*!< Reserved Address offset: 0x000C-0x03FC*/ 485 __IO uint32_t RAM[894]; /*!< PKA RAM, Address offset: 0x0400-0x11F4 */ 486 } PKA_TypeDef; 487 488 /** 489 * @brief Power Control 490 */ 491 typedef struct 492 { 493 __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ 494 __IO uint32_t CR2; /*!< PWR Power Control Register 2, Address offset: 0x04 */ 495 __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */ 496 __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */ 497 __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */ 498 __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */ 499 __IO uint32_t SCR; /*!< PWR Power Status Reset Register, Address offset: 0x18 */ 500 __IO uint32_t CR5; /*!< PWR Power Control Register 5, Address offset: 0x1C */ 501 __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */ 502 __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */ 503 __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */ 504 __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */ 505 __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */ 506 __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */ 507 uint32_t RESERVED0[8]; /*!< Reserved, Address offset: 0x38-0x54 */ 508 __IO uint32_t PUCRH; /*!< PWR Pull-Up Control Register of port H, Address offset: 0x58 */ 509 __IO uint32_t PDCRH; /*!< PWR Pull-Down Control Register of port H, Address offset: 0x5C */ 510 uint32_t RESERVED1[10];/*!< Reserved, Address offset: 0x60-0x84 */ 511 __IO uint32_t EXTSCR; /*!< PWR Power Status Reset Register for CPU2, Address offset: 0x88 */ 512 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x8C */ 513 __IO uint32_t SUBGHZSPICR; /*!< PWR SUBGHZSPI Control Register, Address offset: 0x90 */ 514 } PWR_TypeDef; 515 516 /** 517 * @brief Reset and Clock Control 518 */ 519 typedef struct 520 { 521 __IO uint32_t CR; /*!< RCC clock Control Register, Address offset: 0x00 */ 522 __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ 523 __IO uint32_t CFGR; /*!< RCC Clocks Configuration Register, Address offset: 0x08 */ 524 __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */ 525 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */ 526 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ 527 __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ 528 __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ 529 __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ 530 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ 531 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ 532 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ 533 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ 534 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */ 535 __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ 536 __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ 537 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ 538 __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x44 */ 539 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ 540 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ 541 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ 542 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x54 */ 543 __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ 544 __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ 545 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ 546 __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clocks enable register, Address offset: 0x64 */ 547 __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ 548 __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ 549 __IO uint32_t AHB3SMENR; /*!< RCC AHB3 & AHB4 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ 550 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */ 551 __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ 552 __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ 553 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ 554 __IO uint32_t APB3SMENR; /*!< RCC APB3 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x84 */ 555 __IO uint32_t CCIPR; /*!< RCC Peripherals Clock Configuration Independent Register, Address offset: 0x88 */ 556 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x8C */ 557 __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x90 */ 558 __IO uint32_t CSR; /*!< RCC Control and Status Register, Address offset: 0x94 */ 559 uint32_t RESERVED7[28]; /*!< Reserved, Address offset: 0x98-0x104 */ 560 __IO uint32_t EXTCFGR; /*!< RCC Extended Clock Recovery Register, Address offset: 0x108 */ 561 } RCC_TypeDef; 562 563 /** 564 * @brief RNG 565 */ 566 typedef struct 567 { 568 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ 569 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ 570 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ 571 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x0C */ 572 __IO uint32_t HTCR; /*!< RNG health test control register, Address offset: 0x10 */ 573 } RNG_TypeDef; 574 575 /** 576 * @brief RTC Specific device feature definitions 577 */ 578 #define RTC_BACKUP_NB 20u 579 #define RTC_TAMP_NB 3u 580 581 /** 582 * @brief Real-Time Clock 583 */ 584 typedef struct 585 { 586 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ 587 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ 588 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ 589 __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ 590 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ 591 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ 592 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ 593 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x1C */ 594 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ 595 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ 596 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ 597 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ 598 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ 599 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ 600 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ 601 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x3C */ 602 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ 603 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ 604 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ 605 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ 606 __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ 607 __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ 608 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x58 */ 609 __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ 610 uint32_t RESERVED4[4];/*!< Reserved, Address offset: 0x58 */ 611 __IO uint32_t ALRABINR;/*!< RTC alarm A binary mode register, Address offset: 0x70 */ 612 __IO uint32_t ALRBBINR;/*!< RTC alarm B binary mode register, Address offset: 0x74 */ 613 } RTC_TypeDef; 614 615 /** 616 * @brief Serial Peripheral Interface 617 */ 618 typedef struct 619 { 620 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ 621 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ 622 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ 623 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ 624 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ 625 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ 626 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ 627 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ 628 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ 629 } SPI_TypeDef; 630 631 /** 632 * @brief System configuration controller 633 */ 634 typedef struct 635 { 636 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register Address offset: 0x00 */ 637 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ 638 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ 639 __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */ 640 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ 641 __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register part, Address offset: 0x20 */ 642 __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */ 643 uint32_t RESERVED1[120]; /*!< Reserved, Address offset: 0x28-0x204 */ 644 __IO uint32_t RFDCR; /*!< SYSCFG CPU2 radio debug control register, Address offset: 0x208 */ 645 } SYSCFG_TypeDef; 646 647 /** 648 * @brief Tamper and backup registers 649 */ 650 typedef struct 651 { 652 __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ 653 __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ 654 __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ 655 __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ 656 uint32_t RESERVED0[7];/*!< Reserved, Address offset: 0x10 */ 657 __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ 658 __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ 659 __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ 660 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x38 */ 661 __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ 662 __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ 663 uint32_t RESERVED2[47];/*!< Reserved, Address offset: 0x54 - 0xFC */ 664 __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ 665 __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ 666 __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ 667 __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ 668 __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ 669 __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ 670 __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ 671 __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ 672 __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ 673 __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ 674 __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ 675 __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ 676 __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ 677 __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ 678 __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ 679 __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ 680 __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ 681 __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ 682 __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ 683 __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ 684 } TAMP_TypeDef; 685 686 /** 687 * @brief TIM 688 */ 689 typedef struct 690 { 691 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ 692 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ 693 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ 694 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ 695 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ 696 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ 697 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ 698 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ 699 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ 700 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ 701 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ 702 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ 703 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ 704 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ 705 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ 706 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ 707 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ 708 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ 709 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ 710 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ 711 __IO uint32_t OR1; /*!< TIM option register Address offset: 0x50 */ 712 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ 713 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ 714 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ 715 __IO uint32_t AF1; /*!< TIM Alternate function option register 1, Address offset: 0x60 */ 716 __IO uint32_t AF2; /*!< TIM Alternate function option register 2, Address offset: 0x64 */ 717 } TIM_TypeDef; 718 719 /** 720 * @brief Universal Synchronous Asynchronous Receiver Transmitter 721 */ 722 typedef struct 723 { 724 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ 725 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ 726 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ 727 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ 728 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ 729 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ 730 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ 731 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ 732 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ 733 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ 734 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ 735 __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ 736 } USART_TypeDef; 737 738 /** 739 * @brief VREFBUF 740 */ 741 typedef struct 742 { 743 __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ 744 __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ 745 } VREFBUF_TypeDef; 746 747 /** 748 * @brief Window WATCHDOG 749 */ 750 typedef struct 751 { 752 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ 753 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ 754 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ 755 } WWDG_TypeDef; 756 757 /** 758 * @} 759 */ 760 761 /** @addtogroup Peripheral_memory_map 762 * @{ 763 */ 764 /*!< Boundary memory map */ 765 #define FLASH_BASE 0x08000000UL /*!< FLASH(up to 256 KB) base address */ 766 #define SYSTEM_FLASH_BASE 0x1FFF0000UL /*!< System FLASH(28Kb) base address */ 767 #define SRAM1_BASE 0x20000000UL /*!< SRAM1(up to 32 KB) base address */ 768 #define SRAM2_BASE 0x20008000UL /*!< SRAM2(up to 32 KB) base address */ 769 #define PERIPH_BASE 0x40000000UL /*!< Peripheral base address */ 770 771 #define FLASH_SIZE (((*((uint32_t *)FLASHSIZE_BASE)) & 0xFFFFU) << 10U) 772 #define SRAM1_SIZE 0x00008000UL /*!< SRAM1 default size : 32 kB */ 773 #define SRAM2_SIZE 0x00008000UL /*!< SRAM2 default size : 32 kB */ 774 775 /*!< Memory, OTP and Option bytes */ 776 #define OTP_AREA_BASE (SYSTEM_FLASH_BASE + 0x00007000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) */ 777 #define ENGI_BYTES_BASE (SYSTEM_FLASH_BASE + 0x00007400UL) /*!< Engi Bytes : 1kB (0x1FFF7400 - 0x1FFF77FF) */ 778 #define OPTION_BYTES_BASE (SYSTEM_FLASH_BASE + 0x00007800UL) /*!< Option Bytes : 2kB (0x1FFF7800 - 0x1FFF7FFF) */ 779 780 /*!< Device Electronic Signature */ 781 #define PACKAGE_BASE (ENGI_BYTES_BASE + 0x00000100UL) /*!< Package data register base address */ 782 #define UID64_BASE (ENGI_BYTES_BASE + 0x00000180UL) /*!< 64-bit Unique device Identification */ 783 #define UID_BASE (ENGI_BYTES_BASE + 0x00000190UL) /*!< Unique device ID register base address */ 784 #define FLASHSIZE_BASE (ENGI_BYTES_BASE + 0x000001E0UL) /*!< Flash size data register base address */ 785 786 #define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF) */ 787 #define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) */ 788 #define ENGI_BYTE_END_ADDR (0x1FFF77FFUL) /*!< Engi Bytes : 1kB (0x1FFF7400 - 0x1FFF77FF) */ 789 #define OPTION_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Option Bytes : 2KB (0x1FFF7800 - 0x1FFF7FFF) */ 790 791 /*!< Peripheral memory map */ 792 #define APB1PERIPH_BASE PERIPH_BASE 793 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) 794 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) 795 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) 796 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x18000000UL) 797 #define APB3PERIPH_BASE (PERIPH_BASE + 0x18010000UL) 798 799 /*!< APB1 peripherals */ 800 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) 801 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) 802 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL) 803 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL) 804 #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL) 805 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL) 806 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) 807 #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL) 808 #define I2C3_BASE (APB1PERIPH_BASE + 0x00005C00UL) 809 #define DAC_BASE (APB1PERIPH_BASE + 0x00007400UL) 810 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x00007C00UL) 811 #define LPUART1_BASE (APB1PERIPH_BASE + 0x00008000UL) 812 #define LPTIM2_BASE (APB1PERIPH_BASE + 0x00009400UL) 813 #define LPTIM3_BASE (APB1PERIPH_BASE + 0x00009800UL) 814 #define TAMP_BASE (APB1PERIPH_BASE + 0x0000B000UL) 815 816 /*!< APB2 peripherals */ 817 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000UL) 818 #define VREFBUF_BASE (APB2PERIPH_BASE + 0x00000030UL) 819 #define COMP1_BASE (APB2PERIPH_BASE + 0x00000200UL) 820 #define COMP2_BASE (APB2PERIPH_BASE + 0x00000204UL) 821 #define ADC_BASE (APB2PERIPH_BASE + 0x00002400UL) 822 #define ADC_COMMON_BASE (APB2PERIPH_BASE + 0x00002708UL) 823 #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL) 824 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL) 825 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL) 826 #define TIM16_BASE (APB2PERIPH_BASE + 0x00004400UL) 827 #define TIM17_BASE (APB2PERIPH_BASE + 0x00004800UL) 828 829 /*!< AHB1 peripherals */ 830 #define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000UL) 831 #define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400UL) 832 #define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x00000800UL) 833 #define CRC_BASE (AHB1PERIPH_BASE + 0x00003000UL) 834 835 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) 836 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) 837 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) 838 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) 839 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) 840 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) 841 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) 842 843 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL) 844 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL) 845 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL) 846 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL) 847 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL) 848 #define DMA2_Channel6_BASE (DMA2_BASE + 0x0000006CUL) 849 #define DMA2_Channel7_BASE (DMA2_BASE + 0x00000080UL) 850 851 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) 852 #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) 853 #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) 854 #define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL) 855 #define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL) 856 #define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014UL) 857 #define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018UL) 858 #define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0000001CUL) 859 #define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x00000020UL) 860 #define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x00000024UL) 861 #define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x00000028UL) 862 #define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x0000002CUL) 863 #define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x00000030UL) 864 #define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x00000034UL) 865 866 #define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL) 867 #define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL) 868 #define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL) 869 #define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL) 870 871 #define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) 872 #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) 873 874 /*!< AHB2 peripherals */ 875 #define IOPORT_BASE (AHB2PERIPH_BASE + 0x00000000UL) 876 #define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) 877 #define GPIOB_BASE (IOPORT_BASE + 0x00000400UL) 878 #define GPIOC_BASE (IOPORT_BASE + 0x00000800UL) 879 #define GPIOH_BASE (IOPORT_BASE + 0x00001C00UL) 880 881 /*!< AHB3 peripherals */ 882 #define PWR_BASE (AHB3PERIPH_BASE + 0x00000400UL) 883 #define EXTI_BASE (AHB3PERIPH_BASE + 0x00000800UL) 884 #define RCC_BASE (AHB3PERIPH_BASE + 0x00000000UL) 885 #define RNG_BASE (AHB3PERIPH_BASE + 0x00001000UL) 886 #define HSEM_BASE (AHB3PERIPH_BASE + 0x00001400UL) 887 #define AES_BASE (AHB3PERIPH_BASE + 0x00001800UL) 888 #define PKA_BASE (AHB3PERIPH_BASE + 0x00002000UL) 889 #define FLASH_REG_BASE (AHB3PERIPH_BASE + 0x00004000UL) 890 891 /*!< APB3 peripherals */ 892 #define SUBGHZSPI_BASE (APB3PERIPH_BASE + 0x00000000UL) 893 894 /*!< Peripherals available on CPU1 external PPB bus */ 895 #define DBGMCU_BASE (0xE0042000UL) 896 897 /** 898 * @} 899 */ 900 901 /** @addtogroup Peripheral_declaration 902 * @{ 903 */ 904 905 /* Peripherals available on APB1 bus */ 906 #define TIM2 ((TIM_TypeDef *) TIM2_BASE) 907 #define IWDG ((IWDG_TypeDef *) IWDG_BASE) 908 #define WWDG ((WWDG_TypeDef *) WWDG_BASE) 909 #define DAC ((DAC_TypeDef *) DAC_BASE) 910 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) 911 #define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) 912 #define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE) 913 #define RTC ((RTC_TypeDef *) RTC_BASE) 914 #define SPI2 ((SPI_TypeDef *) SPI2_BASE) 915 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) 916 #define I2C2 ((I2C_TypeDef *) I2C2_BASE) 917 #define I2C3 ((I2C_TypeDef *) I2C3_BASE) 918 #define TAMP ((TAMP_TypeDef *) TAMP_BASE) 919 #define USART2 ((USART_TypeDef *) USART2_BASE) 920 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE) 921 922 /* Peripherals available on APB2 bus */ 923 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) 924 #define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) 925 #define COMP1 ((COMP_TypeDef *) COMP1_BASE) 926 #define COMP2 ((COMP_TypeDef *) COMP2_BASE) 927 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) 928 #define TIM1 ((TIM_TypeDef *) TIM1_BASE) 929 #define SPI1 ((SPI_TypeDef *) SPI1_BASE) 930 #define ADC ((ADC_TypeDef *) ADC_BASE) 931 #define ADC_COMMON ((ADC_Common_TypeDef *) ADC_COMMON_BASE) 932 #define TIM16 ((TIM_TypeDef *) TIM16_BASE) 933 #define TIM17 ((TIM_TypeDef *) TIM17_BASE) 934 #define USART1 ((USART_TypeDef *) USART1_BASE) 935 936 /* Peripherals available on AHB1 bus */ 937 #define DMA1 ((DMA_TypeDef *) DMA1_BASE) 938 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) 939 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) 940 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) 941 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) 942 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) 943 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) 944 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) 945 946 #define DMA2 ((DMA_TypeDef *) DMA2_BASE) 947 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) 948 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) 949 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) 950 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) 951 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) 952 #define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) 953 #define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) 954 955 #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) 956 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) 957 #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) 958 #define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) 959 #define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) 960 #define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) 961 #define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) 962 #define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) 963 #define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) 964 #define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) 965 #define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) 966 #define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) 967 #define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) 968 #define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) 969 #define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) 970 971 #define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) 972 #define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) 973 #define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) 974 #define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) 975 976 #define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) 977 #define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) 978 979 #define CRC ((CRC_TypeDef *) CRC_BASE) 980 981 /* Peripherals available on AHB2 bus */ 982 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 983 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 984 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 985 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) 986 987 /* Peripherals available on AH3 bus */ 988 #define AES ((AES_TypeDef *) AES_BASE) 989 990 #define EXTI ((EXTI_TypeDef *) EXTI_BASE) 991 #define RCC ((RCC_TypeDef *) RCC_BASE) 992 #define PWR ((PWR_TypeDef *) PWR_BASE) 993 #define RNG ((RNG_TypeDef *) RNG_BASE) 994 #define HSEM ((HSEM_TypeDef *) HSEM_BASE) 995 #define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100U)) 996 #define PKA ((PKA_TypeDef *) PKA_BASE) 997 #define FLASH ((FLASH_TypeDef *) FLASH_REG_BASE) 998 999 /* Peripherals available on APB3 bus */ 1000 #define SUBGHZSPI ((SPI_TypeDef *) SUBGHZSPI_BASE) 1001 1002 /* Peripherals available on CPU1 external PPB bus */ 1003 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) 1004 1005 /** 1006 * @} 1007 */ 1008 1009 /** @addtogroup Exported_constants 1010 * @{ 1011 */ 1012 1013 /** @addtogroup Hardware_Constant_Definition 1014 * @{ 1015 */ 1016 #define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ 1017 1018 /** 1019 * @} 1020 */ 1021 1022 /** @addtogroup Peripheral_Registers_Bits_Definition 1023 * @{ 1024 */ 1025 1026 /******************************************************************************/ 1027 /* Peripheral Registers Bits Definition */ 1028 /******************************************************************************/ 1029 1030 /******************************************************************************/ 1031 /* */ 1032 /* Analog to Digital Converter (ADC) */ 1033 /* */ 1034 /******************************************************************************/ 1035 /******************** Bit definition for ADC_ISR register *******************/ 1036 #define ADC_ISR_ADRDY_Pos (0U) 1037 #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ 1038 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ 1039 #define ADC_ISR_EOSMP_Pos (1U) 1040 #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ 1041 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ 1042 #define ADC_ISR_EOC_Pos (2U) 1043 #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ 1044 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ 1045 #define ADC_ISR_EOS_Pos (3U) 1046 #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ 1047 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ 1048 #define ADC_ISR_OVR_Pos (4U) 1049 #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ 1050 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ 1051 #define ADC_ISR_AWD1_Pos (7U) 1052 #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ 1053 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ 1054 #define ADC_ISR_AWD2_Pos (8U) 1055 #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ 1056 #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ 1057 #define ADC_ISR_AWD3_Pos (9U) 1058 #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ 1059 #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ 1060 #define ADC_ISR_EOCAL_Pos (11U) 1061 #define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ 1062 #define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */ 1063 #define ADC_ISR_CCRDY_Pos (13U) 1064 #define ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos) /*!< 0x00002000 */ 1065 #define ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk /*!< ADC channel configuration ready flag */ 1066 1067 /******************** Bit definition for ADC_IER register *******************/ 1068 #define ADC_IER_ADRDYIE_Pos (0U) 1069 #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ 1070 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ 1071 #define ADC_IER_EOSMPIE_Pos (1U) 1072 #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ 1073 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ 1074 #define ADC_IER_EOCIE_Pos (2U) 1075 #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ 1076 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ 1077 #define ADC_IER_EOSIE_Pos (3U) 1078 #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ 1079 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ 1080 #define ADC_IER_OVRIE_Pos (4U) 1081 #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ 1082 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ 1083 #define ADC_IER_AWD1IE_Pos (7U) 1084 #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ 1085 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ 1086 #define ADC_IER_AWD2IE_Pos (8U) 1087 #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ 1088 #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ 1089 #define ADC_IER_AWD3IE_Pos (9U) 1090 #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ 1091 #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ 1092 #define ADC_IER_EOCALIE_Pos (11U) 1093 #define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ 1094 #define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */ 1095 #define ADC_IER_CCRDYIE_Pos (13U) 1096 #define ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos) /*!< 0x00002000 */ 1097 #define ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk /*!< ADC channel configuration ready interrupt */ 1098 1099 /******************** Bit definition for ADC_CR register ********************/ 1100 #define ADC_CR_ADEN_Pos (0U) 1101 #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ 1102 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ 1103 #define ADC_CR_ADDIS_Pos (1U) 1104 #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ 1105 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ 1106 #define ADC_CR_ADSTART_Pos (2U) 1107 #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ 1108 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ 1109 #define ADC_CR_ADSTP_Pos (4U) 1110 #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ 1111 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ 1112 #define ADC_CR_ADVREGEN_Pos (28U) 1113 #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ 1114 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ 1115 #define ADC_CR_ADCAL_Pos (31U) 1116 #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ 1117 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ 1118 1119 /******************** Bit definition for ADC_CFGR1 register *****************/ 1120 #define ADC_CFGR1_DMAEN_Pos (0U) 1121 #define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ 1122 #define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ 1123 #define ADC_CFGR1_DMACFG_Pos (1U) 1124 #define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ 1125 #define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ 1126 1127 #define ADC_CFGR1_SCANDIR_Pos (2U) 1128 #define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ 1129 #define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ 1130 1131 #define ADC_CFGR1_RES_Pos (3U) 1132 #define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ 1133 #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ 1134 #define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ 1135 #define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ 1136 1137 #define ADC_CFGR1_ALIGN_Pos (5U) 1138 #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ 1139 #define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ 1140 1141 #define ADC_CFGR1_EXTSEL_Pos (6U) 1142 #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ 1143 #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ 1144 #define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ 1145 #define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ 1146 #define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ 1147 1148 #define ADC_CFGR1_EXTEN_Pos (10U) 1149 #define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ 1150 #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ 1151 #define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ 1152 #define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ 1153 1154 #define ADC_CFGR1_OVRMOD_Pos (12U) 1155 #define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ 1156 #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ 1157 #define ADC_CFGR1_CONT_Pos (13U) 1158 #define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ 1159 #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ 1160 #define ADC_CFGR1_WAIT_Pos (14U) 1161 #define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ 1162 #define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ 1163 #define ADC_CFGR1_AUTOFF_Pos (15U) 1164 #define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ 1165 #define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ 1166 #define ADC_CFGR1_DISCEN_Pos (16U) 1167 #define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ 1168 #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ 1169 #define ADC_CFGR1_CHSELRMOD_Pos (21U) 1170 #define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ 1171 #define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */ 1172 1173 #define ADC_CFGR1_AWD1SGL_Pos (22U) 1174 #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ 1175 #define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ 1176 #define ADC_CFGR1_AWD1EN_Pos (23U) 1177 #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ 1178 #define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ 1179 1180 #define ADC_CFGR1_AWD1CH_Pos (26U) 1181 #define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ 1182 #define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ 1183 #define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ 1184 #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ 1185 #define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ 1186 #define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ 1187 #define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ 1188 1189 /******************** Bit definition for ADC_CFGR2 register *****************/ 1190 #define ADC_CFGR2_OVSE_Pos (0U) 1191 #define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ 1192 #define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ 1193 1194 #define ADC_CFGR2_OVSR_Pos (2U) 1195 #define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ 1196 #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ 1197 #define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ 1198 #define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ 1199 #define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ 1200 1201 #define ADC_CFGR2_OVSS_Pos (5U) 1202 #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ 1203 #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ 1204 #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ 1205 #define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ 1206 #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ 1207 #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ 1208 1209 #define ADC_CFGR2_TOVS_Pos (9U) 1210 #define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */ 1211 #define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ 1212 1213 #define ADC_CFGR2_LFTRIG_Pos (29U) 1214 #define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ 1215 #define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ 1216 1217 #define ADC_CFGR2_CKMODE_Pos (30U) 1218 #define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ 1219 #define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ 1220 #define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ 1221 #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ 1222 1223 /******************** Bit definition for ADC_SMPR register ******************/ 1224 #define ADC_SMPR_SMP1_Pos (0U) 1225 #define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */ 1226 #define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */ 1227 #define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */ 1228 #define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */ 1229 #define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */ 1230 1231 #define ADC_SMPR_SMP2_Pos (4U) 1232 #define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */ 1233 #define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ 1234 #define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */ 1235 #define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */ 1236 #define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */ 1237 1238 #define ADC_SMPR_SMPSEL_Pos (8U) 1239 #define ADC_SMPR_SMPSEL_Msk (0x3FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x03FFFF00 */ 1240 #define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */ 1241 #define ADC_SMPR_SMPSEL0_Pos (8U) 1242 #define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ 1243 #define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */ 1244 #define ADC_SMPR_SMPSEL1_Pos (9U) 1245 #define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ 1246 #define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */ 1247 #define ADC_SMPR_SMPSEL2_Pos (10U) 1248 #define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ 1249 #define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */ 1250 #define ADC_SMPR_SMPSEL3_Pos (11U) 1251 #define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ 1252 #define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */ 1253 #define ADC_SMPR_SMPSEL4_Pos (12U) 1254 #define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ 1255 #define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */ 1256 #define ADC_SMPR_SMPSEL5_Pos (13U) 1257 #define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ 1258 #define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */ 1259 #define ADC_SMPR_SMPSEL6_Pos (14U) 1260 #define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ 1261 #define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */ 1262 #define ADC_SMPR_SMPSEL7_Pos (15U) 1263 #define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ 1264 #define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */ 1265 #define ADC_SMPR_SMPSEL8_Pos (16U) 1266 #define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ 1267 #define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */ 1268 #define ADC_SMPR_SMPSEL9_Pos (17U) 1269 #define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ 1270 #define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */ 1271 #define ADC_SMPR_SMPSEL10_Pos (18U) 1272 #define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ 1273 #define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */ 1274 #define ADC_SMPR_SMPSEL11_Pos (19U) 1275 #define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ 1276 #define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */ 1277 #define ADC_SMPR_SMPSEL12_Pos (20U) 1278 #define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ 1279 #define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */ 1280 #define ADC_SMPR_SMPSEL13_Pos (21U) 1281 #define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ 1282 #define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */ 1283 #define ADC_SMPR_SMPSEL14_Pos (22U) 1284 #define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ 1285 #define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */ 1286 #define ADC_SMPR_SMPSEL15_Pos (23U) 1287 #define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ 1288 #define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */ 1289 #define ADC_SMPR_SMPSEL16_Pos (24U) 1290 #define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ 1291 #define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */ 1292 #define ADC_SMPR_SMPSEL17_Pos (25U) 1293 #define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ 1294 #define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ 1295 1296 /******************** Bit definition for ADC_AWD1TR register ****************/ 1297 #define ADC_AWD1TR_LT1_Pos (0U) 1298 #define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ 1299 #define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ 1300 #define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ 1301 #define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ 1302 #define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ 1303 #define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ 1304 #define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ 1305 #define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ 1306 #define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ 1307 #define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ 1308 #define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ 1309 #define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ 1310 #define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ 1311 #define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ 1312 1313 #define ADC_AWD1TR_HT1_Pos (16U) 1314 #define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ 1315 #define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ 1316 #define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ 1317 #define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ 1318 #define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ 1319 #define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ 1320 #define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ 1321 #define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ 1322 #define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ 1323 #define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ 1324 #define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ 1325 #define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ 1326 #define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ 1327 #define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ 1328 1329 /* Legacy definitions */ 1330 #define ADC_TR1_LT1 ADC_AWD1TR_LT1 1331 #define ADC_TR1_LT1_0 ADC_AWD1TR_LT1_0 1332 #define ADC_TR1_LT1_1 ADC_AWD1TR_LT1_1 1333 #define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2 1334 #define ADC_TR1_LT1_3 ADC_AWD1TR_LT1_3 1335 #define ADC_TR1_LT1_4 ADC_AWD1TR_LT1_4 1336 #define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5 1337 #define ADC_TR1_LT1_6 ADC_AWD1TR_LT1_6 1338 #define ADC_TR1_LT1_7 ADC_AWD1TR_LT1_7 1339 #define ADC_TR1_LT1_8 ADC_AWD1TR_LT1_8 1340 #define ADC_TR1_LT1_9 ADC_AWD1TR_LT1_9 1341 #define ADC_TR1_LT1_10 ADC_AWD1TR_LT1_10 1342 #define ADC_TR1_LT1_11 ADC_AWD1TR_LT1_11 1343 1344 #define ADC_TR1_HT1 ADC_AWD1TR_HT1 1345 #define ADC_TR1_HT1_0 ADC_AWD1TR_HT1_0 1346 #define ADC_TR1_HT1_1 ADC_AWD1TR_HT1_1 1347 #define ADC_TR1_HT1_2 ADC_AWD1TR_HT1_2 1348 #define ADC_TR1_HT1_3 ADC_AWD1TR_HT1_3 1349 #define ADC_TR1_HT1_4 ADC_AWD1TR_HT1_4 1350 #define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5 1351 #define ADC_TR1_HT1_6 ADC_AWD1TR_HT1_6 1352 #define ADC_TR1_HT1_7 ADC_AWD1TR_HT1_7 1353 #define ADC_TR1_HT1_8 ADC_AWD1TR_HT1_8 1354 #define ADC_TR1_HT1_9 ADC_AWD1TR_HT1_9 1355 #define ADC_TR1_HT1_10 ADC_AWD1TR_HT1_10 1356 #define ADC_TR1_HT1_11 ADC_AWD1TR_HT1_11 1357 1358 /******************** Bit definition for ADC_AWD2TR register *******************/ 1359 #define ADC_AWD2TR_LT2_Pos (0U) 1360 #define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ 1361 #define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ 1362 #define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ 1363 #define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ 1364 #define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ 1365 #define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ 1366 #define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ 1367 #define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ 1368 #define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ 1369 #define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ 1370 #define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ 1371 #define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ 1372 #define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ 1373 #define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ 1374 1375 #define ADC_AWD2TR_HT2_Pos (16U) 1376 #define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ 1377 #define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ 1378 #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ 1379 #define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ 1380 #define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ 1381 #define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ 1382 #define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ 1383 #define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ 1384 #define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ 1385 #define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ 1386 #define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ 1387 #define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ 1388 #define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ 1389 #define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ 1390 1391 /* Legacy definitions */ 1392 #define ADC_TR2_LT2 ADC_AWD2TR_LT2 1393 #define ADC_TR2_LT2_0 ADC_AWD2TR_LT2_0 1394 #define ADC_TR2_LT2_1 ADC_AWD2TR_LT2_1 1395 #define ADC_TR2_LT2_2 ADC_AWD2TR_LT2_2 1396 #define ADC_TR2_LT2_3 ADC_AWD2TR_LT2_3 1397 #define ADC_TR2_LT2_4 ADC_AWD2TR_LT2_4 1398 #define ADC_TR2_LT2_5 ADC_AWD2TR_LT2_5 1399 #define ADC_TR2_LT2_6 ADC_AWD2TR_LT2_6 1400 #define ADC_TR2_LT2_7 ADC_AWD2TR_LT2_7 1401 #define ADC_TR2_LT2_8 ADC_AWD2TR_LT2_8 1402 #define ADC_TR2_LT2_9 ADC_AWD2TR_LT2_9 1403 #define ADC_TR2_LT2_10 ADC_AWD2TR_LT2_10 1404 #define ADC_TR2_LT2_11 ADC_AWD2TR_LT2_11 1405 1406 #define ADC_TR2_HT2 ADC_AWD2TR_HT2 1407 #define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0 1408 #define ADC_TR2_HT2_1 ADC_AWD2TR_HT2_1 1409 #define ADC_TR2_HT2_2 ADC_AWD2TR_HT2_2 1410 #define ADC_TR2_HT2_3 ADC_AWD2TR_HT2_3 1411 #define ADC_TR2_HT2_4 ADC_AWD2TR_HT2_4 1412 #define ADC_TR2_HT2_5 ADC_AWD2TR_HT2_5 1413 #define ADC_TR2_HT2_6 ADC_AWD2TR_HT2_6 1414 #define ADC_TR2_HT2_7 ADC_AWD2TR_HT2_7 1415 #define ADC_TR2_HT2_8 ADC_AWD2TR_HT2_8 1416 #define ADC_TR2_HT2_9 ADC_AWD2TR_HT2_9 1417 #define ADC_TR2_HT2_10 ADC_AWD2TR_HT2_10 1418 #define ADC_TR2_HT2_11 ADC_AWD2TR_HT2_11 1419 1420 /******************** Bit definition for ADC_CHSELR register ****************/ 1421 #define ADC_CHSELR_CHSEL_Pos (0U) 1422 #define ADC_CHSELR_CHSEL_Msk (0x3FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0003FFFF */ 1423 #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ 1424 #define ADC_CHSELR_CHSEL17_Pos (17U) 1425 #define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ 1426 #define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ 1427 #define ADC_CHSELR_CHSEL16_Pos (16U) 1428 #define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ 1429 #define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ 1430 #define ADC_CHSELR_CHSEL15_Pos (15U) 1431 #define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ 1432 #define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ 1433 #define ADC_CHSELR_CHSEL14_Pos (14U) 1434 #define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ 1435 #define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ 1436 #define ADC_CHSELR_CHSEL13_Pos (13U) 1437 #define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ 1438 #define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ 1439 #define ADC_CHSELR_CHSEL12_Pos (12U) 1440 #define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ 1441 #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ 1442 #define ADC_CHSELR_CHSEL11_Pos (11U) 1443 #define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ 1444 #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ 1445 #define ADC_CHSELR_CHSEL10_Pos (10U) 1446 #define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ 1447 #define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ 1448 #define ADC_CHSELR_CHSEL9_Pos (9U) 1449 #define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ 1450 #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ 1451 #define ADC_CHSELR_CHSEL8_Pos (8U) 1452 #define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ 1453 #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ 1454 #define ADC_CHSELR_CHSEL7_Pos (7U) 1455 #define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ 1456 #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ 1457 #define ADC_CHSELR_CHSEL6_Pos (6U) 1458 #define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ 1459 #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ 1460 #define ADC_CHSELR_CHSEL5_Pos (5U) 1461 #define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ 1462 #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ 1463 #define ADC_CHSELR_CHSEL4_Pos (4U) 1464 #define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ 1465 #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ 1466 #define ADC_CHSELR_CHSEL3_Pos (3U) 1467 #define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ 1468 #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ 1469 #define ADC_CHSELR_CHSEL2_Pos (2U) 1470 #define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ 1471 #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ 1472 #define ADC_CHSELR_CHSEL1_Pos (1U) 1473 #define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ 1474 #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ 1475 #define ADC_CHSELR_CHSEL0_Pos (0U) 1476 #define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ 1477 #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ 1478 1479 #define ADC_CHSELR_SQ_ALL_Pos (0U) 1480 #define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ 1481 #define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ 1482 1483 #define ADC_CHSELR_SQ8_Pos (28U) 1484 #define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ 1485 #define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ 1486 #define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ 1487 #define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ 1488 #define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ 1489 #define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ 1490 1491 #define ADC_CHSELR_SQ7_Pos (24U) 1492 #define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ 1493 #define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ 1494 #define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ 1495 #define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ 1496 #define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ 1497 #define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ 1498 1499 #define ADC_CHSELR_SQ6_Pos (20U) 1500 #define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ 1501 #define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ 1502 #define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ 1503 #define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ 1504 #define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ 1505 #define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ 1506 1507 #define ADC_CHSELR_SQ5_Pos (16U) 1508 #define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ 1509 #define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ 1510 #define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ 1511 #define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ 1512 #define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ 1513 #define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ 1514 1515 #define ADC_CHSELR_SQ4_Pos (12U) 1516 #define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ 1517 #define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ 1518 #define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ 1519 #define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ 1520 #define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ 1521 #define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ 1522 1523 #define ADC_CHSELR_SQ3_Pos (8U) 1524 #define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ 1525 #define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ 1526 #define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ 1527 #define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ 1528 #define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ 1529 #define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ 1530 1531 #define ADC_CHSELR_SQ2_Pos (4U) 1532 #define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ 1533 #define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ 1534 #define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ 1535 #define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ 1536 #define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ 1537 #define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ 1538 1539 #define ADC_CHSELR_SQ1_Pos (0U) 1540 #define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ 1541 #define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ 1542 #define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ 1543 #define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ 1544 #define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ 1545 #define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ 1546 1547 /******************** Bit definition for ADC_AWD3TR register *******************/ 1548 #define ADC_AWD3TR_LT3_Pos (0U) 1549 #define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ 1550 #define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ 1551 #define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ 1552 #define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ 1553 #define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ 1554 #define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ 1555 #define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ 1556 #define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ 1557 #define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ 1558 #define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ 1559 #define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ 1560 #define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ 1561 #define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ 1562 #define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ 1563 1564 #define ADC_AWD3TR_HT3_Pos (16U) 1565 #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ 1566 #define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ 1567 #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ 1568 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ 1569 #define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ 1570 #define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ 1571 #define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ 1572 #define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ 1573 #define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ 1574 #define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ 1575 #define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ 1576 #define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ 1577 #define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ 1578 #define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ 1579 1580 /* Legacy definitions */ 1581 #define ADC_TR3_LT3 ADC_AWD3TR_LT3 1582 #define ADC_TR3_LT3_0 ADC_AWD3TR_LT3_0 1583 #define ADC_TR3_LT3_1 ADC_AWD3TR_LT3_1 1584 #define ADC_TR3_LT3_2 ADC_AWD3TR_LT3_2 1585 #define ADC_TR3_LT3_3 ADC_AWD3TR_LT3_3 1586 #define ADC_TR3_LT3_4 ADC_AWD3TR_LT3_4 1587 #define ADC_TR3_LT3_5 ADC_AWD3TR_LT3_5 1588 #define ADC_TR3_LT3_6 ADC_AWD3TR_LT3_6 1589 #define ADC_TR3_LT3_7 ADC_AWD3TR_LT3_7 1590 #define ADC_TR3_LT3_8 ADC_AWD3TR_LT3_8 1591 #define ADC_TR3_LT3_9 ADC_AWD3TR_LT3_9 1592 #define ADC_TR3_LT3_10 ADC_AWD3TR_LT3_10 1593 #define ADC_TR3_LT3_11 ADC_AWD3TR_LT3_11 1594 1595 #define ADC_TR3_HT3 ADC_AWD3TR_HT3 1596 #define ADC_TR3_HT3_0 ADC_AWD3TR_HT3_0 1597 #define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1 1598 #define ADC_TR3_HT3_2 ADC_AWD3TR_HT3_2 1599 #define ADC_TR3_HT3_3 ADC_AWD3TR_HT3_3 1600 #define ADC_TR3_HT3_4 ADC_AWD3TR_HT3_4 1601 #define ADC_TR3_HT3_5 ADC_AWD3TR_HT3_5 1602 #define ADC_TR3_HT3_6 ADC_AWD3TR_HT3_6 1603 #define ADC_TR3_HT3_7 ADC_AWD3TR_HT3_7 1604 #define ADC_TR3_HT3_8 ADC_AWD3TR_HT3_8 1605 #define ADC_TR3_HT3_9 ADC_AWD3TR_HT3_9 1606 #define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10 1607 #define ADC_TR3_HT3_11 ADC_AWD3TR_HT3_11 1608 /******************** Bit definition for ADC_DR register ********************/ 1609 #define ADC_DR_DATA_Pos (0U) 1610 #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ 1611 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ 1612 #define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */ 1613 #define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */ 1614 #define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */ 1615 #define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */ 1616 #define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */ 1617 #define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */ 1618 #define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */ 1619 #define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */ 1620 #define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */ 1621 #define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */ 1622 #define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */ 1623 #define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */ 1624 #define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */ 1625 #define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */ 1626 #define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */ 1627 #define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ 1628 1629 /******************** Bit definition for ADC_AWD2CR register ****************/ 1630 #define ADC_AWD2CR_AWD2CH_Pos (0U) 1631 #define ADC_AWD2CR_AWD2CH_Msk (0x3FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0003FFFF */ 1632 #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ 1633 #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ 1634 #define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ 1635 #define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ 1636 #define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ 1637 #define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ 1638 #define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ 1639 #define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ 1640 #define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ 1641 #define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ 1642 #define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ 1643 #define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ 1644 #define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ 1645 #define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ 1646 #define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ 1647 #define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ 1648 #define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ 1649 #define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ 1650 #define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ 1651 1652 /******************** Bit definition for ADC_AWD3CR register ****************/ 1653 #define ADC_AWD3CR_AWD3CH_Pos (0U) 1654 #define ADC_AWD3CR_AWD3CH_Msk (0x3FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0003FFFF */ 1655 #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ 1656 #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ 1657 #define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ 1658 #define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ 1659 #define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ 1660 #define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ 1661 #define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ 1662 #define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ 1663 #define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ 1664 #define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ 1665 #define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ 1666 #define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ 1667 #define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ 1668 #define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ 1669 #define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ 1670 #define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ 1671 #define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ 1672 #define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ 1673 #define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ 1674 1675 /******************** Bit definition for ADC_CALFACT register ***************/ 1676 #define ADC_CALFACT_CALFACT_Pos (0U) 1677 #define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ 1678 #define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ 1679 #define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ 1680 #define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ 1681 #define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ 1682 #define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ 1683 #define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ 1684 #define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ 1685 #define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ 1686 1687 /************************* ADC Common registers *****************************/ 1688 /******************** Bit definition for ADC_CCR register *******************/ 1689 #define ADC_CCR_PRESC_Pos (18U) 1690 #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ 1691 #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ 1692 #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ 1693 #define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ 1694 #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ 1695 #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ 1696 1697 #define ADC_CCR_VREFEN_Pos (22U) 1698 #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ 1699 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ 1700 #define ADC_CCR_TSEN_Pos (23U) 1701 #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ 1702 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ 1703 #define ADC_CCR_VBATEN_Pos (24U) 1704 #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ 1705 #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ 1706 1707 /******************************************************************************/ 1708 /* */ 1709 /* Analog Comparators (COMP) */ 1710 /* */ 1711 /******************************************************************************/ 1712 /********************** Bit definition for COMP_CSR register ****************/ 1713 #define COMP_CSR_EN_Pos (0U) 1714 #define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ 1715 #define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ 1716 1717 #define COMP_CSR_PWRMODE_Pos (2U) 1718 #define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x0000000C */ 1719 #define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */ 1720 #define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00000004 */ 1721 #define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00000008 */ 1722 1723 #define COMP_CSR_INMSEL_Pos (4U) 1724 #define COMP_CSR_INMSEL_Msk (0x7UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */ 1725 #define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ 1726 #define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ 1727 #define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ 1728 #define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ 1729 1730 #define COMP_CSR_INPSEL_Pos (7U) 1731 #define COMP_CSR_INPSEL_Msk (0x3UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000180 */ 1732 #define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ 1733 #define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */ 1734 #define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ 1735 1736 #define COMP_CSR_WINMODE_Pos (9U) 1737 #define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000200 */ 1738 #define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ 1739 1740 #define COMP_CSR_POLARITY_Pos (15U) 1741 #define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ 1742 #define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ 1743 1744 #define COMP_CSR_HYST_Pos (16U) 1745 #define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00030000 */ 1746 #define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */ 1747 #define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ 1748 #define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ 1749 1750 #define COMP_CSR_BLANKING_Pos (18U) 1751 #define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */ 1752 #define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */ 1753 #define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */ 1754 #define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */ 1755 #define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */ 1756 1757 #define COMP_CSR_BRGEN_Pos (22U) 1758 #define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */ 1759 #define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */ 1760 #define COMP_CSR_SCALEN_Pos (23U) 1761 #define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */ 1762 #define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */ 1763 1764 #define COMP_CSR_INMESEL_Pos (25U) 1765 #define COMP_CSR_INMESEL_Msk (0x3UL << COMP_CSR_INMESEL_Pos) /*!< 0x06000000 */ 1766 #define COMP_CSR_INMESEL COMP_CSR_INMESEL_Msk /*!< Comparator input minus extended selection */ 1767 #define COMP_CSR_INMESEL_0 (0x1UL << COMP_CSR_INMESEL_Pos) /*!< 0x02000000 */ 1768 #define COMP_CSR_INMESEL_1 (0x2UL << COMP_CSR_INMESEL_Pos) /*!< 0x04000000 */ 1769 1770 #define COMP_CSR_VALUE_Pos (30U) 1771 #define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ 1772 #define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ 1773 1774 #define COMP_CSR_LOCK_Pos (31U) 1775 #define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ 1776 #define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ 1777 1778 /******************************************************************************/ 1779 /* */ 1780 /* Digital to Analog Converter */ 1781 /* */ 1782 /******************************************************************************/ 1783 /* 1784 * @brief Specific device feature definitions 1785 */ 1786 1787 /******************** Bit definition for DAC_CR register ********************/ 1788 #define DAC_CR_EN1_Pos (0U) 1789 #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ 1790 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */ 1791 #define DAC_CR_TEN1_Pos (1U) 1792 #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */ 1793 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */ 1794 1795 #define DAC_CR_TSEL1_Pos (2U) 1796 #define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */ 1797 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */ 1798 #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */ 1799 #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ 1800 #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ 1801 #define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ 1802 1803 #define DAC_CR_WAVE1_Pos (6U) 1804 #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ 1805 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ 1806 #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ 1807 #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ 1808 1809 #define DAC_CR_MAMP1_Pos (8U) 1810 #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ 1811 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ 1812 #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ 1813 #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ 1814 #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ 1815 #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ 1816 1817 #define DAC_CR_DMAEN1_Pos (12U) 1818 #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ 1819 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */ 1820 #define DAC_CR_DMAUDRIE1_Pos (13U) 1821 #define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ 1822 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/ 1823 #define DAC_CR_CEN1_Pos (14U) 1824 #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ 1825 #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/ 1826 1827 /***************** Bit definition for DAC_SWTRIGR register ******************/ 1828 #define DAC_SWTRIGR_SWTRIG1_Pos (0U) 1829 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ 1830 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */ 1831 1832 /***************** Bit definition for DAC_DHR12R1 register ******************/ 1833 #define DAC_DHR12R1_DACC1DHR_Pos (0U) 1834 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ 1835 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */ 1836 1837 /***************** Bit definition for DAC_DHR12L1 register ******************/ 1838 #define DAC_DHR12L1_DACC1DHR_Pos (4U) 1839 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ 1840 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */ 1841 1842 /****************** Bit definition for DAC_DHR8R1 register ******************/ 1843 #define DAC_DHR8R1_DACC1DHR_Pos (0U) 1844 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ 1845 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */ 1846 1847 /***************** Bit definition for DAC_DHR12RD register ******************/ 1848 #define DAC_DHR12RD_DACC1DHR_Pos (0U) 1849 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */ 1850 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */ 1851 1852 /***************** Bit definition for DAC_DHR12LD register ******************/ 1853 #define DAC_DHR12LD_DACC1DHR_Pos (4U) 1854 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */ 1855 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */ 1856 1857 /****************** Bit definition for DAC_DHR8RD register ******************/ 1858 #define DAC_DHR8RD_DACC1DHR_Pos (0U) 1859 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */ 1860 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */ 1861 1862 /******************* Bit definition for DAC_DOR1 register *******************/ 1863 #define DAC_DOR1_DACC1DOR_Pos (0U) 1864 #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ 1865 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */ 1866 1867 /******************** Bit definition for DAC_SR register ********************/ 1868 #define DAC_SR_DMAUDR1_Pos (13U) 1869 #define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ 1870 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */ 1871 #define DAC_SR_CAL_FLAG1_Pos (14U) 1872 #define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */ 1873 #define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */ 1874 #define DAC_SR_BWST1_Pos (15U) 1875 #define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */ 1876 #define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */ 1877 1878 /******************* Bit definition for DAC_CCR register ********************/ 1879 #define DAC_CCR_OTRIM1_Pos (0U) 1880 #define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */ 1881 #define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */ 1882 1883 /******************* Bit definition for DAC_MCR register *******************/ 1884 #define DAC_MCR_MODE1_Pos (0U) 1885 #define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */ 1886 #define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */ 1887 #define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */ 1888 #define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */ 1889 #define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */ 1890 1891 /****************** Bit definition for DAC_SHSR1 register ******************/ 1892 #define DAC_SHSR1_TSAMPLE1_Pos (0U) 1893 #define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */ 1894 #define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */ 1895 1896 /****************** Bit definition for DAC_SHHR register ******************/ 1897 #define DAC_SHHR_THOLD1_Pos (0U) 1898 #define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */ 1899 #define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */ 1900 1901 /****************** Bit definition for DAC_SHRR register ******************/ 1902 #define DAC_SHRR_TREFRESH1_Pos (0U) 1903 #define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */ 1904 #define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */ 1905 1906 /******************************************************************************/ 1907 /* */ 1908 /* Low Power Timer (LPTTIM) */ 1909 /* */ 1910 /******************************************************************************/ 1911 /****************** Bit definition for LPTIM_ISR register *******************/ 1912 #define LPTIM_ISR_CMPM_Pos (0U) 1913 #define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */ 1914 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */ 1915 #define LPTIM_ISR_ARRM_Pos (1U) 1916 #define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */ 1917 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */ 1918 #define LPTIM_ISR_EXTTRIG_Pos (2U) 1919 #define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */ 1920 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */ 1921 #define LPTIM_ISR_CMPOK_Pos (3U) 1922 #define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */ 1923 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */ 1924 #define LPTIM_ISR_ARROK_Pos (4U) 1925 #define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */ 1926 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */ 1927 #define LPTIM_ISR_UP_Pos (5U) 1928 #define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */ 1929 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */ 1930 #define LPTIM_ISR_DOWN_Pos (6U) 1931 #define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */ 1932 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */ 1933 #define LPTIM_ISR_UE_Pos (7U) 1934 #define LPTIM_ISR_UE_Msk (0x1UL << LPTIM_ISR_UE_Pos) /*!< 0x00000080 */ 1935 #define LPTIM_ISR_UE LPTIM_ISR_UE_Msk /*!< Update event occurrence */ 1936 #define LPTIM_ISR_REPOK_Pos (8U) 1937 #define LPTIM_ISR_REPOK_Msk (0x1UL << LPTIM_ISR_REPOK_Pos) /*!< 0x00000100 */ 1938 #define LPTIM_ISR_REPOK LPTIM_ISR_REPOK_Msk /*!< Repetition register update OK */ 1939 1940 /****************** Bit definition for LPTIM_ICR register *******************/ 1941 #define LPTIM_ICR_CMPMCF_Pos (0U) 1942 #define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */ 1943 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */ 1944 #define LPTIM_ICR_ARRMCF_Pos (1U) 1945 #define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */ 1946 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */ 1947 #define LPTIM_ICR_EXTTRIGCF_Pos (2U) 1948 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */ 1949 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */ 1950 #define LPTIM_ICR_CMPOKCF_Pos (3U) 1951 #define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */ 1952 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */ 1953 #define LPTIM_ICR_ARROKCF_Pos (4U) 1954 #define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */ 1955 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */ 1956 #define LPTIM_ICR_UPCF_Pos (5U) 1957 #define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */ 1958 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */ 1959 #define LPTIM_ICR_DOWNCF_Pos (6U) 1960 #define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */ 1961 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */ 1962 #define LPTIM_ICR_UECF_Pos (7U) 1963 #define LPTIM_ICR_UECF_Msk (0x1UL << LPTIM_ICR_UECF_Pos) /*!< 0x00000080 */ 1964 #define LPTIM_ICR_UECF LPTIM_ICR_UECF_Msk /*!< Update event Clear Flag */ 1965 #define LPTIM_ICR_REPOKCF_Pos (8U) 1966 #define LPTIM_ICR_REPOKCF_Msk (0x1UL << LPTIM_ICR_REPOKCF_Pos) /*!< 0x00000100 */ 1967 #define LPTIM_ICR_REPOKCF LPTIM_ICR_REPOKCF_Msk /*!< Repetition register update OK Clear Flag */ 1968 1969 /****************** Bit definition for LPTIM_IER register ********************/ 1970 #define LPTIM_IER_CMPMIE_Pos (0U) 1971 #define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */ 1972 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */ 1973 #define LPTIM_IER_ARRMIE_Pos (1U) 1974 #define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */ 1975 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */ 1976 #define LPTIM_IER_EXTTRIGIE_Pos (2U) 1977 #define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */ 1978 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */ 1979 #define LPTIM_IER_CMPOKIE_Pos (3U) 1980 #define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */ 1981 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */ 1982 #define LPTIM_IER_ARROKIE_Pos (4U) 1983 #define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */ 1984 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */ 1985 #define LPTIM_IER_UPIE_Pos (5U) 1986 #define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */ 1987 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */ 1988 #define LPTIM_IER_DOWNIE_Pos (6U) 1989 #define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */ 1990 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */ 1991 #define LPTIM_IER_UEIE_Pos (7U) 1992 #define LPTIM_IER_UEIE_Msk (0x1UL << LPTIM_IER_UEIE_Pos) /*!< 0x00000080 */ 1993 #define LPTIM_IER_UEIE LPTIM_IER_UEIE_Msk /*!< Update event Interrupt Enable */ 1994 #define LPTIM_IER_REPOKIE_Pos (8U) 1995 #define LPTIM_IER_REPOKIE_Msk (0x1UL << LPTIM_IER_REPOKIE_Pos) /*!< 0x00000100 */ 1996 #define LPTIM_IER_REPOKIE LPTIM_IER_REPOKIE_Msk /*!< Repetition register update OK Interrupt Enable */ 1997 1998 /****************** Bit definition for LPTIM_CFGR register *******************/ 1999 #define LPTIM_CFGR_CKSEL_Pos (0U) 2000 #define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */ 2001 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */ 2002 2003 #define LPTIM_CFGR_CKPOL_Pos (1U) 2004 #define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */ 2005 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */ 2006 #define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */ 2007 #define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */ 2008 2009 #define LPTIM_CFGR_CKFLT_Pos (3U) 2010 #define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */ 2011 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */ 2012 #define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */ 2013 #define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */ 2014 2015 #define LPTIM_CFGR_TRGFLT_Pos (6U) 2016 #define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */ 2017 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */ 2018 #define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */ 2019 #define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */ 2020 2021 #define LPTIM_CFGR_PRESC_Pos (9U) 2022 #define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */ 2023 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */ 2024 #define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */ 2025 #define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */ 2026 #define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */ 2027 2028 #define LPTIM_CFGR_TRIGSEL_Pos (13U) 2029 #define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */ 2030 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */ 2031 #define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */ 2032 #define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */ 2033 #define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */ 2034 2035 #define LPTIM_CFGR_TRIGEN_Pos (17U) 2036 #define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */ 2037 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */ 2038 #define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */ 2039 #define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */ 2040 2041 #define LPTIM_CFGR_TIMOUT_Pos (19U) 2042 #define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */ 2043 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */ 2044 #define LPTIM_CFGR_WAVE_Pos (20U) 2045 #define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */ 2046 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */ 2047 #define LPTIM_CFGR_WAVPOL_Pos (21U) 2048 #define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */ 2049 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */ 2050 #define LPTIM_CFGR_PRELOAD_Pos (22U) 2051 #define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */ 2052 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */ 2053 #define LPTIM_CFGR_COUNTMODE_Pos (23U) 2054 #define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */ 2055 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */ 2056 #define LPTIM_CFGR_ENC_Pos (24U) 2057 #define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */ 2058 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */ 2059 2060 /****************** Bit definition for LPTIM_CR register ********************/ 2061 #define LPTIM_CR_ENABLE_Pos (0U) 2062 #define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */ 2063 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */ 2064 #define LPTIM_CR_SNGSTRT_Pos (1U) 2065 #define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */ 2066 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */ 2067 #define LPTIM_CR_CNTSTRT_Pos (2U) 2068 #define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */ 2069 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */ 2070 #define LPTIM_CR_COUNTRST_Pos (3U) 2071 #define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */ 2072 #define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Counter reset */ 2073 #define LPTIM_CR_RSTARE_Pos (4U) 2074 #define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */ 2075 #define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Reset after read enable */ 2076 2077 /****************** Bit definition for LPTIM_CMP register *******************/ 2078 #define LPTIM_CMP_CMP_Pos (0U) 2079 #define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */ 2080 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */ 2081 2082 /****************** Bit definition for LPTIM_ARR register *******************/ 2083 #define LPTIM_ARR_ARR_Pos (0U) 2084 #define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */ 2085 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */ 2086 2087 /****************** Bit definition for LPTIM_CNT register *******************/ 2088 #define LPTIM_CNT_CNT_Pos (0U) 2089 #define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */ 2090 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */ 2091 2092 /****************** Bit definition for LPTIM_OR register ********************/ 2093 #define LPTIM_OR_OR_Pos (0U) 2094 #define LPTIM_OR_OR_Msk (0x3UL << LPTIM_OR_OR_Pos) /*!< 0x00000003 */ 2095 #define LPTIM_OR_OR LPTIM_OR_OR_Msk /*!< OR[1:0] bits (Remap selection) */ 2096 #define LPTIM_OR_OR_0 (0x1UL << LPTIM_OR_OR_Pos) /*!< 0x00000001 */ 2097 #define LPTIM_OR_OR_1 (0x2UL << LPTIM_OR_OR_Pos) /*!< 0x00000002 */ 2098 2099 /****************** Bit definition for LPTIM_RCR register *******************/ 2100 #define LPTIM_RCR_REP_Pos (0U) 2101 #define LPTIM_RCR_REP_Msk (0xFFUL << LPTIM_RCR_REP_Pos) /*!< 0x000000FF */ 2102 #define LPTIM_RCR_REP LPTIM_RCR_REP_Msk /*!<Repetition Counter Value */ 2103 2104 /******************************************************************************/ 2105 /* */ 2106 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ 2107 /* */ 2108 /******************************************************************************/ 2109 /****************** Bit definition for USART_CR1 register *******************/ 2110 #define USART_CR1_UE_Pos (0U) 2111 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */ 2112 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ 2113 #define USART_CR1_UESM_Pos (1U) 2114 #define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */ 2115 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */ 2116 #define USART_CR1_RE_Pos (2U) 2117 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */ 2118 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ 2119 #define USART_CR1_TE_Pos (3U) 2120 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */ 2121 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ 2122 #define USART_CR1_IDLEIE_Pos (4U) 2123 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ 2124 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ 2125 #define USART_CR1_RXNEIE_RXFNEIE_Pos (5U) 2126 #define USART_CR1_RXNEIE_RXFNEIE_Msk (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */ 2127 #define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE_Msk /*!< RXNE/RXFIFO not empty Interrupt Enable */ 2128 #define USART_CR1_TCIE_Pos (6U) 2129 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ 2130 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ 2131 #define USART_CR1_TXEIE_TXFNFIE_Pos (7U) 2132 #define USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */ 2133 #define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE_Msk /*!< TXE/TXFIFO not full Interrupt Enable */ 2134 #define USART_CR1_PEIE_Pos (8U) 2135 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ 2136 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ 2137 #define USART_CR1_PS_Pos (9U) 2138 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */ 2139 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ 2140 #define USART_CR1_PCE_Pos (10U) 2141 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */ 2142 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ 2143 #define USART_CR1_WAKE_Pos (11U) 2144 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ 2145 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */ 2146 #define USART_CR1_M_Pos (12U) 2147 #define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */ 2148 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */ 2149 #define USART_CR1_M0_Pos (12U) 2150 #define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */ 2151 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */ 2152 #define USART_CR1_MME_Pos (13U) 2153 #define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */ 2154 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */ 2155 #define USART_CR1_CMIE_Pos (14U) 2156 #define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */ 2157 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */ 2158 #define USART_CR1_OVER8_Pos (15U) 2159 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ 2160 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */ 2161 #define USART_CR1_DEDT_Pos (16U) 2162 #define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */ 2163 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */ 2164 #define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */ 2165 #define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */ 2166 #define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */ 2167 #define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */ 2168 #define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */ 2169 #define USART_CR1_DEAT_Pos (21U) 2170 #define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */ 2171 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */ 2172 #define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */ 2173 #define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */ 2174 #define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */ 2175 #define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */ 2176 #define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */ 2177 #define USART_CR1_RTOIE_Pos (26U) 2178 #define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */ 2179 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */ 2180 #define USART_CR1_EOBIE_Pos (27U) 2181 #define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */ 2182 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */ 2183 #define USART_CR1_M1_Pos (28U) 2184 #define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */ 2185 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */ 2186 #define USART_CR1_FIFOEN_Pos (29U) 2187 #define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */ 2188 #define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */ 2189 #define USART_CR1_TXFEIE_Pos (30U) 2190 #define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */ 2191 #define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */ 2192 #define USART_CR1_RXFFIE_Pos (31U) 2193 #define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */ 2194 #define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */ 2195 2196 /****************** Bit definition for USART_CR2 register *******************/ 2197 #define USART_CR2_SLVEN_Pos (0U) 2198 #define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */ 2199 #define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode enable */ 2200 #define USART_CR2_DIS_NSS_Pos (3U) 2201 #define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */ 2202 #define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< NSS input pin disable for SPI slave selection */ 2203 #define USART_CR2_ADDM7_Pos (4U) 2204 #define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */ 2205 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */ 2206 #define USART_CR2_LBDL_Pos (5U) 2207 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ 2208 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ 2209 #define USART_CR2_LBDIE_Pos (6U) 2210 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ 2211 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ 2212 #define USART_CR2_LBCL_Pos (8U) 2213 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ 2214 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ 2215 #define USART_CR2_CPHA_Pos (9U) 2216 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ 2217 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ 2218 #define USART_CR2_CPOL_Pos (10U) 2219 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ 2220 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ 2221 #define USART_CR2_CLKEN_Pos (11U) 2222 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ 2223 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ 2224 #define USART_CR2_STOP_Pos (12U) 2225 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */ 2226 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ 2227 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */ 2228 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */ 2229 #define USART_CR2_LINEN_Pos (14U) 2230 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ 2231 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ 2232 #define USART_CR2_SWAP_Pos (15U) 2233 #define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */ 2234 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */ 2235 #define USART_CR2_RXINV_Pos (16U) 2236 #define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */ 2237 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */ 2238 #define USART_CR2_TXINV_Pos (17U) 2239 #define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */ 2240 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */ 2241 #define USART_CR2_DATAINV_Pos (18U) 2242 #define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */ 2243 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */ 2244 #define USART_CR2_MSBFIRST_Pos (19U) 2245 #define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */ 2246 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */ 2247 #define USART_CR2_ABREN_Pos (20U) 2248 #define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */ 2249 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/ 2250 #define USART_CR2_ABRMODE_Pos (21U) 2251 #define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */ 2252 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */ 2253 #define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */ 2254 #define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */ 2255 #define USART_CR2_RTOEN_Pos (23U) 2256 #define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */ 2257 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */ 2258 #define USART_CR2_ADD_Pos (24U) 2259 #define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */ 2260 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ 2261 2262 /****************** Bit definition for USART_CR3 register *******************/ 2263 #define USART_CR3_EIE_Pos (0U) 2264 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */ 2265 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ 2266 #define USART_CR3_IREN_Pos (1U) 2267 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */ 2268 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ 2269 #define USART_CR3_IRLP_Pos (2U) 2270 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ 2271 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ 2272 #define USART_CR3_HDSEL_Pos (3U) 2273 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ 2274 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ 2275 #define USART_CR3_NACK_Pos (4U) 2276 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */ 2277 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */ 2278 #define USART_CR3_SCEN_Pos (5U) 2279 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ 2280 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */ 2281 #define USART_CR3_DMAR_Pos (6U) 2282 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ 2283 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ 2284 #define USART_CR3_DMAT_Pos (7U) 2285 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ 2286 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ 2287 #define USART_CR3_RTSE_Pos (8U) 2288 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ 2289 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ 2290 #define USART_CR3_CTSE_Pos (9U) 2291 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ 2292 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ 2293 #define USART_CR3_CTSIE_Pos (10U) 2294 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ 2295 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ 2296 #define USART_CR3_ONEBIT_Pos (11U) 2297 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ 2298 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */ 2299 #define USART_CR3_OVRDIS_Pos (12U) 2300 #define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */ 2301 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */ 2302 #define USART_CR3_DDRE_Pos (13U) 2303 #define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */ 2304 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */ 2305 #define USART_CR3_DEM_Pos (14U) 2306 #define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */ 2307 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */ 2308 #define USART_CR3_DEP_Pos (15U) 2309 #define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */ 2310 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */ 2311 #define USART_CR3_SCARCNT_Pos (17U) 2312 #define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */ 2313 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */ 2314 #define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */ 2315 #define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */ 2316 #define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */ 2317 #define USART_CR3_WUS_Pos (20U) 2318 #define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */ 2319 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */ 2320 #define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */ 2321 #define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */ 2322 #define USART_CR3_WUFIE_Pos (22U) 2323 #define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */ 2324 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */ 2325 #define USART_CR3_TXFTIE_Pos (23U) 2326 #define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */ 2327 #define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */ 2328 #define USART_CR3_TCBGTIE_Pos (24U) 2329 #define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */ 2330 #define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */ 2331 #define USART_CR3_RXFTCFG_Pos (25U) 2332 #define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */ 2333 #define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFIFO FIFO threshold configuration */ 2334 #define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */ 2335 #define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */ 2336 #define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */ 2337 #define USART_CR3_RXFTIE_Pos (28U) 2338 #define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */ 2339 #define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */ 2340 #define USART_CR3_TXFTCFG_Pos (29U) 2341 #define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */ 2342 #define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFIFO threshold configuration */ 2343 #define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */ 2344 #define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */ 2345 #define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */ 2346 2347 /****************** Bit definition for USART_BRR register *******************/ 2348 #define USART_BRR_BRR ((uint16_t)0xFFFF) /*!< USART Baud rate register [15:0] */ 2349 2350 /****************** Bit definition for USART_GTPR register ******************/ 2351 #define USART_GTPR_PSC_Pos (0U) 2352 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ 2353 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ 2354 #define USART_GTPR_GT_Pos (8U) 2355 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ 2356 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */ 2357 2358 /******************* Bit definition for USART_RTOR register *****************/ 2359 #define USART_RTOR_RTO_Pos (0U) 2360 #define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */ 2361 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */ 2362 #define USART_RTOR_BLEN_Pos (24U) 2363 #define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */ 2364 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */ 2365 2366 /******************* Bit definition for USART_RQR register ******************/ 2367 #define USART_RQR_ABRRQ ((uint16_t)0x0001) /*!< Auto-Baud Rate Request */ 2368 #define USART_RQR_SBKRQ ((uint16_t)0x0002) /*!< Send Break Request */ 2369 #define USART_RQR_MMRQ ((uint16_t)0x0004) /*!< Mute Mode Request */ 2370 #define USART_RQR_RXFRQ ((uint16_t)0x0008) /*!< Receive Data flush Request */ 2371 #define USART_RQR_TXFRQ ((uint16_t)0x0010) /*!< Transmit data flush Request */ 2372 2373 /******************* Bit definition for USART_ISR register ******************/ 2374 #define USART_ISR_PE_Pos (0U) 2375 #define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */ 2376 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */ 2377 #define USART_ISR_FE_Pos (1U) 2378 #define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */ 2379 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */ 2380 #define USART_ISR_NE_Pos (2U) 2381 #define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */ 2382 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */ 2383 #define USART_ISR_ORE_Pos (3U) 2384 #define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */ 2385 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */ 2386 #define USART_ISR_IDLE_Pos (4U) 2387 #define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */ 2388 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */ 2389 #define USART_ISR_RXNE_RXFNE_Pos (5U) 2390 #define USART_ISR_RXNE_RXFNE_Msk (0x1UL << USART_ISR_RXNE_RXFNE_Pos) /*!< 0x00000020 */ 2391 #define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE_Msk /*!< Read Data Register Not Empty/RXFIFO Not Empty */ 2392 #define USART_ISR_TC_Pos (6U) 2393 #define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */ 2394 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */ 2395 #define USART_ISR_TXE_TXFNF_Pos (7U) 2396 #define USART_ISR_TXE_TXFNF_Msk (0x1UL << USART_ISR_TXE_TXFNF_Pos) /*!< 0x00000080 */ 2397 #define USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF_Msk /*!< Transmit Data Register Empty/TXFIFO Not Full */ 2398 #define USART_ISR_LBDF_Pos (8U) 2399 #define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */ 2400 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */ 2401 #define USART_ISR_CTSIF_Pos (9U) 2402 #define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */ 2403 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */ 2404 #define USART_ISR_CTS_Pos (10U) 2405 #define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */ 2406 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */ 2407 #define USART_ISR_RTOF_Pos (11U) 2408 #define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */ 2409 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */ 2410 #define USART_ISR_EOBF_Pos (12U) 2411 #define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */ 2412 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */ 2413 #define USART_ISR_UDR_Pos (13U) 2414 #define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) /*!< 0x00002000 */ 2415 #define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI Slave Underrun Error Flag */ 2416 #define USART_ISR_ABRE_Pos (14U) 2417 #define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */ 2418 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */ 2419 #define USART_ISR_ABRF_Pos (15U) 2420 #define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */ 2421 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */ 2422 #define USART_ISR_BUSY_Pos (16U) 2423 #define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */ 2424 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */ 2425 #define USART_ISR_CMF_Pos (17U) 2426 #define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */ 2427 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */ 2428 #define USART_ISR_SBKF_Pos (18U) 2429 #define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */ 2430 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */ 2431 #define USART_ISR_RWU_Pos (19U) 2432 #define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */ 2433 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */ 2434 #define USART_ISR_WUF_Pos (20U) 2435 #define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */ 2436 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */ 2437 #define USART_ISR_TEACK_Pos (21U) 2438 #define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */ 2439 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */ 2440 #define USART_ISR_REACK_Pos (22U) 2441 #define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */ 2442 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */ 2443 #define USART_ISR_TXFE_Pos (23U) 2444 #define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) /*!< 0x00800000 */ 2445 #define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty Flag */ 2446 #define USART_ISR_RXFF_Pos (24U) 2447 #define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) /*!< 0x01000000 */ 2448 #define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full Flag */ 2449 #define USART_ISR_TCBGT_Pos (25U) 2450 #define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */ 2451 #define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time Completion Flag */ 2452 #define USART_ISR_RXFT_Pos (26U) 2453 #define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) /*!< 0x04000000 */ 2454 #define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO Threshold Flag */ 2455 #define USART_ISR_TXFT_Pos (27U) 2456 #define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) /*!< 0x08000000 */ 2457 #define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO Threshold Flag */ 2458 2459 /******************* Bit definition for USART_ICR register ******************/ 2460 #define USART_ICR_PECF_Pos (0U) 2461 #define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */ 2462 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */ 2463 #define USART_ICR_FECF_Pos (1U) 2464 #define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */ 2465 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */ 2466 #define USART_ICR_NECF_Pos (2U) 2467 #define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) /*!< 0x00000004 */ 2468 #define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */ 2469 #define USART_ICR_ORECF_Pos (3U) 2470 #define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */ 2471 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */ 2472 #define USART_ICR_IDLECF_Pos (4U) 2473 #define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */ 2474 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */ 2475 #define USART_ICR_TXFECF_Pos (5U) 2476 #define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */ 2477 #define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO Empty Clear Flag */ 2478 #define USART_ICR_TCCF_Pos (6U) 2479 #define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */ 2480 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */ 2481 #define USART_ICR_TCBGTCF_Pos (7U) 2482 #define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */ 2483 #define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */ 2484 #define USART_ICR_LBDCF_Pos (8U) 2485 #define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */ 2486 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */ 2487 #define USART_ICR_CTSCF_Pos (9U) 2488 #define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */ 2489 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */ 2490 #define USART_ICR_RTOCF_Pos (11U) 2491 #define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */ 2492 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */ 2493 #define USART_ICR_EOBCF_Pos (12U) 2494 #define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */ 2495 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */ 2496 #define USART_ICR_UDRCF_Pos (13U) 2497 #define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */ 2498 #define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI Slave Underrun Clear Flag */ 2499 #define USART_ICR_CMCF_Pos (17U) 2500 #define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */ 2501 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */ 2502 #define USART_ICR_WUCF_Pos (20U) 2503 #define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */ 2504 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */ 2505 2506 /******************* Bit definition for USART_RDR register ******************/ 2507 #define USART_RDR_RDR_Pos (0U) 2508 #define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */ 2509 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */ 2510 2511 /******************* Bit definition for USART_TDR register ******************/ 2512 #define USART_TDR_TDR_Pos (0U) 2513 #define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */ 2514 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */ 2515 2516 /******************* Bit definition for USART_PRESC register ****************/ 2517 #define USART_PRESC_PRESCALER_Pos (0U) 2518 #define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */ 2519 #define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */ 2520 #define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */ 2521 #define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */ 2522 #define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */ 2523 #define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */ 2524 2525 /******************************************************************************/ 2526 /* */ 2527 /* CRC calculation unit */ 2528 /* */ 2529 /******************************************************************************/ 2530 /******************* Bit definition for CRC_DR register *********************/ 2531 #define CRC_DR_DR_Pos (0U) 2532 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ 2533 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ 2534 2535 /******************* Bit definition for CRC_IDR register ********************/ 2536 #define CRC_IDR_IDR_Pos (0U) 2537 #define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ 2538 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bits data register bits */ 2539 2540 /******************** Bit definition for CRC_CR register ********************/ 2541 #define CRC_CR_RESET_Pos (0U) 2542 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ 2543 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ 2544 #define CRC_CR_POLYSIZE_Pos (3U) 2545 #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ 2546 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ 2547 #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ 2548 #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ 2549 #define CRC_CR_REV_IN_Pos (5U) 2550 #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ 2551 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ 2552 #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ 2553 #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ 2554 #define CRC_CR_REV_OUT_Pos (7U) 2555 #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ 2556 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ 2557 2558 /******************* Bit definition for CRC_INIT register *******************/ 2559 #define CRC_INIT_INIT_Pos (0U) 2560 #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ 2561 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ 2562 2563 /******************* Bit definition for CRC_POL register ********************/ 2564 #define CRC_POL_POL_Pos (0U) 2565 #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ 2566 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ 2567 2568 /******************************************************************************/ 2569 /* */ 2570 /* Advanced Encryption Standard (AES) */ 2571 /* */ 2572 /******************************************************************************/ 2573 /******************* Bit definition for AES_CR register *********************/ 2574 #define AES_CR_EN_Pos (0U) 2575 #define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */ 2576 #define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */ 2577 #define AES_CR_DATATYPE_Pos (1U) 2578 #define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ 2579 #define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */ 2580 #define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ 2581 #define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ 2582 2583 #define AES_CR_MODE_Pos (3U) 2584 #define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */ 2585 #define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */ 2586 #define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */ 2587 #define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */ 2588 2589 #define AES_CR_CHMOD_Pos (5U) 2590 #define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */ 2591 #define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ 2592 #define AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ 2593 #define AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ 2594 #define AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos) /*!< 0x00010000 */ 2595 2596 #define AES_CR_CCFC_Pos (7U) 2597 #define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */ 2598 #define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */ 2599 #define AES_CR_ERRC_Pos (8U) 2600 #define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */ 2601 #define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */ 2602 #define AES_CR_CCFIE_Pos (9U) 2603 #define AES_CR_CCFIE_Msk (0x1UL << AES_CR_CCFIE_Pos) /*!< 0x00000200 */ 2604 #define AES_CR_CCFIE AES_CR_CCFIE_Msk /*!< Computation Complete Flag Interrupt Enable */ 2605 #define AES_CR_ERRIE_Pos (10U) 2606 #define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */ 2607 #define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */ 2608 #define AES_CR_DMAINEN_Pos (11U) 2609 #define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ 2610 #define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ 2611 #define AES_CR_DMAOUTEN_Pos (12U) 2612 #define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ 2613 #define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ 2614 2615 #define AES_CR_GCMPH_Pos (13U) 2616 #define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */ 2617 #define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */ 2618 #define AES_CR_GCMPH_0 (0x1UL << AES_CR_GCMPH_Pos) /*!< 0x00002000 */ 2619 #define AES_CR_GCMPH_1 (0x2UL << AES_CR_GCMPH_Pos) /*!< 0x00004000 */ 2620 2621 #define AES_CR_KEYSIZE_Pos (18U) 2622 #define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ 2623 #define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */ 2624 2625 #define AES_CR_NPBLB_Pos (20U) 2626 #define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */ 2627 #define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in last payload block */ 2628 #define AES_CR_NPBLB_0 (0x1UL << AES_CR_NPBLB_Pos) /*!< 0x00100000 */ 2629 #define AES_CR_NPBLB_1 (0x2UL << AES_CR_NPBLB_Pos) /*!< 0x00200000 */ 2630 #define AES_CR_NPBLB_2 (0x4UL << AES_CR_NPBLB_Pos) /*!< 0x00400000 */ 2631 #define AES_CR_NPBLB_3 (0x8UL << AES_CR_NPBLB_Pos) /*!< 0x00800000 */ 2632 2633 /******************* Bit definition for AES_SR register *********************/ 2634 #define AES_SR_CCF_Pos (0U) 2635 #define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */ 2636 #define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */ 2637 #define AES_SR_RDERR_Pos (1U) 2638 #define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */ 2639 #define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */ 2640 #define AES_SR_WRERR_Pos (2U) 2641 #define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */ 2642 #define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */ 2643 #define AES_SR_BUSY_Pos (3U) 2644 #define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */ 2645 #define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */ 2646 2647 /******************* Bit definition for AES_DINR register *******************/ 2648 #define AES_DINR_Pos (0U) 2649 #define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */ 2650 #define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */ 2651 2652 /******************* Bit definition for AES_DOUTR register ******************/ 2653 #define AES_DOUTR_Pos (0U) 2654 #define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */ 2655 #define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */ 2656 2657 /******************* Bit definition for AES_KEYR0 register ******************/ 2658 #define AES_KEYR0_Pos (0U) 2659 #define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */ 2660 #define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */ 2661 2662 /******************* Bit definition for AES_KEYR1 register ******************/ 2663 #define AES_KEYR1_Pos (0U) 2664 #define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */ 2665 #define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */ 2666 2667 /******************* Bit definition for AES_KEYR2 register ******************/ 2668 #define AES_KEYR2_Pos (0U) 2669 #define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */ 2670 #define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */ 2671 2672 /******************* Bit definition for AES_KEYR3 register ******************/ 2673 #define AES_KEYR3_Pos (0U) 2674 #define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */ 2675 #define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */ 2676 2677 /******************* Bit definition for AES_KEYR4 register ******************/ 2678 #define AES_KEYR4_Pos (0U) 2679 #define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */ 2680 #define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */ 2681 2682 /******************* Bit definition for AES_KEYR5 register ******************/ 2683 #define AES_KEYR5_Pos (0U) 2684 #define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */ 2685 #define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */ 2686 2687 /******************* Bit definition for AES_KEYR6 register ******************/ 2688 #define AES_KEYR6_Pos (0U) 2689 #define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */ 2690 #define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */ 2691 2692 /******************* Bit definition for AES_KEYR7 register ******************/ 2693 #define AES_KEYR7_Pos (0U) 2694 #define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */ 2695 #define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */ 2696 2697 /******************* Bit definition for AES_IVR0 register ******************/ 2698 #define AES_IVR0_Pos (0U) 2699 #define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */ 2700 #define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */ 2701 2702 /******************* Bit definition for AES_IVR1 register ******************/ 2703 #define AES_IVR1_Pos (0U) 2704 #define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */ 2705 #define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */ 2706 2707 /******************* Bit definition for AES_IVR2 register ******************/ 2708 #define AES_IVR2_Pos (0U) 2709 #define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */ 2710 #define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */ 2711 2712 /******************* Bit definition for AES_IVR3 register ******************/ 2713 #define AES_IVR3_Pos (0U) 2714 #define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */ 2715 #define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */ 2716 2717 /******************* Bit definition for AES_SUSP0R register ******************/ 2718 #define AES_SUSP0R_Pos (0U) 2719 #define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */ 2720 #define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */ 2721 2722 /******************* Bit definition for AES_SUSP1R register ******************/ 2723 #define AES_SUSP1R_Pos (0U) 2724 #define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */ 2725 #define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */ 2726 2727 /******************* Bit definition for AES_SUSP2R register ******************/ 2728 #define AES_SUSP2R_Pos (0U) 2729 #define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */ 2730 #define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */ 2731 2732 /******************* Bit definition for AES_SUSP3R register ******************/ 2733 #define AES_SUSP3R_Pos (0U) 2734 #define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */ 2735 #define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */ 2736 2737 /******************* Bit definition for AES_SUSP4R register ******************/ 2738 #define AES_SUSP4R_Pos (0U) 2739 #define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */ 2740 #define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */ 2741 2742 /******************* Bit definition for AES_SUSP5R register ******************/ 2743 #define AES_SUSP5R_Pos (0U) 2744 #define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */ 2745 #define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */ 2746 2747 /******************* Bit definition for AES_SUSP6R register ******************/ 2748 #define AES_SUSP6R_Pos (0U) 2749 #define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */ 2750 #define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */ 2751 2752 /******************* Bit definition for AES_SUSP7R register ******************/ 2753 #define AES_SUSP7R_Pos (0U) 2754 #define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */ 2755 #define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */ 2756 2757 /******************************************************************************/ 2758 /* */ 2759 /* DMA Controller (DMA) */ 2760 /* */ 2761 /******************************************************************************/ 2762 2763 /******************* Bit definition for DMA_ISR register ********************/ 2764 #define DMA_ISR_GIF1_Pos (0U) 2765 #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ 2766 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ 2767 #define DMA_ISR_TCIF1_Pos (1U) 2768 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ 2769 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ 2770 #define DMA_ISR_HTIF1_Pos (2U) 2771 #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ 2772 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ 2773 #define DMA_ISR_TEIF1_Pos (3U) 2774 #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ 2775 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ 2776 #define DMA_ISR_GIF2_Pos (4U) 2777 #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ 2778 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ 2779 #define DMA_ISR_TCIF2_Pos (5U) 2780 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ 2781 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ 2782 #define DMA_ISR_HTIF2_Pos (6U) 2783 #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ 2784 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ 2785 #define DMA_ISR_TEIF2_Pos (7U) 2786 #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ 2787 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ 2788 #define DMA_ISR_GIF3_Pos (8U) 2789 #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ 2790 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ 2791 #define DMA_ISR_TCIF3_Pos (9U) 2792 #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ 2793 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ 2794 #define DMA_ISR_HTIF3_Pos (10U) 2795 #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ 2796 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ 2797 #define DMA_ISR_TEIF3_Pos (11U) 2798 #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ 2799 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ 2800 #define DMA_ISR_GIF4_Pos (12U) 2801 #define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ 2802 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ 2803 #define DMA_ISR_TCIF4_Pos (13U) 2804 #define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ 2805 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ 2806 #define DMA_ISR_HTIF4_Pos (14U) 2807 #define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ 2808 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ 2809 #define DMA_ISR_TEIF4_Pos (15U) 2810 #define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ 2811 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ 2812 #define DMA_ISR_GIF5_Pos (16U) 2813 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ 2814 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ 2815 #define DMA_ISR_TCIF5_Pos (17U) 2816 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ 2817 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ 2818 #define DMA_ISR_HTIF5_Pos (18U) 2819 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ 2820 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ 2821 #define DMA_ISR_TEIF5_Pos (19U) 2822 #define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ 2823 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ 2824 #define DMA_ISR_GIF6_Pos (20U) 2825 #define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ 2826 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ 2827 #define DMA_ISR_TCIF6_Pos (21U) 2828 #define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ 2829 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ 2830 #define DMA_ISR_HTIF6_Pos (22U) 2831 #define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ 2832 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ 2833 #define DMA_ISR_TEIF6_Pos (23U) 2834 #define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ 2835 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ 2836 #define DMA_ISR_GIF7_Pos (24U) 2837 #define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ 2838 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ 2839 #define DMA_ISR_TCIF7_Pos (25U) 2840 #define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ 2841 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ 2842 #define DMA_ISR_HTIF7_Pos (26U) 2843 #define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ 2844 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ 2845 #define DMA_ISR_TEIF7_Pos (27U) 2846 #define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ 2847 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ 2848 2849 /******************* Bit definition for DMA_IFCR register *******************/ 2850 #define DMA_IFCR_CGIF1_Pos (0U) 2851 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ 2852 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ 2853 #define DMA_IFCR_CTCIF1_Pos (1U) 2854 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ 2855 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ 2856 #define DMA_IFCR_CHTIF1_Pos (2U) 2857 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ 2858 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ 2859 #define DMA_IFCR_CTEIF1_Pos (3U) 2860 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ 2861 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ 2862 #define DMA_IFCR_CGIF2_Pos (4U) 2863 #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ 2864 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ 2865 #define DMA_IFCR_CTCIF2_Pos (5U) 2866 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ 2867 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ 2868 #define DMA_IFCR_CHTIF2_Pos (6U) 2869 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ 2870 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ 2871 #define DMA_IFCR_CTEIF2_Pos (7U) 2872 #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ 2873 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ 2874 #define DMA_IFCR_CGIF3_Pos (8U) 2875 #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ 2876 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ 2877 #define DMA_IFCR_CTCIF3_Pos (9U) 2878 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ 2879 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ 2880 #define DMA_IFCR_CHTIF3_Pos (10U) 2881 #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ 2882 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ 2883 #define DMA_IFCR_CTEIF3_Pos (11U) 2884 #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ 2885 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ 2886 #define DMA_IFCR_CGIF4_Pos (12U) 2887 #define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ 2888 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ 2889 #define DMA_IFCR_CTCIF4_Pos (13U) 2890 #define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ 2891 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ 2892 #define DMA_IFCR_CHTIF4_Pos (14U) 2893 #define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ 2894 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ 2895 #define DMA_IFCR_CTEIF4_Pos (15U) 2896 #define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ 2897 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ 2898 #define DMA_IFCR_CGIF5_Pos (16U) 2899 #define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ 2900 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ 2901 #define DMA_IFCR_CTCIF5_Pos (17U) 2902 #define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ 2903 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ 2904 #define DMA_IFCR_CHTIF5_Pos (18U) 2905 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ 2906 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ 2907 #define DMA_IFCR_CTEIF5_Pos (19U) 2908 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ 2909 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ 2910 #define DMA_IFCR_CGIF6_Pos (20U) 2911 #define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ 2912 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ 2913 #define DMA_IFCR_CTCIF6_Pos (21U) 2914 #define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ 2915 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ 2916 #define DMA_IFCR_CHTIF6_Pos (22U) 2917 #define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ 2918 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ 2919 #define DMA_IFCR_CTEIF6_Pos (23U) 2920 #define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ 2921 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ 2922 #define DMA_IFCR_CGIF7_Pos (24U) 2923 #define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ 2924 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ 2925 #define DMA_IFCR_CTCIF7_Pos (25U) 2926 #define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ 2927 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ 2928 #define DMA_IFCR_CHTIF7_Pos (26U) 2929 #define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ 2930 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ 2931 #define DMA_IFCR_CTEIF7_Pos (27U) 2932 #define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ 2933 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ 2934 2935 /******************* Bit definition for DMA_CCR register ********************/ 2936 #define DMA_CCR_EN_Pos (0U) 2937 #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ 2938 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ 2939 #define DMA_CCR_TCIE_Pos (1U) 2940 #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ 2941 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ 2942 #define DMA_CCR_HTIE_Pos (2U) 2943 #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ 2944 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ 2945 #define DMA_CCR_TEIE_Pos (3U) 2946 #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ 2947 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ 2948 #define DMA_CCR_DIR_Pos (4U) 2949 #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ 2950 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ 2951 #define DMA_CCR_CIRC_Pos (5U) 2952 #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ 2953 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ 2954 #define DMA_CCR_PINC_Pos (6U) 2955 #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ 2956 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ 2957 #define DMA_CCR_MINC_Pos (7U) 2958 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ 2959 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ 2960 2961 #define DMA_CCR_PSIZE_Pos (8U) 2962 #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ 2963 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ 2964 #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ 2965 #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ 2966 2967 #define DMA_CCR_MSIZE_Pos (10U) 2968 #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ 2969 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ 2970 #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ 2971 #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ 2972 2973 #define DMA_CCR_PL_Pos (12U) 2974 #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ 2975 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ 2976 #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ 2977 #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ 2978 2979 #define DMA_CCR_MEM2MEM_Pos (14U) 2980 #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ 2981 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ 2982 2983 2984 /****************** Bit definition for DMA_CNDTR register *******************/ 2985 #define DMA_CNDTR_NDT_Pos (0U) 2986 #define DMA_CNDTR_NDT_Msk (0x3FFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0003FFFF */ 2987 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ 2988 2989 /****************** Bit definition for DMA_CPAR register ********************/ 2990 #define DMA_CPAR_PA_Pos (0U) 2991 #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ 2992 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ 2993 2994 /****************** Bit definition for DMA_CMAR register ********************/ 2995 #define DMA_CMAR_MA_Pos (0U) 2996 #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ 2997 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ 2998 2999 /******************************************************************************/ 3000 /* */ 3001 /* DMAMUX Controller */ 3002 /* */ 3003 /******************************************************************************/ 3004 /******************** Bits definition for DMAMUX_CxCR register **************/ 3005 #define DMAMUX_CxCR_DMAREQ_ID_Pos (0U) 3006 #define DMAMUX_CxCR_DMAREQ_ID_Msk (0x7FUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x0000007F */ 3007 #define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA Request ID */ 3008 #define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000001 */ 3009 #define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000002 */ 3010 #define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000004 */ 3011 #define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000008 */ 3012 #define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000010 */ 3013 #define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000020 */ 3014 #define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000040 */ 3015 #define DMAMUX_CxCR_SOIE_Pos (8U) 3016 #define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ 3017 #define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ 3018 #define DMAMUX_CxCR_EGE_Pos (9U) 3019 #define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */ 3020 #define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation interrupt enable */ 3021 #define DMAMUX_CxCR_SE_Pos (16U) 3022 #define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */ 3023 #define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */ 3024 #define DMAMUX_CxCR_SPOL_Pos (17U) 3025 #define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */ 3026 #define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */ 3027 #define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */ 3028 #define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */ 3029 #define DMAMUX_CxCR_NBREQ_Pos (19U) 3030 #define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00F80000 */ 3031 #define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of request */ 3032 #define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00080000 */ 3033 #define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00100000 */ 3034 #define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00200000 */ 3035 #define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00400000 */ 3036 #define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00800000 */ 3037 #define DMAMUX_CxCR_SYNC_ID_Pos (24U) 3038 #define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x1F000000 */ 3039 #define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization ID */ 3040 #define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x01000000 */ 3041 #define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x02000000 */ 3042 #define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x04000000 */ 3043 #define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x08000000 */ 3044 #define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x10000000 */ 3045 3046 /******************* Bits definition for DMAMUX_CSR register **************/ 3047 #define DMAMUX_CSR_SOF0_Pos (0U) 3048 #define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */ 3049 #define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Synchronization Overrun Flag 0 */ 3050 #define DMAMUX_CSR_SOF1_Pos (1U) 3051 #define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */ 3052 #define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Synchronization Overrun Flag 1 */ 3053 #define DMAMUX_CSR_SOF2_Pos (2U) 3054 #define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */ 3055 #define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Synchronization Overrun Flag 2 */ 3056 #define DMAMUX_CSR_SOF3_Pos (3U) 3057 #define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */ 3058 #define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Synchronization Overrun Flag 3 */ 3059 #define DMAMUX_CSR_SOF4_Pos (4U) 3060 #define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */ 3061 #define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Synchronization Overrun Flag 4 */ 3062 #define DMAMUX_CSR_SOF5_Pos (5U) 3063 #define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */ 3064 #define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk /*!< Synchronization Overrun Flag 5 */ 3065 #define DMAMUX_CSR_SOF6_Pos (6U) 3066 #define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */ 3067 #define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk /*!< Synchronization Overrun Flag 6 */ 3068 #define DMAMUX_CSR_SOF7_Pos (7U) 3069 #define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos) /*!< 0x00000080 */ 3070 #define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk /*!< Synchronization Overrun Flag 7 */ 3071 #define DMAMUX_CSR_SOF8_Pos (8U) 3072 #define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos) /*!< 0x00000100 */ 3073 #define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk /*!< Synchronization Overrun Flag 8 */ 3074 #define DMAMUX_CSR_SOF9_Pos (9U) 3075 #define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos) /*!< 0x00000200 */ 3076 #define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk /*!< Synchronization Overrun Flag 9 */ 3077 #define DMAMUX_CSR_SOF10_Pos (10U) 3078 #define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos) /*!< 0x00000400 */ 3079 #define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk /*!< Synchronization Overrun Flag 10 */ 3080 #define DMAMUX_CSR_SOF11_Pos (11U) 3081 #define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos) /*!< 0x00000800 */ 3082 #define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk /*!< Synchronization Overrun Flag 11 */ 3083 #define DMAMUX_CSR_SOF12_Pos (12U) 3084 #define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos) /*!< 0x00001000 */ 3085 #define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk /*!< Synchronization Overrun Flag 12 */ 3086 #define DMAMUX_CSR_SOF13_Pos (13U) 3087 #define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos) /*!< 0x00002000 */ 3088 #define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk /*!< Synchronization Overrun Flag 13 */ 3089 3090 /******************** Bits definition for DMAMUX_CFR register **************/ 3091 #define DMAMUX_CFR_CSOF0_Pos (0U) 3092 #define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */ 3093 #define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Clear Overrun Flag 0 */ 3094 #define DMAMUX_CFR_CSOF1_Pos (1U) 3095 #define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */ 3096 #define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Clear Overrun Flag 1 */ 3097 #define DMAMUX_CFR_CSOF2_Pos (2U) 3098 #define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */ 3099 #define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Clear Overrun Flag 2 */ 3100 #define DMAMUX_CFR_CSOF3_Pos (3U) 3101 #define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */ 3102 #define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Clear Overrun Flag 3 */ 3103 #define DMAMUX_CFR_CSOF4_Pos (4U) 3104 #define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */ 3105 #define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Clear Overrun Flag 4 */ 3106 #define DMAMUX_CFR_CSOF5_Pos (5U) 3107 #define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */ 3108 #define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk /*!< Clear Overrun Flag 5 */ 3109 #define DMAMUX_CFR_CSOF6_Pos (6U) 3110 #define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */ 3111 #define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk /*!< Clear Overrun Flag 6 */ 3112 #define DMAMUX_CFR_CSOF7_Pos (7U) 3113 #define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos) /*!< 0x00000080 */ 3114 #define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk /*!< Clear Overrun Flag 7 */ 3115 #define DMAMUX_CFR_CSOF8_Pos (8U) 3116 #define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos) /*!< 0x00000100 */ 3117 #define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk /*!< Clear Overrun Flag 8 */ 3118 #define DMAMUX_CFR_CSOF9_Pos (9U) 3119 #define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos) /*!< 0x00000200 */ 3120 #define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk /*!< Clear Overrun Flag 9 */ 3121 #define DMAMUX_CFR_CSOF10_Pos (10U) 3122 #define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos)/*!< 0x00000400 */ 3123 #define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk /*!< Clear Overrun Flag 10 */ 3124 #define DMAMUX_CFR_CSOF11_Pos (11U) 3125 #define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos)/*!< 0x00000800 */ 3126 #define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk /*!< Clear Overrun Flag 11 */ 3127 #define DMAMUX_CFR_CSOF12_Pos (12U) 3128 #define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos)/*!< 0x00001000 */ 3129 #define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk /*!< Clear Overrun Flag 12 */ 3130 #define DMAMUX_CFR_CSOF13_Pos (13U) 3131 #define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos)/*!< 0x00002000 */ 3132 #define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk /*!< Clear Overrun Flag 13 */ 3133 3134 /******************** Bits definition for DMAMUX_RGxCR register ************/ 3135 #define DMAMUX_RGxCR_SIG_ID_Pos (0U) 3136 #define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x0000001F */ 3137 #define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal ID */ 3138 #define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000001 */ 3139 #define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000002 */ 3140 #define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000004 */ 3141 #define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000008 */ 3142 #define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000010 */ 3143 #define DMAMUX_RGxCR_OIE_Pos (8U) 3144 #define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */ 3145 #define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Overrun interrupt enable */ 3146 #define DMAMUX_RGxCR_GE_Pos (16U) 3147 #define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */ 3148 #define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< Generation enable */ 3149 #define DMAMUX_RGxCR_GPOL_Pos (17U) 3150 #define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00060000 */ 3151 #define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< Generation polarity */ 3152 #define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00020000 */ 3153 #define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00040000 */ 3154 #define DMAMUX_RGxCR_GNBREQ_Pos (19U) 3155 #define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00F80000 */ 3156 #define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of request */ 3157 #define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00080000 */ 3158 #define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00100000 */ 3159 #define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00200000 */ 3160 #define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00400000 */ 3161 #define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00800000 */ 3162 3163 /******************** Bits definition for DMAMUX_RGSR register **************/ 3164 #define DMAMUX_RGSR_OF0_Pos (0U) 3165 #define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */ 3166 #define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Overrun flag 0 */ 3167 #define DMAMUX_RGSR_OF1_Pos (1U) 3168 #define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */ 3169 #define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Overrun flag 1 */ 3170 #define DMAMUX_RGSR_OF2_Pos (2U) 3171 #define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */ 3172 #define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Overrun flag 2 */ 3173 #define DMAMUX_RGSR_OF3_Pos (3U) 3174 #define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */ 3175 #define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Overrun flag 3 */ 3176 3177 /******************** Bits definition for DMAMUX_RGCFR register **************/ 3178 #define DMAMUX_RGCFR_COF0_Pos (0U) 3179 #define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos)/*!< 0x00000001 */ 3180 #define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Clear Overrun flag 0 */ 3181 #define DMAMUX_RGCFR_COF1_Pos (1U) 3182 #define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos)/*!< 0x00000002 */ 3183 #define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Clear Overrun flag 1 */ 3184 #define DMAMUX_RGCFR_COF2_Pos (2U) 3185 #define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos)/*!< 0x00000004 */ 3186 #define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Clear Overrun flag 2 */ 3187 #define DMAMUX_RGCFR_COF3_Pos (3U) 3188 #define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos)/*!< 0x00000008 */ 3189 #define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */ 3190 3191 /******************************************************************************/ 3192 /* */ 3193 /* Asynchronous Interrupt/Event Controller */ 3194 /* */ 3195 /******************************************************************************/ 3196 3197 /****************** Bit definition for EXTI_RTSR1 register ******************/ 3198 #define EXTI_RTSR1_RT0_Pos (0U) 3199 #define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ 3200 #define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */ 3201 #define EXTI_RTSR1_RT1_Pos (1U) 3202 #define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ 3203 #define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */ 3204 #define EXTI_RTSR1_RT2_Pos (2U) 3205 #define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ 3206 #define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */ 3207 #define EXTI_RTSR1_RT3_Pos (3U) 3208 #define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ 3209 #define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */ 3210 #define EXTI_RTSR1_RT4_Pos (4U) 3211 #define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ 3212 #define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */ 3213 #define EXTI_RTSR1_RT5_Pos (5U) 3214 #define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ 3215 #define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */ 3216 #define EXTI_RTSR1_RT6_Pos (6U) 3217 #define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ 3218 #define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */ 3219 #define EXTI_RTSR1_RT7_Pos (7U) 3220 #define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ 3221 #define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */ 3222 #define EXTI_RTSR1_RT8_Pos (8U) 3223 #define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ 3224 #define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */ 3225 #define EXTI_RTSR1_RT9_Pos (9U) 3226 #define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ 3227 #define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */ 3228 #define EXTI_RTSR1_RT10_Pos (10U) 3229 #define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ 3230 #define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */ 3231 #define EXTI_RTSR1_RT11_Pos (11U) 3232 #define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ 3233 #define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */ 3234 #define EXTI_RTSR1_RT12_Pos (12U) 3235 #define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ 3236 #define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */ 3237 #define EXTI_RTSR1_RT13_Pos (13U) 3238 #define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ 3239 #define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */ 3240 #define EXTI_RTSR1_RT14_Pos (14U) 3241 #define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ 3242 #define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */ 3243 #define EXTI_RTSR1_RT15_Pos (15U) 3244 #define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ 3245 #define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */ 3246 #define EXTI_RTSR1_RT16_Pos (16U) 3247 #define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */ 3248 #define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */ 3249 #define EXTI_RTSR1_RT21_Pos (21U) 3250 #define EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */ 3251 #define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */ 3252 #define EXTI_RTSR1_RT22_Pos (22U) 3253 #define EXTI_RTSR1_RT22_Msk (0x1UL << EXTI_RTSR1_RT22_Pos) /*!< 0x00400000 */ 3254 #define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */ 3255 3256 /****************** Bit definition for EXTI_FTSR1 register ******************/ 3257 #define EXTI_FTSR1_FT0_Pos (0U) 3258 #define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ 3259 #define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */ 3260 #define EXTI_FTSR1_FT1_Pos (1U) 3261 #define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ 3262 #define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */ 3263 #define EXTI_FTSR1_FT2_Pos (2U) 3264 #define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ 3265 #define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */ 3266 #define EXTI_FTSR1_FT3_Pos (3U) 3267 #define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ 3268 #define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */ 3269 #define EXTI_FTSR1_FT4_Pos (4U) 3270 #define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ 3271 #define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */ 3272 #define EXTI_FTSR1_FT5_Pos (5U) 3273 #define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ 3274 #define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */ 3275 #define EXTI_FTSR1_FT6_Pos (6U) 3276 #define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ 3277 #define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */ 3278 #define EXTI_FTSR1_FT7_Pos (7U) 3279 #define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ 3280 #define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */ 3281 #define EXTI_FTSR1_FT8_Pos (8U) 3282 #define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ 3283 #define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */ 3284 #define EXTI_FTSR1_FT9_Pos (9U) 3285 #define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ 3286 #define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */ 3287 #define EXTI_FTSR1_FT10_Pos (10U) 3288 #define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ 3289 #define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */ 3290 #define EXTI_FTSR1_FT11_Pos (11U) 3291 #define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ 3292 #define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */ 3293 #define EXTI_FTSR1_FT12_Pos (12U) 3294 #define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ 3295 #define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */ 3296 #define EXTI_FTSR1_FT13_Pos (13U) 3297 #define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ 3298 #define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */ 3299 #define EXTI_FTSR1_FT14_Pos (14U) 3300 #define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ 3301 #define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */ 3302 #define EXTI_FTSR1_FT15_Pos (15U) 3303 #define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ 3304 #define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */ 3305 #define EXTI_FTSR1_FT16_Pos (16U) 3306 #define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */ 3307 #define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */ 3308 #define EXTI_FTSR1_FT21_Pos (21U) 3309 #define EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */ 3310 #define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */ 3311 #define EXTI_FTSR1_FT22_Pos (22U) 3312 #define EXTI_FTSR1_FT22_Msk (0x1UL << EXTI_FTSR1_FT22_Pos) /*!< 0x00400000 */ 3313 #define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */ 3314 3315 /****************** Bit definition for EXTI_SWIER1 register *****************/ 3316 #define EXTI_SWIER1_SWI0_Pos (0U) 3317 #define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ 3318 #define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */ 3319 #define EXTI_SWIER1_SWI1_Pos (1U) 3320 #define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ 3321 #define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */ 3322 #define EXTI_SWIER1_SWI2_Pos (2U) 3323 #define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ 3324 #define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */ 3325 #define EXTI_SWIER1_SWI3_Pos (3U) 3326 #define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ 3327 #define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */ 3328 #define EXTI_SWIER1_SWI4_Pos (4U) 3329 #define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ 3330 #define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */ 3331 #define EXTI_SWIER1_SWI5_Pos (5U) 3332 #define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ 3333 #define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */ 3334 #define EXTI_SWIER1_SWI6_Pos (6U) 3335 #define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ 3336 #define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */ 3337 #define EXTI_SWIER1_SWI7_Pos (7U) 3338 #define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ 3339 #define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */ 3340 #define EXTI_SWIER1_SWI8_Pos (8U) 3341 #define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ 3342 #define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */ 3343 #define EXTI_SWIER1_SWI9_Pos (9U) 3344 #define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ 3345 #define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */ 3346 #define EXTI_SWIER1_SWI10_Pos (10U) 3347 #define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ 3348 #define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */ 3349 #define EXTI_SWIER1_SWI11_Pos (11U) 3350 #define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ 3351 #define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */ 3352 #define EXTI_SWIER1_SWI12_Pos (12U) 3353 #define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ 3354 #define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */ 3355 #define EXTI_SWIER1_SWI13_Pos (13U) 3356 #define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ 3357 #define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */ 3358 #define EXTI_SWIER1_SWI14_Pos (14U) 3359 #define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ 3360 #define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */ 3361 #define EXTI_SWIER1_SWI15_Pos (15U) 3362 #define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ 3363 #define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */ 3364 #define EXTI_SWIER1_SWI16_Pos (16U) 3365 #define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */ 3366 #define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */ 3367 #define EXTI_SWIER1_SWI21_Pos (21U) 3368 #define EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */ 3369 #define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */ 3370 #define EXTI_SWIER1_SWI22_Pos (22U) 3371 #define EXTI_SWIER1_SWI22_Msk (0x1UL << EXTI_SWIER1_SWI22_Pos) /*!< 0x00400000 */ 3372 #define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk /*!< Software Interrupt on line 22 */ 3373 3374 /******************* Bit definition for EXTI_PR1 register *******************/ 3375 #define EXTI_PR1_PIF0_Pos (0U) 3376 #define EXTI_PR1_PIF0_Msk (0x1UL << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */ 3377 #define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */ 3378 #define EXTI_PR1_PIF1_Pos (1U) 3379 #define EXTI_PR1_PIF1_Msk (0x1UL << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */ 3380 #define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */ 3381 #define EXTI_PR1_PIF2_Pos (2U) 3382 #define EXTI_PR1_PIF2_Msk (0x1UL << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */ 3383 #define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */ 3384 #define EXTI_PR1_PIF3_Pos (3U) 3385 #define EXTI_PR1_PIF3_Msk (0x1UL << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */ 3386 #define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */ 3387 #define EXTI_PR1_PIF4_Pos (4U) 3388 #define EXTI_PR1_PIF4_Msk (0x1UL << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */ 3389 #define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */ 3390 #define EXTI_PR1_PIF5_Pos (5U) 3391 #define EXTI_PR1_PIF5_Msk (0x1UL << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */ 3392 #define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */ 3393 #define EXTI_PR1_PIF6_Pos (6U) 3394 #define EXTI_PR1_PIF6_Msk (0x1UL << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */ 3395 #define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */ 3396 #define EXTI_PR1_PIF7_Pos (7U) 3397 #define EXTI_PR1_PIF7_Msk (0x1UL << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */ 3398 #define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */ 3399 #define EXTI_PR1_PIF8_Pos (8U) 3400 #define EXTI_PR1_PIF8_Msk (0x1UL << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */ 3401 #define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */ 3402 #define EXTI_PR1_PIF9_Pos (9U) 3403 #define EXTI_PR1_PIF9_Msk (0x1UL << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */ 3404 #define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */ 3405 #define EXTI_PR1_PIF10_Pos (10U) 3406 #define EXTI_PR1_PIF10_Msk (0x1UL << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */ 3407 #define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */ 3408 #define EXTI_PR1_PIF11_Pos (11U) 3409 #define EXTI_PR1_PIF11_Msk (0x1UL << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */ 3410 #define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */ 3411 #define EXTI_PR1_PIF12_Pos (12U) 3412 #define EXTI_PR1_PIF12_Msk (0x1UL << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */ 3413 #define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */ 3414 #define EXTI_PR1_PIF13_Pos (13U) 3415 #define EXTI_PR1_PIF13_Msk (0x1UL << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */ 3416 #define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */ 3417 #define EXTI_PR1_PIF14_Pos (14U) 3418 #define EXTI_PR1_PIF14_Msk (0x1UL << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */ 3419 #define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */ 3420 #define EXTI_PR1_PIF15_Pos (15U) 3421 #define EXTI_PR1_PIF15_Msk (0x1UL << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */ 3422 #define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */ 3423 #define EXTI_PR1_PIF16_Pos (16U) 3424 #define EXTI_PR1_PIF16_Msk (0x1UL << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */ 3425 #define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */ 3426 #define EXTI_PR1_PIF21_Pos (21U) 3427 #define EXTI_PR1_PIF21_Msk (0x1UL << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */ 3428 #define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */ 3429 #define EXTI_PR1_PIF22_Pos (22U) 3430 #define EXTI_PR1_PIF22_Msk (0x1UL << EXTI_PR1_PIF22_Pos) /*!< 0x00400000 */ 3431 #define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk /*!< Pending bit for line 22 */ 3432 3433 /****************** Bit definition for EXTI_RTSR2 register ******************/ 3434 #define EXTI_RTSR2_RT34_Pos (2U) 3435 #define EXTI_RTSR2_RT34_Msk (0x1UL << EXTI_RTSR2_RT34_Pos) /*!< 0x00000004 */ 3436 #define EXTI_RTSR2_RT34 EXTI_RTSR2_RT34_Msk /*!< Rising trigger event configuration bit of line 34 */ 3437 #define EXTI_RTSR2_RT45_Pos (13U) 3438 #define EXTI_RTSR2_RT45_Msk (0x1UL << EXTI_RTSR2_RT45_Pos) /*!< 0x00002000 */ 3439 #define EXTI_RTSR2_RT45 EXTI_RTSR2_RT45_Msk /*!< Rising trigger event configuration bit of line 45 */ 3440 3441 /****************** Bit definition for EXTI_FTSR2 register ******************/ 3442 #define EXTI_FTSR2_FT34_Pos (2U) 3443 #define EXTI_FTSR2_FT34_Msk (0x1UL << EXTI_FTSR2_FT34_Pos) /*!< 0x00000004 */ 3444 #define EXTI_FTSR2_FT34 EXTI_FTSR2_FT34_Msk /*!< Falling trigger event configuration bit of line 34 */ 3445 #define EXTI_FTSR2_FT45_Pos (13U) 3446 #define EXTI_FTSR2_FT45_Msk (0x1UL << EXTI_FTSR2_FT45_Pos) /*!< 0x00002000 */ 3447 #define EXTI_FTSR2_FT45 EXTI_FTSR2_FT45_Msk /*!< Falling trigger event configuration bit of line 45 */ 3448 3449 /****************** Bit definition for EXTI_SWIER2 register *****************/ 3450 #define EXTI_SWIER2_SWI34_Pos (2U) 3451 #define EXTI_SWIER2_SWI34_Msk (0x1UL << EXTI_SWIER2_SWI34_Pos) /*!< 0x00000004 */ 3452 #define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWI34_Msk /*!< Software Interrupt on line 34 */ 3453 #define EXTI_SWIER2_SWI45_Pos (13U) 3454 #define EXTI_SWIER2_SWI45_Msk (0x1UL << EXTI_SWIER2_SWI45_Pos) /*!< 0x00002000 */ 3455 #define EXTI_SWIER2_SWI45 EXTI_SWIER2_SWI45_Msk /*!< Software Interrupt on line 45 */ 3456 3457 /******************* Bit definition for EXTI_PR2 register *******************/ 3458 #define EXTI_PR2_PIF34_Pos (2U) 3459 #define EXTI_PR2_PIF34_Msk (0x1UL << EXTI_PR2_PIF34_Pos) /*!< 0x00000004 */ 3460 #define EXTI_PR2_PIF34 EXTI_PR2_PIF34_Msk /*!< Pending bit for line 34 */ 3461 #define EXTI_PR2_PIF45_Pos (13U) 3462 #define EXTI_PR2_PIF45_Msk (0x1UL << EXTI_PR2_PIF45_Pos) /*!< 0x00002000 */ 3463 #define EXTI_PR2_PIF45 EXTI_PR2_PIF45_Msk /*!< Pending bit for line 45 */ 3464 3465 /******************** Bits definition for EXTI_IMR1 register **************/ 3466 #define EXTI_IMR1_IM0_Pos (0U) 3467 #define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ 3468 #define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< CPU1 Interrupt Mask on line 0 */ 3469 #define EXTI_IMR1_IM1_Pos (1U) 3470 #define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ 3471 #define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< CPU1 Interrupt Mask on line 1 */ 3472 #define EXTI_IMR1_IM2_Pos (2U) 3473 #define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ 3474 #define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< CPU1 Interrupt Mask on line 2 */ 3475 #define EXTI_IMR1_IM3_Pos (3U) 3476 #define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ 3477 #define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< CPU1 Interrupt Mask on line 3 */ 3478 #define EXTI_IMR1_IM4_Pos (4U) 3479 #define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ 3480 #define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< CPU1 Interrupt Mask on line 4 */ 3481 #define EXTI_IMR1_IM5_Pos (5U) 3482 #define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ 3483 #define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< CPU1 Interrupt Mask on line 5 */ 3484 #define EXTI_IMR1_IM6_Pos (6U) 3485 #define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ 3486 #define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< CPU1 Interrupt Mask on line 6 */ 3487 #define EXTI_IMR1_IM7_Pos (7U) 3488 #define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ 3489 #define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< CPU1 Interrupt Mask on line 7 */ 3490 #define EXTI_IMR1_IM8_Pos (8U) 3491 #define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ 3492 #define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< CPU1 Interrupt Mask on line 8 */ 3493 #define EXTI_IMR1_IM9_Pos (9U) 3494 #define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ 3495 #define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< CPU1 Interrupt Mask on line 9 */ 3496 #define EXTI_IMR1_IM10_Pos (10U) 3497 #define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ 3498 #define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< CPU1 Interrupt Mask on line 10 */ 3499 #define EXTI_IMR1_IM11_Pos (11U) 3500 #define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ 3501 #define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< CPU1 Interrupt Mask on line 11 */ 3502 #define EXTI_IMR1_IM12_Pos (12U) 3503 #define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ 3504 #define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< CPU1 Interrupt Mask on line 12 */ 3505 #define EXTI_IMR1_IM13_Pos (13U) 3506 #define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ 3507 #define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< CPU1 Interrupt Mask on line 13 */ 3508 #define EXTI_IMR1_IM14_Pos (14U) 3509 #define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ 3510 #define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< CPU1 Interrupt Mask on line 14 */ 3511 #define EXTI_IMR1_IM15_Pos (15U) 3512 #define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ 3513 #define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< CPU1 Interrupt Mask on line 15 */ 3514 #define EXTI_IMR1_IM16_Pos (16U) 3515 #define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */ 3516 #define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< CPU1 Interrupt Mask on line 16 */ 3517 #define EXTI_IMR1_IM17_Pos (17U) 3518 #define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */ 3519 #define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< CPU1 Interrupt Mask on line 17 */ 3520 #define EXTI_IMR1_IM18_Pos (18U) 3521 #define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */ 3522 #define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< CPU1 Interrupt Mask on line 18 */ 3523 #define EXTI_IMR1_IM19_Pos (19U) 3524 #define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ 3525 #define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< CPU1 Interrupt Mask on line 19 */ 3526 #define EXTI_IMR1_IM20_Pos (20U) 3527 #define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */ 3528 #define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< CPU1 Interrupt Mask on line 20 */ 3529 #define EXTI_IMR1_IM21_Pos (21U) 3530 #define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */ 3531 #define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< CPU1 Interrupt Mask on line 21 */ 3532 #define EXTI_IMR1_IM22_Pos (22U) 3533 #define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */ 3534 #define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< CPU1 Interrupt Mask on line 22 */ 3535 #define EXTI_IMR1_IM23_Pos (23U) 3536 #define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ 3537 #define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< CPU1 Interrupt Mask on line 23 */ 3538 #define EXTI_IMR1_IM24_Pos (24U) 3539 #define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */ 3540 #define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< CPU1 Interrupt Mask on line 24 */ 3541 #define EXTI_IMR1_IM25_Pos (25U) 3542 #define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ 3543 #define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< CPU1 Interrupt Mask on line 25 */ 3544 #define EXTI_IMR1_IM26_Pos (26U) 3545 #define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */ 3546 #define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< CPU1 Interrupt Mask on line 26 */ 3547 #define EXTI_IMR1_IM27_Pos (27U) 3548 #define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */ 3549 #define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< CPU1 Interrupt Mask on line 27 */ 3550 #define EXTI_IMR1_IM28_Pos (28U) 3551 #define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */ 3552 #define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< CPU1 Interrupt Mask on line 28 */ 3553 #define EXTI_IMR1_IM29_Pos (29U) 3554 #define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */ 3555 #define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< CPU1 Interrupt Mask on line 29 */ 3556 #define EXTI_IMR1_IM30_Pos (30U) 3557 #define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */ 3558 #define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< CPU1 Interrupt Mask on line 30 */ 3559 #define EXTI_IMR1_IM31_Pos (31U) 3560 #define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ 3561 #define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< CPU1 Interrupt Mask on line 31 */ 3562 3563 /******************** Bits definition for EXTI_EMR1 register **************/ 3564 #define EXTI_EMR1_EM0_Pos (0U) 3565 #define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ 3566 #define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< CPU1 Event Mask on line 0 */ 3567 #define EXTI_EMR1_EM1_Pos (1U) 3568 #define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ 3569 #define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< CPU1 Event Mask on line 1 */ 3570 #define EXTI_EMR1_EM2_Pos (2U) 3571 #define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ 3572 #define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< CPU1 Event Mask on line 2 */ 3573 #define EXTI_EMR1_EM3_Pos (3U) 3574 #define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ 3575 #define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< CPU1 Event Mask on line 3 */ 3576 #define EXTI_EMR1_EM4_Pos (4U) 3577 #define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ 3578 #define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< CPU1 Event Mask on line 4 */ 3579 #define EXTI_EMR1_EM5_Pos (5U) 3580 #define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ 3581 #define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< CPU1 Event Mask on line 5 */ 3582 #define EXTI_EMR1_EM6_Pos (6U) 3583 #define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ 3584 #define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< CPU1 Event Mask on line 6 */ 3585 #define EXTI_EMR1_EM7_Pos (7U) 3586 #define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ 3587 #define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< CPU1 Event Mask on line 7 */ 3588 #define EXTI_EMR1_EM8_Pos (8U) 3589 #define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ 3590 #define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< CPU1 Event Mask on line 8 */ 3591 #define EXTI_EMR1_EM9_Pos (9U) 3592 #define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ 3593 #define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< CPU1 Event Mask on line 9 */ 3594 #define EXTI_EMR1_EM10_Pos (10U) 3595 #define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ 3596 #define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< CPU1 Event Mask on line 10 */ 3597 #define EXTI_EMR1_EM11_Pos (11U) 3598 #define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ 3599 #define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< CPU1 Event Mask on line 11 */ 3600 #define EXTI_EMR1_EM12_Pos (12U) 3601 #define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ 3602 #define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< CPU1 Event Mask on line 12 */ 3603 #define EXTI_EMR1_EM13_Pos (13U) 3604 #define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ 3605 #define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< CPU1 Event Mask on line 13 */ 3606 #define EXTI_EMR1_EM14_Pos (14U) 3607 #define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ 3608 #define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< CPU1 Event Mask on line 14 */ 3609 #define EXTI_EMR1_EM15_Pos (15U) 3610 #define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ 3611 #define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< CPU1 Event Mask on line 15 */ 3612 #define EXTI_EMR1_EM17_Pos (17U) 3613 #define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ 3614 #define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< CPU1 Event Mask on line 17 */ 3615 #define EXTI_EMR1_EM19_Pos (19U) 3616 #define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ 3617 #define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< CPU1 Event Mask on line 19 */ 3618 #define EXTI_EMR1_EM20_Pos (20U) 3619 #define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */ 3620 #define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< CPU1 Event Mask on line 20 */ 3621 #define EXTI_EMR1_EM21_Pos (21U) 3622 #define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */ 3623 #define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< CPU1 Event Mask on line 21 */ 3624 #define EXTI_EMR1_EM22_Pos (22U) 3625 #define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */ 3626 #define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< CPU1 Event Mask on line 22 */ 3627 3628 /******************** Bits definition for EXTI_IMR2 register **************/ 3629 #define EXTI_IMR2_IM34_Pos (2U) 3630 #define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */ 3631 #define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< CPU1 Interrupt Mask on line 34 */ 3632 #define EXTI_IMR2_IM38_Pos (6U) 3633 #define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */ 3634 #define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< CPU1 Interrupt Mask on line 38 */ 3635 #define EXTI_IMR2_IM42_Pos (10U) 3636 #define EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos) /*!< 0x00000400 */ 3637 #define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk /*!< CPU1 Interrupt Mask on line 42 */ 3638 #define EXTI_IMR2_IM43_Pos (11U) 3639 #define EXTI_IMR2_IM43_Msk (0x1UL << EXTI_IMR2_IM43_Pos) /*!< 0x00000800 */ 3640 #define EXTI_IMR2_IM43 EXTI_IMR2_IM43_Msk /*!< CPU1 Interrupt Mask on line 43 */ 3641 #define EXTI_IMR2_IM44_Pos (12U) 3642 #define EXTI_IMR2_IM44_Msk (0x1UL << EXTI_IMR2_IM44_Pos) /*!< 0x00001000 */ 3643 #define EXTI_IMR2_IM44 EXTI_IMR2_IM44_Msk /*!< CPU1 Interrupt Mask on line 44 */ 3644 #define EXTI_IMR2_IM45_Pos (13U) 3645 #define EXTI_IMR2_IM45_Msk (0x1UL << EXTI_IMR2_IM45_Pos) /*!< 0x00002000 */ 3646 #define EXTI_IMR2_IM45 EXTI_IMR2_IM45_Msk /*!< CPU1 Interrupt Mask on line 45 */ 3647 #define EXTI_IMR2_IM46_Pos (14U) 3648 #define EXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos) /*!< 0x00004000 */ 3649 #define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk /*!< CPU1 Interrupt Mask on line 46 */ 3650 3651 /******************************************************************************/ 3652 /* */ 3653 /* FLASH */ 3654 /* */ 3655 /******************************************************************************/ 3656 /******************* Bits definition for FLASH_ACR register *****************/ 3657 #define FLASH_ACR_LATENCY_Pos (0U) 3658 #define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ 3659 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ 3660 #define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ 3661 #define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ 3662 #define FLASH_ACR_PRFTEN_Pos (8U) 3663 #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ 3664 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ 3665 #define FLASH_ACR_ICEN_Pos (9U) 3666 #define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */ 3667 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk /*!< Instruction cache enable */ 3668 #define FLASH_ACR_DCEN_Pos (10U) 3669 #define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */ 3670 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk /*!< Data cache enable */ 3671 #define FLASH_ACR_ICRST_Pos (11U) 3672 #define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */ 3673 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk /*!< Instruction cache reset */ 3674 #define FLASH_ACR_DCRST_Pos (12U) 3675 #define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */ 3676 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk /*!< Data cache reset */ 3677 #define FLASH_ACR_PES_Pos (15U) 3678 #define FLASH_ACR_PES_Msk (0x1UL << FLASH_ACR_PES_Pos) /*!< 0x00008000 */ 3679 #define FLASH_ACR_PES FLASH_ACR_PES_Msk /*!< Program/erase suspend request */ 3680 #define FLASH_ACR_EMPTY_Pos (16U) 3681 #define FLASH_ACR_EMPTY_Msk (0x1UL << FLASH_ACR_EMPTY_Pos) /*!< 0x00010000 */ 3682 #define FLASH_ACR_EMPTY FLASH_ACR_EMPTY_Msk /*!< Flash use area empty */ 3683 3684 /******************* Bits definition for FLASH_SR register ******************/ 3685 #define FLASH_SR_EOP_Pos (0U) 3686 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */ 3687 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of Operation */ 3688 #define FLASH_SR_OPERR_Pos (1U) 3689 #define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */ 3690 #define FLASH_SR_OPERR FLASH_SR_OPERR_Msk /*!< Operation error */ 3691 #define FLASH_SR_PROGERR_Pos (3U) 3692 #define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */ 3693 #define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk /*!< Programming error */ 3694 #define FLASH_SR_WRPERR_Pos (4U) 3695 #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ 3696 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */ 3697 #define FLASH_SR_PGAERR_Pos (5U) 3698 #define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */ 3699 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming alignment error */ 3700 #define FLASH_SR_SIZERR_Pos (6U) 3701 #define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */ 3702 #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */ 3703 #define FLASH_SR_PGSERR_Pos (7U) 3704 #define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */ 3705 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error */ 3706 #define FLASH_SR_MISERR_Pos (8U) 3707 #define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */ 3708 #define FLASH_SR_MISERR FLASH_SR_MISERR_Msk /*!< Fast programming data miss error */ 3709 #define FLASH_SR_FASTERR_Pos (9U) 3710 #define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */ 3711 #define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk /*!< Fast programming error */ 3712 #define FLASH_SR_OPTNV_Pos (13U) 3713 #define FLASH_SR_OPTNV_Msk (0x1UL << FLASH_SR_OPTNV_Pos) /*!< 0x00002000 */ 3714 #define FLASH_SR_OPTNV FLASH_SR_OPTNV_Msk /*!< User option OPTVAL indication */ 3715 #define FLASH_SR_RDERR_Pos (14U) 3716 #define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */ 3717 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< PCROP read error */ 3718 #define FLASH_SR_OPTVERR_Pos (15U) 3719 #define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */ 3720 #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option validity error */ 3721 #define FLASH_SR_BSY_Pos (16U) 3722 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */ 3723 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Flash Busy */ 3724 #define FLASH_SR_CFGBSY_Pos (18U) 3725 #define FLASH_SR_CFGBSY_Msk (0x1UL << FLASH_SR_CFGBSY_Pos) /*!< 0x00040000 */ 3726 #define FLASH_SR_CFGBSY FLASH_SR_CFGBSY_Msk /*!< Programming or erase configuration busy */ 3727 #define FLASH_SR_PESD_Pos (19U) 3728 #define FLASH_SR_PESD_Msk (0x1UL << FLASH_SR_PESD_Pos) /*!< 0x00080000 */ 3729 #define FLASH_SR_PESD FLASH_SR_PESD_Msk /*!< Programming/erase operation suspended */ 3730 3731 /******************* Bits definition for FLASH_CR register ******************/ 3732 #define FLASH_CR_PG_Pos (0U) 3733 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ 3734 #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Flash programming */ 3735 #define FLASH_CR_PER_Pos (1U) 3736 #define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ 3737 #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page erase */ 3738 #define FLASH_CR_MER_Pos (2U) 3739 #define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */ 3740 #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass erase */ 3741 #define FLASH_CR_PNB_Pos (3U) 3742 #define FLASH_CR_PNB_Msk (0x7FUL << FLASH_CR_PNB_Pos) /*!< 0x000003F8 */ 3743 #define FLASH_CR_PNB FLASH_CR_PNB_Msk /*!< Page number selection mask */ 3744 #define FLASH_CR_STRT_Pos (16U) 3745 #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */ 3746 #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start an erase operation */ 3747 #define FLASH_CR_OPTSTRT_Pos (17U) 3748 #define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */ 3749 #define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk /*!< Options modification start */ 3750 #define FLASH_CR_FSTPG_Pos (18U) 3751 #define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */ 3752 #define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk /*!< Fast programming */ 3753 #define FLASH_CR_EOPIE_Pos (24U) 3754 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ 3755 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */ 3756 #define FLASH_CR_ERRIE_Pos (25U) 3757 #define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */ 3758 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error interrupt enable */ 3759 #define FLASH_CR_RDERRIE_Pos (26U) 3760 #define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */ 3761 #define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk /*!< PCROP read error interrupt enable */ 3762 #define FLASH_CR_OBL_LAUNCH_Pos (27U) 3763 #define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ 3764 #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Force the option bute loading */ 3765 #define FLASH_CR_OPTLOCK_Pos (30U) 3766 #define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */ 3767 #define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk /*!< Options lock */ 3768 #define FLASH_CR_LOCK_Pos (31U) 3769 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ 3770 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Flash control register lock */ 3771 3772 /******************* Bits definition for FLASH_ECCR register ****************/ 3773 #define FLASH_ECCR_ADDR_ECC_Pos (0U) 3774 #define FLASH_ECCR_ADDR_ECC_Msk (0x1FFFFUL << FLASH_ECCR_ADDR_ECC_Pos)/*!< 0x0001FFFF */ 3775 #define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< double-word address ECC fail */ 3776 #define FLASH_ECCR_SYSF_ECC_Pos (20U) 3777 #define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */ 3778 #define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System flash ECC fail */ 3779 #define FLASH_ECCR_ECCCIE_Pos (24U) 3780 #define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos) /*!< 0x01000000 */ 3781 #define FLASH_ECCR_ECCCIE FLASH_ECCR_ECCCIE_Msk /*!< ECC correction interrupt enable */ 3782 #define FLASH_ECCR_CPUID_Pos (26U) 3783 #define FLASH_ECCR_CPUID_Msk (0x7UL << FLASH_ECCR_CPUID_Pos) /*!< 0x1C000000 */ 3784 #define FLASH_ECCR_CPUID FLASH_ECCR_CPUID_Msk /*!< CPU identification */ 3785 #define FLASH_ECCR_ECCC_Pos (30U) 3786 #define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ 3787 #define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ 3788 #define FLASH_ECCR_ECCD_Pos (31U) 3789 #define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ 3790 #define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ 3791 3792 /******************* Bits definition for FLASH_OPTR register ****************/ 3793 #define FLASH_OPTR_RDP_Pos (0U) 3794 #define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ 3795 #define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Read protection level */ 3796 #define FLASH_OPTR_ESE_Pos (8U) 3797 #define FLASH_OPTR_ESE_Msk (0x1UL << FLASH_OPTR_ESE_Pos) /*!< 0x00000100 */ 3798 #define FLASH_OPTR_ESE FLASH_OPTR_ESE_Msk /*!< Security enable */ 3799 #define FLASH_OPTR_BOR_LEV_Pos (9U) 3800 #define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000E00 */ 3801 #define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset level mask */ 3802 #define FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ 3803 #define FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ 3804 #define FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000800 */ 3805 #define FLASH_OPTR_nRST_STOP_Pos (12U) 3806 #define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos)/*!< 0x00001000 */ 3807 #define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< Reset option in Stop mode */ 3808 #define FLASH_OPTR_nRST_STDBY_Pos (13U) 3809 #define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)/*!< 0x00002000 */ 3810 #define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< Reset option in Standby mode */ 3811 #define FLASH_OPTR_nRST_SHDW_Pos (14U) 3812 #define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos)/*!< 0x00004000 */ 3813 #define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< Reset option in Shutdown mode */ 3814 #define FLASH_OPTR_IWDG_SW_Pos (16U) 3815 #define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ 3816 #define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ 3817 #define FLASH_OPTR_IWDG_STOP_Pos (17U) 3818 #define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos)/*!< 0x00020000 */ 3819 #define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter option in Stop mode */ 3820 #define FLASH_OPTR_IWDG_STDBY_Pos (18U) 3821 #define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos)/*!< 0x00040000 */ 3822 #define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter option in Standby mode */ 3823 #define FLASH_OPTR_WWDG_SW_Pos (19U) 3824 #define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ 3825 #define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ 3826 #define FLASH_OPTR_nBOOT1_Pos (23U) 3827 #define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */ 3828 #define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk /*!< Boot Configuration */ 3829 #define FLASH_OPTR_SRAM2_PE_Pos (24U) 3830 #define FLASH_OPTR_SRAM2_PE_Msk (0x1UL << FLASH_OPTR_SRAM2_PE_Pos) /*!< 0x01000000 */ 3831 #define FLASH_OPTR_SRAM2_PE FLASH_OPTR_SRAM2_PE_Msk /*!< SRAM2 parity check enable */ 3832 #define FLASH_OPTR_SRAM_RST_Pos (25U) 3833 #define FLASH_OPTR_SRAM_RST_Msk (0x1UL << FLASH_OPTR_SRAM_RST_Pos) /*!< 0x02000000 */ 3834 #define FLASH_OPTR_SRAM_RST FLASH_OPTR_SRAM_RST_Msk /*!< SRAM1 and SRAM2 erase option when system reset */ 3835 #define FLASH_OPTR_nSWBOOT0_Pos (26U) 3836 #define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ 3837 #define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ 3838 #define FLASH_OPTR_nBOOT0_Pos (27U) 3839 #define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ 3840 #define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< BOOT0 option bit */ 3841 #define FLASH_OPTR_BOOT_LOCK_Pos (30U) 3842 #define FLASH_OPTR_BOOT_LOCK_Msk (0x1UL << FLASH_OPTR_BOOT_LOCK_Pos)/*!< 0x40000000 */ 3843 #define FLASH_OPTR_BOOT_LOCK FLASH_OPTR_BOOT_LOCK_Msk /*!< CPU1 Boot Lock enable option bit */ 3844 3845 /****************** Bits definition for FLASH_PCROP1ASR register ************/ 3846 #define FLASH_PCROP1ASR_PCROP1A_STRT_Pos (0U) 3847 #define FLASH_PCROP1ASR_PCROP1A_STRT_Msk (0xFFUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos)/*!< 0x000000FF */ 3848 #define FLASH_PCROP1ASR_PCROP1A_STRT FLASH_PCROP1ASR_PCROP1A_STRT_Msk /*!< PCROP area A start offset */ 3849 3850 /****************** Bits definition for FLASH_PCROP1AER register ************/ 3851 #define FLASH_PCROP1AER_PCROP1A_END_Pos (0U) 3852 #define FLASH_PCROP1AER_PCROP1A_END_Msk (0xFFUL << FLASH_PCROP1AER_PCROP1A_END_Pos)/*!< 0x000000FF */ 3853 #define FLASH_PCROP1AER_PCROP1A_END FLASH_PCROP1AER_PCROP1A_END_Msk /*!< PCROP area A end offset */ 3854 #define FLASH_PCROP1AER_PCROP_RDP_Pos (31U) 3855 #define FLASH_PCROP1AER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos)/*!< 0x80000000 */ 3856 #define FLASH_PCROP1AER_PCROP_RDP FLASH_PCROP1AER_PCROP_RDP_Msk /*!< PCROP area preserved when RDP level decreased */ 3857 3858 /****************** Bits definition for FLASH_WRP1AR register ***************/ 3859 #define FLASH_WRP1AR_WRP1A_STRT_Pos (0U) 3860 #define FLASH_WRP1AR_WRP1A_STRT_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_STRT_Pos)/*!< 0x0000007F */ 3861 #define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk /*!< WRP area A start offset */ 3862 #define FLASH_WRP1AR_WRP1A_END_Pos (16U) 3863 #define FLASH_WRP1AR_WRP1A_END_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_END_Pos)/*!< 0x007F0000 */ 3864 #define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk /*!< WRP area A end offset */ 3865 3866 /****************** Bits definition for FLASH_WRP1BR register ***************/ 3867 #define FLASH_WRP1BR_WRP1B_STRT_Pos (0U) 3868 #define FLASH_WRP1BR_WRP1B_STRT_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_STRT_Pos)/*!< 0x0000007F */ 3869 #define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk /*!< WRP area B start offset */ 3870 #define FLASH_WRP1BR_WRP1B_END_Pos (16U) 3871 #define FLASH_WRP1BR_WRP1B_END_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_END_Pos)/*!< 0x007F0000 */ 3872 #define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk /*!< WRP area B end offset */ 3873 3874 /****************** Bits definition for FLASH_PCROP1BSR register ************/ 3875 #define FLASH_PCROP1BSR_PCROP1B_STRT_Pos (0U) 3876 #define FLASH_PCROP1BSR_PCROP1B_STRT_Msk (0xFFUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos)/*!< 0x000000FF */ 3877 #define FLASH_PCROP1BSR_PCROP1B_STRT FLASH_PCROP1BSR_PCROP1B_STRT_Msk /*!< PCROP area B start offset */ 3878 3879 /****************** Bits definition for FLASH_PCROP1BER register ************/ 3880 #define FLASH_PCROP1BER_PCROP1B_END_Pos (0U) 3881 #define FLASH_PCROP1BER_PCROP1B_END_Msk (0xFFUL << FLASH_PCROP1BER_PCROP1B_END_Pos)/*!< 0x000000FF */ 3882 #define FLASH_PCROP1BER_PCROP1B_END FLASH_PCROP1BER_PCROP1B_END_Msk /*!< PCROP area B end offset */ 3883 3884 /******************************************************************************/ 3885 /* */ 3886 /* General Purpose I/O */ 3887 /* */ 3888 /******************************************************************************/ 3889 /****************** Bits definition for GPIO_MODER register *****************/ 3890 #define GPIO_MODER_MODE0_Pos (0U) 3891 #define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ 3892 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk 3893 #define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ 3894 #define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ 3895 #define GPIO_MODER_MODE1_Pos (2U) 3896 #define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ 3897 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk 3898 #define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ 3899 #define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ 3900 #define GPIO_MODER_MODE2_Pos (4U) 3901 #define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ 3902 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk 3903 #define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ 3904 #define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ 3905 #define GPIO_MODER_MODE3_Pos (6U) 3906 #define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ 3907 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk 3908 #define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ 3909 #define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ 3910 #define GPIO_MODER_MODE4_Pos (8U) 3911 #define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ 3912 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk 3913 #define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ 3914 #define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ 3915 #define GPIO_MODER_MODE5_Pos (10U) 3916 #define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ 3917 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk 3918 #define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ 3919 #define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ 3920 #define GPIO_MODER_MODE6_Pos (12U) 3921 #define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ 3922 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk 3923 #define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ 3924 #define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ 3925 #define GPIO_MODER_MODE7_Pos (14U) 3926 #define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ 3927 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk 3928 #define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ 3929 #define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ 3930 #define GPIO_MODER_MODE8_Pos (16U) 3931 #define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ 3932 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk 3933 #define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ 3934 #define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ 3935 #define GPIO_MODER_MODE9_Pos (18U) 3936 #define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ 3937 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk 3938 #define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ 3939 #define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ 3940 #define GPIO_MODER_MODE10_Pos (20U) 3941 #define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ 3942 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk 3943 #define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ 3944 #define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ 3945 #define GPIO_MODER_MODE11_Pos (22U) 3946 #define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ 3947 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk 3948 #define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ 3949 #define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ 3950 #define GPIO_MODER_MODE12_Pos (24U) 3951 #define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ 3952 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk 3953 #define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ 3954 #define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ 3955 #define GPIO_MODER_MODE13_Pos (26U) 3956 #define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ 3957 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk 3958 #define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ 3959 #define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ 3960 #define GPIO_MODER_MODE14_Pos (28U) 3961 #define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ 3962 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk 3963 #define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ 3964 #define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ 3965 #define GPIO_MODER_MODE15_Pos (30U) 3966 #define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ 3967 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk 3968 #define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ 3969 #define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ 3970 3971 /****************** Bits definition for GPIO_OTYPER register ****************/ 3972 #define GPIO_OTYPER_OT0_Pos (0U) 3973 #define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ 3974 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk 3975 #define GPIO_OTYPER_OT1_Pos (1U) 3976 #define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ 3977 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk 3978 #define GPIO_OTYPER_OT2_Pos (2U) 3979 #define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ 3980 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk 3981 #define GPIO_OTYPER_OT3_Pos (3U) 3982 #define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ 3983 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk 3984 #define GPIO_OTYPER_OT4_Pos (4U) 3985 #define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ 3986 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk 3987 #define GPIO_OTYPER_OT5_Pos (5U) 3988 #define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ 3989 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk 3990 #define GPIO_OTYPER_OT6_Pos (6U) 3991 #define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ 3992 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk 3993 #define GPIO_OTYPER_OT7_Pos (7U) 3994 #define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ 3995 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk 3996 #define GPIO_OTYPER_OT8_Pos (8U) 3997 #define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ 3998 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk 3999 #define GPIO_OTYPER_OT9_Pos (9U) 4000 #define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ 4001 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk 4002 #define GPIO_OTYPER_OT10_Pos (10U) 4003 #define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ 4004 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk 4005 #define GPIO_OTYPER_OT11_Pos (11U) 4006 #define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ 4007 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk 4008 #define GPIO_OTYPER_OT12_Pos (12U) 4009 #define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ 4010 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk 4011 #define GPIO_OTYPER_OT13_Pos (13U) 4012 #define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ 4013 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk 4014 #define GPIO_OTYPER_OT14_Pos (14U) 4015 #define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ 4016 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk 4017 #define GPIO_OTYPER_OT15_Pos (15U) 4018 #define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ 4019 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk 4020 4021 /****************** Bits definition for GPIO_OSPEEDR register ***************/ 4022 #define GPIO_OSPEEDR_OSPEED0_Pos (0U) 4023 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ 4024 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk 4025 #define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ 4026 #define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ 4027 #define GPIO_OSPEEDR_OSPEED1_Pos (2U) 4028 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ 4029 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk 4030 #define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ 4031 #define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ 4032 #define GPIO_OSPEEDR_OSPEED2_Pos (4U) 4033 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ 4034 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk 4035 #define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ 4036 #define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ 4037 #define GPIO_OSPEEDR_OSPEED3_Pos (6U) 4038 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ 4039 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk 4040 #define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ 4041 #define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ 4042 #define GPIO_OSPEEDR_OSPEED4_Pos (8U) 4043 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ 4044 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk 4045 #define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ 4046 #define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ 4047 #define GPIO_OSPEEDR_OSPEED5_Pos (10U) 4048 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ 4049 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk 4050 #define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ 4051 #define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ 4052 #define GPIO_OSPEEDR_OSPEED6_Pos (12U) 4053 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ 4054 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk 4055 #define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ 4056 #define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ 4057 #define GPIO_OSPEEDR_OSPEED7_Pos (14U) 4058 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ 4059 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk 4060 #define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ 4061 #define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ 4062 #define GPIO_OSPEEDR_OSPEED8_Pos (16U) 4063 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ 4064 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk 4065 #define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ 4066 #define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ 4067 #define GPIO_OSPEEDR_OSPEED9_Pos (18U) 4068 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ 4069 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk 4070 #define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ 4071 #define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ 4072 #define GPIO_OSPEEDR_OSPEED10_Pos (20U) 4073 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ 4074 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk 4075 #define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ 4076 #define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ 4077 #define GPIO_OSPEEDR_OSPEED11_Pos (22U) 4078 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ 4079 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk 4080 #define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ 4081 #define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ 4082 #define GPIO_OSPEEDR_OSPEED12_Pos (24U) 4083 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ 4084 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk 4085 #define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ 4086 #define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ 4087 #define GPIO_OSPEEDR_OSPEED13_Pos (26U) 4088 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ 4089 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk 4090 #define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ 4091 #define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ 4092 #define GPIO_OSPEEDR_OSPEED14_Pos (28U) 4093 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ 4094 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk 4095 #define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ 4096 #define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ 4097 #define GPIO_OSPEEDR_OSPEED15_Pos (30U) 4098 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ 4099 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk 4100 #define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ 4101 #define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ 4102 4103 /****************** Bits definition for GPIO_PUPDR register *****************/ 4104 #define GPIO_PUPDR_PUPD0_Pos (0U) 4105 #define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ 4106 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk 4107 #define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ 4108 #define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ 4109 #define GPIO_PUPDR_PUPD1_Pos (2U) 4110 #define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ 4111 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk 4112 #define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ 4113 #define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ 4114 #define GPIO_PUPDR_PUPD2_Pos (4U) 4115 #define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ 4116 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk 4117 #define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ 4118 #define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ 4119 #define GPIO_PUPDR_PUPD3_Pos (6U) 4120 #define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ 4121 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk 4122 #define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ 4123 #define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ 4124 #define GPIO_PUPDR_PUPD4_Pos (8U) 4125 #define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ 4126 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk 4127 #define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ 4128 #define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ 4129 #define GPIO_PUPDR_PUPD5_Pos (10U) 4130 #define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ 4131 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk 4132 #define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ 4133 #define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ 4134 #define GPIO_PUPDR_PUPD6_Pos (12U) 4135 #define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ 4136 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk 4137 #define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ 4138 #define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ 4139 #define GPIO_PUPDR_PUPD7_Pos (14U) 4140 #define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ 4141 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk 4142 #define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ 4143 #define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ 4144 #define GPIO_PUPDR_PUPD8_Pos (16U) 4145 #define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ 4146 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk 4147 #define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ 4148 #define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ 4149 #define GPIO_PUPDR_PUPD9_Pos (18U) 4150 #define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ 4151 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk 4152 #define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ 4153 #define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ 4154 #define GPIO_PUPDR_PUPD10_Pos (20U) 4155 #define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ 4156 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk 4157 #define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ 4158 #define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ 4159 #define GPIO_PUPDR_PUPD11_Pos (22U) 4160 #define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ 4161 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk 4162 #define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ 4163 #define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ 4164 #define GPIO_PUPDR_PUPD12_Pos (24U) 4165 #define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ 4166 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk 4167 #define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ 4168 #define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ 4169 #define GPIO_PUPDR_PUPD13_Pos (26U) 4170 #define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ 4171 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk 4172 #define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ 4173 #define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ 4174 #define GPIO_PUPDR_PUPD14_Pos (28U) 4175 #define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ 4176 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk 4177 #define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ 4178 #define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ 4179 #define GPIO_PUPDR_PUPD15_Pos (30U) 4180 #define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ 4181 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk 4182 #define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ 4183 #define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ 4184 4185 /****************** Bits definition for GPIO_IDR register *******************/ 4186 #define GPIO_IDR_ID0_Pos (0U) 4187 #define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ 4188 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk 4189 #define GPIO_IDR_ID1_Pos (1U) 4190 #define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ 4191 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk 4192 #define GPIO_IDR_ID2_Pos (2U) 4193 #define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ 4194 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk 4195 #define GPIO_IDR_ID3_Pos (3U) 4196 #define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ 4197 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk 4198 #define GPIO_IDR_ID4_Pos (4U) 4199 #define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ 4200 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk 4201 #define GPIO_IDR_ID5_Pos (5U) 4202 #define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ 4203 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk 4204 #define GPIO_IDR_ID6_Pos (6U) 4205 #define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ 4206 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk 4207 #define GPIO_IDR_ID7_Pos (7U) 4208 #define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ 4209 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk 4210 #define GPIO_IDR_ID8_Pos (8U) 4211 #define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ 4212 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk 4213 #define GPIO_IDR_ID9_Pos (9U) 4214 #define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ 4215 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk 4216 #define GPIO_IDR_ID10_Pos (10U) 4217 #define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ 4218 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk 4219 #define GPIO_IDR_ID11_Pos (11U) 4220 #define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ 4221 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk 4222 #define GPIO_IDR_ID12_Pos (12U) 4223 #define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ 4224 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk 4225 #define GPIO_IDR_ID13_Pos (13U) 4226 #define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ 4227 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk 4228 #define GPIO_IDR_ID14_Pos (14U) 4229 #define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ 4230 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk 4231 #define GPIO_IDR_ID15_Pos (15U) 4232 #define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ 4233 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk 4234 4235 /****************** Bits definition for GPIO_ODR register *******************/ 4236 #define GPIO_ODR_OD0_Pos (0U) 4237 #define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ 4238 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk 4239 #define GPIO_ODR_OD1_Pos (1U) 4240 #define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ 4241 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk 4242 #define GPIO_ODR_OD2_Pos (2U) 4243 #define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ 4244 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk 4245 #define GPIO_ODR_OD3_Pos (3U) 4246 #define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ 4247 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk 4248 #define GPIO_ODR_OD4_Pos (4U) 4249 #define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ 4250 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk 4251 #define GPIO_ODR_OD5_Pos (5U) 4252 #define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ 4253 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk 4254 #define GPIO_ODR_OD6_Pos (6U) 4255 #define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ 4256 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk 4257 #define GPIO_ODR_OD7_Pos (7U) 4258 #define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ 4259 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk 4260 #define GPIO_ODR_OD8_Pos (8U) 4261 #define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ 4262 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk 4263 #define GPIO_ODR_OD9_Pos (9U) 4264 #define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ 4265 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk 4266 #define GPIO_ODR_OD10_Pos (10U) 4267 #define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ 4268 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk 4269 #define GPIO_ODR_OD11_Pos (11U) 4270 #define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ 4271 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk 4272 #define GPIO_ODR_OD12_Pos (12U) 4273 #define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ 4274 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk 4275 #define GPIO_ODR_OD13_Pos (13U) 4276 #define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ 4277 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk 4278 #define GPIO_ODR_OD14_Pos (14U) 4279 #define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ 4280 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk 4281 #define GPIO_ODR_OD15_Pos (15U) 4282 #define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ 4283 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk 4284 4285 /****************** Bits definition for GPIO_BSRR register ******************/ 4286 #define GPIO_BSRR_BS0_Pos (0U) 4287 #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ 4288 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk 4289 #define GPIO_BSRR_BS1_Pos (1U) 4290 #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ 4291 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk 4292 #define GPIO_BSRR_BS2_Pos (2U) 4293 #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ 4294 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk 4295 #define GPIO_BSRR_BS3_Pos (3U) 4296 #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ 4297 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk 4298 #define GPIO_BSRR_BS4_Pos (4U) 4299 #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ 4300 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk 4301 #define GPIO_BSRR_BS5_Pos (5U) 4302 #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ 4303 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk 4304 #define GPIO_BSRR_BS6_Pos (6U) 4305 #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ 4306 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk 4307 #define GPIO_BSRR_BS7_Pos (7U) 4308 #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ 4309 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk 4310 #define GPIO_BSRR_BS8_Pos (8U) 4311 #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ 4312 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk 4313 #define GPIO_BSRR_BS9_Pos (9U) 4314 #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ 4315 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk 4316 #define GPIO_BSRR_BS10_Pos (10U) 4317 #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ 4318 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk 4319 #define GPIO_BSRR_BS11_Pos (11U) 4320 #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ 4321 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk 4322 #define GPIO_BSRR_BS12_Pos (12U) 4323 #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ 4324 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk 4325 #define GPIO_BSRR_BS13_Pos (13U) 4326 #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ 4327 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk 4328 #define GPIO_BSRR_BS14_Pos (14U) 4329 #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ 4330 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk 4331 #define GPIO_BSRR_BS15_Pos (15U) 4332 #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ 4333 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk 4334 #define GPIO_BSRR_BR0_Pos (16U) 4335 #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ 4336 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk 4337 #define GPIO_BSRR_BR1_Pos (17U) 4338 #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ 4339 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk 4340 #define GPIO_BSRR_BR2_Pos (18U) 4341 #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ 4342 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk 4343 #define GPIO_BSRR_BR3_Pos (19U) 4344 #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ 4345 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk 4346 #define GPIO_BSRR_BR4_Pos (20U) 4347 #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ 4348 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk 4349 #define GPIO_BSRR_BR5_Pos (21U) 4350 #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ 4351 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk 4352 #define GPIO_BSRR_BR6_Pos (22U) 4353 #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ 4354 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk 4355 #define GPIO_BSRR_BR7_Pos (23U) 4356 #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ 4357 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk 4358 #define GPIO_BSRR_BR8_Pos (24U) 4359 #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ 4360 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk 4361 #define GPIO_BSRR_BR9_Pos (25U) 4362 #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ 4363 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk 4364 #define GPIO_BSRR_BR10_Pos (26U) 4365 #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ 4366 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk 4367 #define GPIO_BSRR_BR11_Pos (27U) 4368 #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ 4369 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk 4370 #define GPIO_BSRR_BR12_Pos (28U) 4371 #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ 4372 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk 4373 #define GPIO_BSRR_BR13_Pos (29U) 4374 #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ 4375 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk 4376 #define GPIO_BSRR_BR14_Pos (30U) 4377 #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ 4378 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk 4379 #define GPIO_BSRR_BR15_Pos (31U) 4380 #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ 4381 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk 4382 4383 /****************** Bit definition for GPIO_LCKR register *********************/ 4384 #define GPIO_LCKR_LCK0_Pos (0U) 4385 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ 4386 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk 4387 #define GPIO_LCKR_LCK1_Pos (1U) 4388 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ 4389 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk 4390 #define GPIO_LCKR_LCK2_Pos (2U) 4391 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ 4392 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk 4393 #define GPIO_LCKR_LCK3_Pos (3U) 4394 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ 4395 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk 4396 #define GPIO_LCKR_LCK4_Pos (4U) 4397 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ 4398 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk 4399 #define GPIO_LCKR_LCK5_Pos (5U) 4400 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ 4401 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk 4402 #define GPIO_LCKR_LCK6_Pos (6U) 4403 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ 4404 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk 4405 #define GPIO_LCKR_LCK7_Pos (7U) 4406 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ 4407 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk 4408 #define GPIO_LCKR_LCK8_Pos (8U) 4409 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ 4410 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk 4411 #define GPIO_LCKR_LCK9_Pos (9U) 4412 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ 4413 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk 4414 #define GPIO_LCKR_LCK10_Pos (10U) 4415 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ 4416 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk 4417 #define GPIO_LCKR_LCK11_Pos (11U) 4418 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ 4419 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk 4420 #define GPIO_LCKR_LCK12_Pos (12U) 4421 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ 4422 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk 4423 #define GPIO_LCKR_LCK13_Pos (13U) 4424 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ 4425 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk 4426 #define GPIO_LCKR_LCK14_Pos (14U) 4427 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ 4428 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk 4429 #define GPIO_LCKR_LCK15_Pos (15U) 4430 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ 4431 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk 4432 #define GPIO_LCKR_LCKK_Pos (16U) 4433 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ 4434 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk 4435 4436 /****************** Bit definition for GPIO_AFRL register *********************/ 4437 #define GPIO_AFRL_AFSEL0_Pos (0U) 4438 #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ 4439 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk 4440 #define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ 4441 #define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ 4442 #define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ 4443 #define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ 4444 #define GPIO_AFRL_AFSEL1_Pos (4U) 4445 #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ 4446 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk 4447 #define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ 4448 #define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ 4449 #define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ 4450 #define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ 4451 #define GPIO_AFRL_AFSEL2_Pos (8U) 4452 #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ 4453 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk 4454 #define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ 4455 #define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ 4456 #define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ 4457 #define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ 4458 #define GPIO_AFRL_AFSEL3_Pos (12U) 4459 #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ 4460 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk 4461 #define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ 4462 #define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ 4463 #define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ 4464 #define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ 4465 #define GPIO_AFRL_AFSEL4_Pos (16U) 4466 #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ 4467 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk 4468 #define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ 4469 #define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ 4470 #define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ 4471 #define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ 4472 #define GPIO_AFRL_AFSEL5_Pos (20U) 4473 #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ 4474 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk 4475 #define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ 4476 #define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ 4477 #define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ 4478 #define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ 4479 #define GPIO_AFRL_AFSEL6_Pos (24U) 4480 #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ 4481 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk 4482 #define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ 4483 #define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ 4484 #define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ 4485 #define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ 4486 #define GPIO_AFRL_AFSEL7_Pos (28U) 4487 #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ 4488 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk 4489 #define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ 4490 #define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ 4491 #define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ 4492 #define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ 4493 4494 /****************** Bit definition for GPIO_AFRH register *********************/ 4495 #define GPIO_AFRH_AFSEL8_Pos (0U) 4496 #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ 4497 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk 4498 #define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ 4499 #define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ 4500 #define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ 4501 #define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ 4502 #define GPIO_AFRH_AFSEL9_Pos (4U) 4503 #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ 4504 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk 4505 #define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ 4506 #define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ 4507 #define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ 4508 #define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ 4509 #define GPIO_AFRH_AFSEL10_Pos (8U) 4510 #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ 4511 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk 4512 #define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ 4513 #define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ 4514 #define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ 4515 #define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ 4516 #define GPIO_AFRH_AFSEL11_Pos (12U) 4517 #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ 4518 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk 4519 #define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ 4520 #define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ 4521 #define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ 4522 #define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ 4523 #define GPIO_AFRH_AFSEL12_Pos (16U) 4524 #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ 4525 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk 4526 #define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ 4527 #define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ 4528 #define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ 4529 #define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ 4530 #define GPIO_AFRH_AFSEL13_Pos (20U) 4531 #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ 4532 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk 4533 #define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ 4534 #define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ 4535 #define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ 4536 #define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ 4537 #define GPIO_AFRH_AFSEL14_Pos (24U) 4538 #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ 4539 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk 4540 #define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ 4541 #define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ 4542 #define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ 4543 #define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ 4544 #define GPIO_AFRH_AFSEL15_Pos (28U) 4545 #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ 4546 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk 4547 #define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ 4548 #define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ 4549 #define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ 4550 #define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ 4551 4552 /****************** Bits definition for GPIO_BRR register ******************/ 4553 #define GPIO_BRR_BR0_Pos (0U) 4554 #define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ 4555 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk 4556 #define GPIO_BRR_BR1_Pos (1U) 4557 #define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ 4558 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk 4559 #define GPIO_BRR_BR2_Pos (2U) 4560 #define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ 4561 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk 4562 #define GPIO_BRR_BR3_Pos (3U) 4563 #define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ 4564 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk 4565 #define GPIO_BRR_BR4_Pos (4U) 4566 #define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ 4567 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk 4568 #define GPIO_BRR_BR5_Pos (5U) 4569 #define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ 4570 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk 4571 #define GPIO_BRR_BR6_Pos (6U) 4572 #define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ 4573 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk 4574 #define GPIO_BRR_BR7_Pos (7U) 4575 #define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ 4576 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk 4577 #define GPIO_BRR_BR8_Pos (8U) 4578 #define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ 4579 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk 4580 #define GPIO_BRR_BR9_Pos (9U) 4581 #define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ 4582 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk 4583 #define GPIO_BRR_BR10_Pos (10U) 4584 #define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ 4585 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk 4586 #define GPIO_BRR_BR11_Pos (11U) 4587 #define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ 4588 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk 4589 #define GPIO_BRR_BR12_Pos (12U) 4590 #define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ 4591 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk 4592 #define GPIO_BRR_BR13_Pos (13U) 4593 #define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ 4594 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk 4595 #define GPIO_BRR_BR14_Pos (14U) 4596 #define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ 4597 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk 4598 #define GPIO_BRR_BR15_Pos (15U) 4599 #define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ 4600 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk 4601 4602 /******************************************************************************/ 4603 /* */ 4604 /* HSEM HW Semaphore */ 4605 /* */ 4606 /******************************************************************************/ 4607 /******************** Bit definition for HSEM_R register ********************/ 4608 #define HSEM_R_PROCID_Pos (0U) 4609 #define HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos) /*!< 0x000000FF */ 4610 #define HSEM_R_PROCID HSEM_R_PROCID_Msk /*!<Semaphore ProcessID */ 4611 #define HSEM_R_COREID_Pos (8U) 4612 #define HSEM_R_COREID_Msk (0xFUL << HSEM_R_COREID_Pos) /*!< 0x00000F00 */ 4613 #define HSEM_R_COREID HSEM_R_COREID_Msk /*!<Semaphore CoreID. */ 4614 #define HSEM_R_LOCK_Pos (31U) 4615 #define HSEM_R_LOCK_Msk (0x1UL << HSEM_R_LOCK_Pos) /*!< 0x80000000 */ 4616 #define HSEM_R_LOCK HSEM_R_LOCK_Msk /*!<Lock indication. */ 4617 4618 /******************** Bit definition for HSEM_RLR register ******************/ 4619 #define HSEM_RLR_PROCID_Pos (0U) 4620 #define HSEM_RLR_PROCID_Msk (0xFFUL << HSEM_RLR_PROCID_Pos) /*!< 0x000000FF */ 4621 #define HSEM_RLR_PROCID HSEM_RLR_PROCID_Msk /*!<Semaphore ProcessID */ 4622 #define HSEM_RLR_COREID_Pos (8U) 4623 #define HSEM_RLR_COREID_Msk (0xFUL << HSEM_RLR_COREID_Pos) /*!< 0x00000F00 */ 4624 #define HSEM_RLR_COREID HSEM_RLR_COREID_Msk /*!<Semaphore CoreID. */ 4625 #define HSEM_RLR_LOCK_Pos (31U) 4626 #define HSEM_RLR_LOCK_Msk (0x1UL << HSEM_RLR_LOCK_Pos) /*!< 0x80000000 */ 4627 #define HSEM_RLR_LOCK HSEM_RLR_LOCK_Msk /*!<Lock indication. */ 4628 4629 /******************** Bit definition for HSEM_C1IER register ****************/ 4630 #define HSEM_C1IER_ISE0_Pos (0U) 4631 #define HSEM_C1IER_ISE0_Msk (0x1UL << HSEM_C1IER_ISE0_Pos) /*!< 0x00000001 */ 4632 #define HSEM_C1IER_ISE0 HSEM_C1IER_ISE0_Msk /*!<semaphore 0 CPU1 interrupt enable bit. */ 4633 #define HSEM_C1IER_ISE1_Pos (1U) 4634 #define HSEM_C1IER_ISE1_Msk (0x1UL << HSEM_C1IER_ISE1_Pos) /*!< 0x00000002 */ 4635 #define HSEM_C1IER_ISE1 HSEM_C1IER_ISE1_Msk /*!<semaphore 1 CPU1 interrupt enable bit. */ 4636 #define HSEM_C1IER_ISE2_Pos (2U) 4637 #define HSEM_C1IER_ISE2_Msk (0x1UL << HSEM_C1IER_ISE2_Pos) /*!< 0x00000004 */ 4638 #define HSEM_C1IER_ISE2 HSEM_C1IER_ISE2_Msk /*!<semaphore 2 CPU1 interrupt enable bit. */ 4639 #define HSEM_C1IER_ISE3_Pos (3U) 4640 #define HSEM_C1IER_ISE3_Msk (0x1UL << HSEM_C1IER_ISE3_Pos) /*!< 0x00000008 */ 4641 #define HSEM_C1IER_ISE3 HSEM_C1IER_ISE3_Msk /*!<semaphore 3 CPU1 interrupt enable bit. */ 4642 #define HSEM_C1IER_ISE4_Pos (4U) 4643 #define HSEM_C1IER_ISE4_Msk (0x1UL << HSEM_C1IER_ISE4_Pos) /*!< 0x00000010 */ 4644 #define HSEM_C1IER_ISE4 HSEM_C1IER_ISE4_Msk /*!<semaphore 4 CPU1 interrupt enable bit. */ 4645 #define HSEM_C1IER_ISE5_Pos (5U) 4646 #define HSEM_C1IER_ISE5_Msk (0x1UL << HSEM_C1IER_ISE5_Pos) /*!< 0x00000020 */ 4647 #define HSEM_C1IER_ISE5 HSEM_C1IER_ISE5_Msk /*!<semaphore 5 CPU1 interrupt enable bit. */ 4648 #define HSEM_C1IER_ISE6_Pos (6U) 4649 #define HSEM_C1IER_ISE6_Msk (0x1UL << HSEM_C1IER_ISE6_Pos) /*!< 0x00000040 */ 4650 #define HSEM_C1IER_ISE6 HSEM_C1IER_ISE6_Msk /*!<semaphore 6 CPU1 interrupt enable bit. */ 4651 #define HSEM_C1IER_ISE7_Pos (7U) 4652 #define HSEM_C1IER_ISE7_Msk (0x1UL << HSEM_C1IER_ISE7_Pos) /*!< 0x00000080 */ 4653 #define HSEM_C1IER_ISE7 HSEM_C1IER_ISE7_Msk /*!<semaphore 7 CPU1 interrupt enable bit. */ 4654 #define HSEM_C1IER_ISE8_Pos (8U) 4655 #define HSEM_C1IER_ISE8_Msk (0x1UL << HSEM_C1IER_ISE8_Pos) /*!< 0x00000100 */ 4656 #define HSEM_C1IER_ISE8 HSEM_C1IER_ISE8_Msk /*!<semaphore 8 CPU1 interrupt enable bit. */ 4657 #define HSEM_C1IER_ISE9_Pos (9U) 4658 #define HSEM_C1IER_ISE9_Msk (0x1UL << HSEM_C1IER_ISE9_Pos) /*!< 0x00000200 */ 4659 #define HSEM_C1IER_ISE9 HSEM_C1IER_ISE9_Msk /*!<semaphore 9 CPU1 interrupt enable bit. */ 4660 #define HSEM_C1IER_ISE10_Pos (10U) 4661 #define HSEM_C1IER_ISE10_Msk (0x1UL << HSEM_C1IER_ISE10_Pos) /*!< 0x00000400 */ 4662 #define HSEM_C1IER_ISE10 HSEM_C1IER_ISE10_Msk /*!<semaphore 10 CPU1 interrupt enable bit. */ 4663 #define HSEM_C1IER_ISE11_Pos (11U) 4664 #define HSEM_C1IER_ISE11_Msk (0x1UL << HSEM_C1IER_ISE11_Pos) /*!< 0x00000800 */ 4665 #define HSEM_C1IER_ISE11 HSEM_C1IER_ISE11_Msk /*!<semaphore 11 CPU1 interrupt enable bit. */ 4666 #define HSEM_C1IER_ISE12_Pos (12U) 4667 #define HSEM_C1IER_ISE12_Msk (0x1UL << HSEM_C1IER_ISE12_Pos) /*!< 0x00001000 */ 4668 #define HSEM_C1IER_ISE12 HSEM_C1IER_ISE12_Msk /*!<semaphore 12 CPU1 interrupt enable bit. */ 4669 #define HSEM_C1IER_ISE13_Pos (13U) 4670 #define HSEM_C1IER_ISE13_Msk (0x1UL << HSEM_C1IER_ISE13_Pos) /*!< 0x00002000 */ 4671 #define HSEM_C1IER_ISE13 HSEM_C1IER_ISE13_Msk /*!<semaphore 13 CPU1 interrupt enable bit. */ 4672 #define HSEM_C1IER_ISE14_Pos (14U) 4673 #define HSEM_C1IER_ISE14_Msk (0x1UL << HSEM_C1IER_ISE14_Pos) /*!< 0x00004000 */ 4674 #define HSEM_C1IER_ISE14 HSEM_C1IER_ISE14_Msk /*!<semaphore 14 CPU1 interrupt enable bit. */ 4675 #define HSEM_C1IER_ISE15_Pos (15U) 4676 #define HSEM_C1IER_ISE15_Msk (0x1UL << HSEM_C1IER_ISE15_Pos) /*!< 0x00008000 */ 4677 #define HSEM_C1IER_ISE15 HSEM_C1IER_ISE15_Msk /*!<semaphore 15 CPU1 interrupt enable bit. */ 4678 4679 /******************** Bit definition for HSEM_C1ICR register *****************/ 4680 #define HSEM_C1ICR_ISC0_Pos (0U) 4681 #define HSEM_C1ICR_ISC0_Msk (0x1UL << HSEM_C1ICR_ISC0_Pos) /*!< 0x00000001 */ 4682 #define HSEM_C1ICR_ISC0 HSEM_C1ICR_ISC0_Msk /*!<semaphore 0 CPU1 interrupt clear bit. */ 4683 #define HSEM_C1ICR_ISC1_Pos (1U) 4684 #define HSEM_C1ICR_ISC1_Msk (0x1UL << HSEM_C1ICR_ISC1_Pos) /*!< 0x00000002 */ 4685 #define HSEM_C1ICR_ISC1 HSEM_C1ICR_ISC1_Msk /*!<semaphore 1 CPU1 interrupt clear bit. */ 4686 #define HSEM_C1ICR_ISC2_Pos (2U) 4687 #define HSEM_C1ICR_ISC2_Msk (0x1UL << HSEM_C1ICR_ISC2_Pos) /*!< 0x00000004 */ 4688 #define HSEM_C1ICR_ISC2 HSEM_C1ICR_ISC2_Msk /*!<semaphore 2 CPU1 interrupt clear bit. */ 4689 #define HSEM_C1ICR_ISC3_Pos (3U) 4690 #define HSEM_C1ICR_ISC3_Msk (0x1UL << HSEM_C1ICR_ISC3_Pos) /*!< 0x00000008 */ 4691 #define HSEM_C1ICR_ISC3 HSEM_C1ICR_ISC3_Msk /*!<semaphore 3 CPU1 interrupt clear bit. */ 4692 #define HSEM_C1ICR_ISC4_Pos (4U) 4693 #define HSEM_C1ICR_ISC4_Msk (0x1UL << HSEM_C1ICR_ISC4_Pos) /*!< 0x00000010 */ 4694 #define HSEM_C1ICR_ISC4 HSEM_C1ICR_ISC4_Msk /*!<semaphore 4 CPU1 interrupt clear bit. */ 4695 #define HSEM_C1ICR_ISC5_Pos (5U) 4696 #define HSEM_C1ICR_ISC5_Msk (0x1UL << HSEM_C1ICR_ISC5_Pos) /*!< 0x00000020 */ 4697 #define HSEM_C1ICR_ISC5 HSEM_C1ICR_ISC5_Msk /*!<semaphore 5 CPU1 interrupt clear bit. */ 4698 #define HSEM_C1ICR_ISC6_Pos (6U) 4699 #define HSEM_C1ICR_ISC6_Msk (0x1UL << HSEM_C1ICR_ISC6_Pos) /*!< 0x00000040 */ 4700 #define HSEM_C1ICR_ISC6 HSEM_C1ICR_ISC6_Msk /*!<semaphore 6 CPU1 interrupt clear bit. */ 4701 #define HSEM_C1ICR_ISC7_Pos (7U) 4702 #define HSEM_C1ICR_ISC7_Msk (0x1UL << HSEM_C1ICR_ISC7_Pos) /*!< 0x00000080 */ 4703 #define HSEM_C1ICR_ISC7 HSEM_C1ICR_ISC7_Msk /*!<semaphore 7 CPU1 interrupt clear bit. */ 4704 #define HSEM_C1ICR_ISC8_Pos (8U) 4705 #define HSEM_C1ICR_ISC8_Msk (0x1UL << HSEM_C1ICR_ISC8_Pos) /*!< 0x00000100 */ 4706 #define HSEM_C1ICR_ISC8 HSEM_C1ICR_ISC8_Msk /*!<semaphore 8 CPU1 interrupt clear bit. */ 4707 #define HSEM_C1ICR_ISC9_Pos (9U) 4708 #define HSEM_C1ICR_ISC9_Msk (0x1UL << HSEM_C1ICR_ISC9_Pos) /*!< 0x00000200 */ 4709 #define HSEM_C1ICR_ISC9 HSEM_C1ICR_ISC9_Msk /*!<semaphore 9 CPU1 interrupt clear bit. */ 4710 #define HSEM_C1ICR_ISC10_Pos (10U) 4711 #define HSEM_C1ICR_ISC10_Msk (0x1UL << HSEM_C1ICR_ISC10_Pos) /*!< 0x00000400 */ 4712 #define HSEM_C1ICR_ISC10 HSEM_C1ICR_ISC10_Msk /*!<semaphore 10 CPU1 interrupt clear bit. */ 4713 #define HSEM_C1ICR_ISC11_Pos (11U) 4714 #define HSEM_C1ICR_ISC11_Msk (0x1UL << HSEM_C1ICR_ISC11_Pos) /*!< 0x00000800 */ 4715 #define HSEM_C1ICR_ISC11 HSEM_C1ICR_ISC11_Msk /*!<semaphore 11 CPU1 interrupt clear bit. */ 4716 #define HSEM_C1ICR_ISC12_Pos (12U) 4717 #define HSEM_C1ICR_ISC12_Msk (0x1UL << HSEM_C1ICR_ISC12_Pos) /*!< 0x00001000 */ 4718 #define HSEM_C1ICR_ISC12 HSEM_C1ICR_ISC12_Msk /*!<semaphore 12 CPU1 interrupt clear bit. */ 4719 #define HSEM_C1ICR_ISC13_Pos (13U) 4720 #define HSEM_C1ICR_ISC13_Msk (0x1UL << HSEM_C1ICR_ISC13_Pos) /*!< 0x00002000 */ 4721 #define HSEM_C1ICR_ISC13 HSEM_C1ICR_ISC13_Msk /*!<semaphore 13 CPU1 interrupt clear bit. */ 4722 #define HSEM_C1ICR_ISC14_Pos (14U) 4723 #define HSEM_C1ICR_ISC14_Msk (0x1UL << HSEM_C1ICR_ISC14_Pos) /*!< 0x00004000 */ 4724 #define HSEM_C1ICR_ISC14 HSEM_C1ICR_ISC14_Msk /*!<semaphore 14 CPU1 interrupt clear bit. */ 4725 #define HSEM_C1ICR_ISC15_Pos (15U) 4726 #define HSEM_C1ICR_ISC15_Msk (0x1UL << HSEM_C1ICR_ISC15_Pos) /*!< 0x00008000 */ 4727 #define HSEM_C1ICR_ISC15 HSEM_C1ICR_ISC15_Msk /*!<semaphore 15 CPU1 interrupt clear bit. */ 4728 4729 /******************** Bit definition for HSEM_C1ISR register *****************/ 4730 #define HSEM_C1ISR_ISF0_Pos (0U) 4731 #define HSEM_C1ISR_ISF0_Msk (0x1UL << HSEM_C1ISR_ISF0_Pos) /*!< 0x00000001 */ 4732 #define HSEM_C1ISR_ISF0 HSEM_C1ISR_ISF0_Msk /*!<semaphore 0 CPU1 interrupt status bit. */ 4733 #define HSEM_C1ISR_ISF1_Pos (1U) 4734 #define HSEM_C1ISR_ISF1_Msk (0x1UL << HSEM_C1ISR_ISF1_Pos) /*!< 0x00000002 */ 4735 #define HSEM_C1ISR_ISF1 HSEM_C1ISR_ISF1_Msk /*!<semaphore 1 CPU1 interrupt status bit. */ 4736 #define HSEM_C1ISR_ISF2_Pos (2U) 4737 #define HSEM_C1ISR_ISF2_Msk (0x1UL << HSEM_C1ISR_ISF2_Pos) /*!< 0x00000004 */ 4738 #define HSEM_C1ISR_ISF2 HSEM_C1ISR_ISF2_Msk /*!<semaphore 2 CPU1 interrupt status bit. */ 4739 #define HSEM_C1ISR_ISF3_Pos (3U) 4740 #define HSEM_C1ISR_ISF3_Msk (0x1UL << HSEM_C1ISR_ISF3_Pos) /*!< 0x00000008 */ 4741 #define HSEM_C1ISR_ISF3 HSEM_C1ISR_ISF3_Msk /*!<semaphore 3 CPU1 interrupt status bit. */ 4742 #define HSEM_C1ISR_ISF4_Pos (4U) 4743 #define HSEM_C1ISR_ISF4_Msk (0x1UL << HSEM_C1ISR_ISF4_Pos) /*!< 0x00000010 */ 4744 #define HSEM_C1ISR_ISF4 HSEM_C1ISR_ISF4_Msk /*!<semaphore 4 CPU1 interrupt status bit. */ 4745 #define HSEM_C1ISR_ISF5_Pos (5U) 4746 #define HSEM_C1ISR_ISF5_Msk (0x1UL << HSEM_C1ISR_ISF5_Pos) /*!< 0x00000020 */ 4747 #define HSEM_C1ISR_ISF5 HSEM_C1ISR_ISF5_Msk /*!<semaphore 5 CPU1 interrupt status bit. */ 4748 #define HSEM_C1ISR_ISF6_Pos (6U) 4749 #define HSEM_C1ISR_ISF6_Msk (0x1UL << HSEM_C1ISR_ISF6_Pos) /*!< 0x00000040 */ 4750 #define HSEM_C1ISR_ISF6 HSEM_C1ISR_ISF6_Msk /*!<semaphore 6 CPU1 interrupt status bit. */ 4751 #define HSEM_C1ISR_ISF7_Pos (7U) 4752 #define HSEM_C1ISR_ISF7_Msk (0x1UL << HSEM_C1ISR_ISF7_Pos) /*!< 0x00000080 */ 4753 #define HSEM_C1ISR_ISF7 HSEM_C1ISR_ISF7_Msk /*!<semaphore 7 CPU1 interrupt status bit. */ 4754 #define HSEM_C1ISR_ISF8_Pos (8U) 4755 #define HSEM_C1ISR_ISF8_Msk (0x1UL << HSEM_C1ISR_ISF8_Pos) /*!< 0x00000100 */ 4756 #define HSEM_C1ISR_ISF8 HSEM_C1ISR_ISF8_Msk /*!<semaphore 8 CPU1 interrupt status bit. */ 4757 #define HSEM_C1ISR_ISF9_Pos (9U) 4758 #define HSEM_C1ISR_ISF9_Msk (0x1UL << HSEM_C1ISR_ISF9_Pos) /*!< 0x00000200 */ 4759 #define HSEM_C1ISR_ISF9 HSEM_C1ISR_ISF9_Msk /*!<semaphore 9 CPU1 interrupt status bit. */ 4760 #define HSEM_C1ISR_ISF10_Pos (10U) 4761 #define HSEM_C1ISR_ISF10_Msk (0x1UL << HSEM_C1ISR_ISF10_Pos) /*!< 0x00000400 */ 4762 #define HSEM_C1ISR_ISF10 HSEM_C1ISR_ISF10_Msk /*!<semaphore 10 CPU1 interrupt status bit. */ 4763 #define HSEM_C1ISR_ISF11_Pos (11U) 4764 #define HSEM_C1ISR_ISF11_Msk (0x1UL << HSEM_C1ISR_ISF11_Pos) /*!< 0x00000800 */ 4765 #define HSEM_C1ISR_ISF11 HSEM_C1ISR_ISF11_Msk /*!<semaphore 11 CPU1 interrupt status bit. */ 4766 #define HSEM_C1ISR_ISF12_Pos (12U) 4767 #define HSEM_C1ISR_ISF12_Msk (0x1UL << HSEM_C1ISR_ISF12_Pos) /*!< 0x00001000 */ 4768 #define HSEM_C1ISR_ISF12 HSEM_C1ISR_ISF12_Msk /*!<semaphore 12 CPU1 interrupt status bit. */ 4769 #define HSEM_C1ISR_ISF13_Pos (13U) 4770 #define HSEM_C1ISR_ISF13_Msk (0x1UL << HSEM_C1ISR_ISF13_Pos) /*!< 0x00002000 */ 4771 #define HSEM_C1ISR_ISF13 HSEM_C1ISR_ISF13_Msk /*!<semaphore 13 CPU1 interrupt status bit. */ 4772 #define HSEM_C1ISR_ISF14_Pos (14U) 4773 #define HSEM_C1ISR_ISF14_Msk (0x1UL << HSEM_C1ISR_ISF14_Pos) /*!< 0x00004000 */ 4774 #define HSEM_C1ISR_ISF14 HSEM_C1ISR_ISF14_Msk /*!<semaphore 14 CPU1 interrupt status bit. */ 4775 #define HSEM_C1ISR_ISF15_Pos (15U) 4776 #define HSEM_C1ISR_ISF15_Msk (0x1UL << HSEM_C1ISR_ISF15_Pos) /*!< 0x00008000 */ 4777 #define HSEM_C1ISR_ISF15 HSEM_C1ISR_ISF15_Msk /*!<semaphore 15 CPU1 interrupt status bit. */ 4778 4779 /******************** Bit definition for HSEM_C1MISR register *****************/ 4780 #define HSEM_C1MISR_MISF0_Pos (0U) 4781 #define HSEM_C1MISR_MISF0_Msk (0x1UL << HSEM_C1MISR_MISF0_Pos) /*!< 0x00000001 */ 4782 #define HSEM_C1MISR_MISF0 HSEM_C1MISR_MISF0_Msk /*!<semaphore 0 CPU1 interrupt masked status bit. */ 4783 #define HSEM_C1MISR_MISF1_Pos (1U) 4784 #define HSEM_C1MISR_MISF1_Msk (0x1UL << HSEM_C1MISR_MISF1_Pos) /*!< 0x00000002 */ 4785 #define HSEM_C1MISR_MISF1 HSEM_C1MISR_MISF1_Msk /*!<semaphore 1 CPU1 interrupt masked status bit. */ 4786 #define HSEM_C1MISR_MISF2_Pos (2U) 4787 #define HSEM_C1MISR_MISF2_Msk (0x1UL << HSEM_C1MISR_MISF2_Pos) /*!< 0x00000004 */ 4788 #define HSEM_C1MISR_MISF2 HSEM_C1MISR_MISF2_Msk /*!<semaphore 2 CPU1 interrupt masked status bit. */ 4789 #define HSEM_C1MISR_MISF3_Pos (3U) 4790 #define HSEM_C1MISR_MISF3_Msk (0x1UL << HSEM_C1MISR_MISF3_Pos) /*!< 0x00000008 */ 4791 #define HSEM_C1MISR_MISF3 HSEM_C1MISR_MISF3_Msk /*!<semaphore 3 CPU1 interrupt masked status bit. */ 4792 #define HSEM_C1MISR_MISF4_Pos (4U) 4793 #define HSEM_C1MISR_MISF4_Msk (0x1UL << HSEM_C1MISR_MISF4_Pos) /*!< 0x00000010 */ 4794 #define HSEM_C1MISR_MISF4 HSEM_C1MISR_MISF4_Msk /*!<semaphore 4 CPU1 interrupt masked status bit. */ 4795 #define HSEM_C1MISR_MISF5_Pos (5U) 4796 #define HSEM_C1MISR_MISF5_Msk (0x1UL << HSEM_C1MISR_MISF5_Pos) /*!< 0x00000020 */ 4797 #define HSEM_C1MISR_MISF5 HSEM_C1MISR_MISF5_Msk /*!<semaphore 5 CPU1 interrupt masked status bit. */ 4798 #define HSEM_C1MISR_MISF6_Pos (6U) 4799 #define HSEM_C1MISR_MISF6_Msk (0x1UL << HSEM_C1MISR_MISF6_Pos) /*!< 0x00000040 */ 4800 #define HSEM_C1MISR_MISF6 HSEM_C1MISR_MISF6_Msk /*!<semaphore 6 CPU1 interrupt masked status bit. */ 4801 #define HSEM_C1MISR_MISF7_Pos (7U) 4802 #define HSEM_C1MISR_MISF7_Msk (0x1UL << HSEM_C1MISR_MISF7_Pos) /*!< 0x00000080 */ 4803 #define HSEM_C1MISR_MISF7 HSEM_C1MISR_MISF7_Msk /*!<semaphore 7 CPU1 interrupt masked status bit. */ 4804 #define HSEM_C1MISR_MISF8_Pos (8U) 4805 #define HSEM_C1MISR_MISF8_Msk (0x1UL << HSEM_C1MISR_MISF8_Pos) /*!< 0x00000100 */ 4806 #define HSEM_C1MISR_MISF8 HSEM_C1MISR_MISF8_Msk /*!<semaphore 8 CPU1 interrupt masked status bit. */ 4807 #define HSEM_C1MISR_MISF9_Pos (9U) 4808 #define HSEM_C1MISR_MISF9_Msk (0x1UL << HSEM_C1MISR_MISF9_Pos) /*!< 0x00000200 */ 4809 #define HSEM_C1MISR_MISF9 HSEM_C1MISR_MISF9_Msk /*!<semaphore 9 CPU1 interrupt masked status bit. */ 4810 #define HSEM_C1MISR_MISF10_Pos (10U) 4811 #define HSEM_C1MISR_MISF10_Msk (0x1UL << HSEM_C1MISR_MISF10_Pos) /*!< 0x00000400 */ 4812 #define HSEM_C1MISR_MISF10 HSEM_C1MISR_MISF10_Msk /*!<semaphore 10 CPU1 interrupt masked status bit. */ 4813 #define HSEM_C1MISR_MISF11_Pos (11U) 4814 #define HSEM_C1MISR_MISF11_Msk (0x1UL << HSEM_C1MISR_MISF11_Pos) /*!< 0x00000800 */ 4815 #define HSEM_C1MISR_MISF11 HSEM_C1MISR_MISF11_Msk /*!<semaphore 11 CPU1 interrupt masked status bit. */ 4816 #define HSEM_C1MISR_MISF12_Pos (12U) 4817 #define HSEM_C1MISR_MISF12_Msk (0x1UL << HSEM_C1MISR_MISF12_Pos) /*!< 0x00001000 */ 4818 #define HSEM_C1MISR_MISF12 HSEM_C1MISR_MISF12_Msk /*!<semaphore 12 CPU1 interrupt masked status bit. */ 4819 #define HSEM_C1MISR_MISF13_Pos (13U) 4820 #define HSEM_C1MISR_MISF13_Msk (0x1UL << HSEM_C1MISR_MISF13_Pos) /*!< 0x00002000 */ 4821 #define HSEM_C1MISR_MISF13 HSEM_C1MISR_MISF13_Msk /*!<semaphore 13 CPU1 interrupt masked status bit. */ 4822 #define HSEM_C1MISR_MISF14_Pos (14U) 4823 #define HSEM_C1MISR_MISF14_Msk (0x1UL << HSEM_C1MISR_MISF14_Pos) /*!< 0x00004000 */ 4824 #define HSEM_C1MISR_MISF14 HSEM_C1MISR_MISF14_Msk /*!<semaphore 14 CPU1 interrupt masked status bit. */ 4825 #define HSEM_C1MISR_MISF15_Pos (15U) 4826 #define HSEM_C1MISR_MISF15_Msk (0x1UL << HSEM_C1MISR_MISF15_Pos) /*!< 0x00008000 */ 4827 #define HSEM_C1MISR_MISF15 HSEM_C1MISR_MISF15_Msk /*!<semaphore 15 CPU1 interrupt masked status bit. */ 4828 4829 /******************** Bit definition for HSEM_C2IER register *****************/ 4830 #define HSEM_C2IER_ISE0_Pos (0U) 4831 #define HSEM_C2IER_ISE0_Msk (0x1UL << HSEM_C2IER_ISE0_Pos) /*!< 0x00000001 */ 4832 #define HSEM_C2IER_ISE0 HSEM_C2IER_ISE0_Msk /*!<semaphore 0 CPU2 interrupt enable bit. */ 4833 #define HSEM_C2IER_ISE1_Pos (1U) 4834 #define HSEM_C2IER_ISE1_Msk (0x1UL << HSEM_C2IER_ISE1_Pos) /*!< 0x00000002 */ 4835 #define HSEM_C2IER_ISE1 HSEM_C2IER_ISE1_Msk /*!<semaphore 1 CPU2 interrupt enable bit. */ 4836 #define HSEM_C2IER_ISE2_Pos (2U) 4837 #define HSEM_C2IER_ISE2_Msk (0x1UL << HSEM_C2IER_ISE2_Pos) /*!< 0x00000004 */ 4838 #define HSEM_C2IER_ISE2 HSEM_C2IER_ISE2_Msk /*!<semaphore 2 CPU2 interrupt enable bit. */ 4839 #define HSEM_C2IER_ISE3_Pos (3U) 4840 #define HSEM_C2IER_ISE3_Msk (0x1UL << HSEM_C2IER_ISE3_Pos) /*!< 0x00000008 */ 4841 #define HSEM_C2IER_ISE3 HSEM_C2IER_ISE3_Msk /*!<semaphore 3 CPU2 interrupt enable bit. */ 4842 #define HSEM_C2IER_ISE4_Pos (4U) 4843 #define HSEM_C2IER_ISE4_Msk (0x1UL << HSEM_C2IER_ISE4_Pos) /*!< 0x00000010 */ 4844 #define HSEM_C2IER_ISE4 HSEM_C2IER_ISE4_Msk /*!<semaphore 4 CPU2 interrupt enable bit. */ 4845 #define HSEM_C2IER_ISE5_Pos (5U) 4846 #define HSEM_C2IER_ISE5_Msk (0x1UL << HSEM_C2IER_ISE5_Pos) /*!< 0x00000020 */ 4847 #define HSEM_C2IER_ISE5 HSEM_C2IER_ISE5_Msk /*!<semaphore 5 CPU2 interrupt enable bit. */ 4848 #define HSEM_C2IER_ISE6_Pos (6U) 4849 #define HSEM_C2IER_ISE6_Msk (0x1UL << HSEM_C2IER_ISE6_Pos) /*!< 0x00000040 */ 4850 #define HSEM_C2IER_ISE6 HSEM_C2IER_ISE6_Msk /*!<semaphore 6 CPU2 interrupt enable bit. */ 4851 #define HSEM_C2IER_ISE7_Pos (7U) 4852 #define HSEM_C2IER_ISE7_Msk (0x1UL << HSEM_C2IER_ISE7_Pos) /*!< 0x00000080 */ 4853 #define HSEM_C2IER_ISE7 HSEM_C2IER_ISE7_Msk /*!<semaphore 7 CPU2 interrupt enable bit. */ 4854 #define HSEM_C2IER_ISE8_Pos (8U) 4855 #define HSEM_C2IER_ISE8_Msk (0x1UL << HSEM_C2IER_ISE8_Pos) /*!< 0x00000100 */ 4856 #define HSEM_C2IER_ISE8 HSEM_C2IER_ISE8_Msk /*!<semaphore 8 CPU2 interrupt enable bit. */ 4857 #define HSEM_C2IER_ISE9_Pos (9U) 4858 #define HSEM_C2IER_ISE9_Msk (0x1UL << HSEM_C2IER_ISE9_Pos) /*!< 0x00000200 */ 4859 #define HSEM_C2IER_ISE9 HSEM_C2IER_ISE9_Msk /*!<semaphore 9 CPU2 interrupt enable bit. */ 4860 #define HSEM_C2IER_ISE10_Pos (10U) 4861 #define HSEM_C2IER_ISE10_Msk (0x1UL << HSEM_C2IER_ISE10_Pos) /*!< 0x00000400 */ 4862 #define HSEM_C2IER_ISE10 HSEM_C2IER_ISE10_Msk /*!<semaphore 10 CPU2 interrupt enable bit. */ 4863 #define HSEM_C2IER_ISE11_Pos (11U) 4864 #define HSEM_C2IER_ISE11_Msk (0x1UL << HSEM_C2IER_ISE11_Pos) /*!< 0x00000800 */ 4865 #define HSEM_C2IER_ISE11 HSEM_C2IER_ISE11_Msk /*!<semaphore 11 CPU2 interrupt enable bit. */ 4866 #define HSEM_C2IER_ISE12_Pos (12U) 4867 #define HSEM_C2IER_ISE12_Msk (0x1UL << HSEM_C2IER_ISE12_Pos) /*!< 0x00001000 */ 4868 #define HSEM_C2IER_ISE12 HSEM_C2IER_ISE12_Msk /*!<semaphore 12 CPU2 interrupt enable bit. */ 4869 #define HSEM_C2IER_ISE13_Pos (13U) 4870 #define HSEM_C2IER_ISE13_Msk (0x1UL << HSEM_C2IER_ISE13_Pos) /*!< 0x00002000 */ 4871 #define HSEM_C2IER_ISE13 HSEM_C2IER_ISE13_Msk /*!<semaphore 13 CPU2 interrupt enable bit. */ 4872 #define HSEM_C2IER_ISE14_Pos (14U) 4873 #define HSEM_C2IER_ISE14_Msk (0x1UL << HSEM_C2IER_ISE14_Pos) /*!< 0x00004000 */ 4874 #define HSEM_C2IER_ISE14 HSEM_C2IER_ISE14_Msk /*!<semaphore 14 CPU2 interrupt enable bit. */ 4875 #define HSEM_C2IER_ISE15_Pos (15U) 4876 #define HSEM_C2IER_ISE15_Msk (0x1UL << HSEM_C2IER_ISE15_Pos) /*!< 0x00008000 */ 4877 #define HSEM_C2IER_ISE15 HSEM_C2IER_ISE15_Msk /*!<semaphore 15 CPU2 interrupt enable bit. */ 4878 4879 /******************** Bit definition for HSEM_C2ICR register *****************/ 4880 #define HSEM_C2ICR_ISC0_Pos (0U) 4881 #define HSEM_C2ICR_ISC0_Msk (0x1UL << HSEM_C2ICR_ISC0_Pos) /*!< 0x00000001 */ 4882 #define HSEM_C2ICR_ISC0 HSEM_C2ICR_ISC0_Msk /*!<semaphore 0 CPU2 interrupt clear bit. */ 4883 #define HSEM_C2ICR_ISC1_Pos (1U) 4884 #define HSEM_C2ICR_ISC1_Msk (0x1UL << HSEM_C2ICR_ISC1_Pos) /*!< 0x00000002 */ 4885 #define HSEM_C2ICR_ISC1 HSEM_C2ICR_ISC1_Msk /*!<semaphore 1 CPU2 interrupt clear bit. */ 4886 #define HSEM_C2ICR_ISC2_Pos (2U) 4887 #define HSEM_C2ICR_ISC2_Msk (0x1UL << HSEM_C2ICR_ISC2_Pos) /*!< 0x00000004 */ 4888 #define HSEM_C2ICR_ISC2 HSEM_C2ICR_ISC2_Msk /*!<semaphore 2 CPU2 interrupt clear bit. */ 4889 #define HSEM_C2ICR_ISC3_Pos (3U) 4890 #define HSEM_C2ICR_ISC3_Msk (0x1UL << HSEM_C2ICR_ISC3_Pos) /*!< 0x00000008 */ 4891 #define HSEM_C2ICR_ISC3 HSEM_C2ICR_ISC3_Msk /*!<semaphore 3 CPU2 interrupt clear bit. */ 4892 #define HSEM_C2ICR_ISC4_Pos (4U) 4893 #define HSEM_C2ICR_ISC4_Msk (0x1UL << HSEM_C2ICR_ISC4_Pos) /*!< 0x00000010 */ 4894 #define HSEM_C2ICR_ISC4 HSEM_C2ICR_ISC4_Msk /*!<semaphore 4 CPU2 interrupt clear bit. */ 4895 #define HSEM_C2ICR_ISC5_Pos (5U) 4896 #define HSEM_C2ICR_ISC5_Msk (0x1UL << HSEM_C2ICR_ISC5_Pos) /*!< 0x00000020 */ 4897 #define HSEM_C2ICR_ISC5 HSEM_C2ICR_ISC5_Msk /*!<semaphore 5 CPU2 interrupt clear bit. */ 4898 #define HSEM_C2ICR_ISC6_Pos (6U) 4899 #define HSEM_C2ICR_ISC6_Msk (0x1UL << HSEM_C2ICR_ISC6_Pos) /*!< 0x00000040 */ 4900 #define HSEM_C2ICR_ISC6 HSEM_C2ICR_ISC6_Msk /*!<semaphore 6 CPU2 interrupt clear bit. */ 4901 #define HSEM_C2ICR_ISC7_Pos (7U) 4902 #define HSEM_C2ICR_ISC7_Msk (0x1UL << HSEM_C2ICR_ISC7_Pos) /*!< 0x00000080 */ 4903 #define HSEM_C2ICR_ISC7 HSEM_C2ICR_ISC7_Msk /*!<semaphore 7 CPU2 interrupt clear bit. */ 4904 #define HSEM_C2ICR_ISC8_Pos (8U) 4905 #define HSEM_C2ICR_ISC8_Msk (0x1UL << HSEM_C2ICR_ISC8_Pos) /*!< 0x00000100 */ 4906 #define HSEM_C2ICR_ISC8 HSEM_C2ICR_ISC8_Msk /*!<semaphore 8 CPU2 interrupt clear bit. */ 4907 #define HSEM_C2ICR_ISC9_Pos (9U) 4908 #define HSEM_C2ICR_ISC9_Msk (0x1UL << HSEM_C2ICR_ISC9_Pos) /*!< 0x00000200 */ 4909 #define HSEM_C2ICR_ISC9 HSEM_C2ICR_ISC9_Msk /*!<semaphore 9 CPU2 interrupt clear bit. */ 4910 #define HSEM_C2ICR_ISC10_Pos (10U) 4911 #define HSEM_C2ICR_ISC10_Msk (0x1UL << HSEM_C2ICR_ISC10_Pos) /*!< 0x00000400 */ 4912 #define HSEM_C2ICR_ISC10 HSEM_C2ICR_ISC10_Msk /*!<semaphore 10 CPU2 interrupt clear bit. */ 4913 #define HSEM_C2ICR_ISC11_Pos (11U) 4914 #define HSEM_C2ICR_ISC11_Msk (0x1UL << HSEM_C2ICR_ISC11_Pos) /*!< 0x00000800 */ 4915 #define HSEM_C2ICR_ISC11 HSEM_C2ICR_ISC11_Msk /*!<semaphore 11 CPU2 interrupt clear bit. */ 4916 #define HSEM_C2ICR_ISC12_Pos (12U) 4917 #define HSEM_C2ICR_ISC12_Msk (0x1UL << HSEM_C2ICR_ISC12_Pos) /*!< 0x00001000 */ 4918 #define HSEM_C2ICR_ISC12 HSEM_C2ICR_ISC12_Msk /*!<semaphore 12 CPU2 interrupt clear bit. */ 4919 #define HSEM_C2ICR_ISC13_Pos (13U) 4920 #define HSEM_C2ICR_ISC13_Msk (0x1UL << HSEM_C2ICR_ISC13_Pos) /*!< 0x00002000 */ 4921 #define HSEM_C2ICR_ISC13 HSEM_C2ICR_ISC13_Msk /*!<semaphore 13 CPU2 interrupt clear bit. */ 4922 #define HSEM_C2ICR_ISC14_Pos (14U) 4923 #define HSEM_C2ICR_ISC14_Msk (0x1UL << HSEM_C2ICR_ISC14_Pos) /*!< 0x00004000 */ 4924 #define HSEM_C2ICR_ISC14 HSEM_C2ICR_ISC14_Msk /*!<semaphore 14 CPU2 interrupt clear bit. */ 4925 #define HSEM_C2ICR_ISC15_Pos (15U) 4926 #define HSEM_C2ICR_ISC15_Msk (0x1UL << HSEM_C2ICR_ISC15_Pos) /*!< 0x00008000 */ 4927 #define HSEM_C2ICR_ISC15 HSEM_C2ICR_ISC15_Msk /*!<semaphore 15 CPU2 interrupt clear bit. */ 4928 4929 /******************** Bit definition for HSEM_C2ISR register *****************/ 4930 #define HSEM_C2ISR_ISF0_Pos (0U) 4931 #define HSEM_C2ISR_ISF0_Msk (0x1UL << HSEM_C2ISR_ISF0_Pos) /*!< 0x00000001 */ 4932 #define HSEM_C2ISR_ISF0 HSEM_C2ISR_ISF0_Msk /*!<semaphore 0 CPU2 interrupt status bit. */ 4933 #define HSEM_C2ISR_ISF1_Pos (1U) 4934 #define HSEM_C2ISR_ISF1_Msk (0x1UL << HSEM_C2ISR_ISF1_Pos) /*!< 0x00000002 */ 4935 #define HSEM_C2ISR_ISF1 HSEM_C2ISR_ISF1_Msk /*!<semaphore 1 CPU2 interrupt status bit. */ 4936 #define HSEM_C2ISR_ISF2_Pos (2U) 4937 #define HSEM_C2ISR_ISF2_Msk (0x1UL << HSEM_C2ISR_ISF2_Pos) /*!< 0x00000004 */ 4938 #define HSEM_C2ISR_ISF2 HSEM_C2ISR_ISF2_Msk /*!<semaphore 2 CPU2 interrupt status bit. */ 4939 #define HSEM_C2ISR_ISF3_Pos (3U) 4940 #define HSEM_C2ISR_ISF3_Msk (0x1UL << HSEM_C2ISR_ISF3_Pos) /*!< 0x00000008 */ 4941 #define HSEM_C2ISR_ISF3 HSEM_C2ISR_ISF3_Msk /*!<semaphore 3 CPU2 interrupt status bit. */ 4942 #define HSEM_C2ISR_ISF4_Pos (4U) 4943 #define HSEM_C2ISR_ISF4_Msk (0x1UL << HSEM_C2ISR_ISF4_Pos) /*!< 0x00000010 */ 4944 #define HSEM_C2ISR_ISF4 HSEM_C2ISR_ISF4_Msk /*!<semaphore 4 CPU2 interrupt status bit. */ 4945 #define HSEM_C2ISR_ISF5_Pos (5U) 4946 #define HSEM_C2ISR_ISF5_Msk (0x1UL << HSEM_C2ISR_ISF5_Pos) /*!< 0x00000020 */ 4947 #define HSEM_C2ISR_ISF5 HSEM_C2ISR_ISF5_Msk /*!<semaphore 5 CPU2 interrupt status bit. */ 4948 #define HSEM_C2ISR_ISF6_Pos (6U) 4949 #define HSEM_C2ISR_ISF6_Msk (0x1UL << HSEM_C2ISR_ISF6_Pos) /*!< 0x00000040 */ 4950 #define HSEM_C2ISR_ISF6 HSEM_C2ISR_ISF6_Msk /*!<semaphore 6 CPU2 interrupt status bit. */ 4951 #define HSEM_C2ISR_ISF7_Pos (7U) 4952 #define HSEM_C2ISR_ISF7_Msk (0x1UL << HSEM_C2ISR_ISF7_Pos) /*!< 0x00000080 */ 4953 #define HSEM_C2ISR_ISF7 HSEM_C2ISR_ISF7_Msk /*!<semaphore 7 CPU2 interrupt status bit. */ 4954 #define HSEM_C2ISR_ISF8_Pos (8U) 4955 #define HSEM_C2ISR_ISF8_Msk (0x1UL << HSEM_C2ISR_ISF8_Pos) /*!< 0x00000100 */ 4956 #define HSEM_C2ISR_ISF8 HSEM_C2ISR_ISF8_Msk /*!<semaphore 8 CPU2 interrupt status bit. */ 4957 #define HSEM_C2ISR_ISF9_Pos (9U) 4958 #define HSEM_C2ISR_ISF9_Msk (0x1UL << HSEM_C2ISR_ISF9_Pos) /*!< 0x00000200 */ 4959 #define HSEM_C2ISR_ISF9 HSEM_C2ISR_ISF9_Msk /*!<semaphore 9 CPU2 interrupt status bit. */ 4960 #define HSEM_C2ISR_ISF10_Pos (10U) 4961 #define HSEM_C2ISR_ISF10_Msk (0x1UL << HSEM_C2ISR_ISF10_Pos) /*!< 0x00000400 */ 4962 #define HSEM_C2ISR_ISF10 HSEM_C2ISR_ISF10_Msk /*!<semaphore 10 CPU2 interrupt status bit. */ 4963 #define HSEM_C2ISR_ISF11_Pos (11U) 4964 #define HSEM_C2ISR_ISF11_Msk (0x1UL << HSEM_C2ISR_ISF11_Pos) /*!< 0x00000800 */ 4965 #define HSEM_C2ISR_ISF11 HSEM_C2ISR_ISF11_Msk /*!<semaphore 11 CPU2 interrupt status bit. */ 4966 #define HSEM_C2ISR_ISF12_Pos (12U) 4967 #define HSEM_C2ISR_ISF12_Msk (0x1UL << HSEM_C2ISR_ISF12_Pos) /*!< 0x00001000 */ 4968 #define HSEM_C2ISR_ISF12 HSEM_C2ISR_ISF12_Msk /*!<semaphore 12 CPU2 interrupt status bit. */ 4969 #define HSEM_C2ISR_ISF13_Pos (13U) 4970 #define HSEM_C2ISR_ISF13_Msk (0x1UL << HSEM_C2ISR_ISF13_Pos) /*!< 0x00002000 */ 4971 #define HSEM_C2ISR_ISF13 HSEM_C2ISR_ISF13_Msk /*!<semaphore 13 CPU2 interrupt status bit. */ 4972 #define HSEM_C2ISR_ISF14_Pos (14U) 4973 #define HSEM_C2ISR_ISF14_Msk (0x1UL << HSEM_C2ISR_ISF14_Pos) /*!< 0x00004000 */ 4974 #define HSEM_C2ISR_ISF14 HSEM_C2ISR_ISF14_Msk /*!<semaphore 14 CPU2 interrupt status bit. */ 4975 #define HSEM_C2ISR_ISF15_Pos (15U) 4976 #define HSEM_C2ISR_ISF15_Msk (0x1UL << HSEM_C2ISR_ISF15_Pos) /*!< 0x00008000 */ 4977 #define HSEM_C2ISR_ISF15 HSEM_C2ISR_ISF15_Msk /*!<semaphore 15 CPU2 interrupt status bit. */ 4978 4979 /******************** Bit definition for HSEM_C2MISR register *****************/ 4980 #define HSEM_C2MISR_MISF0_Pos (0U) 4981 #define HSEM_C2MISR_MISF0_Msk (0x1UL << HSEM_C2MISR_MISF0_Pos) /*!< 0x00000001 */ 4982 #define HSEM_C2MISR_MISF0 HSEM_C2MISR_MISF0_Msk /*!<semaphore 0 CPU2 interrupt masked status bit. */ 4983 #define HSEM_C2MISR_MISF1_Pos (1U) 4984 #define HSEM_C2MISR_MISF1_Msk (0x1UL << HSEM_C2MISR_MISF1_Pos) /*!< 0x00000002 */ 4985 #define HSEM_C2MISR_MISF1 HSEM_C2MISR_MISF1_Msk /*!<semaphore 1 CPU2 interrupt masked status bit. */ 4986 #define HSEM_C2MISR_MISF2_Pos (2U) 4987 #define HSEM_C2MISR_MISF2_Msk (0x1UL << HSEM_C2MISR_MISF2_Pos) /*!< 0x00000004 */ 4988 #define HSEM_C2MISR_MISF2 HSEM_C2MISR_MISF2_Msk /*!<semaphore 2 CPU2 interrupt masked status bit. */ 4989 #define HSEM_C2MISR_MISF3_Pos (3U) 4990 #define HSEM_C2MISR_MISF3_Msk (0x1UL << HSEM_C2MISR_MISF3_Pos) /*!< 0x00000008 */ 4991 #define HSEM_C2MISR_MISF3 HSEM_C2MISR_MISF3_Msk /*!<semaphore 3 CPU2 interrupt masked status bit. */ 4992 #define HSEM_C2MISR_MISF4_Pos (4U) 4993 #define HSEM_C2MISR_MISF4_Msk (0x1UL << HSEM_C2MISR_MISF4_Pos) /*!< 0x00000010 */ 4994 #define HSEM_C2MISR_MISF4 HSEM_C2MISR_MISF4_Msk /*!<semaphore 4 CPU2 interrupt masked status bit. */ 4995 #define HSEM_C2MISR_MISF5_Pos (5U) 4996 #define HSEM_C2MISR_MISF5_Msk (0x1UL << HSEM_C2MISR_MISF5_Pos) /*!< 0x00000020 */ 4997 #define HSEM_C2MISR_MISF5 HSEM_C2MISR_MISF5_Msk /*!<semaphore 5 CPU2 interrupt masked status bit. */ 4998 #define HSEM_C2MISR_MISF6_Pos (6U) 4999 #define HSEM_C2MISR_MISF6_Msk (0x1UL << HSEM_C2MISR_MISF6_Pos) /*!< 0x00000040 */ 5000 #define HSEM_C2MISR_MISF6 HSEM_C2MISR_MISF6_Msk /*!<semaphore 6 CPU2 interrupt masked status bit. */ 5001 #define HSEM_C2MISR_MISF7_Pos (7U) 5002 #define HSEM_C2MISR_MISF7_Msk (0x1UL << HSEM_C2MISR_MISF7_Pos) /*!< 0x00000080 */ 5003 #define HSEM_C2MISR_MISF7 HSEM_C2MISR_MISF7_Msk /*!<semaphore 7 CPU2 interrupt masked status bit. */ 5004 #define HSEM_C2MISR_MISF8_Pos (8U) 5005 #define HSEM_C2MISR_MISF8_Msk (0x1UL << HSEM_C2MISR_MISF8_Pos) /*!< 0x00000100 */ 5006 #define HSEM_C2MISR_MISF8 HSEM_C2MISR_MISF8_Msk /*!<semaphore 8 CPU2 interrupt masked status bit. */ 5007 #define HSEM_C2MISR_MISF9_Pos (9U) 5008 #define HSEM_C2MISR_MISF9_Msk (0x1UL << HSEM_C2MISR_MISF9_Pos) /*!< 0x00000200 */ 5009 #define HSEM_C2MISR_MISF9 HSEM_C2MISR_MISF9_Msk /*!<semaphore 9 CPU2 interrupt masked status bit. */ 5010 #define HSEM_C2MISR_MISF10_Pos (10U) 5011 #define HSEM_C2MISR_MISF10_Msk (0x1UL << HSEM_C2MISR_MISF10_Pos) /*!< 0x00000400 */ 5012 #define HSEM_C2MISR_MISF10 HSEM_C2MISR_MISF10_Msk /*!<semaphore 10 CPU2 interrupt masked status bit. */ 5013 #define HSEM_C2MISR_MISF11_Pos (11U) 5014 #define HSEM_C2MISR_MISF11_Msk (0x1UL << HSEM_C2MISR_MISF11_Pos) /*!< 0x00000800 */ 5015 #define HSEM_C2MISR_MISF11 HSEM_C2MISR_MISF11_Msk /*!<semaphore 11 CPU2 interrupt masked status bit. */ 5016 #define HSEM_C2MISR_MISF12_Pos (12U) 5017 #define HSEM_C2MISR_MISF12_Msk (0x1UL << HSEM_C2MISR_MISF12_Pos) /*!< 0x00001000 */ 5018 #define HSEM_C2MISR_MISF12 HSEM_C2MISR_MISF12_Msk /*!<semaphore 12 CPU2 interrupt masked status bit. */ 5019 #define HSEM_C2MISR_MISF13_Pos (13U) 5020 #define HSEM_C2MISR_MISF13_Msk (0x1UL << HSEM_C2MISR_MISF13_Pos) /*!< 0x00002000 */ 5021 #define HSEM_C2MISR_MISF13 HSEM_C2MISR_MISF13_Msk /*!<semaphore 13 CPU2 interrupt masked status bit. */ 5022 #define HSEM_C2MISR_MISF14_Pos (14U) 5023 #define HSEM_C2MISR_MISF14_Msk (0x1UL << HSEM_C2MISR_MISF14_Pos) /*!< 0x00004000 */ 5024 #define HSEM_C2MISR_MISF14 HSEM_C2MISR_MISF14_Msk /*!<semaphore 14 CPU2 interrupt masked status bit. */ 5025 #define HSEM_C2MISR_MISF15_Pos (15U) 5026 #define HSEM_C2MISR_MISF15_Msk (0x1UL << HSEM_C2MISR_MISF15_Pos) /*!< 0x00008000 */ 5027 #define HSEM_C2MISR_MISF15 HSEM_C2MISR_MISF15_Msk /*!<semaphore 15 CPU2 interrupt masked status bit. */ 5028 5029 /******************** Bit definition for HSEM_CR register *****************/ 5030 #define HSEM_CR_COREID_Pos (8U) 5031 #define HSEM_CR_COREID_Msk (0xFUL << HSEM_CR_COREID_Pos) /*!< 0x00000F00 */ 5032 #define HSEM_CR_COREID HSEM_CR_COREID_Msk /*!<CoreID of semaphores to be cleared. */ 5033 #define HSEM_CR_COREID_CPU1 (0x4U << HSEM_CR_COREID_Pos) 5034 #define HSEM_CR_COREID_CPU2 (0x8U << HSEM_CR_COREID_Pos) 5035 #define HSEM_CR_COREID_CURRENT HSEM_CR_COREID_CPU1 5036 #define HSEM_CR_KEY_Pos (16U) 5037 #define HSEM_CR_KEY_Msk (0xFFFFUL << HSEM_CR_KEY_Pos) /*!< 0xFFFF0000 */ 5038 #define HSEM_CR_KEY HSEM_CR_KEY_Msk /*!<semaphores clear key. */ 5039 5040 /******************** Bit definition for HSEM_KEYR register *****************/ 5041 #define HSEM_KEYR_KEY_Pos (16U) 5042 #define HSEM_KEYR_KEY_Msk (0xFFFFUL << HSEM_KEYR_KEY_Pos) /*!< 0xFFFF0000 */ 5043 #define HSEM_KEYR_KEY HSEM_KEYR_KEY_Msk /*!<semaphores clear key. */ 5044 5045 /******************************************************************************/ 5046 /* */ 5047 /* Public Key Accelerator (PKA) */ 5048 /* */ 5049 /******************************************************************************/ 5050 5051 /******************* Bits definition for PKA_CR register **************/ 5052 #define PKA_CR_EN_Pos (0U) 5053 #define PKA_CR_EN_Msk (0x1UL << PKA_CR_EN_Pos) /*!< 0x00000001 */ 5054 #define PKA_CR_EN PKA_CR_EN_Msk /*!< PKA enable */ 5055 #define PKA_CR_START_Pos (1U) 5056 #define PKA_CR_START_Msk (0x1UL << PKA_CR_START_Pos) /*!< 0x00000002 */ 5057 #define PKA_CR_START PKA_CR_START_Msk /*!< Start operation */ 5058 #define PKA_CR_MODE_Pos (8U) 5059 #define PKA_CR_MODE_Msk (0x3FUL << PKA_CR_MODE_Pos) /*!< 0x00003F00 */ 5060 #define PKA_CR_MODE PKA_CR_MODE_Msk /*!< MODE[5:0] PKA operation code */ 5061 #define PKA_CR_MODE_0 (0x01UL << PKA_CR_MODE_Pos) /*!< 0x00000100 */ 5062 #define PKA_CR_MODE_1 (0x02UL << PKA_CR_MODE_Pos) /*!< 0x00000200 */ 5063 #define PKA_CR_MODE_2 (0x04UL << PKA_CR_MODE_Pos) /*!< 0x00000400 */ 5064 #define PKA_CR_MODE_3 (0x08UL << PKA_CR_MODE_Pos) /*!< 0x00000800 */ 5065 #define PKA_CR_MODE_4 (0x10UL << PKA_CR_MODE_Pos) /*!< 0x00001000 */ 5066 #define PKA_CR_MODE_5 (0x20UL << PKA_CR_MODE_Pos) /*!< 0x00002000 */ 5067 #define PKA_CR_PROCENDIE_Pos (17U) 5068 #define PKA_CR_PROCENDIE_Msk (0x1UL << PKA_CR_PROCENDIE_Pos) /*!< 0x00020000 */ 5069 #define PKA_CR_PROCENDIE PKA_CR_PROCENDIE_Msk /*!< End of operation interrupt enable */ 5070 #define PKA_CR_RAMERRIE_Pos (19U) 5071 #define PKA_CR_RAMERRIE_Msk (0x1UL << PKA_CR_RAMERRIE_Pos) /*!< 0x00080000 */ 5072 #define PKA_CR_RAMERRIE PKA_CR_RAMERRIE_Msk /*!< RAM error interrupt enable */ 5073 #define PKA_CR_ADDRERRIE_Pos (20U) 5074 #define PKA_CR_ADDRERRIE_Msk (0x1UL << PKA_CR_ADDRERRIE_Pos) /*!< 0x00100000 */ 5075 #define PKA_CR_ADDRERRIE PKA_CR_ADDRERRIE_Msk /*!< RAM error interrupt enable */ 5076 5077 /******************* Bits definition for PKA_SR register **************/ 5078 #define PKA_SR_BUSY_Pos (16U) 5079 #define PKA_SR_BUSY_Msk (0x1UL << PKA_SR_BUSY_Pos) /*!< 0x00010000 */ 5080 #define PKA_SR_BUSY PKA_SR_BUSY_Msk /*!< PKA operation is in progress */ 5081 #define PKA_SR_PROCENDF_Pos (17U) 5082 #define PKA_SR_PROCENDF_Msk (0x1UL << PKA_SR_PROCENDF_Pos) /*!< 0x00020000 */ 5083 #define PKA_SR_PROCENDF PKA_SR_PROCENDF_Msk /*!< PKA end of operation flag */ 5084 #define PKA_SR_RAMERRF_Pos (19U) 5085 #define PKA_SR_RAMERRF_Msk (0x1UL << PKA_SR_RAMERRF_Pos) /*!< 0x00080000 */ 5086 #define PKA_SR_RAMERRF PKA_SR_RAMERRF_Msk /*!< PKA RAM error flag */ 5087 #define PKA_SR_ADDRERRF_Pos (20U) 5088 #define PKA_SR_ADDRERRF_Msk (0x1UL << PKA_SR_ADDRERRF_Pos) /*!< 0x00100000 */ 5089 #define PKA_SR_ADDRERRF PKA_SR_ADDRERRF_Msk /*!< Address error flag */ 5090 5091 /******************* Bits definition for PKA_CLRFR register **************/ 5092 #define PKA_CLRFR_PROCENDFC_Pos (17U) 5093 #define PKA_CLRFR_PROCENDFC_Msk (0x1UL << PKA_CLRFR_PROCENDFC_Pos) /*!< 0x00020000 */ 5094 #define PKA_CLRFR_PROCENDFC PKA_CLRFR_PROCENDFC_Msk /*!< Clear PKA end of operation flag */ 5095 #define PKA_CLRFR_RAMERRFC_Pos (19U) 5096 #define PKA_CLRFR_RAMERRFC_Msk (0x1UL << PKA_CLRFR_RAMERRFC_Pos) /*!< 0x00080000 */ 5097 #define PKA_CLRFR_RAMERRFC PKA_CLRFR_RAMERRFC_Msk /*!< Clear PKA RAM error flag */ 5098 #define PKA_CLRFR_ADDRERRFC_Pos (20U) 5099 #define PKA_CLRFR_ADDRERRFC_Msk (0x1UL << PKA_CLRFR_ADDRERRFC_Pos) /*!< 0x00100000 */ 5100 #define PKA_CLRFR_ADDRERRFC PKA_CLRFR_ADDRERRFC_Msk /*!< Clear address error flag */ 5101 5102 /******************* Bits definition for PKA RAM *************************/ 5103 #define PKA_RAM_OFFSET 0x400U /*!< PKA RAM address offset */ 5104 5105 /* Compute Montgomery parameter input data */ 5106 #define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ 5107 #define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ 5108 5109 /* Compute Montgomery parameter output data */ 5110 #define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ 5111 5112 /* Compute modular exponentiation input data */ 5113 #define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ 5114 #define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ 5115 #define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ 5116 #define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ 5117 #define PKA_MODULAR_EXP_IN_EXPONENT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ 5118 #define PKA_MODULAR_EXP_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ 5119 5120 /* Compute modular exponentiation output data */ 5121 #define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ 5122 #define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC1 ((0x724U - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 1 */ 5123 #define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC2 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 2 */ 5124 #define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ 5125 #define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC3 ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 3 */ 5126 5127 /* Compute ECC scalar multiplication input data */ 5128 #define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ 5129 #define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ 5130 #define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ 5131 #define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ 5132 #define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ 5133 #define PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM ((0x4B4U - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ 5134 #define PKA_ECC_SCALAR_MUL_IN_K ((0x508U - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ 5135 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ 5136 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ 5137 5138 /* Compute ECC scalar multiplication output data */ 5139 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ 5140 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ 5141 #define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_X1 ((0xDE8U - PKA_RAM_OFFSET)>>2) /*!< Output last double X1 coordinate */ 5142 #define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Y1 ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Output last double Y1 coordinate */ 5143 #define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Z1 ((0xE90U - PKA_RAM_OFFSET)>>2) /*!< Output last double Z1 coordinate */ 5144 #define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_X2 ((0xEE4U - PKA_RAM_OFFSET)>>2) /*!< Output check point X2 coordinate */ 5145 #define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Y2 ((0xF38U - PKA_RAM_OFFSET)>>2) /*!< Output check point Y2 coordinate */ 5146 #define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Z2 ((0xF8CU - PKA_RAM_OFFSET)>>2) /*!< Output check point Z2 coordinate */ 5147 5148 /* Point check input data */ 5149 #define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ 5150 #define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ 5151 #define PKA_POINT_CHECK_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ 5152 #define PKA_POINT_CHECK_IN_B_COEFF ((0x7FCU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ 5153 #define PKA_POINT_CHECK_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ 5154 #define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ 5155 #define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ 5156 5157 /* Point check output data */ 5158 #define PKA_POINT_CHECK_OUT_ERROR ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Output error */ 5159 5160 /* ECDSA signature input data */ 5161 #define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ 5162 #define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ 5163 #define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ 5164 #define PKA_ECDSA_SIGN_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ 5165 #define PKA_ECDSA_SIGN_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ 5166 #define PKA_ECDSA_SIGN_IN_K ((0x508U - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ 5167 #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ 5168 #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ 5169 #define PKA_ECDSA_SIGN_IN_HASH_E ((0xDE8U - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ 5170 #define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ 5171 #define PKA_ECDSA_SIGN_IN_ORDER_N ((0xE94U - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ 5172 5173 /* ECDSA signature output data */ 5174 #define PKA_ECDSA_SIGN_OUT_ERROR ((0xEE8U - PKA_RAM_OFFSET)>>2) /*!< Output error */ 5175 #define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x700U - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ 5176 #define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x754U - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ 5177 #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x103CU - PKA_RAM_OFFSET)>>2) /*!< Output final point kP X coordinate */ 5178 #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1090U - PKA_RAM_OFFSET)>>2) /*!< Output final point kP Y coordinate */ 5179 5180 /* ECDSA verification input data */ 5181 #define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ 5182 #define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x4B4U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ 5183 #define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x45CU - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ 5184 #define PKA_ECDSA_VERIF_IN_A_COEFF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ 5185 #define PKA_ECDSA_VERIF_IN_MOD_GF ((0x4B8U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ 5186 #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x5E8U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ 5187 #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x63CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ 5188 #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0xF40U - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ 5189 #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0xF94U - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ 5190 #define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x1098U - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ 5191 #define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ 5192 #define PKA_ECDSA_VERIF_IN_HASH_E ((0xFE8U - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ 5193 #define PKA_ECDSA_VERIF_IN_ORDER_N ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ 5194 5195 /* ECDSA verification output data */ 5196 #define PKA_ECDSA_VERIF_OUT_RESULT ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ 5197 5198 /* RSA CRT exponentiation input data */ 5199 #define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ 5200 #define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x65CU - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ 5201 #define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ 5202 #define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x7ECU - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ 5203 #define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x97CU - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ 5204 #define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ 5205 #define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0xEECU - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ 5206 5207 /* RSA CRT exponentiation output data */ 5208 #define PKA_RSA_CRT_EXP_OUT_RESULT ((0x724U - PKA_RAM_OFFSET)>>2) /*!< Output result */ 5209 5210 /* Modular reduction input data */ 5211 #define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ 5212 #define PKA_MODULAR_REDUC_IN_OPERAND ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand */ 5213 #define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ 5214 #define PKA_MODULAR_REDUC_IN_MODULUS ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ 5215 5216 /* Modular reduction output data */ 5217 #define PKA_MODULAR_REDUC_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ 5218 5219 /* Arithmetic addition input data */ 5220 #define PKA_ARITHMETIC_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ 5221 #define PKA_ARITHMETIC_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ 5222 #define PKA_ARITHMETIC_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ 5223 5224 /* Arithmetic addition output data */ 5225 #define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ 5226 5227 /* Arithmetic subtraction input data */ 5228 #define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ 5229 #define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ 5230 #define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ 5231 5232 /* Arithmetic subtraction output data */ 5233 #define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ 5234 5235 /* Arithmetic multiplication input data */ 5236 #define PKA_ARITHMETIC_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ 5237 #define PKA_ARITHMETIC_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ 5238 #define PKA_ARITHMETIC_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ 5239 5240 /* Arithmetic multiplication output data */ 5241 #define PKA_ARITHMETIC_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ 5242 5243 /* Comparison input data */ 5244 #define PKA_COMPARISON_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ 5245 #define PKA_COMPARISON_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ 5246 #define PKA_COMPARISON_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ 5247 5248 /* Comparison output data */ 5249 #define PKA_COMPARISON_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ 5250 5251 /* Modular addition input data */ 5252 #define PKA_MODULAR_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ 5253 #define PKA_MODULAR_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ 5254 #define PKA_MODULAR_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ 5255 #define PKA_MODULAR_ADD_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ 5256 5257 /* Modular addition output data */ 5258 #define PKA_MODULAR_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ 5259 5260 /* Modular inversion input data */ 5261 #define PKA_MODULAR_INV_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ 5262 #define PKA_MODULAR_INV_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ 5263 #define PKA_MODULAR_INV_IN_OP2_MOD ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ 5264 5265 /* Modular inversion output data */ 5266 #define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ 5267 5268 /* Modular subtraction input data */ 5269 #define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ 5270 #define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ 5271 #define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ 5272 #define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ 5273 5274 /* Modular subtraction output data */ 5275 #define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ 5276 5277 /* Montgomery multiplication input data */ 5278 #define PKA_MONTGOMERY_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ 5279 #define PKA_MONTGOMERY_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ 5280 #define PKA_MONTGOMERY_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ 5281 #define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ 5282 5283 /* Montgomery multiplication output data */ 5284 #define PKA_MONTGOMERY_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ 5285 5286 /* Generic Arithmetic input data */ 5287 #define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ 5288 #define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ 5289 #define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ 5290 #define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ 5291 5292 /* Generic Arithmetic output data */ 5293 #define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ 5294 5295 /******************************************************************************/ 5296 /* */ 5297 /* Power Control */ 5298 /* */ 5299 /******************************************************************************/ 5300 5301 /******************** Bit definition for PWR_CR1 register ********************/ 5302 #define PWR_CR1_LPMS_Pos (0U) 5303 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */ 5304 #define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low Power Mode Selection for CPU1 */ 5305 #define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */ 5306 #define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */ 5307 #define PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */ 5308 5309 #define PWR_CR1_SUBGHZSPINSSSEL_Pos (3U) 5310 #define PWR_CR1_SUBGHZSPINSSSEL_Msk (0x1UL << PWR_CR1_SUBGHZSPINSSSEL_Pos) /*!< 0x00000008 */ 5311 #define PWR_CR1_SUBGHZSPINSSSEL PWR_CR1_SUBGHZSPINSSSEL_Msk /*!< Sub-GHz radio SPI NSS source select */ 5312 5313 #define PWR_CR1_FPDR_Pos (4U) 5314 #define PWR_CR1_FPDR_Msk (0x1UL << PWR_CR1_FPDR_Pos) /*!< 0x00000010 */ 5315 #define PWR_CR1_FPDR PWR_CR1_FPDR_Msk /*!< Flash power down mode during LPrun for CPU1 */ 5316 5317 #define PWR_CR1_FPDS_Pos (5U) 5318 #define PWR_CR1_FPDS_Msk (0x1UL << PWR_CR1_FPDS_Pos) /*!< 0x00000020 */ 5319 #define PWR_CR1_FPDS PWR_CR1_FPDS_Msk /*!< Flash power down mode during LPsleep for CPU1 */ 5320 5321 #define PWR_CR1_DBP_Pos (8U) 5322 #define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */ 5323 #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Backup Domain write protection */ 5324 5325 #define PWR_CR1_VOS_Pos (9U) 5326 #define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos) /*!< 0x00000600 */ 5327 #define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< Voltage scaling range selection */ 5328 #define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos) /*!< 0x00000200 */ 5329 #define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos) /*!< 0x00000400 */ 5330 5331 #define PWR_CR1_LPR_Pos (14U) 5332 #define PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos) /*!< 0x00004000 */ 5333 #define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator Low-Power Run mode */ 5334 5335 /******************** Bit definition for PWR_CR2 register ********************/ 5336 #define PWR_CR2_PVDE_Pos (0U) 5337 #define PWR_CR2_PVDE_Msk (0x1UL << PWR_CR2_PVDE_Pos) /*!< 0x00000001 */ 5338 #define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power voltage detector enable */ 5339 5340 #define PWR_CR2_PLS_Pos (1U) 5341 #define PWR_CR2_PLS_Msk (0x7UL << PWR_CR2_PLS_Pos) /*!< 0x0000000E */ 5342 #define PWR_CR2_PLS PWR_CR2_PLS_Msk /*!< Power voltage detector level selection */ 5343 #define PWR_CR2_PLS_0 (0x1UL << PWR_CR2_PLS_Pos) /*!< 0x00000002 */ 5344 #define PWR_CR2_PLS_1 (0x2UL << PWR_CR2_PLS_Pos) /*!< 0x00000004 */ 5345 #define PWR_CR2_PLS_2 (0x4UL << PWR_CR2_PLS_Pos) /*!< 0x00000008 */ 5346 5347 #define PWR_CR2_PVME3_Pos (6U) 5348 #define PWR_CR2_PVME3_Msk (0x1UL << PWR_CR2_PVME3_Pos) /*!< 0x00000040 */ 5349 #define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk /*!< Peripherical Voltage Monitor Vdda Enable */ 5350 5351 /******************** Bit definition for PWR_CR3 register ********************/ 5352 #define PWR_CR3_EWUP_Pos (0U) 5353 #define PWR_CR3_EWUP_Msk (0x07UL << PWR_CR3_EWUP_Pos) /*!< 0x00000007 */ 5354 #define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable all external Wake-Up lines */ 5355 #define PWR_CR3_EWUP1_Pos (0U) 5356 #define PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */ 5357 #define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable external WKUP Pin 1 [line 0] */ 5358 #define PWR_CR3_EWUP2_Pos (1U) 5359 #define PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */ 5360 #define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable external WKUP Pin 2 [line 1] */ 5361 #define PWR_CR3_EWUP3_Pos (2U) 5362 #define PWR_CR3_EWUP3_Msk (0x1UL << PWR_CR3_EWUP3_Pos) /*!< 0x00000004 */ 5363 #define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk /*!< Enable external WKUP Pin 3 [line 2] */ 5364 5365 #define PWR_CR3_ULPEN_Pos (7U) 5366 #define PWR_CR3_ULPEN_Msk (0x1UL << PWR_CR3_ULPEN_Pos) /*!< 0x00000080 */ 5367 #define PWR_CR3_ULPEN PWR_CR3_ULPEN_Msk /*!< Enable periodical sampling of supply voltage in Stop and Standby modes for detecting condition of PDR and BOR reset */ 5368 5369 #define PWR_CR3_EWPVD_Pos (8U) 5370 #define PWR_CR3_EWPVD_Msk (0x1UL << PWR_CR3_EWPVD_Pos) /*!< 0x00000100 */ 5371 #define PWR_CR3_EWPVD PWR_CR3_EWPVD_Msk /*!< Enable wakeup PVD for CPU1 */ 5372 5373 #define PWR_CR3_RRS_Pos (9U) 5374 #define PWR_CR3_RRS_Msk (0x1UL << PWR_CR3_RRS_Pos) /*!< 0x00000200 */ 5375 #define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 retention in STANDBY mode */ 5376 5377 #define PWR_CR3_APC_Pos (10U) 5378 #define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos) /*!< 0x00000400 */ 5379 #define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration for CPU1 */ 5380 5381 #define PWR_CR3_EWRFBUSY_Pos (11U) 5382 #define PWR_CR3_EWRFBUSY_Msk (0x1UL << PWR_CR3_EWRFBUSY_Pos) /*!< 0x00008000 */ 5383 #define PWR_CR3_EWRFBUSY PWR_CR3_EWRFBUSY_Msk /*!< Enable Radio busy IRQ and wake-up for CPU1 */ 5384 #define PWR_CR3_EWRFIRQ_Pos (13U) 5385 #define PWR_CR3_EWRFIRQ_Msk (0x1UL << PWR_CR3_EWRFIRQ_Pos) /*!< 0x00020000 */ 5386 #define PWR_CR3_EWRFIRQ PWR_CR3_EWRFIRQ_Msk /*!< Enable Radio IRQ[2:0] and wake-up for CPU1 */ 5387 5388 #define PWR_CR3_EIWUL_Pos (15U) 5389 #define PWR_CR3_EIWUL_Msk (0x1UL << PWR_CR3_EIWUL_Pos) /*!< 0x00080000 */ 5390 #define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Internal Wake-Up line interrupt for CPU1 */ 5391 5392 /******************** Bit definition for PWR_CR4 register ********************/ 5393 #define PWR_CR4_WP1_Pos (0U) 5394 #define PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos) /*!< 0x00000001 */ 5395 #define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 [line 0] polarity */ 5396 #define PWR_CR4_WP2_Pos (1U) 5397 #define PWR_CR4_WP2_Msk (0x1UL << PWR_CR4_WP2_Pos) /*!< 0x00000002 */ 5398 #define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 [line 1] polarity */ 5399 #define PWR_CR4_WP3_Pos (2U) 5400 #define PWR_CR4_WP3_Msk (0x1UL << PWR_CR4_WP3_Pos) /*!< 0x00000004 */ 5401 #define PWR_CR4_WP3 PWR_CR4_WP3_Msk /*!< Wake-Up Pin 3 [line 2] polarity */ 5402 5403 #define PWR_CR4_VBE_Pos (8U) 5404 #define PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos) /*!< 0x00000100 */ 5405 #define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT battery charging enable */ 5406 #define PWR_CR4_VBRS_Pos (9U) 5407 #define PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */ 5408 #define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT battery charging resistor selection */ 5409 5410 #define PWR_CR4_WRFBUSYP_Pos (11U) 5411 #define PWR_CR4_WRFBUSYP_Msk (0x1UL << PWR_CR4_WRFBUSYP_Pos) /*!< 0x00008000 */ 5412 #define PWR_CR4_WRFBUSYP PWR_CR4_WRFBUSYP_Msk /*!< Wake-up radio busy polarity */ 5413 5414 /******************** Bit definition for PWR_SR1 register ********************/ 5415 #define PWR_SR1_WUF_Pos (0U) 5416 #define PWR_SR1_WUF_Msk (0x1FUL << PWR_SR1_WUF_Pos) /*!< 0x00000007 */ 5417 #define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wakeup Flags of all pins */ 5418 #define PWR_SR1_WUF1_Pos (0U) 5419 #define PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */ 5420 #define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wakeup Pin 1 [Flag 0] */ 5421 #define PWR_SR1_WUF2_Pos (1U) 5422 #define PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */ 5423 #define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wakeup Pin 2 [Flag 1] */ 5424 #define PWR_SR1_WUF3_Pos (2U) 5425 #define PWR_SR1_WUF3_Msk (0x1UL << PWR_SR1_WUF3_Pos) /*!< 0x00000004 */ 5426 #define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk /*!< Wakeup Pin 3 [Flag 2] */ 5427 5428 #define PWR_SR1_WPVDF_Pos (8U) 5429 #define PWR_SR1_WPVDF_Msk (0x1UL << PWR_SR1_WPVDF_Pos) /*!< 0x00000100 */ 5430 #define PWR_SR1_WPVDF PWR_SR1_WPVDF_Msk /*!< Wakeup PVD flag */ 5431 5432 #define PWR_SR1_WRFBUSYF_Pos (11U) 5433 #define PWR_SR1_WRFBUSYF_Msk (0x1UL << PWR_SR1_WRFBUSYF_Pos) /*!< 0x00000800 */ 5434 #define PWR_SR1_WRFBUSYF PWR_SR1_WRFBUSYF_Msk /*!< Wakeup radio busy flag */ 5435 5436 #define PWR_SR1_WUFI_Pos (15U) 5437 #define PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */ 5438 #define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Internal wakeup interrupt flag */ 5439 5440 /******************** Bit definition for PWR_SR2 register ********************/ 5441 #define PWR_SR2_RFBUSYS_Pos (1U) 5442 #define PWR_SR2_RFBUSYS_Msk (0x1UL << PWR_SR2_RFBUSYS_Pos) /*!< 0x00000002 */ 5443 #define PWR_SR2_RFBUSYS PWR_SR2_RFBUSYS_Msk /*!< Radio busy signal status */ 5444 5445 #define PWR_SR2_RFBUSYMS_Pos (2U) 5446 #define PWR_SR2_RFBUSYMS_Msk (0x1UL << PWR_SR2_RFBUSYMS_Pos) /*!< 0x00000004 */ 5447 #define PWR_SR2_RFBUSYMS PWR_SR2_RFBUSYMS_Msk /*!< Radio busy masked signal status */ 5448 5449 #define PWR_SR2_SMPSRDY_Pos (3U) 5450 #define PWR_SR2_SMPSRDY_Msk (0x1UL << PWR_SR2_SMPSRDY_Pos) /*!< 0x00000008 */ 5451 #define PWR_SR2_SMPSRDY PWR_SR2_SMPSRDY_Msk /*!< SMPS ready flag */ 5452 #define PWR_SR2_LDORDY_Pos (4U) 5453 #define PWR_SR2_LDORDY_Msk (0x1UL << PWR_SR2_LDORDY_Pos) /*!< 0x00000010 */ 5454 #define PWR_SR2_LDORDY PWR_SR2_LDORDY_Msk /*!< LDO ready flag */ 5455 5456 #define PWR_SR2_RFEOLF_Pos (5U) 5457 #define PWR_SR2_RFEOLF_Msk (0x1UL << PWR_SR2_RFEOLF_Pos) /*!< 0x00000020 */ 5458 #define PWR_SR2_RFEOLF PWR_SR2_RFEOLF_Msk /*!< Radio end of life flag */ 5459 5460 #define PWR_SR2_REGMRS_Pos (6U) 5461 #define PWR_SR2_REGMRS_Msk (0x1UL << PWR_SR2_REGMRS_Pos) /*!< 0x00000040 */ 5462 #define PWR_SR2_REGMRS PWR_SR2_REGMRS_Msk /*!< Main regulator status */ 5463 5464 #define PWR_SR2_FLASHRDY_Pos (7U) 5465 #define PWR_SR2_FLASHRDY_Msk (0x1UL << PWR_SR2_FLASHRDY_Pos) /*!< 0x00000080 */ 5466 #define PWR_SR2_FLASHRDY PWR_SR2_FLASHRDY_Msk /*!< Flash ready */ 5467 5468 #define PWR_SR2_REGLPS_Pos (8U) 5469 #define PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */ 5470 #define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power regulator ready */ 5471 #define PWR_SR2_REGLPF_Pos (9U) 5472 #define PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */ 5473 #define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power regulator being used */ 5474 5475 #define PWR_SR2_VOSF_Pos (10U) 5476 #define PWR_SR2_VOSF_Msk (0x1UL << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */ 5477 #define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage scaling flag */ 5478 #define PWR_SR2_PVDO_Pos (11U) 5479 #define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */ 5480 #define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power voltage detector output */ 5481 5482 #define PWR_SR2_PVMO3_Pos (14U) 5483 #define PWR_SR2_PVMO3_Msk (0x1UL << PWR_SR2_PVMO3_Pos) /*!< 0x00004000 */ 5484 #define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk /*!< Peripheral voltage monitor output 3: VDDA vs. 1.62V */ 5485 5486 /******************** Bit definition for PWR_SCR register ********************/ 5487 #define PWR_SCR_CWUF_Pos (0U) 5488 #define PWR_SCR_CWUF_Msk (0x7UL << PWR_SCR_CWUF_Pos) /*!< 0x00000007 */ 5489 #define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags for all pins */ 5490 #define PWR_SCR_CWUF1_Pos (0U) 5491 #define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */ 5492 #define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Pin 1 [Flag 0] */ 5493 #define PWR_SCR_CWUF2_Pos (1U) 5494 #define PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */ 5495 #define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Pin 2 [Flag 1] */ 5496 #define PWR_SCR_CWUF3_Pos (2U) 5497 #define PWR_SCR_CWUF3_Msk (0x1UL << PWR_SCR_CWUF3_Pos) /*!< 0x00000004 */ 5498 #define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk /*!< Clear Wake-up Pin 3 [Flag 2] */ 5499 5500 #define PWR_SCR_CWPVDF_Pos (8U) 5501 #define PWR_SCR_CWPVDF_Msk (0x1UL << PWR_SCR_CWPVDF_Pos) /*!< 0x00000100 */ 5502 #define PWR_SCR_CWPVDF PWR_SCR_CWPVDF_Msk /*!< Clear wakeup PVD interrupt flag */ 5503 5504 #define PWR_SCR_CWRFBUSYF_Pos (11U) 5505 #define PWR_SCR_CWRFBUSYF_Msk (0x1UL << PWR_SCR_CWRFBUSYF_Pos) /*!< 0x00000800 */ 5506 #define PWR_SCR_CWRFBUSYF PWR_SCR_CWRFBUSYF_Msk /*!< Clear Radio busy interrupt flag */ 5507 5508 /******************** Bit definition for PWR_CR5 register ********************/ 5509 #define PWR_CR5_RFEOLEN_Pos (14U) 5510 #define PWR_CR5_RFEOLEN_Msk (0x1UL << PWR_CR5_RFEOLEN_Pos) /*!< 0x00004000 */ 5511 #define PWR_CR5_RFEOLEN PWR_CR5_RFEOLEN_Msk /*!< Enable Radio End Of Life detector enabled */ 5512 5513 #define PWR_CR5_SMPSEN_Pos (15U) 5514 #define PWR_CR5_SMPSEN_Msk (0x1UL << PWR_CR5_SMPSEN_Pos) /*!< 0x00008000 */ 5515 #define PWR_CR5_SMPSEN PWR_CR5_SMPSEN_Msk /*!< Enable SMPS Step Down converter SMPS mode enable */ 5516 5517 /******************** Bit definition for PWR_PUCRA register *****************/ 5518 #define PWR_PUCRA_PA0_Pos (0U) 5519 #define PWR_PUCRA_PA0_Msk (0x1UL << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */ 5520 #define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Pin PA0 Pull-Up set */ 5521 #define PWR_PUCRA_PA1_Pos (1U) 5522 #define PWR_PUCRA_PA1_Msk (0x1UL << PWR_PUCRA_PA1_Pos) /*!< 0x00000002 */ 5523 #define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Pin PA1 Pull-Up set */ 5524 #define PWR_PUCRA_PA2_Pos (2U) 5525 #define PWR_PUCRA_PA2_Msk (0x1UL << PWR_PUCRA_PA2_Pos) /*!< 0x00000004 */ 5526 #define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Pin PA2 Pull-Up set */ 5527 #define PWR_PUCRA_PA3_Pos (3U) 5528 #define PWR_PUCRA_PA3_Msk (0x1UL << PWR_PUCRA_PA3_Pos) /*!< 0x00000008 */ 5529 #define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Pin PA3 Pull-Up set */ 5530 #define PWR_PUCRA_PA4_Pos (4U) 5531 #define PWR_PUCRA_PA4_Msk (0x1UL << PWR_PUCRA_PA4_Pos) /*!< 0x00000010 */ 5532 #define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Pin PA4 Pull-Up set */ 5533 #define PWR_PUCRA_PA5_Pos (5U) 5534 #define PWR_PUCRA_PA5_Msk (0x1UL << PWR_PUCRA_PA5_Pos) /*!< 0x00000020 */ 5535 #define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Pin PA5 Pull-Up set */ 5536 #define PWR_PUCRA_PA6_Pos (6U) 5537 #define PWR_PUCRA_PA6_Msk (0x1UL << PWR_PUCRA_PA6_Pos) /*!< 0x00000040 */ 5538 #define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Pin PA6 Pull-Up set */ 5539 #define PWR_PUCRA_PA7_Pos (7U) 5540 #define PWR_PUCRA_PA7_Msk (0x1UL << PWR_PUCRA_PA7_Pos) /*!< 0x00000080 */ 5541 #define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Pin PA7 Pull-Up set */ 5542 #define PWR_PUCRA_PA8_Pos (8U) 5543 #define PWR_PUCRA_PA8_Msk (0x1UL << PWR_PUCRA_PA8_Pos) /*!< 0x00000100 */ 5544 #define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Pin PA8 Pull-Up set */ 5545 #define PWR_PUCRA_PA9_Pos (9U) 5546 #define PWR_PUCRA_PA9_Msk (0x1UL << PWR_PUCRA_PA9_Pos) /*!< 0x00000200 */ 5547 #define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Pin PA9 Pull-Up set */ 5548 #define PWR_PUCRA_PA10_Pos (10U) 5549 #define PWR_PUCRA_PA10_Msk (0x1UL << PWR_PUCRA_PA10_Pos) /*!< 0x00000400 */ 5550 #define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Pin PA10 Pull-Up set */ 5551 #define PWR_PUCRA_PA11_Pos (11U) 5552 #define PWR_PUCRA_PA11_Msk (0x1UL << PWR_PUCRA_PA11_Pos) /*!< 0x00000800 */ 5553 #define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Pin PA11 Pull-Up set */ 5554 #define PWR_PUCRA_PA12_Pos (12U) 5555 #define PWR_PUCRA_PA12_Msk (0x1UL << PWR_PUCRA_PA12_Pos) /*!< 0x00001000 */ 5556 #define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Pin PA12 Pull-Up set */ 5557 #define PWR_PUCRA_PA13_Pos (13U) 5558 #define PWR_PUCRA_PA13_Msk (0x1UL << PWR_PUCRA_PA13_Pos) /*!< 0x00002000 */ 5559 #define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Pin PA13 Pull-Up set */ 5560 #define PWR_PUCRA_PA14_Pos (14U) 5561 #define PWR_PUCRA_PA14_Msk (0x1UL << PWR_PUCRA_PA14_Pos) /*!< 0x00004000 */ 5562 #define PWR_PUCRA_PA14 PWR_PUCRA_PA14_Msk /*!< Pin PA14 Pull-Up set */ 5563 #define PWR_PUCRA_PA15_Pos (15U) 5564 #define PWR_PUCRA_PA15_Msk (0x1UL << PWR_PUCRA_PA15_Pos) /*!< 0x00008000 */ 5565 #define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Pin PA15 Pull-Up set */ 5566 5567 /******************** Bit definition for PWR_PDCRA register *****************/ 5568 #define PWR_PDCRA_PA0_Pos (0U) 5569 #define PWR_PDCRA_PA0_Msk (0x1UL << PWR_PDCRA_PA0_Pos) /*!< 0x00000001 */ 5570 #define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Pin PA0 Pull-Down set */ 5571 #define PWR_PDCRA_PA1_Pos (1U) 5572 #define PWR_PDCRA_PA1_Msk (0x1UL << PWR_PDCRA_PA1_Pos) /*!< 0x00000002 */ 5573 #define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Pin PA1 Pull-Down set */ 5574 #define PWR_PDCRA_PA2_Pos (2U) 5575 #define PWR_PDCRA_PA2_Msk (0x1UL << PWR_PDCRA_PA2_Pos) /*!< 0x00000004 */ 5576 #define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Pin PA2 Pull-Down set */ 5577 #define PWR_PDCRA_PA3_Pos (3U) 5578 #define PWR_PDCRA_PA3_Msk (0x1UL << PWR_PDCRA_PA3_Pos) /*!< 0x00000008 */ 5579 #define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Pin PA3 Pull-Down set */ 5580 #define PWR_PDCRA_PA4_Pos (4U) 5581 #define PWR_PDCRA_PA4_Msk (0x1UL << PWR_PDCRA_PA4_Pos) /*!< 0x00000010 */ 5582 #define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Pin PA4 Pull-Down set */ 5583 #define PWR_PDCRA_PA5_Pos (5U) 5584 #define PWR_PDCRA_PA5_Msk (0x1UL << PWR_PDCRA_PA5_Pos) /*!< 0x00000020 */ 5585 #define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Pin PA5 Pull-Down set */ 5586 #define PWR_PDCRA_PA6_Pos (6U) 5587 #define PWR_PDCRA_PA6_Msk (0x1UL << PWR_PDCRA_PA6_Pos) /*!< 0x00000040 */ 5588 #define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Pin PA6 Pull-Down set */ 5589 #define PWR_PDCRA_PA7_Pos (7U) 5590 #define PWR_PDCRA_PA7_Msk (0x1UL << PWR_PDCRA_PA7_Pos) /*!< 0x00000080 */ 5591 #define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Pin PA7 Pull-Down set */ 5592 #define PWR_PDCRA_PA8_Pos (8U) 5593 #define PWR_PDCRA_PA8_Msk (0x1UL << PWR_PDCRA_PA8_Pos) /*!< 0x00000100 */ 5594 #define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Pin PA8 Pull-Down set */ 5595 #define PWR_PDCRA_PA9_Pos (9U) 5596 #define PWR_PDCRA_PA9_Msk (0x1UL << PWR_PDCRA_PA9_Pos) /*!< 0x00000200 */ 5597 #define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Pin PA9 Pull-Down set */ 5598 #define PWR_PDCRA_PA10_Pos (10U) 5599 #define PWR_PDCRA_PA10_Msk (0x1UL << PWR_PDCRA_PA10_Pos) /*!< 0x00000400 */ 5600 #define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Pin PA10 Pull-Down set */ 5601 #define PWR_PDCRA_PA11_Pos (11U) 5602 #define PWR_PDCRA_PA11_Msk (0x1UL << PWR_PDCRA_PA11_Pos) /*!< 0x00000800 */ 5603 #define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Pin PA11 Pull-Down set */ 5604 #define PWR_PDCRA_PA12_Pos (12U) 5605 #define PWR_PDCRA_PA12_Msk (0x1UL << PWR_PDCRA_PA12_Pos) /*!< 0x00001000 */ 5606 #define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Pin PA12 Pull-Down set */ 5607 #define PWR_PDCRA_PA13_Pos (13U) 5608 #define PWR_PDCRA_PA13_Msk (0x1UL << PWR_PDCRA_PA13_Pos) /*!< 0x00002000 */ 5609 #define PWR_PDCRA_PA13 PWR_PDCRA_PA13_Msk /*!< Pin PA13 Pull-Down set */ 5610 #define PWR_PDCRA_PA14_Pos (14U) 5611 #define PWR_PDCRA_PA14_Msk (0x1UL << PWR_PDCRA_PA14_Pos) /*!< 0x00004000 */ 5612 #define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Pin PA14 Pull-Down set */ 5613 #define PWR_PDCRA_PA15_Pos (15U) 5614 #define PWR_PDCRA_PA15_Msk (0x1UL << PWR_PDCRA_PA15_Pos) /*!< 0x00008000 */ 5615 #define PWR_PDCRA_PA15 PWR_PDCRA_PA15_Msk /*!< Pin PA15 Pull-Down set */ 5616 5617 /******************** Bit definition for PWR_PUCRB register *****************/ 5618 #define PWR_PUCRB_PB0_Pos (0U) 5619 #define PWR_PUCRB_PB0_Msk (0x1UL << PWR_PUCRB_PB0_Pos) /*!< 0x00000001 */ 5620 #define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Pin PB0 Pull-Up set */ 5621 #define PWR_PUCRB_PB1_Pos (1U) 5622 #define PWR_PUCRB_PB1_Msk (0x1UL << PWR_PUCRB_PB1_Pos) /*!< 0x00000002 */ 5623 #define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Pin PB1 Pull-Up set */ 5624 #define PWR_PUCRB_PB2_Pos (2U) 5625 #define PWR_PUCRB_PB2_Msk (0x1UL << PWR_PUCRB_PB2_Pos) /*!< 0x00000004 */ 5626 #define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk /*!< Pin PB2 Pull-Up set */ 5627 #define PWR_PUCRB_PB3_Pos (3U) 5628 #define PWR_PUCRB_PB3_Msk (0x1UL << PWR_PUCRB_PB3_Pos) /*!< 0x00000008 */ 5629 #define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Pin PB3 Pull-Up set */ 5630 #define PWR_PUCRB_PB4_Pos (4U) 5631 #define PWR_PUCRB_PB4_Msk (0x1UL << PWR_PUCRB_PB4_Pos) /*!< 0x00000010 */ 5632 #define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Pin PB4 Pull-Up set */ 5633 #define PWR_PUCRB_PB5_Pos (5U) 5634 #define PWR_PUCRB_PB5_Msk (0x1UL << PWR_PUCRB_PB5_Pos) /*!< 0x00000020 */ 5635 #define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Pin PB5 Pull-Up set */ 5636 #define PWR_PUCRB_PB6_Pos (6U) 5637 #define PWR_PUCRB_PB6_Msk (0x1UL << PWR_PUCRB_PB6_Pos) /*!< 0x00000040 */ 5638 #define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Pin PB6 Pull-Up set */ 5639 #define PWR_PUCRB_PB7_Pos (7U) 5640 #define PWR_PUCRB_PB7_Msk (0x1UL << PWR_PUCRB_PB7_Pos) /*!< 0x00000080 */ 5641 #define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Pin PB7 Pull-Up set */ 5642 #define PWR_PUCRB_PB8_Pos (8U) 5643 #define PWR_PUCRB_PB8_Msk (0x1UL << PWR_PUCRB_PB8_Pos) /*!< 0x00000100 */ 5644 #define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk /*!< Pin PB8 Pull-Up set */ 5645 #define PWR_PUCRB_PB9_Pos (9U) 5646 #define PWR_PUCRB_PB9_Msk (0x1UL << PWR_PUCRB_PB9_Pos) /*!< 0x00000200 */ 5647 #define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk /*!< Pin PB9 Pull-Up set */ 5648 #define PWR_PUCRB_PB10_Pos (10U) 5649 #define PWR_PUCRB_PB10_Msk (0x1UL << PWR_PUCRB_PB10_Pos) /*!< 0x00000400 */ 5650 #define PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk /*!< Pin PB10 Pull-Up set */ 5651 #define PWR_PUCRB_PB11_Pos (11U) 5652 #define PWR_PUCRB_PB11_Msk (0x1UL << PWR_PUCRB_PB11_Pos) /*!< 0x00000800 */ 5653 #define PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk /*!< Pin PB11 Pull-Up set */ 5654 #define PWR_PUCRB_PB12_Pos (12U) 5655 #define PWR_PUCRB_PB12_Msk (0x1UL << PWR_PUCRB_PB12_Pos) /*!< 0x00001000 */ 5656 #define PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk /*!< Pin PB12 Pull-Up set */ 5657 #define PWR_PUCRB_PB13_Pos (13U) 5658 #define PWR_PUCRB_PB13_Msk (0x1UL << PWR_PUCRB_PB13_Pos) /*!< 0x00002000 */ 5659 #define PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk /*!< Pin PB13 Pull-Up set */ 5660 #define PWR_PUCRB_PB14_Pos (14U) 5661 #define PWR_PUCRB_PB14_Msk (0x1UL << PWR_PUCRB_PB14_Pos) /*!< 0x00004000 */ 5662 #define PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk /*!< Pin PB14 Pull-Up set */ 5663 #define PWR_PUCRB_PB15_Pos (15U) 5664 #define PWR_PUCRB_PB15_Msk (0x1UL << PWR_PUCRB_PB15_Pos) /*!< 0x00008000 */ 5665 #define PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk /*!< Pin PB15 Pull-Up set */ 5666 5667 /******************** Bit definition for PWR_PDCRB register *****************/ 5668 #define PWR_PDCRB_PB0_Pos (0U) 5669 #define PWR_PDCRB_PB0_Msk (0x1UL << PWR_PDCRB_PB0_Pos) /*!< 0x00000001 */ 5670 #define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Pin PB0 Pull-Down set */ 5671 #define PWR_PDCRB_PB1_Pos (1U) 5672 #define PWR_PDCRB_PB1_Msk (0x1UL << PWR_PDCRB_PB1_Pos) /*!< 0x00000002 */ 5673 #define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Pin PB1 Pull-Down set */ 5674 #define PWR_PDCRB_PB2_Pos (2U) 5675 #define PWR_PDCRB_PB2_Msk (0x1UL << PWR_PDCRB_PB2_Pos) /*!< 0x00000004 */ 5676 #define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk /*!< Pin PB2 Pull-Down set */ 5677 #define PWR_PDCRB_PB3_Pos (3U) 5678 #define PWR_PDCRB_PB3_Msk (0x1UL << PWR_PDCRB_PB3_Pos) /*!< 0x00000008 */ 5679 #define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Pin PB3 Pull-Down set */ 5680 #define PWR_PDCRB_PB4_Pos (4U) 5681 #define PWR_PDCRB_PB4_Msk (0x1UL << PWR_PDCRB_PB4_Pos) /*!< 0x00000010 */ 5682 #define PWR_PDCRB_PB4 PWR_PDCRB_PB4_Msk /*!< Pin PB4 Pull-Down set */ 5683 #define PWR_PDCRB_PB5_Pos (5U) 5684 #define PWR_PDCRB_PB5_Msk (0x1UL << PWR_PDCRB_PB5_Pos) /*!< 0x00000020 */ 5685 #define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Pin PB5 Pull-Down set */ 5686 #define PWR_PDCRB_PB6_Pos (6U) 5687 #define PWR_PDCRB_PB6_Msk (0x1UL << PWR_PDCRB_PB6_Pos) /*!< 0x00000040 */ 5688 #define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Pin PB6 Pull-Down set */ 5689 #define PWR_PDCRB_PB7_Pos (7U) 5690 #define PWR_PDCRB_PB7_Msk (0x1UL << PWR_PDCRB_PB7_Pos) /*!< 0x00000080 */ 5691 #define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Pin PB7 Pull-Down set */ 5692 #define PWR_PDCRB_PB8_Pos (8U) 5693 #define PWR_PDCRB_PB8_Msk (0x1UL << PWR_PDCRB_PB8_Pos) /*!< 0x00000100 */ 5694 #define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk /*!< Pin PB8 Pull-Down set */ 5695 #define PWR_PDCRB_PB9_Pos (9U) 5696 #define PWR_PDCRB_PB9_Msk (0x1UL << PWR_PDCRB_PB9_Pos) /*!< 0x00000200 */ 5697 #define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk /*!< Pin PB9 Pull-Down set */ 5698 #define PWR_PDCRB_PB10_Pos (10U) 5699 #define PWR_PDCRB_PB10_Msk (0x1UL << PWR_PDCRB_PB10_Pos) /*!< 0x00000400 */ 5700 #define PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk /*!< Pin PB10 Pull-Down set */ 5701 #define PWR_PDCRB_PB11_Pos (11U) 5702 #define PWR_PDCRB_PB11_Msk (0x1UL << PWR_PDCRB_PB11_Pos) /*!< 0x00000800 */ 5703 #define PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk /*!< Pin PB11 Pull-Down set */ 5704 #define PWR_PDCRB_PB12_Pos (12U) 5705 #define PWR_PDCRB_PB12_Msk (0x1UL << PWR_PDCRB_PB12_Pos) /*!< 0x00001000 */ 5706 #define PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk /*!< Pin PB12 Pull-Down set */ 5707 #define PWR_PDCRB_PB13_Pos (13U) 5708 #define PWR_PDCRB_PB13_Msk (0x1UL << PWR_PDCRB_PB13_Pos) /*!< 0x00002000 */ 5709 #define PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk /*!< Pin PB13 Pull-Down set */ 5710 #define PWR_PDCRB_PB14_Pos (14U) 5711 #define PWR_PDCRB_PB14_Msk (0x1UL << PWR_PDCRB_PB14_Pos) /*!< 0x00004000 */ 5712 #define PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk /*!< Pin PB14 Pull-Down set */ 5713 #define PWR_PDCRB_PB15_Pos (15U) 5714 #define PWR_PDCRB_PB15_Msk (0x1UL << PWR_PDCRB_PB15_Pos) /*!< 0x00008000 */ 5715 #define PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk /*!< Pin PB15 Pull-Down set */ 5716 5717 /******************** Bit definition for PWR_PUCRC register *****************/ 5718 #define PWR_PUCRC_PC0_Pos (0U) 5719 #define PWR_PUCRC_PC0_Msk (0x1UL << PWR_PUCRC_PC0_Pos) /*!< 0x00000001 */ 5720 #define PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk /*!< Pin PC0 Pull-Up set */ 5721 #define PWR_PUCRC_PC1_Pos (1U) 5722 #define PWR_PUCRC_PC1_Msk (0x1UL << PWR_PUCRC_PC1_Pos) /*!< 0x00000002 */ 5723 #define PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk /*!< Pin PC1 Pull-Up set */ 5724 #define PWR_PUCRC_PC2_Pos (2U) 5725 #define PWR_PUCRC_PC2_Msk (0x1UL << PWR_PUCRC_PC2_Pos) /*!< 0x00000004 */ 5726 #define PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk /*!< Pin PC2 Pull-Up set */ 5727 #define PWR_PUCRC_PC3_Pos (3U) 5728 #define PWR_PUCRC_PC3_Msk (0x1UL << PWR_PUCRC_PC3_Pos) /*!< 0x00000008 */ 5729 #define PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk /*!< Pin PC3 Pull-Up set */ 5730 #define PWR_PUCRC_PC4_Pos (4U) 5731 #define PWR_PUCRC_PC4_Msk (0x1UL << PWR_PUCRC_PC4_Pos) /*!< 0x00000010 */ 5732 #define PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk /*!< Pin PC4 Pull-Up set */ 5733 #define PWR_PUCRC_PC5_Pos (5U) 5734 #define PWR_PUCRC_PC5_Msk (0x1UL << PWR_PUCRC_PC5_Pos) /*!< 0x00000020 */ 5735 #define PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk /*!< Pin PC5 Pull-Up set */ 5736 #define PWR_PUCRC_PC6_Pos (6U) 5737 #define PWR_PUCRC_PC6_Msk (0x1UL << PWR_PUCRC_PC6_Pos) /*!< 0x00000040 */ 5738 #define PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk /*!< Pin PC6 Pull-Up set */ 5739 #define PWR_PUCRC_PC13_Pos (13U) 5740 #define PWR_PUCRC_PC13_Msk (0x1UL << PWR_PUCRC_PC13_Pos) /*!< 0x00002000 */ 5741 #define PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk /*!< Pin PC13 Pull-Up set */ 5742 #define PWR_PUCRC_PC14_Pos (14U) 5743 #define PWR_PUCRC_PC14_Msk (0x1UL << PWR_PUCRC_PC14_Pos) /*!< 0x00004000 */ 5744 #define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Pin PC14 Pull-Up set */ 5745 #define PWR_PUCRC_PC15_Pos (15U) 5746 #define PWR_PUCRC_PC15_Msk (0x1UL << PWR_PUCRC_PC15_Pos) /*!< 0x00008000 */ 5747 #define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Pin PC15 Pull-Up set */ 5748 5749 /******************** Bit definition for PWR_PDCRC register *****************/ 5750 #define PWR_PDCRC_PC0_Pos (0U) 5751 #define PWR_PDCRC_PC0_Msk (0x1UL << PWR_PDCRC_PC0_Pos) /*!< 0x00000001 */ 5752 #define PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk /*!< Pin PC0 Pull-Down set */ 5753 #define PWR_PDCRC_PC1_Pos (1U) 5754 #define PWR_PDCRC_PC1_Msk (0x1UL << PWR_PDCRC_PC1_Pos) /*!< 0x00000002 */ 5755 #define PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk /*!< Pin PC1 Pull-Down set */ 5756 #define PWR_PDCRC_PC2_Pos (2U) 5757 #define PWR_PDCRC_PC2_Msk (0x1UL << PWR_PDCRC_PC2_Pos) /*!< 0x00000004 */ 5758 #define PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk /*!< Pin PC2 Pull-Down set */ 5759 #define PWR_PDCRC_PC3_Pos (3U) 5760 #define PWR_PDCRC_PC3_Msk (0x1UL << PWR_PDCRC_PC3_Pos) /*!< 0x00000008 */ 5761 #define PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk /*!< Pin PC3 Pull-Down set */ 5762 #define PWR_PDCRC_PC4_Pos (4U) 5763 #define PWR_PDCRC_PC4_Msk (0x1UL << PWR_PDCRC_PC4_Pos) /*!< 0x00000010 */ 5764 #define PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk /*!< Pin PC4 Pull-Down set */ 5765 #define PWR_PDCRC_PC5_Pos (5U) 5766 #define PWR_PDCRC_PC5_Msk (0x1UL << PWR_PDCRC_PC5_Pos) /*!< 0x00000020 */ 5767 #define PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk /*!< Pin PC5 Pull-Down set */ 5768 #define PWR_PDCRC_PC6_Pos (6U) 5769 #define PWR_PDCRC_PC6_Msk (0x1UL << PWR_PDCRC_PC6_Pos) /*!< 0x00000040 */ 5770 #define PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk /*!< Pin PC6 Pull-Down set */ 5771 #define PWR_PDCRC_PC13_Pos (13U) 5772 #define PWR_PDCRC_PC13_Msk (0x1UL << PWR_PDCRC_PC13_Pos) /*!< 0x00002000 */ 5773 #define PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk /*!< Pin PC13 Pull-Down set */ 5774 #define PWR_PDCRC_PC14_Pos (14U) 5775 #define PWR_PDCRC_PC14_Msk (0x1UL << PWR_PDCRC_PC14_Pos) /*!< 0x00004000 */ 5776 #define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Pin PC14 Pull-Down set */ 5777 #define PWR_PDCRC_PC15_Pos (15U) 5778 #define PWR_PDCRC_PC15_Msk (0x1UL << PWR_PDCRC_PC15_Pos) /*!< 0x00008000 */ 5779 #define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Pin PC15 Pull-Down set */ 5780 5781 /******************** Bit definition for PWR_PUCRH register *****************/ 5782 #define PWR_PUCRH_PH3_Pos (3U) 5783 #define PWR_PUCRH_PH3_Msk (0x1UL << PWR_PUCRH_PH3_Pos) /*!< 0x00000004 */ 5784 #define PWR_PUCRH_PH3 PWR_PUCRH_PH3_Msk /*!< Pin PH3 Pull-Up set */ 5785 5786 /******************** Bit definition for PWR_PDCRH register *****************/ 5787 #define PWR_PDCRH_PH3_Pos (3U) 5788 #define PWR_PDCRH_PH3_Msk (0x1UL << PWR_PDCRH_PH3_Pos) /*!< 0x00000004 */ 5789 #define PWR_PDCRH_PH3 PWR_PDCRH_PH3_Msk /*!< Pin PH3 Pull-Down set */ 5790 5791 /******************** Bit definition for PWR_EXTSCR register ********************/ 5792 #define PWR_EXTSCR_C1CSSF_Pos (0U) 5793 #define PWR_EXTSCR_C1CSSF_Msk (0x1UL << PWR_EXTSCR_C1CSSF_Pos) /*!< 0x00000001 */ 5794 #define PWR_EXTSCR_C1CSSF PWR_EXTSCR_C1CSSF_Msk /*!< Clear standby and stop flags for CPU1 */ 5795 5796 #define PWR_EXTSCR_C1SBF_Pos (8U) 5797 #define PWR_EXTSCR_C1SBF_Msk (0x1UL << PWR_EXTSCR_C1SBF_Pos) /*!< 0x00000100 */ 5798 #define PWR_EXTSCR_C1SBF PWR_EXTSCR_C1SBF_Msk /*!< System standby flag for CPU1 */ 5799 #define PWR_EXTSCR_C1STOP2F_Pos (9U) 5800 #define PWR_EXTSCR_C1STOP2F_Msk (0x1UL << PWR_EXTSCR_C1STOP2F_Pos) /*!< 0x00000200 */ 5801 #define PWR_EXTSCR_C1STOP2F PWR_EXTSCR_C1STOP2F_Msk /*!< System stop2 flag for CPU1 */ 5802 #define PWR_EXTSCR_C1STOPF_Pos (10U) 5803 #define PWR_EXTSCR_C1STOPF_Msk (0x1UL << PWR_EXTSCR_C1STOPF_Pos) /*!< 0x00000400 */ 5804 #define PWR_EXTSCR_C1STOPF PWR_EXTSCR_C1STOPF_Msk /*!< System stop0 or stop1 flag for CPU1 */ 5805 5806 #define PWR_EXTSCR_C1DS_Pos (14U) 5807 #define PWR_EXTSCR_C1DS_Msk (0x1UL << PWR_EXTSCR_C1DS_Pos) /*!< 0x00004000 */ 5808 #define PWR_EXTSCR_C1DS PWR_EXTSCR_C1DS_Msk /*!< CPU1 deepsleep mode flag */ 5809 5810 /******************** Bit definition for PWR_SUBGHZSPICR register ********************/ 5811 #define PWR_SUBGHZSPICR_NSS_Pos (15U) 5812 #define PWR_SUBGHZSPICR_NSS_Msk (0x1UL << PWR_SUBGHZSPICR_NSS_Pos) /*!< 0x00008000 */ 5813 #define PWR_SUBGHZSPICR_NSS PWR_SUBGHZSPICR_NSS_Msk /*!< Sub-GHz radio SUBGHZSPI_NSS control */ 5814 5815 /******************************************************************************/ 5816 /* */ 5817 /* Reset and Clock Control */ 5818 /* */ 5819 /******************************************************************************/ 5820 5821 /******************** Bit definition for RCC_CR register *****************/ 5822 #define RCC_CR_MSION_Pos (0U) 5823 #define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000001 */ 5824 #define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed oscillator (MSI) clock enable */ 5825 #define RCC_CR_MSIRDY_Pos (1U) 5826 #define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos) /*!< 0x00000002 */ 5827 #define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed oscillator (MSI) clock ready flag */ 5828 #define RCC_CR_MSIPLLEN_Pos (2U) 5829 #define RCC_CR_MSIPLLEN_Msk (0x1UL << RCC_CR_MSIPLLEN_Pos) /*!< 0x00000004 */ 5830 #define RCC_CR_MSIPLLEN RCC_CR_MSIPLLEN_Msk /*!< Internal Multi Speed oscillator (MSI) PLL enable */ 5831 #define RCC_CR_MSIRGSEL_Pos (3U) 5832 #define RCC_CR_MSIRGSEL_Msk (0x1UL << RCC_CR_MSIRGSEL_Pos) /*!< 0x00000008 */ 5833 #define RCC_CR_MSIRGSEL RCC_CR_MSIRGSEL_Msk /*!< Internal Multi Speed oscillator (MSI) range selection */ 5834 5835 /*!< MSIRANGE configuration : 12 frequency ranges available */ 5836 #define RCC_CR_MSIRANGE_Pos (4U) 5837 #define RCC_CR_MSIRANGE_Msk (0xFUL << RCC_CR_MSIRANGE_Pos) /*!< 0x000000F0 */ 5838 #define RCC_CR_MSIRANGE RCC_CR_MSIRANGE_Msk /*!< Internal Multi Speed oscillator (MSI) clock Range */ 5839 #define RCC_CR_MSIRANGE_0 (0x0UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000000 */ 5840 #define RCC_CR_MSIRANGE_1 (0x1UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000010 */ 5841 #define RCC_CR_MSIRANGE_2 (0x2UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000020 */ 5842 #define RCC_CR_MSIRANGE_3 (0x3UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000030 */ 5843 #define RCC_CR_MSIRANGE_4 (0x4UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000040 */ 5844 #define RCC_CR_MSIRANGE_5 (0x5UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000050 */ 5845 #define RCC_CR_MSIRANGE_6 (0x6UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000060 */ 5846 #define RCC_CR_MSIRANGE_7 (0x7UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000070 */ 5847 #define RCC_CR_MSIRANGE_8 (0x8UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000080 */ 5848 #define RCC_CR_MSIRANGE_9 (0x9UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000090 */ 5849 #define RCC_CR_MSIRANGE_10 (0xAUL << RCC_CR_MSIRANGE_Pos) /*!< 0x000000A0 */ 5850 #define RCC_CR_MSIRANGE_11 (0xBUL << RCC_CR_MSIRANGE_Pos) /*!< 0x000000B0 */ 5851 5852 #define RCC_CR_HSION_Pos (8U) 5853 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000100 */ 5854 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */ 5855 #define RCC_CR_HSIKERON_Pos (9U) 5856 #define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */ 5857 #define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */ 5858 #define RCC_CR_HSIRDY_Pos (10U) 5859 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */ 5860 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */ 5861 #define RCC_CR_HSIASFS_Pos (11U) 5862 #define RCC_CR_HSIASFS_Msk (0x1UL << RCC_CR_HSIASFS_Pos) /*!< 0x00000800 */ 5863 #define RCC_CR_HSIASFS RCC_CR_HSIASFS_Msk /*!< HSI16 Automatic Start from Stop */ 5864 #define RCC_CR_HSIKERDY_Pos (12U) 5865 #define RCC_CR_HSIKERDY_Msk (0x1UL << RCC_CR_HSIKERDY_Pos) /*!< 0x00001000 */ 5866 #define RCC_CR_HSIKERDY RCC_CR_HSIKERDY_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel ready flag*/ 5867 5868 #define RCC_CR_HSEON_Pos (16U) 5869 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ 5870 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */ 5871 #define RCC_CR_HSERDY_Pos (17U) 5872 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ 5873 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */ 5874 #define RCC_CR_CSSON_Pos (19U) 5875 #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ 5876 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */ 5877 #define RCC_CR_HSEPRE_Pos (20U) 5878 #define RCC_CR_HSEPRE_Msk (0x1UL << RCC_CR_HSEPRE_Pos) /*!< 0x00100000 */ 5879 #define RCC_CR_HSEPRE RCC_CR_HSEPRE_Msk /*!< HSE sysclk prescaler */ 5880 #define RCC_CR_HSEBYPPWR_Pos (21U) 5881 #define RCC_CR_HSEBYPPWR_Msk (0x1UL << RCC_CR_HSEBYPPWR_Pos) /*!< 0x00200000 */ 5882 #define RCC_CR_HSEBYPPWR RCC_CR_HSEBYPPWR_Msk /*!< Enable HSE32 VDDTCXO */ 5883 5884 #define RCC_CR_PLLON_Pos (24U) 5885 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ 5886 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */ 5887 #define RCC_CR_PLLRDY_Pos (25U) 5888 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ 5889 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */ 5890 5891 /******************** Bit definition for RCC_ICSCR register ***************/ 5892 /*!< MSICAL configuration */ 5893 #define RCC_ICSCR_MSICAL_Pos (0U) 5894 #define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos) /*!< 0x000000FF */ 5895 #define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< MSICAL[7:0] bits */ 5896 5897 /*!< MSITRIM configuration */ 5898 #define RCC_ICSCR_MSITRIM_Pos (8U) 5899 #define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */ 5900 #define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< MSITRIM[7:0] bits */ 5901 5902 /*!< HSICAL configuration */ 5903 #define RCC_ICSCR_HSICAL_Pos (16U) 5904 #define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00FF0000 */ 5905 #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */ 5906 5907 /*!< HSITRIM configuration */ 5908 #define RCC_ICSCR_HSITRIM_Pos (24U) 5909 #define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */ 5910 #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */ 5911 5912 /******************** Bit definition for RCC_CFGR register ******************/ 5913 /*!< SW configuration */ 5914 #define RCC_CFGR_SW_Pos (0U) 5915 #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ 5916 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ 5917 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ 5918 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ 5919 5920 /*!< SWS configuration */ 5921 #define RCC_CFGR_SWS_Pos (2U) 5922 #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ 5923 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ 5924 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ 5925 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ 5926 5927 /*!< HPRE configuration */ 5928 #define RCC_CFGR_HPRE_Pos (4U) 5929 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ 5930 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ 5931 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ 5932 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ 5933 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ 5934 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ 5935 5936 /*!< PPRE1 configuration */ 5937 #define RCC_CFGR_PPRE1_Pos (8U) 5938 #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ 5939 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ 5940 #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ 5941 #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ 5942 #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ 5943 5944 /*!< PPRE2 configuration */ 5945 #define RCC_CFGR_PPRE2_Pos (11U) 5946 #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ 5947 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ 5948 #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ 5949 #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ 5950 #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ 5951 5952 /*!< STOPWUCK configuration */ 5953 #define RCC_CFGR_STOPWUCK_Pos (15U) 5954 #define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */ 5955 #define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */ 5956 5957 /*!< HPREF configuration */ 5958 #define RCC_CFGR_HPREF_Pos (16U) 5959 #define RCC_CFGR_HPREF_Msk (0x1UL << RCC_CFGR_HPREF_Pos) /*!< 0x00010000 */ 5960 #define RCC_CFGR_HPREF RCC_CFGR_HPREF_Msk /*!< AHB prescaler flag */ 5961 5962 /*!< PPRE1F configuration */ 5963 #define RCC_CFGR_PPRE1F_Pos (17U) 5964 #define RCC_CFGR_PPRE1F_Msk (0x1UL << RCC_CFGR_PPRE1F_Pos) /*!< 0x00020000 */ 5965 #define RCC_CFGR_PPRE1F RCC_CFGR_PPRE1F_Msk /*!< CPU1 APB1 prescaler flag */ 5966 5967 /*!< PPRE2F configuration */ 5968 #define RCC_CFGR_PPRE2F_Pos (18U) 5969 #define RCC_CFGR_PPRE2F_Msk (0x1UL << RCC_CFGR_PPRE2F_Pos) /*!< 0x00040000 */ 5970 #define RCC_CFGR_PPRE2F RCC_CFGR_PPRE2F_Msk /*!< APB2 prescaler flag */ 5971 5972 /*!< MCOSEL configuration */ 5973 #define RCC_CFGR_MCOSEL_Pos (24U) 5974 #define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */ 5975 #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [3:0] bits (Clock output selection) */ 5976 #define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */ 5977 #define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */ 5978 #define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */ 5979 #define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */ 5980 5981 /*!< MCOPRE configuration */ 5982 #define RCC_CFGR_MCOPRE_Pos (28U) 5983 #define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */ 5984 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */ 5985 #define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */ 5986 #define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */ 5987 #define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */ 5988 5989 /******************** Bit definition for RCC_PLLCFGR register ***************/ 5990 #define RCC_PLLCFGR_PLLSRC_Pos (0U) 5991 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000003 */ 5992 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk 5993 #define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000001 */ 5994 #define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000002 */ 5995 5996 #define RCC_PLLCFGR_PLLM_Pos (4U) 5997 #define RCC_PLLCFGR_PLLM_Msk (0x7UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000070 */ 5998 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk 5999 #define RCC_PLLCFGR_PLLM_0 (0x1UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */ 6000 #define RCC_PLLCFGR_PLLM_1 (0x2UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */ 6001 #define RCC_PLLCFGR_PLLM_2 (0x4UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */ 6002 6003 #define RCC_PLLCFGR_PLLN_Pos (8U) 6004 #define RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00007F00 */ 6005 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk 6006 #define RCC_PLLCFGR_PLLN_0 (0x01UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00000100 */ 6007 #define RCC_PLLCFGR_PLLN_1 (0x02UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00000200 */ 6008 #define RCC_PLLCFGR_PLLN_2 (0x04UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00000400 */ 6009 #define RCC_PLLCFGR_PLLN_3 (0x08UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00000800 */ 6010 #define RCC_PLLCFGR_PLLN_4 (0x10UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00001000 */ 6011 #define RCC_PLLCFGR_PLLN_5 (0x20UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00002000 */ 6012 #define RCC_PLLCFGR_PLLN_6 (0x40UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00004000 */ 6013 6014 #define RCC_PLLCFGR_PLLPEN_Pos (16U) 6015 #define RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos)/*!< 0x00010000 */ 6016 #define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk 6017 #define RCC_PLLCFGR_PLLP_Pos (17U) 6018 #define RCC_PLLCFGR_PLLP_Msk (0x1FUL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x003E0000 */ 6019 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk 6020 #define RCC_PLLCFGR_PLLP_0 (0x01UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00020000 */ 6021 #define RCC_PLLCFGR_PLLP_1 (0x02UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00040000 */ 6022 #define RCC_PLLCFGR_PLLP_2 (0x04UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00080000 */ 6023 #define RCC_PLLCFGR_PLLP_3 (0x08UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00100000 */ 6024 #define RCC_PLLCFGR_PLLP_4 (0x10UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00200000 */ 6025 6026 #define RCC_PLLCFGR_PLLQEN_Pos (24U) 6027 #define RCC_PLLCFGR_PLLQEN_Msk (0x1UL << RCC_PLLCFGR_PLLQEN_Pos)/*!< 0x01000000 */ 6028 #define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk 6029 #define RCC_PLLCFGR_PLLQ_Pos (25U) 6030 #define RCC_PLLCFGR_PLLQ_Msk (0x7UL << RCC_PLLCFGR_PLLQ_Pos)/*!< 0x0E000000 */ 6031 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk 6032 #define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)/*!< 0x02000000 */ 6033 #define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)/*!< 0x04000000 */ 6034 #define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)/*!< 0x08000000 */ 6035 6036 #define RCC_PLLCFGR_PLLREN_Pos (28U) 6037 #define RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos)/*!< 0x10000000 */ 6038 #define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk 6039 #define RCC_PLLCFGR_PLLR_Pos (29U) 6040 #define RCC_PLLCFGR_PLLR_Msk (0x7UL << RCC_PLLCFGR_PLLR_Pos)/*!< 0xE0000000 */ 6041 #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk 6042 #define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos)/*!< 0x20000000 */ 6043 #define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos)/*!< 0x40000000 */ 6044 #define RCC_PLLCFGR_PLLR_2 (0x4UL << RCC_PLLCFGR_PLLR_Pos)/*!< 0x80000000 */ 6045 6046 6047 /******************** Bit definition for RCC_CIER register ******************/ 6048 #define RCC_CIER_LSIRDYIE_Pos (0U) 6049 #define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ 6050 #define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk 6051 #define RCC_CIER_LSERDYIE_Pos (1U) 6052 #define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ 6053 #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk 6054 #define RCC_CIER_MSIRDYIE_Pos (2U) 6055 #define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000004 */ 6056 #define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk 6057 #define RCC_CIER_HSIRDYIE_Pos (3U) 6058 #define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */ 6059 #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk 6060 #define RCC_CIER_HSERDYIE_Pos (4U) 6061 #define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */ 6062 #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk 6063 #define RCC_CIER_PLLRDYIE_Pos (5U) 6064 #define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos)/*!< 0x00000020 */ 6065 #define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk 6066 #define RCC_CIER_LSECSSIE_Pos (9U) 6067 #define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */ 6068 #define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk 6069 6070 /******************** Bit definition for RCC_CIFR register ******************/ 6071 #define RCC_CIFR_LSIRDYF_Pos (0U) 6072 #define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ 6073 #define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk 6074 #define RCC_CIFR_LSERDYF_Pos (1U) 6075 #define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ 6076 #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk 6077 #define RCC_CIFR_MSIRDYF_Pos (2U) 6078 #define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000004 */ 6079 #define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk 6080 #define RCC_CIFR_HSIRDYF_Pos (3U) 6081 #define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */ 6082 #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk 6083 #define RCC_CIFR_HSERDYF_Pos (4U) 6084 #define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */ 6085 #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk 6086 #define RCC_CIFR_PLLRDYF_Pos (5U) 6087 #define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos)/*!< 0x00000020 */ 6088 #define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk 6089 #define RCC_CIFR_CSSF_Pos (8U) 6090 #define RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */ 6091 #define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk 6092 #define RCC_CIFR_LSECSSF_Pos (9U) 6093 #define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */ 6094 #define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk 6095 6096 /******************** Bit definition for RCC_CICR register ******************/ 6097 #define RCC_CICR_LSIRDYC_Pos (0U) 6098 #define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ 6099 #define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk 6100 #define RCC_CICR_LSERDYC_Pos (1U) 6101 #define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ 6102 #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk 6103 #define RCC_CICR_MSIRDYC_Pos (2U) 6104 #define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000004 */ 6105 #define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk 6106 #define RCC_CICR_HSIRDYC_Pos (3U) 6107 #define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */ 6108 #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk 6109 #define RCC_CICR_HSERDYC_Pos (4U) 6110 #define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */ 6111 #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk 6112 #define RCC_CICR_PLLRDYC_Pos (5U) 6113 #define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos)/*!< 0x00000020 */ 6114 #define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk 6115 #define RCC_CICR_CSSC_Pos (8U) 6116 #define RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */ 6117 #define RCC_CICR_CSSC RCC_CICR_CSSC_Msk 6118 #define RCC_CICR_LSECSSC_Pos (9U) 6119 #define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */ 6120 #define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk 6121 6122 /******************** Bit definition for RCC_AHB1RSTR register **************/ 6123 #define RCC_AHB1RSTR_DMA1RST_Pos (0U) 6124 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)/*!< 0x00000001 */ 6125 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk 6126 #define RCC_AHB1RSTR_DMA2RST_Pos (1U) 6127 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)/*!< 0x00000002 */ 6128 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk 6129 #define RCC_AHB1RSTR_DMAMUX1RST_Pos (2U) 6130 #define RCC_AHB1RSTR_DMAMUX1RST_Msk (0x1UL << RCC_AHB1RSTR_DMAMUX1RST_Pos)/*!< 0x00000004 */ 6131 #define RCC_AHB1RSTR_DMAMUX1RST RCC_AHB1RSTR_DMAMUX1RST_Msk 6132 #define RCC_AHB1RSTR_CRCRST_Pos (12U) 6133 #define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)/*!< 0x00001000 */ 6134 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk 6135 6136 /******************** Bit definition for RCC_AHB2RSTR register ***************/ 6137 #define RCC_AHB2RSTR_GPIOARST_Pos (0U) 6138 #define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)/*!< 0x00000001 */ 6139 #define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk 6140 #define RCC_AHB2RSTR_GPIOBRST_Pos (1U) 6141 #define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)/*!< 0x00000002 */ 6142 #define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk 6143 #define RCC_AHB2RSTR_GPIOCRST_Pos (2U) 6144 #define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)/*!< 0x00000004 */ 6145 #define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk 6146 #define RCC_AHB2RSTR_GPIOHRST_Pos (7U) 6147 #define RCC_AHB2RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos)/*!< 0x00000080 */ 6148 #define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk 6149 6150 /******************** Bit definition for RCC_AHB3RSTR register ***************/ 6151 #define RCC_AHB3RSTR_PKARST_Pos (16U) 6152 #define RCC_AHB3RSTR_PKARST_Msk (0x1UL << RCC_AHB3RSTR_PKARST_Pos) /*!< 0x00010000 */ 6153 #define RCC_AHB3RSTR_PKARST RCC_AHB3RSTR_PKARST_Msk 6154 #define RCC_AHB3RSTR_AESRST_Pos (17U) 6155 #define RCC_AHB3RSTR_AESRST_Msk (0x1UL << RCC_AHB3RSTR_AESRST_Pos)/*!< 0x00020000 */ 6156 #define RCC_AHB3RSTR_AESRST RCC_AHB3RSTR_AESRST_Msk 6157 #define RCC_AHB3RSTR_RNGRST_Pos (18U) 6158 #define RCC_AHB3RSTR_RNGRST_Msk (0x1UL << RCC_AHB3RSTR_RNGRST_Pos)/*!< 0x00040000 */ 6159 #define RCC_AHB3RSTR_RNGRST RCC_AHB3RSTR_RNGRST_Msk 6160 6161 #define RCC_AHB3RSTR_HSEMRST_Pos (19U) 6162 #define RCC_AHB3RSTR_HSEMRST_Msk (0x1UL << RCC_AHB3RSTR_HSEMRST_Pos)/*!< 0x00080000 */ 6163 #define RCC_AHB3RSTR_HSEMRST RCC_AHB3RSTR_HSEMRST_Msk 6164 #define RCC_AHB3RSTR_FLASHRST_Pos (25U) 6165 #define RCC_AHB3RSTR_FLASHRST_Msk (0x1UL << RCC_AHB3RSTR_FLASHRST_Pos) /*!< 0x02000000 */ 6166 #define RCC_AHB3RSTR_FLASHRST RCC_AHB3RSTR_FLASHRST_Msk 6167 6168 /******************** Bit definition for RCC_APB1RSTR1 register **************/ 6169 #define RCC_APB1RSTR1_TIM2RST_Pos (0U) 6170 #define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)/*!< 0x00000001 */ 6171 #define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk 6172 #define RCC_APB1RSTR1_SPI2RST_Pos (14U) 6173 #define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)/*!< 0x00004000 */ 6174 #define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk 6175 #define RCC_APB1RSTR1_USART2RST_Pos (17U) 6176 #define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */ 6177 #define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk 6178 #define RCC_APB1RSTR1_I2C1RST_Pos (21U) 6179 #define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)/*!< 0x00200000 */ 6180 #define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk 6181 #define RCC_APB1RSTR1_I2C2RST_Pos (22U) 6182 #define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)/*!< 0x00400000 */ 6183 #define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk 6184 #define RCC_APB1RSTR1_I2C3RST_Pos (23U) 6185 #define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)/*!< 0x00800000 */ 6186 #define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk 6187 #define RCC_APB1RSTR1_DACRST_Pos (29U) 6188 #define RCC_APB1RSTR1_DACRST_Msk (0x1UL << RCC_APB1RSTR1_DACRST_Pos)/*!< 0x20000000 */ 6189 #define RCC_APB1RSTR1_DACRST RCC_APB1RSTR1_DACRST_Msk 6190 #define RCC_APB1RSTR1_LPTIM1RST_Pos (31U) 6191 #define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x80000000 */ 6192 #define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk 6193 6194 /******************** Bit definition for RCC_APB1RSTR2 register **************/ 6195 #define RCC_APB1RSTR2_LPUART1RST_Pos (0U) 6196 #define RCC_APB1RSTR2_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos)/*!< 0x00000001 */ 6197 #define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk 6198 #define RCC_APB1RSTR2_LPTIM2RST_Pos (5U) 6199 #define RCC_APB1RSTR2_LPTIM2RST_Msk (0x1UL << RCC_APB1RSTR2_LPTIM2RST_Pos)/*!< 0x00000020 */ 6200 #define RCC_APB1RSTR2_LPTIM2RST RCC_APB1RSTR2_LPTIM2RST_Msk 6201 #define RCC_APB1RSTR2_LPTIM3RST_Pos (6U) 6202 #define RCC_APB1RSTR2_LPTIM3RST_Msk (0x1UL << RCC_APB1RSTR2_LPTIM3RST_Pos)/*!< 0x00000040 */ 6203 #define RCC_APB1RSTR2_LPTIM3RST RCC_APB1RSTR2_LPTIM3RST_Msk 6204 6205 /******************** Bit definition for RCC_APB2RSTR register **************/ 6206 #define RCC_APB2RSTR_ADCRST_Pos (9U) 6207 #define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos)/*!< 0x00000200 */ 6208 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk 6209 #define RCC_APB2RSTR_TIM1RST_Pos (11U) 6210 #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)/*!< 0x00000800 */ 6211 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk 6212 #define RCC_APB2RSTR_SPI1RST_Pos (12U) 6213 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)/*!< 0x00001000 */ 6214 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk 6215 #define RCC_APB2RSTR_USART1RST_Pos (14U) 6216 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)/*!< 0x00004000 */ 6217 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk 6218 #define RCC_APB2RSTR_TIM16RST_Pos (17U) 6219 #define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)/*!< 0x00020000 */ 6220 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk 6221 #define RCC_APB2RSTR_TIM17RST_Pos (18U) 6222 #define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)/*!< 0x00040000 */ 6223 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk 6224 6225 /******************** Bit definition for RCC_APB3RSTR register **************/ 6226 #define RCC_APB3RSTR_SUBGHZSPIRST_Pos (0U) 6227 #define RCC_APB3RSTR_SUBGHZSPIRST_Msk (0x1UL << RCC_APB3RSTR_SUBGHZSPIRST_Pos) /*!< 0x00000001 */ 6228 #define RCC_APB3RSTR_SUBGHZSPIRST RCC_APB3RSTR_SUBGHZSPIRST_Msk 6229 6230 /******************** Bit definition for RCC_AHB1ENR register ****************/ 6231 #define RCC_AHB1ENR_DMA1EN_Pos (0U) 6232 #define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */ 6233 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk 6234 #define RCC_AHB1ENR_DMA2EN_Pos (1U) 6235 #define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */ 6236 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk 6237 #define RCC_AHB1ENR_DMAMUX1EN_Pos (2U) 6238 #define RCC_AHB1ENR_DMAMUX1EN_Msk (0x1UL << RCC_AHB1ENR_DMAMUX1EN_Pos)/*!< 0x00000004 */ 6239 #define RCC_AHB1ENR_DMAMUX1EN RCC_AHB1ENR_DMAMUX1EN_Msk 6240 #define RCC_AHB1ENR_CRCEN_Pos (12U) 6241 #define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */ 6242 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk 6243 6244 /******************** Bit definition for RCC_AHB2ENR register ***************/ 6245 #define RCC_AHB2ENR_GPIOAEN_Pos (0U) 6246 #define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */ 6247 #define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk 6248 #define RCC_AHB2ENR_GPIOBEN_Pos (1U) 6249 #define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */ 6250 #define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk 6251 #define RCC_AHB2ENR_GPIOCEN_Pos (2U) 6252 #define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */ 6253 #define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk 6254 #define RCC_AHB2ENR_GPIOHEN_Pos (7U) 6255 #define RCC_AHB2ENR_GPIOHEN_Msk (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */ 6256 #define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk 6257 6258 /******************** Bit definition for RCC_AHB3ENR register ***************/ 6259 #define RCC_AHB3ENR_PKAEN_Pos (16U) 6260 #define RCC_AHB3ENR_PKAEN_Msk (0x1UL << RCC_AHB3ENR_PKAEN_Pos) /*!< 0x00010000 */ 6261 #define RCC_AHB3ENR_PKAEN RCC_AHB3ENR_PKAEN_Msk 6262 #define RCC_AHB3ENR_AESEN_Pos (17U) 6263 #define RCC_AHB3ENR_AESEN_Msk (0x1UL << RCC_AHB3ENR_AESEN_Pos)/*!< 0x00020000 */ 6264 #define RCC_AHB3ENR_AESEN RCC_AHB3ENR_AESEN_Msk 6265 #define RCC_AHB3ENR_RNGEN_Pos (18U) 6266 #define RCC_AHB3ENR_RNGEN_Msk (0x1UL << RCC_AHB3ENR_RNGEN_Pos) /*!< 0x00040000 */ 6267 #define RCC_AHB3ENR_RNGEN RCC_AHB3ENR_RNGEN_Msk 6268 #define RCC_AHB3ENR_HSEMEN_Pos (19U) 6269 #define RCC_AHB3ENR_HSEMEN_Msk (0x1UL << RCC_AHB3ENR_HSEMEN_Pos) /*!< 0x00080000 */ 6270 #define RCC_AHB3ENR_HSEMEN RCC_AHB3ENR_HSEMEN_Msk 6271 #define RCC_AHB3ENR_FLASHEN_Pos (25U) 6272 #define RCC_AHB3ENR_FLASHEN_Msk (0x1UL << RCC_AHB3ENR_FLASHEN_Pos) /*!< 0x02000000 */ 6273 #define RCC_AHB3ENR_FLASHEN RCC_AHB3ENR_FLASHEN_Msk 6274 6275 /******************** Bit definition for RCC_APB1ENR1 register **************/ 6276 #define RCC_APB1ENR1_TIM2EN_Pos (0U) 6277 #define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */ 6278 #define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk 6279 #define RCC_APB1ENR1_RTCAPBEN_Pos (10U) 6280 #define RCC_APB1ENR1_RTCAPBEN_Msk (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos)/*!< 0x00000400 */ 6281 #define RCC_APB1ENR1_RTCAPBEN RCC_APB1ENR1_RTCAPBEN_Msk 6282 #define RCC_APB1ENR1_WWDGEN_Pos (11U) 6283 #define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */ 6284 #define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk 6285 #define RCC_APB1ENR1_SPI2EN_Pos (14U) 6286 #define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */ 6287 #define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk 6288 #define RCC_APB1ENR1_USART2EN_Pos (17U) 6289 #define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */ 6290 #define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk 6291 #define RCC_APB1ENR1_I2C1EN_Pos (21U) 6292 #define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */ 6293 #define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk 6294 #define RCC_APB1ENR1_I2C2EN_Pos (22U) 6295 #define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */ 6296 #define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk 6297 #define RCC_APB1ENR1_I2C3EN_Pos (23U) 6298 #define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */ 6299 #define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk 6300 #define RCC_APB1ENR1_DACEN_Pos (29U) 6301 #define RCC_APB1ENR1_DACEN_Msk (0x1UL << RCC_APB1ENR1_DACEN_Pos)/*!< 0x20000000 */ 6302 #define RCC_APB1ENR1_DACEN RCC_APB1ENR1_DACEN_Msk 6303 #define RCC_APB1ENR1_LPTIM1EN_Pos (31U) 6304 #define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)/*!< 0x80000000 */ 6305 #define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk 6306 6307 /******************** Bit definition for RCC_APB1ENR2 register **************/ 6308 #define RCC_APB1ENR2_LPUART1EN_Pos (0U) 6309 #define RCC_APB1ENR2_LPUART1EN_Msk (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos)/*!< 0x00000001 */ 6310 #define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk 6311 #define RCC_APB1ENR2_LPTIM2EN_Pos (5U) 6312 #define RCC_APB1ENR2_LPTIM2EN_Msk (0x1UL << RCC_APB1ENR2_LPTIM2EN_Pos)/*!< 0x00000020 */ 6313 #define RCC_APB1ENR2_LPTIM2EN RCC_APB1ENR2_LPTIM2EN_Msk 6314 #define RCC_APB1ENR2_LPTIM3EN_Pos (6U) 6315 #define RCC_APB1ENR2_LPTIM3EN_Msk (0x1UL << RCC_APB1ENR2_LPTIM3EN_Pos)/*!< 0x00000040 */ 6316 #define RCC_APB1ENR2_LPTIM3EN RCC_APB1ENR2_LPTIM3EN_Msk 6317 6318 /******************** Bit definition for RCC_APB2ENR register **************/ 6319 #define RCC_APB2ENR_ADCEN_Pos (9U) 6320 #define RCC_APB2ENR_ADCEN_Msk (0x1UL << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */ 6321 #define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk 6322 #define RCC_APB2ENR_TIM1EN_Pos (11U) 6323 #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ 6324 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk 6325 #define RCC_APB2ENR_SPI1EN_Pos (12U) 6326 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ 6327 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk 6328 #define RCC_APB2ENR_USART1EN_Pos (14U) 6329 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)/*!< 0x00004000 */ 6330 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk 6331 #define RCC_APB2ENR_TIM16EN_Pos (17U) 6332 #define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ 6333 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk 6334 #define RCC_APB2ENR_TIM17EN_Pos (18U) 6335 #define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ 6336 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk 6337 6338 /******************** Bit definition for RCC_APB3ENR register **************/ 6339 #define RCC_APB3ENR_SUBGHZSPIEN_Pos (0U) 6340 #define RCC_APB3ENR_SUBGHZSPIEN_Msk (0x1UL << RCC_APB3ENR_SUBGHZSPIEN_Pos)/*!< 0x00000001 */ 6341 #define RCC_APB3ENR_SUBGHZSPIEN RCC_APB3ENR_SUBGHZSPIEN_Msk 6342 6343 /******************** Bit definition for RCC_AHB1SMENR register ****************/ 6344 #define RCC_AHB1SMENR_DMA1SMEN_Pos (0U) 6345 #define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos)/*!< 0x00000001 */ 6346 #define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk 6347 #define RCC_AHB1SMENR_DMA2SMEN_Pos (1U) 6348 #define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos)/*!< 0x00000002 */ 6349 #define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk 6350 #define RCC_AHB1SMENR_DMAMUX1SMEN_Pos (2U) 6351 #define RCC_AHB1SMENR_DMAMUX1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMAMUX1SMEN_Pos)/*!< 0x00000004 */ 6352 #define RCC_AHB1SMENR_DMAMUX1SMEN RCC_AHB1SMENR_DMAMUX1SMEN_Msk 6353 #define RCC_AHB1SMENR_CRCSMEN_Pos (12U) 6354 #define RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)/*!< 0x00001000 */ 6355 #define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk 6356 6357 /******************** Bit definition for RCC_AHB2SMENR register ***************/ 6358 #define RCC_AHB2SMENR_GPIOASMEN_Pos (0U) 6359 #define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos)/*!< 0x00000001 */ 6360 #define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk 6361 #define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U) 6362 #define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos)/*!< 0x00000002 */ 6363 #define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk 6364 #define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U) 6365 #define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos)/*!< 0x00000004 */ 6366 #define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk 6367 #define RCC_AHB2SMENR_GPIOHSMEN_Pos (7U) 6368 #define RCC_AHB2SMENR_GPIOHSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOHSMEN_Pos)/*!< 0x00000080 */ 6369 #define RCC_AHB2SMENR_GPIOHSMEN RCC_AHB2SMENR_GPIOHSMEN_Msk 6370 6371 /******************** Bit definition for RCC_AHB3SMENR register ***************/ 6372 #define RCC_AHB3SMENR_PKASMEN_Pos (16U) 6373 #define RCC_AHB3SMENR_PKASMEN_Msk (0x1UL << RCC_AHB3SMENR_PKASMEN_Pos) /*!< 0x00010000 */ 6374 #define RCC_AHB3SMENR_PKASMEN RCC_AHB3SMENR_PKASMEN_Msk 6375 #define RCC_AHB3SMENR_AESSMEN_Pos (17U) 6376 #define RCC_AHB3SMENR_AESSMEN_Msk (0x1UL << RCC_AHB3SMENR_AESSMEN_Pos) /*!< 0x00020000 */ 6377 #define RCC_AHB3SMENR_AESSMEN RCC_AHB3SMENR_AESSMEN_Msk 6378 #define RCC_AHB3SMENR_RNGSMEN_Pos (18U) 6379 #define RCC_AHB3SMENR_RNGSMEN_Msk (0x1UL << RCC_AHB3SMENR_RNGSMEN_Pos)/*!< 0x00040000 */ 6380 #define RCC_AHB3SMENR_RNGSMEN RCC_AHB3SMENR_RNGSMEN_Msk 6381 #define RCC_AHB3SMENR_SRAM1SMEN_Pos (23U) 6382 #define RCC_AHB3SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB3SMENR_SRAM1SMEN_Pos)/*!< 0x00800000 */ 6383 #define RCC_AHB3SMENR_SRAM1SMEN RCC_AHB3SMENR_SRAM1SMEN_Msk 6384 #define RCC_AHB3SMENR_SRAM2SMEN_Pos (24U) 6385 #define RCC_AHB3SMENR_SRAM2SMEN_Msk (0x1UL << RCC_AHB3SMENR_SRAM2SMEN_Pos)/*!< 0x01000000 */ 6386 #define RCC_AHB3SMENR_SRAM2SMEN RCC_AHB3SMENR_SRAM2SMEN_Msk 6387 #define RCC_AHB3SMENR_FLASHSMEN_Pos (25U) 6388 #define RCC_AHB3SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB3SMENR_FLASHSMEN_Pos)/*!< 0x02000000 */ 6389 #define RCC_AHB3SMENR_FLASHSMEN RCC_AHB3SMENR_FLASHSMEN_Msk 6390 6391 /******************** Bit definition for RCC_APB1SMENR1 register **************/ 6392 #define RCC_APB1SMENR1_TIM2SMEN_Pos (0U) 6393 #define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)/*!< 0x00000001 */ 6394 #define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk 6395 #define RCC_APB1SMENR1_RTCAPBSMEN_Pos (10U) 6396 #define RCC_APB1SMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos)/*!< 0x00000400 */ 6397 #define RCC_APB1SMENR1_RTCAPBSMEN RCC_APB1SMENR1_RTCAPBSMEN_Msk 6398 #define RCC_APB1SMENR1_WWDGSMEN_Pos (11U) 6399 #define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)/*!< 0x00000800 */ 6400 #define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk 6401 #define RCC_APB1SMENR1_SPI2SMEN_Pos (14U) 6402 #define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)/*!< 0x00004000 */ 6403 #define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk 6404 #define RCC_APB1SMENR1_USART2SMEN_Pos (17U) 6405 #define RCC_APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)/*!< 0x00020000 */ 6406 #define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk 6407 #define RCC_APB1SMENR1_I2C1SMEN_Pos (21U) 6408 #define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)/*!< 0x00200000 */ 6409 #define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk 6410 #define RCC_APB1SMENR1_I2C2SMEN_Pos (22U) 6411 #define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)/*!< 0x00400000 */ 6412 #define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk 6413 #define RCC_APB1SMENR1_I2C3SMEN_Pos (23U) 6414 #define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos)/*!< 0x00800000 */ 6415 #define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk 6416 #define RCC_APB1SMENR1_DACSMEN_Pos (29U) 6417 #define RCC_APB1SMENR1_DACSMEN_Msk (0x1UL << RCC_APB1SMENR1_DACSMEN_Pos)/*!< 0x20000000 */ 6418 #define RCC_APB1SMENR1_DACSMEN RCC_APB1SMENR1_DACSMEN_Msk 6419 #define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U) 6420 #define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos)/*!< 0x80000000 */ 6421 #define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk 6422 6423 /******************** Bit definition for RCC_APB1SMENR2 register **************/ 6424 #define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U) 6425 #define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos)/*!< 0x00000001 */ 6426 #define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk 6427 #define RCC_APB1SMENR2_LPTIM2SMEN_Pos (5U) 6428 #define RCC_APB1SMENR2_LPTIM2SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPTIM2SMEN_Pos)/*!< 0x00000020 */ 6429 #define RCC_APB1SMENR2_LPTIM2SMEN RCC_APB1SMENR2_LPTIM2SMEN_Msk 6430 #define RCC_APB1SMENR2_LPTIM3SMEN_Pos (6U) 6431 #define RCC_APB1SMENR2_LPTIM3SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPTIM3SMEN_Pos)/*!< 0x00000040 */ 6432 #define RCC_APB1SMENR2_LPTIM3SMEN RCC_APB1SMENR2_LPTIM3SMEN_Msk 6433 6434 /******************** Bit definition for RCC_APB2SMENR register **************/ 6435 #define RCC_APB2SMENR_ADCSMEN_Pos (9U) 6436 #define RCC_APB2SMENR_ADCSMEN_Msk (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos)/*!< 0x00000200 */ 6437 #define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk 6438 #define RCC_APB2SMENR_TIM1SMEN_Pos (11U) 6439 #define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)/*!< 0x00000800 */ 6440 #define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk 6441 #define RCC_APB2SMENR_SPI1SMEN_Pos (12U) 6442 #define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)/*!< 0x00001000 */ 6443 #define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk 6444 #define RCC_APB2SMENR_USART1SMEN_Pos (14U) 6445 #define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)/*!< 0x00004000 */ 6446 #define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk 6447 #define RCC_APB2SMENR_TIM16SMEN_Pos (17U) 6448 #define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)/*!< 0x00020000 */ 6449 #define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk 6450 #define RCC_APB2SMENR_TIM17SMEN_Pos (18U) 6451 #define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */ 6452 #define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk 6453 6454 /******************** Bit definition for RCC_APB3SMENR register **************/ 6455 #define RCC_APB3SMENR_SUBGHZSPISMEN_Pos (0U) 6456 #define RCC_APB3SMENR_SUBGHZSPISMEN_Msk (0x1UL << RCC_APB3SMENR_SUBGHZSPISMEN_Pos)/*!< 0x00000001 */ 6457 #define RCC_APB3SMENR_SUBGHZSPISMEN RCC_APB3SMENR_SUBGHZSPISMEN_Msk 6458 6459 /******************** Bit definition for RCC_CCIPR register ******************/ 6460 #define RCC_CCIPR_USART1SEL_Pos (0U) 6461 #define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */ 6462 #define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk 6463 #define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */ 6464 #define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */ 6465 6466 #define RCC_CCIPR_USART2SEL_Pos (2U) 6467 #define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */ 6468 #define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk 6469 #define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */ 6470 #define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */ 6471 6472 #define RCC_CCIPR_I2S2SEL_Pos (8U) 6473 #define RCC_CCIPR_I2S2SEL_Msk (0x3UL << RCC_CCIPR_I2S2SEL_Pos) /*!< 0x00000300 */ 6474 #define RCC_CCIPR_I2S2SEL RCC_CCIPR_I2S2SEL_Msk 6475 #define RCC_CCIPR_I2S2SEL_0 (0x1UL << RCC_CCIPR_I2S2SEL_Pos) /*!< 0x00000100 */ 6476 #define RCC_CCIPR_I2S2SEL_1 (0x2UL << RCC_CCIPR_I2S2SEL_Pos) /*!< 0x00000200 */ 6477 6478 #define RCC_CCIPR_LPUART1SEL_Pos (10U) 6479 #define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */ 6480 #define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk 6481 #define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */ 6482 #define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */ 6483 6484 #define RCC_CCIPR_I2C1SEL_Pos (12U) 6485 #define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */ 6486 #define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk 6487 #define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */ 6488 #define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */ 6489 6490 #define RCC_CCIPR_I2C2SEL_Pos (14U) 6491 #define RCC_CCIPR_I2C2SEL_Msk (0x3UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x0000C000 */ 6492 #define RCC_CCIPR_I2C2SEL RCC_CCIPR_I2C2SEL_Msk 6493 #define RCC_CCIPR_I2C2SEL_0 (0x1UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00004000 */ 6494 #define RCC_CCIPR_I2C2SEL_1 (0x2UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00008000 */ 6495 6496 #define RCC_CCIPR_I2C3SEL_Pos (16U) 6497 #define RCC_CCIPR_I2C3SEL_Msk (0x3UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */ 6498 #define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk 6499 #define RCC_CCIPR_I2C3SEL_0 (0x1UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */ 6500 #define RCC_CCIPR_I2C3SEL_1 (0x2UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */ 6501 6502 #define RCC_CCIPR_LPTIM1SEL_Pos (18U) 6503 #define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */ 6504 #define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk 6505 #define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */ 6506 #define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */ 6507 6508 #define RCC_CCIPR_LPTIM2SEL_Pos (20U) 6509 #define RCC_CCIPR_LPTIM2SEL_Msk (0x3UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */ 6510 #define RCC_CCIPR_LPTIM2SEL RCC_CCIPR_LPTIM2SEL_Msk 6511 #define RCC_CCIPR_LPTIM2SEL_0 (0x1UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */ 6512 #define RCC_CCIPR_LPTIM2SEL_1 (0x2UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */ 6513 6514 #define RCC_CCIPR_LPTIM3SEL_Pos (22U) 6515 #define RCC_CCIPR_LPTIM3SEL_Msk (0x3UL << RCC_CCIPR_LPTIM3SEL_Pos) /*!< 0x00C00000 */ 6516 #define RCC_CCIPR_LPTIM3SEL RCC_CCIPR_LPTIM3SEL_Msk 6517 #define RCC_CCIPR_LPTIM3SEL_0 (0x1UL << RCC_CCIPR_LPTIM3SEL_Pos) /*!< 0x00400000 */ 6518 #define RCC_CCIPR_LPTIM3SEL_1 (0x2UL << RCC_CCIPR_LPTIM3SEL_Pos) /*!< 0x00800000 */ 6519 6520 #define RCC_CCIPR_ADCSEL_Pos (28U) 6521 #define RCC_CCIPR_ADCSEL_Msk (0x3UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0x30000000 */ 6522 #define RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk 6523 #define RCC_CCIPR_ADCSEL_0 (0x1UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0x10000000 */ 6524 #define RCC_CCIPR_ADCSEL_1 (0x2UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0x20000000 */ 6525 6526 #define RCC_CCIPR_RNGSEL_Pos (30U) 6527 #define RCC_CCIPR_RNGSEL_Msk (0x3UL << RCC_CCIPR_RNGSEL_Pos) /*!< 0xC0000000 */ 6528 #define RCC_CCIPR_RNGSEL RCC_CCIPR_RNGSEL_Msk 6529 #define RCC_CCIPR_RNGSEL_0 (0x1UL << RCC_CCIPR_RNGSEL_Pos) /*!< 0x40000000 */ 6530 #define RCC_CCIPR_RNGSEL_1 (0x2UL << RCC_CCIPR_RNGSEL_Pos) /*!< 0x80000000 */ 6531 6532 /******************** Bit definition for RCC_BDCR register ******************/ 6533 #define RCC_BDCR_LSEON_Pos (0U) 6534 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ 6535 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk 6536 #define RCC_BDCR_LSERDY_Pos (1U) 6537 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ 6538 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk 6539 #define RCC_BDCR_LSEBYP_Pos (2U) 6540 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ 6541 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk 6542 6543 #define RCC_BDCR_LSEDRV_Pos (3U) 6544 #define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */ 6545 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk 6546 #define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */ 6547 #define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ 6548 6549 #define RCC_BDCR_LSECSSON_Pos (5U) 6550 #define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */ 6551 #define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk 6552 #define RCC_BDCR_LSECSSD_Pos (6U) 6553 #define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */ 6554 #define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk 6555 #define RCC_BDCR_LSESYSEN_Pos (7U) 6556 #define RCC_BDCR_LSESYSEN_Msk (0x1UL << RCC_BDCR_LSESYSEN_Pos) /*!< 0x00000080 */ 6557 #define RCC_BDCR_LSESYSEN RCC_BDCR_LSESYSEN_Msk 6558 6559 #define RCC_BDCR_RTCSEL_Pos (8U) 6560 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ 6561 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk 6562 #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ 6563 #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ 6564 6565 #define RCC_BDCR_LSESYSRDY_Pos (11U) 6566 #define RCC_BDCR_LSESYSRDY_Msk (0x1UL << RCC_BDCR_LSESYSRDY_Pos) /*!< 0x00000800 */ 6567 #define RCC_BDCR_LSESYSRDY RCC_BDCR_LSESYSRDY_Msk 6568 6569 #define RCC_BDCR_RTCEN_Pos (15U) 6570 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ 6571 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk 6572 6573 #define RCC_BDCR_BDRST_Pos (16U) 6574 #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ 6575 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk 6576 6577 #define RCC_BDCR_LSCOEN_Pos (24U) 6578 #define RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */ 6579 #define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk 6580 #define RCC_BDCR_LSCOSEL_Pos (25U) 6581 #define RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */ 6582 #define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk 6583 6584 /******************** Bit definition for RCC_CSR register *******************/ 6585 #define RCC_CSR_LSION_Pos (0U) 6586 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ 6587 #define RCC_CSR_LSION RCC_CSR_LSION_Msk 6588 #define RCC_CSR_LSIRDY_Pos (1U) 6589 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ 6590 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk 6591 #define RCC_CSR_LSIPRE_Pos (4U) 6592 #define RCC_CSR_LSIPRE_Msk (0x1UL << RCC_CSR_LSIPRE_Pos) /*!< 0x00000010 */ 6593 #define RCC_CSR_LSIPRE RCC_CSR_LSIPRE_Msk 6594 6595 #define RCC_CSR_MSISRANGE_Pos (8U) 6596 #define RCC_CSR_MSISRANGE_Msk (0xFUL << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000F00 */ 6597 #define RCC_CSR_MSISRANGE RCC_CSR_MSISRANGE_Msk 6598 #define RCC_CSR_MSISRANGE_1 (0x4UL << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000400 */ 6599 #define RCC_CSR_MSISRANGE_2 (0x5UL << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000500 */ 6600 #define RCC_CSR_MSISRANGE_4 (0x6UL << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000600 */ 6601 #define RCC_CSR_MSISRANGE_8 (0x7UL << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000700 */ 6602 6603 #define RCC_CSR_RFRSTF_Pos (14U) 6604 #define RCC_CSR_RFRSTF_Msk (0x1UL << RCC_CSR_RFRSTF_Pos) /*!< 0x0004000 */ 6605 #define RCC_CSR_RFRSTF RCC_CSR_RFRSTF_Msk 6606 #define RCC_CSR_RFRST_Pos (15U) 6607 #define RCC_CSR_RFRST_Msk (0x1UL << RCC_CSR_RFRST_Pos) /*!< 0x0008000 */ 6608 #define RCC_CSR_RFRST RCC_CSR_RFRST_Msk 6609 6610 #define RCC_CSR_RMVF_Pos (23U) 6611 #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */ 6612 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk 6613 #define RCC_CSR_RFILARSTF_Pos (24U) 6614 #define RCC_CSR_RFILARSTF_Msk (0x1UL << RCC_CSR_RFILARSTF_Pos) /*!< 0x01000000 */ 6615 #define RCC_CSR_RFILARSTF RCC_CSR_RFILARSTF_Msk 6616 #define RCC_CSR_OBLRSTF_Pos (25U) 6617 #define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ 6618 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk 6619 #define RCC_CSR_PINRSTF_Pos (26U) 6620 #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ 6621 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk 6622 #define RCC_CSR_BORRSTF_Pos (27U) 6623 #define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */ 6624 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk 6625 #define RCC_CSR_SFTRSTF_Pos (28U) 6626 #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ 6627 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk 6628 #define RCC_CSR_IWDGRSTF_Pos (29U) 6629 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ 6630 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk 6631 #define RCC_CSR_WWDGRSTF_Pos (30U) 6632 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ 6633 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk 6634 #define RCC_CSR_LPWRRSTF_Pos (31U) 6635 #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ 6636 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk 6637 6638 /******************** Bit definition for RCC_EXTCFGR register *******************/ 6639 #define RCC_EXTCFGR_SHDHPRE_Pos (0U) 6640 #define RCC_EXTCFGR_SHDHPRE_Msk (0xFUL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x0000000F */ 6641 #define RCC_EXTCFGR_SHDHPRE RCC_EXTCFGR_SHDHPRE_Msk 6642 #define RCC_EXTCFGR_SHDHPRE_0 (0x1UL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000001 */ 6643 #define RCC_EXTCFGR_SHDHPRE_1 (0x2UL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000002 */ 6644 #define RCC_EXTCFGR_SHDHPRE_2 (0x4UL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000004 */ 6645 #define RCC_EXTCFGR_SHDHPRE_3 (0x8UL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000008 */ 6646 6647 #define RCC_EXTCFGR_SHDHPREF_Pos (16U) 6648 #define RCC_EXTCFGR_SHDHPREF_Msk (0x1UL << RCC_EXTCFGR_SHDHPREF_Pos)/*!< 0x00010000 */ 6649 #define RCC_EXTCFGR_SHDHPREF RCC_EXTCFGR_SHDHPREF_Msk 6650 6651 /******************************************************************************/ 6652 /* */ 6653 /* RNG */ 6654 /* */ 6655 /******************************************************************************/ 6656 /* 6657 * @brief Specific device feature definitions 6658 */ 6659 #define RNG_VER_3_2 6660 6661 /******************** Bits definition for RNG_CR register *******************/ 6662 #define RNG_CR_RNGEN_Pos (2U) 6663 #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ 6664 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk 6665 #define RNG_CR_IE_Pos (3U) 6666 #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ 6667 #define RNG_CR_IE RNG_CR_IE_Msk 6668 #define RNG_CR_CED_Pos (5U) 6669 #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ 6670 #define RNG_CR_CED RNG_CR_CED_Msk 6671 #define RNG_CR_RNG_CONFIG3_Pos (8U) 6672 #define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */ 6673 #define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk 6674 #define RNG_CR_NISTC_Pos (12U) 6675 #define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */ 6676 #define RNG_CR_NISTC RNG_CR_NISTC_Msk 6677 #define RNG_CR_RNG_CONFIG2_Pos (13U) 6678 #define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */ 6679 #define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk 6680 #define RNG_CR_CLKDIV_Pos (16U) 6681 #define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ 6682 #define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk 6683 #define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ 6684 #define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ 6685 #define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ 6686 #define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ 6687 #define RNG_CR_RNG_CONFIG1_Pos (20U) 6688 #define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */ 6689 #define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk 6690 #define RNG_CR_CONDRST_Pos (30U) 6691 #define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */ 6692 #define RNG_CR_CONDRST RNG_CR_CONDRST_Msk 6693 #define RNG_CR_CONFIGLOCK_Pos (31U) 6694 #define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */ 6695 #define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk 6696 6697 /******************** Bits definition for RNG_SR register *******************/ 6698 #define RNG_SR_DRDY_Pos (0U) 6699 #define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ 6700 #define RNG_SR_DRDY RNG_SR_DRDY_Msk 6701 #define RNG_SR_CECS_Pos (1U) 6702 #define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ 6703 #define RNG_SR_CECS RNG_SR_CECS_Msk 6704 #define RNG_SR_SECS_Pos (2U) 6705 #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ 6706 #define RNG_SR_SECS RNG_SR_SECS_Msk 6707 #define RNG_SR_CEIS_Pos (5U) 6708 #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ 6709 #define RNG_SR_CEIS RNG_SR_CEIS_Msk 6710 #define RNG_SR_SEIS_Pos (6U) 6711 #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ 6712 #define RNG_SR_SEIS RNG_SR_SEIS_Msk 6713 6714 /******************** Bits definition for RNG_DR register *******************/ 6715 #define RNG_DR_RNDATA_Pos (0U) 6716 #define RNG_DR_RNDATA_Msk (0xFFFFFFFFUL << RNG_DR_RNDATA_Pos) /*!< 0xFFFFFFFF */ 6717 #define RNG_DR_RNDATA RNG_DR_RNDATA_Msk 6718 6719 /******************** Bits definition for RNG_HTCR register *****************/ 6720 #define RNG_HTCR_HTCFG_Pos (0U) 6721 #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ 6722 #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk 6723 6724 /******************************************************************************/ 6725 /* */ 6726 /* Real-Time Clock (RTC) */ 6727 /* */ 6728 /******************************************************************************/ 6729 /******************** Bits definition for RTC_TR register *******************/ 6730 #define RTC_TR_PM_Pos (22U) 6731 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ 6732 #define RTC_TR_PM RTC_TR_PM_Msk 6733 #define RTC_TR_HT_Pos (20U) 6734 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ 6735 #define RTC_TR_HT RTC_TR_HT_Msk 6736 #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ 6737 #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ 6738 #define RTC_TR_HU_Pos (16U) 6739 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ 6740 #define RTC_TR_HU RTC_TR_HU_Msk 6741 #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ 6742 #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ 6743 #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ 6744 #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ 6745 #define RTC_TR_MNT_Pos (12U) 6746 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ 6747 #define RTC_TR_MNT RTC_TR_MNT_Msk 6748 #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ 6749 #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ 6750 #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ 6751 #define RTC_TR_MNU_Pos (8U) 6752 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ 6753 #define RTC_TR_MNU RTC_TR_MNU_Msk 6754 #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ 6755 #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ 6756 #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ 6757 #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ 6758 #define RTC_TR_ST_Pos (4U) 6759 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ 6760 #define RTC_TR_ST RTC_TR_ST_Msk 6761 #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ 6762 #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ 6763 #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ 6764 #define RTC_TR_SU_Pos (0U) 6765 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ 6766 #define RTC_TR_SU RTC_TR_SU_Msk 6767 #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ 6768 #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ 6769 #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ 6770 #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ 6771 6772 /******************** Bits definition for RTC_DR register *******************/ 6773 #define RTC_DR_YT_Pos (20U) 6774 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ 6775 #define RTC_DR_YT RTC_DR_YT_Msk 6776 #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ 6777 #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ 6778 #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ 6779 #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ 6780 #define RTC_DR_YU_Pos (16U) 6781 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ 6782 #define RTC_DR_YU RTC_DR_YU_Msk 6783 #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ 6784 #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ 6785 #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ 6786 #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ 6787 #define RTC_DR_WDU_Pos (13U) 6788 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ 6789 #define RTC_DR_WDU RTC_DR_WDU_Msk 6790 #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ 6791 #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ 6792 #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ 6793 #define RTC_DR_MT_Pos (12U) 6794 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ 6795 #define RTC_DR_MT RTC_DR_MT_Msk 6796 #define RTC_DR_MU_Pos (8U) 6797 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ 6798 #define RTC_DR_MU RTC_DR_MU_Msk 6799 #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ 6800 #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ 6801 #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ 6802 #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ 6803 #define RTC_DR_DT_Pos (4U) 6804 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ 6805 #define RTC_DR_DT RTC_DR_DT_Msk 6806 #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ 6807 #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ 6808 #define RTC_DR_DU_Pos (0U) 6809 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ 6810 #define RTC_DR_DU RTC_DR_DU_Msk 6811 #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ 6812 #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ 6813 #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ 6814 #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ 6815 6816 /******************** Bits definition for RTC_SSR register ******************/ 6817 #define RTC_SSR_SS_Pos (0U) 6818 #define RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) /*!< 0xFFFFFFFF */ 6819 #define RTC_SSR_SS RTC_SSR_SS_Msk 6820 6821 /******************** Bits definition for RTC_ICSR register ******************/ 6822 #define RTC_ICSR_RECALPF_Pos (16U) 6823 #define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ 6824 #define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk 6825 #define RTC_ICSR_BCDU_Pos (10U) 6826 #define RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001C00 */ 6827 #define RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk 6828 #define RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000400 */ 6829 #define RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000800 */ 6830 #define RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001000 */ 6831 #define RTC_ICSR_BIN_Pos (8U) 6832 #define RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) /*!< 0x00000300 */ 6833 #define RTC_ICSR_BIN RTC_ICSR_BIN_Msk 6834 #define RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) /*!< 0x00000100 */ 6835 #define RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) /*!< 0x00000200 */ 6836 #define RTC_ICSR_INIT_Pos (7U) 6837 #define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ 6838 #define RTC_ICSR_INIT RTC_ICSR_INIT_Msk 6839 #define RTC_ICSR_INITF_Pos (6U) 6840 #define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ 6841 #define RTC_ICSR_INITF RTC_ICSR_INITF_Msk 6842 #define RTC_ICSR_RSF_Pos (5U) 6843 #define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ 6844 #define RTC_ICSR_RSF RTC_ICSR_RSF_Msk 6845 #define RTC_ICSR_INITS_Pos (4U) 6846 #define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ 6847 #define RTC_ICSR_INITS RTC_ICSR_INITS_Msk 6848 #define RTC_ICSR_SHPF_Pos (3U) 6849 #define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ 6850 #define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk 6851 #define RTC_ICSR_WUTWF_Pos (2U) 6852 #define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ 6853 #define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk 6854 6855 /******************** Bits definition for RTC_PRER register *****************/ 6856 #define RTC_PRER_PREDIV_A_Pos (16U) 6857 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ 6858 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk 6859 #define RTC_PRER_PREDIV_S_Pos (0U) 6860 #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ 6861 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk 6862 6863 /******************** Bits definition for RTC_WUTR register *****************/ 6864 #define RTC_WUTR_WUTOCLR_Pos (16U) 6865 #define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0x0000FFFF */ 6866 #define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk 6867 #define RTC_WUTR_WUT_Pos (0U) 6868 #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ 6869 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk 6870 6871 /******************** Bits definition for RTC_CR register *******************/ 6872 #define RTC_CR_OUT2EN_Pos (31U) 6873 #define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */ 6874 #define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!<RTC_OUT2 output enable */ 6875 #define RTC_CR_TAMPALRM_TYPE_Pos (30U) 6876 #define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */ 6877 #define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk /*!<TAMPALARM output type */ 6878 #define RTC_CR_TAMPALRM_PU_Pos (29U) 6879 #define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ 6880 #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!<TAMPALARM output pull-up config */ 6881 #define RTC_CR_TAMPOE_Pos (26U) 6882 #define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ 6883 #define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk /*!<Tamper detection output enable on TAMPALARM */ 6884 #define RTC_CR_TAMPTS_Pos (25U) 6885 #define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */ 6886 #define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!<Activate timestamp on tamper detection event */ 6887 #define RTC_CR_ITSE_Pos (24U) 6888 #define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */ 6889 #define RTC_CR_ITSE RTC_CR_ITSE_Msk /*!<Timestamp on internal event enable */ 6890 #define RTC_CR_COE_Pos (23U) 6891 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ 6892 #define RTC_CR_COE RTC_CR_COE_Msk 6893 #define RTC_CR_OSEL_Pos (21U) 6894 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ 6895 #define RTC_CR_OSEL RTC_CR_OSEL_Msk 6896 #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ 6897 #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ 6898 #define RTC_CR_POL_Pos (20U) 6899 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ 6900 #define RTC_CR_POL RTC_CR_POL_Msk 6901 #define RTC_CR_COSEL_Pos (19U) 6902 #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ 6903 #define RTC_CR_COSEL RTC_CR_COSEL_Msk 6904 #define RTC_CR_BKP_Pos (18U) 6905 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ 6906 #define RTC_CR_BKP RTC_CR_BKP_Msk 6907 #define RTC_CR_SUB1H_Pos (17U) 6908 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ 6909 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk 6910 #define RTC_CR_ADD1H_Pos (16U) 6911 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ 6912 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk 6913 #define RTC_CR_TSIE_Pos (15U) 6914 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ 6915 #define RTC_CR_TSIE RTC_CR_TSIE_Msk 6916 #define RTC_CR_WUTIE_Pos (14U) 6917 #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ 6918 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk 6919 #define RTC_CR_ALRBIE_Pos (13U) 6920 #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ 6921 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk 6922 #define RTC_CR_ALRAIE_Pos (12U) 6923 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ 6924 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk 6925 #define RTC_CR_TSE_Pos (11U) 6926 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ 6927 #define RTC_CR_TSE RTC_CR_TSE_Msk 6928 #define RTC_CR_WUTE_Pos (10U) 6929 #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ 6930 #define RTC_CR_WUTE RTC_CR_WUTE_Msk 6931 #define RTC_CR_ALRBE_Pos (9U) 6932 #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ 6933 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk 6934 #define RTC_CR_ALRAE_Pos (8U) 6935 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ 6936 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk 6937 #define RTC_CR_SSRUIE_Pos (7U) 6938 #define RTC_CR_SSRUIE_Msk (0x1UL << RTC_CR_SSRUIE_Pos) /*!< 0x00000080 */ 6939 #define RTC_CR_SSRUIE RTC_CR_SSRUIE_Msk 6940 #define RTC_CR_FMT_Pos (6U) 6941 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ 6942 #define RTC_CR_FMT RTC_CR_FMT_Msk 6943 #define RTC_CR_BYPSHAD_Pos (5U) 6944 #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ 6945 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk 6946 #define RTC_CR_REFCKON_Pos (4U) 6947 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ 6948 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk 6949 #define RTC_CR_TSEDGE_Pos (3U) 6950 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ 6951 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk 6952 #define RTC_CR_WUCKSEL_Pos (0U) 6953 #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ 6954 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk 6955 #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ 6956 #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ 6957 #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ 6958 6959 /******************** Bits definition for RTC_WPR register ******************/ 6960 #define RTC_WPR_KEY_Pos (0U) 6961 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ 6962 #define RTC_WPR_KEY RTC_WPR_KEY_Msk 6963 6964 /******************** Bits definition for RTC_CALR register *****************/ 6965 #define RTC_CALR_CALP_Pos (15U) 6966 #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ 6967 #define RTC_CALR_CALP RTC_CALR_CALP_Msk 6968 #define RTC_CALR_CALW8_Pos (14U) 6969 #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ 6970 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk 6971 #define RTC_CALR_CALW16_Pos (13U) 6972 #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ 6973 #define RTC_CALR_LPCAL RTC_CALR_LPCAL_Msk 6974 #define RTC_CALR_LPCAL_Pos (12U) 6975 #define RTC_CALR_LPCAL_Msk (0x1UL << RTC_CALR_LPCAL_Pos) /*!< 0x00001000 */ 6976 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk 6977 #define RTC_CALR_CALM_Pos (0U) 6978 #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ 6979 #define RTC_CALR_CALM RTC_CALR_CALM_Msk 6980 #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ 6981 #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ 6982 #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ 6983 #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ 6984 #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ 6985 #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ 6986 #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ 6987 #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ 6988 #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ 6989 6990 /******************** Bits definition for RTC_SHIFTR register ***************/ 6991 #define RTC_SHIFTR_ADD1S_Pos (31U) 6992 #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ 6993 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk 6994 #define RTC_SHIFTR_SUBFS_Pos (0U) 6995 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ 6996 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk 6997 6998 /******************** Bits definition for RTC_TSTR register *****************/ 6999 #define RTC_TSTR_PM_Pos (22U) 7000 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ 7001 #define RTC_TSTR_PM RTC_TSTR_PM_Msk 7002 #define RTC_TSTR_HT_Pos (20U) 7003 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ 7004 #define RTC_TSTR_HT RTC_TSTR_HT_Msk 7005 #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ 7006 #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ 7007 #define RTC_TSTR_HU_Pos (16U) 7008 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ 7009 #define RTC_TSTR_HU RTC_TSTR_HU_Msk 7010 #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ 7011 #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ 7012 #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ 7013 #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ 7014 #define RTC_TSTR_MNT_Pos (12U) 7015 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ 7016 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk 7017 #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ 7018 #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ 7019 #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ 7020 #define RTC_TSTR_MNU_Pos (8U) 7021 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ 7022 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk 7023 #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ 7024 #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ 7025 #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ 7026 #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ 7027 #define RTC_TSTR_ST_Pos (4U) 7028 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ 7029 #define RTC_TSTR_ST RTC_TSTR_ST_Msk 7030 #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ 7031 #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ 7032 #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ 7033 #define RTC_TSTR_SU_Pos (0U) 7034 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ 7035 #define RTC_TSTR_SU RTC_TSTR_SU_Msk 7036 #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ 7037 #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ 7038 #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ 7039 #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ 7040 7041 /******************** Bits definition for RTC_TSDR register *****************/ 7042 #define RTC_TSDR_WDU_Pos (13U) 7043 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ 7044 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk 7045 #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ 7046 #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ 7047 #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ 7048 #define RTC_TSDR_MT_Pos (12U) 7049 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ 7050 #define RTC_TSDR_MT RTC_TSDR_MT_Msk 7051 #define RTC_TSDR_MU_Pos (8U) 7052 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ 7053 #define RTC_TSDR_MU RTC_TSDR_MU_Msk 7054 #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ 7055 #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ 7056 #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ 7057 #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ 7058 #define RTC_TSDR_DT_Pos (4U) 7059 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ 7060 #define RTC_TSDR_DT RTC_TSDR_DT_Msk 7061 #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ 7062 #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ 7063 #define RTC_TSDR_DU_Pos (0U) 7064 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ 7065 #define RTC_TSDR_DU RTC_TSDR_DU_Msk 7066 #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ 7067 #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ 7068 #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ 7069 #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ 7070 7071 /******************** Bits definition for RTC_TSSSR register ****************/ 7072 #define RTC_TSSSR_SS_Pos (0U) 7073 #define RTC_TSSSR_SS_Msk (0xFFFFFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0xFFFFFFFF */ 7074 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk 7075 7076 /******************** Bits definition for RTC_ALRMAR register ***************/ 7077 #define RTC_ALRMAR_MSK4_Pos (31U) 7078 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ 7079 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk 7080 #define RTC_ALRMAR_WDSEL_Pos (30U) 7081 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ 7082 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk 7083 #define RTC_ALRMAR_DT_Pos (28U) 7084 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ 7085 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk 7086 #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ 7087 #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ 7088 #define RTC_ALRMAR_DU_Pos (24U) 7089 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ 7090 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk 7091 #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ 7092 #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ 7093 #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ 7094 #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ 7095 #define RTC_ALRMAR_MSK3_Pos (23U) 7096 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ 7097 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk 7098 #define RTC_ALRMAR_PM_Pos (22U) 7099 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ 7100 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk 7101 #define RTC_ALRMAR_HT_Pos (20U) 7102 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ 7103 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk 7104 #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ 7105 #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ 7106 #define RTC_ALRMAR_HU_Pos (16U) 7107 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ 7108 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk 7109 #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ 7110 #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ 7111 #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ 7112 #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ 7113 #define RTC_ALRMAR_MSK2_Pos (15U) 7114 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ 7115 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk 7116 #define RTC_ALRMAR_MNT_Pos (12U) 7117 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ 7118 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk 7119 #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ 7120 #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ 7121 #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ 7122 #define RTC_ALRMAR_MNU_Pos (8U) 7123 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ 7124 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk 7125 #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ 7126 #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ 7127 #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ 7128 #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ 7129 #define RTC_ALRMAR_MSK1_Pos (7U) 7130 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ 7131 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk 7132 #define RTC_ALRMAR_ST_Pos (4U) 7133 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ 7134 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk 7135 #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ 7136 #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ 7137 #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ 7138 #define RTC_ALRMAR_SU_Pos (0U) 7139 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ 7140 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk 7141 #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ 7142 #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ 7143 #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ 7144 #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ 7145 7146 /******************** Bits definition for RTC_ALRMASSR register *************/ 7147 #define RTC_ALRMASSR_SSCLR_Pos (31U) 7148 #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ 7149 #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk 7150 #define RTC_ALRMASSR_MASKSS_Pos (24U) 7151 #define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ 7152 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk 7153 #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ 7154 #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ 7155 #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ 7156 #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ 7157 #define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ 7158 #define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ 7159 #define RTC_ALRMASSR_SS_Pos (0U) 7160 #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ 7161 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk 7162 7163 /******************** Bits definition for RTC_ALRMBR register ***************/ 7164 #define RTC_ALRMBR_MSK4_Pos (31U) 7165 #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ 7166 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk 7167 #define RTC_ALRMBR_WDSEL_Pos (30U) 7168 #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ 7169 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk 7170 #define RTC_ALRMBR_DT_Pos (28U) 7171 #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ 7172 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk 7173 #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ 7174 #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ 7175 #define RTC_ALRMBR_DU_Pos (24U) 7176 #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ 7177 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk 7178 #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ 7179 #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ 7180 #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ 7181 #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ 7182 #define RTC_ALRMBR_MSK3_Pos (23U) 7183 #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ 7184 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk 7185 #define RTC_ALRMBR_PM_Pos (22U) 7186 #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ 7187 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk 7188 #define RTC_ALRMBR_HT_Pos (20U) 7189 #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ 7190 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk 7191 #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ 7192 #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ 7193 #define RTC_ALRMBR_HU_Pos (16U) 7194 #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ 7195 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk 7196 #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ 7197 #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ 7198 #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ 7199 #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ 7200 #define RTC_ALRMBR_MSK2_Pos (15U) 7201 #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ 7202 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk 7203 #define RTC_ALRMBR_MNT_Pos (12U) 7204 #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ 7205 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk 7206 #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ 7207 #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ 7208 #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ 7209 #define RTC_ALRMBR_MNU_Pos (8U) 7210 #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ 7211 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk 7212 #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ 7213 #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ 7214 #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ 7215 #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ 7216 #define RTC_ALRMBR_MSK1_Pos (7U) 7217 #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ 7218 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk 7219 #define RTC_ALRMBR_ST_Pos (4U) 7220 #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ 7221 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk 7222 #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ 7223 #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ 7224 #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ 7225 #define RTC_ALRMBR_SU_Pos (0U) 7226 #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ 7227 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk 7228 #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ 7229 #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ 7230 #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ 7231 #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ 7232 7233 /******************** Bits definition for RTC_ALRMBSSR register *************/ 7234 #define RTC_ALRMBSSR_SSCLR_Pos (31U) 7235 #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ 7236 #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk 7237 #define RTC_ALRMBSSR_MASKSS_Pos (24U) 7238 #define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ 7239 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk 7240 #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ 7241 #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ 7242 #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ 7243 #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ 7244 #define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ 7245 #define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ 7246 #define RTC_ALRMBSSR_SS_Pos (0U) 7247 #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ 7248 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk 7249 7250 /******************** Bits definition for RTC_SR register *******************/ 7251 #define RTC_SR_SSRUF_Pos (6U) 7252 #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ 7253 #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk 7254 #define RTC_SR_ITSF_Pos (5U) 7255 #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ 7256 #define RTC_SR_ITSF RTC_SR_ITSF_Msk 7257 #define RTC_SR_TSOVF_Pos (4U) 7258 #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ 7259 #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk 7260 #define RTC_SR_TSF_Pos (3U) 7261 #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ 7262 #define RTC_SR_TSF RTC_SR_TSF_Msk 7263 #define RTC_SR_WUTF_Pos (2U) 7264 #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ 7265 #define RTC_SR_WUTF RTC_SR_WUTF_Msk 7266 #define RTC_SR_ALRBF_Pos (1U) 7267 #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ 7268 #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk 7269 #define RTC_SR_ALRAF_Pos (0U) 7270 #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ 7271 #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk 7272 7273 /******************** Bits definition for RTC_MISR register *****************/ 7274 #define RTC_MISR_SSRUMF_Pos (6U) 7275 #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ 7276 #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk 7277 #define RTC_MISR_ITSMF_Pos (5U) 7278 #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ 7279 #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk 7280 #define RTC_MISR_TSOVMF_Pos (4U) 7281 #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ 7282 #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk 7283 #define RTC_MISR_TSMF_Pos (3U) 7284 #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ 7285 #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk 7286 #define RTC_MISR_WUTMF_Pos (2U) 7287 #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ 7288 #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk 7289 #define RTC_MISR_ALRBMF_Pos (1U) 7290 #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ 7291 #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk 7292 #define RTC_MISR_ALRAMF_Pos (0U) 7293 #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ 7294 #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk 7295 7296 /******************** Bits definition for RTC_SCR register ******************/ 7297 #define RTC_SCR_CSSRUF_Pos (6U) 7298 #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ 7299 #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk 7300 #define RTC_SCR_CITSF_Pos (5U) 7301 #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ 7302 #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk 7303 #define RTC_SCR_CTSOVF_Pos (4U) 7304 #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ 7305 #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk 7306 #define RTC_SCR_CTSF_Pos (3U) 7307 #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ 7308 #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk 7309 #define RTC_SCR_CWUTF_Pos (2U) 7310 #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ 7311 #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk 7312 #define RTC_SCR_CALRBF_Pos (1U) 7313 #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ 7314 #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk 7315 #define RTC_SCR_CALRAF_Pos (0U) 7316 #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ 7317 #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk 7318 7319 /******************** Bits definition for RTC_ALRABINR register ******************/ 7320 #define RTC_ALRABINR_SS_Pos (0U) 7321 #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ 7322 #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk 7323 7324 /******************** Bits definition for RTC_ALRBBINR register ******************/ 7325 #define RTC_ALRBBINR_SS_Pos (0U) 7326 #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ 7327 #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk 7328 7329 /******************************************************************************/ 7330 /* */ 7331 /* Serial Peripheral Interface (SPI) */ 7332 /* */ 7333 /******************************************************************************/ 7334 /******************* Bit definition for SPI_CR1 register ********************/ 7335 #define SPI_CR1_CPHA_Pos (0U) 7336 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ 7337 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */ 7338 #define SPI_CR1_CPOL_Pos (1U) 7339 #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ 7340 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */ 7341 #define SPI_CR1_MSTR_Pos (2U) 7342 #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ 7343 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */ 7344 7345 #define SPI_CR1_BR_Pos (3U) 7346 #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */ 7347 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */ 7348 #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */ 7349 #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */ 7350 #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */ 7351 7352 #define SPI_CR1_SPE_Pos (6U) 7353 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ 7354 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */ 7355 #define SPI_CR1_LSBFIRST_Pos (7U) 7356 #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ 7357 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */ 7358 #define SPI_CR1_SSI_Pos (8U) 7359 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ 7360 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */ 7361 #define SPI_CR1_SSM_Pos (9U) 7362 #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ 7363 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */ 7364 #define SPI_CR1_RXONLY_Pos (10U) 7365 #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ 7366 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */ 7367 #define SPI_CR1_CRCL_Pos (11U) 7368 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ 7369 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */ 7370 #define SPI_CR1_CRCNEXT_Pos (12U) 7371 #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ 7372 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */ 7373 #define SPI_CR1_CRCEN_Pos (13U) 7374 #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ 7375 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */ 7376 #define SPI_CR1_BIDIOE_Pos (14U) 7377 #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ 7378 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */ 7379 #define SPI_CR1_BIDIMODE_Pos (15U) 7380 #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ 7381 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */ 7382 7383 /******************* Bit definition for SPI_CR2 register ********************/ 7384 #define SPI_CR2_RXDMAEN_Pos (0U) 7385 #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ 7386 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ 7387 #define SPI_CR2_TXDMAEN_Pos (1U) 7388 #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ 7389 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ 7390 #define SPI_CR2_SSOE_Pos (2U) 7391 #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ 7392 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ 7393 #define SPI_CR2_NSSP_Pos (3U) 7394 #define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */ 7395 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */ 7396 #define SPI_CR2_FRF_Pos (4U) 7397 #define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */ 7398 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */ 7399 #define SPI_CR2_ERRIE_Pos (5U) 7400 #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ 7401 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ 7402 #define SPI_CR2_RXNEIE_Pos (6U) 7403 #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ 7404 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ 7405 #define SPI_CR2_TXEIE_Pos (7U) 7406 #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ 7407 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ 7408 #define SPI_CR2_DS_Pos (8U) 7409 #define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */ 7410 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */ 7411 #define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */ 7412 #define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */ 7413 #define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */ 7414 #define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */ 7415 #define SPI_CR2_FRXTH_Pos (12U) 7416 #define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */ 7417 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */ 7418 #define SPI_CR2_LDMARX_Pos (13U) 7419 #define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */ 7420 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */ 7421 #define SPI_CR2_LDMATX_Pos (14U) 7422 #define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */ 7423 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */ 7424 7425 /******************** Bit definition for SPI_SR register ********************/ 7426 #define SPI_SR_RXNE_Pos (0U) 7427 #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ 7428 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ 7429 #define SPI_SR_TXE_Pos (1U) 7430 #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */ 7431 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ 7432 #define SPI_SR_CHSIDE_Pos (2U) 7433 #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ 7434 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ 7435 #define SPI_SR_UDR_Pos (3U) 7436 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ 7437 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ 7438 #define SPI_SR_CRCERR_Pos (4U) 7439 #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ 7440 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ 7441 #define SPI_SR_MODF_Pos (5U) 7442 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */ 7443 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ 7444 #define SPI_SR_OVR_Pos (6U) 7445 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */ 7446 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ 7447 #define SPI_SR_BSY_Pos (7U) 7448 #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */ 7449 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ 7450 #define SPI_SR_FRE_Pos (8U) 7451 #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */ 7452 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */ 7453 #define SPI_SR_FRLVL_Pos (9U) 7454 #define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */ 7455 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */ 7456 #define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */ 7457 #define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */ 7458 #define SPI_SR_FTLVL_Pos (11U) 7459 #define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */ 7460 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */ 7461 #define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */ 7462 #define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */ 7463 7464 /******************** Bit definition for SPI_DR register ********************/ 7465 #define SPI_DR_DR_Pos (0U) 7466 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ 7467 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */ 7468 7469 /******************* Bit definition for SPI_CRCPR register ******************/ 7470 #define SPI_CRCPR_CRCPOLY_Pos (0U) 7471 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ 7472 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */ 7473 7474 /****************** Bit definition for SPI_RXCRCR register ******************/ 7475 #define SPI_RXCRCR_RXCRC_Pos (0U) 7476 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ 7477 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */ 7478 7479 /****************** Bit definition for SPI_TXCRCR register ******************/ 7480 #define SPI_TXCRCR_TXCRC_Pos (0U) 7481 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ 7482 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */ 7483 7484 /****************** Bit definition for SPI_I2SCFGR register *****************/ 7485 #define SPI_I2SCFGR_CHLEN_Pos (0U) 7486 #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */ 7487 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */ 7488 #define SPI_I2SCFGR_DATLEN_Pos (1U) 7489 #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */ 7490 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */ 7491 #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */ 7492 #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */ 7493 #define SPI_I2SCFGR_CKPOL_Pos (3U) 7494 #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */ 7495 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */ 7496 #define SPI_I2SCFGR_I2SSTD_Pos (4U) 7497 #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */ 7498 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */ 7499 #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */ 7500 #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */ 7501 #define SPI_I2SCFGR_PCMSYNC_Pos (7U) 7502 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */ 7503 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */ 7504 #define SPI_I2SCFGR_I2SCFG_Pos (8U) 7505 #define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */ 7506 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */ 7507 #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */ 7508 #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */ 7509 #define SPI_I2SCFGR_I2SE_Pos (10U) 7510 #define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */ 7511 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */ 7512 #define SPI_I2SCFGR_I2SMOD_Pos (11U) 7513 #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ 7514 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */ 7515 #define SPI_I2SCFGR_ASTRTEN_Pos (12U) 7516 #define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */ 7517 #define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */ 7518 7519 /****************** Bit definition for SPI_I2SPR register *******************/ 7520 #define SPI_I2SPR_I2SDIV_Pos (0U) 7521 #define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */ 7522 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */ 7523 #define SPI_I2SPR_ODD_Pos (8U) 7524 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */ 7525 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */ 7526 #define SPI_I2SPR_MCKOE_Pos (9U) 7527 #define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */ 7528 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */ 7529 7530 /******************************************************************************/ 7531 /* */ 7532 /* Tamper and backup register (TAMP) */ 7533 /* */ 7534 /******************************************************************************/ 7535 /******************** Bits definition for TAMP_CR1 register *****************/ 7536 #define TAMP_CR1_TAMP1E_Pos (0U) 7537 #define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ 7538 #define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk 7539 #define TAMP_CR1_TAMP2E_Pos (1U) 7540 #define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ 7541 #define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk 7542 #define TAMP_CR1_TAMP3E_Pos (2U) 7543 #define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ 7544 #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk 7545 #define TAMP_CR1_ITAMP3E_Pos (18U) 7546 #define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ 7547 #define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk 7548 #define TAMP_CR1_ITAMP5E_Pos (20U) 7549 #define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ 7550 #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk 7551 #define TAMP_CR1_ITAMP6E_Pos (21U) 7552 #define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x0020000 */ 7553 #define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk 7554 #define TAMP_CR1_ITAMP8E_Pos (23U) 7555 #define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ 7556 #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk 7557 7558 /******************** Bits definition for TAMP_CR2 register *****************/ 7559 #define TAMP_CR2_TAMP1NOERASE_Pos (0U) 7560 #define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ 7561 #define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk 7562 #define TAMP_CR2_TAMP2NOERASE_Pos (1U) 7563 #define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ 7564 #define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk 7565 #define TAMP_CR2_TAMP3NOERASE_Pos (2U) 7566 #define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ 7567 #define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk 7568 #define TAMP_CR2_TAMP1MSK_Pos (16U) 7569 #define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ 7570 #define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk 7571 #define TAMP_CR2_TAMP2MSK_Pos (17U) 7572 #define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ 7573 #define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk 7574 #define TAMP_CR2_TAMP3MSK_Pos (18U) 7575 #define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ 7576 #define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk 7577 #define TAMP_CR2_BKERASE_Pos (23U) 7578 #define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ 7579 #define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk 7580 #define TAMP_CR2_TAMP1TRG_Pos (24U) 7581 #define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ 7582 #define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk 7583 #define TAMP_CR2_TAMP2TRG_Pos (25U) 7584 #define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ 7585 #define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk 7586 #define TAMP_CR2_TAMP3TRG_Pos (26U) 7587 #define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ 7588 #define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk 7589 7590 /******************** Bits definition for TAMP_CR3 register *****************/ 7591 #define TAMP_CR3_ITAMP3NOER_Pos (2U) 7592 #define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ 7593 #define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk 7594 #define TAMP_CR3_ITAMP5NOER_Pos (4U) 7595 #define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ 7596 #define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk 7597 #define TAMP_CR3_ITAMP6NOER_Pos (5U) 7598 #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ 7599 #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk 7600 #define TAMP_CR3_ITAMP8NOER_Pos (7U) 7601 #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00800000 */ 7602 #define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk 7603 7604 /******************** Bits definition for TAMP_FLTCR register ***************/ 7605 #define TAMP_FLTCR_TAMPFREQ_Pos (0U) 7606 #define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ 7607 #define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk 7608 #define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ 7609 #define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ 7610 #define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ 7611 #define TAMP_FLTCR_TAMPFLT_Pos (3U) 7612 #define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ 7613 #define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk 7614 #define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ 7615 #define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ 7616 #define TAMP_FLTCR_TAMPPRCH_Pos (5U) 7617 #define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ 7618 #define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk 7619 #define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ 7620 #define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ 7621 #define TAMP_FLTCR_TAMPPUDIS_Pos (7U) 7622 #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ 7623 #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk 7624 7625 /******************** Bits definition for TAMP_IER register *****************/ 7626 #define TAMP_IER_TAMP1IE_Pos (0U) 7627 #define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ 7628 #define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk 7629 #define TAMP_IER_TAMP2IE_Pos (1U) 7630 #define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ 7631 #define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk 7632 #define TAMP_IER_TAMP3IE_Pos (2U) 7633 #define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ 7634 #define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk 7635 #define TAMP_IER_ITAMP3IE_Pos (18U) 7636 #define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ 7637 #define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk 7638 #define TAMP_IER_ITAMP5IE_Pos (20U) 7639 #define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ 7640 #define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk 7641 #define TAMP_IER_ITAMP6IE_Pos (21U) 7642 #define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x0020000 */ 7643 #define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk 7644 #define TAMP_IER_ITAMP8IE_Pos (23U) 7645 #define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ 7646 #define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk 7647 7648 /******************** Bits definition for TAMP_SR register *****************/ 7649 #define TAMP_SR_TAMP1F_Pos (0U) 7650 #define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ 7651 #define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk 7652 #define TAMP_SR_TAMP2F_Pos (1U) 7653 #define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ 7654 #define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk 7655 #define TAMP_SR_TAMP3F_Pos (2U) 7656 #define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ 7657 #define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk 7658 #define TAMP_SR_ITAMP3F_Pos (18U) 7659 #define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ 7660 #define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk 7661 #define TAMP_SR_ITAMP5F_Pos (20U) 7662 #define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ 7663 #define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk 7664 #define TAMP_SR_ITAMP6F_Pos (21U) 7665 #define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x0020000 */ 7666 #define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk 7667 #define TAMP_SR_ITAMP8F_Pos (23U) 7668 #define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ 7669 #define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk 7670 7671 /******************** Bits definition for TAMP_MISR register ************ *****/ 7672 #define TAMP_MISR_TAMP1MF_Pos (0U) 7673 #define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ 7674 #define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk 7675 #define TAMP_MISR_TAMP2MF_Pos (1U) 7676 #define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ 7677 #define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk 7678 #define TAMP_MISR_TAMP3MF_Pos (2U) 7679 #define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ 7680 #define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk 7681 #define TAMP_MISR_ITAMP3MF_Pos (18U) 7682 #define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ 7683 #define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk 7684 #define TAMP_MISR_ITAMP5MF_Pos (20U) 7685 #define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ 7686 #define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk 7687 #define TAMP_MISR_ITAMP6MF_Pos (21U) 7688 #define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x0020000 */ 7689 #define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk 7690 #define TAMP_MISR_ITAMP8MF_Pos (23U) 7691 #define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ 7692 #define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk 7693 7694 /******************** Bits definition for TAMP_SMISR register ************ *****/ 7695 #define TAMP_SMISR_TAMP1MF_Pos (0U) 7696 #define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ 7697 #define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk 7698 #define TAMP_SMISR_TAMP2MF_Pos (1U) 7699 #define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ 7700 #define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk 7701 #define TAMP_SMISR_TAMP3MF_Pos (2U) 7702 #define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ 7703 #define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk 7704 #define TAMP_SMISR_ITAMP3MF_Pos (18U) 7705 #define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ 7706 #define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk 7707 #define TAMP_SMISR_ITAMP5MF_Pos (20U) 7708 #define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ 7709 #define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk 7710 #define TAMP_SMISR_ITAMP6MF_Pos (21U) 7711 #define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x0020000 */ 7712 #define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk 7713 #define TAMP_SMISR_ITAMP8MF_Pos (23U) 7714 #define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ 7715 #define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk 7716 7717 /******************** Bits definition for TAMP_SCR register *****************/ 7718 #define TAMP_SCR_CTAMP1F_Pos (0U) 7719 #define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ 7720 #define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk 7721 #define TAMP_SCR_CTAMP2F_Pos (1U) 7722 #define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ 7723 #define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk 7724 #define TAMP_SCR_CTAMP3F_Pos (2U) 7725 #define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ 7726 #define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk 7727 #define TAMP_SCR_CITAMP3F_Pos (18U) 7728 #define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ 7729 #define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk 7730 #define TAMP_SCR_CITAMP5F_Pos (20U) 7731 #define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ 7732 #define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk 7733 #define TAMP_SCR_CITAMP6F_Pos (21U) 7734 #define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x0020000 */ 7735 #define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk 7736 #define TAMP_SCR_CITAMP8F_Pos (23U) 7737 #define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ 7738 #define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk 7739 7740 /******************** Bits definition for TAMP_COUNTR register ***************/ 7741 #define TAMP_COUNTR_Pos (0U) 7742 #define TAMP_COUNTR_Msk (0xFFFFFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFFFFFF */ 7743 #define TAMP_COUNTR TAMP_COUNTR_Msk 7744 7745 /******************** Bits definition for TAMP_BKP0R register ***************/ 7746 #define TAMP_BKP0R_Pos (0U) 7747 #define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ 7748 #define TAMP_BKP0R TAMP_BKP0R_Msk 7749 7750 /******************** Bits definition for TAMP_BKP1R register ****************/ 7751 #define TAMP_BKP1R_Pos (0U) 7752 #define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ 7753 #define TAMP_BKP1R TAMP_BKP1R_Msk 7754 7755 /******************** Bits definition for TAMP_BKP2R register ****************/ 7756 #define TAMP_BKP2R_Pos (0U) 7757 #define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ 7758 #define TAMP_BKP2R TAMP_BKP2R_Msk 7759 7760 /******************** Bits definition for TAMP_BKP3R register ****************/ 7761 #define TAMP_BKP3R_Pos (0U) 7762 #define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ 7763 #define TAMP_BKP3R TAMP_BKP3R_Msk 7764 7765 /******************** Bits definition for TAMP_BKP4R register ****************/ 7766 #define TAMP_BKP4R_Pos (0U) 7767 #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ 7768 #define TAMP_BKP4R TAMP_BKP4R_Msk 7769 7770 /******************** Bits definition for TAMP_BKP5R register ****************/ 7771 #define TAMP_BKP5R_Pos (0U) 7772 #define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ 7773 #define TAMP_BKP5R TAMP_BKP5R_Msk 7774 7775 /******************** Bits definition for TAMP_BKP6R register ****************/ 7776 #define TAMP_BKP6R_Pos (0U) 7777 #define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ 7778 #define TAMP_BKP6R TAMP_BKP6R_Msk 7779 7780 /******************** Bits definition for TAMP_BKP7R register ****************/ 7781 #define TAMP_BKP7R_Pos (0U) 7782 #define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ 7783 #define TAMP_BKP7R TAMP_BKP7R_Msk 7784 7785 /******************** Bits definition for TAMP_BKP8R register ****************/ 7786 #define TAMP_BKP8R_Pos (0U) 7787 #define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ 7788 #define TAMP_BKP8R TAMP_BKP8R_Msk 7789 7790 /******************** Bits definition for TAMP_BKP9R register ****************/ 7791 #define TAMP_BKP9R_Pos (0U) 7792 #define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ 7793 #define TAMP_BKP9R TAMP_BKP9R_Msk 7794 7795 /******************** Bits definition for TAMP_BKP10R register ***************/ 7796 #define TAMP_BKP10R_Pos (0U) 7797 #define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ 7798 #define TAMP_BKP10R TAMP_BKP10R_Msk 7799 7800 /******************** Bits definition for TAMP_BKP11R register ***************/ 7801 #define TAMP_BKP11R_Pos (0U) 7802 #define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ 7803 #define TAMP_BKP11R TAMP_BKP11R_Msk 7804 7805 /******************** Bits definition for TAMP_BKP12R register ***************/ 7806 #define TAMP_BKP12R_Pos (0U) 7807 #define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ 7808 #define TAMP_BKP12R TAMP_BKP12R_Msk 7809 7810 /******************** Bits definition for TAMP_BKP13R register ***************/ 7811 #define TAMP_BKP13R_Pos (0U) 7812 #define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ 7813 #define TAMP_BKP13R TAMP_BKP13R_Msk 7814 7815 /******************** Bits definition for TAMP_BKP14R register ***************/ 7816 #define TAMP_BKP14R_Pos (0U) 7817 #define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ 7818 #define TAMP_BKP14R TAMP_BKP14R_Msk 7819 7820 /******************** Bits definition for TAMP_BKP15R register ***************/ 7821 #define TAMP_BKP15R_Pos (0U) 7822 #define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ 7823 #define TAMP_BKP15R TAMP_BKP15R_Msk 7824 7825 /******************** Bits definition for TAMP_BKP16R register ***************/ 7826 #define TAMP_BKP16R_Pos (0U) 7827 #define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ 7828 #define TAMP_BKP16R TAMP_BKP16R_Msk 7829 7830 /******************** Bits definition for TAMP_BKP17R register ***************/ 7831 #define TAMP_BKP17R_Pos (0U) 7832 #define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ 7833 #define TAMP_BKP17R TAMP_BKP17R_Msk 7834 7835 /******************** Bits definition for TAMP_BKP18R register ***************/ 7836 #define TAMP_BKP18R_Pos (0U) 7837 #define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ 7838 #define TAMP_BKP18R TAMP_BKP18R_Msk 7839 7840 /******************** Bits definition for TAMP_BKP19R register ***************/ 7841 #define TAMP_BKP19R_Pos (0U) 7842 #define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ 7843 #define TAMP_BKP19R TAMP_BKP19R_Msk 7844 7845 /******************************************************************************/ 7846 /* */ 7847 /* SYSCFG */ 7848 /* */ 7849 /******************************************************************************/ 7850 /***************** Bit definition for SYSCFG_MEMRMP register (SYSCFG memory remap register) ***********************************/ 7851 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U) 7852 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */ 7853 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */ 7854 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */ 7855 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */ 7856 #define SYSCFG_MEMRMP_MEM_MODE_2 (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */ 7857 7858 /***************** Bit definition for SYSCFG_CFGR1 register (SYSCFG configuration register 1) ****************************************************************/ 7859 #define SYSCFG_CFGR1_BOOSTEN_Pos (8U) 7860 #define SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */ 7861 #define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */ 7862 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U) 7863 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */ 7864 #define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< Fast-mode Plus (Fm+) driving capability activation on PB6 */ 7865 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U) 7866 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */ 7867 #define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< Fast-mode Plus (Fm+) driving capability activation on PB7 */ 7868 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U) 7869 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */ 7870 #define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< Fast-mode Plus (Fm+) driving capability activation on PB8 */ 7871 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U) 7872 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */ 7873 #define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< Fast-mode Plus (Fm+) driving capability activation on PB9 */ 7874 #define SYSCFG_CFGR1_I2C1_FMP_Pos (20U) 7875 #define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */ 7876 #define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast-mode Plus (Fm+) driving capability activation */ 7877 #define SYSCFG_CFGR1_I2C2_FMP_Pos (21U) 7878 #define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */ 7879 #define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk /*!< I2C2 Fast-mode Plus (Fm+) driving capability activation */ 7880 #define SYSCFG_CFGR1_I2C3_FMP_Pos (22U) 7881 #define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos) /*!< 0x00400000 */ 7882 #define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk /*!< I2C3 Fast-mode Plus (Fm+) driving capability activation */ 7883 7884 /***************** Bit definition for SYSCFG_EXTICR1 register (External interrupt configuration register 1) ********************************/ 7885 #define SYSCFG_EXTICR1_EXTI0_Pos (0U) 7886 #define SYSCFG_EXTICR1_EXTI0_Msk (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */ 7887 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< External Interrupt Line 0 configuration */ 7888 #define SYSCFG_EXTICR1_EXTI1_Pos (4U) 7889 #define SYSCFG_EXTICR1_EXTI1_Msk (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x00000070 */ 7890 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< External Interrupt Line 1 configuration */ 7891 #define SYSCFG_EXTICR1_EXTI2_Pos (8U) 7892 #define SYSCFG_EXTICR1_EXTI2_Msk (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000700 */ 7893 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< External Interrupt Line 2 configuration */ 7894 #define SYSCFG_EXTICR1_EXTI3_Pos (12U) 7895 #define SYSCFG_EXTICR1_EXTI3_Msk (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x00007000 */ 7896 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< External Interrupt Line 3 configuration */ 7897 7898 /** 7899 * @brief External Interrupt Line 0 Source Input configuration 7900 */ 7901 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */ 7902 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */ 7903 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */ 7904 7905 /** 7906 * @brief External Interrupt Line 1 Source Input configuration 7907 */ 7908 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */ 7909 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */ 7910 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */ 7911 7912 /** 7913 * @brief External Interrupt Line 2 Source Input configuration 7914 */ 7915 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */ 7916 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */ 7917 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */ 7918 7919 /** 7920 * @brief External Interrupt Line 3 Source Input configuration 7921 */ 7922 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */ 7923 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */ 7924 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */ 7925 7926 /***************** Bit definition for SYSCFG_EXTICR2 register (External interrupt configuration register 2) ********************************/ 7927 #define SYSCFG_EXTICR2_EXTI4_Pos (0U) 7928 #define SYSCFG_EXTICR2_EXTI4_Msk (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */ 7929 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< External Interrupt Line 4 configuration */ 7930 #define SYSCFG_EXTICR2_EXTI5_Pos (4U) 7931 #define SYSCFG_EXTICR2_EXTI5_Msk (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x00000070 */ 7932 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< External Interrupt Line 5 configuration */ 7933 #define SYSCFG_EXTICR2_EXTI6_Pos (8U) 7934 #define SYSCFG_EXTICR2_EXTI6_Msk (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000700 */ 7935 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< External Interrupt Line 6 configuration */ 7936 #define SYSCFG_EXTICR2_EXTI7_Pos (12U) 7937 #define SYSCFG_EXTICR2_EXTI7_Msk (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x00007000 */ 7938 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< External Interrupt Line 7 configuration */ 7939 7940 /** 7941 * @brief External Interrupt Line 4 Source Input configuration 7942 */ 7943 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */ 7944 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */ 7945 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */ 7946 7947 /** 7948 * @brief External Interrupt Line 5 Source Input configuration 7949 */ 7950 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */ 7951 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */ 7952 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */ 7953 7954 /** 7955 * @brief External Interrupt Line 6 Source Input configuration 7956 */ 7957 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */ 7958 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */ 7959 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */ 7960 7961 /** 7962 * @brief External Interrupt Line 7 Source Input configuration 7963 */ 7964 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */ 7965 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */ 7966 7967 /***************** Bit definition for SYSCFG_EXTICR3 register (External interrupt configuration register 3) ********************************/ 7968 #define SYSCFG_EXTICR3_EXTI8_Pos (0U) 7969 #define SYSCFG_EXTICR3_EXTI8_Msk (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */ 7970 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< External Interrupt Line 8 configuration */ 7971 #define SYSCFG_EXTICR3_EXTI9_Pos (4U) 7972 #define SYSCFG_EXTICR3_EXTI9_Msk (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x00000070 */ 7973 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< External Interrupt Line 9 configuration */ 7974 #define SYSCFG_EXTICR3_EXTI10_Pos (8U) 7975 #define SYSCFG_EXTICR3_EXTI10_Msk (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000700 */ 7976 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< External Interrupt Line 10 configuration */ 7977 #define SYSCFG_EXTICR3_EXTI11_Pos (12U) 7978 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ 7979 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< External Interrupt Line 11 configuration */ 7980 7981 /** 7982 * @brief External Interrupt Line 8 Source Input configuration 7983 */ 7984 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */ 7985 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */ 7986 7987 /** 7988 * @brief External Interrupt Line 9 Source Input configuration 7989 */ 7990 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */ 7991 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */ 7992 7993 /** 7994 * @brief External Interrupt Line 10 Source Input configuration 7995 */ 7996 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */ 7997 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */ 7998 7999 /** 8000 * @brief External Interrupt Line 11 Source Input configuration 8001 */ 8002 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */ 8003 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */ 8004 8005 /***************** Bit definition for SYSCFG_EXTICR4 register (External interrupt configuration register 4) *********************************/ 8006 #define SYSCFG_EXTICR4_EXTI12_Pos (0U) 8007 #define SYSCFG_EXTICR4_EXTI12_Msk (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */ 8008 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< External Interrupt Line 12 configuration */ 8009 #define SYSCFG_EXTICR4_EXTI13_Pos (4U) 8010 #define SYSCFG_EXTICR4_EXTI13_Msk (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x00000070 */ 8011 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< External Interrupt Line 13 configuration */ 8012 #define SYSCFG_EXTICR4_EXTI14_Pos (8U) 8013 #define SYSCFG_EXTICR4_EXTI14_Msk (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000700 */ 8014 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< External Interrupt Line 14 configuration */ 8015 #define SYSCFG_EXTICR4_EXTI15_Pos (12U) 8016 #define SYSCFG_EXTICR4_EXTI15_Msk (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x00007000 */ 8017 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< External Interrupt Line 15 configuration */ 8018 8019 /** 8020 * @brief External Interrupt Line 12 Source Input configuration 8021 */ 8022 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */ 8023 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */ 8024 8025 /** 8026 * @brief External Interrupt Line 13 Source Input configuration 8027 */ 8028 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */ 8029 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */ 8030 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */ 8031 8032 /** 8033 * @brief External Interrupt Line 14 Source Input configuration 8034 */ 8035 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */ 8036 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */ 8037 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */ 8038 8039 /** 8040 * @brief External Interrupt Line 15 Source Input configuration 8041 */ 8042 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */ 8043 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */ 8044 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */ 8045 8046 /***************** Bit definition for SYSCFG_SCSR register (SYSCFG SRAM control and status register) **********************************************************/ 8047 #define SYSCFG_SCSR_SRAM2ER_Pos (0U) 8048 #define SYSCFG_SCSR_SRAM2ER_Msk (0x1UL << SYSCFG_SCSR_SRAM2ER_Pos) /*!< 0x00000001 */ 8049 #define SYSCFG_SCSR_SRAM2ER SYSCFG_SCSR_SRAM2ER_Msk /*!< SRAM2 Erase */ 8050 #define SYSCFG_SCSR_SRAMBSY_Pos (1U) 8051 #define SYSCFG_SCSR_SRAMBSY_Msk (0x1UL << SYSCFG_SCSR_SRAMBSY_Pos) /*!< 0x00000002 */ 8052 #define SYSCFG_SCSR_SRAMBSY SYSCFG_SCSR_SRAMBSY_Msk /*!< SRAM2 and SRAM1 busy by erase operation */ 8053 #define SYSCFG_SCSR_PKASRAMBSY_Pos (8U) 8054 #define SYSCFG_SCSR_PKASRAMBSY_Msk (0x1UL << SYSCFG_SCSR_PKASRAMBSY_Pos) /*!< 0x00000100 */ 8055 #define SYSCFG_SCSR_PKASRAMBSY SYSCFG_SCSR_PKASRAMBSY_Msk /*!< PKA SRAM busy by erase operation */ 8056 8057 /***************** Bit definition for SYSCFG_CFGR2 register (SYSCFG configuration register 2) *****************************************************************/ 8058 #define SYSCFG_CFGR2_CLL_Pos (0U) 8059 #define SYSCFG_CFGR2_CLL_Msk (0x1UL << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */ 8060 #define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Cortex M4 LOCKUP (hardfault) output enable */ 8061 #define SYSCFG_CFGR2_SPL_Pos (1U) 8062 #define SYSCFG_CFGR2_SPL_Msk (0x1UL << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */ 8063 #define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< SRAM2 Parity Lock */ 8064 #define SYSCFG_CFGR2_PVDL_Pos (2U) 8065 #define SYSCFG_CFGR2_PVDL_Msk (0x1UL << SYSCFG_CFGR2_PVDL_Pos) /*!< 0x00000004 */ 8066 #define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk /*!< PVD Lock */ 8067 #define SYSCFG_CFGR2_ECCL_Pos (3U) 8068 #define SYSCFG_CFGR2_ECCL_Msk (0x1UL << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */ 8069 #define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECC Lock */ 8070 #define SYSCFG_CFGR2_SPF_Pos (8U) 8071 #define SYSCFG_CFGR2_SPF_Msk (0x1UL << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */ 8072 #define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM2 Parity Lock */ 8073 8074 /***************** Bit definition for SYSCFG_SWPR register (SYSCFG SRAM2 write protection register) ***********************************************************/ 8075 #define SYSCFG_SWPR_PAGE0_Pos (0U) 8076 #define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */ 8077 #define SYSCFG_SWPR_PAGE0 SYSCFG_SWPR_PAGE0_Msk /*!< SRAM2 Write protection page 0 (0x20008000 - 0x200083FF) */ 8078 #define SYSCFG_SWPR_PAGE1_Pos (1U) 8079 #define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */ 8080 #define SYSCFG_SWPR_PAGE1 SYSCFG_SWPR_PAGE1_Msk /*!< SRAM2 Write protection page 1 (0x20008400 - 0x200087FF) */ 8081 #define SYSCFG_SWPR_PAGE2_Pos (2U) 8082 #define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */ 8083 #define SYSCFG_SWPR_PAGE2 SYSCFG_SWPR_PAGE2_Msk /*!< SRAM2 Write protection page 2 (0x20008800 - 0x20008BFF) */ 8084 #define SYSCFG_SWPR_PAGE3_Pos (3U) 8085 #define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */ 8086 #define SYSCFG_SWPR_PAGE3 SYSCFG_SWPR_PAGE3_Msk /*!< SRAM2 Write protection page 3 (0x20008C00 - 0x20008FFF) */ 8087 #define SYSCFG_SWPR_PAGE4_Pos (4U) 8088 #define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */ 8089 #define SYSCFG_SWPR_PAGE4 SYSCFG_SWPR_PAGE4_Msk /*!< SRAM2 Write protection page 4 (0x20009000 - 0x200093FF) */ 8090 #define SYSCFG_SWPR_PAGE5_Pos (5U) 8091 #define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */ 8092 #define SYSCFG_SWPR_PAGE5 SYSCFG_SWPR_PAGE5_Msk /*!< SRAM2 Write protection page 5 (0x20009400 - 0x200097FF) */ 8093 #define SYSCFG_SWPR_PAGE6_Pos (6U) 8094 #define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */ 8095 #define SYSCFG_SWPR_PAGE6 SYSCFG_SWPR_PAGE6_Msk /*!< SRAM2 Write protection page 6 (0x20009800 - 0x20009BFF) */ 8096 #define SYSCFG_SWPR_PAGE7_Pos (7U) 8097 #define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */ 8098 #define SYSCFG_SWPR_PAGE7 SYSCFG_SWPR_PAGE7_Msk /*!< SRAM2 Write protection page 7 (0x20009C00 - 0x20009FFF) */ 8099 #define SYSCFG_SWPR_PAGE8_Pos (8U) 8100 #define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */ 8101 #define SYSCFG_SWPR_PAGE8 SYSCFG_SWPR_PAGE8_Msk /*!< SRAM2 Write protection page 8 (0x2000A000 - 0x2000A3FF) */ 8102 #define SYSCFG_SWPR_PAGE9_Pos (9U) 8103 #define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */ 8104 #define SYSCFG_SWPR_PAGE9 SYSCFG_SWPR_PAGE9_Msk /*!< SRAM2 Write protection page 9 (0x2000A400 - 0x2000A7FF) */ 8105 #define SYSCFG_SWPR_PAGE10_Pos (10U) 8106 #define SYSCFG_SWPR_PAGE10_Msk (0x1UL << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */ 8107 #define SYSCFG_SWPR_PAGE10 SYSCFG_SWPR_PAGE10_Msk /*!< SRAM2 Write protection page 10 (0x2000A800 - 0x2000ABFF) */ 8108 #define SYSCFG_SWPR_PAGE11_Pos (11U) 8109 #define SYSCFG_SWPR_PAGE11_Msk (0x1UL << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */ 8110 #define SYSCFG_SWPR_PAGE11 SYSCFG_SWPR_PAGE11_Msk /*!< SRAM2 Write protection page 11 (0x2000AC00 - 0x2000AFFF) */ 8111 #define SYSCFG_SWPR_PAGE12_Pos (12U) 8112 #define SYSCFG_SWPR_PAGE12_Msk (0x1UL << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */ 8113 #define SYSCFG_SWPR_PAGE12 SYSCFG_SWPR_PAGE12_Msk /*!< SRAM2 Write protection page 12 (0x2000B000 - 0x2000B3FF) */ 8114 #define SYSCFG_SWPR_PAGE13_Pos (13U) 8115 #define SYSCFG_SWPR_PAGE13_Msk (0x1UL << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */ 8116 #define SYSCFG_SWPR_PAGE13 SYSCFG_SWPR_PAGE13_Msk /*!< SRAM2 Write protection page 13 (0x2000B400 - 0x2000B7FF) */ 8117 #define SYSCFG_SWPR_PAGE14_Pos (14U) 8118 #define SYSCFG_SWPR_PAGE14_Msk (0x1UL << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */ 8119 #define SYSCFG_SWPR_PAGE14 SYSCFG_SWPR_PAGE14_Msk /*!< SRAM2 Write protection page 14 (0x2000B800 - 0x2000BBFF) */ 8120 #define SYSCFG_SWPR_PAGE15_Pos (15U) 8121 #define SYSCFG_SWPR_PAGE15_Msk (0x1UL << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */ 8122 #define SYSCFG_SWPR_PAGE15 SYSCFG_SWPR_PAGE15_Msk /*!< SRAM2 Write protection page 15 (0x2000BC00 - 0x2000BFFF) */ 8123 #define SYSCFG_SWPR_PAGE16_Pos (16U) 8124 #define SYSCFG_SWPR_PAGE16_Msk (0x1UL << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */ 8125 #define SYSCFG_SWPR_PAGE16 SYSCFG_SWPR_PAGE16_Msk /*!< SRAM2 Write protection page 16 (0x2000C000 - 0x2000C3FF) */ 8126 #define SYSCFG_SWPR_PAGE17_Pos (17U) 8127 #define SYSCFG_SWPR_PAGE17_Msk (0x1UL << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */ 8128 #define SYSCFG_SWPR_PAGE17 SYSCFG_SWPR_PAGE17_Msk /*!< SRAM2 Write protection page 17 (0x2000C400 - 0x2000C7FF) */ 8129 #define SYSCFG_SWPR_PAGE18_Pos (18U) 8130 #define SYSCFG_SWPR_PAGE18_Msk (0x1UL << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */ 8131 #define SYSCFG_SWPR_PAGE18 SYSCFG_SWPR_PAGE18_Msk /*!< SRAM2 Write protection page 18 (0x2000C800 - 0x2000CBFF) */ 8132 #define SYSCFG_SWPR_PAGE19_Pos (19U) 8133 #define SYSCFG_SWPR_PAGE19_Msk (0x1UL << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */ 8134 #define SYSCFG_SWPR_PAGE19 SYSCFG_SWPR_PAGE19_Msk /*!< SRAM2 Write protection page 19 (0x2000CC00 - 0x2000CFFF) */ 8135 #define SYSCFG_SWPR_PAGE20_Pos (20U) 8136 #define SYSCFG_SWPR_PAGE20_Msk (0x1UL << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */ 8137 #define SYSCFG_SWPR_PAGE20 SYSCFG_SWPR_PAGE20_Msk /*!< SRAM2 Write protection page 20 (0x2000D000 - 0x2000D3FF) */ 8138 #define SYSCFG_SWPR_PAGE21_Pos (21U) 8139 #define SYSCFG_SWPR_PAGE21_Msk (0x1UL << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */ 8140 #define SYSCFG_SWPR_PAGE21 SYSCFG_SWPR_PAGE21_Msk /*!< SRAM2 Write protection page 21 (0x2000D400 - 0x2000D7FF) */ 8141 #define SYSCFG_SWPR_PAGE22_Pos (22U) 8142 #define SYSCFG_SWPR_PAGE22_Msk (0x1UL << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */ 8143 #define SYSCFG_SWPR_PAGE22 SYSCFG_SWPR_PAGE22_Msk /*!< SRAM2 Write protection page 22 (0x2000D800 - 0x2000DBFF) */ 8144 #define SYSCFG_SWPR_PAGE23_Pos (23U) 8145 #define SYSCFG_SWPR_PAGE23_Msk (0x1UL << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */ 8146 #define SYSCFG_SWPR_PAGE23 SYSCFG_SWPR_PAGE23_Msk /*!< SRAM2 Write protection page 23 (0x2000DC00 - 0x2000DFFF) */ 8147 #define SYSCFG_SWPR_PAGE24_Pos (24U) 8148 #define SYSCFG_SWPR_PAGE24_Msk (0x1UL << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */ 8149 #define SYSCFG_SWPR_PAGE24 SYSCFG_SWPR_PAGE24_Msk /*!< SRAM2 Write protection page 24 (0x2000E000 - 0x2000E3FF) */ 8150 #define SYSCFG_SWPR_PAGE25_Pos (25U) 8151 #define SYSCFG_SWPR_PAGE25_Msk (0x1UL << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */ 8152 #define SYSCFG_SWPR_PAGE25 SYSCFG_SWPR_PAGE25_Msk /*!< SRAM2 Write protection page 25 (0x2000E400 - 0x2000E7FF) */ 8153 #define SYSCFG_SWPR_PAGE26_Pos (26U) 8154 #define SYSCFG_SWPR_PAGE26_Msk (0x1UL << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */ 8155 #define SYSCFG_SWPR_PAGE26 SYSCFG_SWPR_PAGE26_Msk /*!< SRAM2 Write protection page 26 (0x2000E800 - 0x2000EBFF) */ 8156 #define SYSCFG_SWPR_PAGE27_Pos (27U) 8157 #define SYSCFG_SWPR_PAGE27_Msk (0x1UL << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */ 8158 #define SYSCFG_SWPR_PAGE27 SYSCFG_SWPR_PAGE27_Msk /*!< SRAM2 Write protection page 27 (0x2000EC00 - 0x2000EFFF) */ 8159 #define SYSCFG_SWPR_PAGE28_Pos (28U) 8160 #define SYSCFG_SWPR_PAGE28_Msk (0x1UL << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */ 8161 #define SYSCFG_SWPR_PAGE28 SYSCFG_SWPR_PAGE28_Msk /*!< SRAM2 Write protection page 28 (0x2000F000 - 0x2000F3FF) */ 8162 #define SYSCFG_SWPR_PAGE29_Pos (29U) 8163 #define SYSCFG_SWPR_PAGE29_Msk (0x1UL << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */ 8164 #define SYSCFG_SWPR_PAGE29 SYSCFG_SWPR_PAGE29_Msk /*!< SRAM2 Write protection page 29 (0x2000F400 - 0x2000F7FF) */ 8165 #define SYSCFG_SWPR_PAGE30_Pos (30U) 8166 #define SYSCFG_SWPR_PAGE30_Msk (0x1UL << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */ 8167 #define SYSCFG_SWPR_PAGE30 SYSCFG_SWPR_PAGE30_Msk /*!< SRAM2 Write protection page 30 (0x2000F800 - 0x2000FBFF) */ 8168 #define SYSCFG_SWPR_PAGE31_Pos (31U) 8169 #define SYSCFG_SWPR_PAGE31_Msk (0x1UL << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */ 8170 #define SYSCFG_SWPR_PAGE31 SYSCFG_SWPR_PAGE31_Msk /*!< SRAM2 Write protection page 31 (0x2000FC00 - 0x2000FFFF) */ 8171 8172 /***************** Bit definition for SYSCFG_SKR register (SYSCFG SRAM2 key register) *************************************************************************/ 8173 #define SYSCFG_SKR_KEY_Pos (0U) 8174 #define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */ 8175 #define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk /*!< SRAM2 write protection key for software erase */ 8176 8177 /************************************** Bit definition for SYSCFG_RFDCR register (SYSCFG radio debug control register) ************************************************/ 8178 #define SYSCFG_RFDCR_RFTBSEL_Pos (0U) 8179 #define SYSCFG_RFDCR_RFTBSEL_Msk (0x1UL << SYSCFG_RFDCR_RFTBSEL_Pos) /*!< 0x00000001 */ 8180 #define SYSCFG_RFDCR_RFTBSEL SYSCFG_RFDCR_RFTBSEL_Msk /*!< Radio debug test bus selection */ 8181 8182 /******************************************************************************/ 8183 /* */ 8184 /* Inter-integrated Circuit Interface (I2C) */ 8185 /* */ 8186 /******************************************************************************/ 8187 /******************* Bit definition for I2C_CR1 register *******************/ 8188 #define I2C_CR1_PE_Pos (0U) 8189 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ 8190 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ 8191 #define I2C_CR1_TXIE_Pos (1U) 8192 #define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ 8193 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ 8194 #define I2C_CR1_RXIE_Pos (2U) 8195 #define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ 8196 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ 8197 #define I2C_CR1_ADDRIE_Pos (3U) 8198 #define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ 8199 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ 8200 #define I2C_CR1_NACKIE_Pos (4U) 8201 #define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ 8202 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ 8203 #define I2C_CR1_STOPIE_Pos (5U) 8204 #define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ 8205 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ 8206 #define I2C_CR1_TCIE_Pos (6U) 8207 #define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ 8208 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ 8209 #define I2C_CR1_ERRIE_Pos (7U) 8210 #define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ 8211 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ 8212 #define I2C_CR1_DNF_Pos (8U) 8213 #define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ 8214 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ 8215 #define I2C_CR1_ANFOFF_Pos (12U) 8216 #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ 8217 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ 8218 #define I2C_CR1_TXDMAEN_Pos (14U) 8219 #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ 8220 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ 8221 #define I2C_CR1_RXDMAEN_Pos (15U) 8222 #define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ 8223 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ 8224 #define I2C_CR1_SBC_Pos (16U) 8225 #define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ 8226 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ 8227 #define I2C_CR1_NOSTRETCH_Pos (17U) 8228 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ 8229 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ 8230 #define I2C_CR1_WUPEN_Pos (18U) 8231 #define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ 8232 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ 8233 #define I2C_CR1_GCEN_Pos (19U) 8234 #define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ 8235 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ 8236 #define I2C_CR1_SMBHEN_Pos (20U) 8237 #define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ 8238 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ 8239 #define I2C_CR1_SMBDEN_Pos (21U) 8240 #define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ 8241 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ 8242 #define I2C_CR1_ALERTEN_Pos (22U) 8243 #define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ 8244 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ 8245 #define I2C_CR1_PECEN_Pos (23U) 8246 #define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ 8247 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ 8248 8249 /****************** Bit definition for I2C_CR2 register ********************/ 8250 #define I2C_CR2_SADD_Pos (0U) 8251 #define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ 8252 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ 8253 #define I2C_CR2_RD_WRN_Pos (10U) 8254 #define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ 8255 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ 8256 #define I2C_CR2_ADD10_Pos (11U) 8257 #define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ 8258 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ 8259 #define I2C_CR2_HEAD10R_Pos (12U) 8260 #define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ 8261 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ 8262 #define I2C_CR2_START_Pos (13U) 8263 #define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ 8264 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ 8265 #define I2C_CR2_STOP_Pos (14U) 8266 #define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ 8267 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ 8268 #define I2C_CR2_NACK_Pos (15U) 8269 #define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ 8270 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ 8271 #define I2C_CR2_NBYTES_Pos (16U) 8272 #define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ 8273 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ 8274 #define I2C_CR2_RELOAD_Pos (24U) 8275 #define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ 8276 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ 8277 #define I2C_CR2_AUTOEND_Pos (25U) 8278 #define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ 8279 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ 8280 #define I2C_CR2_PECBYTE_Pos (26U) 8281 #define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ 8282 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ 8283 8284 /******************* Bit definition for I2C_OAR1 register ******************/ 8285 #define I2C_OAR1_OA1_Pos (0U) 8286 #define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ 8287 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ 8288 #define I2C_OAR1_OA1MODE_Pos (10U) 8289 #define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ 8290 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ 8291 #define I2C_OAR1_OA1EN_Pos (15U) 8292 #define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ 8293 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ 8294 8295 /******************* Bit definition for I2C_OAR2 register ******************/ 8296 #define I2C_OAR2_OA2_Pos (1U) 8297 #define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ 8298 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ 8299 #define I2C_OAR2_OA2MSK_Pos (8U) 8300 #define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ 8301 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ 8302 #define I2C_OAR2_OA2NOMASK (0x00000000UL) /*!< No mask */ 8303 #define I2C_OAR2_OA2MASK01_Pos (8U) 8304 #define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ 8305 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ 8306 #define I2C_OAR2_OA2MASK02_Pos (9U) 8307 #define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ 8308 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ 8309 #define I2C_OAR2_OA2MASK03_Pos (8U) 8310 #define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ 8311 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ 8312 #define I2C_OAR2_OA2MASK04_Pos (10U) 8313 #define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ 8314 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ 8315 #define I2C_OAR2_OA2MASK05_Pos (8U) 8316 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ 8317 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ 8318 #define I2C_OAR2_OA2MASK06_Pos (9U) 8319 #define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ 8320 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ 8321 #define I2C_OAR2_OA2MASK07_Pos (8U) 8322 #define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ 8323 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ 8324 #define I2C_OAR2_OA2EN_Pos (15U) 8325 #define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ 8326 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ 8327 8328 /******************* Bit definition for I2C_TIMINGR register *******************/ 8329 #define I2C_TIMINGR_SCLL_Pos (0U) 8330 #define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ 8331 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ 8332 #define I2C_TIMINGR_SCLH_Pos (8U) 8333 #define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ 8334 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ 8335 #define I2C_TIMINGR_SDADEL_Pos (16U) 8336 #define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ 8337 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ 8338 #define I2C_TIMINGR_SCLDEL_Pos (20U) 8339 #define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ 8340 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ 8341 #define I2C_TIMINGR_PRESC_Pos (28U) 8342 #define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ 8343 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ 8344 8345 /******************* Bit definition for I2C_TIMEOUTR register *******************/ 8346 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) 8347 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ 8348 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ 8349 #define I2C_TIMEOUTR_TIDLE_Pos (12U) 8350 #define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ 8351 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ 8352 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) 8353 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ 8354 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ 8355 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) 8356 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ 8357 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ 8358 #define I2C_TIMEOUTR_TEXTEN_Pos (31U) 8359 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ 8360 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ 8361 8362 /****************** Bit definition for I2C_ISR register *********************/ 8363 #define I2C_ISR_TXE_Pos (0U) 8364 #define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ 8365 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ 8366 #define I2C_ISR_TXIS_Pos (1U) 8367 #define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ 8368 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ 8369 #define I2C_ISR_RXNE_Pos (2U) 8370 #define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ 8371 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ 8372 #define I2C_ISR_ADDR_Pos (3U) 8373 #define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ 8374 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ 8375 #define I2C_ISR_NACKF_Pos (4U) 8376 #define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ 8377 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ 8378 #define I2C_ISR_STOPF_Pos (5U) 8379 #define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ 8380 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ 8381 #define I2C_ISR_TC_Pos (6U) 8382 #define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ 8383 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ 8384 #define I2C_ISR_TCR_Pos (7U) 8385 #define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ 8386 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ 8387 #define I2C_ISR_BERR_Pos (8U) 8388 #define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ 8389 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ 8390 #define I2C_ISR_ARLO_Pos (9U) 8391 #define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ 8392 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ 8393 #define I2C_ISR_OVR_Pos (10U) 8394 #define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ 8395 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ 8396 #define I2C_ISR_PECERR_Pos (11U) 8397 #define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ 8398 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ 8399 #define I2C_ISR_TIMEOUT_Pos (12U) 8400 #define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ 8401 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ 8402 #define I2C_ISR_ALERT_Pos (13U) 8403 #define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ 8404 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ 8405 #define I2C_ISR_BUSY_Pos (15U) 8406 #define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ 8407 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ 8408 #define I2C_ISR_DIR_Pos (16U) 8409 #define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ 8410 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ 8411 #define I2C_ISR_ADDCODE_Pos (17U) 8412 #define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ 8413 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ 8414 8415 /****************** Bit definition for I2C_ICR register *********************/ 8416 #define I2C_ICR_ADDRCF_Pos (3U) 8417 #define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ 8418 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ 8419 #define I2C_ICR_NACKCF_Pos (4U) 8420 #define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ 8421 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ 8422 #define I2C_ICR_STOPCF_Pos (5U) 8423 #define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ 8424 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ 8425 #define I2C_ICR_BERRCF_Pos (8U) 8426 #define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ 8427 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ 8428 #define I2C_ICR_ARLOCF_Pos (9U) 8429 #define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ 8430 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ 8431 #define I2C_ICR_OVRCF_Pos (10U) 8432 #define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ 8433 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ 8434 #define I2C_ICR_PECCF_Pos (11U) 8435 #define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ 8436 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ 8437 #define I2C_ICR_TIMOUTCF_Pos (12U) 8438 #define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ 8439 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ 8440 #define I2C_ICR_ALERTCF_Pos (13U) 8441 #define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ 8442 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ 8443 8444 /****************** Bit definition for I2C_PECR register *********************/ 8445 #define I2C_PECR_PEC_Pos (0U) 8446 #define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ 8447 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ 8448 8449 /****************** Bit definition for I2C_RXDR register *********************/ 8450 #define I2C_RXDR_RXDATA_Pos (0U) 8451 #define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ 8452 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ 8453 8454 /****************** Bit definition for I2C_TXDR register *********************/ 8455 #define I2C_TXDR_TXDATA_Pos (0U) 8456 #define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ 8457 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ 8458 8459 8460 8461 /******************************************************************************/ 8462 /* */ 8463 /* Independent WATCHDOG (IWDG) */ 8464 /* */ 8465 /******************************************************************************/ 8466 /******************* Bit definition for IWDG_KR register ********************/ 8467 #define IWDG_KR_KEY_Pos (0U) 8468 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ 8469 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */ 8470 8471 /******************* Bit definition for IWDG_PR register ********************/ 8472 #define IWDG_PR_PR_Pos (0U) 8473 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */ 8474 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */ 8475 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */ 8476 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */ 8477 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */ 8478 8479 /******************* Bit definition for IWDG_RLR register *******************/ 8480 #define IWDG_RLR_RL_Pos (0U) 8481 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ 8482 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */ 8483 8484 /******************* Bit definition for IWDG_SR register ********************/ 8485 #define IWDG_SR_PVU_Pos (0U) 8486 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ 8487 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ 8488 #define IWDG_SR_RVU_Pos (1U) 8489 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ 8490 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ 8491 #define IWDG_SR_WVU_Pos (2U) 8492 #define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */ 8493 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */ 8494 8495 /******************* Bit definition for IWDG_KR register ********************/ 8496 #define IWDG_WINR_WIN_Pos (0U) 8497 #define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */ 8498 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */ 8499 8500 /******************************************************************************/ 8501 /* */ 8502 /* VREFBUF */ 8503 /* */ 8504 /******************************************************************************/ 8505 /******************* Bit definition for VREFBUF_CSR register ****************/ 8506 #define VREFBUF_CSR_ENVR_Pos (0U) 8507 #define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */ 8508 #define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */ 8509 #define VREFBUF_CSR_HIZ_Pos (1U) 8510 #define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */ 8511 #define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */ 8512 #define VREFBUF_CSR_VRS_Pos (2U) 8513 #define VREFBUF_CSR_VRS_Msk (0x1UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000004 */ 8514 #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference buffer ready */ 8515 #define VREFBUF_CSR_VRR_Pos (3U) 8516 #define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */ 8517 #define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference scale */ 8518 8519 /******************* Bit definition for VREFBUF_CCR register ******************/ 8520 #define VREFBUF_CCR_TRIM_Pos (0U) 8521 #define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */ 8522 #define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */ 8523 8524 /******************************************************************************/ 8525 /* */ 8526 /* Window WATCHDOG */ 8527 /* */ 8528 /******************************************************************************/ 8529 /******************* Bit definition for WWDG_CR register ********************/ 8530 #define WWDG_CR_T_Pos (0U) 8531 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */ 8532 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */ 8533 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */ 8534 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */ 8535 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */ 8536 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */ 8537 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */ 8538 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */ 8539 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */ 8540 8541 #define WWDG_CR_WDGA_Pos (7U) 8542 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ 8543 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */ 8544 8545 /******************* Bit definition for WWDG_CFR register *******************/ 8546 #define WWDG_CFR_W_Pos (0U) 8547 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */ 8548 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */ 8549 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */ 8550 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */ 8551 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */ 8552 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */ 8553 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */ 8554 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */ 8555 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */ 8556 8557 #define WWDG_CFR_EWI_Pos (9U) 8558 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ 8559 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */ 8560 8561 #define WWDG_CFR_WDGTB_Pos (11U) 8562 #define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00003800 */ 8563 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[2:0] bits (Timer Base) */ 8564 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000800 */ 8565 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00001000 */ 8566 #define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00002000 */ 8567 8568 /******************* Bit definition for WWDG_SR register ********************/ 8569 #define WWDG_SR_EWIF_Pos (0U) 8570 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ 8571 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */ 8572 8573 8574 /******************************************************************************/ 8575 /* */ 8576 /* Debug MCU */ 8577 /* */ 8578 /******************************************************************************/ 8579 /******************** Bit definition for DBGMCU_IDCODE register *************/ 8580 #define DBGMCU_IDCODE_DEV_ID_Pos (0U) 8581 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ 8582 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk 8583 #define DBGMCU_IDCODE_REV_ID_Pos (16U) 8584 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)/*!< 0xFFFF0000 */ 8585 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk 8586 8587 /******************** Bit definition for DBGMCU_CR register *****************/ 8588 #define DBGMCU_CR_DBG_SLEEP_Pos (0U) 8589 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ 8590 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk 8591 #define DBGMCU_CR_DBG_STOP_Pos (1U) 8592 #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ 8593 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk 8594 #define DBGMCU_CR_DBG_STANDBY_Pos (2U) 8595 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)/*!< 0x00000004 */ 8596 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk 8597 8598 /******************** Bit definition for DBGMCU_APB1FZR1 register ***********/ 8599 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U) 8600 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ 8601 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk 8602 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U) 8603 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ 8604 #define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk 8605 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U) 8606 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ 8607 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk 8608 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U) 8609 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ 8610 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk 8611 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U) 8612 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */ 8613 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk 8614 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos (22U) 8615 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */ 8616 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk 8617 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (23U) 8618 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */ 8619 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk 8620 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U) 8621 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)/*!< 0x80000000 */ 8622 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk 8623 8624 /******************** Bit definition for DBGMCU_APB1FZR2 register ***********/ 8625 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos (5U) 8626 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos)/*!< 0x00000020 */ 8627 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk 8628 #define DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Pos (6U) 8629 #define DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Pos)/*!< 0x00000040 */ 8630 #define DBGMCU_APB1FZR2_DBG_LPTIM3_STOP DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Msk 8631 8632 /******************** Bit definition for DBGMCU_APB2FZR register ************/ 8633 #define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos (11U) 8634 #define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos)/*!< 0x000000800 */ 8635 #define DBGMCU_APB2FZR_DBG_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk 8636 #define DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos (17U) 8637 #define DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */ 8638 #define DBGMCU_APB2FZR_DBG_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk 8639 #define DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos (18U) 8640 #define DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */ 8641 #define DBGMCU_APB2FZR_DBG_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk 8642 8643 8644 /******************************************************************************/ 8645 /* */ 8646 /* TIM */ 8647 /* */ 8648 /******************************************************************************/ 8649 /******************* Bit definition for TIM_CR1 register ********************/ 8650 #define TIM_CR1_CEN_Pos (0U) 8651 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ 8652 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ 8653 #define TIM_CR1_UDIS_Pos (1U) 8654 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ 8655 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ 8656 #define TIM_CR1_URS_Pos (2U) 8657 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */ 8658 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ 8659 #define TIM_CR1_OPM_Pos (3U) 8660 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ 8661 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ 8662 #define TIM_CR1_DIR_Pos (4U) 8663 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ 8664 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ 8665 8666 #define TIM_CR1_CMS_Pos (5U) 8667 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ 8668 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ 8669 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ 8670 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ 8671 8672 #define TIM_CR1_ARPE_Pos (7U) 8673 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ 8674 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ 8675 8676 #define TIM_CR1_CKD_Pos (8U) 8677 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ 8678 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ 8679 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ 8680 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ 8681 8682 #define TIM_CR1_UIFREMAP_Pos (11U) 8683 #define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */ 8684 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */ 8685 8686 /******************* Bit definition for TIM_CR2 register ********************/ 8687 #define TIM_CR2_CCPC_Pos (0U) 8688 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */ 8689 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */ 8690 #define TIM_CR2_CCUS_Pos (2U) 8691 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */ 8692 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */ 8693 #define TIM_CR2_CCDS_Pos (3U) 8694 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ 8695 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ 8696 8697 #define TIM_CR2_MMS_Pos (4U) 8698 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ 8699 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ 8700 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ 8701 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ 8702 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ 8703 8704 #define TIM_CR2_TI1S_Pos (7U) 8705 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ 8706 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ 8707 #define TIM_CR2_OIS1_Pos (8U) 8708 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */ 8709 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */ 8710 #define TIM_CR2_OIS1N_Pos (9U) 8711 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */ 8712 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */ 8713 #define TIM_CR2_OIS2_Pos (10U) 8714 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */ 8715 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */ 8716 #define TIM_CR2_OIS2N_Pos (11U) 8717 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */ 8718 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */ 8719 #define TIM_CR2_OIS3_Pos (12U) 8720 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */ 8721 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */ 8722 #define TIM_CR2_OIS3N_Pos (13U) 8723 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */ 8724 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */ 8725 #define TIM_CR2_OIS4_Pos (14U) 8726 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */ 8727 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */ 8728 #define TIM_CR2_OIS5_Pos (16U) 8729 #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */ 8730 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */ 8731 #define TIM_CR2_OIS6_Pos (18U) 8732 #define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */ 8733 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */ 8734 8735 #define TIM_CR2_MMS2_Pos (20U) 8736 #define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */ 8737 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ 8738 #define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */ 8739 #define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */ 8740 #define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */ 8741 #define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */ 8742 8743 /******************* Bit definition for TIM_SMCR register *******************/ 8744 #define TIM_SMCR_SMS_Pos (0U) 8745 #define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */ 8746 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ 8747 #define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */ 8748 #define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ 8749 #define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ 8750 #define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */ 8751 8752 #define TIM_SMCR_OCCS_Pos (3U) 8753 #define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */ 8754 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */ 8755 8756 #define TIM_SMCR_TS_Pos (4U) 8757 #define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) /*!< 0x00300070 */ 8758 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ 8759 #define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ 8760 #define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ 8761 #define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ 8762 #define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos) /*!< 0x00100000 */ 8763 #define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos) /*!< 0x00200000 */ 8764 8765 #define TIM_SMCR_MSM_Pos (7U) 8766 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ 8767 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ 8768 8769 #define TIM_SMCR_ETF_Pos (8U) 8770 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ 8771 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ 8772 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ 8773 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ 8774 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ 8775 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ 8776 8777 #define TIM_SMCR_ETPS_Pos (12U) 8778 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ 8779 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ 8780 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ 8781 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ 8782 8783 #define TIM_SMCR_ECE_Pos (14U) 8784 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ 8785 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ 8786 #define TIM_SMCR_ETP_Pos (15U) 8787 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ 8788 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ 8789 8790 /******************* Bit definition for TIM_DIER register *******************/ 8791 #define TIM_DIER_UIE_Pos (0U) 8792 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ 8793 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ 8794 #define TIM_DIER_CC1IE_Pos (1U) 8795 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ 8796 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ 8797 #define TIM_DIER_CC2IE_Pos (2U) 8798 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ 8799 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ 8800 #define TIM_DIER_CC3IE_Pos (3U) 8801 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ 8802 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ 8803 #define TIM_DIER_CC4IE_Pos (4U) 8804 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ 8805 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ 8806 #define TIM_DIER_COMIE_Pos (5U) 8807 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */ 8808 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */ 8809 #define TIM_DIER_TIE_Pos (6U) 8810 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ 8811 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ 8812 #define TIM_DIER_BIE_Pos (7U) 8813 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */ 8814 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */ 8815 #define TIM_DIER_UDE_Pos (8U) 8816 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ 8817 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ 8818 #define TIM_DIER_CC1DE_Pos (9U) 8819 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ 8820 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ 8821 #define TIM_DIER_CC2DE_Pos (10U) 8822 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ 8823 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ 8824 #define TIM_DIER_CC3DE_Pos (11U) 8825 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ 8826 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ 8827 #define TIM_DIER_CC4DE_Pos (12U) 8828 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ 8829 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ 8830 #define TIM_DIER_COMDE_Pos (13U) 8831 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */ 8832 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */ 8833 #define TIM_DIER_TDE_Pos (14U) 8834 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ 8835 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ 8836 8837 /******************** Bit definition for TIM_SR register ********************/ 8838 #define TIM_SR_UIF_Pos (0U) 8839 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */ 8840 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ 8841 #define TIM_SR_CC1IF_Pos (1U) 8842 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ 8843 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ 8844 #define TIM_SR_CC2IF_Pos (2U) 8845 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ 8846 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ 8847 #define TIM_SR_CC3IF_Pos (3U) 8848 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ 8849 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ 8850 #define TIM_SR_CC4IF_Pos (4U) 8851 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ 8852 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ 8853 #define TIM_SR_COMIF_Pos (5U) 8854 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */ 8855 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */ 8856 #define TIM_SR_TIF_Pos (6U) 8857 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */ 8858 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ 8859 #define TIM_SR_BIF_Pos (7U) 8860 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */ 8861 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */ 8862 #define TIM_SR_B2IF_Pos (8U) 8863 #define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */ 8864 #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */ 8865 #define TIM_SR_CC1OF_Pos (9U) 8866 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ 8867 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ 8868 #define TIM_SR_CC2OF_Pos (10U) 8869 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ 8870 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ 8871 #define TIM_SR_CC3OF_Pos (11U) 8872 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ 8873 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ 8874 #define TIM_SR_CC4OF_Pos (12U) 8875 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ 8876 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ 8877 #define TIM_SR_SBIF_Pos (13U) 8878 #define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */ 8879 #define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */ 8880 #define TIM_SR_CC5IF_Pos (16U) 8881 #define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */ 8882 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */ 8883 #define TIM_SR_CC6IF_Pos (17U) 8884 #define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */ 8885 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */ 8886 8887 8888 /******************* Bit definition for TIM_EGR register ********************/ 8889 #define TIM_EGR_UG_Pos (0U) 8890 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */ 8891 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ 8892 #define TIM_EGR_CC1G_Pos (1U) 8893 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ 8894 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ 8895 #define TIM_EGR_CC2G_Pos (2U) 8896 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ 8897 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ 8898 #define TIM_EGR_CC3G_Pos (3U) 8899 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ 8900 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ 8901 #define TIM_EGR_CC4G_Pos (4U) 8902 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ 8903 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ 8904 #define TIM_EGR_COMG_Pos (5U) 8905 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */ 8906 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */ 8907 #define TIM_EGR_TG_Pos (6U) 8908 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */ 8909 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ 8910 #define TIM_EGR_BG_Pos (7U) 8911 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */ 8912 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */ 8913 #define TIM_EGR_B2G_Pos (8U) 8914 #define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */ 8915 #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */ 8916 8917 /****************** Bit definition for TIM_CCMR1 register *******************/ 8918 #define TIM_CCMR1_CC1S_Pos (0U) 8919 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ 8920 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ 8921 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ 8922 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ 8923 8924 #define TIM_CCMR1_OC1FE_Pos (2U) 8925 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ 8926 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ 8927 #define TIM_CCMR1_OC1PE_Pos (3U) 8928 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ 8929 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ 8930 8931 #define TIM_CCMR1_OC1M_Pos (4U) 8932 #define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */ 8933 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ 8934 #define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */ 8935 #define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */ 8936 #define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */ 8937 #define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */ 8938 8939 #define TIM_CCMR1_OC1CE_Pos (7U) 8940 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ 8941 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */ 8942 8943 #define TIM_CCMR1_CC2S_Pos (8U) 8944 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ 8945 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ 8946 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ 8947 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ 8948 8949 #define TIM_CCMR1_OC2FE_Pos (10U) 8950 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ 8951 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ 8952 #define TIM_CCMR1_OC2PE_Pos (11U) 8953 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ 8954 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ 8955 8956 #define TIM_CCMR1_OC2M_Pos (12U) 8957 #define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */ 8958 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ 8959 #define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */ 8960 #define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */ 8961 #define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */ 8962 #define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */ 8963 8964 #define TIM_CCMR1_OC2CE_Pos (15U) 8965 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ 8966 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ 8967 8968 /*----------------------------------------------------------------------------*/ 8969 #define TIM_CCMR1_IC1PSC_Pos (2U) 8970 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ 8971 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ 8972 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ 8973 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ 8974 8975 #define TIM_CCMR1_IC1F_Pos (4U) 8976 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ 8977 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ 8978 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ 8979 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ 8980 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ 8981 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ 8982 8983 #define TIM_CCMR1_IC2PSC_Pos (10U) 8984 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ 8985 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ 8986 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ 8987 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ 8988 8989 #define TIM_CCMR1_IC2F_Pos (12U) 8990 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ 8991 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ 8992 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ 8993 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ 8994 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ 8995 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ 8996 8997 /****************** Bit definition for TIM_CCMR2 register *******************/ 8998 #define TIM_CCMR2_CC3S_Pos (0U) 8999 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ 9000 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ 9001 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ 9002 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ 9003 9004 #define TIM_CCMR2_OC3FE_Pos (2U) 9005 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ 9006 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ 9007 #define TIM_CCMR2_OC3PE_Pos (3U) 9008 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ 9009 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ 9010 9011 #define TIM_CCMR2_OC3M_Pos (4U) 9012 #define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */ 9013 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ 9014 #define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */ 9015 #define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */ 9016 #define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */ 9017 #define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */ 9018 9019 #define TIM_CCMR2_OC3CE_Pos (7U) 9020 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ 9021 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ 9022 9023 #define TIM_CCMR2_CC4S_Pos (8U) 9024 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ 9025 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ 9026 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ 9027 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ 9028 9029 #define TIM_CCMR2_OC4FE_Pos (10U) 9030 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ 9031 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ 9032 #define TIM_CCMR2_OC4PE_Pos (11U) 9033 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ 9034 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ 9035 9036 #define TIM_CCMR2_OC4M_Pos (12U) 9037 #define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */ 9038 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ 9039 #define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */ 9040 #define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */ 9041 #define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */ 9042 #define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */ 9043 9044 #define TIM_CCMR2_OC4CE_Pos (15U) 9045 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ 9046 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ 9047 9048 /*----------------------------------------------------------------------------*/ 9049 #define TIM_CCMR2_IC3PSC_Pos (2U) 9050 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ 9051 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ 9052 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ 9053 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ 9054 9055 #define TIM_CCMR2_IC3F_Pos (4U) 9056 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ 9057 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ 9058 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ 9059 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ 9060 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ 9061 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ 9062 9063 #define TIM_CCMR2_IC4PSC_Pos (10U) 9064 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ 9065 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ 9066 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ 9067 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ 9068 9069 #define TIM_CCMR2_IC4F_Pos (12U) 9070 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ 9071 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ 9072 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ 9073 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ 9074 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ 9075 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ 9076 9077 /****************** Bit definition for TIM_CCMR3 register *******************/ 9078 #define TIM_CCMR3_OC5FE_Pos (2U) 9079 #define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */ 9080 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */ 9081 #define TIM_CCMR3_OC5PE_Pos (3U) 9082 #define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */ 9083 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */ 9084 9085 #define TIM_CCMR3_OC5M_Pos (4U) 9086 #define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */ 9087 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */ 9088 #define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */ 9089 #define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */ 9090 #define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */ 9091 #define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */ 9092 9093 #define TIM_CCMR3_OC5CE_Pos (7U) 9094 #define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */ 9095 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */ 9096 9097 #define TIM_CCMR3_OC6FE_Pos (10U) 9098 #define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */ 9099 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */ 9100 #define TIM_CCMR3_OC6PE_Pos (11U) 9101 #define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */ 9102 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */ 9103 9104 #define TIM_CCMR3_OC6M_Pos (12U) 9105 #define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */ 9106 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */ 9107 #define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */ 9108 #define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */ 9109 #define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */ 9110 #define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */ 9111 9112 #define TIM_CCMR3_OC6CE_Pos (15U) 9113 #define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */ 9114 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */ 9115 9116 /******************* Bit definition for TIM_CCER register *******************/ 9117 #define TIM_CCER_CC1E_Pos (0U) 9118 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ 9119 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ 9120 #define TIM_CCER_CC1P_Pos (1U) 9121 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ 9122 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ 9123 #define TIM_CCER_CC1NE_Pos (2U) 9124 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */ 9125 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */ 9126 #define TIM_CCER_CC1NP_Pos (3U) 9127 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ 9128 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ 9129 #define TIM_CCER_CC2E_Pos (4U) 9130 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ 9131 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ 9132 #define TIM_CCER_CC2P_Pos (5U) 9133 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ 9134 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ 9135 #define TIM_CCER_CC2NE_Pos (6U) 9136 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */ 9137 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */ 9138 #define TIM_CCER_CC2NP_Pos (7U) 9139 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ 9140 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ 9141 #define TIM_CCER_CC3E_Pos (8U) 9142 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ 9143 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ 9144 #define TIM_CCER_CC3P_Pos (9U) 9145 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ 9146 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ 9147 #define TIM_CCER_CC3NE_Pos (10U) 9148 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */ 9149 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */ 9150 #define TIM_CCER_CC3NP_Pos (11U) 9151 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ 9152 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ 9153 #define TIM_CCER_CC4E_Pos (12U) 9154 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ 9155 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ 9156 #define TIM_CCER_CC4P_Pos (13U) 9157 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ 9158 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ 9159 #define TIM_CCER_CC4NP_Pos (15U) 9160 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */ 9161 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */ 9162 #define TIM_CCER_CC5E_Pos (16U) 9163 #define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */ 9164 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */ 9165 #define TIM_CCER_CC5P_Pos (17U) 9166 #define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */ 9167 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */ 9168 #define TIM_CCER_CC6E_Pos (20U) 9169 #define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */ 9170 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */ 9171 #define TIM_CCER_CC6P_Pos (21U) 9172 #define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */ 9173 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */ 9174 9175 /******************* Bit definition for TIM_CNT register ********************/ 9176 #define TIM_CNT_CNT_Pos (0U) 9177 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ 9178 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ 9179 #define TIM_CNT_UIFCPY_Pos (31U) 9180 #define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */ 9181 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */ 9182 9183 /******************* Bit definition for TIM_PSC register ********************/ 9184 #define TIM_PSC_PSC_Pos (0U) 9185 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ 9186 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ 9187 9188 /******************* Bit definition for TIM_ARR register ********************/ 9189 #define TIM_ARR_ARR_Pos (0U) 9190 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ 9191 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */ 9192 9193 /******************* Bit definition for TIM_RCR register ********************/ 9194 #define TIM_RCR_REP_Pos (0U) 9195 #define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */ 9196 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */ 9197 9198 /******************* Bit definition for TIM_CCR1 register *******************/ 9199 #define TIM_CCR1_CCR1_Pos (0U) 9200 #define TIM_CCR1_CCR1_Msk (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0xFFFFFFFF */ 9201 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ 9202 9203 /******************* Bit definition for TIM_CCR2 register *******************/ 9204 #define TIM_CCR2_CCR2_Pos (0U) 9205 #define TIM_CCR2_CCR2_Msk (0xFFFFFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0xFFFFFFFF */ 9206 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ 9207 9208 /******************* Bit definition for TIM_CCR3 register *******************/ 9209 #define TIM_CCR3_CCR3_Pos (0U) 9210 #define TIM_CCR3_CCR3_Msk (0xFFFFFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0xFFFFFFFF */ 9211 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ 9212 9213 /******************* Bit definition for TIM_CCR4 register *******************/ 9214 #define TIM_CCR4_CCR4_Pos (0U) 9215 #define TIM_CCR4_CCR4_Msk (0xFFFFFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0xFFFFFFFF */ 9216 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ 9217 9218 /******************* Bit definition for TIM_CCR5 register *******************/ 9219 #define TIM_CCR5_CCR5_Pos (0U) 9220 #define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0x0000FFFF */ 9221 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ 9222 #define TIM_CCR5_GC5C1_Pos (29U) 9223 #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ 9224 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */ 9225 #define TIM_CCR5_GC5C2_Pos (30U) 9226 #define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */ 9227 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */ 9228 #define TIM_CCR5_GC5C3_Pos (31U) 9229 #define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */ 9230 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */ 9231 9232 /******************* Bit definition for TIM_CCR6 register *******************/ 9233 #define TIM_CCR6_CCR6_Pos (0U) 9234 #define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */ 9235 #define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */ 9236 9237 /******************* Bit definition for TIM_BDTR register *******************/ 9238 #define TIM_BDTR_DTG_Pos (0U) 9239 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ 9240 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ 9241 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */ 9242 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */ 9243 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */ 9244 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */ 9245 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */ 9246 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */ 9247 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */ 9248 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */ 9249 9250 #define TIM_BDTR_LOCK_Pos (8U) 9251 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */ 9252 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */ 9253 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */ 9254 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */ 9255 9256 #define TIM_BDTR_OSSI_Pos (10U) 9257 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */ 9258 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */ 9259 #define TIM_BDTR_OSSR_Pos (11U) 9260 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */ 9261 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */ 9262 #define TIM_BDTR_BKE_Pos (12U) 9263 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */ 9264 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */ 9265 #define TIM_BDTR_BKP_Pos (13U) 9266 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */ 9267 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */ 9268 #define TIM_BDTR_AOE_Pos (14U) 9269 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */ 9270 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */ 9271 #define TIM_BDTR_MOE_Pos (15U) 9272 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */ 9273 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */ 9274 9275 #define TIM_BDTR_BKF_Pos (16U) 9276 #define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */ 9277 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */ 9278 #define TIM_BDTR_BK2F_Pos (20U) 9279 #define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */ 9280 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */ 9281 9282 #define TIM_BDTR_BK2E_Pos (24U) 9283 #define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */ 9284 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */ 9285 #define TIM_BDTR_BK2P_Pos (25U) 9286 #define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */ 9287 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */ 9288 9289 9290 #define TIM_BDTR_BKDSRM_Pos (26U) 9291 #define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */ 9292 #define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */ 9293 #define TIM_BDTR_BK2DSRM_Pos (27U) 9294 #define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */ 9295 #define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */ 9296 9297 #define TIM_BDTR_BKBID_Pos (28U) 9298 #define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */ 9299 #define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break BIDirectional */ 9300 #define TIM_BDTR_BK2BID_Pos (29U) 9301 #define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */ 9302 #define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 BIDirectional */ 9303 /******************* Bit definition for TIM_DCR register ********************/ 9304 #define TIM_DCR_DBA_Pos (0U) 9305 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ 9306 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ 9307 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ 9308 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ 9309 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ 9310 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ 9311 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ 9312 9313 #define TIM_DCR_DBL_Pos (8U) 9314 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ 9315 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ 9316 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ 9317 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ 9318 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ 9319 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ 9320 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ 9321 9322 /******************* Bit definition for TIM_DMAR register *******************/ 9323 #define TIM_DMAR_DMAB_Pos (0U) 9324 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ 9325 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ 9326 9327 /******************* Bit definition for TIM1_OR1 register ******************/ 9328 #define TIM1_OR1_ETR_ADC_RMP_Pos (0U) 9329 #define TIM1_OR1_ETR_ADC_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC_RMP_Pos) /*!< 0x00000003 */ 9330 #define TIM1_OR1_ETR_ADC_RMP TIM1_OR1_ETR_ADC_RMP_Msk /*!< TIM1_ETR_ADC remapping capability */ 9331 #define TIM1_OR1_ETR_ADC_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC_RMP_Pos) /*!< 0x00000001 */ 9332 #define TIM1_OR1_ETR_ADC_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC_RMP_Pos) /*!< 0x00000002 */ 9333 #define TIM1_OR1_TI1_RMP_Pos (4U) 9334 #define TIM1_OR1_TI1_RMP_Msk (0x1UL << TIM1_OR1_TI1_RMP_Pos) /*!< 0x00000010 */ 9335 #define TIM1_OR1_TI1_RMP TIM1_OR1_TI1_RMP_Msk /*!< Input Capture 1 remap*/ 9336 9337 /******************* Bit definition for TIM2_OR1 register ******************/ 9338 #define TIM2_OR1_TI4_RMP_Pos (2U) 9339 #define TIM2_OR1_TI4_RMP_Msk (0x3UL << TIM2_OR1_TI4_RMP_Pos) /*!< 0x0000000C */ 9340 #define TIM2_OR1_TI4_RMP TIM2_OR1_TI4_RMP_Msk /*!< TI4 RMA[1:0]Input capture 4 remap*/ 9341 #define TIM2_OR1_TI4_RMP_0 (0x1UL << TIM2_OR1_TI4_RMP_Pos) /*!< 0x00000004 */ 9342 #define TIM2_OR1_TI4_RMP_1 (0x2UL << TIM2_OR1_TI4_RMP_Pos) /*!< 0x00000008 */ 9343 #define TIM2_OR1_ETR_RMP_Pos (1U) 9344 #define TIM2_OR1_ETR_RMP_Msk (0x1UL << TIM2_OR1_ETR_RMP_Pos) /*!< 0x00000002 */ 9345 #define TIM2_OR1_ETR_RMP TIM2_OR1_ETR_RMP_Msk /*!< External trigger remap*/ 9346 9347 /******************* Bit definition for TIM16_OR1 register *****************/ 9348 #define TIM16_OR1_TI1_RMP_Pos (0U) 9349 #define TIM16_OR1_TI1_RMP_Msk (0x3UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000003 */ 9350 #define TIM16_OR1_TI1_RMP TIM16_OR1_TI1_RMP_Msk /*!<Timer 16 input 1 connection. */ 9351 #define TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */ 9352 #define TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */ 9353 9354 /******************* Bit definition for TIM17_OR1 register *****************/ 9355 #define TIM17_OR1_TI1_RMP_Pos (0U) 9356 #define TIM17_OR1_TI1_RMP_Msk (0x3UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000003 */ 9357 #define TIM17_OR1_TI1_RMP TIM17_OR1_TI1_RMP_Msk /*!<Timer 17 input 1 connection. */ 9358 #define TIM17_OR1_TI1_RMP_0 (0x1UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000001 */ 9359 #define TIM17_OR1_TI1_RMP_1 (0x2UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000002 */ 9360 9361 /******************* Bit definition for TIM1_AF1 register *******************/ 9362 #define TIM1_AF1_BKINE_Pos (0U) 9363 #define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */ 9364 #define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BRK BKIN input enable */ 9365 #define TIM1_AF1_BKCMP1E_Pos (1U) 9366 #define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos) /*!< 0x00000002 */ 9367 #define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */ 9368 #define TIM1_AF1_BKCMP2E_Pos (2U) 9369 #define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos) /*!< 0x00000004 */ 9370 #define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */ 9371 #define TIM1_AF1_BKINP_Pos (9U) 9372 #define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */ 9373 #define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRK BKIN input polarity */ 9374 #define TIM1_AF1_BKCMP1P_Pos (10U) 9375 #define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos) /*!< 0x00000400 */ 9376 #define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */ 9377 #define TIM1_AF1_BKCMP2P_Pos (11U) 9378 #define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos) /*!< 0x00000800 */ 9379 #define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */ 9380 #define TIM1_AF1_ETRSEL_Pos (14U) 9381 #define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos) /*!< 0x0003C000 */ 9382 #define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */ 9383 #define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00004000 */ 9384 #define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */ 9385 #define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00010000 */ 9386 #define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */ 9387 9388 /******************* Bit definition for TIM2_AF1 register *******************/ 9389 #define TIM2_AF1_ETRSEL_Pos (14U) 9390 #define TIM2_AF1_ETRSEL_Msk (0xFUL << TIM2_AF1_ETRSEL_Pos) /*!< 0x0003C000 */ 9391 #define TIM2_AF1_ETRSEL (0x00003C000) /*!< External trigger source selection */ 9392 #define TIM2_AF1_ETRSEL_0 (0x000004000) /*!< Bit_0 */ 9393 #define TIM2_AF1_ETRSEL_1 (0x000008000) /*!< Bit_1 */ 9394 #define TIM2_AF1_ETRSEL_2 (0x000010000) /*!< Bit_2 */ 9395 #define TIM2_AF1_ETRSEL_3 (0x000020000) /*!< Bit_3 */ 9396 9397 /******************* Bit definition for TIM16_AF1 register *******************/ 9398 #define TIM16_AF1_BKINE_Pos (0U) 9399 #define TIM16_AF1_BKINE_Msk (0x1UL << TIM16_AF1_BKINE_Pos) /*!< 0x00000001 */ 9400 #define TIM16_AF1_BKINE TIM16_AF1_BKINE_Msk /*!<BRK BKIN input enable */ 9401 #define TIM16_AF1_BKCMP1E_Pos (1U) 9402 #define TIM16_AF1_BKCMP1E_Msk (0x1UL << TIM16_AF1_BKCMP1E_Pos) /*!< 0x00000002 */ 9403 #define TIM16_AF1_BKCMP1E TIM16_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */ 9404 #define TIM16_AF1_BKCMP2E_Pos (2U) 9405 #define TIM16_AF1_BKCMP2E_Msk (0x1UL << TIM16_AF1_BKCMP2E_Pos) /*!< 0x00000004 */ 9406 #define TIM16_AF1_BKCMP2E TIM16_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */ 9407 #define TIM16_AF1_BKINP_Pos (9U) 9408 #define TIM16_AF1_BKINP_Msk (0x1UL << TIM16_AF1_BKINP_Pos) /*!< 0x00000200 */ 9409 #define TIM16_AF1_BKINP TIM16_AF1_BKINP_Msk /*!<BRK BKIN2 input polarity */ 9410 #define TIM16_AF1_BKCMP1P_Pos (10U) 9411 #define TIM16_AF1_BKCMP1P_Msk (0x1UL << TIM16_AF1_BKCMP1P_Pos) /*!< 0x00000400 */ 9412 #define TIM16_AF1_BKCMP1P TIM16_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */ 9413 #define TIM16_AF1_BKCMP2P_Pos (11U) 9414 #define TIM16_AF1_BKCMP2P_Msk (0x1UL << TIM16_AF1_BKCMP2P_Pos) /*!< 0x00000800 */ 9415 #define TIM16_AF1_BKCMP2P TIM16_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */ 9416 9417 /******************* Bit definition for TIM17_AF1 register *******************/ 9418 #define TIM17_AF1_BKINE_Pos (0U) 9419 #define TIM17_AF1_BKINE_Msk (0x1UL << TIM17_AF1_BKINE_Pos) /*!< 0x00000001 */ 9420 #define TIM17_AF1_BKINE TIM17_AF1_BKINE_Msk /*!<BRK BKIN input enable */ 9421 #define TIM17_AF1_BKCMP1E_Pos (1U) 9422 #define TIM17_AF1_BKCMP1E_Msk (0x1UL << TIM17_AF1_BKCMP1E_Pos) /*!< 0x00000002 */ 9423 #define TIM17_AF1_BKCMP1E TIM17_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */ 9424 #define TIM17_AF1_BKCMP2E_Pos (2U) 9425 #define TIM17_AF1_BKCMP2E_Msk (0x1UL << TIM17_AF1_BKCMP2E_Pos) /*!< 0x00000004 */ 9426 #define TIM17_AF1_BKCMP2E TIM17_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */ 9427 #define TIM17_AF1_BKINP_Pos (9U) 9428 #define TIM17_AF1_BKINP_Msk (0x1UL << TIM17_AF1_BKINP_Pos) /*!< 0x00000200 */ 9429 #define TIM17_AF1_BKINP TIM17_AF1_BKINP_Msk /*!<BRK BKIN2 input polarity */ 9430 #define TIM17_AF1_BKCMP1P_Pos (10U) 9431 #define TIM17_AF1_BKCMP1P_Msk (0x1UL << TIM17_AF1_BKCMP1P_Pos) /*!< 0x00000400 */ 9432 #define TIM17_AF1_BKCMP1P TIM17_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */ 9433 #define TIM17_AF1_BKCMP2P_Pos (11U) 9434 #define TIM17_AF1_BKCMP2P_Msk (0x1UL << TIM17_AF1_BKCMP2P_Pos) /*!< 0x00000800 */ 9435 #define TIM17_AF1_BKCMP2P TIM17_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */ 9436 9437 /******************* Bit definition for TIM1_AF2 register *******************/ 9438 #define TIM1_AF2_BK2INE_Pos (0U) 9439 #define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */ 9440 #define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BRK2 BKIN2 input enable */ 9441 #define TIM1_AF2_BK2CMP1E_Pos (1U) 9442 #define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */ 9443 #define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */ 9444 #define TIM1_AF2_BK2CMP2E_Pos (2U) 9445 #define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */ 9446 #define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */ 9447 #define TIM1_AF2_BK2INP_Pos (9U) 9448 #define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */ 9449 #define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */ 9450 #define TIM1_AF2_BK2CMP1P_Pos (10U) 9451 #define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */ 9452 #define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */ 9453 #define TIM1_AF2_BK2CMP2P_Pos (11U) 9454 #define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */ 9455 #define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */ 9456 9457 9458 /** @addtogroup Exported_macros 9459 * @{ 9460 */ 9461 9462 9463 /******************************* ADC Instances ********************************/ 9464 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC) 9465 9466 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC_COMMON) 9467 9468 /******************************* AES Instances ********************************/ 9469 #define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES) 9470 9471 /******************************** COMP Instances ******************************/ 9472 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \ 9473 ((INSTANCE) == COMP2)) 9474 9475 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON) 9476 9477 /******************************* CRC Instances ********************************/ 9478 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) 9479 9480 /******************************* DAC Instances ********************************/ 9481 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC) 9482 9483 /******************************** DMA Instances *******************************/ 9484 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ 9485 ((INSTANCE) == DMA1_Channel2) || \ 9486 ((INSTANCE) == DMA1_Channel3) || \ 9487 ((INSTANCE) == DMA1_Channel4) || \ 9488 ((INSTANCE) == DMA1_Channel5) || \ 9489 ((INSTANCE) == DMA1_Channel6) || \ 9490 ((INSTANCE) == DMA1_Channel7) || \ 9491 ((INSTANCE) == DMA2_Channel1) || \ 9492 ((INSTANCE) == DMA2_Channel2) || \ 9493 ((INSTANCE) == DMA2_Channel3) || \ 9494 ((INSTANCE) == DMA2_Channel4) || \ 9495 ((INSTANCE) == DMA2_Channel5) || \ 9496 ((INSTANCE) == DMA2_Channel6) || \ 9497 ((INSTANCE) == DMA2_Channel7)) 9498 9499 /******************************* GPIO Instances *******************************/ 9500 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 9501 ((INSTANCE) == GPIOB) || \ 9502 ((INSTANCE) == GPIOC) || \ 9503 ((INSTANCE) == GPIOH)) 9504 9505 /******************************* GPIO AF Instances ****************************/ 9506 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) 9507 9508 /**************************** GPIO Lock Instances *****************************/ 9509 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) 9510 9511 /******************************** I2C Instances *******************************/ 9512 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ 9513 ((INSTANCE) == I2C2) || \ 9514 ((INSTANCE) == I2C3)) 9515 9516 /****************** I2C Instances : wakeup capability from stop modes *********/ 9517 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) 9518 9519 /******************************* SMBUS Instances ******************************/ 9520 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) 9521 9522 /******************************** I2S Instances *******************************/ 9523 #define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI2) 9524 9525 /******************************** HSEM Instances *******************************/ 9526 #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) 9527 9528 #define HSEM_CPU1_COREID (0x00000004U) /* Semaphore Core ID */ 9529 #define HSEM_CPU2_COREID (0x00000008U) /* Semaphore Core ID */ 9530 9531 #define HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ 9532 #define HSEM_SEMID_MAX (15U) /* HSEM ID Max */ 9533 9534 #define HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ 9535 #define HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ 9536 9537 #define HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ 9538 #define HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ 9539 9540 /******************************** PKA Instances *******************************/ 9541 #define IS_PKA_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PKA) 9542 9543 /******************************* RNG Instances ********************************/ 9544 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) 9545 9546 /****************************** RTC Instances *********************************/ 9547 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) 9548 9549 /****************************** RTC Instances *********************************/ 9550 #define IS_TAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TAMP) 9551 9552 /******************************** SPI Instances *******************************/ 9553 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ 9554 ((INSTANCE) == SPI2) || \ 9555 ((INSTANCE) == SUBGHZSPI)) 9556 9557 /******************************** SUBGHZSPI Instances *************************/ 9558 #define IS_SUBGHZ_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SUBGHZSPI) 9559 #define IS_SUBGHZ_MODULATION_SUPPORTED(COMMAND,PACKET_TYPE) (1U == 1U) 9560 9561 /****************************** IWDG Instances ********************************/ 9562 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) 9563 9564 /****************************** WWDG Instances ********************************/ 9565 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) 9566 9567 /****************** LPTIM Instances : All supported instances *****************/ 9568 #define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \ 9569 ((INSTANCE) == LPTIM2) || \ 9570 ((INSTANCE) == LPTIM3)) 9571 9572 /****************** LPTIM Instances : Encoder mode ****************************/ 9573 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1) 9574 9575 /****************** TIM Instances : All supported instances *******************/ 9576 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 9577 ((INSTANCE) == TIM2) || \ 9578 ((INSTANCE) == TIM16) || \ 9579 ((INSTANCE) == TIM17)) 9580 9581 /****************** TIM Instances : supporting 32 bits counter ****************/ 9582 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2) 9583 9584 /****************** TIM Instances : supporting the break function *************/ 9585 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 9586 ((INSTANCE) == TIM16) || \ 9587 ((INSTANCE) == TIM17)) 9588 9589 /************** TIM Instances : supporting Break source selection *************/ 9590 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 9591 ((INSTANCE) == TIM16) || \ 9592 ((INSTANCE) == TIM17)) 9593 9594 /****************** TIM Instances : supporting 2 break inputs *****************/ 9595 #define IS_TIM_BKIN2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) 9596 9597 /************* TIM Instances : at least 1 capture/compare channel *************/ 9598 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 9599 ((INSTANCE) == TIM2) || \ 9600 ((INSTANCE) == TIM16) || \ 9601 ((INSTANCE) == TIM17)) 9602 9603 /************ TIM Instances : at least 2 capture/compare channels *************/ 9604 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 9605 ((INSTANCE) == TIM2)) 9606 9607 /************ TIM Instances : at least 3 capture/compare channels *************/ 9608 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 9609 ((INSTANCE) == TIM2)) 9610 9611 /************ TIM Instances : at least 4 capture/compare channels *************/ 9612 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 9613 ((INSTANCE) == TIM2)) 9614 9615 /****************** TIM Instances : at least 5 capture/compare channels *******/ 9616 #define IS_TIM_CC5_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) 9617 9618 /****************** TIM Instances : at least 6 capture/compare channels *******/ 9619 #define IS_TIM_CC6_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) 9620 9621 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ 9622 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 9623 ((INSTANCE) == TIM2) || \ 9624 ((INSTANCE) == TIM16) || \ 9625 ((INSTANCE) == TIM17)) 9626 9627 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ 9628 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 9629 ((INSTANCE) == TIM2) || \ 9630 ((INSTANCE) == TIM16) || \ 9631 ((INSTANCE) == TIM17)) 9632 9633 /******************** TIM Instances : DMA burst feature ***********************/ 9634 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 9635 ((INSTANCE) == TIM2) || \ 9636 ((INSTANCE) == TIM16) || \ 9637 ((INSTANCE) == TIM17)) 9638 9639 /******************* TIM Instances : Timer input selection ********************/ 9640 #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 9641 ((INSTANCE) == TIM2) || \ 9642 ((INSTANCE) == TIM16) || \ 9643 ((INSTANCE) == TIM17)) 9644 9645 /******************* TIM Instances : output(s) available **********************/ 9646 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ 9647 ((((INSTANCE) == TIM1) && \ 9648 (((CHANNEL) == TIM_CHANNEL_1) || \ 9649 ((CHANNEL) == TIM_CHANNEL_2) || \ 9650 ((CHANNEL) == TIM_CHANNEL_3) || \ 9651 ((CHANNEL) == TIM_CHANNEL_4) || \ 9652 ((CHANNEL) == TIM_CHANNEL_5) || \ 9653 ((CHANNEL) == TIM_CHANNEL_6))) \ 9654 || \ 9655 (((INSTANCE) == TIM2) && \ 9656 (((CHANNEL) == TIM_CHANNEL_1) || \ 9657 ((CHANNEL) == TIM_CHANNEL_2) || \ 9658 ((CHANNEL) == TIM_CHANNEL_3) || \ 9659 ((CHANNEL) == TIM_CHANNEL_4))) \ 9660 || \ 9661 (((INSTANCE) == TIM16) && \ 9662 (((CHANNEL) == TIM_CHANNEL_1))) \ 9663 || \ 9664 (((INSTANCE) == TIM17) && \ 9665 (((CHANNEL) == TIM_CHANNEL_1)))) 9666 9667 /****************** TIM Instances : supporting complementary output(s) ********/ 9668 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ 9669 ((((INSTANCE) == TIM1) && \ 9670 (((CHANNEL) == TIM_CHANNEL_1) || \ 9671 ((CHANNEL) == TIM_CHANNEL_2) || \ 9672 ((CHANNEL) == TIM_CHANNEL_3))) \ 9673 || \ 9674 (((INSTANCE) == TIM17) && \ 9675 ((CHANNEL) == TIM_CHANNEL_1)) \ 9676 || \ 9677 (((INSTANCE) == TIM16) && \ 9678 ((CHANNEL) == TIM_CHANNEL_1))) 9679 9680 9681 /****************** TIM Instances : supporting clock division *****************/ 9682 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 9683 ((INSTANCE) == TIM2) || \ 9684 ((INSTANCE) == TIM16) || \ 9685 ((INSTANCE) == TIM17)) 9686 9687 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ 9688 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 9689 ((INSTANCE) == TIM2)) 9690 9691 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ 9692 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 9693 ((INSTANCE) == TIM2)) 9694 9695 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ 9696 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 9697 ((INSTANCE) == TIM2)) 9698 9699 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ 9700 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 9701 ((INSTANCE) == TIM2)) 9702 9703 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/ 9704 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) 9705 9706 /****************** TIM Instances : supporting commutation event generation ***/ 9707 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 9708 ((INSTANCE) == TIM16) || \ 9709 ((INSTANCE) == TIM17)) 9710 9711 /****************** TIM Instances : supporting counting mode selection ********/ 9712 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 9713 ((INSTANCE) == TIM2)) 9714 9715 /****************** TIM Instances : supporting encoder interface **************/ 9716 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 9717 ((INSTANCE) == TIM2)) 9718 9719 /****************** TIM Instances : supporting Hall sensor interface **********/ 9720 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) 9721 9722 /**************** TIM Instances : external trigger input available ************/ 9723 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 9724 ((INSTANCE) == TIM2)) 9725 9726 /************* TIM Instances : supporting ETR source selection ***************/ 9727 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 9728 ((INSTANCE) == TIM2)) 9729 9730 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ 9731 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 9732 ((INSTANCE) == TIM2)) 9733 9734 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ 9735 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 9736 ((INSTANCE) == TIM2)) 9737 9738 /****************** TIM Instances : supporting OCxREF clear *******************/ 9739 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 9740 ((INSTANCE) == TIM2)) 9741 9742 /****************** TIM Instances : remapping capability **********************/ 9743 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 9744 ((INSTANCE) == TIM2) || \ 9745 ((INSTANCE) == TIM16) || \ 9746 ((INSTANCE) == TIM17)) 9747 9748 /****************** TIM Instances : supporting repetition counter *************/ 9749 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 9750 ((INSTANCE) == TIM16) || \ 9751 ((INSTANCE) == TIM17)) 9752 9753 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ 9754 #define IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) 9755 9756 /******************* TIM Instances : Timer input XOR function *****************/ 9757 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 9758 ((INSTANCE) == TIM2)) 9759 9760 /************ TIM Instances : Advanced timers ********************************/ 9761 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)) 9762 9763 /******************** UART Instances : Asynchronous mode **********************/ 9764 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9765 ((INSTANCE) == USART2)) 9766 9767 9768 /******************** USART Instances : Synchronous mode **********************/ 9769 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9770 ((INSTANCE) == USART2)) 9771 9772 /****************** UART Instances : Hardware Flow control ********************/ 9773 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9774 ((INSTANCE) == USART2) || \ 9775 ((INSTANCE) == LPUART1)) 9776 9777 /********************* USART Instances : Smard card mode ***********************/ 9778 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9779 ((INSTANCE) == USART2)) 9780 9781 /****************** UART Instances : Auto Baud Rate detection ****************/ 9782 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9783 ((INSTANCE) == USART2)) 9784 9785 /******************** UART Instances : Half-Duplex mode **********************/ 9786 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9787 ((INSTANCE) == USART2) || \ 9788 ((INSTANCE) == LPUART1)) 9789 9790 /******************** UART Instances : LIN mode **********************/ 9791 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9792 ((INSTANCE) == USART2)) 9793 9794 /******************** UART Instances : Wake-up from Stop mode **********************/ 9795 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9796 ((INSTANCE) == USART2) || \ 9797 ((INSTANCE) == LPUART1)) 9798 9799 /****************** UART Instances : Driver Enable *****************/ 9800 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9801 ((INSTANCE) == USART2) || \ 9802 ((INSTANCE) == LPUART1)) 9803 9804 /****************** UART Instances : SPI Slave selection mode ***************/ 9805 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9806 ((INSTANCE) == USART2)) 9807 9808 /****************** UART Instances : Driver Enable *****************/ 9809 #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9810 ((INSTANCE) == USART2) || \ 9811 ((INSTANCE) == LPUART1)) 9812 9813 /*********************** UART Instances : IRDA mode ***************************/ 9814 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9815 ((INSTANCE) == USART2)) 9816 9817 /******************** LPUART Instance *****************************************/ 9818 #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) 9819 9820 /******************************************************************************/ 9821 /* For a painless codes migration between the STM32WLxx device product */ 9822 /* lines, the aliases defined below are put in place to overcome the */ 9823 /* differences in the interrupt handlers and IRQn definitions. */ 9824 /* No need to update developed interrupt code when moving across */ 9825 /* product lines within the same STM32WL Family */ 9826 /******************************************************************************/ 9827 /** 9828 * @} 9829 */ 9830 9831 /** 9832 * @} 9833 */ 9834 9835 /** 9836 * @} 9837 */ 9838 9839 #ifdef __cplusplus 9840 } 9841 #endif /* __cplusplus */ 9842 9843 #endif /* __STM32WLE5xx_H */ 9844 9845 /** 9846 * @} 9847 */ 9848 9849 /** 9850 * @} 9851 */ 9852
