1 /** 2 ****************************************************************************** 3 * @file stm32wlxx_hal_cortex.h 4 * @author MCD Application Team 5 * @brief Header file of CORTEX HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2020 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32WLxx_HAL_CORTEX_H 21 #define __STM32WLxx_HAL_CORTEX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32wlxx_hal_def.h" 29 30 /** @addtogroup STM32WLxx_HAL_Driver 31 * @{ 32 */ 33 34 /** @defgroup CORTEX CORTEX 35 * @brief CORTEX HAL module driver 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types 41 * @{ 42 */ 43 44 #if (__MPU_PRESENT == 1) 45 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition 46 * @brief MPU Region initialization structure 47 * @{ 48 */ 49 typedef struct 50 { 51 uint8_t Enable; /*!< Specifies the status of the region. 52 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ 53 uint8_t Number; /*!< Specifies the number of the region to protect. 54 This parameter can be a value of @ref CORTEX_MPU_Region_Number */ 55 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. 56 */ 57 uint8_t Size; /*!< Specifies the size of the region to protect. 58 This parameter can be a value of @ref CORTEX_MPU_Region_Size */ 59 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. 60 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 61 uint8_t TypeExtField; /*!< Specifies the TEX field level. 62 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ 63 uint8_t AccessPermission; /*!< Specifies the region access permission type. 64 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ 65 uint8_t DisableExec; /*!< Specifies the instruction access status. 66 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ 67 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. 68 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ 69 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. 70 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ 71 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. 72 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ 73 } MPU_Region_InitTypeDef; 74 /** 75 * @} 76 */ 77 #endif /* __MPU_PRESENT */ 78 79 /** 80 * @} 81 */ 82 83 /* Exported constants --------------------------------------------------------*/ 84 85 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants 86 * @{ 87 */ 88 #ifdef CORE_CM0PLUS 89 #else 90 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group 91 * @{ 92 */ 93 #define NVIC_PRIORITYGROUP_0 (0x00000007U) /*!< 0 bit for pre-emption priority, 94 4 bits for subpriority */ 95 #define NVIC_PRIORITYGROUP_1 (0x00000006U) /*!< 1 bit for pre-emption priority, 96 3 bits for subpriority */ 97 #define NVIC_PRIORITYGROUP_2 (0x00000005U) /*!< 2 bits for pre-emption priority, 98 2 bits for subpriority */ 99 #define NVIC_PRIORITYGROUP_3 (0x00000004U) /*!< 3 bits for pre-emption priority, 100 1 bit for subpriority */ 101 #define NVIC_PRIORITYGROUP_4 (0x00000003U) /*!< 4 bits for pre-emption priority, 102 0 bit for subpriority */ 103 /** 104 * @} 105 */ 106 #endif /* CORE_CM0PLUS */ 107 108 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source 109 * @{ 110 */ 111 #define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U 112 #define SYSTICK_CLKSOURCE_HCLK 0x00000004U 113 114 /** 115 * @} 116 */ 117 118 #if (__MPU_PRESENT == 1) 119 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control 120 * @{ 121 */ 122 #define MPU_HFNMI_PRIVDEF_NONE 0x00000000U 123 #define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk) 124 #define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk) 125 #define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) 126 /** 127 * @} 128 */ 129 130 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable 131 * @{ 132 */ 133 #define MPU_REGION_ENABLE ((uint8_t)0x01) 134 #define MPU_REGION_DISABLE ((uint8_t)0x00) 135 /** 136 * @} 137 */ 138 139 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access 140 * @{ 141 */ 142 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) 143 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) 144 /** 145 * @} 146 */ 147 148 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable 149 * @{ 150 */ 151 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) 152 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) 153 /** 154 * @} 155 */ 156 157 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable 158 * @{ 159 */ 160 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) 161 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) 162 /** 163 * @} 164 */ 165 166 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable 167 * @{ 168 */ 169 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) 170 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) 171 /** 172 * @} 173 */ 174 175 /** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels 176 * @{ 177 */ 178 #define MPU_TEX_LEVEL0 ((uint8_t)0x00) 179 #define MPU_TEX_LEVEL1 ((uint8_t)0x01) 180 #define MPU_TEX_LEVEL2 ((uint8_t)0x02) 181 182 /** 183 * @} 184 */ 185 186 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size 187 * @{ 188 */ 189 #if defined(CORE_CM0PLUS) 190 #else 191 #define MPU_REGION_SIZE_32B ((uint8_t)0x04) 192 #define MPU_REGION_SIZE_64B ((uint8_t)0x05) 193 #define MPU_REGION_SIZE_128B ((uint8_t)0x06) 194 #endif 195 #define MPU_REGION_SIZE_256B ((uint8_t)0x07) 196 #define MPU_REGION_SIZE_512B ((uint8_t)0x08) 197 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09) 198 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) 199 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) 200 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) 201 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) 202 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) 203 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) 204 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) 205 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) 206 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) 207 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13) 208 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14) 209 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15) 210 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16) 211 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) 212 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) 213 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) 214 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) 215 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) 216 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) 217 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) 218 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) 219 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) 220 /** 221 * @} 222 */ 223 224 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 225 * @{ 226 */ 227 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) 228 #define MPU_REGION_PRIV_RW ((uint8_t)0x01) 229 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) 230 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) 231 #define MPU_REGION_PRIV_RO ((uint8_t)0x05) 232 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) 233 /** 234 * @} 235 */ 236 237 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number 238 * @{ 239 */ 240 #define MPU_REGION_NUMBER0 ((uint8_t)0x00) 241 #define MPU_REGION_NUMBER1 ((uint8_t)0x01) 242 #define MPU_REGION_NUMBER2 ((uint8_t)0x02) 243 #define MPU_REGION_NUMBER3 ((uint8_t)0x03) 244 #define MPU_REGION_NUMBER4 ((uint8_t)0x04) 245 #define MPU_REGION_NUMBER5 ((uint8_t)0x05) 246 #define MPU_REGION_NUMBER6 ((uint8_t)0x06) 247 #define MPU_REGION_NUMBER7 ((uint8_t)0x07) 248 /** 249 * @} 250 */ 251 #endif /* __MPU_PRESENT */ 252 253 /** 254 * @} 255 */ 256 257 /* Exported macros -----------------------------------------------------------*/ 258 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros 259 * @{ 260 */ 261 262 /** 263 * @} 264 */ 265 266 /* Exported functions --------------------------------------------------------*/ 267 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions 268 * @{ 269 */ 270 271 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions 272 * @brief Initialization and Configuration functions 273 * @{ 274 */ 275 /* Initialization and Configuration functions *****************************/ 276 #ifdef CORE_CM0PLUS 277 #else 278 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); 279 #endif /* CORE_CM0PLUS */ 280 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); 281 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); 282 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); 283 void HAL_NVIC_SystemReset(void); 284 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); 285 /** 286 * @} 287 */ 288 289 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions 290 * @brief Cortex control functions 291 * @{ 292 */ 293 /* Peripheral Control functions *************************************************/ 294 #ifdef CORE_CM0PLUS 295 uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn); 296 #else 297 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority); 298 uint32_t HAL_NVIC_GetPriorityGrouping(void); 299 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); 300 #endif /* CORE_CM0PLUS */ 301 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); 302 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); 303 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); 304 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); 305 void HAL_SYSTICK_IRQHandler(void); 306 void HAL_SYSTICK_Callback(void); 307 308 #if (__MPU_PRESENT == 1U) 309 void HAL_MPU_Enable(uint32_t MPU_Control); 310 void HAL_MPU_Disable(void); 311 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); 312 #endif /* __MPU_PRESENT */ 313 /** 314 * @} 315 */ 316 317 /** 318 * @} 319 */ 320 321 /* Private types -------------------------------------------------------------*/ 322 /* Private variables ---------------------------------------------------------*/ 323 /* Private constants ---------------------------------------------------------*/ 324 /* Private macros ------------------------------------------------------------*/ 325 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros 326 * @{ 327 */ 328 #ifdef CORE_CM0PLUS 329 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4U) 330 #else 331 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ 332 ((GROUP) == NVIC_PRIORITYGROUP_1) || \ 333 ((GROUP) == NVIC_PRIORITYGROUP_2) || \ 334 ((GROUP) == NVIC_PRIORITYGROUP_3) || \ 335 ((GROUP) == NVIC_PRIORITYGROUP_4)) 336 337 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) 338 339 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) 340 #endif /* CORE_CM0PLUS */ 341 342 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn) 343 344 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ 345 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) 346 347 #if (__MPU_PRESENT == 1) 348 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ 349 ((STATE) == MPU_REGION_DISABLE)) 350 351 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ 352 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) 353 354 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ 355 ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) 356 357 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ 358 ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) 359 360 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ 361 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) 362 363 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ 364 ((TYPE) == MPU_TEX_LEVEL1) || \ 365 ((TYPE) == MPU_TEX_LEVEL2)) 366 367 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ 368 ((TYPE) == MPU_REGION_PRIV_RW) || \ 369 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ 370 ((TYPE) == MPU_REGION_FULL_ACCESS) || \ 371 ((TYPE) == MPU_REGION_PRIV_RO) || \ 372 ((TYPE) == MPU_REGION_PRIV_RO_URO)) 373 374 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ 375 ((NUMBER) == MPU_REGION_NUMBER1) || \ 376 ((NUMBER) == MPU_REGION_NUMBER2) || \ 377 ((NUMBER) == MPU_REGION_NUMBER3) || \ 378 ((NUMBER) == MPU_REGION_NUMBER4) || \ 379 ((NUMBER) == MPU_REGION_NUMBER5) || \ 380 ((NUMBER) == MPU_REGION_NUMBER6) || \ 381 ((NUMBER) == MPU_REGION_NUMBER7)) 382 383 #if defined(CORE_CM0PLUS) 384 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_256B) || \ 385 ((SIZE) == MPU_REGION_SIZE_512B) || \ 386 ((SIZE) == MPU_REGION_SIZE_1KB) || \ 387 ((SIZE) == MPU_REGION_SIZE_2KB) || \ 388 ((SIZE) == MPU_REGION_SIZE_4KB) || \ 389 ((SIZE) == MPU_REGION_SIZE_8KB) || \ 390 ((SIZE) == MPU_REGION_SIZE_16KB) || \ 391 ((SIZE) == MPU_REGION_SIZE_32KB) || \ 392 ((SIZE) == MPU_REGION_SIZE_64KB) || \ 393 ((SIZE) == MPU_REGION_SIZE_128KB) || \ 394 ((SIZE) == MPU_REGION_SIZE_256KB) || \ 395 ((SIZE) == MPU_REGION_SIZE_512KB) || \ 396 ((SIZE) == MPU_REGION_SIZE_1MB) || \ 397 ((SIZE) == MPU_REGION_SIZE_2MB) || \ 398 ((SIZE) == MPU_REGION_SIZE_4MB) || \ 399 ((SIZE) == MPU_REGION_SIZE_8MB) || \ 400 ((SIZE) == MPU_REGION_SIZE_16MB) || \ 401 ((SIZE) == MPU_REGION_SIZE_32MB) || \ 402 ((SIZE) == MPU_REGION_SIZE_64MB) || \ 403 ((SIZE) == MPU_REGION_SIZE_128MB) || \ 404 ((SIZE) == MPU_REGION_SIZE_256MB) || \ 405 ((SIZE) == MPU_REGION_SIZE_512MB) || \ 406 ((SIZE) == MPU_REGION_SIZE_1GB) || \ 407 ((SIZE) == MPU_REGION_SIZE_2GB) || \ 408 ((SIZE) == MPU_REGION_SIZE_4GB)) 409 #else 410 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ 411 ((SIZE) == MPU_REGION_SIZE_64B) || \ 412 ((SIZE) == MPU_REGION_SIZE_128B) || \ 413 ((SIZE) == MPU_REGION_SIZE_256B) || \ 414 ((SIZE) == MPU_REGION_SIZE_512B) || \ 415 ((SIZE) == MPU_REGION_SIZE_1KB) || \ 416 ((SIZE) == MPU_REGION_SIZE_2KB) || \ 417 ((SIZE) == MPU_REGION_SIZE_4KB) || \ 418 ((SIZE) == MPU_REGION_SIZE_8KB) || \ 419 ((SIZE) == MPU_REGION_SIZE_16KB) || \ 420 ((SIZE) == MPU_REGION_SIZE_32KB) || \ 421 ((SIZE) == MPU_REGION_SIZE_64KB) || \ 422 ((SIZE) == MPU_REGION_SIZE_128KB) || \ 423 ((SIZE) == MPU_REGION_SIZE_256KB) || \ 424 ((SIZE) == MPU_REGION_SIZE_512KB) || \ 425 ((SIZE) == MPU_REGION_SIZE_1MB) || \ 426 ((SIZE) == MPU_REGION_SIZE_2MB) || \ 427 ((SIZE) == MPU_REGION_SIZE_4MB) || \ 428 ((SIZE) == MPU_REGION_SIZE_8MB) || \ 429 ((SIZE) == MPU_REGION_SIZE_16MB) || \ 430 ((SIZE) == MPU_REGION_SIZE_32MB) || \ 431 ((SIZE) == MPU_REGION_SIZE_64MB) || \ 432 ((SIZE) == MPU_REGION_SIZE_128MB) || \ 433 ((SIZE) == MPU_REGION_SIZE_256MB) || \ 434 ((SIZE) == MPU_REGION_SIZE_512MB) || \ 435 ((SIZE) == MPU_REGION_SIZE_1GB) || \ 436 ((SIZE) == MPU_REGION_SIZE_2GB) || \ 437 ((SIZE) == MPU_REGION_SIZE_4GB)) 438 #endif 439 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU) 440 #endif /* __MPU_PRESENT */ 441 442 /** 443 * @} 444 */ 445 446 /* Private functions ---------------------------------------------------------*/ 447 448 /** 449 * @} 450 */ 451 452 /** 453 * @} 454 */ 455 456 #ifdef __cplusplus 457 } 458 #endif 459 460 #endif /* __STM32WLxx_HAL_CORTEX_H */ 461
