1 /**
2 ******************************************************************************
3 * @file stm32wbxx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WBxx_LL_ADC_H
21 #define STM32WBxx_LL_ADC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wbxx.h"
29
30 /** @addtogroup STM32WBxx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1)
35
36 /** @defgroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
45 * @{
46 */
47
48 /* Internal mask for ADC group regular sequencer: */
49 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
50 /* - sequencer register offset */
51 /* - sequencer rank bits position into the selected register */
52
53 /* Internal register offset for ADC group regular sequencer configuration */
54 /* (offset placed into a spare area of literal definition) */
55 #if defined(ADC_SUPPORT_2_5_MSPS)
56 /* No register ADC_SQRx on this ADC peripheral version */
57 #else
58 #define ADC_SQR1_REGOFFSET (0x00000000UL)
59 #define ADC_SQR2_REGOFFSET (0x00000100UL)
60 #define ADC_SQR3_REGOFFSET (0x00000200UL)
61 #define ADC_SQR4_REGOFFSET (0x00000300UL)
62
63 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
64 #define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */
65 #endif /* ADC_SUPPORT_2_5_MSPS */
66 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
67
68 /* Definition of ADC group regular sequencer bits information to be inserted */
69 /* into ADC group regular sequencer ranks literals definition. */
70 #if defined(ADC_SUPPORT_2_5_MSPS)
71 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ1" position in register */
72 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 4UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ2" position in register */
73 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ( 8UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ3" position in register */
74 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ4" position in register */
75 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ5" position in register */
76 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ6" position in register */
77 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ7" position in register */
78 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (28UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ8" position in register */
79 #else
80 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR1_SQ1" position in register */
81 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR1_SQ2" position in register */
82 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR1_SQ3" position in register */
83 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR1_SQ4" position in register */
84 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR2_SQ5" position in register */
85 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR2_SQ6" position in register */
86 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR2_SQ7" position in register */
87 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR2_SQ8" position in register */
88 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR2_SQ9" position in register */
89 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR3_SQ10" position in register */
90 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR3_SQ11" position in register */
91 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR3_SQ12" position in register */
92 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR3_SQ13" position in register */
93 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR3_SQ14" position in register */
94 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR4_SQ15" position in register */
95 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR4_SQ16" position in register */
96 #endif /* ADC_SUPPORT_2_5_MSPS */
97
98
99
100 /* Internal mask for ADC group injected sequencer: */
101 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
102 /* - data register offset */
103 /* - sequencer rank bits position into the selected register */
104
105 /* Internal register offset for ADC group injected data register */
106 /* (offset placed into a spare area of literal definition) */
107 #define ADC_JDR1_REGOFFSET (0x00000000UL)
108 #define ADC_JDR2_REGOFFSET (0x00000100UL)
109 #define ADC_JDR3_REGOFFSET (0x00000200UL)
110 #define ADC_JDR4_REGOFFSET (0x00000300UL)
111
112 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
113 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
114 #define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */
115
116 /* Definition of ADC group injected sequencer bits information to be inserted */
117 /* into ADC group injected sequencer ranks literals definition. */
118 #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ( 8UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ1" position in register */
119 #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (14UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ2" position in register */
120 #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ3" position in register */
121 #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (26UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ4" position in register */
122
123
124
125 /* Internal mask for ADC group regular trigger: */
126 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
127 /* - regular trigger source */
128 /* - regular trigger edge */
129 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
130
131 /* Mask containing trigger source masks for each of possible */
132 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
133 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
134 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \
135 ((ADC_CFGR_EXTSEL) << (4U * 1UL)) | \
136 ((ADC_CFGR_EXTSEL) << (4U * 2UL)) | \
137 ((ADC_CFGR_EXTSEL) << (4U * 3UL)) )
138
139 /* Mask containing trigger edge masks for each of possible */
140 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
141 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
142 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \
143 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
144 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
145 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
146
147 /* Definition of ADC group regular trigger bits information. */
148 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CFGR_EXTSEL" position in register */
149 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CFGR_EXTEN" position in register */
150
151
152
153 /* Internal mask for ADC group injected trigger: */
154 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
155 /* - injected trigger source */
156 /* - injected trigger edge */
157 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
158
159 /* Mask containing trigger source masks for each of possible */
160 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
161 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
162 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \
163 ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \
164 ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \
165 ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) )
166
167 /* Mask containing trigger edge masks for each of possible */
168 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
169 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
170 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
171 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
172 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
173 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
174
175 /* Definition of ADC group injected trigger bits information. */
176 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTSEL" position in register */
177 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTEN" position in register */
178
179
180
181
182
183
184 /* Internal mask for ADC channel: */
185 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
186 /* - channel identifier defined by number */
187 /* - channel identifier defined by bitfield */
188 /* - channel differentiation between external channels (connected to */
189 /* GPIO pins) and internal channels (connected to internal paths) */
190 /* - channel sampling time defined by SMPRx register offset */
191 /* and SMPx bits positions into SMPRx register */
192 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
193 #if defined(ADC_SUPPORT_2_5_MSPS)
194 #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL)
195 #else
196 #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
197 #endif
198 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */
199 #if defined(ADC_SUPPORT_2_5_MSPS)
200 #define ADC_CHANNEL_ID_NUMBER_MASK_SEQ (ADC_CHSELR_SQ1 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Value equivalent to ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer, if set to mode "fully configurable", can contain channels with a restricted channel number. Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */
201 #endif
202 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
203 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
204 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FUL) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
205
206 /* Channel differentiation between external and internal channels */
207 #define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
208 #define ADC_CHANNEL_ID_INTERNAL_CH_2 (0x00080000UL) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
209 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
210
211 /* Internal register offset for ADC channel sampling time configuration */
212 /* (offset placed into a spare area of literal definition) */
213 #define ADC_SMPR1_REGOFFSET (0x00000000UL)
214 #define ADC_SMPR2_REGOFFSET (0x02000000UL)
215 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
216 #define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
217
218 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)
219 #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */
220
221 /* Definition of channels ID number information to be inserted into */
222 /* channels literals definition. */
223 #define ADC_CHANNEL_0_NUMBER (0x00000000UL)
224 #define ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)
225 #define ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )
226 #define ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
227 #define ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )
228 #define ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
229 #define ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
230 #define ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
231 #define ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )
232 #define ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
233 #define ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 )
234 #define ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
235 #define ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 )
236 #define ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
237 #define ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
238 #define ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
239 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )
240 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
241 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 )
242
243 /* Definition of channels ID bitfield information to be inserted into */
244 /* channels literals definition. */
245 #if defined(ADC_SUPPORT_2_5_MSPS)
246 #define ADC_CHANNEL_0_BITFIELD (ADC_CHSELR_CHSEL0)
247 #define ADC_CHANNEL_1_BITFIELD (ADC_CHSELR_CHSEL1)
248 #define ADC_CHANNEL_2_BITFIELD (ADC_CHSELR_CHSEL2)
249 #define ADC_CHANNEL_3_BITFIELD (ADC_CHSELR_CHSEL3)
250 #define ADC_CHANNEL_4_BITFIELD (ADC_CHSELR_CHSEL4)
251 #define ADC_CHANNEL_5_BITFIELD (ADC_CHSELR_CHSEL5)
252 #define ADC_CHANNEL_6_BITFIELD (ADC_CHSELR_CHSEL6)
253 #define ADC_CHANNEL_7_BITFIELD (ADC_CHSELR_CHSEL7)
254 #define ADC_CHANNEL_8_BITFIELD (ADC_CHSELR_CHSEL8)
255 #define ADC_CHANNEL_9_BITFIELD (ADC_CHSELR_CHSEL9)
256 #define ADC_CHANNEL_10_BITFIELD (ADC_CHSELR_CHSEL10)
257 #define ADC_CHANNEL_11_BITFIELD (ADC_CHSELR_CHSEL11)
258 #define ADC_CHANNEL_12_BITFIELD (ADC_CHSELR_CHSEL12)
259 #define ADC_CHANNEL_13_BITFIELD (ADC_CHSELR_CHSEL13)
260 #define ADC_CHANNEL_14_BITFIELD (ADC_CHSELR_CHSEL14)
261 #define ADC_CHANNEL_15_BITFIELD (ADC_CHSELR_CHSEL15)
262 #define ADC_CHANNEL_16_BITFIELD (ADC_CHSELR_CHSEL16)
263 #define ADC_CHANNEL_17_BITFIELD (ADC_CHSELR_CHSEL17)
264 #define ADC_CHANNEL_18_BITFIELD (ADC_CHSELR_CHSEL18)
265 #else
266 #define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
267 #define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
268 #define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
269 #define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
270 #define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
271 #define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
272 #define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
273 #define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
274 #define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
275 #define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
276 #define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
277 #define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
278 #define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
279 #define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
280 #define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
281 #define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
282 #define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
283 #define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
284 #define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
285 #endif /* ADC_SUPPORT_2_5_MSPS */
286
287 /* Definition of channels sampling time information to be inserted into */
288 /* channels literals definition. */
289 #define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */
290 #define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */
291 #define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */
292 #define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */
293 #define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */
294 #define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */
295 #define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */
296 #define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */
297 #define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */
298 #define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */
299 #define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */
300 #define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */
301 #define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */
302 #define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */
303 #define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */
304 #define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */
305 #define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */
306 #define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */
307 #define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */
308
309
310 #if defined(ADC_SUPPORT_2_5_MSPS)
311 /* Internal mask for ADC channel sampling time: */
312 /* To select into literals LL_ADC_SAMPLINGTIME_x */
313 /* the relevant bits for: */
314 /* (concatenation of multiple bits used in register SMPR) */
315 /* - ADC channels sampling time: setting channel wise, to map each channel */
316 /* on one of the common sampling time available. */
317 /* - ADC channels common sampling time: set a sampling time into one of the */
318 /* common sampling time available. */
319 #define ADC_SAMPLING_TIME_CH_MASK (ADC_CHANNEL_ID_BITFIELD_MASK << ADC_SMPR_SMPSEL0_BITOFFSET_POS)
320 #define ADC_SAMPLING_TIME_SMP_MASK (ADC_SMPR_SMP2 | ADC_SMPR_SMP1)
321 #define ADC_SAMPLING_TIME_SMP_SHIFT_MASK (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SMPR_SMP1_BITOFFSET_POS)
322
323 #endif /* ADC_SUPPORT_2_5_MSPS */
324
325 /* Internal mask for ADC mode single or differential ended: */
326 /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
327 /* the relevant bits for: */
328 /* (concatenation of multiple bits used in different registers) */
329 /* - ADC calibration: calibration start, calibration factor get or set */
330 /* - ADC channels: set each ADC channel ending mode */
331 #define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
332 #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
333 #define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
334 #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
335 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode: mask of bit */
336 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode: position of bit */
337 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */
338
339 /* Internal mask for ADC analog watchdog: */
340 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
341 /* (concatenation of multiple bits used in different analog watchdogs, */
342 /* (feature of several watchdogs not available on all STM32 families)). */
343 /* - analog watchdog 1: monitored channel defined by number, */
344 /* selection of ADC group (ADC groups regular and-or injected). */
345 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
346 /* selection on groups. */
347
348 /* Internal register offset for ADC analog watchdog channel configuration */
349 #define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
350 #define ADC_AWD_CR2_REGOFFSET (0x00100000UL)
351 #define ADC_AWD_CR3_REGOFFSET (0x00200000UL)
352
353 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
354 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
355 #define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
356 #define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
357
358 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
359 #define ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS (20UL)
360
361 #if defined(ADC_SUPPORT_2_5_MSPS)
362 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
363 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
364 #else
365 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
366 #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
367 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
368 #endif /* ADC_SUPPORT_2_5_MSPS */
369
370 #define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
371
372 /* Internal register offset for ADC analog watchdog threshold configuration */
373 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
374 #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
375 #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
376 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
377 #define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */
378 #define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */
379 #define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */
380 #define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */
381
382 /* Internal mask for ADC offset: */
383 /* Internal register offset for ADC offset number configuration */
384 #define ADC_OFR1_REGOFFSET (0x00000000UL)
385 #define ADC_OFR2_REGOFFSET (0x00000001UL)
386 #define ADC_OFR3_REGOFFSET (0x00000002UL)
387 #define ADC_OFR4_REGOFFSET (0x00000003UL)
388 #define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
389
390 /* ADC registers bits positions */
391 #if defined(ADC_SUPPORT_2_5_MSPS)
392 #define ADC_CFGR1_RES_BITOFFSET_POS ( 3UL) /* Value equivalent to bitfield "ADC_CFGR1_RES" position in register */
393 #define ADC_CFGR1_AWDSGL_BITOFFSET_POS (22UL) /* Value equivalent to bitfield "ADC_CFGR1_AWDSGL" position in register */
394 #define ADC_TR_HT_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_TR_HT" position in register */
395 #define ADC_CHSELR_CHSEL0_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL0" position in register */
396 #define ADC_CHSELR_CHSEL1_BITOFFSET_POS ( 1UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL1" position in register */
397 #define ADC_CHSELR_CHSEL2_BITOFFSET_POS ( 2UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL2" position in register */
398 #define ADC_CHSELR_CHSEL3_BITOFFSET_POS ( 3UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL3" position in register */
399 #define ADC_CHSELR_CHSEL4_BITOFFSET_POS ( 4UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL4" position in register */
400 #define ADC_CHSELR_CHSEL5_BITOFFSET_POS ( 5UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL5" position in register */
401 #define ADC_CHSELR_CHSEL6_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL6" position in register */
402 #define ADC_CHSELR_CHSEL7_BITOFFSET_POS ( 7UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL7" position in register */
403 #define ADC_CHSELR_CHSEL8_BITOFFSET_POS ( 8UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL8" position in register */
404 #define ADC_CHSELR_CHSEL9_BITOFFSET_POS ( 9UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL9" position in register */
405 #define ADC_CHSELR_CHSEL10_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL10" position in register */
406 #define ADC_CHSELR_CHSEL11_BITOFFSET_POS (11UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL11" position in register */
407 #define ADC_CHSELR_CHSEL12_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL12" position in register */
408 #define ADC_CHSELR_CHSEL13_BITOFFSET_POS (13UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL13" position in register */
409 #define ADC_CHSELR_CHSEL14_BITOFFSET_POS (14UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL14" position in register */
410 #define ADC_CHSELR_CHSEL15_BITOFFSET_POS (15UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL15" position in register */
411 #define ADC_CHSELR_CHSEL16_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL16" position in register */
412 #define ADC_CHSELR_CHSEL17_BITOFFSET_POS (17UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL17" position in register */
413 #define ADC_CHSELR_CHSEL18_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL18" position in register */
414 #define ADC_SMPR_SMP1_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SMPR_SMP1" position in register */
415 #define ADC_SMPR_SMP2_BITOFFSET_POS ( 4UL) /* Value equivalent to bitfield "ADC_SMPR_SMP2" position in register */
416 #define ADC_SMPR_SMPSEL0_BITOFFSET_POS ( 8UL) /* Value equivalent to bitfield "ADC_SMPR_SMPSEL0" position in register */
417 #define ADC_CFGR_RES_BITOFFSET_POS ADC_CFGR1_RES_BITOFFSET_POS
418 #define ADC_CFGR_AWDSGL_BITOFFSET_POS ADC_CFGR1_AWDSGL_BITOFFSET_POS
419 #else
420 #define ADC_CFGR_RES_BITOFFSET_POS ( 3UL) /* Value equivalent to bitfield "ADC_CFGR_RES" position in register */
421 #define ADC_CFGR_AWD1SGL_BITOFFSET_POS (22UL) /* Value equivalent to bitfield "ADC_CFGR_AWD1SGL" position in register */
422 #define ADC_CFGR_AWD1EN_BITOFFSET_POS (23UL) /* Value equivalent to bitfield "ADC_CFGR_AWD1EN" position in register */
423 #define ADC_CFGR_JAWD1EN_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_CFGR_JAWD1EN" position in register */
424 #define ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_TR1_HT1" position in register */
425 #endif /* ADC_SUPPORT_2_5_MSPS */
426
427
428 /* ADC registers bits groups */
429 #if defined(ADC_SUPPORT_2_5_MSPS)
430 #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
431 #else
432 #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
433 #endif /* ADC_SUPPORT_2_5_MSPS */
434
435
436 /* ADC internal channels related definitions */
437 /* Internal voltage reference VrefInt */
438 #define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of parameter VREFINT: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.6 V (tolerance: +-10 mV). */
439 #define VREFINT_CAL_VREF (3600UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
440 /* Temperature sensor */
441 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32WB, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
442 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAUL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32WB, temperature sensor ADC raw data acquired at temperature 130 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
443 #define TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
444 #define TEMPSENSOR_CAL2_TEMP (130L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
445 #define TEMPSENSOR_CAL_VREFANALOG (3000UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
446
447
448 /**
449 * @}
450 */
451
452
453 /* Private macros ------------------------------------------------------------*/
454 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
455 * @{
456 */
457
458 /**
459 * @brief Driver macro reserved for internal use: set a pointer to
460 * a register from a register basis from which an offset
461 * is applied.
462 * @param __REG__ Register basis from which the offset is applied.
463 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
464 * @retval Pointer to register address
465 */
466 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
467 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
468
469 /**
470 * @}
471 */
472
473
474 /* Exported types ------------------------------------------------------------*/
475 #if defined(USE_FULL_LL_DRIVER)
476 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
477 * @{
478 */
479
480 /**
481 * @brief Structure definition of some features of ADC common parameters
482 * and multimode
483 * (all ADC instances belonging to the same ADC common instance).
484 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
485 * is conditioned to ADC instances state (all ADC instances
486 * sharing the same ADC common instance):
487 * All ADC instances sharing the same ADC common instance must be
488 * disabled.
489 */
490 typedef struct
491 {
492 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
493 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
494 @note On this STM32 series, if ADC group injected is used, some
495 clock ratio constraints between ADC clock and AHB clock
496 must be respected. Refer to reference manual.
497
498 This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
499
500 } LL_ADC_CommonInitTypeDef;
501
502 /**
503 * @brief Structure definition of some features of ADC instance.
504 * @note These parameters have an impact on ADC scope: ADC instance.
505 * Affects both group regular and group injected (availability
506 * of ADC group injected depends on STM32 families).
507 * Refer to corresponding unitary functions into
508 * @ref ADC_LL_EF_Configuration_ADC_Instance .
509 * @note The setting of these parameters by function @ref LL_ADC_Init()
510 * is conditioned to ADC state:
511 * ADC instance must be disabled.
512 * This condition is applied to all ADC features, for efficiency
513 * and compatibility over all STM32 families. However, the different
514 * features can be set under different ADC state conditions
515 * (setting possible with ADC enabled without conversion on going,
516 * ADC enabled with conversion on going, ...)
517 * Each feature can be updated afterwards with a unitary function
518 * and potentially with ADC in a different state than disabled,
519 * refer to description of each function for setting
520 * conditioned to ADC state.
521 */
522 typedef struct
523 {
524 #if defined(ADC_SUPPORT_2_5_MSPS)
525 uint32_t Clock; /*!< Set ADC instance clock source and prescaler.
526 This parameter can be a value of @ref ADC_LL_EC_CLOCK_SOURCE
527 @note On this STM32 series, this parameter has some clock ratio constraints:
528 ADC clock synchronous (from PCLK) with prescaler 1 must be enabled only if PCLK has a 50% duty clock cycle
529 (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle).
530
531 This feature can be modified afterwards using unitary function @ref LL_ADC_SetClock().
532 For more details, refer to description of this function. */
533
534 #endif /* ADC_SUPPORT_2_5_MSPS */
535 uint32_t Resolution; /*!< Set ADC resolution.
536 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
537
538 This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
539
540 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
541 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
542
543 This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
544
545 uint32_t LowPowerMode; /*!< Set ADC low power mode.
546 This parameter can be a value of @ref ADC_LL_EC_LP_MODE
547
548 This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
549
550 } LL_ADC_InitTypeDef;
551
552 /**
553 * @brief Structure definition of some features of ADC group regular.
554 * @note These parameters have an impact on ADC scope: ADC group regular.
555 * Refer to corresponding unitary functions into
556 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
557 * (functions with prefix "REG").
558 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
559 * is conditioned to ADC state:
560 * ADC instance must be disabled.
561 * This condition is applied to all ADC features, for efficiency
562 * and compatibility over all STM32 families. However, the different
563 * features can be set under different ADC state conditions
564 * (setting possible with ADC enabled without conversion on going,
565 * ADC enabled with conversion on going, ...)
566 * Each feature can be updated afterwards with a unitary function
567 * and potentially with ADC in a different state than disabled,
568 * refer to description of each function for setting
569 * conditioned to ADC state.
570 */
571 typedef struct
572 {
573 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
574 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
575 @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge
576 (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
577 In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
578
579 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
580
581 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
582 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
583
584 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
585
586 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
587 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
588 @note This parameter has an effect only if group regular sequencer is enabled
589 (scan length of 2 ranks or more).
590
591 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
592
593 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
594 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
595 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
596
597 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
598
599 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
600 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
601
602 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
603
604 uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
605 data preserved or overwritten.
606 This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
607
608 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
609
610 } LL_ADC_REG_InitTypeDef;
611
612 #if defined(ADC_SUPPORT_2_5_MSPS)
613 /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
614 #else
615 /**
616 * @brief Structure definition of some features of ADC group injected.
617 * @note These parameters have an impact on ADC scope: ADC group injected.
618 * Refer to corresponding unitary functions into
619 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
620 * (functions with prefix "INJ").
621 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
622 * is conditioned to ADC state:
623 * ADC instance must be disabled.
624 * This condition is applied to all ADC features, for efficiency
625 * and compatibility over all STM32 families. However, the different
626 * features can be set under different ADC state conditions
627 * (setting possible with ADC enabled without conversion on going,
628 * ADC enabled with conversion on going, ...)
629 * Each feature can be updated afterwards with a unitary function
630 * and potentially with ADC in a different state than disabled,
631 * refer to description of each function for setting
632 * conditioned to ADC state.
633 */
634 typedef struct
635 {
636 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
637 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
638 @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge
639 (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
640 In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().
641
642 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
643
644 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
645 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
646
647 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
648
649 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
650 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
651 @note This parameter has an effect only if group injected sequencer is enabled
652 (scan length of 2 ranks or more).
653
654 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
655
656 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
657 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
658 Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
659
660 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
661
662 } LL_ADC_INJ_InitTypeDef;
663 #endif /* ADC_SUPPORT_2_5_MSPS */
664
665 /**
666 * @}
667 */
668 #endif /* USE_FULL_LL_DRIVER */
669
670 /* Exported constants --------------------------------------------------------*/
671 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
672 * @{
673 */
674
675 /** @defgroup ADC_LL_EC_FLAG ADC flags
676 * @brief Flags defines which can be used with LL_ADC_ReadReg function
677 * @{
678 */
679 #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
680 #if defined(ADC_SUPPORT_2_5_MSPS)
681 #define LL_ADC_FLAG_CCRDY ADC_ISR_CCRDY /*!< ADC flag ADC channel configuration ready */
682 #else
683 #endif /* ADC_SUPPORT_2_5_MSPS */
684 #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */
685 #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */
686 #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
687 #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
688 #define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary conversion */
689 #define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence conversions */
690 #define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue overflow */
691 #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
692 #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
693 #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
694 #if defined(ADC_SUPPORT_2_5_MSPS)
695 #define LL_ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC flag end of calibration */
696 #endif /* ADC_SUPPORT_2_5_MSPS */
697 /**
698 * @}
699 */
700
701 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
702 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
703 * @{
704 */
705 #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
706 #if defined(ADC_SUPPORT_2_5_MSPS)
707 #define LL_ADC_IT_CCRDY ADC_IER_CCRDYIE /*!< ADC interruption channel configuration ready */
708 #else
709 #endif /* ADC_SUPPORT_2_5_MSPS */
710 #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */
711 #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */
712 #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
713 #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */
714 #define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary conversion */
715 #define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence conversions */
716 #define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts queue overflow */
717 #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
718 #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
719 #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
720 #if defined(ADC_SUPPORT_2_5_MSPS)
721 #define LL_ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC interruption ADC end of calibration */
722 #endif /* ADC_SUPPORT_2_5_MSPS */
723 /**
724 * @}
725 */
726
727 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
728 * @{
729 */
730 /* List of ADC registers intended to be used (most commonly) with */
731 /* DMA transfer. */
732 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
733 #define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
734 /**
735 * @}
736 */
737
738 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
739 * @{
740 */
741 #if !defined(ADC_SUPPORT_2_5_MSPS)
742 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */
743 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
744 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
745 #endif /* !ADC_SUPPORT_2_5_MSPS */
746 #define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without prescaler */
747 #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 2 */
748 #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 4 */
749 #define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 6 */
750 #define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 ) /*!< ADC asynchronous clock with prescaler division by 8 */
751 #define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10 */
752 #define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 12 */
753 #define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16 */
754 #define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with prescaler division by 32 */
755 #define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 64 */
756 #define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division by 128 */
757 #define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256 */
758 /**
759 * @}
760 */
761
762 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
763 * @{
764 */
765 /* Note: Other measurement paths to internal channels may be available */
766 /* (connections to other peripherals). */
767 /* If they are not listed below, they do not require any specific */
768 /* path enable. In this case, Access to measurement path is done */
769 /* only by selecting the corresponding ADC internal channel. */
770 #define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */
771 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
772 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */
773 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
774 /**
775 * @}
776 */
777
778 #if defined(ADC_SUPPORT_2_5_MSPS)
779 /** @defgroup ADC_LL_EC_CLOCK_SOURCE ADC instance - Clock source
780 * @{
781 */
782 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by 4 */
783 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock divided by 2 */
784 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CFGR2_CKMODE_1 | ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock not divided */
785 #define LL_ADC_CLOCK_ASYNC (0x00000000UL) /*!< ADC asynchronous clock. Asynchronous clock prescaler can be configured using function @ref LL_ADC_SetCommonClock(). */
786 /**
787 * @}
788 */
789 #endif /* ADC_SUPPORT_2_5_MSPS */
790
791 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
792 * @{
793 */
794 #define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bits */
795 #define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */
796 #define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 ) /*!< ADC resolution 8 bits */
797 #define LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 6 bits */
798 /**
799 * @}
800 */
801
802 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
803 * @{
804 */
805 #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
806 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
807 /**
808 * @}
809 */
810
811 /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
812 * @{
813 */
814 #define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */
815 #if defined(ADC_SUPPORT_2_5_MSPS)
816 #define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_WAIT) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
817 #define LL_ADC_LP_AUTOPOWEROFF (ADC_CFGR1_AUTOFF) /*!< ADC low power mode auto power-off: the ADC automatically powers-off after a ADC conversion and automatically wakes up when a new ADC conversion is triggered (with startup time between trigger and start of sampling). See description with function @ref LL_ADC_SetLowPowerMode(). */
818 #define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF) /*!< ADC low power modes auto wait and auto power-off combined. See description with function @ref LL_ADC_SetLowPowerMode(). */
819 #else
820 #define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
821 #endif /* ADC_SUPPORT_2_5_MSPS */
822 /**
823 * @}
824 */
825
826 /** @defgroup ADC_LL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode
827 * @{
828 */
829 #define LL_ADC_TRIGGER_FREQ_HIGH (0x00000000UL) /*!< ADC trigger frequency mode set to high frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
830 #define LL_ADC_TRIGGER_FREQ_LOW (ADC_CFGR2_LFTRIG) /*!< ADC trigger frequency mode set to low frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
831 /**
832 * @}
833 */
834
835 #if defined(ADC_SUPPORT_2_5_MSPS)
836 /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels
837 * @{
838 */
839 #define LL_ADC_SAMPLINGTIME_COMMON_1 (ADC_SMPR_SMP1_BITOFFSET_POS) /*!< Set sampling time common to a group of channels: sampling time nb 1 */
840 #define LL_ADC_SAMPLINGTIME_COMMON_2 (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SAMPLING_TIME_CH_MASK) /*!< Set sampling time common to a group of channels: sampling time nb 2 */
841 /**
842 * @}
843 */
844
845 #endif /* ADC_SUPPORT_2_5_MSPS */
846 /** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number
847 * @{
848 */
849 #define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
850 #define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
851 #define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
852 #define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
853 /**
854 * @}
855 */
856
857 /** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
858 * @{
859 */
860 #define LL_ADC_OFFSET_DISABLE (0x00000000UL) /*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */
861 #define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN) /*!< ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4) */
862 /**
863 * @}
864 */
865
866 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
867 * @{
868 */
869 #define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
870 #if !defined(ADC_SUPPORT_2_5_MSPS)
871 #define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/
872 #define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */
873 #endif /* !ADC_SUPPORT_2_5_MSPS */
874 /**
875 * @}
876 */
877
878 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
879 * @{
880 */
881 #if defined(ADC_SUPPORT_2_5_MSPS)
882 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
883 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
884 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
885 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
886 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
887 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
888 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
889 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
890 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
891 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
892 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
893 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
894 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
895 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
896 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
897 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
898 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
899 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
900 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
901 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */
902 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_12 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */
903 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. */
904 #else
905 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
906 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
907 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
908 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
909 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
910 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
911 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
912 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
913 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
914 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
915 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
916 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
917 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
918 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
919 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
920 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
921 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
922 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
923 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
924 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_0 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */
925 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */
926 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/2: Vbat voltage through a divider ladder of factor 1/2 to have Vbat always below Vdda. */
927
928 #endif /* ADC_SUPPORT_2_5_MSPS */
929 /**
930 * @}
931 */
932
933 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
934 * @{
935 */
936 #if defined(ADC_SUPPORT_2_5_MSPS)
937 #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start. */
938 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 ( ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
939 #define LL_ADC_REG_TRIG_EXT_TIM1_CH4 ( ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
940 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO ( ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
941 #define LL_ADC_REG_TRIG_EXT_TIM2_CH4 ( ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
942 #define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
943 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
944 #else
945 #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start. */
946 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
947 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
948 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
949 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
950 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
951 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
952 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
953 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
954 #endif /* ADC_SUPPORT_2_5_MSPS */
955 /**
956 * @}
957 */
958
959 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
960 * @{
961 */
962 #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
963 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
964 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
965 /**
966 * @}
967 */
968
969 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
970 * @{
971 */
972 #define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions are performed in single mode: one conversion per trigger */
973 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
974 /**
975 * @}
976 */
977
978 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
979 * @{
980 */
981 #define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */
982 #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
983 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
984 /**
985 * @}
986 */
987
988
989
990 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
991 * @{
992 */
993 #define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: data preserved */
994 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */
995 /**
996 * @}
997 */
998
999 #if defined(ADC_SUPPORT_2_5_MSPS)
1000 /** @defgroup ADC_LL_EC_REG_SEQ_MODE ADC group regular - Sequencer configuration flexibility
1001 * @{
1002 */
1003 #define LL_ADC_REG_SEQ_FIXED (0x00000000UL) /*!< Sequencer configured to fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). */
1004 #define LL_ADC_REG_SEQ_CONFIGURABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer configured to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number. Refer to description of function @ref LL_ADC_REG_SetSequencerChannels(). */
1005 /**
1006 * @}
1007 */
1008
1009 #endif /* ADC_SUPPORT_2_5_MSPS */
1010 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
1011 * @{
1012 */
1013 #if defined(ADC_SUPPORT_2_5_MSPS)
1014 #define LL_ADC_REG_SEQ_SCAN_DISABLE (ADC_CHSELR_SQ2) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1015 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_CHSELR_SQ3) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
1016 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_CHSELR_SQ4) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
1017 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
1018 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_CHSELR_SQ6) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
1019 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_CHSELR_SQ7) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
1020 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_CHSELR_SQ8) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
1021 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS (0x00000000UL) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
1022 #else
1023 #define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1024 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
1025 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
1026 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
1027 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
1028 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
1029 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
1030 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
1031 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
1032 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
1033 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
1034 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
1035 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
1036 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
1037 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
1038 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
1039 #endif /* ADC_SUPPORT_2_5_MSPS */
1040 /**
1041 * @}
1042 */
1043
1044 #if defined(ADC_SUPPORT_2_5_MSPS)
1045 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION ADC group regular - Sequencer scan direction
1046 * @{
1047 */
1048 #define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000UL) /*!< On this STM32 series, parameter relevant only is sequencer set to mode not fully configurable, refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other STM32 families, this setting is not available and the default scan direction is forward. */
1049 #define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR) /*!< On this STM32 series, parameter relevant only is sequencer set to mode not fully configurable, refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan direction backward: from highest channel number to lowest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer) */
1050 /**
1051 * @}
1052 */
1053
1054 #endif /* ADC_SUPPORT_2_5_MSPS */
1055 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
1056 * @{
1057 */
1058 #define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer discontinuous mode disable */
1059 #if defined(ADC_SUPPORT_2_5_MSPS)
1060 #define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
1061 #else
1062 #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
1063 #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
1064 #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
1065 #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
1066 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
1067 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
1068 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
1069 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
1070 #endif /* ADC_SUPPORT_2_5_MSPS */
1071 /**
1072 * @}
1073 */
1074
1075 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
1076 * @{
1077 */
1078 #if defined(ADC_SUPPORT_2_5_MSPS)
1079 #define LL_ADC_REG_RANK_1 (ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
1080 #define LL_ADC_REG_RANK_2 (ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
1081 #define LL_ADC_REG_RANK_3 (ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
1082 #define LL_ADC_REG_RANK_4 (ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
1083 #define LL_ADC_REG_RANK_5 (ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
1084 #define LL_ADC_REG_RANK_6 (ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
1085 #define LL_ADC_REG_RANK_7 (ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
1086 #define LL_ADC_REG_RANK_8 (ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
1087 #else
1088 #define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
1089 #define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
1090 #define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
1091 #define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
1092 #define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
1093 #define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
1094 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
1095 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
1096 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
1097 #define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
1098 #define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
1099 #define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
1100 #define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
1101 #define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
1102 #define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
1103 #define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
1104 #endif /* ADC_SUPPORT_2_5_MSPS */
1105 /**
1106 * @}
1107 */
1108
1109 #if defined(ADC_SUPPORT_2_5_MSPS)
1110 /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
1111 #else
1112 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
1113 * @{
1114 */
1115 #define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group injected conversion trigger internal: SW start.. Trigger edge set to rising edge (default setting). */
1116 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
1117 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
1118 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1119 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
1120 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1121 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */
1122 /**
1123 * @}
1124 */
1125
1126 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
1127 * @{
1128 */
1129 #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
1130 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */
1131 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
1132 /**
1133 * @}
1134 */
1135
1136 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
1137 * @{
1138 */
1139 #define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
1140 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
1141 /**
1142 * @}
1143 */
1144
1145 /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode
1146 * @{
1147 */
1148 #define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
1149 #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
1150 #define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */
1151 /**
1152 * @}
1153 */
1154
1155 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
1156 * @{
1157 */
1158 #define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1159 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
1160 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
1161 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
1162 /**
1163 * @}
1164 */
1165
1166 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
1167 * @{
1168 */
1169 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode disable */
1170 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
1171 /**
1172 * @}
1173 */
1174
1175 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
1176 * @{
1177 */
1178 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
1179 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
1180 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
1181 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
1182 /**
1183 * @}
1184 */
1185 #endif /* ADC_SUPPORT_2_5_MSPS */
1186
1187 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
1188 * @{
1189 */
1190 #if defined(ADC_SUPPORT_2_5_MSPS)
1191 #define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL) /*!< Sampling time 1.5 ADC clock cycle */
1192 #define LL_ADC_SAMPLINGTIME_3CYCLES_5 (ADC_SMPR_SMP1_0) /*!< Sampling time 3.5 ADC clock cycles */
1193 #define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP1_1) /*!< Sampling time 7.5 ADC clock cycles */
1194 #define LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR_SMP1_1 | ADC_SMPR_SMP1_0) /*!< Sampling time 12.5 ADC clock cycles */
1195 #define LL_ADC_SAMPLINGTIME_19CYCLES_5 (ADC_SMPR_SMP1_2) /*!< Sampling time 19.5 ADC clock cycles */
1196 #define LL_ADC_SAMPLINGTIME_39CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_0) /*!< Sampling time 39.5 ADC clock cycles */
1197 #define LL_ADC_SAMPLINGTIME_79CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_1) /*!< Sampling time 79.5 ADC clock cycles */
1198 #define LL_ADC_SAMPLINGTIME_160CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_1 | ADC_SMPR_SMP1_0) /*!< Sampling time 160.5 ADC clock cycles */
1199 #else
1200 #define LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000UL) /*!< Sampling time 2.5 ADC clock cycles */
1201 #define LL_ADC_SAMPLINGTIME_6CYCLES_5 ( ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */
1202 #define LL_ADC_SAMPLINGTIME_12CYCLES_5 ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 12.5 ADC clock cycles */
1203 #define LL_ADC_SAMPLINGTIME_24CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */
1204 #define LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2 ) /*!< Sampling time 47.5 ADC clock cycles */
1205 #define LL_ADC_SAMPLINGTIME_92CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */
1206 #define LL_ADC_SAMPLINGTIME_247CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 247.5 ADC clock cycles */
1207 #define LL_ADC_SAMPLINGTIME_640CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */
1208 #endif /* ADC_SUPPORT_2_5_MSPS */
1209 /**
1210 * @}
1211 */
1212
1213 /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
1214 * @{
1215 */
1216 #if defined(ADC_SUPPORT_2_5_MSPS)
1217 #define LL_ADC_SINGLE_ENDED (0x00000000UL) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
1218 #else
1219 #define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
1220 #define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
1221 #define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */
1222 #endif /* ADC_SUPPORT_2_5_MSPS */
1223 /**
1224 * @}
1225 */
1226
1227 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
1228 * @{
1229 */
1230 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
1231 #if defined(ADC_SUPPORT_2_5_MSPS)
1232 /* Feature "ADC analog watchdog 2 and 3" not available on ADC peripheral of this STM32WB device */
1233 #else
1234 #define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
1235 #define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
1236 #endif /* ADC_SUPPORT_2_5_MSPS */
1237 /**
1238 * @}
1239 */
1240
1241 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
1242 * @{
1243 */
1244 #if defined(ADC_SUPPORT_2_5_MSPS)
1245 #define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */
1246 #define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CFGR1_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
1247 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
1248 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
1249 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
1250 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
1251 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
1252 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
1253 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
1254 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
1255 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
1256 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
1257 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
1258 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
1259 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
1260 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
1261 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
1262 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
1263 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
1264 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
1265 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
1266 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
1267 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
1268 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
1269 #else
1270 #define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */
1271 #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
1272 #define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
1273 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
1274 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
1275 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
1276 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
1277 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
1278 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
1279 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
1280 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
1281 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
1282 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
1283 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
1284 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
1285 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
1286 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
1287 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
1288 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
1289 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
1290 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
1291 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
1292 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
1293 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
1294 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
1295 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
1296 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
1297 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
1298 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
1299 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
1300 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
1301 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
1302 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
1303 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
1304 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
1305 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
1306 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
1307 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
1308 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
1309 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
1310 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
1311 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
1312 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
1313 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
1314 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
1315 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
1316 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
1317 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
1318 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
1319 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
1320 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
1321 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
1322 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
1323 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
1324 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
1325 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
1326 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
1327 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
1328 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
1329 #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
1330 #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
1331 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
1332 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
1333 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
1334 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
1335 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
1336 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
1337 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
1338 #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */
1339 #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */
1340 #endif /* ADC_SUPPORT_2_5_MSPS */
1341 /**
1342 * @}
1343 */
1344
1345 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
1346 * @{
1347 */
1348 #if defined (ADC_SUPPORT_2_5_MSPS)
1349 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR_HT ) /*!< ADC analog watchdog threshold high */
1350 #define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR_LT) /*!< ADC analog watchdog threshold low */
1351 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR_HT | ADC_TR_LT) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */
1352 #else
1353 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1 ) /*!< ADC analog watchdog threshold high */
1354 #define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */
1355 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */
1356 #endif /* ADC_SUPPORT_2_5_MSPS */
1357 /**
1358 * @}
1359 */
1360
1361 /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
1362 * @{
1363 */
1364 #if defined(ADC_SUPPORT_2_5_MSPS)
1365 #define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
1366 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_OVSE) /*!< ADC oversampling on conversions of ADC group regular. Literal suffix "continued" is kept for compatibility with other STM32 devices featuring ADC group injected, in this case other oversampling scope parameters are available. */
1367 #else
1368 #define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
1369 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */
1370 #define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
1371 #define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE ) /*!< ADC oversampling on conversions of ADC group injected. */
1372 #define LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
1373 #endif /* ADC_SUPPORT_2_5_MSPS */
1374 /**
1375 * @}
1376 */
1377
1378 /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
1379 * @{
1380 */
1381 #define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
1382 #if defined(ADC_SUPPORT_2_5_MSPS)
1383 #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TOVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
1384 #else
1385 #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
1386 #endif /* ADC_SUPPORT_2_5_MSPS */
1387 /**
1388 * @}
1389 */
1390
1391 /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio
1392 * @{
1393 */
1394 #define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1395 #define LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1396 #define LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1397 #define LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1398 #define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2 ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1399 #define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1400 #define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1401 #define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1402 /**
1403 * @}
1404 */
1405
1406 /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift
1407 * @{
1408 */
1409 #define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
1410 #define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
1411 #define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
1412 #define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
1413 #define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
1414 #define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
1415 #define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
1416 #define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
1417 #define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
1418 /**
1419 * @}
1420 */
1421
1422
1423 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
1424 * @note Only ADC peripheral HW delays are defined in ADC LL driver driver,
1425 * not timeout values.
1426 * For details on delays values, refer to descriptions in source code
1427 * above each literal definition.
1428 * @{
1429 */
1430
1431 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
1432 /* not timeout values. */
1433 /* Timeout values for ADC operations are dependent to device clock */
1434 /* configuration (system clock versus ADC clock), */
1435 /* and therefore must be defined in user application. */
1436 /* Indications for estimation of ADC timeout delays, for this */
1437 /* STM32 series: */
1438 /* - ADC calibration time: maximum delay is 112/fADC. */
1439 /* (refer to device datasheet, parameter "tCAL") */
1440 /* - ADC enable time: maximum delay is 1 conversion cycle. */
1441 /* (refer to device datasheet, parameter "tSTAB") */
1442 /* - ADC disable time: maximum delay should be a few ADC clock cycles */
1443 /* - ADC stop conversion time: maximum delay should be a few ADC clock */
1444 /* cycles */
1445 /* - ADC conversion time: duration depending on ADC clock and ADC */
1446 /* configuration. */
1447 /* (refer to device reference manual, section "Timing") */
1448
1449 /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1450 /* Delay set to maximum value (refer to device datasheet, */
1451 /* parameter "tADCVREG_STUP"). */
1452 /* Unit: us */
1453 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1454
1455 /* Delay for internal voltage reference stabilization time. */
1456 /* Delay set to maximum value (refer to device datasheet, */
1457 /* parameter "tstart_vrefint"). */
1458 /* Unit: us */
1459 #define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization time */
1460
1461 /* Delay for temperature sensor stabilization time. */
1462 /* Literal set to maximum value (refer to device datasheet, */
1463 /* parameter "tSTART"). */
1464 /* Unit: us */
1465 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */
1466 #define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL) /*!< Delay for temperature sensor buffer stabilization time (starting from ADC enable, refer to @ref LL_ADC_Enable()) */
1467
1468 /* Delay required between ADC end of calibration and ADC enable. */
1469 /* Note: On this STM32 series, a minimum number of ADC clock cycles */
1470 /* are required between ADC end of calibration and ADC enable. */
1471 /* Wait time can be computed in user application by waiting for the */
1472 /* equivalent number of CPU cycles, by taking into account */
1473 /* ratio of CPU clock versus ADC clock prescalers. */
1474 /* Unit: ADC clock cycles. */
1475 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */
1476
1477 /**
1478 * @}
1479 */
1480
1481 /**
1482 * @}
1483 */
1484
1485
1486 /* Exported macro ------------------------------------------------------------*/
1487 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
1488 * @{
1489 */
1490
1491 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
1492 * @{
1493 */
1494
1495 /**
1496 * @brief Write a value in ADC register
1497 * @param __INSTANCE__ ADC Instance
1498 * @param __REG__ Register to be written
1499 * @param __VALUE__ Value to be written in the register
1500 * @retval None
1501 */
1502 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1503
1504 /**
1505 * @brief Read a value in ADC register
1506 * @param __INSTANCE__ ADC Instance
1507 * @param __REG__ Register to be read
1508 * @retval Register value
1509 */
1510 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1511 /**
1512 * @}
1513 */
1514
1515 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
1516 * @{
1517 */
1518
1519 /**
1520 * @brief Helper macro to get ADC channel number in decimal format
1521 * from literals LL_ADC_CHANNEL_x.
1522 * @note Example:
1523 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
1524 * will return decimal number "4".
1525 * @note The input can be a value from functions where a channel
1526 * number is returned, either defined with number
1527 * or with bitfield (only one bit must be set).
1528 * @param __CHANNEL__ This parameter can be one of the following values:
1529 * @arg @ref LL_ADC_CHANNEL_0
1530 * @arg @ref LL_ADC_CHANNEL_1 (7)
1531 * @arg @ref LL_ADC_CHANNEL_2 (7)
1532 * @arg @ref LL_ADC_CHANNEL_3 (7)
1533 * @arg @ref LL_ADC_CHANNEL_4 (7)
1534 * @arg @ref LL_ADC_CHANNEL_5 (7)
1535 * @arg @ref LL_ADC_CHANNEL_6
1536 * @arg @ref LL_ADC_CHANNEL_7
1537 * @arg @ref LL_ADC_CHANNEL_8
1538 * @arg @ref LL_ADC_CHANNEL_9
1539 * @arg @ref LL_ADC_CHANNEL_10
1540 * @arg @ref LL_ADC_CHANNEL_11
1541 * @arg @ref LL_ADC_CHANNEL_12
1542 * @arg @ref LL_ADC_CHANNEL_13
1543 * @arg @ref LL_ADC_CHANNEL_14
1544 * @arg @ref LL_ADC_CHANNEL_15
1545 * @arg @ref LL_ADC_CHANNEL_16
1546 * @arg @ref LL_ADC_CHANNEL_17
1547 * @arg @ref LL_ADC_CHANNEL_18
1548 * @arg @ref LL_ADC_CHANNEL_VREFINT
1549 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
1550 * @arg @ref LL_ADC_CHANNEL_VBAT
1551 *
1552 * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
1553 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
1554 * @retval Value between Min_Data=0 and Max_Data=18
1555 */
1556 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1557 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) \
1558 ? ( \
1559 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
1560 ) \
1561 : \
1562 ( \
1563 (uint32_t)POSITION_VAL((__CHANNEL__)) \
1564 ) \
1565 )
1566
1567 /**
1568 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
1569 * from number in decimal format.
1570 * @note Example:
1571 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
1572 * will return a data equivalent to "LL_ADC_CHANNEL_4".
1573 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
1574 * @retval Returned value can be one of the following values:
1575 * @arg @ref LL_ADC_CHANNEL_0
1576 * @arg @ref LL_ADC_CHANNEL_1 (7)
1577 * @arg @ref LL_ADC_CHANNEL_2 (7)
1578 * @arg @ref LL_ADC_CHANNEL_3 (7)
1579 * @arg @ref LL_ADC_CHANNEL_4 (7)
1580 * @arg @ref LL_ADC_CHANNEL_5 (7)
1581 * @arg @ref LL_ADC_CHANNEL_6
1582 * @arg @ref LL_ADC_CHANNEL_7
1583 * @arg @ref LL_ADC_CHANNEL_8
1584 * @arg @ref LL_ADC_CHANNEL_9
1585 * @arg @ref LL_ADC_CHANNEL_10
1586 * @arg @ref LL_ADC_CHANNEL_11
1587 * @arg @ref LL_ADC_CHANNEL_12
1588 * @arg @ref LL_ADC_CHANNEL_13
1589 * @arg @ref LL_ADC_CHANNEL_14
1590 * @arg @ref LL_ADC_CHANNEL_15
1591 * @arg @ref LL_ADC_CHANNEL_16
1592 * @arg @ref LL_ADC_CHANNEL_17
1593 * @arg @ref LL_ADC_CHANNEL_18
1594 * @arg @ref LL_ADC_CHANNEL_VREFINT (4)
1595 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
1596 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
1597 *
1598 * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
1599 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
1600 * (4) For ADC channel read back from ADC register,
1601 * comparison with internal channel parameter to be done
1602 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1603 */
1604 #if defined(ADC_SUPPORT_2_5_MSPS)
1605 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1606 ( \
1607 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1608 (ADC_CHSELR_CHSEL0 << (__DECIMAL_NB__)) \
1609 )
1610 #else
1611 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1612 (((__DECIMAL_NB__) <= 9UL) \
1613 ? ( \
1614 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1615 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
1616 (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1617 ) \
1618 : \
1619 ( \
1620 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1621 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
1622 (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1623 ) \
1624 )
1625 #endif /* ADC_SUPPORT_2_5_MSPS */
1626
1627 /**
1628 * @brief Helper macro to determine whether the selected channel
1629 * corresponds to literal definitions of driver.
1630 * @note The different literal definitions of ADC channels are:
1631 * - ADC internal channel:
1632 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
1633 * - ADC external channel (channel connected to a GPIO pin):
1634 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
1635 * @note The channel parameter must be a value defined from literal
1636 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1637 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1638 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
1639 * must not be a value from functions where a channel number is
1640 * returned from ADC registers,
1641 * because internal and external channels share the same channel
1642 * number in ADC registers. The differentiation is made only with
1643 * parameters definitions of driver.
1644 * @param __CHANNEL__ This parameter can be one of the following values:
1645 * @arg @ref LL_ADC_CHANNEL_0
1646 * @arg @ref LL_ADC_CHANNEL_1 (7)
1647 * @arg @ref LL_ADC_CHANNEL_2 (7)
1648 * @arg @ref LL_ADC_CHANNEL_3 (7)
1649 * @arg @ref LL_ADC_CHANNEL_4 (7)
1650 * @arg @ref LL_ADC_CHANNEL_5 (7)
1651 * @arg @ref LL_ADC_CHANNEL_6
1652 * @arg @ref LL_ADC_CHANNEL_7
1653 * @arg @ref LL_ADC_CHANNEL_8
1654 * @arg @ref LL_ADC_CHANNEL_9
1655 * @arg @ref LL_ADC_CHANNEL_10
1656 * @arg @ref LL_ADC_CHANNEL_11
1657 * @arg @ref LL_ADC_CHANNEL_12
1658 * @arg @ref LL_ADC_CHANNEL_13
1659 * @arg @ref LL_ADC_CHANNEL_14
1660 * @arg @ref LL_ADC_CHANNEL_15
1661 * @arg @ref LL_ADC_CHANNEL_16
1662 * @arg @ref LL_ADC_CHANNEL_17
1663 * @arg @ref LL_ADC_CHANNEL_18
1664 * @arg @ref LL_ADC_CHANNEL_VREFINT
1665 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
1666 * @arg @ref LL_ADC_CHANNEL_VBAT
1667 *
1668 * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
1669 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
1670 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
1671 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
1672 */
1673 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1674 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
1675
1676 /**
1677 * @brief Helper macro to convert a channel defined from parameter
1678 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1679 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1680 * to its equivalent parameter definition of a ADC external channel
1681 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
1682 * @note The channel parameter can be, additionally to a value
1683 * defined from parameter definition of a ADC internal channel
1684 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
1685 * a value defined from parameter definition of
1686 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1687 * or a value from functions where a channel number is returned
1688 * from ADC registers.
1689 * @param __CHANNEL__ This parameter can be one of the following values:
1690 * @arg @ref LL_ADC_CHANNEL_0
1691 * @arg @ref LL_ADC_CHANNEL_1 (7)
1692 * @arg @ref LL_ADC_CHANNEL_2 (7)
1693 * @arg @ref LL_ADC_CHANNEL_3 (7)
1694 * @arg @ref LL_ADC_CHANNEL_4 (7)
1695 * @arg @ref LL_ADC_CHANNEL_5 (7)
1696 * @arg @ref LL_ADC_CHANNEL_6
1697 * @arg @ref LL_ADC_CHANNEL_7
1698 * @arg @ref LL_ADC_CHANNEL_8
1699 * @arg @ref LL_ADC_CHANNEL_9
1700 * @arg @ref LL_ADC_CHANNEL_10
1701 * @arg @ref LL_ADC_CHANNEL_11
1702 * @arg @ref LL_ADC_CHANNEL_12
1703 * @arg @ref LL_ADC_CHANNEL_13
1704 * @arg @ref LL_ADC_CHANNEL_14
1705 * @arg @ref LL_ADC_CHANNEL_15
1706 * @arg @ref LL_ADC_CHANNEL_16
1707 * @arg @ref LL_ADC_CHANNEL_17
1708 * @arg @ref LL_ADC_CHANNEL_18
1709 * @arg @ref LL_ADC_CHANNEL_VREFINT
1710 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
1711 * @arg @ref LL_ADC_CHANNEL_VBAT
1712 *
1713 * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
1714 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
1715 * @retval Returned value can be one of the following values:
1716 * @arg @ref LL_ADC_CHANNEL_0
1717 * @arg @ref LL_ADC_CHANNEL_1
1718 * @arg @ref LL_ADC_CHANNEL_2
1719 * @arg @ref LL_ADC_CHANNEL_3
1720 * @arg @ref LL_ADC_CHANNEL_4
1721 * @arg @ref LL_ADC_CHANNEL_5
1722 * @arg @ref LL_ADC_CHANNEL_6
1723 * @arg @ref LL_ADC_CHANNEL_7
1724 * @arg @ref LL_ADC_CHANNEL_8
1725 * @arg @ref LL_ADC_CHANNEL_9
1726 * @arg @ref LL_ADC_CHANNEL_10
1727 * @arg @ref LL_ADC_CHANNEL_11
1728 * @arg @ref LL_ADC_CHANNEL_12
1729 * @arg @ref LL_ADC_CHANNEL_13
1730 * @arg @ref LL_ADC_CHANNEL_14
1731 * @arg @ref LL_ADC_CHANNEL_15
1732 * @arg @ref LL_ADC_CHANNEL_16
1733 * @arg @ref LL_ADC_CHANNEL_17
1734 * @arg @ref LL_ADC_CHANNEL_18
1735 */
1736 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1737 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1738
1739 /**
1740 * @brief Helper macro to determine whether the internal channel
1741 * selected is available on the ADC instance selected.
1742 * @note The channel parameter must be a value defined from parameter
1743 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1744 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1745 * must not be a value defined from parameter definition of
1746 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1747 * or a value from functions where a channel number is
1748 * returned from ADC registers,
1749 * because internal and external channels share the same channel
1750 * number in ADC registers. The differentiation is made only with
1751 * parameters definitions of driver.
1752 * @param __ADC_INSTANCE__ ADC instance
1753 * @param __CHANNEL__ This parameter can be one of the following values:
1754 * @arg @ref LL_ADC_CHANNEL_VREFINT
1755 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
1756 * @arg @ref LL_ADC_CHANNEL_VBAT
1757 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
1758 * Value "1" if the internal channel selected is available on the ADC instance selected.
1759 */
1760 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1761 ( \
1762 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1763 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1764 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
1765 )
1766
1767 #if defined(ADC_SUPPORT_2_5_MSPS)
1768 /**
1769 * @brief Helper macro to define ADC analog watchdog parameter:
1770 * define a single channel to monitor with analog watchdog
1771 * from sequencer channel and groups definition.
1772 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
1773 * Example:
1774 * LL_ADC_SetAnalogWDMonitChannels(
1775 * ADC1, LL_ADC_AWD1,
1776 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
1777 * @param __CHANNEL__ This parameter can be one of the following values:
1778 * @arg @ref LL_ADC_CHANNEL_0
1779 * @arg @ref LL_ADC_CHANNEL_1 (7)
1780 * @arg @ref LL_ADC_CHANNEL_2 (7)
1781 * @arg @ref LL_ADC_CHANNEL_3 (7)
1782 * @arg @ref LL_ADC_CHANNEL_4 (7)
1783 * @arg @ref LL_ADC_CHANNEL_5 (7)
1784 * @arg @ref LL_ADC_CHANNEL_6
1785 * @arg @ref LL_ADC_CHANNEL_7
1786 * @arg @ref LL_ADC_CHANNEL_8
1787 * @arg @ref LL_ADC_CHANNEL_9
1788 * @arg @ref LL_ADC_CHANNEL_10
1789 * @arg @ref LL_ADC_CHANNEL_11
1790 * @arg @ref LL_ADC_CHANNEL_12
1791 * @arg @ref LL_ADC_CHANNEL_13
1792 * @arg @ref LL_ADC_CHANNEL_14
1793 * @arg @ref LL_ADC_CHANNEL_15
1794 * @arg @ref LL_ADC_CHANNEL_16
1795 * @arg @ref LL_ADC_CHANNEL_17
1796 * @arg @ref LL_ADC_CHANNEL_18
1797 * @arg @ref LL_ADC_CHANNEL_VREFINT (4)
1798 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
1799 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
1800 *
1801 * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
1802 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
1803 * (4) For ADC channel read back from ADC register,
1804 * comparison with internal channel parameter to be done
1805 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1806 * @param __GROUP__ This parameter can be one of the following values:
1807 * @arg @ref LL_ADC_GROUP_REGULAR
1808 * @retval Returned value can be one of the following values:
1809 * @arg @ref LL_ADC_AWD_DISABLE
1810 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
1811 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
1812 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
1813 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
1814 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
1815 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
1816 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
1817 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
1818 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
1819 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
1820 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
1821 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
1822 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
1823 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
1824 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
1825 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
1826 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
1827 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
1828 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
1829 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
1830 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)
1831 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)
1832 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)
1833 *
1834 * (0) On STM32WB, parameter available only on analog watchdog number: AWD1.
1835 */
1836 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
1837 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
1838 #else
1839 /**
1840 * @brief Helper macro to define ADC analog watchdog parameter:
1841 * define a single channel to monitor with analog watchdog
1842 * from sequencer channel and groups definition.
1843 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
1844 * Example:
1845 * LL_ADC_SetAnalogWDMonitChannels(
1846 * ADC1, LL_ADC_AWD1,
1847 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
1848 * @param __CHANNEL__ This parameter can be one of the following values:
1849 * @arg @ref LL_ADC_CHANNEL_0
1850 * @arg @ref LL_ADC_CHANNEL_1 (7)
1851 * @arg @ref LL_ADC_CHANNEL_2 (7)
1852 * @arg @ref LL_ADC_CHANNEL_3 (7)
1853 * @arg @ref LL_ADC_CHANNEL_4 (7)
1854 * @arg @ref LL_ADC_CHANNEL_5 (7)
1855 * @arg @ref LL_ADC_CHANNEL_6
1856 * @arg @ref LL_ADC_CHANNEL_7
1857 * @arg @ref LL_ADC_CHANNEL_8
1858 * @arg @ref LL_ADC_CHANNEL_9
1859 * @arg @ref LL_ADC_CHANNEL_10
1860 * @arg @ref LL_ADC_CHANNEL_11
1861 * @arg @ref LL_ADC_CHANNEL_12
1862 * @arg @ref LL_ADC_CHANNEL_13
1863 * @arg @ref LL_ADC_CHANNEL_14
1864 * @arg @ref LL_ADC_CHANNEL_15
1865 * @arg @ref LL_ADC_CHANNEL_16
1866 * @arg @ref LL_ADC_CHANNEL_17
1867 * @arg @ref LL_ADC_CHANNEL_18
1868 * @arg @ref LL_ADC_CHANNEL_VREFINT (4)
1869 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
1870 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
1871 *
1872 * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
1873 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
1874 * (4) For ADC channel read back from ADC register,
1875 * comparison with internal channel parameter to be done
1876 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1877 * @param __GROUP__ This parameter can be one of the following values:
1878 * @arg @ref LL_ADC_GROUP_REGULAR
1879 * @arg @ref LL_ADC_GROUP_INJECTED
1880 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
1881 * @retval Returned value can be one of the following values:
1882 * @arg @ref LL_ADC_AWD_DISABLE
1883 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
1884 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)(1)
1885 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ (1)
1886 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
1887 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)(1)
1888 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ (1)
1889 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
1890 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)(1)
1891 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ (1)
1892 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
1893 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)(1)
1894 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ (1)
1895 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
1896 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)(1)
1897 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ (1)
1898 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
1899 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)(1)
1900 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ (1)
1901 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
1902 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)(1)
1903 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ (1)
1904 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
1905 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)(1)
1906 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ (1)
1907 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
1908 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)(1)
1909 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ (1)
1910 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
1911 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)(1)
1912 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ (1)
1913 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
1914 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)(1)
1915 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ (1)
1916 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
1917 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)(1)
1918 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ (1)
1919 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
1920 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)(1)
1921 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ (1)
1922 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
1923 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)(1)
1924 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ (1)
1925 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
1926 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)(1)
1927 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ (1)
1928 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
1929 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)(1)
1930 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ (1)
1931 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
1932 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)(1)
1933 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ (1)
1934 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
1935 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)(1)
1936 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ (1)
1937 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
1938 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)(1)
1939 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ (1)
1940 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
1941 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)(1)
1942 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ (1)
1943 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)
1944 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
1945 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
1946 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)
1947 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
1948 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
1949 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)
1950 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
1951 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
1952 *
1953 * (0) On STM32WB, parameter available only on analog watchdog number: AWD1.
1954 * (1) On STM32WB series, parameter not available on devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx.
1955 */
1956 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
1957 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
1958 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
1959 : \
1960 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
1961 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \
1962 : \
1963 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
1964 )
1965 #endif /* ADC_SUPPORT_2_5_MSPS */
1966
1967 /**
1968 * @brief Helper macro to set the value of ADC analog watchdog threshold high
1969 * or low in function of ADC resolution, when ADC resolution is
1970 * different of 12 bits.
1971 * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
1972 * or @ref LL_ADC_SetAnalogWDThresholds().
1973 * Example, with a ADC resolution of 8 bits, to set the value of
1974 * analog watchdog threshold high (on 8 bits):
1975 * LL_ADC_SetAnalogWDThresholds
1976 * (< ADCx param >,
1977 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
1978 * );
1979 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1980 * @arg @ref LL_ADC_RESOLUTION_12B
1981 * @arg @ref LL_ADC_RESOLUTION_10B
1982 * @arg @ref LL_ADC_RESOLUTION_8B
1983 * @arg @ref LL_ADC_RESOLUTION_6B
1984 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
1985 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1986 */
1987 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
1988 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
1989
1990 /**
1991 * @brief Helper macro to get the value of ADC analog watchdog threshold high
1992 * or low in function of ADC resolution, when ADC resolution is
1993 * different of 12 bits.
1994 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1995 * Example, with a ADC resolution of 8 bits, to get the value of
1996 * analog watchdog threshold high (on 8 bits):
1997 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
1998 * (LL_ADC_RESOLUTION_8B,
1999 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
2000 * );
2001 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2002 * @arg @ref LL_ADC_RESOLUTION_12B
2003 * @arg @ref LL_ADC_RESOLUTION_10B
2004 * @arg @ref LL_ADC_RESOLUTION_8B
2005 * @arg @ref LL_ADC_RESOLUTION_6B
2006 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
2007 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2008 */
2009 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
2010 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
2011
2012 /**
2013 * @brief Helper macro to get the ADC analog watchdog threshold high
2014 * or low from raw value containing both thresholds concatenated.
2015 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
2016 * Example, to get analog watchdog threshold high from the register raw value:
2017 * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
2018 * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
2019 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
2020 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
2021 * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2022 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2023 */
2024 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
2025 (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & LL_ADC_AWD_THRESHOLD_LOW)
2026
2027 /**
2028 * @brief Helper macro to set the ADC calibration value with both single ended
2029 * and differential modes calibration factors concatenated.
2030 * @note To be used with function @ref LL_ADC_SetCalibrationFactor().
2031 * Example, to set calibration factors single ended to 0x55
2032 * and differential ended to 0x2A:
2033 * LL_ADC_SetCalibrationFactor(
2034 * ADC1,
2035 * __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
2036 * @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
2037 * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
2038 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2039 */
2040 #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \
2041 (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))
2042
2043 /**
2044 * @brief Helper macro to select the ADC common instance
2045 * to which is belonging the selected ADC instance.
2046 * @note ADC common register instance can be used for:
2047 * - Set parameters common to several ADC instances
2048 * - Multimode (for devices with several ADC instances)
2049 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2050 * @param __ADCx__ ADC instance
2051 * @retval ADC common register instance
2052 */
2053 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
2054 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2055 (ADC123_COMMON)
2056 #elif defined(ADC1) && defined(ADC2)
2057 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2058 (ADC12_COMMON)
2059 #else
2060 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2061 (ADC1_COMMON)
2062 #endif
2063
2064 /**
2065 * @brief Helper macro to check if all ADC instances sharing the same
2066 * ADC common instance are disabled.
2067 * @note This check is required by functions with setting conditioned to
2068 * ADC state:
2069 * All ADC instances of the ADC common group must be disabled.
2070 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2071 * @note On devices with only 1 ADC common instance, parameter of this macro
2072 * is useless and can be ignored (parameter kept for compatibility
2073 * with devices featuring several ADC common instances).
2074 * @param __ADCXY_COMMON__ ADC common instance
2075 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2076 * @retval Value "0" if all ADC instances sharing the same ADC common instance
2077 * are disabled.
2078 * Value "1" if at least one ADC instance sharing the same ADC common instance
2079 * is enabled.
2080 */
2081 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
2082 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2083 (LL_ADC_IsEnabled(ADC1) | \
2084 LL_ADC_IsEnabled(ADC2) | \
2085 LL_ADC_IsEnabled(ADC3) )
2086 #elif defined(ADC1) && defined(ADC2)
2087 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2088 (LL_ADC_IsEnabled(ADC1) | \
2089 LL_ADC_IsEnabled(ADC2) )
2090 #else
2091 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2092 (LL_ADC_IsEnabled(ADC1))
2093 #endif
2094
2095 /**
2096 * @brief Helper macro to define the ADC conversion data full-scale digital
2097 * value corresponding to the selected ADC resolution.
2098 * @note ADC conversion data full-scale corresponds to voltage range
2099 * determined by analog voltage references Vref+ and Vref-
2100 * (refer to reference manual).
2101 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2102 * @arg @ref LL_ADC_RESOLUTION_12B
2103 * @arg @ref LL_ADC_RESOLUTION_10B
2104 * @arg @ref LL_ADC_RESOLUTION_8B
2105 * @arg @ref LL_ADC_RESOLUTION_6B
2106 * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
2107 */
2108 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2109 (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
2110
2111 /**
2112 * @brief Helper macro to convert the ADC conversion data from
2113 * a resolution to another resolution.
2114 * @param __DATA__ ADC conversion data to be converted
2115 * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
2116 * This parameter can be one of the following values:
2117 * @arg @ref LL_ADC_RESOLUTION_12B
2118 * @arg @ref LL_ADC_RESOLUTION_10B
2119 * @arg @ref LL_ADC_RESOLUTION_8B
2120 * @arg @ref LL_ADC_RESOLUTION_6B
2121 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
2122 * This parameter can be one of the following values:
2123 * @arg @ref LL_ADC_RESOLUTION_12B
2124 * @arg @ref LL_ADC_RESOLUTION_10B
2125 * @arg @ref LL_ADC_RESOLUTION_8B
2126 * @arg @ref LL_ADC_RESOLUTION_6B
2127 * @retval ADC conversion data to the requested resolution
2128 */
2129 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
2130 __ADC_RESOLUTION_CURRENT__,\
2131 __ADC_RESOLUTION_TARGET__) \
2132 (((__DATA__) \
2133 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2134 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2135 )
2136
2137 /**
2138 * @brief Helper macro to calculate the voltage (unit: mVolt)
2139 * corresponding to a ADC conversion data (unit: digital value).
2140 * @note Analog reference voltage (Vref+) must be either known from
2141 * user board environment or can be calculated using ADC measurement
2142 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2143 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2144 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
2145 * (unit: digital value).
2146 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2147 * @arg @ref LL_ADC_RESOLUTION_12B
2148 * @arg @ref LL_ADC_RESOLUTION_10B
2149 * @arg @ref LL_ADC_RESOLUTION_8B
2150 * @arg @ref LL_ADC_RESOLUTION_6B
2151 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
2152 */
2153 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
2154 __ADC_DATA__,\
2155 __ADC_RESOLUTION__) \
2156 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
2157 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2158 )
2159
2160 /**
2161 * @brief Helper macro to calculate analog reference voltage (Vref+)
2162 * (unit: mVolt) from ADC conversion data of internal voltage
2163 * reference VrefInt.
2164 * @note Computation is using VrefInt calibration value
2165 * stored in system memory for each device during production.
2166 * @note This voltage depends on user board environment: voltage level
2167 * connected to pin Vref+.
2168 * On devices with small package, the pin Vref+ is not present
2169 * and internally bonded to pin Vdda.
2170 * @note On this STM32 series, calibration data of internal voltage reference
2171 * VrefInt corresponds to a resolution of 12 bits,
2172 * this is the recommended ADC resolution to convert voltage of
2173 * internal voltage reference VrefInt.
2174 * Otherwise, this macro performs the processing to scale
2175 * ADC conversion data to 12 bits.
2176 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
2177 * of internal voltage reference VrefInt (unit: digital value).
2178 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2179 * @arg @ref LL_ADC_RESOLUTION_12B
2180 * @arg @ref LL_ADC_RESOLUTION_10B
2181 * @arg @ref LL_ADC_RESOLUTION_8B
2182 * @arg @ref LL_ADC_RESOLUTION_6B
2183 * @retval Analog reference voltage (unit: mV)
2184 */
2185 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
2186 __ADC_RESOLUTION__) \
2187 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
2188 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
2189 (__ADC_RESOLUTION__), \
2190 LL_ADC_RESOLUTION_12B))
2191
2192 /**
2193 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2194 * from ADC conversion data of internal temperature sensor.
2195 * @note Computation is using temperature sensor calibration values
2196 * stored in system memory for each device during production.
2197 * @note Calculation formula:
2198 * Temperature = ((TS_ADC_DATA - TS_CAL1)
2199 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
2200 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
2201 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2202 * Avg_Slope = (TS_CAL2 - TS_CAL1)
2203 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
2204 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
2205 * TEMP_DEGC_CAL1 (calibrated in factory)
2206 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
2207 * TEMP_DEGC_CAL2 (calibrated in factory)
2208 * Caution: Calculation relevancy under reserve that calibration
2209 * parameters are correct (address and data).
2210 * To calculate temperature using temperature sensor
2211 * datasheet typical values (generic values less, therefore
2212 * less accurate than calibrated values),
2213 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
2214 * @note As calculation input, the analog reference voltage (Vref+) must be
2215 * defined as it impacts the ADC LSB equivalent voltage.
2216 * @note Analog reference voltage (Vref+) must be either known from
2217 * user board environment or can be calculated using ADC measurement
2218 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2219 * @note On this STM32 series, calibration data of temperature sensor
2220 * corresponds to a resolution of 12 bits,
2221 * this is the recommended ADC resolution to convert voltage of
2222 * temperature sensor.
2223 * Otherwise, this macro performs the processing to scale
2224 * ADC conversion data to 12 bits.
2225 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2226 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
2227 * temperature sensor (unit: digital value).
2228 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
2229 * sensor voltage has been measured.
2230 * This parameter can be one of the following values:
2231 * @arg @ref LL_ADC_RESOLUTION_12B
2232 * @arg @ref LL_ADC_RESOLUTION_10B
2233 * @arg @ref LL_ADC_RESOLUTION_8B
2234 * @arg @ref LL_ADC_RESOLUTION_6B
2235 * @retval Temperature (unit: degree Celsius)
2236 */
2237 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
2238 __TEMPSENSOR_ADC_DATA__,\
2239 __ADC_RESOLUTION__) \
2240 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
2241 (__ADC_RESOLUTION__), \
2242 LL_ADC_RESOLUTION_12B) \
2243 * (__VREFANALOG_VOLTAGE__)) \
2244 / TEMPSENSOR_CAL_VREFANALOG) \
2245 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
2246 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
2247 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
2248 ) + TEMPSENSOR_CAL1_TEMP \
2249 )
2250
2251 /**
2252 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2253 * from ADC conversion data of internal temperature sensor.
2254 * @note Computation is using temperature sensor typical values
2255 * (refer to device datasheet).
2256 * @note Calculation formula:
2257 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
2258 * / Avg_Slope + CALx_TEMP
2259 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2260 * (unit: digital value)
2261 * Avg_Slope = temperature sensor slope
2262 * (unit: uV/Degree Celsius)
2263 * TS_TYP_CALx_VOLT = temperature sensor digital value at
2264 * temperature CALx_TEMP (unit: mV)
2265 * Caution: Calculation relevancy under reserve the temperature sensor
2266 * of the current device has characteristics in line with
2267 * datasheet typical values.
2268 * If temperature sensor calibration values are available on
2269 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
2270 * temperature calculation will be more accurate using
2271 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
2272 * @note As calculation input, the analog reference voltage (Vref+) must be
2273 * defined as it impacts the ADC LSB equivalent voltage.
2274 * @note Analog reference voltage (Vref+) must be either known from
2275 * user board environment or can be calculated using ADC measurement
2276 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2277 * @note ADC measurement data must correspond to a resolution of 12 bits
2278 * (full scale digital value 4095). If not the case, the data must be
2279 * preliminarily rescaled to an equivalent resolution of 12 bits.
2280 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
2281 * On STM32WB, refer to device datasheet parameter "Avg_Slope".
2282 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
2283 * On STM32WB, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
2284 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
2285 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
2286 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
2287 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
2288 * This parameter can be one of the following values:
2289 * @arg @ref LL_ADC_RESOLUTION_12B
2290 * @arg @ref LL_ADC_RESOLUTION_10B
2291 * @arg @ref LL_ADC_RESOLUTION_8B
2292 * @arg @ref LL_ADC_RESOLUTION_6B
2293 * @retval Temperature (unit: degree Celsius)
2294 */
2295 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
2296 __TEMPSENSOR_TYP_CALX_V__,\
2297 __TEMPSENSOR_CALX_TEMP__,\
2298 __VREFANALOG_VOLTAGE__,\
2299 __TEMPSENSOR_ADC_DATA__,\
2300 __ADC_RESOLUTION__) \
2301 ((( ( \
2302 (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
2303 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
2304 * 1000UL) \
2305 - \
2306 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
2307 * 1000UL) \
2308 ) \
2309 ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
2310 ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
2311 )
2312
2313 /**
2314 * @}
2315 */
2316
2317 /**
2318 * @}
2319 */
2320
2321
2322 /* Exported functions --------------------------------------------------------*/
2323 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
2324 * @{
2325 */
2326
2327 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
2328 * @{
2329 */
2330 /* Note: LL ADC functions to set DMA transfer are located into sections of */
2331 /* configuration of ADC instance, groups and multimode (if available): */
2332 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
2333
2334 /**
2335 * @brief Function to help to configure DMA transfer from ADC: retrieve the
2336 * ADC register address from ADC instance and a list of ADC registers
2337 * intended to be used (most commonly) with DMA transfer.
2338 * @note These ADC registers are data registers:
2339 * when ADC conversion data is available in ADC data registers,
2340 * ADC generates a DMA transfer request.
2341 * @note This macro is intended to be used with LL DMA driver, refer to
2342 * function "LL_DMA_ConfigAddresses()".
2343 * Example:
2344 * LL_DMA_ConfigAddresses(DMA1,
2345 * LL_DMA_CHANNEL_1,
2346 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
2347 * (uint32_t)&< array or variable >,
2348 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
2349 * @note For devices with several ADC: in multimode, some devices
2350 * use a different data register outside of ADC instance scope
2351 * (common data register). This macro manages this register difference,
2352 * only ADC instance has to be set as parameter.
2353 * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr
2354 * @param ADCx ADC instance
2355 * @param Register This parameter can be one of the following values:
2356 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
2357 * @retval ADC register address
2358 */
LL_ADC_DMA_GetRegAddr(const ADC_TypeDef * ADCx,uint32_t Register)2359 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register)
2360 {
2361 /* Prevent unused argument(s) compilation warning */
2362 (void)(Register);
2363
2364 /* Retrieve address of register DR */
2365 return (uint32_t)&(ADCx->DR);
2366 }
2367
2368 /**
2369 * @}
2370 */
2371
2372 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
2373 * @{
2374 */
2375
2376 /**
2377 * @brief Set parameter common to several ADC: Clock source and prescaler.
2378 * @note ADC clock source and prescaler must be selected in function of system clock to not exceed ADC maximum frequency, depending on devices.
2379 * Example: STM32WB55xx ADC maximum frequency is 64MHz (corresponding to 4.27Msmp/s maximum)
2380 * Example: STM32WB50xx ADC maximum frequency is 32MHz (corresponding to 2.13Msmp/s maximum)
2381 * For ADC maximum frequency, refer to datasheet of the selected device.
2382 * @note On this STM32 series, if ADC group injected is used, some
2383 * clock ratio constraints between ADC clock and AHB clock
2384 * must be respected.
2385 * Refer to reference manual.
2386 * @note On this STM32 series, setting of this feature is conditioned to
2387 * ADC state:
2388 * All ADC instances of the ADC common group must be disabled.
2389 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2390 * ADC instance or by using helper macro helper macro
2391 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2392 * @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n
2393 * CCR PRESC LL_ADC_SetCommonClock
2394 * @param ADCxy_COMMON ADC common instance
2395 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2396 * @param CommonClock This parameter can be one of the following values:
2397 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (*)
2398 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 (*)
2399 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 (*)
2400 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
2401 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
2402 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
2403 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
2404 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
2405 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
2406 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
2407 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
2408 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
2409 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
2410 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
2411 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
2412 *
2413 * (*) Value available on all STM32 devices except: STM32W10xxx, STM32W15xxx.
2414 * @retval None
2415 */
LL_ADC_SetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t CommonClock)2416 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
2417 {
2418 #if defined(ADC_SUPPORT_2_5_MSPS)
2419 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_PRESC, CommonClock);
2420 #else
2421 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
2422 #endif /* ADC_SUPPORT_2_5_MSPS */
2423 }
2424
2425 /**
2426 * @brief Get parameter common to several ADC: Clock source and prescaler.
2427 * @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n
2428 * CCR PRESC LL_ADC_GetCommonClock
2429 * @param ADCxy_COMMON ADC common instance
2430 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2431 * @retval Returned value can be one of the following values:
2432 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (*)
2433 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 (*)
2434 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 (*)
2435 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
2436 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
2437 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
2438 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
2439 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
2440 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
2441 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
2442 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
2443 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
2444 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
2445 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
2446 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
2447 *
2448 * (*) Value available on all STM32 devices except: STM32W10xxx, STM32W15xxx.
2449 */
LL_ADC_GetCommonClock(const ADC_Common_TypeDef * ADCxy_COMMON)2450 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON)
2451 {
2452 #if defined(ADC_SUPPORT_2_5_MSPS)
2453 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC));
2454 #else
2455 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
2456 #endif /* ADC_SUPPORT_2_5_MSPS */
2457 }
2458
2459 /**
2460 * @brief Set parameter common to several ADC: measurement path to
2461 * internal channels (VrefInt, temperature sensor, ...).
2462 * Configure all paths (overwrite current configuration).
2463 * @note One or several values can be selected.
2464 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2465 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2466 * The values not selected are removed from configuration.
2467 * @note Stabilization time of measurement path to internal channel:
2468 * After enabling internal paths, before starting ADC conversion,
2469 * a delay is required for internal voltage reference and
2470 * temperature sensor stabilization time.
2471 * Refer to device datasheet.
2472 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
2473 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
2474 * @note ADC internal channel sampling time constraint:
2475 * For ADC conversion of internal channels,
2476 * a sampling time minimum value is required.
2477 * Refer to device datasheet.
2478 * @note On this STM32 series, setting of this feature is conditioned to
2479 * ADC state:
2480 * All ADC instances of the ADC common group must be disabled.
2481 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2482 * ADC instance or by using helper macro helper macro
2483 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2484 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
2485 * CCR TSEN LL_ADC_SetCommonPathInternalCh\n
2486 * CCR VBATEN LL_ADC_SetCommonPathInternalCh
2487 * @param ADCxy_COMMON ADC common instance
2488 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2489 * @param PathInternal This parameter can be a combination of the following values:
2490 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2491 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2492 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2493 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2494 * @retval None
2495 */
LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)2496 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2497 {
2498 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
2499 }
2500
2501 /**
2502 * @brief Set parameter common to several ADC: measurement path to
2503 * internal channels (VrefInt, temperature sensor, ...).
2504 * Add paths to the current configuration.
2505 * @note One or several values can be selected.
2506 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2507 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2508 * @note Stabilization time of measurement path to internal channel:
2509 * After enabling internal paths, before starting ADC conversion,
2510 * a delay is required for internal voltage reference and
2511 * temperature sensor stabilization time.
2512 * Refer to device datasheet.
2513 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
2514 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
2515 * @note ADC internal channel sampling time constraint:
2516 * For ADC conversion of internal channels,
2517 * a sampling time minimum value is required.
2518 * Refer to device datasheet.
2519 * @note On this STM32 series, setting of this feature is conditioned to
2520 * ADC state:
2521 * All ADC instances of the ADC common group must be disabled.
2522 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2523 * ADC instance or by using helper macro helper macro
2524 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2525 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n
2526 * CCR TSEN LL_ADC_SetCommonPathInternalChAdd\n
2527 * CCR VBATEN LL_ADC_SetCommonPathInternalChAdd
2528 * @param ADCxy_COMMON ADC common instance
2529 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2530 * @param PathInternal This parameter can be a combination of the following values:
2531 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2532 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2533 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2534 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2535 * @retval None
2536 */
LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)2537 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2538 {
2539 SET_BIT(ADCxy_COMMON->CCR, PathInternal);
2540 }
2541
2542 /**
2543 * @brief Set parameter common to several ADC: measurement path to
2544 * internal channels (VrefInt, temperature sensor, ...).
2545 * Remove paths to the current configuration.
2546 * @note One or several values can be selected.
2547 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2548 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2549 * @note On this STM32 series, setting of this feature is conditioned to
2550 * ADC state:
2551 * All ADC instances of the ADC common group must be disabled.
2552 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2553 * ADC instance or by using helper macro helper macro
2554 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2555 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n
2556 * CCR TSEN LL_ADC_SetCommonPathInternalChRem\n
2557 * CCR VBATEN LL_ADC_SetCommonPathInternalChRem
2558 * @param ADCxy_COMMON ADC common instance
2559 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2560 * @param PathInternal This parameter can be a combination of the following values:
2561 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2562 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2563 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2564 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2565 * @retval None
2566 */
LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)2567 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2568 {
2569 CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
2570 }
2571
2572 /**
2573 * @brief Get parameter common to several ADC: measurement path to internal
2574 * channels (VrefInt, temperature sensor, ...).
2575 * @note One or several values can be selected.
2576 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2577 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2578 * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
2579 * CCR TSEN LL_ADC_GetCommonPathInternalCh\n
2580 * CCR VBATEN LL_ADC_GetCommonPathInternalCh
2581 * @param ADCxy_COMMON ADC common instance
2582 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2583 * @retval Returned value can be a combination of the following values:
2584 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2585 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2586 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2587 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2588 */
LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef * ADCxy_COMMON)2589 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON)
2590 {
2591 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
2592 }
2593
2594 /**
2595 * @}
2596 */
2597
2598 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
2599 * @{
2600 */
2601
2602 #if defined(ADC_SUPPORT_2_5_MSPS)
2603 /**
2604 * @brief Set ADC instance clock source and prescaler.
2605 * @note On this STM32 series, setting of this feature is conditioned to
2606 * ADC state:
2607 * ADC must be disabled.
2608 * @rmtoll CFGR2 CKMODE LL_ADC_SetClock
2609 * @param ADCx ADC instance
2610 * @param ClockSource This parameter can be one of the following values:
2611 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
2612 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
2613 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2)
2614 * @arg @ref LL_ADC_CLOCK_ASYNC (1)
2615 *
2616 * (1) Asynchronous clock prescaler can be configured using
2617 * function @ref LL_ADC_SetCommonClock().\n
2618 * (2) Caution: This parameter has some clock ratio constraints:
2619 * This configuration must be enabled only if PCLK has a 50%
2620 * duty clock cycle (APB prescaler configured inside the RCC
2621 * must be bypassed and the system clock must by 50% duty
2622 * cycle).
2623 * Refer to reference manual.
2624 * @retval None
2625 */
LL_ADC_SetClock(ADC_TypeDef * ADCx,uint32_t ClockSource)2626 __STATIC_INLINE void LL_ADC_SetClock(ADC_TypeDef *ADCx, uint32_t ClockSource)
2627 {
2628 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource);
2629 }
2630
2631 /**
2632 * @brief Get ADC instance clock source and prescaler.
2633 * @rmtoll CFGR2 CKMODE LL_ADC_GetClock
2634 * @param ADCx ADC instance
2635 * @retval Returned value can be one of the following values:
2636 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
2637 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
2638 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2)
2639 * @arg @ref LL_ADC_CLOCK_ASYNC (1)
2640 *
2641 * (1) Asynchronous clock prescaler can be retrieved using
2642 * function @ref LL_ADC_GetCommonClock().\n
2643 * (2) Caution: This parameter has some clock ratio constraints:
2644 * This configuration must be enabled only if PCLK has a 50%
2645 * duty clock cycle (APB prescaler configured inside the RCC
2646 * must be bypassed and the system clock must by 50% duty
2647 * cycle).
2648 * Refer to reference manual.
2649 */
LL_ADC_GetClock(ADC_TypeDef * ADCx)2650 __STATIC_INLINE uint32_t LL_ADC_GetClock(ADC_TypeDef *ADCx)
2651 {
2652 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE));
2653 }
2654 #endif /* ADC_SUPPORT_2_5_MSPS */
2655
2656 #if defined(ADC_SUPPORT_2_5_MSPS)
2657 /**
2658 * @brief Set ADC calibration factor in the mode single-ended
2659 * or differential (for devices with differential mode available).
2660 * @note This function is intended to set calibration parameters
2661 * without having to perform a new calibration using
2662 * @ref LL_ADC_StartCalibration().
2663 * @note For devices with differential mode available:
2664 * Calibration of offset is specific to each of
2665 * single-ended and differential modes
2666 * (calibration factor must be specified for each of these
2667 * differential modes, if used afterwards and if the application
2668 * requires their calibration).
2669 * @note In case of setting calibration factors of both modes single ended
2670 * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
2671 * both calibration factors must be concatenated.
2672 * To perform this processing, use helper macro
2673 * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
2674 * @note On this STM32 series, setting of this feature is conditioned to
2675 * ADC state:
2676 * ADC must be enabled, without calibration on going, without conversion
2677 * on going on group regular.
2678 * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationFactor\n
2679 * CALFACT CALFACT_D LL_ADC_SetCalibrationFactor
2680 * @param ADCx ADC instance
2681 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
2682 * @retval None
2683 */
LL_ADC_SetCalibrationFactor(ADC_TypeDef * ADCx,uint32_t CalibrationFactor)2684 __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t CalibrationFactor)
2685 {
2686 MODIFY_REG(ADCx->CALFACT,
2687 ADC_CALFACT_CALFACT,
2688 CalibrationFactor);
2689 }
2690 #else
2691 /**
2692 * @brief Set ADC calibration factor in the mode single-ended
2693 * or differential (for devices with differential mode available).
2694 * @note This function is intended to set calibration parameters
2695 * without having to perform a new calibration using
2696 * @ref LL_ADC_StartCalibration().
2697 * @note For devices with differential mode available:
2698 * Calibration of offset is specific to each of
2699 * single-ended and differential modes
2700 * (calibration factor must be specified for each of these
2701 * differential modes, if used afterwards and if the application
2702 * requires their calibration).
2703 * @note In case of setting calibration factors of both modes single ended
2704 * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
2705 * both calibration factors must be concatenated.
2706 * To perform this processing, use helper macro
2707 * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
2708 * @note On this STM32 series, setting of this feature is conditioned to
2709 * ADC state:
2710 * ADC must be enabled, without calibration on going, without conversion
2711 * on going on group regular.
2712 * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationFactor\n
2713 * CALFACT CALFACT_D LL_ADC_SetCalibrationFactor
2714 * @param ADCx ADC instance
2715 * @param SingleDiff This parameter can be one of the following values:
2716 * @arg @ref LL_ADC_SINGLE_ENDED
2717 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED (1)
2718 * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED (1)
2719 *
2720 * (1) On STM32WB series, parameter not available on devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx.
2721 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
2722 * @retval None
2723 */
LL_ADC_SetCalibrationFactor(ADC_TypeDef * ADCx,uint32_t SingleDiff,uint32_t CalibrationFactor)2724 __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
2725 {
2726 MODIFY_REG(ADCx->CALFACT,
2727 SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
2728 CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
2729 }
2730 #endif /* ADC_SUPPORT_2_5_MSPS */
2731
2732 #if defined(ADC_SUPPORT_2_5_MSPS)
2733 /**
2734 * @brief Get ADC calibration factor in the mode single-ended
2735 * or differential (for devices with differential mode available).
2736 * @note Calibration factors are set by hardware after performing
2737 * a calibration run using function @ref LL_ADC_StartCalibration().
2738 * @note For devices with differential mode available:
2739 * Calibration of offset is specific to each of
2740 * single-ended and differential modes
2741 * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationFactor\n
2742 * CALFACT CALFACT_D LL_ADC_GetCalibrationFactor
2743 * @param ADCx ADC instance
2744 * @retval Value between Min_Data=0x00 and Max_Data=0x7F
2745 */
LL_ADC_GetCalibrationFactor(const ADC_TypeDef * ADCx)2746 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(const ADC_TypeDef *ADCx)
2747 {
2748 return (uint32_t)(READ_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT));
2749 }
2750 #else
2751 /**
2752 * @brief Get ADC calibration factor in the mode single-ended
2753 * or differential (for devices with differential mode available).
2754 * @note Calibration factors are set by hardware after performing
2755 * a calibration run using function @ref LL_ADC_StartCalibration().
2756 * @note For devices with differential mode available:
2757 * Calibration of offset is specific to each of
2758 * single-ended and differential modes
2759 * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationFactor\n
2760 * CALFACT CALFACT_D LL_ADC_GetCalibrationFactor
2761 * @param ADCx ADC instance
2762 * @param SingleDiff This parameter can be one of the following values:
2763 * @arg @ref LL_ADC_SINGLE_ENDED
2764 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
2765 * @retval Value between Min_Data=0x00 and Max_Data=0x7F
2766 */
LL_ADC_GetCalibrationFactor(const ADC_TypeDef * ADCx,uint32_t SingleDiff)2767 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(const ADC_TypeDef *ADCx, uint32_t SingleDiff)
2768 {
2769 /* Retrieve bits with position in register depending on parameter */
2770 /* "SingleDiff". */
2771 /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
2772 /* containing other bits reserved for other purpose. */
2773 return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
2774 }
2775 #endif /* ADC_SUPPORT_2_5_MSPS */
2776 /**
2777 * @brief Set ADC resolution.
2778 * Refer to reference manual for alignments formats
2779 * dependencies to ADC resolutions.
2780 * @note On this STM32 series, setting of this feature is conditioned to
2781 * ADC state:
2782 * ADC must be disabled or enabled without conversion on going
2783 * on either groups regular or injected.
2784 * @rmtoll CFGR RES LL_ADC_SetResolution
2785 * @param ADCx ADC instance
2786 * @param Resolution This parameter can be one of the following values:
2787 * @arg @ref LL_ADC_RESOLUTION_12B
2788 * @arg @ref LL_ADC_RESOLUTION_10B
2789 * @arg @ref LL_ADC_RESOLUTION_8B
2790 * @arg @ref LL_ADC_RESOLUTION_6B
2791 * @retval None
2792 */
LL_ADC_SetResolution(ADC_TypeDef * ADCx,uint32_t Resolution)2793 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
2794 {
2795 #if defined(ADC_SUPPORT_2_5_MSPS)
2796 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution);
2797 #else
2798 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
2799 #endif /* ADC_SUPPORT_2_5_MSPS */
2800 }
2801
2802 /**
2803 * @brief Get ADC resolution.
2804 * Refer to reference manual for alignments formats
2805 * dependencies to ADC resolutions.
2806 * @rmtoll CFGR RES LL_ADC_GetResolution
2807 * @param ADCx ADC instance
2808 * @retval Returned value can be one of the following values:
2809 * @arg @ref LL_ADC_RESOLUTION_12B
2810 * @arg @ref LL_ADC_RESOLUTION_10B
2811 * @arg @ref LL_ADC_RESOLUTION_8B
2812 * @arg @ref LL_ADC_RESOLUTION_6B
2813 */
LL_ADC_GetResolution(const ADC_TypeDef * ADCx)2814 __STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx)
2815 {
2816 #if defined(ADC_SUPPORT_2_5_MSPS)
2817 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES));
2818 #else
2819 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
2820 #endif /* ADC_SUPPORT_2_5_MSPS */
2821 }
2822
2823 /**
2824 * @brief Set ADC conversion data alignment.
2825 * @note Refer to reference manual for alignments formats
2826 * dependencies to ADC resolutions.
2827 * @note On this STM32 series, setting of this feature is conditioned to
2828 * ADC state:
2829 * ADC must be disabled or enabled without conversion on going
2830 * on either groups regular or injected.
2831 * @rmtoll CFGR ALIGN LL_ADC_SetDataAlignment
2832 * @param ADCx ADC instance
2833 * @param DataAlignment This parameter can be one of the following values:
2834 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2835 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2836 * @retval None
2837 */
LL_ADC_SetDataAlignment(ADC_TypeDef * ADCx,uint32_t DataAlignment)2838 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
2839 {
2840 #if defined(ADC_SUPPORT_2_5_MSPS)
2841 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_ALIGN, DataAlignment);
2842 #else
2843 MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
2844 #endif /* ADC_SUPPORT_2_5_MSPS */
2845 }
2846
2847 /**
2848 * @brief Get ADC conversion data alignment.
2849 * @note Refer to reference manual for alignments formats
2850 * dependencies to ADC resolutions.
2851 * @rmtoll CFGR ALIGN LL_ADC_GetDataAlignment
2852 * @param ADCx ADC instance
2853 * @retval Returned value can be one of the following values:
2854 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2855 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2856 */
LL_ADC_GetDataAlignment(const ADC_TypeDef * ADCx)2857 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(const ADC_TypeDef *ADCx)
2858 {
2859 #if defined(ADC_SUPPORT_2_5_MSPS)
2860 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN));
2861 #else
2862 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
2863 #endif /* ADC_SUPPORT_2_5_MSPS */
2864 }
2865
2866 /**
2867 * @brief Set ADC low power mode.
2868 * @note Description of ADC low power modes:
2869 * - ADC low power mode "auto wait": Dynamic low power mode,
2870 * ADC conversions occurrences are limited to the minimum necessary
2871 * in order to reduce power consumption.
2872 * New ADC conversion starts only when the previous
2873 * unitary conversion data (for ADC group regular)
2874 * or previous sequence conversions data (for ADC group injected)
2875 * has been retrieved by user software.
2876 * In the meantime, ADC remains idle: does not performs any
2877 * other conversion.
2878 * This mode allows to automatically adapt the ADC conversions
2879 * triggers to the speed of the software that reads the data.
2880 * Moreover, this avoids risk of overrun for low frequency
2881 * applications.
2882 * How to use this low power mode:
2883 * - It is not recommended to use with interruption or DMA
2884 * since these modes have to clear immediately the EOC flag
2885 * (by CPU to free the IRQ pending event or by DMA).
2886 * Auto wait will work but fort a very short time, discarding
2887 * its intended benefit (except specific case of high load of CPU
2888 * or DMA transfers which can justify usage of auto wait).
2889 * - Do use with polling: 1. Start conversion,
2890 * 2. Later on, when conversion data is needed: poll for end of
2891 * conversion to ensure that conversion is completed and
2892 * retrieve ADC conversion data. This will trig another
2893 * ADC conversion start.
2894 * - ADC low power mode "auto power-off" (feature available on
2895 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
2896 * the ADC automatically powers-off after a conversion and
2897 * automatically wakes up when a new conversion is triggered
2898 * (with startup time between trigger and start of sampling).
2899 * This feature can be combined with low power mode "auto wait".
2900 * @note With ADC low power mode "auto wait", the ADC conversion data read
2901 * is corresponding to previous ADC conversion start, independently
2902 * of delay during which ADC was idle.
2903 * Therefore, the ADC conversion data may be outdated: does not
2904 * correspond to the current voltage level on the selected
2905 * ADC channel.
2906 * @note On this STM32 series, setting of this feature is conditioned to
2907 * ADC state:
2908 * ADC must be disabled or enabled without conversion on going
2909 * on either groups regular or injected.
2910 * @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode
2911 * @param ADCx ADC instance
2912 * @param LowPowerMode This parameter can be one of the following values:
2913 * @arg @ref LL_ADC_LP_MODE_NONE
2914 * @arg @ref LL_ADC_LP_AUTOWAIT
2915 * @arg @ref LL_ADC_LP_AUTOPOWEROFF (1)
2916 * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (1)
2917 *
2918 * (1) On STM32WB series, parameter available only on devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx.
2919 * @retval None
2920 */
LL_ADC_SetLowPowerMode(ADC_TypeDef * ADCx,uint32_t LowPowerMode)2921 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
2922 {
2923 #if defined(ADC_SUPPORT_2_5_MSPS)
2924 MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF), LowPowerMode);
2925 #else
2926 MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
2927 #endif /* ADC_SUPPORT_2_5_MSPS */
2928 }
2929
2930 /**
2931 * @brief Get ADC low power mode:
2932 * @note Description of ADC low power modes:
2933 * - ADC low power mode "auto wait": Dynamic low power mode,
2934 * ADC conversions occurrences are limited to the minimum necessary
2935 * in order to reduce power consumption.
2936 * New ADC conversion starts only when the previous
2937 * unitary conversion data (for ADC group regular)
2938 * or previous sequence conversions data (for ADC group injected)
2939 * has been retrieved by user software.
2940 * In the meantime, ADC remains idle: does not performs any
2941 * other conversion.
2942 * This mode allows to automatically adapt the ADC conversions
2943 * triggers to the speed of the software that reads the data.
2944 * Moreover, this avoids risk of overrun for low frequency
2945 * applications.
2946 * How to use this low power mode:
2947 * - It is not recommended to use with interruption or DMA
2948 * since these modes have to clear immediately the EOC flag
2949 * (by CPU to free the IRQ pending event or by DMA).
2950 * Auto wait will work but fort a very short time, discarding
2951 * its intended benefit (except specific case of high load of CPU
2952 * or DMA transfers which can justify usage of auto wait).
2953 * - Do use with polling: 1. Start conversion,
2954 * 2. Later on, when conversion data is needed: poll for end of
2955 * conversion to ensure that conversion is completed and
2956 * retrieve ADC conversion data. This will trig another
2957 * ADC conversion start.
2958 * - ADC low power mode "auto power-off" (feature available on
2959 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
2960 * the ADC automatically powers-off after a conversion and
2961 * automatically wakes up when a new conversion is triggered
2962 * (with startup time between trigger and start of sampling).
2963 * This feature can be combined with low power mode "auto wait".
2964 * @note With ADC low power mode "auto wait", the ADC conversion data read
2965 * is corresponding to previous ADC conversion start, independently
2966 * of delay during which ADC was idle.
2967 * Therefore, the ADC conversion data may be outdated: does not
2968 * correspond to the current voltage level on the selected
2969 * ADC channel.
2970 * @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode
2971 * @param ADCx ADC instance
2972 * @retval Returned value can be one of the following values:
2973 * @arg @ref LL_ADC_LP_MODE_NONE
2974 * @arg @ref LL_ADC_LP_AUTOWAIT
2975 * @arg @ref LL_ADC_LP_AUTOPOWEROFF (1)
2976 * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (1)
2977 *
2978 * (1) On STM32WB series, parameter available only on devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx.
2979 */
LL_ADC_GetLowPowerMode(const ADC_TypeDef * ADCx)2980 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *ADCx)
2981 {
2982 #if defined(ADC_SUPPORT_2_5_MSPS)
2983 return (uint32_t)(READ_BIT(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF)));
2984 #else
2985 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
2986 #endif /* ADC_SUPPORT_2_5_MSPS */
2987 }
2988
2989 #if defined(ADC_SUPPORT_2_5_MSPS)
2990 /**
2991 * @brief Set ADC trigger frequency mode.
2992 * @note ADC trigger frequency mode must be set to low frequency when
2993 * a duration is exceeded before ADC conversion start trigger event
2994 * (between ADC enable and ADC conversion start trigger event
2995 * or between two ADC conversion start trigger event).
2996 * Duration value: Refer to device datasheet, parameter "tIdle".
2997 * @note When ADC trigger frequency mode is set to low frequency,
2998 * some rearm cycles are inserted before performing ADC conversion
2999 * start, inducing a delay of 2 ADC clock cycles.
3000 * @note Usage of ADC trigger frequency mode with ADC low power mode:
3001 * - Low power mode auto wait: Only the first ADC conversion
3002 * start trigger inserts the rearm delay.
3003 * @note On this STM32 series, setting of this feature is conditioned to
3004 * ADC state:
3005 * ADC must be disabled or enabled without conversion on going
3006 * on group regular.
3007 * @rmtoll CFGR2 LFTRIG LL_ADC_SetTriggerFrequencyMode
3008 * @param ADCx ADC instance
3009 * @param TriggerFrequencyMode This parameter can be one of the following values:
3010 * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH
3011 * @arg @ref LL_ADC_TRIGGER_FREQ_LOW
3012 * @retval None
3013 */
LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef * ADCx,uint32_t TriggerFrequencyMode)3014 __STATIC_INLINE void LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef *ADCx, uint32_t TriggerFrequencyMode)
3015 {
3016 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LFTRIG, TriggerFrequencyMode);
3017 }
3018
3019 /**
3020 * @brief Get ADC trigger frequency mode.
3021 * @rmtoll CFGR2 LFTRIG LL_ADC_GetTriggerFrequencyMode
3022 * @param ADCx ADC instance
3023 * @retval Returned value can be one of the following values:
3024 * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH
3025 * @arg @ref LL_ADC_TRIGGER_FREQ_LOW
3026 */
LL_ADC_GetTriggerFrequencyMode(ADC_TypeDef * ADCx)3027 __STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(ADC_TypeDef *ADCx)
3028 {
3029 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG));
3030 }
3031
3032 #endif /* ADC_SUPPORT_2_5_MSPS */
3033 #if defined(ADC_SUPPORT_2_5_MSPS)
3034 /**
3035 * @brief Set sampling time common to a group of channels.
3036 * @note Unit: ADC clock cycles.
3037 * @note On this STM32 series, sampling time scope is on ADC instance:
3038 * Sampling time common to all channels, independently
3039 * of channels mapped on ADC group regular or injected.
3040 * (on some other STM32 families, sampling time is channel wise)
3041 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
3042 * converted:
3043 * sampling time constraints must be respected (sampling time can be
3044 * adjusted in function of ADC clock frequency and sampling time
3045 * setting).
3046 * Refer to device datasheet for timings values (parameters TS_vrefint,
3047 * TS_temp, ...).
3048 * @note Conversion time is the addition of sampling time and processing time.
3049 * On this STM32 series, ADC processing time is:
3050 * - 12.5 ADC clock cycles at ADC resolution 12 bits
3051 * - 10.5 ADC clock cycles at ADC resolution 10 bits
3052 * - 8.5 ADC clock cycles at ADC resolution 8 bits
3053 * - 6.5 ADC clock cycles at ADC resolution 6 bits
3054 * @note In case of ADC conversion of internal channel (VrefInt,
3055 * temperature sensor, ...), a sampling time minimum value
3056 * is required.
3057 * Refer to device datasheet.
3058 * @note On this STM32 series, setting of this feature is conditioned to
3059 * ADC state:
3060 * ADC must be disabled or enabled without conversion on going
3061 * on either groups regular or injected.
3062 * @rmtoll SMPR SMP1 LL_ADC_SetSamplingTimeCommonChannels\n
3063 * @rmtoll SMPR SMP2 LL_ADC_SetSamplingTimeCommonChannels
3064 * @param ADCx ADC instance
3065 * @param SamplingTimeY This parameter can be one of the following values:
3066 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
3067 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
3068 * @param SamplingTime This parameter can be one of the following values:
3069 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
3070 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5
3071 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
3072 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
3073 * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
3074 * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5
3075 * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5
3076 * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5
3077 * @retval None
3078 */
LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef * ADCx,uint32_t SamplingTimeY,uint32_t SamplingTime)3079 __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY, uint32_t SamplingTime)
3080 {
3081 MODIFY_REG(ADCx->SMPR,
3082 ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK),
3083 SamplingTime << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK));
3084 }
3085
3086 /**
3087 * @brief Get sampling time common to a group of channels.
3088 * @note Unit: ADC clock cycles.
3089 * @note On this STM32 series, sampling time scope is on ADC instance:
3090 * Sampling time common to all channels, independently
3091 * of channels mapped on ADC group regular or injected.
3092 * (on some other STM32 families, sampling time is channel wise)
3093 * @note Conversion time is the addition of sampling time and processing time.
3094 * On this STM32 series, ADC processing time is:
3095 * - 12.5 ADC clock cycles at ADC resolution 12 bits
3096 * - 10.5 ADC clock cycles at ADC resolution 10 bits
3097 * - 8.5 ADC clock cycles at ADC resolution 8 bits
3098 * - 6.5 ADC clock cycles at ADC resolution 6 bits
3099 * @rmtoll SMPR SMP1 LL_ADC_GetSamplingTimeCommonChannels\n
3100 * @rmtoll SMPR SMP2 LL_ADC_GetSamplingTimeCommonChannels
3101 * @param ADCx ADC instance
3102 * @param SamplingTimeY This parameter can be one of the following values:
3103 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
3104 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
3105 * @retval Returned value can be one of the following values:
3106 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
3107 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5
3108 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
3109 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
3110 * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
3111 * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5
3112 * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5
3113 * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5
3114 */
LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef * ADCx,uint32_t SamplingTimeY)3115 __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY)
3116 {
3117 return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)))
3118 >> (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK));
3119 }
3120
3121 #endif /* ADC_SUPPORT_2_5_MSPS */
3122
3123 #if defined(ADC_SUPPORT_2_5_MSPS)
3124 /* Feature "ADC offset" not available on ADC peripheral of this STM32WB device */
3125 #else
3126 /**
3127 * @brief Set ADC selected offset number 1, 2, 3 or 4.
3128 * @note This function set the 2 items of offset configuration:
3129 * - ADC channel to which the offset programmed will be applied
3130 * (independently of channel mapped on ADC group regular
3131 * or group injected)
3132 * - Offset level (offset to be subtracted from the raw
3133 * converted data).
3134 * @note Caution: Offset format is dependent to ADC resolution:
3135 * offset has to be left-aligned on bit 11, the LSB (right bits)
3136 * are set to 0.
3137 * @note This function enables the offset, by default. It can be forced
3138 * to disable state using function LL_ADC_SetOffsetState().
3139 * @note If a channel is mapped on several offsets numbers, only the offset
3140 * with the lowest value is considered for the subtraction.
3141 * @note On this STM32 series, setting of this feature is conditioned to
3142 * ADC state:
3143 * ADC must be disabled or enabled without conversion on going
3144 * on either groups regular or injected.
3145 * @note On STM32WB (except devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx), some fast channels are available: fast analog inputs
3146 * coming from GPIO pads (ADC_IN1..5).
3147 * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n
3148 * OFR1 OFFSET1 LL_ADC_SetOffset\n
3149 * OFR1 OFFSET1_EN LL_ADC_SetOffset\n
3150 * OFR2 OFFSET2_CH LL_ADC_SetOffset\n
3151 * OFR2 OFFSET2 LL_ADC_SetOffset\n
3152 * OFR2 OFFSET2_EN LL_ADC_SetOffset\n
3153 * OFR3 OFFSET3_CH LL_ADC_SetOffset\n
3154 * OFR3 OFFSET3 LL_ADC_SetOffset\n
3155 * OFR3 OFFSET3_EN LL_ADC_SetOffset\n
3156 * OFR4 OFFSET4_CH LL_ADC_SetOffset\n
3157 * OFR4 OFFSET4 LL_ADC_SetOffset\n
3158 * OFR4 OFFSET4_EN LL_ADC_SetOffset
3159 * @param ADCx ADC instance
3160 * @param Offsety This parameter can be one of the following values:
3161 * @arg @ref LL_ADC_OFFSET_1
3162 * @arg @ref LL_ADC_OFFSET_2
3163 * @arg @ref LL_ADC_OFFSET_3
3164 * @arg @ref LL_ADC_OFFSET_4
3165 * @param Channel This parameter can be one of the following values:
3166 * @arg @ref LL_ADC_CHANNEL_0
3167 * @arg @ref LL_ADC_CHANNEL_1 (7)
3168 * @arg @ref LL_ADC_CHANNEL_2 (7)
3169 * @arg @ref LL_ADC_CHANNEL_3 (7)
3170 * @arg @ref LL_ADC_CHANNEL_4 (7)
3171 * @arg @ref LL_ADC_CHANNEL_5 (7)
3172 * @arg @ref LL_ADC_CHANNEL_6
3173 * @arg @ref LL_ADC_CHANNEL_7
3174 * @arg @ref LL_ADC_CHANNEL_8
3175 * @arg @ref LL_ADC_CHANNEL_9
3176 * @arg @ref LL_ADC_CHANNEL_10
3177 * @arg @ref LL_ADC_CHANNEL_11
3178 * @arg @ref LL_ADC_CHANNEL_12
3179 * @arg @ref LL_ADC_CHANNEL_13
3180 * @arg @ref LL_ADC_CHANNEL_14
3181 * @arg @ref LL_ADC_CHANNEL_15
3182 * @arg @ref LL_ADC_CHANNEL_16
3183 * @arg @ref LL_ADC_CHANNEL_17
3184 * @arg @ref LL_ADC_CHANNEL_18
3185 * @arg @ref LL_ADC_CHANNEL_VREFINT
3186 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3187 * @arg @ref LL_ADC_CHANNEL_VBAT
3188 *
3189 * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
3190 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
3191 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
3192 * @retval None
3193 */
LL_ADC_SetOffset(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t Channel,uint32_t OffsetLevel)3194 __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
3195 {
3196 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3197
3198 MODIFY_REG(*preg,
3199 ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
3200 ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
3201 }
3202
3203 /**
3204 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3205 * Channel to which the offset programmed will be applied
3206 * (independently of channel mapped on ADC group regular
3207 * or group injected)
3208 * @note Usage of the returned channel number:
3209 * - To reinject this channel into another function LL_ADC_xxx:
3210 * the returned channel number is only partly formatted on definition
3211 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3212 * with parts of literals LL_ADC_CHANNEL_x or using
3213 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3214 * Then the selected literal LL_ADC_CHANNEL_x can be used
3215 * as parameter for another function.
3216 * - To get the channel number in decimal format:
3217 * process the returned value with the helper macro
3218 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3219 * @note On STM32WB (except devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx), some fast channels are available: fast analog inputs
3220 * coming from GPIO pads (ADC_IN1..5).
3221 * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n
3222 * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n
3223 * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n
3224 * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel
3225 * @param ADCx ADC instance
3226 * @param Offsety This parameter can be one of the following values:
3227 * @arg @ref LL_ADC_OFFSET_1
3228 * @arg @ref LL_ADC_OFFSET_2
3229 * @arg @ref LL_ADC_OFFSET_3
3230 * @arg @ref LL_ADC_OFFSET_4
3231 * @retval Returned value can be one of the following values:
3232 * @arg @ref LL_ADC_CHANNEL_0
3233 * @arg @ref LL_ADC_CHANNEL_1 (7)
3234 * @arg @ref LL_ADC_CHANNEL_2 (7)
3235 * @arg @ref LL_ADC_CHANNEL_3 (7)
3236 * @arg @ref LL_ADC_CHANNEL_4 (7)
3237 * @arg @ref LL_ADC_CHANNEL_5 (7)
3238 * @arg @ref LL_ADC_CHANNEL_6
3239 * @arg @ref LL_ADC_CHANNEL_7
3240 * @arg @ref LL_ADC_CHANNEL_8
3241 * @arg @ref LL_ADC_CHANNEL_9
3242 * @arg @ref LL_ADC_CHANNEL_10
3243 * @arg @ref LL_ADC_CHANNEL_11
3244 * @arg @ref LL_ADC_CHANNEL_12
3245 * @arg @ref LL_ADC_CHANNEL_13
3246 * @arg @ref LL_ADC_CHANNEL_14
3247 * @arg @ref LL_ADC_CHANNEL_15
3248 * @arg @ref LL_ADC_CHANNEL_16
3249 * @arg @ref LL_ADC_CHANNEL_17
3250 * @arg @ref LL_ADC_CHANNEL_18
3251 * @arg @ref LL_ADC_CHANNEL_VREFINT (4)
3252 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
3253 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
3254 *
3255 * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
3256 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
3257 * (4) For ADC channel read back from ADC register,
3258 * comparison with internal channel parameter to be done
3259 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3260 */
LL_ADC_GetOffsetChannel(const ADC_TypeDef * ADCx,uint32_t Offsety)3261 __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety)
3262 {
3263 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3264
3265 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
3266 }
3267
3268 /**
3269 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3270 * Offset level (offset to be subtracted from the raw
3271 * converted data).
3272 * @note Caution: Offset format is dependent to ADC resolution:
3273 * offset has to be left-aligned on bit 11, the LSB (right bits)
3274 * are set to 0.
3275 * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n
3276 * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n
3277 * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n
3278 * OFR4 OFFSET4 LL_ADC_GetOffsetLevel
3279 * @param ADCx ADC instance
3280 * @param Offsety This parameter can be one of the following values:
3281 * @arg @ref LL_ADC_OFFSET_1
3282 * @arg @ref LL_ADC_OFFSET_2
3283 * @arg @ref LL_ADC_OFFSET_3
3284 * @arg @ref LL_ADC_OFFSET_4
3285 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3286 */
LL_ADC_GetOffsetLevel(const ADC_TypeDef * ADCx,uint32_t Offsety)3287 __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(const ADC_TypeDef *ADCx, uint32_t Offsety)
3288 {
3289 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3290
3291 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
3292 }
3293
3294 /**
3295 * @brief Set for the ADC selected offset number 1, 2, 3 or 4:
3296 * force offset state disable or enable
3297 * without modifying offset channel or offset value.
3298 * @note This function should be needed only in case of offset to be
3299 * enabled-disabled dynamically, and should not be needed in other cases:
3300 * function LL_ADC_SetOffset() automatically enables the offset.
3301 * @note On this STM32 series, setting of this feature is conditioned to
3302 * ADC state:
3303 * ADC must be disabled or enabled without conversion on going
3304 * on either groups regular or injected.
3305 * @rmtoll OFR1 OFFSET1_EN LL_ADC_SetOffsetState\n
3306 * OFR2 OFFSET2_EN LL_ADC_SetOffsetState\n
3307 * OFR3 OFFSET3_EN LL_ADC_SetOffsetState\n
3308 * OFR4 OFFSET4_EN LL_ADC_SetOffsetState
3309 * @param ADCx ADC instance
3310 * @param Offsety This parameter can be one of the following values:
3311 * @arg @ref LL_ADC_OFFSET_1
3312 * @arg @ref LL_ADC_OFFSET_2
3313 * @arg @ref LL_ADC_OFFSET_3
3314 * @arg @ref LL_ADC_OFFSET_4
3315 * @param OffsetState This parameter can be one of the following values:
3316 * @arg @ref LL_ADC_OFFSET_DISABLE
3317 * @arg @ref LL_ADC_OFFSET_ENABLE
3318 * @retval None
3319 */
LL_ADC_SetOffsetState(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t OffsetState)3320 __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
3321 {
3322 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3323
3324 MODIFY_REG(*preg,
3325 ADC_OFR1_OFFSET1_EN,
3326 OffsetState);
3327 }
3328
3329 /**
3330 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3331 * offset state disabled or enabled.
3332 * @rmtoll OFR1 OFFSET1_EN LL_ADC_GetOffsetState\n
3333 * OFR2 OFFSET2_EN LL_ADC_GetOffsetState\n
3334 * OFR3 OFFSET3_EN LL_ADC_GetOffsetState\n
3335 * OFR4 OFFSET4_EN LL_ADC_GetOffsetState
3336 * @param ADCx ADC instance
3337 * @param Offsety This parameter can be one of the following values:
3338 * @arg @ref LL_ADC_OFFSET_1
3339 * @arg @ref LL_ADC_OFFSET_2
3340 * @arg @ref LL_ADC_OFFSET_3
3341 * @arg @ref LL_ADC_OFFSET_4
3342 * @retval Returned value can be one of the following values:
3343 * @arg @ref LL_ADC_OFFSET_DISABLE
3344 * @arg @ref LL_ADC_OFFSET_ENABLE
3345 */
LL_ADC_GetOffsetState(const ADC_TypeDef * ADCx,uint32_t Offsety)3346 __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(const ADC_TypeDef *ADCx, uint32_t Offsety)
3347 {
3348 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3349
3350 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
3351 }
3352
3353 #endif /* ADC_SUPPORT_2_5_MSPS */
3354
3355 /**
3356 * @}
3357 */
3358
3359 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
3360 * @{
3361 */
3362
3363 /**
3364 * @brief Set ADC group regular conversion trigger source:
3365 * internal (SW start) or from external peripheral (timer event,
3366 * external interrupt line).
3367 * @note On this STM32 series, setting trigger source to external trigger
3368 * also set trigger polarity to rising edge
3369 * (default setting for compatibility with some ADC on other
3370 * STM32 families having this setting set by HW default value).
3371 * In case of need to modify trigger edge, use
3372 * function @ref LL_ADC_REG_SetTriggerEdge().
3373 * @note On devices STM32WB10xx, STM32WB15xx, STM32WB1Mxx: ADC trigger frequency mode must be set
3374 * in function of frequency of ADC group regular conversion trigger.
3375 * Refer to description of function
3376 * "LL_ADC_SetTriggerFrequencyMode()".
3377 * @note Availability of parameters of trigger sources from timer
3378 * depends on timers availability on the selected device.
3379 * @note On this STM32 series, setting of this feature is conditioned to
3380 * ADC state:
3381 * ADC must be disabled or enabled without conversion on going
3382 * on group regular.
3383 * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n
3384 * CFGR EXTEN LL_ADC_REG_SetTriggerSource
3385 * @param ADCx ADC instance
3386 * @param TriggerSource This parameter can be one of the following values:
3387 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
3388 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO (1)
3389 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
3390 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (1)
3391 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (1)
3392 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 (1)
3393 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4 (2)
3394 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
3395 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
3396 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (2)
3397 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4 (2)
3398 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
3399 *
3400 * (1) On STM32WB series, parameter not available on devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx.
3401 * (2) On STM32WB series, parameter available only devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx.
3402 * @retval None
3403 */
LL_ADC_REG_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)3404 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
3405 {
3406 #if defined(ADC_SUPPORT_2_5_MSPS)
3407 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource);
3408 #else
3409 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
3410 #endif /* ADC_SUPPORT_2_5_MSPS */
3411 }
3412
3413 /**
3414 * @brief Get ADC group regular conversion trigger source:
3415 * internal (SW start) or from external peripheral (timer event,
3416 * external interrupt line).
3417 * @note To determine whether group regular trigger source is
3418 * internal (SW start) or external, without detail
3419 * of which peripheral is selected as external trigger,
3420 * (equivalent to
3421 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
3422 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
3423 * @note Availability of parameters of trigger sources from timer
3424 * depends on timers availability on the selected device.
3425 * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n
3426 * CFGR EXTEN LL_ADC_REG_GetTriggerSource
3427 * @param ADCx ADC instance
3428 * @retval Returned value can be one of the following values:
3429 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
3430 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO (1)
3431 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
3432 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (1)
3433 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (1)
3434 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 (1)
3435 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4 (2)
3436 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
3437 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
3438 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (2)
3439 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4 (2)
3440 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
3441 *
3442 * (1) On STM32WB series, parameter not available on devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx.
3443 * (2) On STM32WB series, parameter available only devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx.
3444 */
LL_ADC_REG_GetTriggerSource(const ADC_TypeDef * ADCx)3445 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx)
3446 {
3447 #if defined(ADC_SUPPORT_2_5_MSPS)
3448 __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN);
3449
3450 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
3451 /* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}. */
3452 uint32_t ShiftExten = ((TriggerSource & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
3453
3454 /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL */
3455 /* to match with triggers literals definition. */
3456 return ((TriggerSource
3457 & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR1_EXTSEL)
3458 | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR1_EXTEN)
3459 );
3460 #else
3461 __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
3462
3463 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
3464 /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
3465 uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
3466
3467 /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
3468 /* to match with triggers literals definition. */
3469 return ((TriggerSource
3470 & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)
3471 | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)
3472 );
3473 #endif /* ADC_SUPPORT_2_5_MSPS */
3474 }
3475
3476 /**
3477 * @brief Get ADC group regular conversion trigger source internal (SW start)
3478 * or external.
3479 * @note In case of group regular trigger source set to external trigger,
3480 * to determine which peripheral is selected as external trigger,
3481 * use function @ref LL_ADC_REG_GetTriggerSource().
3482 * @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart
3483 * @param ADCx ADC instance
3484 * @retval Value "0" if trigger source external trigger
3485 * Value "1" if trigger source SW start.
3486 */
LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef * ADCx)3487 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
3488 {
3489 #if defined(ADC_SUPPORT_2_5_MSPS)
3490 return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ? 1UL : 0UL);
3491 #else
3492 return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
3493 #endif /* ADC_SUPPORT_2_5_MSPS */
3494 }
3495
3496 /**
3497 * @brief Set ADC group regular conversion trigger polarity.
3498 * @note Applicable only for trigger source set to external trigger.
3499 * @note On this STM32 series, setting of this feature is conditioned to
3500 * ADC state:
3501 * ADC must be disabled or enabled without conversion on going
3502 * on group regular.
3503 * @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge
3504 * @param ADCx ADC instance
3505 * @param ExternalTriggerEdge This parameter can be one of the following values:
3506 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3507 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3508 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3509 * @retval None
3510 */
LL_ADC_REG_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)3511 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
3512 {
3513 #if defined(ADC_SUPPORT_2_5_MSPS)
3514 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge);
3515 #else
3516 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
3517 #endif /* ADC_SUPPORT_2_5_MSPS */
3518 }
3519
3520 /**
3521 * @brief Get ADC group regular conversion trigger polarity.
3522 * @note Applicable only for trigger source set to external trigger.
3523 * @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge
3524 * @param ADCx ADC instance
3525 * @retval Returned value can be one of the following values:
3526 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3527 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3528 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3529 */
LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef * ADCx)3530 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx)
3531 {
3532 #if defined(ADC_SUPPORT_2_5_MSPS)
3533 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN));
3534 #else
3535 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
3536 #endif /* ADC_SUPPORT_2_5_MSPS */
3537 }
3538
3539 #if defined(ADC_SUPPORT_2_5_MSPS)
3540 /**
3541 * @brief Set ADC group regular sequencer configuration flexibility.
3542 * @note On this STM32 series, ADC group regular sequencer both modes
3543 * "fully configurable" or "not fully configurable" are
3544 * available:
3545 * - sequencer configured to fully configurable:
3546 * sequencer length and each rank
3547 * affectation to a channel are configurable.
3548 * Refer to description of function
3549 * @ref LL_ADC_REG_SetSequencerLength().
3550 * - sequencer configured to not fully configurable:
3551 * sequencer length and each rank affectation to a channel
3552 * are fixed by channel HW number.
3553 * Refer to description of function
3554 * @ref LL_ADC_REG_SetSequencerChannels().
3555 * @note On this STM32 series, setting of this feature is conditioned to
3556 * ADC state:
3557 * ADC must be disabled or enabled without conversion on going
3558 * on group regular.
3559 * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable
3560 * @param ADCx ADC instance
3561 * @param Configurability This parameter can be one of the following values:
3562 * @arg @ref LL_ADC_REG_SEQ_FIXED
3563 * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE
3564 * @retval None
3565 */
LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef * ADCx,uint32_t Configurability)3566 __STATIC_INLINE void LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef *ADCx, uint32_t Configurability)
3567 {
3568 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD, Configurability);
3569 }
3570
3571 /**
3572 * @brief Get ADC group regular sequencer configuration flexibility.
3573 * @note On this STM32 series, ADC group regular sequencer both modes
3574 * "fully configurable" or "not fully configurable" are
3575 * available:
3576 * - sequencer configured to fully configurable:
3577 * sequencer length and each rank
3578 * affectation to a channel are configurable.
3579 * Refer to description of function
3580 * @ref LL_ADC_REG_SetSequencerLength().
3581 * - sequencer configured to not fully configurable:
3582 * sequencer length and each rank affectation to a channel
3583 * are fixed by channel HW number.
3584 * Refer to description of function
3585 * @ref LL_ADC_REG_SetSequencerChannels().
3586 * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable
3587 * @param ADCx ADC instance
3588 * @retval Returned value can be one of the following values:
3589 * @arg @ref LL_ADC_REG_SEQ_FIXED
3590 * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE
3591 */
LL_ADC_REG_GetSequencerConfigurable(ADC_TypeDef * ADCx)3592 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerConfigurable(ADC_TypeDef *ADCx)
3593 {
3594 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD));
3595 }
3596
3597 #endif /* ADC_SUPPORT_2_5_MSPS */
3598 /**
3599 * @brief Set ADC group regular sequencer length and scan direction.
3600 * @note Description of ADC group regular sequencer features:
3601 * - For devices with sequencer fully configurable
3602 * (function "LL_ADC_REG_SetSequencerRanks()" available):
3603 * sequencer length and each rank affectation to a channel
3604 * are configurable.
3605 * This function performs configuration of:
3606 * - Sequence length: Number of ranks in the scan sequence.
3607 * - Sequence direction: Unless specified in parameters, sequencer
3608 * scan direction is forward (from rank 1 to rank n).
3609 * Sequencer ranks are selected using
3610 * function "LL_ADC_REG_SetSequencerRanks()".
3611 * - For devices with sequencer not fully configurable
3612 * (function "LL_ADC_REG_SetSequencerChannels()" available):
3613 * sequencer length and each rank affectation to a channel
3614 * are defined by channel number.
3615 * This function performs configuration of:
3616 * - Sequence length: Number of ranks in the scan sequence is
3617 * defined by number of channels set in the sequence,
3618 * rank of each channel is fixed by channel HW number.
3619 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3620 * - Sequence direction: Unless specified in parameters, sequencer
3621 * scan direction is forward (from lowest channel number to
3622 * highest channel number).
3623 * Sequencer ranks are selected using
3624 * function "LL_ADC_REG_SetSequencerChannels()".
3625 * To set scan direction differently, refer to function
3626 * "LL_ADC_REG_SetSequencerScanDirection()".
3627 * @note On devices STM32WB10xx, STM32WB15xx, STM32WB1Mxx: after calling functions
3628 * @ref LL_ADC_REG_SetSequencerLength()
3629 * or @ref LL_ADC_REG_SetSequencerRanks(),
3630 * it is mandatory to wait for the assertion of CCRDY flag
3631 * using "LL_ADC_IsActiveFlag_CCRDY()".
3632 * Otherwise, performing some actions (configuration update,
3633 * ADC conversion start, ... ) will be ignored.
3634 * Refer to reference manual for more details.
3635 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
3636 * ADC conversion on only 1 channel.
3637 * @note On this STM32 series, setting of this feature is conditioned to
3638 * ADC state:
3639 * ADC must be disabled or enabled without conversion on going
3640 * on group regular.
3641 * @rmtoll CHSELR SQ1 LL_ADC_REG_SetSequencerLength\n
3642 * CHSELR SQ2 LL_ADC_REG_SetSequencerLength\n
3643 * CHSELR SQ3 LL_ADC_REG_SetSequencerLength\n
3644 * CHSELR SQ4 LL_ADC_REG_SetSequencerLength\n
3645 * CHSELR SQ5 LL_ADC_REG_SetSequencerLength\n
3646 * CHSELR SQ6 LL_ADC_REG_SetSequencerLength\n
3647 * CHSELR SQ7 LL_ADC_REG_SetSequencerLength\n
3648 * CHSELR SQ8 LL_ADC_REG_SetSequencerLength
3649 * @param ADCx ADC instance
3650 * @param SequencerNbRanks This parameter can be one of the following values:
3651 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
3652 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
3653 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
3654 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
3655 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
3656 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
3657 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
3658 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
3659 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (1)
3660 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (1)
3661 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (1)
3662 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (1)
3663 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (1)
3664 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (1)
3665 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (1)
3666 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (1)
3667 *
3668 * (1) On STM32WB series, parameter not available on devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx.
3669 * @retval None
3670 */
LL_ADC_REG_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)3671 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
3672 {
3673 #if defined(ADC_SUPPORT_2_5_MSPS)
3674 SET_BIT(ADCx->CHSELR, SequencerNbRanks);
3675 #else
3676 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
3677 #endif /* ADC_SUPPORT_2_5_MSPS */
3678 }
3679
3680 /**
3681 * @brief Get ADC group regular sequencer length and scan direction.
3682 * @note Description of ADC group regular sequencer features:
3683 * - For devices with sequencer fully configurable
3684 * (function "LL_ADC_REG_SetSequencerRanks()" available):
3685 * sequencer length and each rank affectation to a channel
3686 * are configurable.
3687 * This function retrieves:
3688 * - Sequence length: Number of ranks in the scan sequence.
3689 * - Sequence direction: Unless specified in parameters, sequencer
3690 * scan direction is forward (from rank 1 to rank n).
3691 * Sequencer ranks are selected using
3692 * function "LL_ADC_REG_SetSequencerRanks()".
3693 * - For devices with sequencer not fully configurable
3694 * (function "LL_ADC_REG_SetSequencerChannels()" available):
3695 * sequencer length and each rank affectation to a channel
3696 * are defined by channel number.
3697 * This function retrieves:
3698 * - Sequence length: Number of ranks in the scan sequence is
3699 * defined by number of channels set in the sequence,
3700 * rank of each channel is fixed by channel HW number.
3701 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3702 * - Sequence direction: Unless specified in parameters, sequencer
3703 * scan direction is forward (from lowest channel number to
3704 * highest channel number).
3705 * Sequencer ranks are selected using
3706 * function "LL_ADC_REG_SetSequencerChannels()".
3707 * To set scan direction differently, refer to function
3708 * "LL_ADC_REG_SetSequencerScanDirection()".
3709 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
3710 * ADC conversion on only 1 channel.
3711 * @rmtoll CHSELR SQ1 LL_ADC_REG_GetSequencerLength\n
3712 * CHSELR SQ2 LL_ADC_REG_GetSequencerLength\n
3713 * CHSELR SQ3 LL_ADC_REG_GetSequencerLength\n
3714 * CHSELR SQ4 LL_ADC_REG_GetSequencerLength\n
3715 * CHSELR SQ5 LL_ADC_REG_GetSequencerLength\n
3716 * CHSELR SQ6 LL_ADC_REG_GetSequencerLength\n
3717 * CHSELR SQ7 LL_ADC_REG_GetSequencerLength\n
3718 * CHSELR SQ8 LL_ADC_REG_GetSequencerLength
3719 * @param ADCx ADC instance
3720 * @retval Returned value can be one of the following values:
3721 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
3722 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
3723 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
3724 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
3725 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
3726 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
3727 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
3728 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
3729 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (1)
3730 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (1)
3731 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (1)
3732 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (1)
3733 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (1)
3734 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (1)
3735 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (1)
3736 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (1)
3737 *
3738 * (1) On STM32WB series, parameter not available on devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx.
3739 */
LL_ADC_REG_GetSequencerLength(const ADC_TypeDef * ADCx)3740 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx)
3741 {
3742 #if defined(ADC_SUPPORT_2_5_MSPS)
3743 __IO uint32_t ChannelsRanks = READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ_ALL);
3744 uint32_t SequencerLength = LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS;
3745 uint32_t RankIndex;
3746
3747 /* Parse register for end of sequence identifier */
3748 for(RankIndex = 0UL; RankIndex < (32U - 4U); RankIndex+=4U)
3749 {
3750 if((ChannelsRanks & (ADC_CHSELR_SQ2 << RankIndex)) == (ADC_CHSELR_SQ2 << RankIndex))
3751 {
3752 SequencerLength = (ADC_CHSELR_SQ2 << RankIndex);
3753 break;
3754 }
3755 }
3756
3757 return SequencerLength;
3758 #else
3759 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
3760 #endif /* ADC_SUPPORT_2_5_MSPS */
3761 }
3762
3763 #if defined(ADC_SUPPORT_2_5_MSPS)
3764 /**
3765 * @brief Set ADC group regular sequencer scan direction.
3766 * @note On this STM32 series, parameter relevant only is sequencer is set
3767 * to mode not fully configurable,
3768 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
3769 * @note On some other STM32 families, this setting is not available and
3770 * the default scan direction is forward.
3771 * @note On this STM32 series, setting of this feature is conditioned to
3772 * ADC state:
3773 * ADC must be disabled or enabled without conversion on going
3774 * on group regular.
3775 * @rmtoll CFGR1 SCANDIR LL_ADC_REG_SetSequencerScanDirection
3776 * @param ADCx ADC instance
3777 * @param ScanDirection This parameter can be one of the following values:
3778 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
3779 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
3780 * @retval None
3781 */
LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef * ADCx,uint32_t ScanDirection)3782 __STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uint32_t ScanDirection)
3783 {
3784 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_SCANDIR, ScanDirection);
3785 }
3786
3787 /**
3788 * @brief Get ADC group regular sequencer scan direction.
3789 * @note On some other STM32 families, this setting is not available and
3790 * the default scan direction is forward.
3791 * @rmtoll CFGR1 SCANDIR LL_ADC_REG_GetSequencerScanDirection
3792 * @param ADCx ADC instance
3793 * @retval Returned value can be one of the following values:
3794 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
3795 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
3796 */
LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef * ADCx)3797 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef *ADCx)
3798 {
3799 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR));
3800 }
3801
3802 #endif /* ADC_SUPPORT_2_5_MSPS */
3803 /**
3804 * @brief Set ADC group regular sequencer discontinuous mode:
3805 * sequence subdivided and scan conversions interrupted every selected
3806 * number of ranks.
3807 * @note It is not possible to enable both ADC group regular
3808 * continuous mode and sequencer discontinuous mode.
3809 * @note It is not possible to enable both ADC auto-injected mode
3810 * and ADC group regular sequencer discontinuous mode.
3811 * @note On this STM32 series, setting of this feature is conditioned to
3812 * ADC state:
3813 * ADC must be disabled or enabled without conversion on going
3814 * on group regular.
3815 * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n
3816 * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont
3817 * @param ADCx ADC instance
3818 * @param SeqDiscont This parameter can be one of the following values:
3819 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
3820 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
3821 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS (1)
3822 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS (1)
3823 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS (1)
3824 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS (1)
3825 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS (1)
3826 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS (1)
3827 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS (1)
3828 *
3829 * (1) On STM32WB series, parameter not available on devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx.
3830 * @retval None
3831 */
LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)3832 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
3833 {
3834 #if defined(ADC_SUPPORT_2_5_MSPS)
3835 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN, SeqDiscont);
3836 #else
3837 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
3838 #endif /* ADC_SUPPORT_2_5_MSPS */
3839 }
3840
3841 /**
3842 * @brief Get ADC group regular sequencer discontinuous mode:
3843 * sequence subdivided and scan conversions interrupted every selected
3844 * number of ranks.
3845 * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n
3846 * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont
3847 * @param ADCx ADC instance
3848 * @retval Returned value can be one of the following values:
3849 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
3850 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
3851 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS (1)
3852 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS (1)
3853 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS (1)
3854 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS (1)
3855 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS (1)
3856 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS (1)
3857 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS (1)
3858 *
3859 * (1) On STM32WB series, parameter not available on devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx.
3860 */
LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef * ADCx)3861 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx)
3862 {
3863 #if defined(ADC_SUPPORT_2_5_MSPS)
3864 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN));
3865 #else
3866 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
3867 #endif /* ADC_SUPPORT_2_5_MSPS */
3868 }
3869
3870 /**
3871 * @brief Set ADC group regular sequence: channel on the selected
3872 * scan sequence rank.
3873 * @note This function performs configuration of:
3874 * - Channels ordering into each rank of scan sequence:
3875 * whatever channel can be placed into whatever rank.
3876 * @note On this STM32 series, ADC group regular sequencer is
3877 * fully configurable: sequencer length and each rank
3878 * affectation to a channel are configurable.
3879 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
3880 * @note Depending on devices and packages, some channels may not be available.
3881 * Refer to device datasheet for channels availability.
3882 * @note On this STM32 series, to measure internal channels (VrefInt,
3883 * TempSensor, ...), measurement paths to internal channels must be
3884 * enabled separately.
3885 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3886 * @note On devices STM32WB10xx, STM32WB15xx, STM32WB1Mxx: after calling functions
3887 * @ref LL_ADC_REG_SetSequencerLength()
3888 * or @ref LL_ADC_REG_SetSequencerRanks(),
3889 * it is mandatory to wait for the assertion of CCRDY flag
3890 * using "LL_ADC_IsActiveFlag_CCRDY()".
3891 * Otherwise, performing some actions (configuration update,
3892 * ADC conversion start, ... ) will be ignored.
3893 * Refer to reference manual for more details.
3894 * @note On this STM32 series, setting of this feature is conditioned to
3895 * ADC state:
3896 * ADC must be disabled or enabled without conversion on going
3897 * on group regular.
3898 * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n
3899 * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n
3900 * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n
3901 * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n
3902 * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n
3903 * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n
3904 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
3905 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
3906 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
3907 * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n
3908 * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n
3909 * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n
3910 * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n
3911 * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n
3912 * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n
3913 * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
3914 * @param ADCx ADC instance
3915 * @param Rank This parameter can be one of the following values:
3916 * @arg @ref LL_ADC_REG_RANK_1
3917 * @arg @ref LL_ADC_REG_RANK_2
3918 * @arg @ref LL_ADC_REG_RANK_3
3919 * @arg @ref LL_ADC_REG_RANK_4
3920 * @arg @ref LL_ADC_REG_RANK_5
3921 * @arg @ref LL_ADC_REG_RANK_6
3922 * @arg @ref LL_ADC_REG_RANK_7
3923 * @arg @ref LL_ADC_REG_RANK_8
3924 * @arg @ref LL_ADC_REG_RANK_9 (1)
3925 * @arg @ref LL_ADC_REG_RANK_10 (1)
3926 * @arg @ref LL_ADC_REG_RANK_11 (1)
3927 * @arg @ref LL_ADC_REG_RANK_12 (1)
3928 * @arg @ref LL_ADC_REG_RANK_13 (1)
3929 * @arg @ref LL_ADC_REG_RANK_14 (1)
3930 * @arg @ref LL_ADC_REG_RANK_15 (1)
3931 * @arg @ref LL_ADC_REG_RANK_16 (1)
3932 *
3933 * (1) On STM32WB series, parameter not available on devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx.
3934 * @param Channel This parameter can be one of the following values:
3935 * @arg @ref LL_ADC_CHANNEL_0
3936 * @arg @ref LL_ADC_CHANNEL_1 (7)
3937 * @arg @ref LL_ADC_CHANNEL_2 (7)
3938 * @arg @ref LL_ADC_CHANNEL_3 (7)
3939 * @arg @ref LL_ADC_CHANNEL_4 (7)
3940 * @arg @ref LL_ADC_CHANNEL_5 (7)
3941 * @arg @ref LL_ADC_CHANNEL_6
3942 * @arg @ref LL_ADC_CHANNEL_7
3943 * @arg @ref LL_ADC_CHANNEL_8
3944 * @arg @ref LL_ADC_CHANNEL_9
3945 * @arg @ref LL_ADC_CHANNEL_10
3946 * @arg @ref LL_ADC_CHANNEL_11
3947 * @arg @ref LL_ADC_CHANNEL_12
3948 * @arg @ref LL_ADC_CHANNEL_13
3949 * @arg @ref LL_ADC_CHANNEL_14
3950 * @arg @ref LL_ADC_CHANNEL_15
3951 * @arg @ref LL_ADC_CHANNEL_16
3952 * @arg @ref LL_ADC_CHANNEL_17
3953 * @arg @ref LL_ADC_CHANNEL_18
3954 * @arg @ref LL_ADC_CHANNEL_VREFINT
3955 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3956 * @arg @ref LL_ADC_CHANNEL_VBAT
3957 *
3958 * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
3959 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
3960 * @retval None
3961 */
LL_ADC_REG_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)3962 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
3963 {
3964 #if defined(ADC_SUPPORT_2_5_MSPS)
3965 /* Set bits with content of parameter "Channel" with bits position */
3966 /* in register depending on parameter "Rank". */
3967 /* Parameters "Rank" and "Channel" are used with masks because containing */
3968 /* other bits reserved for other purpose. */
3969 MODIFY_REG(ADCx->CHSELR,
3970 ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
3971 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK_SEQ) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
3972 #else
3973 /* Set bits with content of parameter "Channel" with bits position */
3974 /* in register and register position depending on parameter "Rank". */
3975 /* Parameters "Rank" and "Channel" are used with masks because containing */
3976 /* other bits reserved for other purpose. */
3977 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
3978
3979 MODIFY_REG(*preg,
3980 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
3981 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
3982 #endif /* ADC_SUPPORT_2_5_MSPS */
3983 }
3984
3985 /**
3986 * @brief Get ADC group regular sequence: channel on the selected
3987 * scan sequence rank.
3988 * @note On this STM32 series, ADC group regular sequencer is
3989 * fully configurable: sequencer length and each rank
3990 * affectation to a channel are configurable.
3991 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
3992 * @note Depending on devices and packages, some channels may not be available.
3993 * Refer to device datasheet for channels availability.
3994 * @note Usage of the returned channel number:
3995 * - To reinject this channel into another function LL_ADC_xxx:
3996 * the returned channel number is only partly formatted on definition
3997 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3998 * with parts of literals LL_ADC_CHANNEL_x or using
3999 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4000 * Then the selected literal LL_ADC_CHANNEL_x can be used
4001 * as parameter for another function.
4002 * - To get the channel number in decimal format:
4003 * process the returned value with the helper macro
4004 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4005 * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n
4006 * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n
4007 * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n
4008 * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n
4009 * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n
4010 * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n
4011 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
4012 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
4013 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
4014 * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n
4015 * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n
4016 * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n
4017 * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n
4018 * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n
4019 * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n
4020 * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
4021 * @param ADCx ADC instance
4022 * @param Rank This parameter can be one of the following values:
4023 * @arg @ref LL_ADC_REG_RANK_1
4024 * @arg @ref LL_ADC_REG_RANK_2
4025 * @arg @ref LL_ADC_REG_RANK_3
4026 * @arg @ref LL_ADC_REG_RANK_4
4027 * @arg @ref LL_ADC_REG_RANK_5
4028 * @arg @ref LL_ADC_REG_RANK_6
4029 * @arg @ref LL_ADC_REG_RANK_7
4030 * @arg @ref LL_ADC_REG_RANK_8
4031 * @arg @ref LL_ADC_REG_RANK_9 (1)
4032 * @arg @ref LL_ADC_REG_RANK_10 (1)
4033 * @arg @ref LL_ADC_REG_RANK_11 (1)
4034 * @arg @ref LL_ADC_REG_RANK_12 (1)
4035 * @arg @ref LL_ADC_REG_RANK_13 (1)
4036 * @arg @ref LL_ADC_REG_RANK_14 (1)
4037 * @arg @ref LL_ADC_REG_RANK_15 (1)
4038 * @arg @ref LL_ADC_REG_RANK_16 (1)
4039 *
4040 * (1) On STM32WB series, parameter not available on devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx.
4041 * @retval Returned value can be one of the following values:
4042 * @arg @ref LL_ADC_CHANNEL_0
4043 * @arg @ref LL_ADC_CHANNEL_1 (7)
4044 * @arg @ref LL_ADC_CHANNEL_2 (7)
4045 * @arg @ref LL_ADC_CHANNEL_3 (7)
4046 * @arg @ref LL_ADC_CHANNEL_4 (7)
4047 * @arg @ref LL_ADC_CHANNEL_5 (7)
4048 * @arg @ref LL_ADC_CHANNEL_6
4049 * @arg @ref LL_ADC_CHANNEL_7
4050 * @arg @ref LL_ADC_CHANNEL_8
4051 * @arg @ref LL_ADC_CHANNEL_9
4052 * @arg @ref LL_ADC_CHANNEL_10
4053 * @arg @ref LL_ADC_CHANNEL_11
4054 * @arg @ref LL_ADC_CHANNEL_12
4055 * @arg @ref LL_ADC_CHANNEL_13
4056 * @arg @ref LL_ADC_CHANNEL_14
4057 * @arg @ref LL_ADC_CHANNEL_15
4058 * @arg @ref LL_ADC_CHANNEL_16
4059 * @arg @ref LL_ADC_CHANNEL_17
4060 * @arg @ref LL_ADC_CHANNEL_18
4061 * @arg @ref LL_ADC_CHANNEL_VREFINT (4)
4062 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
4063 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
4064 *
4065 * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4066 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
4067 * (4) For ADC channel read back from ADC register,
4068 * comparison with internal channel parameter to be done
4069 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
4070 */
LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef * ADCx,uint32_t Rank)4071 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
4072 {
4073 #if defined(ADC_SUPPORT_2_5_MSPS)
4074 return (uint32_t) ((READ_BIT(ADCx->CHSELR,
4075 ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
4076 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
4077 ) << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
4078 );
4079 #else
4080 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
4081
4082 return (uint32_t)((READ_BIT(*preg,
4083 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
4084 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
4085 );
4086 #endif /* ADC_SUPPORT_2_5_MSPS */
4087 }
4088
4089 #if defined(ADC_SUPPORT_2_5_MSPS)
4090 /**
4091 * @brief Set ADC group regular sequence: channel on rank corresponding to
4092 * channel number.
4093 * @note This function performs:
4094 * - Channels ordering into each rank of scan sequence:
4095 * rank of each channel is fixed by channel HW number
4096 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
4097 * - Set channels selected by overwriting the current sequencer
4098 * configuration.
4099 * @note On this STM32 series, ADC group regular sequencer both modes
4100 * "fully configurable" or "not fully configurable"
4101 * are available, they can be chosen using
4102 * function @ref LL_ADC_REG_SetSequencerConfigurable().
4103 * This function can be used with setting "not fully configurable".
4104 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
4105 * and @ref LL_ADC_REG_SetSequencerLength().
4106 * @note Depending on devices and packages, some channels may not be available.
4107 * Refer to device datasheet for channels availability.
4108 * @note On this STM32 series, to measure internal channels (VrefInt,
4109 * TempSensor, ...), measurement paths to internal channels must be
4110 * enabled separately.
4111 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4112 * @note On STM32WB (except devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx), some fast channels are available: fast analog inputs
4113 * coming from GPIO pads (ADC_IN1..5).
4114 * @note On this STM32 series, setting of this feature is conditioned to
4115 * ADC state:
4116 * ADC must be disabled or enabled without conversion on going
4117 * on group regular.
4118 * @note One or several values can be selected.
4119 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
4120 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChannels\n
4121 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChannels\n
4122 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChannels\n
4123 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChannels\n
4124 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChannels\n
4125 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChannels\n
4126 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChannels\n
4127 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChannels\n
4128 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChannels\n
4129 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChannels\n
4130 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChannels\n
4131 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChannels\n
4132 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChannels\n
4133 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChannels\n
4134 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChannels\n
4135 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChannels\n
4136 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChannels\n
4137 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChannels\n
4138 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChannels
4139 * @param ADCx ADC instance
4140 * @param Channel This parameter can be a combination of the following values:
4141 * @arg @ref LL_ADC_CHANNEL_0
4142 * @arg @ref LL_ADC_CHANNEL_1 (7)
4143 * @arg @ref LL_ADC_CHANNEL_2 (7)
4144 * @arg @ref LL_ADC_CHANNEL_3 (7)
4145 * @arg @ref LL_ADC_CHANNEL_4 (7)
4146 * @arg @ref LL_ADC_CHANNEL_5 (7)
4147 * @arg @ref LL_ADC_CHANNEL_6
4148 * @arg @ref LL_ADC_CHANNEL_7
4149 * @arg @ref LL_ADC_CHANNEL_8
4150 * @arg @ref LL_ADC_CHANNEL_9
4151 * @arg @ref LL_ADC_CHANNEL_10
4152 * @arg @ref LL_ADC_CHANNEL_11
4153 * @arg @ref LL_ADC_CHANNEL_12
4154 * @arg @ref LL_ADC_CHANNEL_13
4155 * @arg @ref LL_ADC_CHANNEL_14
4156 * @arg @ref LL_ADC_CHANNEL_15
4157 * @arg @ref LL_ADC_CHANNEL_16
4158 * @arg @ref LL_ADC_CHANNEL_17
4159 * @arg @ref LL_ADC_CHANNEL_18
4160 * @arg @ref LL_ADC_CHANNEL_VREFINT
4161 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
4162 * @arg @ref LL_ADC_CHANNEL_VBAT
4163 *
4164 * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4165 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4166 * @retval None
4167 */
LL_ADC_REG_SetSequencerChannels(ADC_TypeDef * ADCx,uint32_t Channel)4168 __STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel)
4169 {
4170 /* Parameter "Channel" is used with masks because containing */
4171 /* other bits reserved for other purpose. */
4172 WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
4173 }
4174
4175 /**
4176 * @brief Add channel to ADC group regular sequence: channel on rank corresponding to
4177 * channel number.
4178 * @note This function performs:
4179 * - Channels ordering into each rank of scan sequence:
4180 * rank of each channel is fixed by channel HW number
4181 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
4182 * - Set channels selected by adding them to the current sequencer
4183 * configuration.
4184 * @note On this STM32 series, ADC group regular sequencer both modes
4185 * "fully configurable" or "not fully configurable"
4186 * are available, they can be chosen using
4187 * function @ref LL_ADC_REG_SetSequencerConfigurable().
4188 * This function can be used with setting "not fully configurable".
4189 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
4190 * and @ref LL_ADC_REG_SetSequencerLength().
4191 * @note Depending on devices and packages, some channels may not be available.
4192 * Refer to device datasheet for channels availability.
4193 * @note On this STM32 series, to measure internal channels (VrefInt,
4194 * TempSensor, ...), measurement paths to internal channels must be
4195 * enabled separately.
4196 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4197 * @note On STM32WB (except devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx), some fast channels are available: fast analog inputs
4198 * coming from GPIO pads (ADC_IN1..5).
4199 * @note On this STM32 series, setting of this feature is conditioned to
4200 * ADC state:
4201 * ADC must be disabled or enabled without conversion on going
4202 * on group regular.
4203 * @note One or several values can be selected.
4204 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
4205 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChAdd\n
4206 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChAdd\n
4207 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChAdd\n
4208 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChAdd\n
4209 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChAdd\n
4210 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChAdd\n
4211 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChAdd\n
4212 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChAdd\n
4213 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChAdd\n
4214 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChAdd\n
4215 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChAdd\n
4216 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChAdd\n
4217 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChAdd\n
4218 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChAdd\n
4219 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChAdd\n
4220 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChAdd\n
4221 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChAdd\n
4222 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChAdd\n
4223 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChAdd
4224 * @param ADCx ADC instance
4225 * @param Channel This parameter can be a combination of the following values:
4226 * @arg @ref LL_ADC_CHANNEL_0
4227 * @arg @ref LL_ADC_CHANNEL_1 (7)
4228 * @arg @ref LL_ADC_CHANNEL_2 (7)
4229 * @arg @ref LL_ADC_CHANNEL_3 (7)
4230 * @arg @ref LL_ADC_CHANNEL_4 (7)
4231 * @arg @ref LL_ADC_CHANNEL_5 (7)
4232 * @arg @ref LL_ADC_CHANNEL_6
4233 * @arg @ref LL_ADC_CHANNEL_7
4234 * @arg @ref LL_ADC_CHANNEL_8
4235 * @arg @ref LL_ADC_CHANNEL_9
4236 * @arg @ref LL_ADC_CHANNEL_10
4237 * @arg @ref LL_ADC_CHANNEL_11
4238 * @arg @ref LL_ADC_CHANNEL_12
4239 * @arg @ref LL_ADC_CHANNEL_13
4240 * @arg @ref LL_ADC_CHANNEL_14
4241 * @arg @ref LL_ADC_CHANNEL_15
4242 * @arg @ref LL_ADC_CHANNEL_16
4243 * @arg @ref LL_ADC_CHANNEL_17
4244 * @arg @ref LL_ADC_CHANNEL_18
4245 * @arg @ref LL_ADC_CHANNEL_VREFINT
4246 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
4247 * @arg @ref LL_ADC_CHANNEL_VBAT
4248 *
4249 * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4250 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4251 * @retval None
4252 */
LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef * ADCx,uint32_t Channel)4253 __STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel)
4254 {
4255 /* Parameter "Channel" is used with masks because containing */
4256 /* other bits reserved for other purpose. */
4257 SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
4258 }
4259
4260 /**
4261 * @brief Remove channel to ADC group regular sequence: channel on rank corresponding to
4262 * channel number.
4263 * @note This function performs:
4264 * - Channels ordering into each rank of scan sequence:
4265 * rank of each channel is fixed by channel HW number
4266 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
4267 * - Set channels selected by removing them to the current sequencer
4268 * configuration.
4269 * @note On this STM32 series, ADC group regular sequencer both modes
4270 * "fully configurable" or "not fully configurable"
4271 * are available, they can be chosen using
4272 * function @ref LL_ADC_REG_SetSequencerConfigurable().
4273 * This function can be used with setting "not fully configurable".
4274 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
4275 * and @ref LL_ADC_REG_SetSequencerLength().
4276 * @note Depending on devices and packages, some channels may not be available.
4277 * Refer to device datasheet for channels availability.
4278 * @note On this STM32 series, to measure internal channels (VrefInt,
4279 * TempSensor, ...), measurement paths to internal channels must be
4280 * enabled separately.
4281 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4282 * @note On STM32WB (except devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx), some fast channels are available: fast analog inputs
4283 * coming from GPIO pads (ADC_IN1..5).
4284 * @note On this STM32 series, setting of this feature is conditioned to
4285 * ADC state:
4286 * ADC must be disabled or enabled without conversion on going
4287 * on group regular.
4288 * @note One or several values can be selected.
4289 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
4290 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChRem\n
4291 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChRem\n
4292 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChRem\n
4293 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChRem\n
4294 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChRem\n
4295 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChRem\n
4296 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChRem\n
4297 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChRem\n
4298 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChRem\n
4299 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChRem\n
4300 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChRem\n
4301 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChRem\n
4302 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChRem\n
4303 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChRem\n
4304 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChRem\n
4305 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChRem\n
4306 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChRem\n
4307 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChRem\n
4308 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChRem
4309 * @param ADCx ADC instance
4310 * @param Channel This parameter can be a combination of the following values:
4311 * @arg @ref LL_ADC_CHANNEL_0
4312 * @arg @ref LL_ADC_CHANNEL_1 (7)
4313 * @arg @ref LL_ADC_CHANNEL_2 (7)
4314 * @arg @ref LL_ADC_CHANNEL_3 (7)
4315 * @arg @ref LL_ADC_CHANNEL_4 (7)
4316 * @arg @ref LL_ADC_CHANNEL_5 (7)
4317 * @arg @ref LL_ADC_CHANNEL_6
4318 * @arg @ref LL_ADC_CHANNEL_7
4319 * @arg @ref LL_ADC_CHANNEL_8
4320 * @arg @ref LL_ADC_CHANNEL_9
4321 * @arg @ref LL_ADC_CHANNEL_10
4322 * @arg @ref LL_ADC_CHANNEL_11
4323 * @arg @ref LL_ADC_CHANNEL_12
4324 * @arg @ref LL_ADC_CHANNEL_13
4325 * @arg @ref LL_ADC_CHANNEL_14
4326 * @arg @ref LL_ADC_CHANNEL_15
4327 * @arg @ref LL_ADC_CHANNEL_16
4328 * @arg @ref LL_ADC_CHANNEL_17
4329 * @arg @ref LL_ADC_CHANNEL_18
4330 * @arg @ref LL_ADC_CHANNEL_VREFINT
4331 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
4332 * @arg @ref LL_ADC_CHANNEL_VBAT
4333 *
4334 * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4335 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4336 * @retval None
4337 */
LL_ADC_REG_SetSequencerChRem(ADC_TypeDef * ADCx,uint32_t Channel)4338 __STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel)
4339 {
4340 /* Parameter "Channel" is used with masks because containing */
4341 /* other bits reserved for other purpose. */
4342 CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
4343 }
4344
4345 /**
4346 * @brief Get ADC group regular sequence: channel on rank corresponding to
4347 * channel number.
4348 * @note This function performs:
4349 * - Channels order reading into each rank of scan sequence:
4350 * rank of each channel is fixed by channel HW number
4351 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
4352 * @note On this STM32 series, ADC group regular sequencer both modes
4353 * "fully configurable" or "not fully configurable"
4354 * are available, they can be chosen using
4355 * function @ref LL_ADC_REG_SetSequencerConfigurable().
4356 * This function can be used with setting "not fully configurable".
4357 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
4358 * and @ref LL_ADC_REG_SetSequencerLength().
4359 * @note Depending on devices and packages, some channels may not be available.
4360 * Refer to device datasheet for channels availability.
4361 * @note On this STM32 series, to measure internal channels (VrefInt,
4362 * TempSensor, ...), measurement paths to internal channels must be
4363 * enabled separately.
4364 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4365 * @note On STM32WB (except devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx), some fast channels are available: fast analog inputs
4366 * coming from GPIO pads (ADC_IN1..5).
4367 * @note On this STM32 series, setting of this feature is conditioned to
4368 * ADC state:
4369 * ADC must be disabled or enabled without conversion on going
4370 * on group regular.
4371 * @note One or several values can be retrieved.
4372 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
4373 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_GetSequencerChannels\n
4374 * CHSELR CHSEL1 LL_ADC_REG_GetSequencerChannels\n
4375 * CHSELR CHSEL2 LL_ADC_REG_GetSequencerChannels\n
4376 * CHSELR CHSEL3 LL_ADC_REG_GetSequencerChannels\n
4377 * CHSELR CHSEL4 LL_ADC_REG_GetSequencerChannels\n
4378 * CHSELR CHSEL5 LL_ADC_REG_GetSequencerChannels\n
4379 * CHSELR CHSEL6 LL_ADC_REG_GetSequencerChannels\n
4380 * CHSELR CHSEL7 LL_ADC_REG_GetSequencerChannels\n
4381 * CHSELR CHSEL8 LL_ADC_REG_GetSequencerChannels\n
4382 * CHSELR CHSEL9 LL_ADC_REG_GetSequencerChannels\n
4383 * CHSELR CHSEL10 LL_ADC_REG_GetSequencerChannels\n
4384 * CHSELR CHSEL11 LL_ADC_REG_GetSequencerChannels\n
4385 * CHSELR CHSEL12 LL_ADC_REG_GetSequencerChannels\n
4386 * CHSELR CHSEL13 LL_ADC_REG_GetSequencerChannels\n
4387 * CHSELR CHSEL14 LL_ADC_REG_GetSequencerChannels\n
4388 * CHSELR CHSEL15 LL_ADC_REG_GetSequencerChannels\n
4389 * CHSELR CHSEL16 LL_ADC_REG_GetSequencerChannels\n
4390 * CHSELR CHSEL17 LL_ADC_REG_GetSequencerChannels\n
4391 * CHSELR CHSEL18 LL_ADC_REG_GetSequencerChannels
4392 * @param ADCx ADC instance
4393 * @retval Returned value can be a combination of the following values:
4394 * @arg @ref LL_ADC_CHANNEL_0
4395 * @arg @ref LL_ADC_CHANNEL_1 (7)
4396 * @arg @ref LL_ADC_CHANNEL_2 (7)
4397 * @arg @ref LL_ADC_CHANNEL_3 (7)
4398 * @arg @ref LL_ADC_CHANNEL_4 (7)
4399 * @arg @ref LL_ADC_CHANNEL_5 (7)
4400 * @arg @ref LL_ADC_CHANNEL_6
4401 * @arg @ref LL_ADC_CHANNEL_7
4402 * @arg @ref LL_ADC_CHANNEL_8
4403 * @arg @ref LL_ADC_CHANNEL_9
4404 * @arg @ref LL_ADC_CHANNEL_10
4405 * @arg @ref LL_ADC_CHANNEL_11
4406 * @arg @ref LL_ADC_CHANNEL_12
4407 * @arg @ref LL_ADC_CHANNEL_13
4408 * @arg @ref LL_ADC_CHANNEL_14
4409 * @arg @ref LL_ADC_CHANNEL_15
4410 * @arg @ref LL_ADC_CHANNEL_16
4411 * @arg @ref LL_ADC_CHANNEL_17
4412 * @arg @ref LL_ADC_CHANNEL_18
4413 * @arg @ref LL_ADC_CHANNEL_VREFINT
4414 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
4415 * @arg @ref LL_ADC_CHANNEL_VBAT
4416 *
4417 * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4418 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4419 */
LL_ADC_REG_GetSequencerChannels(ADC_TypeDef * ADCx)4420 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx)
4421 {
4422 uint32_t ChannelsBitfield = READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL);
4423
4424 return ( (((ChannelsBitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0)
4425 | (((ChannelsBitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1)
4426 | (((ChannelsBitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2)
4427 | (((ChannelsBitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3)
4428 | (((ChannelsBitfield & ADC_CHSELR_CHSEL4) >> ADC_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4)
4429 | (((ChannelsBitfield & ADC_CHSELR_CHSEL5) >> ADC_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5)
4430 | (((ChannelsBitfield & ADC_CHSELR_CHSEL6) >> ADC_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6)
4431 | (((ChannelsBitfield & ADC_CHSELR_CHSEL7) >> ADC_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7)
4432 | (((ChannelsBitfield & ADC_CHSELR_CHSEL8) >> ADC_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_CHANNEL_8)
4433 | (((ChannelsBitfield & ADC_CHSELR_CHSEL9) >> ADC_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_CHANNEL_9)
4434 | (((ChannelsBitfield & ADC_CHSELR_CHSEL10) >> ADC_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10)
4435 | (((ChannelsBitfield & ADC_CHSELR_CHSEL11) >> ADC_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11)
4436 | (((ChannelsBitfield & ADC_CHSELR_CHSEL12) >> ADC_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12)
4437 | (((ChannelsBitfield & ADC_CHSELR_CHSEL13) >> ADC_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13)
4438 | (((ChannelsBitfield & ADC_CHSELR_CHSEL14) >> ADC_CHSELR_CHSEL14_BITOFFSET_POS) * LL_ADC_CHANNEL_14)
4439 | (((ChannelsBitfield & ADC_CHSELR_CHSEL15) >> ADC_CHSELR_CHSEL15_BITOFFSET_POS) * LL_ADC_CHANNEL_15)
4440 | (((ChannelsBitfield & ADC_CHSELR_CHSEL16) >> ADC_CHSELR_CHSEL16_BITOFFSET_POS) * LL_ADC_CHANNEL_16)
4441 | (((ChannelsBitfield & ADC_CHSELR_CHSEL17) >> ADC_CHSELR_CHSEL17_BITOFFSET_POS) * LL_ADC_CHANNEL_17)
4442 | (((ChannelsBitfield & ADC_CHSELR_CHSEL18) >> ADC_CHSELR_CHSEL18_BITOFFSET_POS) * LL_ADC_CHANNEL_18)
4443 );
4444 }
4445 #endif /* ADC_SUPPORT_2_5_MSPS */
4446 /**
4447 * @brief Set ADC continuous conversion mode on ADC group regular.
4448 * @note Description of ADC continuous conversion mode:
4449 * - single mode: one conversion per trigger
4450 * - continuous mode: after the first trigger, following
4451 * conversions launched successively automatically.
4452 * @note It is not possible to enable both ADC group regular
4453 * continuous mode and sequencer discontinuous mode.
4454 * @note On this STM32 series, setting of this feature is conditioned to
4455 * ADC state:
4456 * ADC must be disabled or enabled without conversion on going
4457 * on group regular.
4458 * @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode
4459 * @param ADCx ADC instance
4460 * @param Continuous This parameter can be one of the following values:
4461 * @arg @ref LL_ADC_REG_CONV_SINGLE
4462 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
4463 * @retval None
4464 */
LL_ADC_REG_SetContinuousMode(ADC_TypeDef * ADCx,uint32_t Continuous)4465 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
4466 {
4467 #if defined(ADC_SUPPORT_2_5_MSPS)
4468 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous);
4469 #else
4470 MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
4471 #endif /* ADC_SUPPORT_2_5_MSPS */
4472 }
4473
4474 /**
4475 * @brief Get ADC continuous conversion mode on ADC group regular.
4476 * @note Description of ADC continuous conversion mode:
4477 * - single mode: one conversion per trigger
4478 * - continuous mode: after the first trigger, following
4479 * conversions launched successively automatically.
4480 * @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode
4481 * @param ADCx ADC instance
4482 * @retval Returned value can be one of the following values:
4483 * @arg @ref LL_ADC_REG_CONV_SINGLE
4484 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
4485 */
LL_ADC_REG_GetContinuousMode(const ADC_TypeDef * ADCx)4486 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx)
4487 {
4488 #if defined(ADC_SUPPORT_2_5_MSPS)
4489 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT));
4490 #else
4491 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
4492 #endif /* ADC_SUPPORT_2_5_MSPS */
4493 }
4494
4495 /**
4496 * @brief Set ADC group regular conversion data transfer: no transfer or
4497 * transfer by DMA, and DMA requests mode.
4498 * @note If transfer by DMA selected, specifies the DMA requests
4499 * mode:
4500 * - Limited mode (One shot mode): DMA transfer requests are stopped
4501 * when number of DMA data transfers (number of
4502 * ADC conversions) is reached.
4503 * This ADC mode is intended to be used with DMA mode non-circular.
4504 * - Unlimited mode: DMA transfer requests are unlimited,
4505 * whatever number of DMA data transfers (number of
4506 * ADC conversions).
4507 * This ADC mode is intended to be used with DMA mode circular.
4508 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
4509 * mode non-circular:
4510 * when DMA transfers size will be reached, DMA will stop transfers of
4511 * ADC conversions data ADC will raise an overrun error
4512 * (overrun flag and interruption if enabled).
4513 * @note To configure DMA source address (peripheral address),
4514 * use function @ref LL_ADC_DMA_GetRegAddr().
4515 * @note On this STM32 series, setting of this feature is conditioned to
4516 * ADC state:
4517 * ADC must be disabled or enabled without conversion on going
4518 * on either groups regular or injected.
4519 * @rmtoll CFGR DMAEN LL_ADC_REG_SetDMATransfer\n
4520 * CFGR DMACFG LL_ADC_REG_SetDMATransfer
4521 * @param ADCx ADC instance
4522 * @param DMATransfer This parameter can be one of the following values:
4523 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
4524 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
4525 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
4526 * @retval None
4527 */
LL_ADC_REG_SetDMATransfer(ADC_TypeDef * ADCx,uint32_t DMATransfer)4528 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
4529 {
4530 #if defined(ADC_SUPPORT_2_5_MSPS)
4531 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG, DMATransfer);
4532 #else
4533 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);
4534 #endif /* ADC_SUPPORT_2_5_MSPS */
4535 }
4536
4537 /**
4538 * @brief Get ADC group regular conversion data transfer: no transfer or
4539 * transfer by DMA, and DMA requests mode.
4540 * @note If transfer by DMA selected, specifies the DMA requests
4541 * mode:
4542 * - Limited mode (One shot mode): DMA transfer requests are stopped
4543 * when number of DMA data transfers (number of
4544 * ADC conversions) is reached.
4545 * This ADC mode is intended to be used with DMA mode non-circular.
4546 * - Unlimited mode: DMA transfer requests are unlimited,
4547 * whatever number of DMA data transfers (number of
4548 * ADC conversions).
4549 * This ADC mode is intended to be used with DMA mode circular.
4550 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
4551 * mode non-circular:
4552 * when DMA transfers size will be reached, DMA will stop transfers of
4553 * ADC conversions data ADC will raise an overrun error
4554 * (overrun flag and interruption if enabled).
4555 * @note To configure DMA source address (peripheral address),
4556 * use function @ref LL_ADC_DMA_GetRegAddr().
4557 * @rmtoll CFGR DMAEN LL_ADC_REG_GetDMATransfer\n
4558 * CFGR DMACFG LL_ADC_REG_GetDMATransfer
4559 * @param ADCx ADC instance
4560 * @retval Returned value can be one of the following values:
4561 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
4562 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
4563 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
4564 */
LL_ADC_REG_GetDMATransfer(const ADC_TypeDef * ADCx)4565 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(const ADC_TypeDef *ADCx)
4566 {
4567 #if defined(ADC_SUPPORT_2_5_MSPS)
4568 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG));
4569 #else
4570 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));
4571 #endif /* ADC_SUPPORT_2_5_MSPS */
4572 }
4573
4574
4575 /**
4576 * @brief Set ADC group regular behavior in case of overrun:
4577 * data preserved or overwritten.
4578 * @note Compatibility with devices without feature overrun:
4579 * other devices without this feature have a behavior
4580 * equivalent to data overwritten.
4581 * The default setting of overrun is data preserved.
4582 * Therefore, for compatibility with all devices, parameter
4583 * overrun should be set to data overwritten.
4584 * @note On this STM32 series, setting of this feature is conditioned to
4585 * ADC state:
4586 * ADC must be disabled or enabled without conversion on going
4587 * on group regular.
4588 * @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun
4589 * @param ADCx ADC instance
4590 * @param Overrun This parameter can be one of the following values:
4591 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
4592 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
4593 * @retval None
4594 */
LL_ADC_REG_SetOverrun(ADC_TypeDef * ADCx,uint32_t Overrun)4595 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
4596 {
4597 #if defined(ADC_SUPPORT_2_5_MSPS)
4598 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun);
4599 #else
4600 MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
4601 #endif /* ADC_SUPPORT_2_5_MSPS */
4602 }
4603
4604 /**
4605 * @brief Get ADC group regular behavior in case of overrun:
4606 * data preserved or overwritten.
4607 * @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun
4608 * @param ADCx ADC instance
4609 * @retval Returned value can be one of the following values:
4610 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
4611 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
4612 */
LL_ADC_REG_GetOverrun(const ADC_TypeDef * ADCx)4613 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx)
4614 {
4615 #if defined(ADC_SUPPORT_2_5_MSPS)
4616 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD));
4617 #else
4618 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
4619 #endif /* ADC_SUPPORT_2_5_MSPS */
4620 }
4621
4622 /**
4623 * @}
4624 */
4625
4626 #if defined(ADC_SUPPORT_2_5_MSPS)
4627 /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
4628 #else
4629 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
4630 * @{
4631 */
4632
4633 /**
4634 * @brief Set ADC group injected conversion trigger source:
4635 * internal (SW start) or from external peripheral (timer event,
4636 * external interrupt line).
4637 * @note On this STM32 series, setting trigger source to external trigger
4638 * also set trigger polarity to rising edge
4639 * (default setting for compatibility with some ADC on other
4640 * STM32 families having this setting set by HW default value).
4641 * In case of need to modify trigger edge, use
4642 * function @ref LL_ADC_INJ_SetTriggerEdge().
4643 * @note Availability of parameters of trigger sources from timer
4644 * depends on timers availability on the selected device.
4645 * @note On this STM32 series, setting of this feature is conditioned to
4646 * ADC state:
4647 * ADC must not be disabled. Can be enabled with or without conversion
4648 * on going on either groups regular or injected.
4649 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n
4650 * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource
4651 * @param ADCx ADC instance
4652 * @param TriggerSource This parameter can be one of the following values:
4653 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
4654 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
4655 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
4656 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
4657 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
4658 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
4659 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
4660 * @retval None
4661 */
LL_ADC_INJ_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)4662 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
4663 {
4664 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
4665 }
4666
4667 /**
4668 * @brief Get ADC group injected conversion trigger source:
4669 * internal (SW start) or from external peripheral (timer event,
4670 * external interrupt line).
4671 * @note To determine whether group injected trigger source is
4672 * internal (SW start) or external, without detail
4673 * of which peripheral is selected as external trigger,
4674 * (equivalent to
4675 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
4676 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
4677 * @note Availability of parameters of trigger sources from timer
4678 * depends on timers availability on the selected device.
4679 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n
4680 * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource
4681 * @param ADCx ADC instance
4682 * @retval Returned value can be one of the following values:
4683 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
4684 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
4685 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
4686 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
4687 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
4688 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
4689 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
4690 */
LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef * ADCx)4691 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef *ADCx)
4692 {
4693 __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
4694
4695 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
4696 /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
4697 uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
4698
4699 /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
4700 /* to match with triggers literals definition. */
4701 return ((TriggerSource
4702 & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)
4703 | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)
4704 );
4705 }
4706
4707 /**
4708 * @brief Get ADC group injected conversion trigger source internal (SW start)
4709 or external
4710 * @note In case of group injected trigger source set to external trigger,
4711 * to determine which peripheral is selected as external trigger,
4712 * use function @ref LL_ADC_INJ_GetTriggerSource.
4713 * @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
4714 * @param ADCx ADC instance
4715 * @retval Value "0" if trigger source external trigger
4716 * Value "1" if trigger source SW start.
4717 */
LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef * ADCx)4718 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
4719 {
4720 return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
4721 }
4722
4723 /**
4724 * @brief Set ADC group injected conversion trigger polarity.
4725 * Applicable only for trigger source set to external trigger.
4726 * @note On this STM32 series, setting of this feature is conditioned to
4727 * ADC state:
4728 * ADC must not be disabled. Can be enabled with or without conversion
4729 * on going on either groups regular or injected.
4730 * @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge
4731 * @param ADCx ADC instance
4732 * @param ExternalTriggerEdge This parameter can be one of the following values:
4733 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4734 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4735 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4736 * @retval None
4737 */
LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)4738 __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
4739 {
4740 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
4741 }
4742
4743 /**
4744 * @brief Get ADC group injected conversion trigger polarity.
4745 * Applicable only for trigger source set to external trigger.
4746 * @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge
4747 * @param ADCx ADC instance
4748 * @retval Returned value can be one of the following values:
4749 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4750 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4751 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4752 */
LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef * ADCx)4753 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef *ADCx)
4754 {
4755 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
4756 }
4757
4758 /**
4759 * @brief Set ADC group injected sequencer length and scan direction.
4760 * @note This function performs configuration of:
4761 * - Sequence length: Number of ranks in the scan sequence.
4762 * - Sequence direction: Unless specified in parameters, sequencer
4763 * scan direction is forward (from rank 1 to rank n).
4764 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4765 * ADC conversion on only 1 channel.
4766 * @note On this STM32 series, setting of this feature is conditioned to
4767 * ADC state:
4768 * ADC must not be disabled. Can be enabled with or without conversion
4769 * on going on either groups regular or injected.
4770 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
4771 * @param ADCx ADC instance
4772 * @param SequencerNbRanks This parameter can be one of the following values:
4773 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4774 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4775 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4776 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4777 * @retval None
4778 */
LL_ADC_INJ_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)4779 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
4780 {
4781 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
4782 }
4783
4784 /**
4785 * @brief Get ADC group injected sequencer length and scan direction.
4786 * @note This function retrieves:
4787 * - Sequence length: Number of ranks in the scan sequence.
4788 * - Sequence direction: Unless specified in parameters, sequencer
4789 * scan direction is forward (from rank 1 to rank n).
4790 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4791 * ADC conversion on only 1 channel.
4792 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
4793 * @param ADCx ADC instance
4794 * @retval Returned value can be one of the following values:
4795 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4796 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4797 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4798 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4799 */
LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef * ADCx)4800 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef *ADCx)
4801 {
4802 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
4803 }
4804
4805 /**
4806 * @brief Set ADC group injected sequencer discontinuous mode:
4807 * sequence subdivided and scan conversions interrupted every selected
4808 * number of ranks.
4809 * @note It is not possible to enable both ADC group injected
4810 * auto-injected mode and sequencer discontinuous mode.
4811 * @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont
4812 * @param ADCx ADC instance
4813 * @param SeqDiscont This parameter can be one of the following values:
4814 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
4815 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
4816 * @retval None
4817 */
LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)4818 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
4819 {
4820 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
4821 }
4822
4823 /**
4824 * @brief Get ADC group injected sequencer discontinuous mode:
4825 * sequence subdivided and scan conversions interrupted every selected
4826 * number of ranks.
4827 * @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont
4828 * @param ADCx ADC instance
4829 * @retval Returned value can be one of the following values:
4830 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
4831 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
4832 */
LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef * ADCx)4833 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef *ADCx)
4834 {
4835 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
4836 }
4837
4838 /**
4839 * @brief Set ADC group injected sequence: channel on the selected
4840 * sequence rank.
4841 * @note Depending on devices and packages, some channels may not be available.
4842 * Refer to device datasheet for channels availability.
4843 * @note On this STM32 series, to measure internal channels (VrefInt,
4844 * TempSensor, ...), measurement paths to internal channels must be
4845 * enabled separately.
4846 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4847 * @note On STM32WB (except devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx), some fast channels are available: fast analog inputs
4848 * coming from GPIO pads (ADC_IN1..5).
4849 * @note On this STM32 series, setting of this feature is conditioned to
4850 * ADC state:
4851 * ADC must not be disabled. Can be enabled with or without conversion
4852 * on going on either groups regular or injected.
4853 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
4854 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
4855 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
4856 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
4857 * @param ADCx ADC instance
4858 * @param Rank This parameter can be one of the following values:
4859 * @arg @ref LL_ADC_INJ_RANK_1
4860 * @arg @ref LL_ADC_INJ_RANK_2
4861 * @arg @ref LL_ADC_INJ_RANK_3
4862 * @arg @ref LL_ADC_INJ_RANK_4
4863 * @param Channel This parameter can be one of the following values:
4864 * @arg @ref LL_ADC_CHANNEL_0
4865 * @arg @ref LL_ADC_CHANNEL_1 (7)
4866 * @arg @ref LL_ADC_CHANNEL_2 (7)
4867 * @arg @ref LL_ADC_CHANNEL_3 (7)
4868 * @arg @ref LL_ADC_CHANNEL_4 (7)
4869 * @arg @ref LL_ADC_CHANNEL_5 (7)
4870 * @arg @ref LL_ADC_CHANNEL_6
4871 * @arg @ref LL_ADC_CHANNEL_7
4872 * @arg @ref LL_ADC_CHANNEL_8
4873 * @arg @ref LL_ADC_CHANNEL_9
4874 * @arg @ref LL_ADC_CHANNEL_10
4875 * @arg @ref LL_ADC_CHANNEL_11
4876 * @arg @ref LL_ADC_CHANNEL_12
4877 * @arg @ref LL_ADC_CHANNEL_13
4878 * @arg @ref LL_ADC_CHANNEL_14
4879 * @arg @ref LL_ADC_CHANNEL_15
4880 * @arg @ref LL_ADC_CHANNEL_16
4881 * @arg @ref LL_ADC_CHANNEL_17
4882 * @arg @ref LL_ADC_CHANNEL_18
4883 * @arg @ref LL_ADC_CHANNEL_VREFINT
4884 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
4885 * @arg @ref LL_ADC_CHANNEL_VBAT
4886 *
4887 * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4888 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4889 * @retval None
4890 */
LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)4891 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
4892 {
4893 /* Set bits with content of parameter "Channel" with bits position */
4894 /* in register depending on parameter "Rank". */
4895 /* Parameters "Rank" and "Channel" are used with masks because containing */
4896 /* other bits reserved for other purpose. */
4897 MODIFY_REG(ADCx->JSQR,
4898 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
4899 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
4900 }
4901
4902 /**
4903 * @brief Get ADC group injected sequence: channel on the selected
4904 * sequence rank.
4905 * @note Depending on devices and packages, some channels may not be available.
4906 * Refer to device datasheet for channels availability.
4907 * @note Usage of the returned channel number:
4908 * - To reinject this channel into another function LL_ADC_xxx:
4909 * the returned channel number is only partly formatted on definition
4910 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
4911 * with parts of literals LL_ADC_CHANNEL_x or using
4912 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4913 * Then the selected literal LL_ADC_CHANNEL_x can be used
4914 * as parameter for another function.
4915 * - To get the channel number in decimal format:
4916 * process the returned value with the helper macro
4917 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4918 * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n
4919 * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n
4920 * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n
4921 * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
4922 * @param ADCx ADC instance
4923 * @param Rank This parameter can be one of the following values:
4924 * @arg @ref LL_ADC_INJ_RANK_1
4925 * @arg @ref LL_ADC_INJ_RANK_2
4926 * @arg @ref LL_ADC_INJ_RANK_3
4927 * @arg @ref LL_ADC_INJ_RANK_4
4928 * @retval Returned value can be one of the following values:
4929 * @arg @ref LL_ADC_CHANNEL_0
4930 * @arg @ref LL_ADC_CHANNEL_1 (7)
4931 * @arg @ref LL_ADC_CHANNEL_2 (7)
4932 * @arg @ref LL_ADC_CHANNEL_3 (7)
4933 * @arg @ref LL_ADC_CHANNEL_4 (7)
4934 * @arg @ref LL_ADC_CHANNEL_5 (7)
4935 * @arg @ref LL_ADC_CHANNEL_6
4936 * @arg @ref LL_ADC_CHANNEL_7
4937 * @arg @ref LL_ADC_CHANNEL_8
4938 * @arg @ref LL_ADC_CHANNEL_9
4939 * @arg @ref LL_ADC_CHANNEL_10
4940 * @arg @ref LL_ADC_CHANNEL_11
4941 * @arg @ref LL_ADC_CHANNEL_12
4942 * @arg @ref LL_ADC_CHANNEL_13
4943 * @arg @ref LL_ADC_CHANNEL_14
4944 * @arg @ref LL_ADC_CHANNEL_15
4945 * @arg @ref LL_ADC_CHANNEL_16
4946 * @arg @ref LL_ADC_CHANNEL_17
4947 * @arg @ref LL_ADC_CHANNEL_18
4948 * @arg @ref LL_ADC_CHANNEL_VREFINT (4)
4949 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
4950 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
4951 *
4952 * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4953 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
4954 * (4) For ADC channel read back from ADC register,
4955 * comparison with internal channel parameter to be done
4956 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
4957 */
LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef * ADCx,uint32_t Rank)4958 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
4959 {
4960 return (uint32_t)((READ_BIT(ADCx->JSQR,
4961 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
4962 >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
4963 );
4964 }
4965
4966 /**
4967 * @brief Set ADC group injected conversion trigger:
4968 * independent or from ADC group regular.
4969 * @note This mode can be used to extend number of data registers
4970 * updated after one ADC conversion trigger and with data
4971 * permanently kept (not erased by successive conversions of scan of
4972 * ADC sequencer ranks), up to 5 data registers:
4973 * 1 data register on ADC group regular, 4 data registers
4974 * on ADC group injected.
4975 * @note If ADC group injected injected trigger source is set to an
4976 * external trigger, this feature must be must be set to
4977 * independent trigger.
4978 * ADC group injected automatic trigger is compliant only with
4979 * group injected trigger source set to SW start, without any
4980 * further action on ADC group injected conversion start or stop:
4981 * in this case, ADC group injected is controlled only
4982 * from ADC group regular.
4983 * @note It is not possible to enable both ADC group injected
4984 * auto-injected mode and sequencer discontinuous mode.
4985 * @note On this STM32 series, setting of this feature is conditioned to
4986 * ADC state:
4987 * ADC must be disabled or enabled without conversion on going
4988 * on either groups regular or injected.
4989 * @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto
4990 * @param ADCx ADC instance
4991 * @param TrigAuto This parameter can be one of the following values:
4992 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
4993 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
4994 * @retval None
4995 */
LL_ADC_INJ_SetTrigAuto(ADC_TypeDef * ADCx,uint32_t TrigAuto)4996 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
4997 {
4998 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
4999 }
5000
5001 /**
5002 * @brief Get ADC group injected conversion trigger:
5003 * independent or from ADC group regular.
5004 * @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto
5005 * @param ADCx ADC instance
5006 * @retval Returned value can be one of the following values:
5007 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
5008 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
5009 */
LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef * ADCx)5010 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef *ADCx)
5011 {
5012 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
5013 }
5014
5015 /**
5016 * @brief Set ADC group injected contexts queue mode.
5017 * @note A context is a setting of group injected sequencer:
5018 * - group injected trigger
5019 * - sequencer length
5020 * - sequencer ranks
5021 * If contexts queue is disabled:
5022 * - only 1 sequence can be configured
5023 * and is active perpetually.
5024 * If contexts queue is enabled:
5025 * - up to 2 contexts can be queued
5026 * and are checked in and out as a FIFO stack (first-in, first-out).
5027 * - If a new context is set when queues is full, error is triggered
5028 * by interruption "Injected Queue Overflow".
5029 * - Two behaviors are possible when all contexts have been processed:
5030 * the contexts queue can maintain the last context active perpetually
5031 * or can be empty and injected group triggers are disabled.
5032 * - Triggers can be only external (not internal SW start)
5033 * - Caution: The sequence must be fully configured in one time
5034 * (one write of register JSQR makes a check-in of a new context
5035 * into the queue).
5036 * Therefore functions to set separately injected trigger and
5037 * sequencer channels cannot be used, register JSQR must be set
5038 * using function @ref LL_ADC_INJ_ConfigQueueContext().
5039 * @note This parameter can be modified only when no conversion is on going
5040 * on either groups regular or injected.
5041 * @note A modification of the context mode (bit JQDIS) causes the contexts
5042 * queue to be flushed and the register JSQR is cleared.
5043 * @note On this STM32 series, setting of this feature is conditioned to
5044 * ADC state:
5045 * ADC must be disabled or enabled without conversion on going
5046 * on either groups regular or injected.
5047 * @rmtoll CFGR JQM LL_ADC_INJ_SetQueueMode\n
5048 * CFGR JQDIS LL_ADC_INJ_SetQueueMode
5049 * @param ADCx ADC instance
5050 * @param QueueMode This parameter can be one of the following values:
5051 * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
5052 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
5053 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
5054 * @retval None
5055 */
LL_ADC_INJ_SetQueueMode(ADC_TypeDef * ADCx,uint32_t QueueMode)5056 __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
5057 {
5058 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
5059 }
5060
5061 /**
5062 * @brief Get ADC group injected context queue mode.
5063 * @rmtoll CFGR JQM LL_ADC_INJ_GetQueueMode\n
5064 * CFGR JQDIS LL_ADC_INJ_GetQueueMode
5065 * @param ADCx ADC instance
5066 * @retval Returned value can be one of the following values:
5067 * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
5068 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
5069 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
5070 */
LL_ADC_INJ_GetQueueMode(const ADC_TypeDef * ADCx)5071 __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(const ADC_TypeDef *ADCx)
5072 {
5073 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
5074 }
5075
5076 /**
5077 * @brief Set one context on ADC group injected that will be checked in
5078 * contexts queue.
5079 * @note A context is a setting of group injected sequencer:
5080 * - group injected trigger
5081 * - sequencer length
5082 * - sequencer ranks
5083 * This function is intended to be used when contexts queue is enabled,
5084 * because the sequence must be fully configured in one time
5085 * (functions to set separately injected trigger and sequencer channels
5086 * cannot be used):
5087 * Refer to function @ref LL_ADC_INJ_SetQueueMode().
5088 * @note In the contexts queue, only the active context can be read.
5089 * The parameters of this function can be read using functions:
5090 * @arg @ref LL_ADC_INJ_GetTriggerSource()
5091 * @arg @ref LL_ADC_INJ_GetTriggerEdge()
5092 * @arg @ref LL_ADC_INJ_GetSequencerRanks()
5093 * @note On this STM32 series, to measure internal channels (VrefInt,
5094 * TempSensor, ...), measurement paths to internal channels must be
5095 * enabled separately.
5096 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
5097 * @note On STM32WB (except devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx), some fast channels are available: fast analog inputs
5098 * coming from GPIO pads (ADC_IN1..5).
5099 * @note On this STM32 series, setting of this feature is conditioned to
5100 * ADC state:
5101 * ADC must not be disabled. Can be enabled with or without conversion
5102 * on going on either groups regular or injected.
5103 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n
5104 * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n
5105 * JSQR JL LL_ADC_INJ_ConfigQueueContext\n
5106 * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n
5107 * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n
5108 * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n
5109 * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext
5110 * @param ADCx ADC instance
5111 * @param TriggerSource This parameter can be one of the following values:
5112 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
5113 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
5114 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
5115 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
5116 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
5117 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
5118 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
5119 * @param ExternalTriggerEdge This parameter can be one of the following values:
5120 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
5121 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
5122 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
5123 *
5124 * Note: This parameter is discarded in case of SW start:
5125 * parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
5126 * @param SequencerNbRanks This parameter can be one of the following values:
5127 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
5128 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
5129 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
5130 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
5131 * @param Rank1_Channel This parameter can be one of the following values:
5132 * @arg @ref LL_ADC_CHANNEL_0
5133 * @arg @ref LL_ADC_CHANNEL_1 (7)
5134 * @arg @ref LL_ADC_CHANNEL_2 (7)
5135 * @arg @ref LL_ADC_CHANNEL_3 (7)
5136 * @arg @ref LL_ADC_CHANNEL_4 (7)
5137 * @arg @ref LL_ADC_CHANNEL_5 (7)
5138 * @arg @ref LL_ADC_CHANNEL_6
5139 * @arg @ref LL_ADC_CHANNEL_7
5140 * @arg @ref LL_ADC_CHANNEL_8
5141 * @arg @ref LL_ADC_CHANNEL_9
5142 * @arg @ref LL_ADC_CHANNEL_10
5143 * @arg @ref LL_ADC_CHANNEL_11
5144 * @arg @ref LL_ADC_CHANNEL_12
5145 * @arg @ref LL_ADC_CHANNEL_13
5146 * @arg @ref LL_ADC_CHANNEL_14
5147 * @arg @ref LL_ADC_CHANNEL_15
5148 * @arg @ref LL_ADC_CHANNEL_16
5149 * @arg @ref LL_ADC_CHANNEL_17
5150 * @arg @ref LL_ADC_CHANNEL_18
5151 * @arg @ref LL_ADC_CHANNEL_VREFINT
5152 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
5153 * @arg @ref LL_ADC_CHANNEL_VBAT
5154 *
5155 * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
5156 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
5157 * @param Rank2_Channel This parameter can be one of the following values:
5158 * @arg @ref LL_ADC_CHANNEL_0
5159 * @arg @ref LL_ADC_CHANNEL_1 (7)
5160 * @arg @ref LL_ADC_CHANNEL_2 (7)
5161 * @arg @ref LL_ADC_CHANNEL_3 (7)
5162 * @arg @ref LL_ADC_CHANNEL_4 (7)
5163 * @arg @ref LL_ADC_CHANNEL_5 (7)
5164 * @arg @ref LL_ADC_CHANNEL_6
5165 * @arg @ref LL_ADC_CHANNEL_7
5166 * @arg @ref LL_ADC_CHANNEL_8
5167 * @arg @ref LL_ADC_CHANNEL_9
5168 * @arg @ref LL_ADC_CHANNEL_10
5169 * @arg @ref LL_ADC_CHANNEL_11
5170 * @arg @ref LL_ADC_CHANNEL_12
5171 * @arg @ref LL_ADC_CHANNEL_13
5172 * @arg @ref LL_ADC_CHANNEL_14
5173 * @arg @ref LL_ADC_CHANNEL_15
5174 * @arg @ref LL_ADC_CHANNEL_16
5175 * @arg @ref LL_ADC_CHANNEL_17
5176 * @arg @ref LL_ADC_CHANNEL_18
5177 * @arg @ref LL_ADC_CHANNEL_VREFINT
5178 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
5179 * @arg @ref LL_ADC_CHANNEL_VBAT
5180 *
5181 * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
5182 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
5183 * @param Rank3_Channel This parameter can be one of the following values:
5184 * @arg @ref LL_ADC_CHANNEL_0
5185 * @arg @ref LL_ADC_CHANNEL_1 (7)
5186 * @arg @ref LL_ADC_CHANNEL_2 (7)
5187 * @arg @ref LL_ADC_CHANNEL_3 (7)
5188 * @arg @ref LL_ADC_CHANNEL_4 (7)
5189 * @arg @ref LL_ADC_CHANNEL_5 (7)
5190 * @arg @ref LL_ADC_CHANNEL_6
5191 * @arg @ref LL_ADC_CHANNEL_7
5192 * @arg @ref LL_ADC_CHANNEL_8
5193 * @arg @ref LL_ADC_CHANNEL_9
5194 * @arg @ref LL_ADC_CHANNEL_10
5195 * @arg @ref LL_ADC_CHANNEL_11
5196 * @arg @ref LL_ADC_CHANNEL_12
5197 * @arg @ref LL_ADC_CHANNEL_13
5198 * @arg @ref LL_ADC_CHANNEL_14
5199 * @arg @ref LL_ADC_CHANNEL_15
5200 * @arg @ref LL_ADC_CHANNEL_16
5201 * @arg @ref LL_ADC_CHANNEL_17
5202 * @arg @ref LL_ADC_CHANNEL_18
5203 * @arg @ref LL_ADC_CHANNEL_VREFINT
5204 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
5205 * @arg @ref LL_ADC_CHANNEL_VBAT
5206 *
5207 * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
5208 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
5209 * @param Rank4_Channel This parameter can be one of the following values:
5210 * @arg @ref LL_ADC_CHANNEL_0
5211 * @arg @ref LL_ADC_CHANNEL_1 (7)
5212 * @arg @ref LL_ADC_CHANNEL_2 (7)
5213 * @arg @ref LL_ADC_CHANNEL_3 (7)
5214 * @arg @ref LL_ADC_CHANNEL_4 (7)
5215 * @arg @ref LL_ADC_CHANNEL_5 (7)
5216 * @arg @ref LL_ADC_CHANNEL_6
5217 * @arg @ref LL_ADC_CHANNEL_7
5218 * @arg @ref LL_ADC_CHANNEL_8
5219 * @arg @ref LL_ADC_CHANNEL_9
5220 * @arg @ref LL_ADC_CHANNEL_10
5221 * @arg @ref LL_ADC_CHANNEL_11
5222 * @arg @ref LL_ADC_CHANNEL_12
5223 * @arg @ref LL_ADC_CHANNEL_13
5224 * @arg @ref LL_ADC_CHANNEL_14
5225 * @arg @ref LL_ADC_CHANNEL_15
5226 * @arg @ref LL_ADC_CHANNEL_16
5227 * @arg @ref LL_ADC_CHANNEL_17
5228 * @arg @ref LL_ADC_CHANNEL_18
5229 * @arg @ref LL_ADC_CHANNEL_VREFINT
5230 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
5231 * @arg @ref LL_ADC_CHANNEL_VBAT
5232 *
5233 * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
5234 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
5235 * @retval None
5236 */
LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef * ADCx,uint32_t TriggerSource,uint32_t ExternalTriggerEdge,uint32_t SequencerNbRanks,uint32_t Rank1_Channel,uint32_t Rank2_Channel,uint32_t Rank3_Channel,uint32_t Rank4_Channel)5237 __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
5238 uint32_t TriggerSource,
5239 uint32_t ExternalTriggerEdge,
5240 uint32_t SequencerNbRanks,
5241 uint32_t Rank1_Channel,
5242 uint32_t Rank2_Channel,
5243 uint32_t Rank3_Channel,
5244 uint32_t Rank4_Channel)
5245 {
5246 /* Set bits with content of parameter "Rankx_Channel" with bits position */
5247 /* in register depending on literal "LL_ADC_INJ_RANK_x". */
5248 /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */
5249 /* because containing other bits reserved for other purpose. */
5250 /* If parameter "TriggerSource" is set to SW start, then parameter */
5251 /* "ExternalTriggerEdge" is discarded. */
5252 uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
5253 MODIFY_REG(ADCx->JSQR,
5254 ADC_JSQR_JEXTSEL |
5255 ADC_JSQR_JEXTEN |
5256 ADC_JSQR_JSQ4 |
5257 ADC_JSQR_JSQ3 |
5258 ADC_JSQR_JSQ2 |
5259 ADC_JSQR_JSQ1 |
5260 ADC_JSQR_JL,
5261 (TriggerSource & ADC_JSQR_JEXTSEL) |
5262 (ExternalTriggerEdge * (is_trigger_not_sw)) |
5263 (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5264 (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5265 (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5266 (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5267 SequencerNbRanks
5268 );
5269 }
5270
5271 /**
5272 * @}
5273 */
5274
5275 #endif /* ADC_SUPPORT_2_5_MSPS */
5276 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
5277 * @{
5278 */
5279
5280 #if defined(ADC_SUPPORT_2_5_MSPS)
5281 /**
5282 * @brief Set sampling time of the selected ADC channel
5283 * Unit: ADC clock cycles.
5284 * @note On this device, sampling time is on channel scope: independently
5285 * of channel mapped on ADC group regular or injected.
5286 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
5287 * converted:
5288 * sampling time constraints must be respected (sampling time can be
5289 * adjusted in function of ADC clock frequency and sampling time
5290 * setting).
5291 * Refer to device datasheet for timings values (parameters TS_vrefint,
5292 * TS_temp, ...).
5293 * @note Conversion time is the addition of sampling time and processing time.
5294 * On this STM32 series, ADC processing time is:
5295 * - 12.5 ADC clock cycles at ADC resolution 12 bits
5296 * - 10.5 ADC clock cycles at ADC resolution 10 bits
5297 * - 8.5 ADC clock cycles at ADC resolution 8 bits
5298 * - 6.5 ADC clock cycles at ADC resolution 6 bits
5299 * @note In case of ADC conversion of internal channel (VrefInt,
5300 * temperature sensor, ...), a sampling time minimum value
5301 * is required.
5302 * Refer to device datasheet.
5303 * @note On this STM32 series, setting of this feature is conditioned to
5304 * ADC state:
5305 * ADC must be disabled or enabled without conversion on going
5306 * on either groups regular or injected.
5307 * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n
5308 * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n
5309 * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n
5310 * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n
5311 * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n
5312 * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n
5313 * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n
5314 * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n
5315 * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n
5316 * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n
5317 * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n
5318 * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n
5319 * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n
5320 * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n
5321 * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n
5322 * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n
5323 * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n
5324 * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n
5325 * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
5326 * @param ADCx ADC instance
5327 * @param Channel This parameter can be one of the following values:
5328 * @arg @ref LL_ADC_CHANNEL_0
5329 * @arg @ref LL_ADC_CHANNEL_1 (7)
5330 * @arg @ref LL_ADC_CHANNEL_2 (7)
5331 * @arg @ref LL_ADC_CHANNEL_3 (7)
5332 * @arg @ref LL_ADC_CHANNEL_4 (7)
5333 * @arg @ref LL_ADC_CHANNEL_5 (7)
5334 * @arg @ref LL_ADC_CHANNEL_6
5335 * @arg @ref LL_ADC_CHANNEL_7
5336 * @arg @ref LL_ADC_CHANNEL_8
5337 * @arg @ref LL_ADC_CHANNEL_9
5338 * @arg @ref LL_ADC_CHANNEL_10
5339 * @arg @ref LL_ADC_CHANNEL_11
5340 * @arg @ref LL_ADC_CHANNEL_12
5341 * @arg @ref LL_ADC_CHANNEL_13
5342 * @arg @ref LL_ADC_CHANNEL_14
5343 * @arg @ref LL_ADC_CHANNEL_15
5344 * @arg @ref LL_ADC_CHANNEL_16
5345 * @arg @ref LL_ADC_CHANNEL_17
5346 * @arg @ref LL_ADC_CHANNEL_18
5347 * @arg @ref LL_ADC_CHANNEL_VREFINT
5348 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
5349 * @arg @ref LL_ADC_CHANNEL_VBAT
5350 *
5351 * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
5352 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
5353 * @param SamplingTimeY This parameter can be one of the following values:
5354 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
5355 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
5356 * @retval None
5357 */
LL_ADC_SetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SamplingTimeY)5358 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTimeY)
5359 {
5360 /* Parameter "Channel" is used with masks because containing */
5361 /* other bits reserved for other purpose. */
5362 MODIFY_REG(ADCx->SMPR,
5363 (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS),
5364 (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS) & (SamplingTimeY & ADC_SAMPLING_TIME_CH_MASK)
5365 );
5366 }
5367 #else
5368 /**
5369 * @brief Set sampling time of the selected ADC channel
5370 * Unit: ADC clock cycles.
5371 * @note On this device, sampling time is on channel scope: independently
5372 * of channel mapped on ADC group regular or injected.
5373 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
5374 * converted:
5375 * sampling time constraints must be respected (sampling time can be
5376 * adjusted in function of ADC clock frequency and sampling time
5377 * setting).
5378 * Refer to device datasheet for timings values (parameters TS_vrefint,
5379 * TS_temp, ...).
5380 * @note Conversion time is the addition of sampling time and processing time.
5381 * On this STM32 series, ADC processing time is:
5382 * - 12.5 ADC clock cycles at ADC resolution 12 bits
5383 * - 10.5 ADC clock cycles at ADC resolution 10 bits
5384 * - 8.5 ADC clock cycles at ADC resolution 8 bits
5385 * - 6.5 ADC clock cycles at ADC resolution 6 bits
5386 * @note In case of ADC conversion of internal channel (VrefInt,
5387 * temperature sensor, ...), a sampling time minimum value
5388 * is required.
5389 * Refer to device datasheet.
5390 * @note On this STM32 series, setting of this feature is conditioned to
5391 * ADC state:
5392 * ADC must be disabled or enabled without conversion on going
5393 * on either groups regular or injected.
5394 * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n
5395 * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n
5396 * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n
5397 * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n
5398 * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n
5399 * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n
5400 * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n
5401 * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n
5402 * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n
5403 * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n
5404 * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n
5405 * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n
5406 * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n
5407 * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n
5408 * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n
5409 * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n
5410 * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n
5411 * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n
5412 * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
5413 * @param ADCx ADC instance
5414 * @param Channel This parameter can be one of the following values:
5415 * @arg @ref LL_ADC_CHANNEL_0
5416 * @arg @ref LL_ADC_CHANNEL_1 (7)
5417 * @arg @ref LL_ADC_CHANNEL_2 (7)
5418 * @arg @ref LL_ADC_CHANNEL_3 (7)
5419 * @arg @ref LL_ADC_CHANNEL_4 (7)
5420 * @arg @ref LL_ADC_CHANNEL_5 (7)
5421 * @arg @ref LL_ADC_CHANNEL_6
5422 * @arg @ref LL_ADC_CHANNEL_7
5423 * @arg @ref LL_ADC_CHANNEL_8
5424 * @arg @ref LL_ADC_CHANNEL_9
5425 * @arg @ref LL_ADC_CHANNEL_10
5426 * @arg @ref LL_ADC_CHANNEL_11
5427 * @arg @ref LL_ADC_CHANNEL_12
5428 * @arg @ref LL_ADC_CHANNEL_13
5429 * @arg @ref LL_ADC_CHANNEL_14
5430 * @arg @ref LL_ADC_CHANNEL_15
5431 * @arg @ref LL_ADC_CHANNEL_16
5432 * @arg @ref LL_ADC_CHANNEL_17
5433 * @arg @ref LL_ADC_CHANNEL_18
5434 * @arg @ref LL_ADC_CHANNEL_VREFINT
5435 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
5436 * @arg @ref LL_ADC_CHANNEL_VBAT
5437 *
5438 * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
5439 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
5440 * @param SamplingTime This parameter can be one of the following values:
5441 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
5442 * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
5443 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
5444 * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
5445 * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
5446 * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
5447 * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
5448 * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
5449 * @retval None
5450 */
LL_ADC_SetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SamplingTime)5451 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
5452 {
5453 #if defined(ADC_SUPPORT_2_5_MSPS)
5454 /* Parameter "Channel" is used with masks because containing */
5455 /* other bits reserved for other purpose. */
5456 MODIFY_REG(ADCx->SMPR,
5457 (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS),
5458 (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS) & (SamplingTimeY & ADC_SAMPLING_TIME_CH_MASK)
5459 );
5460 #else
5461 /* Set bits with content of parameter "SamplingTime" with bits position */
5462 /* in register and register position depending on parameter "Channel". */
5463 /* Parameter "Channel" is used with masks because containing */
5464 /* other bits reserved for other purpose. */
5465 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
5466
5467 MODIFY_REG(*preg,
5468 ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
5469 SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
5470 #endif /* ADC_SUPPORT_2_5_MSPS */
5471 }
5472 #endif /* ADC_SUPPORT_2_5_MSPS */
5473
5474 #if defined(ADC_SUPPORT_2_5_MSPS)
5475 /**
5476 * @brief Get sampling time of the selected ADC channel
5477 * Unit: ADC clock cycles.
5478 * @note On this device, sampling time is on channel scope: independently
5479 * of channel mapped on ADC group regular or injected.
5480 * @note Conversion time is the addition of sampling time and processing time.
5481 * On this STM32 series, ADC processing time is:
5482 * - 12.5 ADC clock cycles at ADC resolution 12 bits
5483 * - 10.5 ADC clock cycles at ADC resolution 10 bits
5484 * - 8.5 ADC clock cycles at ADC resolution 8 bits
5485 * - 6.5 ADC clock cycles at ADC resolution 6 bits
5486 * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n
5487 * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n
5488 * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n
5489 * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n
5490 * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n
5491 * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n
5492 * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n
5493 * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n
5494 * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n
5495 * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n
5496 * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n
5497 * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n
5498 * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n
5499 * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n
5500 * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n
5501 * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n
5502 * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n
5503 * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n
5504 * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
5505 * @param ADCx ADC instance
5506 * @param Channel This parameter can be one of the following values:
5507 * @arg @ref LL_ADC_CHANNEL_0
5508 * @arg @ref LL_ADC_CHANNEL_1 (7)
5509 * @arg @ref LL_ADC_CHANNEL_2 (7)
5510 * @arg @ref LL_ADC_CHANNEL_3 (7)
5511 * @arg @ref LL_ADC_CHANNEL_4 (7)
5512 * @arg @ref LL_ADC_CHANNEL_5 (7)
5513 * @arg @ref LL_ADC_CHANNEL_6
5514 * @arg @ref LL_ADC_CHANNEL_7
5515 * @arg @ref LL_ADC_CHANNEL_8
5516 * @arg @ref LL_ADC_CHANNEL_9
5517 * @arg @ref LL_ADC_CHANNEL_10
5518 * @arg @ref LL_ADC_CHANNEL_11
5519 * @arg @ref LL_ADC_CHANNEL_12
5520 * @arg @ref LL_ADC_CHANNEL_13
5521 * @arg @ref LL_ADC_CHANNEL_14
5522 * @arg @ref LL_ADC_CHANNEL_15
5523 * @arg @ref LL_ADC_CHANNEL_16
5524 * @arg @ref LL_ADC_CHANNEL_17
5525 * @arg @ref LL_ADC_CHANNEL_18
5526 * @arg @ref LL_ADC_CHANNEL_VREFINT
5527 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
5528 * @arg @ref LL_ADC_CHANNEL_VBAT
5529 *
5530 * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
5531 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
5532 * @retval Returned value can be one of the following values:
5533 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
5534 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
5535 */
LL_ADC_GetChannelSamplingTime(const ADC_TypeDef * ADCx,uint32_t Channel)5536 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel)
5537 {
5538 __IO uint32_t smpr = READ_REG(ADCx->SMPR);
5539
5540 /* Retrieve sampling time bit corresponding to the selected channel */
5541 /* and shift it to position 0. */
5542 uint32_t smp_channel_posbit0 = ((smpr & ADC_SAMPLING_TIME_CH_MASK)
5543 >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + ADC_SMPR_SMPSEL0_BITOFFSET_POS) & 0x1FUL));
5544
5545 /* Select sampling time bitfield depending on sampling time bit value 0 or 1. */
5546 return( (~(smp_channel_posbit0) * LL_ADC_SAMPLINGTIME_COMMON_1)
5547 | (smp_channel_posbit0 * LL_ADC_SAMPLINGTIME_COMMON_2) );
5548 }
5549 #else
5550 /**
5551 * @brief Get sampling time of the selected ADC channel
5552 * Unit: ADC clock cycles.
5553 * @note On this device, sampling time is on channel scope: independently
5554 * of channel mapped on ADC group regular or injected.
5555 * @note Conversion time is the addition of sampling time and processing time.
5556 * On this STM32 series, ADC processing time is:
5557 * - 12.5 ADC clock cycles at ADC resolution 12 bits
5558 * - 10.5 ADC clock cycles at ADC resolution 10 bits
5559 * - 8.5 ADC clock cycles at ADC resolution 8 bits
5560 * - 6.5 ADC clock cycles at ADC resolution 6 bits
5561 * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n
5562 * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n
5563 * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n
5564 * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n
5565 * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n
5566 * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n
5567 * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n
5568 * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n
5569 * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n
5570 * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n
5571 * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n
5572 * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n
5573 * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n
5574 * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n
5575 * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n
5576 * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n
5577 * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n
5578 * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n
5579 * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
5580 * @param ADCx ADC instance
5581 * @param Channel This parameter can be one of the following values:
5582 * @arg @ref LL_ADC_CHANNEL_0
5583 * @arg @ref LL_ADC_CHANNEL_1 (7)
5584 * @arg @ref LL_ADC_CHANNEL_2 (7)
5585 * @arg @ref LL_ADC_CHANNEL_3 (7)
5586 * @arg @ref LL_ADC_CHANNEL_4 (7)
5587 * @arg @ref LL_ADC_CHANNEL_5 (7)
5588 * @arg @ref LL_ADC_CHANNEL_6
5589 * @arg @ref LL_ADC_CHANNEL_7
5590 * @arg @ref LL_ADC_CHANNEL_8
5591 * @arg @ref LL_ADC_CHANNEL_9
5592 * @arg @ref LL_ADC_CHANNEL_10
5593 * @arg @ref LL_ADC_CHANNEL_11
5594 * @arg @ref LL_ADC_CHANNEL_12
5595 * @arg @ref LL_ADC_CHANNEL_13
5596 * @arg @ref LL_ADC_CHANNEL_14
5597 * @arg @ref LL_ADC_CHANNEL_15
5598 * @arg @ref LL_ADC_CHANNEL_16
5599 * @arg @ref LL_ADC_CHANNEL_17
5600 * @arg @ref LL_ADC_CHANNEL_18
5601 * @arg @ref LL_ADC_CHANNEL_VREFINT
5602 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
5603 * @arg @ref LL_ADC_CHANNEL_VBAT
5604 *
5605 * (7) On STM32WB devices (except devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx) fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
5606 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
5607 * @retval Returned value can be one of the following values:
5608 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
5609 * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
5610 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
5611 * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
5612 * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
5613 * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
5614 * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
5615 * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
5616 */
LL_ADC_GetChannelSamplingTime(const ADC_TypeDef * ADCx,uint32_t Channel)5617 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel)
5618 {
5619 #if defined(ADC_SUPPORT_2_5_MSPS)
5620 __IO uint32_t smpr = READ_REG(ADCx->SMPR);
5621
5622 /* Retrieve sampling time bit corresponding to the selected channel */
5623 /* and shift it to position 0. */
5624 uint32_t smp_channel_posbit0 = ((smpr & ADC_SAMPLING_TIME_CH_MASK)
5625 >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + ADC_SMPR_SMPSEL0_BITOFFSET_POS) & 0x1FUL));
5626
5627 /* Select sampling time bitfield depending on sampling time bit value 0 or 1. */
5628 return( (~(smp_channel_posbit0) * LL_ADC_SAMPLINGTIME_COMMON_1)
5629 | (smp_channel_posbit0 * LL_ADC_SAMPLINGTIME_COMMON_2) );
5630 #else
5631 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
5632
5633 return (uint32_t)(READ_BIT(*preg,
5634 ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))
5635 >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)
5636 );
5637 #endif /* ADC_SUPPORT_2_5_MSPS */
5638 }
5639 #endif /* ADC_SUPPORT_2_5_MSPS */
5640
5641 #if defined(ADC_SUPPORT_2_5_MSPS)
5642 /* Feature "ADC channel differential mode" not available on ADC peripheral of this STM32WB device */
5643 #else
5644 /**
5645 * @brief Set mode single-ended or differential input of the selected
5646 * ADC channel.
5647 * @note Channel ending is on channel scope: independently of channel mapped
5648 * on ADC group regular or injected.
5649 * In differential mode: Differential measurement is carried out
5650 * between the selected channel 'i' (positive input) and
5651 * channel 'i+1' (negative input). Only channel 'i' has to be
5652 * configured, channel 'i+1' is configured automatically.
5653 * @note Refer to Reference Manual to ensure the selected channel is
5654 * available in differential mode.
5655 * For example, internal channels (VrefInt, TempSensor, ...) are
5656 * not available in differential mode.
5657 * @note When configuring a channel 'i' in differential mode,
5658 * the channel 'i+1' is not usable separately.
5659 * @note On STM32WB, channels 16, 17, 18 of ADC1
5660 * are internally fixed to single-ended inputs configuration.
5661 * @note For ADC channels configured in differential mode, both inputs
5662 * should be biased at (Vref+)/2 +/-200mV.
5663 * (Vref+ is the analog voltage reference)
5664 * @note On this STM32 series, setting of this feature is conditioned to
5665 * ADC state:
5666 * ADC must be ADC disabled.
5667 * @note One or several values can be selected.
5668 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
5669 * @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff
5670 * @param ADCx ADC instance
5671 * @param Channel This parameter can be one of the following values:
5672 * @arg @ref LL_ADC_CHANNEL_1
5673 * @arg @ref LL_ADC_CHANNEL_2
5674 * @arg @ref LL_ADC_CHANNEL_3
5675 * @arg @ref LL_ADC_CHANNEL_4
5676 * @arg @ref LL_ADC_CHANNEL_5
5677 * @arg @ref LL_ADC_CHANNEL_6
5678 * @arg @ref LL_ADC_CHANNEL_7
5679 * @arg @ref LL_ADC_CHANNEL_8
5680 * @arg @ref LL_ADC_CHANNEL_9
5681 * @arg @ref LL_ADC_CHANNEL_10
5682 * @arg @ref LL_ADC_CHANNEL_11
5683 * @arg @ref LL_ADC_CHANNEL_12
5684 * @arg @ref LL_ADC_CHANNEL_13
5685 * @arg @ref LL_ADC_CHANNEL_14
5686 * @arg @ref LL_ADC_CHANNEL_15
5687 * @param SingleDiff This parameter can be a combination of the following values:
5688 * @arg @ref LL_ADC_SINGLE_ENDED
5689 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
5690 * @retval None
5691 */
LL_ADC_SetChannelSingleDiff(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SingleDiff)5692 __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
5693 {
5694 /* Bits of channels in single or differential mode are set only for */
5695 /* differential mode (for single mode, mask of bits allowed to be set is */
5696 /* shifted out of range of bits of channels in single or differential mode. */
5697 MODIFY_REG(ADCx->DIFSEL,
5698 Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
5699 (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
5700 }
5701
5702 /**
5703 * @brief Get mode single-ended or differential input of the selected
5704 * ADC channel.
5705 * @note When configuring a channel 'i' in differential mode,
5706 * the channel 'i+1' is not usable separately.
5707 * Therefore, to ensure a channel is configured in single-ended mode,
5708 * the configuration of channel itself and the channel 'i-1' must be
5709 * read back (to ensure that the selected channel channel has not been
5710 * configured in differential mode by the previous channel).
5711 * @note Refer to Reference Manual to ensure the selected channel is
5712 * available in differential mode.
5713 * For example, internal channels (VrefInt, TempSensor, ...) are
5714 * not available in differential mode.
5715 * @note When configuring a channel 'i' in differential mode,
5716 * the channel 'i+1' is not usable separately.
5717 * @note On STM32WB, channels 16, 17, 18 of ADC1
5718 * are internally fixed to single-ended inputs configuration.
5719 * @note One or several values can be selected. In this case, the value
5720 * returned is null if all channels are in single ended-mode.
5721 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
5722 * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff
5723 * @param ADCx ADC instance
5724 * @param Channel This parameter can be a combination of the following values:
5725 * @arg @ref LL_ADC_CHANNEL_1
5726 * @arg @ref LL_ADC_CHANNEL_2
5727 * @arg @ref LL_ADC_CHANNEL_3
5728 * @arg @ref LL_ADC_CHANNEL_4
5729 * @arg @ref LL_ADC_CHANNEL_5
5730 * @arg @ref LL_ADC_CHANNEL_6
5731 * @arg @ref LL_ADC_CHANNEL_7
5732 * @arg @ref LL_ADC_CHANNEL_8
5733 * @arg @ref LL_ADC_CHANNEL_9
5734 * @arg @ref LL_ADC_CHANNEL_10
5735 * @arg @ref LL_ADC_CHANNEL_11
5736 * @arg @ref LL_ADC_CHANNEL_12
5737 * @arg @ref LL_ADC_CHANNEL_13
5738 * @arg @ref LL_ADC_CHANNEL_14
5739 * @arg @ref LL_ADC_CHANNEL_15
5740 * @retval 0: channel in single-ended mode, else: channel in differential mode
5741 */
LL_ADC_GetChannelSingleDiff(const ADC_TypeDef * ADCx,uint32_t Channel)5742 __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(const ADC_TypeDef *ADCx, uint32_t Channel)
5743 {
5744 return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
5745 }
5746
5747 #endif /* ADC_SUPPORT_2_5_MSPS */
5748 /**
5749 * @}
5750 */
5751
5752 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
5753 * @{
5754 */
5755
5756 /**
5757 * @brief Set ADC analog watchdog monitored channels:
5758 * a single channel, multiple channels or all channels,
5759 * on ADC groups regular and-or injected.
5760 * @note Once monitored channels are selected, analog watchdog
5761 * is enabled.
5762 * @note In case of need to define a single channel to monitor
5763 * with analog watchdog from sequencer channel definition,
5764 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
5765 * @note On this STM32 series, there are 2 kinds of analog watchdog
5766 * instance:
5767 * - AWD standard (instance AWD1):
5768 * - channels monitored: can monitor 1 channel or all channels.
5769 * - groups monitored: ADC groups regular and-or injected.
5770 * - resolution: resolution is not limited (corresponds to
5771 * ADC resolution configured).
5772 * - AWD flexible (instances AWD2, AWD3):
5773 * - channels monitored: flexible on channels monitored, selection is
5774 * channel wise, from from 1 to all channels.
5775 * Specificity of this analog watchdog: Multiple channels can
5776 * be selected. For example:
5777 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5778 * - groups monitored: not selection possible (monitoring on both
5779 * groups regular and injected).
5780 * Channels selected are monitored on groups regular and injected:
5781 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5782 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5783 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5784 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5785 * the 2 LSB are ignored.
5786 * @note On this STM32 series, setting of this feature is conditioned to
5787 * ADC state:
5788 * ADC must be disabled or enabled without conversion on going
5789 * on either groups regular or injected.
5790 * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
5791 * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
5792 * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
5793 * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n
5794 * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
5795 * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
5796 * @param ADCx ADC instance
5797 * @param AWDy This parameter can be one of the following values:
5798 * @arg @ref LL_ADC_AWD1
5799 * @arg @ref LL_ADC_AWD2
5800 * @arg @ref LL_ADC_AWD3
5801 * @param AWDChannelGroup This parameter can be one of the following values:
5802 * @arg @ref LL_ADC_AWD_DISABLE
5803 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
5804 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)(1)
5805 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ (1)
5806 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
5807 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)(1)
5808 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ (1)
5809 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
5810 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)(1)
5811 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ (1)
5812 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
5813 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)(1)
5814 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ (1)
5815 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
5816 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)(1)
5817 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ (1)
5818 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
5819 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)(1)
5820 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ (1)
5821 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
5822 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)(1)
5823 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ (1)
5824 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
5825 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)(1)
5826 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ (1)
5827 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
5828 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)(1)
5829 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ (1)
5830 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
5831 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)(1)
5832 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ (1)
5833 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
5834 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)(1)
5835 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ (1)
5836 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
5837 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)(1)
5838 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ (1)
5839 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
5840 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)(1)
5841 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ (1)
5842 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
5843 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)(1)
5844 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ (1)
5845 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
5846 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)(1)
5847 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ (1)
5848 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
5849 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)(1)
5850 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ (1)
5851 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
5852 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)(1)
5853 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ (1)
5854 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
5855 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)(1)
5856 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ (1)
5857 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
5858 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)(1)
5859 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ (1)
5860 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
5861 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)(1)
5862 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ (1)
5863 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)
5864 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
5865 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
5866 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)
5867 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
5868 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
5869 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)
5870 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
5871 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
5872 *
5873 * (0) On STM32WB, parameter available only on analog watchdog number: AWD1.
5874 * (1) On STM32WB series, parameter not available on devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx.
5875 * @retval None
5876 */
LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDChannelGroup)5877 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
5878 {
5879 #if defined(ADC_SUPPORT_2_5_MSPS)
5880 /* Prevent unused argument(s) compilation warning */
5881 (void)(AWDy);
5882
5883 MODIFY_REG(ADCx->CFGR1,
5884 (LL_ADC_AWD1 & ADC_AWD_CR_ALL_CHANNEL_MASK),
5885 AWDChannelGroup & LL_ADC_AWD1);
5886 #else
5887 /* Set bits with content of parameter "AWDChannelGroup" with bits position */
5888 /* in register and register position depending on parameter "AWDy". */
5889 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
5890 /* containing other bits reserved for other purpose. */
5891 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
5892 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
5893
5894 MODIFY_REG(*preg,
5895 (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
5896 AWDChannelGroup & AWDy);
5897 #endif /* ADC_SUPPORT_2_5_MSPS */
5898 }
5899
5900 /**
5901 * @brief Get ADC analog watchdog monitored channel.
5902 * @note Usage of the returned channel number:
5903 * - To reinject this channel into another function LL_ADC_xxx:
5904 * the returned channel number is only partly formatted on definition
5905 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
5906 * with parts of literals LL_ADC_CHANNEL_x or using
5907 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5908 * Then the selected literal LL_ADC_CHANNEL_x can be used
5909 * as parameter for another function.
5910 * - To get the channel number in decimal format:
5911 * process the returned value with the helper macro
5912 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5913 * Applicable only when the analog watchdog is set to monitor
5914 * one channel.
5915 * @note On this STM32 series, there are 2 kinds of analog watchdog
5916 * instance:
5917 * - AWD standard (instance AWD1):
5918 * - channels monitored: can monitor 1 channel or all channels.
5919 * - groups monitored: ADC groups regular and-or injected.
5920 * - resolution: resolution is not limited (corresponds to
5921 * ADC resolution configured).
5922 * - AWD flexible (instances AWD2, AWD3):
5923 * - channels monitored: flexible on channels monitored, selection is
5924 * channel wise, from from 1 to all channels.
5925 * Specificity of this analog watchdog: Multiple channels can
5926 * be selected. For example:
5927 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5928 * - groups monitored: not selection possible (monitoring on both
5929 * groups regular and injected).
5930 * Channels selected are monitored on groups regular and injected:
5931 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5932 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5933 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5934 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5935 * the 2 LSB are ignored.
5936 * @note On this STM32 series, setting of this feature is conditioned to
5937 * ADC state:
5938 * ADC must be disabled or enabled without conversion on going
5939 * on either groups regular or injected.
5940 * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
5941 * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
5942 * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
5943 * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n
5944 * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
5945 * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
5946 * @param ADCx ADC instance
5947 * @param AWDy This parameter can be one of the following values:
5948 * @arg @ref LL_ADC_AWD1
5949 * @arg @ref LL_ADC_AWD2 (1)(2)
5950 * @arg @ref LL_ADC_AWD3 (1)(2)
5951 *
5952 * (1) On this AWD number, monitored channel can be retrieved
5953 * if only 1 channel is programmed (or none or all channels).
5954 * This function cannot retrieve monitored channel if
5955 * multiple channels are programmed simultaneously
5956 * by bitfield.
5957 * (2) On STM32WB series, parameter not available on devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx.
5958 * @retval Returned value can be one of the following values:
5959 * @arg @ref LL_ADC_AWD_DISABLE
5960 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
5961 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)(1)
5962 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ (1)
5963 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
5964 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)(1)
5965 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ (1)
5966 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
5967 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)(1)
5968 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ (1)
5969 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
5970 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)(1)
5971 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ (1)
5972 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
5973 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)(1)
5974 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ (1)
5975 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
5976 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)(1)
5977 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ (1)
5978 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
5979 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)(1)
5980 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ (1)
5981 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
5982 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)(1)
5983 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ (1)
5984 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
5985 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)(1)
5986 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ (1)
5987 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
5988 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)(1)
5989 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ (1)
5990 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
5991 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)(1)
5992 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ (1)
5993 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
5994 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)(1)
5995 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ (1)
5996 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
5997 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)(1)
5998 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ (1)
5999 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
6000 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)(1)
6001 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ (1)
6002 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
6003 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)(1)
6004 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ (1)
6005 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
6006 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)(1)
6007 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ (1)
6008 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
6009 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)(1)
6010 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ (1)
6011 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
6012 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)(1)
6013 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ (1)
6014 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
6015 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)(1)
6016 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ (1)
6017 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
6018 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)(1)
6019 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ (1)
6020 *
6021 * (0) On STM32WB, parameter available only on analog watchdog number: AWD1.
6022 * (1) On STM32WB series, parameter not available on devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx.
6023 */
LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef * ADCx,uint32_t AWDy)6024 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy)
6025 {
6026 #if defined(ADC_SUPPORT_2_5_MSPS)
6027 /* Prevent unused argument(s) compilation warning */
6028 (void)(AWDy);
6029
6030 uint32_t AnalogWDMonitChannels = (READ_BIT(ADCx->CFGR1, LL_ADC_AWD1) & LL_ADC_AWD1 & ADC_AWD_CR_ALL_CHANNEL_MASK);
6031
6032 /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */
6033 /* (parameter value LL_ADC_AWD_DISABLE). */
6034 /* Else, the selected AWD is enabled and is monitoring a group of channels */
6035 /* or a single channel. */
6036 if(AnalogWDMonitChannels != 0UL)
6037 {
6038 if((AnalogWDMonitChannels & ADC_CFGR1_AWD1SGL) == 0UL)
6039 {
6040 /* AWD monitoring a group of channels */
6041 AnalogWDMonitChannels = (AnalogWDMonitChannels
6042 & (~(ADC_CFGR1_AWD1CH))
6043 );
6044 }
6045 else
6046 {
6047 /* AWD monitoring a single channel */
6048 AnalogWDMonitChannels = (AnalogWDMonitChannels
6049 | (0x01UL << (AnalogWDMonitChannels >> ADC_CFGR1_AWD1CH_Pos))
6050 );
6051 }
6052 }
6053
6054 return AnalogWDMonitChannels;
6055 #else
6056 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
6057 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
6058
6059 uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
6060
6061 /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */
6062 /* (parameter value LL_ADC_AWD_DISABLE). */
6063 /* Else, the selected AWD is enabled and is monitoring a group of channels */
6064 /* or a single channel. */
6065 if (AnalogWDMonitChannels != 0UL)
6066 {
6067 if (AWDy == LL_ADC_AWD1)
6068 {
6069 if ((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL)
6070 {
6071 /* AWD monitoring a group of channels */
6072 AnalogWDMonitChannels = ((AnalogWDMonitChannels
6073 | (ADC_AWD_CR23_CHANNEL_MASK)
6074 )
6075 & (~(ADC_CFGR_AWD1CH))
6076 );
6077 }
6078 else
6079 {
6080 /* AWD monitoring a single channel */
6081 AnalogWDMonitChannels = (AnalogWDMonitChannels
6082 | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR_AWD1CH_Pos))
6083 );
6084 }
6085 }
6086 else
6087 {
6088 if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
6089 {
6090 /* AWD monitoring a group of channels */
6091 AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK
6092 | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))
6093 );
6094 }
6095 else
6096 {
6097 /* AWD monitoring a single channel */
6098 /* AWD monitoring a group of channels */
6099 AnalogWDMonitChannels = (AnalogWDMonitChannels
6100 | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
6101 | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos)
6102 );
6103 }
6104 }
6105 }
6106
6107 return AnalogWDMonitChannels;
6108 #endif /* ADC_SUPPORT_2_5_MSPS */
6109 }
6110
6111 /**
6112 * @brief Set ADC analog watchdog thresholds value of both thresholds
6113 * high and low.
6114 * @note If value of only one threshold high or low must be set,
6115 * use function @ref LL_ADC_SetAnalogWDThresholds().
6116 * @note In case of ADC resolution different of 12 bits,
6117 * analog watchdog thresholds data require a specific shift.
6118 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
6119 * @note On this STM32 series, there are 2 kinds of analog watchdog
6120 * instance:
6121 * - AWD standard (instance AWD1):
6122 * - channels monitored: can monitor 1 channel or all channels.
6123 * - groups monitored: ADC groups regular and-or injected.
6124 * - resolution: resolution is not limited (corresponds to
6125 * ADC resolution configured).
6126 * - AWD flexible (instances AWD2, AWD3):
6127 * - channels monitored: flexible on channels monitored, selection is
6128 * channel wise, from from 1 to all channels.
6129 * Specificity of this analog watchdog: Multiple channels can
6130 * be selected. For example:
6131 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
6132 * - groups monitored: not selection possible (monitoring on both
6133 * groups regular and injected).
6134 * Channels selected are monitored on groups regular and injected:
6135 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
6136 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
6137 * - resolution: resolution is limited to 8 bits: if ADC resolution is
6138 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
6139 * the 2 LSB are ignored.
6140 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
6141 * impacted: the comparison of analog watchdog thresholds is done on
6142 * oversampling final computation (after ratio and shift application):
6143 * ADC data register bitfield [15:4] (12 most significant bits).
6144 * @note On this STM32 series, setting of this feature is conditioned to
6145 * ADC state:
6146 * ADC must be disabled or enabled without conversion on going
6147 * on either groups regular or injected.
6148 * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n
6149 * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n
6150 * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n
6151 * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n
6152 * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n
6153 * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds
6154 * @note For devices STM32WB15xx and STM32WB10xx, register ADC_TR is equivalent to ADC_TR1 (generic naming)
6155 * @param ADCx ADC instance
6156 * @param AWDy This parameter can be one of the following values:
6157 * @arg @ref LL_ADC_AWD1
6158 * @arg @ref LL_ADC_AWD2 (1)
6159 * @arg @ref LL_ADC_AWD3 (1)
6160 *
6161 * (1) On STM32WB series, parameter not available on devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx.
6162 * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
6163 * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
6164 * @retval None
6165 */
LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdHighValue,uint32_t AWDThresholdLowValue)6166 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
6167 uint32_t AWDThresholdLowValue)
6168 {
6169 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
6170 /* position in register and register position depending on parameter */
6171 /* "AWDy". */
6172 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
6173 /* containing other bits reserved for other purpose. */
6174 #if defined(ADC_SUPPORT_2_5_MSPS)
6175 /* Prevent unused argument(s) compilation warning */
6176 (void)(AWDy);
6177
6178 MODIFY_REG(ADCx->TR,
6179 ADC_TR_HT | ADC_TR_LT,
6180 (AWDThresholdHighValue << ADC_TR_HT_BITOFFSET_POS) | AWDThresholdLowValue);
6181 #else
6182 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
6183
6184 MODIFY_REG(*preg,
6185 ADC_TR1_HT1 | ADC_TR1_LT1,
6186 (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
6187 #endif /* ADC_SUPPORT_2_5_MSPS */
6188 }
6189
6190 /**
6191 * @brief Set ADC analog watchdog threshold value of threshold
6192 * high or low.
6193 * @note If values of both thresholds high or low must be set,
6194 * use function @ref LL_ADC_ConfigAnalogWDThresholds().
6195 * @note In case of ADC resolution different of 12 bits,
6196 * analog watchdog thresholds data require a specific shift.
6197 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
6198 * @note On this STM32 series, there are 2 kinds of analog watchdog
6199 * instance:
6200 * - AWD standard (instance AWD1):
6201 * - channels monitored: can monitor 1 channel or all channels.
6202 * - groups monitored: ADC groups regular and-or injected.
6203 * - resolution: resolution is not limited (corresponds to
6204 * ADC resolution configured).
6205 * - AWD flexible (instances AWD2, AWD3):
6206 * - channels monitored: flexible on channels monitored, selection is
6207 * channel wise, from from 1 to all channels.
6208 * Specificity of this analog watchdog: Multiple channels can
6209 * be selected. For example:
6210 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
6211 * - groups monitored: not selection possible (monitoring on both
6212 * groups regular and injected).
6213 * Channels selected are monitored on groups regular and injected:
6214 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
6215 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
6216 * - resolution: resolution is limited to 8 bits: if ADC resolution is
6217 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
6218 * the 2 LSB are ignored.
6219 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
6220 * impacted: the comparison of analog watchdog thresholds is done on
6221 * oversampling final computation (after ratio and shift application):
6222 * ADC data register bitfield [15:4] (12 most significant bits).
6223 * @note On this STM32 series, setting of this feature is conditioned to
6224 * ADC state:
6225 * ADC must be disabled or enabled without conversion on going
6226 * on either ADC groups regular or injected.
6227 * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n
6228 * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n
6229 * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n
6230 * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n
6231 * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n
6232 * TR3 LT3 LL_ADC_SetAnalogWDThresholds
6233 * @note For devices STM32WB15xx and STM32WB10xx, register ADC_TR is equivalent to ADC_TR1 (generic naming)
6234 * @param ADCx ADC instance
6235 * @param AWDy This parameter can be one of the following values:
6236 * @arg @ref LL_ADC_AWD1
6237 * @arg @ref LL_ADC_AWD2 (1)
6238 * @arg @ref LL_ADC_AWD3 (1)
6239 *
6240 * (1) On STM32WB series, parameter not available on devices: STM32WB10xx, STM32, STM32WB1Mxx.
6241 * @param AWDThresholdsHighLow This parameter can be one of the following values:
6242 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
6243 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
6244 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
6245 * @retval None
6246 */
LL_ADC_SetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow,uint32_t AWDThresholdValue)6247 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
6248 uint32_t AWDThresholdValue)
6249 {
6250 /* Set bits with content of parameter "AWDThresholdValue" with bits */
6251 /* position in register and register position depending on parameters */
6252 /* "AWDThresholdsHighLow" and "AWDy". */
6253 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
6254 /* containing other bits reserved for other purpose. */
6255 #if defined(ADC_SUPPORT_2_5_MSPS)
6256 /* Prevent unused argument(s) compilation warning */
6257 (void)(AWDy);
6258
6259 MODIFY_REG(ADCx->TR,
6260 AWDThresholdsHighLow,
6261 AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
6262 #else
6263 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
6264
6265 MODIFY_REG(*preg,
6266 AWDThresholdsHighLow,
6267 AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
6268 #endif /* ADC_SUPPORT_2_5_MSPS */
6269 }
6270
6271 /**
6272 * @brief Get ADC analog watchdog threshold value of threshold high,
6273 * threshold low or raw data with ADC thresholds high and low
6274 * concatenated.
6275 * @note If raw data with ADC thresholds high and low is retrieved,
6276 * the data of each threshold high or low can be isolated
6277 * using helper macro:
6278 * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
6279 * @note In case of ADC resolution different of 12 bits,
6280 * analog watchdog thresholds data require a specific shift.
6281 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
6282 * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n
6283 * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n
6284 * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n
6285 * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n
6286 * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n
6287 * TR3 LT3 LL_ADC_GetAnalogWDThresholds
6288 * @note For devices STM32WB15xx and STM32WB10xx, register ADC_TR is equivalent to ADC_TR1 (generic naming)
6289 * @param ADCx ADC instance
6290 * @param AWDy This parameter can be one of the following values:
6291 * @arg @ref LL_ADC_AWD1
6292 * @arg @ref LL_ADC_AWD2 (1)
6293 * @arg @ref LL_ADC_AWD3 (1)
6294 *
6295 * (1) On STM32WB series, parameter not available on devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx.
6296 * @param AWDThresholdsHighLow This parameter can be one of the following values:
6297 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
6298 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
6299 * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
6300 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
6301 */
LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow)6302 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
6303 {
6304 #if defined(ADC_SUPPORT_2_5_MSPS)
6305 /* Prevent unused argument(s) compilation warning */
6306 (void)(AWDy);
6307
6308 return (uint32_t)(READ_BIT(ADCx->TR,
6309 (AWDThresholdsHighLow | ADC_TR_LT))
6310 >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~(AWDThresholdsHighLow & ADC_TR_LT))
6311 );
6312 #else
6313 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
6314
6315 return (uint32_t)(READ_BIT(*preg,
6316 (AWDThresholdsHighLow | ADC_TR1_LT1))
6317 >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~(AWDThresholdsHighLow & ADC_TR1_LT1))
6318 );
6319 #endif /* ADC_SUPPORT_2_5_MSPS */
6320 }
6321
6322 /**
6323 * @}
6324 */
6325
6326 #if defined(ADC_SUPPORT_2_5_MSPS)
6327 /* Feature "ADC oversampling" not available on ADC peripheral of this STM32WB device */
6328 #else
6329 /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
6330 * @{
6331 */
6332
6333 /**
6334 * @brief Set ADC oversampling scope: ADC groups regular and-or injected
6335 * (availability of ADC group injected depends on STM32 families).
6336 * @note If both groups regular and injected are selected,
6337 * specify behavior of ADC group injected interrupting
6338 * group regular: when ADC group injected is triggered,
6339 * the oversampling on ADC group regular is either
6340 * temporary stopped and continued, or resumed from start
6341 * (oversampler buffer reset).
6342 * @note On this STM32 series, setting of this feature is conditioned to
6343 * ADC state:
6344 * ADC must be disabled or enabled without conversion on going
6345 * on either groups regular or injected.
6346 * @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope\n
6347 * CFGR2 JOVSE LL_ADC_SetOverSamplingScope\n
6348 * CFGR2 ROVSM LL_ADC_SetOverSamplingScope
6349 * @param ADCx ADC instance
6350 * @param OvsScope This parameter can be one of the following values:
6351 * @arg @ref LL_ADC_OVS_DISABLE
6352 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
6353 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED (1)
6354 * @arg @ref LL_ADC_OVS_GRP_INJECTED (1)
6355 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED (1)
6356 *
6357 * (1) On STM32WB series, parameter not available on devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx.
6358 * @retval None
6359 */
LL_ADC_SetOverSamplingScope(ADC_TypeDef * ADCx,uint32_t OvsScope)6360 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
6361 {
6362 #if defined(ADC_SUPPORT_2_5_MSPS)
6363 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_OVSE, OvsScope);
6364 #else
6365 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
6366 #endif /* ADC_SUPPORT_2_5_MSPS */
6367 }
6368
6369 /**
6370 * @brief Get ADC oversampling scope: ADC groups regular and-or injected
6371 * (availability of ADC group injected depends on STM32 families).
6372 * @note If both groups regular and injected are selected,
6373 * specify behavior of ADC group injected interrupting
6374 * group regular: when ADC group injected is triggered,
6375 * the oversampling on ADC group regular is either
6376 * temporary stopped and continued, or resumed from start
6377 * (oversampler buffer reset).
6378 * @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope\n
6379 * CFGR2 JOVSE LL_ADC_GetOverSamplingScope\n
6380 * CFGR2 ROVSM LL_ADC_GetOverSamplingScope
6381 * @param ADCx ADC instance
6382 * @retval Returned value can be one of the following values:
6383 * @arg @ref LL_ADC_OVS_DISABLE
6384 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
6385 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED (1)
6386 * @arg @ref LL_ADC_OVS_GRP_INJECTED (1)
6387 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED (1)
6388 *
6389 * (1) On STM32WB series, parameter not available on devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx.
6390 */
LL_ADC_GetOverSamplingScope(const ADC_TypeDef * ADCx)6391 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx)
6392 {
6393 #if defined(ADC_SUPPORT_2_5_MSPS)
6394 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE));
6395 #else
6396 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
6397 #endif /* ADC_SUPPORT_2_5_MSPS */
6398 }
6399
6400 /**
6401 * @brief Set ADC oversampling discontinuous mode (triggered mode)
6402 * on the selected ADC group.
6403 * @note Number of oversampled conversions are done either in:
6404 * - continuous mode (all conversions of oversampling ratio
6405 * are done from 1 trigger)
6406 * - discontinuous mode (each conversion of oversampling ratio
6407 * needs a trigger)
6408 * @note On this STM32 series, setting of this feature is conditioned to
6409 * ADC state:
6410 * ADC must be disabled or enabled without conversion on going
6411 * on group regular.
6412 * @note On this STM32 series, oversampling discontinuous mode
6413 * (triggered mode) can be used only when oversampling is
6414 * set on group regular only and in resumed mode.
6415 * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont
6416 * @param ADCx ADC instance
6417 * @param OverSamplingDiscont This parameter can be one of the following values:
6418 * @arg @ref LL_ADC_OVS_REG_CONT
6419 * @arg @ref LL_ADC_OVS_REG_DISCONT
6420 * @retval None
6421 */
LL_ADC_SetOverSamplingDiscont(ADC_TypeDef * ADCx,uint32_t OverSamplingDiscont)6422 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
6423 {
6424 #if defined(ADC_SUPPORT_2_5_MSPS)
6425 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TOVS, OverSamplingDiscont);
6426 #else
6427 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
6428 #endif /* ADC_SUPPORT_2_5_MSPS */
6429 }
6430
6431 /**
6432 * @brief Get ADC oversampling discontinuous mode (triggered mode)
6433 * on the selected ADC group.
6434 * @note Number of oversampled conversions are done either in:
6435 * - continuous mode (all conversions of oversampling ratio
6436 * are done from 1 trigger)
6437 * - discontinuous mode (each conversion of oversampling ratio
6438 * needs a trigger)
6439 * @rmtoll CFGR2 TROVS LL_ADC_GetOverSamplingDiscont
6440 * @param ADCx ADC instance
6441 * @retval Returned value can be one of the following values:
6442 * @arg @ref LL_ADC_OVS_REG_CONT
6443 * @arg @ref LL_ADC_OVS_REG_DISCONT
6444 */
LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef * ADCx)6445 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx)
6446 {
6447 #if defined(ADC_SUPPORT_2_5_MSPS)
6448 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS));
6449 #else
6450 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
6451 #endif /* ADC_SUPPORT_2_5_MSPS */
6452 }
6453
6454 /**
6455 * @brief Set ADC oversampling
6456 * (impacting both ADC groups regular and injected)
6457 * @note This function set the 2 items of oversampling configuration:
6458 * - ratio
6459 * - shift
6460 * @note On this STM32 series, setting of this feature is conditioned to
6461 * ADC state:
6462 * ADC must be disabled or enabled without conversion on going
6463 * on either groups regular or injected.
6464 * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n
6465 * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
6466 * @param ADCx ADC instance
6467 * @param Ratio This parameter can be one of the following values:
6468 * @arg @ref LL_ADC_OVS_RATIO_2
6469 * @arg @ref LL_ADC_OVS_RATIO_4
6470 * @arg @ref LL_ADC_OVS_RATIO_8
6471 * @arg @ref LL_ADC_OVS_RATIO_16
6472 * @arg @ref LL_ADC_OVS_RATIO_32
6473 * @arg @ref LL_ADC_OVS_RATIO_64
6474 * @arg @ref LL_ADC_OVS_RATIO_128
6475 * @arg @ref LL_ADC_OVS_RATIO_256
6476 * @param Shift This parameter can be one of the following values:
6477 * @arg @ref LL_ADC_OVS_SHIFT_NONE
6478 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
6479 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
6480 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
6481 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
6482 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
6483 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
6484 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
6485 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
6486 * @retval None
6487 */
LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef * ADCx,uint32_t Ratio,uint32_t Shift)6488 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
6489 {
6490 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
6491 }
6492
6493 /**
6494 * @brief Get ADC oversampling ratio
6495 * (impacting both ADC groups regular and injected)
6496 * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
6497 * @param ADCx ADC instance
6498 * @retval Ratio This parameter can be one of the following values:
6499 * @arg @ref LL_ADC_OVS_RATIO_2
6500 * @arg @ref LL_ADC_OVS_RATIO_4
6501 * @arg @ref LL_ADC_OVS_RATIO_8
6502 * @arg @ref LL_ADC_OVS_RATIO_16
6503 * @arg @ref LL_ADC_OVS_RATIO_32
6504 * @arg @ref LL_ADC_OVS_RATIO_64
6505 * @arg @ref LL_ADC_OVS_RATIO_128
6506 * @arg @ref LL_ADC_OVS_RATIO_256
6507 */
LL_ADC_GetOverSamplingRatio(const ADC_TypeDef * ADCx)6508 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx)
6509 {
6510 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
6511 }
6512
6513 /**
6514 * @brief Get ADC oversampling shift
6515 * (impacting both ADC groups regular and injected)
6516 * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
6517 * @param ADCx ADC instance
6518 * @retval Shift This parameter can be one of the following values:
6519 * @arg @ref LL_ADC_OVS_SHIFT_NONE
6520 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
6521 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
6522 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
6523 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
6524 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
6525 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
6526 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
6527 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
6528 */
LL_ADC_GetOverSamplingShift(const ADC_TypeDef * ADCx)6529 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx)
6530 {
6531 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
6532 }
6533
6534 /**
6535 * @}
6536 */
6537
6538 #endif /* ADC_SUPPORT_2_5_MSPS */
6539 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
6540 * @{
6541 */
6542
6543 #if defined(ADC_SUPPORT_2_5_MSPS)
6544 /* Feature "ADC deep power down" not available on ADC peripheral of this STM32WB device */
6545 #else
6546 /**
6547 * @brief Put ADC instance in deep power down state.
6548 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
6549 * state, the internal analog calibration is lost. After exiting from
6550 * deep power down, calibration must be relaunched or calibration factor
6551 * (preliminarily saved) must be set back into calibration register.
6552 * @note On this STM32 series, setting of this feature is conditioned to
6553 * ADC state:
6554 * ADC must be ADC disabled.
6555 * @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown
6556 * @param ADCx ADC instance
6557 * @retval None
6558 */
LL_ADC_EnableDeepPowerDown(ADC_TypeDef * ADCx)6559 __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
6560 {
6561 /* Note: Write register with some additional bits forced to state reset */
6562 /* instead of modifying only the selected bit for this function, */
6563 /* to not interfere with bits with HW property "rs". */
6564 MODIFY_REG(ADCx->CR,
6565 ADC_CR_BITS_PROPERTY_RS,
6566 ADC_CR_DEEPPWD);
6567 }
6568
6569 /**
6570 * @brief Disable ADC deep power down mode.
6571 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
6572 * state, the internal analog calibration is lost. After exiting from
6573 * deep power down, calibration must be relaunched or calibration factor
6574 * (preliminarily saved) must be set back into calibration register.
6575 * @note On this STM32 series, setting of this feature is conditioned to
6576 * ADC state:
6577 * ADC must be ADC disabled.
6578 * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
6579 * @param ADCx ADC instance
6580 * @retval None
6581 */
LL_ADC_DisableDeepPowerDown(ADC_TypeDef * ADCx)6582 __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
6583 {
6584 /* Note: Write register with some additional bits forced to state reset */
6585 /* instead of modifying only the selected bit for this function, */
6586 /* to not interfere with bits with HW property "rs". */
6587 CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
6588 }
6589
6590 /**
6591 * @brief Get the selected ADC instance deep power down state.
6592 * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
6593 * @param ADCx ADC instance
6594 * @retval 0: deep power down is disabled, 1: deep power down is enabled.
6595 */
LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef * ADCx)6596 __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx)
6597 {
6598 return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
6599 }
6600 #endif /* ADC_SUPPORT_2_5_MSPS */
6601
6602 /**
6603 * @brief Enable ADC instance internal voltage regulator.
6604 * @note On this STM32 series, after ADC internal voltage regulator enable,
6605 * a delay for ADC internal voltage regulator stabilization
6606 * is required before performing a ADC calibration or ADC enable.
6607 * Refer to device datasheet, parameter tADCVREG_STUP.
6608 * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
6609 * @note On this STM32 series, setting of this feature is conditioned to
6610 * ADC state:
6611 * ADC must be ADC disabled.
6612 * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
6613 * @param ADCx ADC instance
6614 * @retval None
6615 */
LL_ADC_EnableInternalRegulator(ADC_TypeDef * ADCx)6616 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
6617 {
6618 /* Note: Write register with some additional bits forced to state reset */
6619 /* instead of modifying only the selected bit for this function, */
6620 /* to not interfere with bits with HW property "rs". */
6621 MODIFY_REG(ADCx->CR,
6622 ADC_CR_BITS_PROPERTY_RS,
6623 ADC_CR_ADVREGEN);
6624 }
6625
6626 /**
6627 * @brief Disable ADC internal voltage regulator.
6628 * @note On this STM32 series, setting of this feature is conditioned to
6629 * ADC state:
6630 * ADC must be ADC disabled.
6631 * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
6632 * @param ADCx ADC instance
6633 * @retval None
6634 */
LL_ADC_DisableInternalRegulator(ADC_TypeDef * ADCx)6635 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
6636 {
6637 CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
6638 }
6639
6640 /**
6641 * @brief Get the selected ADC instance internal voltage regulator state.
6642 * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
6643 * @param ADCx ADC instance
6644 * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
6645 */
LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef * ADCx)6646 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx)
6647 {
6648 return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
6649 }
6650
6651 /**
6652 * @brief Enable the selected ADC instance.
6653 * @note On this STM32 series, after ADC enable, a delay for
6654 * ADC internal analog stabilization is required before performing a
6655 * ADC conversion start.
6656 * Refer to device datasheet, parameter tSTAB.
6657 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6658 * is enabled and when conversion clock is active.
6659 * (not only core clock: this ADC has a dual clock domain)
6660 * @note On this STM32 series, setting of this feature is conditioned to
6661 * ADC state:
6662 * ADC must be ADC disabled and ADC internal voltage regulator enabled.
6663 * @rmtoll CR ADEN LL_ADC_Enable
6664 * @param ADCx ADC instance
6665 * @retval None
6666 */
LL_ADC_Enable(ADC_TypeDef * ADCx)6667 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
6668 {
6669 /* Note: Write register with some additional bits forced to state reset */
6670 /* instead of modifying only the selected bit for this function, */
6671 /* to not interfere with bits with HW property "rs". */
6672 MODIFY_REG(ADCx->CR,
6673 ADC_CR_BITS_PROPERTY_RS,
6674 ADC_CR_ADEN);
6675 }
6676
6677 /**
6678 * @brief Disable the selected ADC instance.
6679 * @note On this STM32 series, setting of this feature is conditioned to
6680 * ADC state:
6681 * ADC must be not disabled. Must be enabled without conversion on going
6682 * on either groups regular or injected.
6683 * @rmtoll CR ADDIS LL_ADC_Disable
6684 * @param ADCx ADC instance
6685 * @retval None
6686 */
LL_ADC_Disable(ADC_TypeDef * ADCx)6687 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
6688 {
6689 /* Note: Write register with some additional bits forced to state reset */
6690 /* instead of modifying only the selected bit for this function, */
6691 /* to not interfere with bits with HW property "rs". */
6692 MODIFY_REG(ADCx->CR,
6693 ADC_CR_BITS_PROPERTY_RS,
6694 ADC_CR_ADDIS);
6695 }
6696
6697 /**
6698 * @brief Get the selected ADC instance enable state.
6699 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6700 * is enabled and when conversion clock is active.
6701 * (not only core clock: this ADC has a dual clock domain)
6702 * @rmtoll CR ADEN LL_ADC_IsEnabled
6703 * @param ADCx ADC instance
6704 * @retval 0: ADC is disabled, 1: ADC is enabled.
6705 */
LL_ADC_IsEnabled(const ADC_TypeDef * ADCx)6706 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx)
6707 {
6708 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
6709 }
6710
6711 /**
6712 * @brief Get the selected ADC instance disable state.
6713 * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
6714 * @param ADCx ADC instance
6715 * @retval 0: no ADC disable command on going.
6716 */
LL_ADC_IsDisableOngoing(const ADC_TypeDef * ADCx)6717 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx)
6718 {
6719 return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
6720 }
6721
6722 #if defined(ADC_SUPPORT_2_5_MSPS)
6723 /**
6724 * @brief Start ADC calibration in the mode single-ended
6725 * or differential (for devices with differential mode available).
6726 * @note On this STM32 series, a minimum number of ADC clock cycles
6727 * are required between ADC end of calibration and ADC enable.
6728 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
6729 * @note For devices with differential mode available:
6730 * Calibration of offset is specific to each of
6731 * single-ended and differential modes
6732 * (calibration run must be performed for each of these
6733 * differential modes, if used afterwards and if the application
6734 * requires their calibration).
6735 * @note On this STM32 series, setting of this feature is conditioned to
6736 * ADC state:
6737 * ADC must be ADC disabled.
6738 * @note In case of usage of feature auto power-off:
6739 * This mode must be disabled during calibration
6740 * Refer to function @ref LL_ADC_SetLowPowerMode().
6741 * @rmtoll CR ADCAL LL_ADC_StartCalibration\n
6742 * CR ADCALDIF LL_ADC_StartCalibration
6743 * @param ADCx ADC instance
6744 * @retval None
6745 */
LL_ADC_StartCalibration(ADC_TypeDef * ADCx)6746 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx)
6747 {
6748 /* Note: Write register with some additional bits forced to state reset */
6749 /* instead of modifying only the selected bit for this function, */
6750 /* to not interfere with bits with HW property "rs". */
6751 MODIFY_REG(ADCx->CR,
6752 ADC_CR_BITS_PROPERTY_RS,
6753 ADC_CR_ADCAL);
6754 }
6755 #else
6756 /**
6757 * @brief Start ADC calibration in the mode single-ended
6758 * or differential (for devices with differential mode available).
6759 * @note On this STM32 series, a minimum number of ADC clock cycles
6760 * are required between ADC end of calibration and ADC enable.
6761 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
6762 * @note For devices with differential mode available:
6763 * Calibration of offset is specific to each of
6764 * single-ended and differential modes
6765 * (calibration run must be performed for each of these
6766 * differential modes, if used afterwards and if the application
6767 * requires their calibration).
6768 * @note On this STM32 series, setting of this feature is conditioned to
6769 * ADC state:
6770 * ADC must be ADC disabled.
6771 * @rmtoll CR ADCAL LL_ADC_StartCalibration\n
6772 * CR ADCALDIF LL_ADC_StartCalibration
6773 * @param ADCx ADC instance
6774 * @param SingleDiff This parameter can be one of the following values:
6775 * @arg @ref LL_ADC_SINGLE_ENDED
6776 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
6777 * @retval None
6778 */
LL_ADC_StartCalibration(ADC_TypeDef * ADCx,uint32_t SingleDiff)6779 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)
6780 {
6781 /* Note: Write register with some additional bits forced to state reset */
6782 /* instead of modifying only the selected bit for this function, */
6783 /* to not interfere with bits with HW property "rs". */
6784 MODIFY_REG(ADCx->CR,
6785 ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
6786 ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
6787 }
6788 #endif /* ADC_SUPPORT_2_5_MSPS */
6789
6790 /**
6791 * @brief Get ADC calibration state.
6792 * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
6793 * @param ADCx ADC instance
6794 * @retval 0: calibration complete, 1: calibration in progress.
6795 */
LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef * ADCx)6796 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx)
6797 {
6798 return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
6799 }
6800
6801 /**
6802 * @}
6803 */
6804
6805 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
6806 * @{
6807 */
6808
6809 /**
6810 * @brief Start ADC group regular conversion.
6811 * @note On this STM32 series, this function is relevant for both
6812 * internal trigger (SW start) and external trigger:
6813 * - If ADC trigger has been set to software start, ADC conversion
6814 * starts immediately.
6815 * - If ADC trigger has been set to external trigger, ADC conversion
6816 * will start at next trigger event (on the selected trigger edge)
6817 * following the ADC start conversion command.
6818 * @note On this STM32 series, setting of this feature is conditioned to
6819 * ADC state:
6820 * ADC must be enabled without conversion on going on group regular,
6821 * without conversion stop command on going on group regular,
6822 * without ADC disable command on going.
6823 * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
6824 * @param ADCx ADC instance
6825 * @retval None
6826 */
LL_ADC_REG_StartConversion(ADC_TypeDef * ADCx)6827 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
6828 {
6829 /* Note: Write register with some additional bits forced to state reset */
6830 /* instead of modifying only the selected bit for this function, */
6831 /* to not interfere with bits with HW property "rs". */
6832 MODIFY_REG(ADCx->CR,
6833 ADC_CR_BITS_PROPERTY_RS,
6834 ADC_CR_ADSTART);
6835 }
6836
6837 /**
6838 * @brief Stop ADC group regular conversion.
6839 * @note On this STM32 series, setting of this feature is conditioned to
6840 * ADC state:
6841 * ADC must be enabled with conversion on going on group regular,
6842 * without ADC disable command on going.
6843 * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
6844 * @param ADCx ADC instance
6845 * @retval None
6846 */
LL_ADC_REG_StopConversion(ADC_TypeDef * ADCx)6847 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
6848 {
6849 /* Note: Write register with some additional bits forced to state reset */
6850 /* instead of modifying only the selected bit for this function, */
6851 /* to not interfere with bits with HW property "rs". */
6852 MODIFY_REG(ADCx->CR,
6853 ADC_CR_BITS_PROPERTY_RS,
6854 ADC_CR_ADSTP);
6855 }
6856
6857 /**
6858 * @brief Get ADC group regular conversion state.
6859 * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
6860 * @param ADCx ADC instance
6861 * @retval 0: no conversion is on going on ADC group regular.
6862 */
LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef * ADCx)6863 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx)
6864 {
6865 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
6866 }
6867
6868 /**
6869 * @brief Get ADC group regular command of conversion stop state
6870 * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
6871 * @param ADCx ADC instance
6872 * @retval 0: no command of conversion stop is on going on ADC group regular.
6873 */
LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef * ADCx)6874 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
6875 {
6876 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
6877 }
6878
6879 /**
6880 * @brief Get ADC group regular conversion data, range fit for
6881 * all ADC configurations: all ADC resolutions and
6882 * all oversampling increased data width (for devices
6883 * with feature oversampling).
6884 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
6885 * @param ADCx ADC instance
6886 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
6887 */
LL_ADC_REG_ReadConversionData32(const ADC_TypeDef * ADCx)6888 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx)
6889 {
6890 return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6891 }
6892
6893 /**
6894 * @brief Get ADC group regular conversion data, range fit for
6895 * ADC resolution 12 bits.
6896 * @note For devices with feature oversampling: Oversampling
6897 * can increase data width, function for extended range
6898 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6899 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
6900 * @param ADCx ADC instance
6901 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
6902 */
LL_ADC_REG_ReadConversionData12(const ADC_TypeDef * ADCx)6903 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx)
6904 {
6905 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6906 }
6907
6908 /**
6909 * @brief Get ADC group regular conversion data, range fit for
6910 * ADC resolution 10 bits.
6911 * @note For devices with feature oversampling: Oversampling
6912 * can increase data width, function for extended range
6913 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6914 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
6915 * @param ADCx ADC instance
6916 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
6917 */
LL_ADC_REG_ReadConversionData10(const ADC_TypeDef * ADCx)6918 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx)
6919 {
6920 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6921 }
6922
6923 /**
6924 * @brief Get ADC group regular conversion data, range fit for
6925 * ADC resolution 8 bits.
6926 * @note For devices with feature oversampling: Oversampling
6927 * can increase data width, function for extended range
6928 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6929 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
6930 * @param ADCx ADC instance
6931 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
6932 */
LL_ADC_REG_ReadConversionData8(const ADC_TypeDef * ADCx)6933 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx)
6934 {
6935 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6936 }
6937
6938 /**
6939 * @brief Get ADC group regular conversion data, range fit for
6940 * ADC resolution 6 bits.
6941 * @note For devices with feature oversampling: Oversampling
6942 * can increase data width, function for extended range
6943 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6944 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
6945 * @param ADCx ADC instance
6946 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
6947 */
LL_ADC_REG_ReadConversionData6(const ADC_TypeDef * ADCx)6948 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(const ADC_TypeDef *ADCx)
6949 {
6950 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6951 }
6952
6953 /**
6954 * @}
6955 */
6956
6957 #if defined(ADC_SUPPORT_2_5_MSPS)
6958 /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
6959 #else
6960 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
6961 * @{
6962 */
6963
6964 /**
6965 * @brief Start ADC group injected conversion.
6966 * @note On this STM32 series, this function is relevant for both
6967 * internal trigger (SW start) and external trigger:
6968 * - If ADC trigger has been set to software start, ADC conversion
6969 * starts immediately.
6970 * - If ADC trigger has been set to external trigger, ADC conversion
6971 * will start at next trigger event (on the selected trigger edge)
6972 * following the ADC start conversion command.
6973 * @note On this STM32 series, setting of this feature is conditioned to
6974 * ADC state:
6975 * ADC must be enabled without conversion on going on group injected,
6976 * without conversion stop command on going on group injected,
6977 * without ADC disable command on going.
6978 * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion
6979 * @param ADCx ADC instance
6980 * @retval None
6981 */
LL_ADC_INJ_StartConversion(ADC_TypeDef * ADCx)6982 __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
6983 {
6984 /* Note: Write register with some additional bits forced to state reset */
6985 /* instead of modifying only the selected bit for this function, */
6986 /* to not interfere with bits with HW property "rs". */
6987 MODIFY_REG(ADCx->CR,
6988 ADC_CR_BITS_PROPERTY_RS,
6989 ADC_CR_JADSTART);
6990 }
6991
6992 /**
6993 * @brief Stop ADC group injected conversion.
6994 * @note On this STM32 series, setting of this feature is conditioned to
6995 * ADC state:
6996 * ADC must be enabled with conversion on going on group injected,
6997 * without ADC disable command on going.
6998 * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
6999 * @param ADCx ADC instance
7000 * @retval None
7001 */
LL_ADC_INJ_StopConversion(ADC_TypeDef * ADCx)7002 __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
7003 {
7004 /* Note: Write register with some additional bits forced to state reset */
7005 /* instead of modifying only the selected bit for this function, */
7006 /* to not interfere with bits with HW property "rs". */
7007 MODIFY_REG(ADCx->CR,
7008 ADC_CR_BITS_PROPERTY_RS,
7009 ADC_CR_JADSTP);
7010 }
7011
7012 /**
7013 * @brief Get ADC group injected conversion state.
7014 * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
7015 * @param ADCx ADC instance
7016 * @retval 0: no conversion is on going on ADC group injected.
7017 */
LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef * ADCx)7018 __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx)
7019 {
7020 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
7021 }
7022
7023 /**
7024 * @brief Get ADC group injected command of conversion stop state
7025 * @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
7026 * @param ADCx ADC instance
7027 * @retval 0: no command of conversion stop is on going on ADC group injected.
7028 */
LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef * ADCx)7029 __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
7030 {
7031 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
7032 }
7033
7034 /**
7035 * @brief Get ADC group injected conversion data, range fit for
7036 * all ADC configurations: all ADC resolutions and
7037 * all oversampling increased data width (for devices
7038 * with feature oversampling).
7039 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
7040 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
7041 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
7042 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
7043 * @param ADCx ADC instance
7044 * @param Rank This parameter can be one of the following values:
7045 * @arg @ref LL_ADC_INJ_RANK_1
7046 * @arg @ref LL_ADC_INJ_RANK_2
7047 * @arg @ref LL_ADC_INJ_RANK_3
7048 * @arg @ref LL_ADC_INJ_RANK_4
7049 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
7050 */
LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef * ADCx,uint32_t Rank)7051 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef *ADCx, uint32_t Rank)
7052 {
7053 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7054
7055 return (uint32_t)(READ_BIT(*preg,
7056 ADC_JDR1_JDATA)
7057 );
7058 }
7059
7060 /**
7061 * @brief Get ADC group injected conversion data, range fit for
7062 * ADC resolution 12 bits.
7063 * @note For devices with feature oversampling: Oversampling
7064 * can increase data width, function for extended range
7065 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7066 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
7067 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
7068 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
7069 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
7070 * @param ADCx ADC instance
7071 * @param Rank This parameter can be one of the following values:
7072 * @arg @ref LL_ADC_INJ_RANK_1
7073 * @arg @ref LL_ADC_INJ_RANK_2
7074 * @arg @ref LL_ADC_INJ_RANK_3
7075 * @arg @ref LL_ADC_INJ_RANK_4
7076 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
7077 */
LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef * ADCx,uint32_t Rank)7078 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef *ADCx, uint32_t Rank)
7079 {
7080 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7081
7082 return (uint16_t)(READ_BIT(*preg,
7083 ADC_JDR1_JDATA)
7084 );
7085 }
7086
7087 /**
7088 * @brief Get ADC group injected conversion data, range fit for
7089 * ADC resolution 10 bits.
7090 * @note For devices with feature oversampling: Oversampling
7091 * can increase data width, function for extended range
7092 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7093 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
7094 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
7095 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
7096 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
7097 * @param ADCx ADC instance
7098 * @param Rank This parameter can be one of the following values:
7099 * @arg @ref LL_ADC_INJ_RANK_1
7100 * @arg @ref LL_ADC_INJ_RANK_2
7101 * @arg @ref LL_ADC_INJ_RANK_3
7102 * @arg @ref LL_ADC_INJ_RANK_4
7103 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
7104 */
LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef * ADCx,uint32_t Rank)7105 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef *ADCx, uint32_t Rank)
7106 {
7107 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7108
7109 return (uint16_t)(READ_BIT(*preg,
7110 ADC_JDR1_JDATA)
7111 );
7112 }
7113
7114 /**
7115 * @brief Get ADC group injected conversion data, range fit for
7116 * ADC resolution 8 bits.
7117 * @note For devices with feature oversampling: Oversampling
7118 * can increase data width, function for extended range
7119 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7120 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
7121 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
7122 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
7123 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
7124 * @param ADCx ADC instance
7125 * @param Rank This parameter can be one of the following values:
7126 * @arg @ref LL_ADC_INJ_RANK_1
7127 * @arg @ref LL_ADC_INJ_RANK_2
7128 * @arg @ref LL_ADC_INJ_RANK_3
7129 * @arg @ref LL_ADC_INJ_RANK_4
7130 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
7131 */
LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef * ADCx,uint32_t Rank)7132 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef *ADCx, uint32_t Rank)
7133 {
7134 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7135
7136 return (uint8_t)(READ_BIT(*preg,
7137 ADC_JDR1_JDATA)
7138 );
7139 }
7140
7141 /**
7142 * @brief Get ADC group injected conversion data, range fit for
7143 * ADC resolution 6 bits.
7144 * @note For devices with feature oversampling: Oversampling
7145 * can increase data width, function for extended range
7146 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7147 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
7148 * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
7149 * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
7150 * JDR4 JDATA LL_ADC_INJ_ReadConversionData6
7151 * @param ADCx ADC instance
7152 * @param Rank This parameter can be one of the following values:
7153 * @arg @ref LL_ADC_INJ_RANK_1
7154 * @arg @ref LL_ADC_INJ_RANK_2
7155 * @arg @ref LL_ADC_INJ_RANK_3
7156 * @arg @ref LL_ADC_INJ_RANK_4
7157 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
7158 */
LL_ADC_INJ_ReadConversionData6(const ADC_TypeDef * ADCx,uint32_t Rank)7159 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(const ADC_TypeDef *ADCx, uint32_t Rank)
7160 {
7161 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7162
7163 return (uint8_t)(READ_BIT(*preg,
7164 ADC_JDR1_JDATA)
7165 );
7166 }
7167
7168 /**
7169 * @}
7170 */
7171
7172 #endif /* ADC_SUPPORT_2_5_MSPS */
7173 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
7174 * @{
7175 */
7176
7177 /**
7178 * @brief Get flag ADC ready.
7179 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
7180 * is enabled and when conversion clock is active.
7181 * (not only core clock: this ADC has a dual clock domain)
7182 * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
7183 * @param ADCx ADC instance
7184 * @retval State of bit (1 or 0).
7185 */
LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef * ADCx)7186 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx)
7187 {
7188 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
7189 }
7190
7191 #if defined(ADC_SUPPORT_2_5_MSPS)
7192 /**
7193 * @brief Get flag ADC channel configuration ready.
7194 * @note Duration of ADC channel configuration ready: CCRDY handshake
7195 * requires 1APB + 2 ADC + 3 APB cycles after the channel configuration
7196 * has been changed.
7197 * @rmtoll ISR CCRDY LL_ADC_IsActiveFlag_CCRDY
7198 * @param ADCx ADC instance
7199 * @retval State of bit (1 or 0).
7200 */
LL_ADC_IsActiveFlag_CCRDY(const ADC_TypeDef * ADCx)7201 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_CCRDY(const ADC_TypeDef *ADCx)
7202 {
7203 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL);
7204 }
7205
7206 #else
7207 #endif /* ADC_SUPPORT_2_5_MSPS */
7208 /**
7209 * @brief Get flag ADC group regular end of unitary conversion.
7210 * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
7211 * @param ADCx ADC instance
7212 * @retval State of bit (1 or 0).
7213 */
LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef * ADCx)7214 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx)
7215 {
7216 return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
7217 }
7218
7219 /**
7220 * @brief Get flag ADC group regular end of sequence conversions.
7221 * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
7222 * @param ADCx ADC instance
7223 * @retval State of bit (1 or 0).
7224 */
LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef * ADCx)7225 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx)
7226 {
7227 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
7228 }
7229
7230 /**
7231 * @brief Get flag ADC group regular overrun.
7232 * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
7233 * @param ADCx ADC instance
7234 * @retval State of bit (1 or 0).
7235 */
LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef * ADCx)7236 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx)
7237 {
7238 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
7239 }
7240
7241 /**
7242 * @brief Get flag ADC group regular end of sampling phase.
7243 * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
7244 * @param ADCx ADC instance
7245 * @retval State of bit (1 or 0).
7246 */
LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef * ADCx)7247 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx)
7248 {
7249 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
7250 }
7251
7252 #if defined(ADC_SUPPORT_2_5_MSPS)
7253 /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
7254 #else
7255 /**
7256 * @brief Get flag ADC group injected end of unitary conversion.
7257 * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC
7258 * @param ADCx ADC instance
7259 * @retval State of bit (1 or 0).
7260 */
LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef * ADCx)7261 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef *ADCx)
7262 {
7263 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);
7264 }
7265
7266 /**
7267 * @brief Get flag ADC group injected end of sequence conversions.
7268 * @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS
7269 * @param ADCx ADC instance
7270 * @retval State of bit (1 or 0).
7271 */
LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef * ADCx)7272 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef *ADCx)
7273 {
7274 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);
7275 }
7276
7277 /**
7278 * @brief Get flag ADC group injected contexts queue overflow.
7279 * @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF
7280 * @param ADCx ADC instance
7281 * @retval State of bit (1 or 0).
7282 */
LL_ADC_IsActiveFlag_JQOVF(const ADC_TypeDef * ADCx)7283 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(const ADC_TypeDef *ADCx)
7284 {
7285 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);
7286 }
7287
7288 #endif /* ADC_SUPPORT_2_5_MSPS */
7289 /**
7290 * @brief Get flag ADC analog watchdog 1 flag
7291 * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
7292 * @param ADCx ADC instance
7293 * @retval State of bit (1 or 0).
7294 */
LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef * ADCx)7295 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx)
7296 {
7297 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
7298 }
7299
7300 /**
7301 * @brief Get flag ADC analog watchdog 2.
7302 * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
7303 * @param ADCx ADC instance
7304 * @retval State of bit (1 or 0).
7305 */
LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef * ADCx)7306 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx)
7307 {
7308 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
7309 }
7310
7311 /**
7312 * @brief Get flag ADC analog watchdog 3.
7313 * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
7314 * @param ADCx ADC instance
7315 * @retval State of bit (1 or 0).
7316 */
LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef * ADCx)7317 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx)
7318 {
7319 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
7320 }
7321
7322 #if defined(ADC_SUPPORT_2_5_MSPS)
7323 /**
7324 * @brief Get flag ADC end of calibration.
7325 * @rmtoll ISR EOCAL LL_ADC_IsActiveFlag_EOCAL
7326 * @param ADCx ADC instance
7327 * @retval State of bit (1 or 0).
7328 */
LL_ADC_IsActiveFlag_EOCAL(const ADC_TypeDef * ADCx)7329 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCAL(const ADC_TypeDef *ADCx)
7330 {
7331 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOCAL) == (LL_ADC_FLAG_EOCAL)) ? 1UL : 0UL);
7332 }
7333
7334 #endif /* ADC_SUPPORT_2_5_MSPS */
7335 /**
7336 * @brief Clear flag ADC ready.
7337 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
7338 * is enabled and when conversion clock is active.
7339 * (not only core clock: this ADC has a dual clock domain)
7340 * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
7341 * @param ADCx ADC instance
7342 * @retval None
7343 */
LL_ADC_ClearFlag_ADRDY(ADC_TypeDef * ADCx)7344 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
7345 {
7346 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
7347 }
7348
7349 #if defined(ADC_SUPPORT_2_5_MSPS)
7350 /**
7351 * @brief Clear flag ADC channel configuration ready.
7352 * @rmtoll ISR CCRDY LL_ADC_ClearFlag_CCRDY
7353 * @param ADCx ADC instance
7354 * @retval State of bit (1 or 0).
7355 */
LL_ADC_ClearFlag_CCRDY(ADC_TypeDef * ADCx)7356 __STATIC_INLINE void LL_ADC_ClearFlag_CCRDY(ADC_TypeDef *ADCx)
7357 {
7358 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_CCRDY);
7359 }
7360
7361 #else
7362 #endif /* ADC_SUPPORT_2_5_MSPS */
7363 /**
7364 * @brief Clear flag ADC group regular end of unitary conversion.
7365 * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
7366 * @param ADCx ADC instance
7367 * @retval None
7368 */
LL_ADC_ClearFlag_EOC(ADC_TypeDef * ADCx)7369 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
7370 {
7371 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
7372 }
7373
7374 /**
7375 * @brief Clear flag ADC group regular end of sequence conversions.
7376 * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
7377 * @param ADCx ADC instance
7378 * @retval None
7379 */
LL_ADC_ClearFlag_EOS(ADC_TypeDef * ADCx)7380 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
7381 {
7382 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
7383 }
7384
7385 /**
7386 * @brief Clear flag ADC group regular overrun.
7387 * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
7388 * @param ADCx ADC instance
7389 * @retval None
7390 */
LL_ADC_ClearFlag_OVR(ADC_TypeDef * ADCx)7391 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
7392 {
7393 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
7394 }
7395
7396 /**
7397 * @brief Clear flag ADC group regular end of sampling phase.
7398 * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
7399 * @param ADCx ADC instance
7400 * @retval None
7401 */
LL_ADC_ClearFlag_EOSMP(ADC_TypeDef * ADCx)7402 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
7403 {
7404 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
7405 }
7406
7407 #if defined(ADC_SUPPORT_2_5_MSPS)
7408 /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
7409 #else
7410 /**
7411 * @brief Clear flag ADC group injected end of unitary conversion.
7412 * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC
7413 * @param ADCx ADC instance
7414 * @retval None
7415 */
LL_ADC_ClearFlag_JEOC(ADC_TypeDef * ADCx)7416 __STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
7417 {
7418 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
7419 }
7420
7421 /**
7422 * @brief Clear flag ADC group injected end of sequence conversions.
7423 * @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS
7424 * @param ADCx ADC instance
7425 * @retval None
7426 */
LL_ADC_ClearFlag_JEOS(ADC_TypeDef * ADCx)7427 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
7428 {
7429 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
7430 }
7431
7432 /**
7433 * @brief Clear flag ADC group injected contexts queue overflow.
7434 * @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF
7435 * @param ADCx ADC instance
7436 * @retval None
7437 */
LL_ADC_ClearFlag_JQOVF(ADC_TypeDef * ADCx)7438 __STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
7439 {
7440 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
7441 }
7442
7443 #endif /* ADC_SUPPORT_2_5_MSPS */
7444 /**
7445 * @brief Clear flag ADC analog watchdog 1.
7446 * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
7447 * @param ADCx ADC instance
7448 * @retval None
7449 */
LL_ADC_ClearFlag_AWD1(ADC_TypeDef * ADCx)7450 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
7451 {
7452 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
7453 }
7454
7455 /**
7456 * @brief Clear flag ADC analog watchdog 2.
7457 * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
7458 * @param ADCx ADC instance
7459 * @retval None
7460 */
LL_ADC_ClearFlag_AWD2(ADC_TypeDef * ADCx)7461 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
7462 {
7463 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
7464 }
7465
7466 /**
7467 * @brief Clear flag ADC analog watchdog 3.
7468 * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
7469 * @param ADCx ADC instance
7470 * @retval None
7471 */
LL_ADC_ClearFlag_AWD3(ADC_TypeDef * ADCx)7472 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
7473 {
7474 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
7475 }
7476
7477 #if defined(ADC_SUPPORT_2_5_MSPS)
7478 /**
7479 * @brief Clear flag ADC end of calibration.
7480 * @rmtoll ISR EOCAL LL_ADC_ClearFlag_EOCAL
7481 * @param ADCx ADC instance
7482 * @retval None
7483 */
LL_ADC_ClearFlag_EOCAL(ADC_TypeDef * ADCx)7484 __STATIC_INLINE void LL_ADC_ClearFlag_EOCAL(ADC_TypeDef *ADCx)
7485 {
7486 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOCAL);
7487 }
7488
7489 #endif /* ADC_SUPPORT_2_5_MSPS */
7490 /**
7491 * @}
7492 */
7493
7494 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
7495 * @{
7496 */
7497
7498 /**
7499 * @brief Enable ADC ready.
7500 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
7501 * @param ADCx ADC instance
7502 * @retval None
7503 */
LL_ADC_EnableIT_ADRDY(ADC_TypeDef * ADCx)7504 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
7505 {
7506 SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
7507 }
7508
7509 #if defined(ADC_SUPPORT_2_5_MSPS)
7510 /**
7511 * @brief Enable interruption ADC channel configuration ready.
7512 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_CCRDY
7513 * @param ADCx ADC instance
7514 * @retval State of bit (1 or 0).
7515 */
LL_ADC_EnableIT_CCRDY(ADC_TypeDef * ADCx)7516 __STATIC_INLINE void LL_ADC_EnableIT_CCRDY(ADC_TypeDef *ADCx)
7517 {
7518 SET_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY);
7519 }
7520
7521 #else
7522 #endif /* ADC_SUPPORT_2_5_MSPS */
7523 /**
7524 * @brief Enable interruption ADC group regular end of unitary conversion.
7525 * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
7526 * @param ADCx ADC instance
7527 * @retval None
7528 */
LL_ADC_EnableIT_EOC(ADC_TypeDef * ADCx)7529 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
7530 {
7531 SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
7532 }
7533
7534 /**
7535 * @brief Enable interruption ADC group regular end of sequence conversions.
7536 * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
7537 * @param ADCx ADC instance
7538 * @retval None
7539 */
LL_ADC_EnableIT_EOS(ADC_TypeDef * ADCx)7540 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
7541 {
7542 SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
7543 }
7544
7545 /**
7546 * @brief Enable ADC group regular interruption overrun.
7547 * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
7548 * @param ADCx ADC instance
7549 * @retval None
7550 */
LL_ADC_EnableIT_OVR(ADC_TypeDef * ADCx)7551 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
7552 {
7553 SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
7554 }
7555
7556 /**
7557 * @brief Enable interruption ADC group regular end of sampling.
7558 * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
7559 * @param ADCx ADC instance
7560 * @retval None
7561 */
LL_ADC_EnableIT_EOSMP(ADC_TypeDef * ADCx)7562 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
7563 {
7564 SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
7565 }
7566
7567 #if defined(ADC_SUPPORT_2_5_MSPS)
7568 /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
7569 #else
7570 /**
7571 * @brief Enable interruption ADC group injected end of unitary conversion.
7572 * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC
7573 * @param ADCx ADC instance
7574 * @retval None
7575 */
LL_ADC_EnableIT_JEOC(ADC_TypeDef * ADCx)7576 __STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
7577 {
7578 SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
7579 }
7580
7581 /**
7582 * @brief Enable interruption ADC group injected end of sequence conversions.
7583 * @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS
7584 * @param ADCx ADC instance
7585 * @retval None
7586 */
LL_ADC_EnableIT_JEOS(ADC_TypeDef * ADCx)7587 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
7588 {
7589 SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
7590 }
7591
7592 /**
7593 * @brief Enable interruption ADC group injected context queue overflow.
7594 * @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF
7595 * @param ADCx ADC instance
7596 * @retval None
7597 */
LL_ADC_EnableIT_JQOVF(ADC_TypeDef * ADCx)7598 __STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
7599 {
7600 SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
7601 }
7602
7603 #endif /* ADC_SUPPORT_2_5_MSPS */
7604 /**
7605 * @brief Enable interruption ADC analog watchdog 1.
7606 * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
7607 * @param ADCx ADC instance
7608 * @retval None
7609 */
LL_ADC_EnableIT_AWD1(ADC_TypeDef * ADCx)7610 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
7611 {
7612 SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
7613 }
7614
7615 /**
7616 * @brief Enable interruption ADC analog watchdog 2.
7617 * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
7618 * @param ADCx ADC instance
7619 * @retval None
7620 */
LL_ADC_EnableIT_AWD2(ADC_TypeDef * ADCx)7621 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
7622 {
7623 SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
7624 }
7625
7626 /**
7627 * @brief Enable interruption ADC analog watchdog 3.
7628 * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
7629 * @param ADCx ADC instance
7630 * @retval None
7631 */
LL_ADC_EnableIT_AWD3(ADC_TypeDef * ADCx)7632 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
7633 {
7634 SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
7635 }
7636
7637 #if defined(ADC_SUPPORT_2_5_MSPS)
7638 /**
7639 * @brief Enable interruption ADC end of calibration.
7640 * @rmtoll IER EOCALIE LL_ADC_EnableIT_EOCAL
7641 * @param ADCx ADC instance
7642 * @retval None
7643 */
LL_ADC_EnableIT_EOCAL(ADC_TypeDef * ADCx)7644 __STATIC_INLINE void LL_ADC_EnableIT_EOCAL(ADC_TypeDef *ADCx)
7645 {
7646 SET_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
7647 }
7648
7649 #endif /* ADC_SUPPORT_2_5_MSPS */
7650 /**
7651 * @brief Disable interruption ADC ready.
7652 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
7653 * @param ADCx ADC instance
7654 * @retval None
7655 */
LL_ADC_DisableIT_ADRDY(ADC_TypeDef * ADCx)7656 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
7657 {
7658 CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
7659 }
7660
7661 #if defined(ADC_SUPPORT_2_5_MSPS)
7662 /**
7663 * @brief Disable interruption ADC channel configuration ready.
7664 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_CCRDY
7665 * @param ADCx ADC instance
7666 * @retval State of bit (1 or 0).
7667 */
LL_ADC_DisableIT_CCRDY(ADC_TypeDef * ADCx)7668 __STATIC_INLINE void LL_ADC_DisableIT_CCRDY(ADC_TypeDef *ADCx)
7669 {
7670 CLEAR_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY);
7671 }
7672
7673 #else
7674 #endif /* ADC_SUPPORT_2_5_MSPS */
7675 /**
7676 * @brief Disable interruption ADC group regular end of unitary conversion.
7677 * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
7678 * @param ADCx ADC instance
7679 * @retval None
7680 */
LL_ADC_DisableIT_EOC(ADC_TypeDef * ADCx)7681 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
7682 {
7683 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
7684 }
7685
7686 /**
7687 * @brief Disable interruption ADC group regular end of sequence conversions.
7688 * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
7689 * @param ADCx ADC instance
7690 * @retval None
7691 */
LL_ADC_DisableIT_EOS(ADC_TypeDef * ADCx)7692 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
7693 {
7694 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
7695 }
7696
7697 /**
7698 * @brief Disable interruption ADC group regular overrun.
7699 * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
7700 * @param ADCx ADC instance
7701 * @retval None
7702 */
LL_ADC_DisableIT_OVR(ADC_TypeDef * ADCx)7703 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
7704 {
7705 CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
7706 }
7707
7708 /**
7709 * @brief Disable interruption ADC group regular end of sampling.
7710 * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
7711 * @param ADCx ADC instance
7712 * @retval None
7713 */
LL_ADC_DisableIT_EOSMP(ADC_TypeDef * ADCx)7714 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
7715 {
7716 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
7717 }
7718
7719 #if defined(ADC_SUPPORT_2_5_MSPS)
7720 /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
7721 #else
7722 /**
7723 * @brief Disable interruption ADC group regular end of unitary conversion.
7724 * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC
7725 * @param ADCx ADC instance
7726 * @retval None
7727 */
LL_ADC_DisableIT_JEOC(ADC_TypeDef * ADCx)7728 __STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
7729 {
7730 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
7731 }
7732
7733 /**
7734 * @brief Disable interruption ADC group injected end of sequence conversions.
7735 * @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS
7736 * @param ADCx ADC instance
7737 * @retval None
7738 */
LL_ADC_DisableIT_JEOS(ADC_TypeDef * ADCx)7739 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
7740 {
7741 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
7742 }
7743
7744 /**
7745 * @brief Disable interruption ADC group injected context queue overflow.
7746 * @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF
7747 * @param ADCx ADC instance
7748 * @retval None
7749 */
LL_ADC_DisableIT_JQOVF(ADC_TypeDef * ADCx)7750 __STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
7751 {
7752 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
7753 }
7754
7755 #endif /* ADC_SUPPORT_2_5_MSPS */
7756 /**
7757 * @brief Disable interruption ADC analog watchdog 1.
7758 * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
7759 * @param ADCx ADC instance
7760 * @retval None
7761 */
LL_ADC_DisableIT_AWD1(ADC_TypeDef * ADCx)7762 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
7763 {
7764 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
7765 }
7766
7767 /**
7768 * @brief Disable interruption ADC analog watchdog 2.
7769 * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
7770 * @param ADCx ADC instance
7771 * @retval None
7772 */
LL_ADC_DisableIT_AWD2(ADC_TypeDef * ADCx)7773 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
7774 {
7775 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
7776 }
7777
7778 /**
7779 * @brief Disable interruption ADC analog watchdog 3.
7780 * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
7781 * @param ADCx ADC instance
7782 * @retval None
7783 */
LL_ADC_DisableIT_AWD3(ADC_TypeDef * ADCx)7784 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
7785 {
7786 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
7787 }
7788
7789 #if defined(ADC_SUPPORT_2_5_MSPS)
7790 /**
7791 * @brief Disable interruption ADC end of calibration.
7792 * @rmtoll IER EOCALIE LL_ADC_DisableIT_EOCAL
7793 * @param ADCx ADC instance
7794 * @retval None
7795 */
LL_ADC_DisableIT_EOCAL(ADC_TypeDef * ADCx)7796 __STATIC_INLINE void LL_ADC_DisableIT_EOCAL(ADC_TypeDef *ADCx)
7797 {
7798 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
7799 }
7800
7801 #endif /* ADC_SUPPORT_2_5_MSPS */
7802 /**
7803 * @brief Get state of interruption ADC ready
7804 * (0: interrupt disabled, 1: interrupt enabled).
7805 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
7806 * @param ADCx ADC instance
7807 * @retval State of bit (1 or 0).
7808 */
LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef * ADCx)7809 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx)
7810 {
7811 return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
7812 }
7813
7814 #if defined(ADC_SUPPORT_2_5_MSPS)
7815 /**
7816 * @brief Get state of interruption ADC channel configuration ready.
7817 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_CCRDY
7818 * @param ADCx ADC instance
7819 * @retval State of bit (1 or 0).
7820 */
LL_ADC_IsEnabledIT_CCRDY(const ADC_TypeDef * ADCx)7821 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_CCRDY(const ADC_TypeDef *ADCx)
7822 {
7823 return ((READ_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL);
7824 }
7825
7826 #else
7827 #endif /* ADC_SUPPORT_2_5_MSPS */
7828 /**
7829 * @brief Get state of interruption ADC group regular end of unitary conversion
7830 * (0: interrupt disabled, 1: interrupt enabled).
7831 * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
7832 * @param ADCx ADC instance
7833 * @retval State of bit (1 or 0).
7834 */
LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef * ADCx)7835 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx)
7836 {
7837 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
7838 }
7839
7840 /**
7841 * @brief Get state of interruption ADC group regular end of sequence conversions
7842 * (0: interrupt disabled, 1: interrupt enabled).
7843 * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
7844 * @param ADCx ADC instance
7845 * @retval State of bit (1 or 0).
7846 */
LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef * ADCx)7847 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx)
7848 {
7849 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
7850 }
7851
7852 /**
7853 * @brief Get state of interruption ADC group regular overrun
7854 * (0: interrupt disabled, 1: interrupt enabled).
7855 * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
7856 * @param ADCx ADC instance
7857 * @retval State of bit (1 or 0).
7858 */
LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef * ADCx)7859 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx)
7860 {
7861 return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
7862 }
7863
7864 /**
7865 * @brief Get state of interruption ADC group regular end of sampling
7866 * (0: interrupt disabled, 1: interrupt enabled).
7867 * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
7868 * @param ADCx ADC instance
7869 * @retval State of bit (1 or 0).
7870 */
LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef * ADCx)7871 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx)
7872 {
7873 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
7874 }
7875
7876 #if defined(ADC_SUPPORT_2_5_MSPS)
7877 /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
7878 #else
7879 /**
7880 * @brief Get state of interruption ADC group injected end of unitary conversion
7881 * (0: interrupt disabled, 1: interrupt enabled).
7882 * @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC
7883 * @param ADCx ADC instance
7884 * @retval State of bit (1 or 0).
7885 */
LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef * ADCx)7886 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef *ADCx)
7887 {
7888 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);
7889 }
7890
7891 /**
7892 * @brief Get state of interruption ADC group injected end of sequence conversions
7893 * (0: interrupt disabled, 1: interrupt enabled).
7894 * @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS
7895 * @param ADCx ADC instance
7896 * @retval State of bit (1 or 0).
7897 */
LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef * ADCx)7898 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef *ADCx)
7899 {
7900 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);
7901 }
7902
7903 /**
7904 * @brief Get state of interruption ADC group injected context queue overflow interrupt state
7905 * (0: interrupt disabled, 1: interrupt enabled).
7906 * @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF
7907 * @param ADCx ADC instance
7908 * @retval State of bit (1 or 0).
7909 */
LL_ADC_IsEnabledIT_JQOVF(const ADC_TypeDef * ADCx)7910 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(const ADC_TypeDef *ADCx)
7911 {
7912 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL);
7913 }
7914
7915 #endif /* ADC_SUPPORT_2_5_MSPS */
7916 /**
7917 * @brief Get state of interruption ADC analog watchdog 1
7918 * (0: interrupt disabled, 1: interrupt enabled).
7919 * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
7920 * @param ADCx ADC instance
7921 * @retval State of bit (1 or 0).
7922 */
LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef * ADCx)7923 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx)
7924 {
7925 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
7926 }
7927
7928 /**
7929 * @brief Get state of interruption Get ADC analog watchdog 2
7930 * (0: interrupt disabled, 1: interrupt enabled).
7931 * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
7932 * @param ADCx ADC instance
7933 * @retval State of bit (1 or 0).
7934 */
LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef * ADCx)7935 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx)
7936 {
7937 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
7938 }
7939
7940 /**
7941 * @brief Get state of interruption Get ADC analog watchdog 3
7942 * (0: interrupt disabled, 1: interrupt enabled).
7943 * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
7944 * @param ADCx ADC instance
7945 * @retval State of bit (1 or 0).
7946 */
LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef * ADCx)7947 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx)
7948 {
7949 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
7950 }
7951
7952 #if defined(ADC_SUPPORT_2_5_MSPS)
7953 /**
7954 * @brief Get state of interruption ADC end of calibration
7955 * (0: interrupt disabled, 1: interrupt enabled).
7956 * @rmtoll IER EOCALIE LL_ADC_IsEnabledIT_EOCAL
7957 * @param ADCx ADC instance
7958 * @retval State of bit (1 or 0).
7959 */
LL_ADC_IsEnabledIT_EOCAL(const ADC_TypeDef * ADCx)7960 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(const ADC_TypeDef *ADCx)
7961 {
7962 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOCAL) == (LL_ADC_IT_EOCAL)) ? 1UL : 0UL);
7963 }
7964
7965 #endif /* ADC_SUPPORT_2_5_MSPS */
7966 /**
7967 * @}
7968 */
7969
7970 #if defined(USE_FULL_LL_DRIVER)
7971 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
7972 * @{
7973 */
7974
7975 /* Initialization of some features of ADC common parameters and multimode */
7976 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
7977 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
7978 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
7979
7980 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
7981 /* (availability of ADC group injected depends on STM32 families) */
7982 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
7983
7984 /* Initialization of some features of ADC instance */
7985 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *ADC_InitStruct);
7986 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
7987
7988 /* Initialization of some features of ADC instance and ADC group regular */
7989 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
7990 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
7991
7992 #if defined(ADC_SUPPORT_2_5_MSPS)
7993 /* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
7994 #else
7995 /* Initialization of some features of ADC instance and ADC group injected */
7996 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, const LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
7997 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
7998
7999 #endif /* ADC_SUPPORT_2_5_MSPS */
8000 /**
8001 * @}
8002 */
8003 #endif /* USE_FULL_LL_DRIVER */
8004
8005 /**
8006 * @}
8007 */
8008
8009 /**
8010 * @}
8011 */
8012
8013 #endif /* ADC1 */
8014
8015 /**
8016 * @}
8017 */
8018
8019 #ifdef __cplusplus
8020 }
8021 #endif
8022
8023 #endif /* STM32WBxx_LL_ADC_H */
8024
