1 /** 2 ****************************************************************************** 3 * @file stm32wbxx_hal_cortex.h 4 * @author MCD Application Team 5 * @brief Header file of CORTEX HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32WBxx_HAL_CORTEX_H 21 #define STM32WBxx_HAL_CORTEX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32wbxx_hal_def.h" 29 30 /** @addtogroup STM32WBxx_HAL_Driver 31 * @{ 32 */ 33 34 /** @defgroup CORTEX CORTEX 35 * @brief CORTEX HAL module driver 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types 41 * @{ 42 */ 43 44 #if (__MPU_PRESENT == 1) 45 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition 46 * @brief MPU Region initialization structure 47 * @{ 48 */ 49 typedef struct 50 { 51 uint8_t Enable; /*!< Specifies the status of the region. 52 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ 53 uint8_t Number; /*!< Specifies the number of the region to protect. 54 This parameter can be a value of @ref CORTEX_MPU_Region_Number */ 55 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. 56 */ 57 uint8_t Size; /*!< Specifies the size of the region to protect. 58 This parameter can be a value of @ref CORTEX_MPU_Region_Size */ 59 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. 60 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 61 uint8_t TypeExtField; /*!< Specifies the TEX field level. 62 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ 63 uint8_t AccessPermission; /*!< Specifies the region access permission type. 64 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ 65 uint8_t DisableExec; /*!< Specifies the instruction access status. 66 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ 67 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. 68 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ 69 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. 70 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ 71 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. 72 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ 73 } MPU_Region_InitTypeDef; 74 /** 75 * @} 76 */ 77 #endif /* __MPU_PRESENT */ 78 79 /** 80 * @} 81 */ 82 83 /* Exported constants --------------------------------------------------------*/ 84 85 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants 86 * @{ 87 */ 88 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group 89 * @{ 90 */ 91 #define NVIC_PRIORITYGROUP_0 (0x00000007U) /*!< 0 bit for pre-emption priority, 92 4 bits for subpriority */ 93 #define NVIC_PRIORITYGROUP_1 (0x00000006U) /*!< 1 bit for pre-emption priority, 94 3 bits for subpriority */ 95 #define NVIC_PRIORITYGROUP_2 (0x00000005U) /*!< 2 bits for pre-emption priority, 96 2 bits for subpriority */ 97 #define NVIC_PRIORITYGROUP_3 (0x00000004U) /*!< 3 bits for pre-emption priority, 98 1 bit for subpriority */ 99 #define NVIC_PRIORITYGROUP_4 (0x00000003U) /*!< 4 bits for pre-emption priority, 100 0 bit for subpriority */ 101 /** 102 * @} 103 */ 104 105 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source 106 * @{ 107 */ 108 #define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U 109 #define SYSTICK_CLKSOURCE_HCLK 0x00000004U 110 111 /** 112 * @} 113 */ 114 115 #if (__MPU_PRESENT == 1) 116 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control 117 * @{ 118 */ 119 #define MPU_HFNMI_PRIVDEF_NONE 0x00000000U 120 #define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk) 121 #define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk) 122 #define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) 123 /** 124 * @} 125 */ 126 127 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable 128 * @{ 129 */ 130 #define MPU_REGION_ENABLE ((uint8_t)0x01) 131 #define MPU_REGION_DISABLE ((uint8_t)0x00) 132 /** 133 * @} 134 */ 135 136 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access 137 * @{ 138 */ 139 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) 140 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) 141 /** 142 * @} 143 */ 144 145 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable 146 * @{ 147 */ 148 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) 149 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) 150 /** 151 * @} 152 */ 153 154 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable 155 * @{ 156 */ 157 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) 158 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) 159 /** 160 * @} 161 */ 162 163 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable 164 * @{ 165 */ 166 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) 167 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) 168 /** 169 * @} 170 */ 171 172 /** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels 173 * @{ 174 */ 175 #define MPU_TEX_LEVEL0 ((uint8_t)0x00) 176 #define MPU_TEX_LEVEL1 ((uint8_t)0x01) 177 #define MPU_TEX_LEVEL2 ((uint8_t)0x02) 178 /** 179 * @} 180 */ 181 182 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size 183 * @{ 184 */ 185 #define MPU_REGION_SIZE_32B ((uint8_t)0x04) 186 #define MPU_REGION_SIZE_64B ((uint8_t)0x05) 187 #define MPU_REGION_SIZE_128B ((uint8_t)0x06) 188 #define MPU_REGION_SIZE_256B ((uint8_t)0x07) 189 #define MPU_REGION_SIZE_512B ((uint8_t)0x08) 190 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09) 191 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) 192 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) 193 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) 194 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) 195 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) 196 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) 197 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) 198 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) 199 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) 200 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13) 201 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14) 202 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15) 203 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16) 204 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) 205 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) 206 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) 207 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) 208 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) 209 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) 210 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) 211 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) 212 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) 213 /** 214 * @} 215 */ 216 217 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 218 * @{ 219 */ 220 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) 221 #define MPU_REGION_PRIV_RW ((uint8_t)0x01) 222 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) 223 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) 224 #define MPU_REGION_PRIV_RO ((uint8_t)0x05) 225 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) 226 /** 227 * @} 228 */ 229 230 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number 231 * @{ 232 */ 233 #define MPU_REGION_NUMBER0 ((uint8_t)0x00) 234 #define MPU_REGION_NUMBER1 ((uint8_t)0x01) 235 #define MPU_REGION_NUMBER2 ((uint8_t)0x02) 236 #define MPU_REGION_NUMBER3 ((uint8_t)0x03) 237 #define MPU_REGION_NUMBER4 ((uint8_t)0x04) 238 #define MPU_REGION_NUMBER5 ((uint8_t)0x05) 239 #define MPU_REGION_NUMBER6 ((uint8_t)0x06) 240 #define MPU_REGION_NUMBER7 ((uint8_t)0x07) 241 /** 242 * @} 243 */ 244 #endif /* __MPU_PRESENT */ 245 246 /** 247 * @} 248 */ 249 250 /* Exported macros -----------------------------------------------------------*/ 251 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros 252 * @{ 253 */ 254 255 /** 256 * @} 257 */ 258 259 /* Exported functions --------------------------------------------------------*/ 260 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions 261 * @{ 262 */ 263 264 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions 265 * @brief Initialization and Configuration functions 266 * @{ 267 */ 268 /* Initialization and Configuration functions *****************************/ 269 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); 270 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); 271 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); 272 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); 273 void HAL_NVIC_SystemReset(void); 274 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); 275 /** 276 * @} 277 */ 278 279 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions 280 * @brief Cortex control functions 281 * @{ 282 */ 283 /* Peripheral Control functions *************************************************/ 284 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority); 285 uint32_t HAL_NVIC_GetPriorityGrouping(void); 286 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); 287 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); 288 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); 289 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); 290 void HAL_SYSTICK_IRQHandler(void); 291 void HAL_SYSTICK_Callback(void); 292 293 #if (__MPU_PRESENT == 1U) 294 void HAL_MPU_Enable(uint32_t MPU_Control); 295 void HAL_MPU_Disable(void); 296 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); 297 #endif /* __MPU_PRESENT */ 298 /** 299 * @} 300 */ 301 302 /** 303 * @} 304 */ 305 306 /* Private types -------------------------------------------------------------*/ 307 /* Private variables ---------------------------------------------------------*/ 308 /* Private constants ---------------------------------------------------------*/ 309 /* Private macros ------------------------------------------------------------*/ 310 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros 311 * @{ 312 */ 313 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ 314 ((GROUP) == NVIC_PRIORITYGROUP_1) || \ 315 ((GROUP) == NVIC_PRIORITYGROUP_2) || \ 316 ((GROUP) == NVIC_PRIORITYGROUP_3) || \ 317 ((GROUP) == NVIC_PRIORITYGROUP_4)) 318 319 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) 320 321 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) 322 323 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn) 324 325 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ 326 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) 327 328 #if (__MPU_PRESENT == 1) 329 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ 330 ((STATE) == MPU_REGION_DISABLE)) 331 332 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ 333 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) 334 335 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ 336 ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) 337 338 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ 339 ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) 340 341 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ 342 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) 343 344 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ 345 ((TYPE) == MPU_TEX_LEVEL1) || \ 346 ((TYPE) == MPU_TEX_LEVEL2)) 347 348 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ 349 ((TYPE) == MPU_REGION_PRIV_RW) || \ 350 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ 351 ((TYPE) == MPU_REGION_FULL_ACCESS) || \ 352 ((TYPE) == MPU_REGION_PRIV_RO) || \ 353 ((TYPE) == MPU_REGION_PRIV_RO_URO)) 354 355 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ 356 ((NUMBER) == MPU_REGION_NUMBER1) || \ 357 ((NUMBER) == MPU_REGION_NUMBER2) || \ 358 ((NUMBER) == MPU_REGION_NUMBER3) || \ 359 ((NUMBER) == MPU_REGION_NUMBER4) || \ 360 ((NUMBER) == MPU_REGION_NUMBER5) || \ 361 ((NUMBER) == MPU_REGION_NUMBER6) || \ 362 ((NUMBER) == MPU_REGION_NUMBER7)) 363 364 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ 365 ((SIZE) == MPU_REGION_SIZE_64B) || \ 366 ((SIZE) == MPU_REGION_SIZE_128B) || \ 367 ((SIZE) == MPU_REGION_SIZE_256B) || \ 368 ((SIZE) == MPU_REGION_SIZE_512B) || \ 369 ((SIZE) == MPU_REGION_SIZE_1KB) || \ 370 ((SIZE) == MPU_REGION_SIZE_2KB) || \ 371 ((SIZE) == MPU_REGION_SIZE_4KB) || \ 372 ((SIZE) == MPU_REGION_SIZE_8KB) || \ 373 ((SIZE) == MPU_REGION_SIZE_16KB) || \ 374 ((SIZE) == MPU_REGION_SIZE_32KB) || \ 375 ((SIZE) == MPU_REGION_SIZE_64KB) || \ 376 ((SIZE) == MPU_REGION_SIZE_128KB) || \ 377 ((SIZE) == MPU_REGION_SIZE_256KB) || \ 378 ((SIZE) == MPU_REGION_SIZE_512KB) || \ 379 ((SIZE) == MPU_REGION_SIZE_1MB) || \ 380 ((SIZE) == MPU_REGION_SIZE_2MB) || \ 381 ((SIZE) == MPU_REGION_SIZE_4MB) || \ 382 ((SIZE) == MPU_REGION_SIZE_8MB) || \ 383 ((SIZE) == MPU_REGION_SIZE_16MB) || \ 384 ((SIZE) == MPU_REGION_SIZE_32MB) || \ 385 ((SIZE) == MPU_REGION_SIZE_64MB) || \ 386 ((SIZE) == MPU_REGION_SIZE_128MB) || \ 387 ((SIZE) == MPU_REGION_SIZE_256MB) || \ 388 ((SIZE) == MPU_REGION_SIZE_512MB) || \ 389 ((SIZE) == MPU_REGION_SIZE_1GB) || \ 390 ((SIZE) == MPU_REGION_SIZE_2GB) || \ 391 ((SIZE) == MPU_REGION_SIZE_4GB)) 392 393 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU) 394 #endif /* __MPU_PRESENT */ 395 396 /** 397 * @} 398 */ 399 400 /* Private functions ---------------------------------------------------------*/ 401 402 /** 403 * @} 404 */ 405 406 /** 407 * @} 408 */ 409 410 #ifdef __cplusplus 411 } 412 #endif 413 414 #endif /* STM32WBxx_HAL_CORTEX_H */ 415
