1 /**
2 ******************************************************************************
3 * @file stm32u5xx_hal_pwr_ex.c
4 * @author MCD Application Team
5 * @brief Extended PWR HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Power Controller extension peripheral :
8 * + Power Supply Control Functions
9 * + Low Power Control Functions
10 * + Voltage Monitoring Functions
11 * + Memories Retention Functions
12 * + I/O Pull-Up Pull-Down Configuration Functions
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * Copyright (c) 2021 STMicroelectronics.
18 * All rights reserved.
19 *
20 * This software is licensed under terms that can be found in the LICENSE file
21 * in the root directory of this software component.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
23 *
24 ******************************************************************************
25 @verbatim
26 ==============================================================================
27 ##### How to use this driver #####
28 ==============================================================================
29 [..]
30 (#) Call HAL_PWREx_ControlVoltageScaling() and HAL_PWREx_GetVoltageRange() to
31 set / get the voltage scaling range.
32 (+) Voltage scaling can be one of the following values :
33 (++) voltage output scale 1 : 1V2
34 => Used when system clock frequency is up to 160 MHz
35 (++) voltage output scale 2 : 1V1
36 => Used when system clock frequency is up to 100 MHz
37 (++) voltage output scale 3 : 1V0
38 => Used when system clock frequency is up to 50 MHz
39 (++) voltage output scale 4 : 0V9
40 => Used when system clock frequency is up to 24 MHz
41
42 (#) Call HAL_PWREx_EnableFastSoftStart() and HAL_PWREx_DisableFastSoftStart()
43 to enable / disable the fast software startup for the current regulator.
44
45 (#) Call HAL_PWREx_EnterSTOP1Mode() function to enter the whole system to
46 Stop 1 mode. Wake-up from Stop 1 mode could be following to an event or
47 an interrupt according to low power mode intrinsic request called
48 (__WFI() or __WFE()). (Regulator state on U5 devices is managed
49 internally but regulator parameter is kept for product compatibility).
50
51 (#) Call HAL_PWREx_EnterSTOP2Mode() function to enter the whole system to
52 Stop 2 mode. Wake-up from Stop 2 mode could be following to an event or
53 an interrupt according to low power mode intrinsic request called
54 (__WFI() or __WFE()). (Regulator state on U5 devices is managed
55 internally but regulator parameter is kept for product compatibility).
56
57 (#) Call HAL_PWREx_EnterSTOP3Mode() function to enter the whole system to
58 Stop 3 mode. Wake-up from Stop 3 mode could be following to an event or
59 an interrupt according to low power mode intrinsic request called
60 (__WFI() or __WFE()). (Regulator state on U5 devices is managed
61 internally but regulator parameter is kept for product compatibility).
62
63 (#) Call HAL_PWREx_EnterSHUTDOWNMode() function to enter the whole system in
64 Shutdown mode. Wake-up from Shutdown mode can be following to an external
65 reset (NRST pin), a WKUP pin event (configurable rising or falling edge),
66 or an RTC event occurs (alarm, periodic wakeup, timestamp), or a tamper
67 detection.
68
69 (#) Call HAL_PWREx_ConfigSRDDomain() to force in Run mode or to enter in Stop
70 mode Smart Run Domain when the system enters Stop mode (Stop 0/1/2).
71
72 (#) Call HAL_PWREx_EnableUltraLowPowerMode() and
73 HAL_PWREx_DisableUltraLowPowerMode() to enable / disable the BOR ultra
74 low power mode.
75
76 (#) Call HAL_PWREx_S3WU_IRQHandler() function to handle the PWR Stop 3 wake
77 up interrupt request.
78
79 (#) Call HAL_PWREx_EnableBatteryCharging() and
80 HAL_PWREx_DisableBatteryCharging() to enable / disable the battery
81 charging capability when VDD alimentation is available.
82
83 (#) Call HAL_PWREx_EnableVddUSB(), HAL_PWREx_EnableVddIO2() and
84 HAL_PWREx_EnableVddA() to enable respectively VDDUSB, VDDIO2 and VDDA
85 electrical and logical isolation.
86 It is recommended to disable VDDUSB, VDDIO2 and VDDA electrical and
87 logical isolation through HAL_PWREx_DisableVddUSB(),
88 HAL_PWREx_DisableVddIO2() and HAL_PWREx_DisableVddA().
89
90 (#) Call HAL_PWREx_ConfigPVM() after setting parameters to be configured
91 (event mode and PVD type) in order to set up the Peripheral Voltage
92 Monitor, then use HAL_PWREx_EnableUVM(), HAL_PWREx_EnableIO2VM(),
93 HAL_PWREx_EnableAVM1() and HAL_PWREx_EnableAVM2() functions to start the
94 PVM VDDx monitoring and use HAL_PWREx_DisableUVM(),
95 HAL_PWREx_DisableIO2VM(), HAL_PWREx_DisableAVM1() and
96 HAL_PWREx_DisableAVM2() to stop the PVM VDDx monitoring.
97 (+) PVM monitored voltages are :
98 (++) VDDUSB versus 1V2
99 (++) VDDIO2 versus 0V9
100 (++) VDDA versus 1V6
101 (++) VDDA versus 1V8
102
103 (#) Call HAL_PWREx_EnableUSBHSTranceiverSupply() and
104 HAL_PWREx_DisableUSBHSTranceiverSupply() to enable / disable the internal
105 USB HS transceiver supply.
106 (+) This feature is available only for STM32U59xxx, STM32U5Axxx, STM32U5Fxxx
107 and STM32U5Gxxx devices
108
109 (#) Call HAL_PWREx_EnableOTGHSPHYLowPowerRetention() and
110 HAL_PWREx_DisableOTGHSPHYLowPowerRetention() to enable / disable OTG_HS PHY power during
111 low power modes (Stop2, Stop3 and Standby).
112 (+) This feature is available only for STM32U59xxx, STM32U5Axxx, STM32U5Fxxx
113 and STM32U5Gxxx devices
114
115 (#) Call HAL_PWREx_EnableVDD11USB() and
116 HAL_PWREx_DisableVDD11USB() to enable/ disable the VDD11USB.
117 (+) This feature is available only for STM32U59xxx, STM32U5Axxx, STM32U5Fxxx
118 and STM32U5Gxxx devices
119
120 (#) Call HAL_PWREx_EnableMonitoring() and HAL_PWREx_DisableMonitoring() to
121 enable / disable the VBAT and temperature monitoring.
122
123 (#) Call HAL_PWREx_EnableUCPDStandbyMode() and
124 HAL_PWREx_DisableUCPDStandbyMode() to enable / disable the UCPD
125 configuration memorization in Standby mode.
126
127 (#) Call HAL_PWREx_EnableUCPDDeadBattery() and
128 HAL_PWREx_DisableUCPDDeadBattery() to enable / disable the dead battery
129 behavior.
130
131 (#) Call HAL_PWREx_PVD_PVM_IRQHandler() function to handle the PWR PVD and
132 PVM interrupt request.
133
134 (#) Call HAL_PWREx_EnableSRAM2ContentStandbyRetention() and
135 HAL_PWREx_DisableSRAM2ContentStandbyRetention() to
136 enable / disable the SRAM2 content retention in Stop 3 and Standby low
137 power modes.
138
139 (#) Call HAL_PWREx_EnableRAMsContentStopRetention() and
140 HAL_PWREx_DisableRAMsContentStopRetention() to
141 enable / disable the RAMs content retention in Stop mode (Stop 0/1/2/3).
142 (+) Retained RAM can be one of the following RAMs :
143 (++) SRAM1
144 (++) SRAM2
145 (++) SRAM3 (available only for STM32U575xx, STM32U585xx, STM32U59xxx,
146 STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices)
147 (++) SRAM4
148 (++) SRAM5 (available only for STM32U59xxx, STM32U5Axxx,
149 STM32U5Fxxx and STM32U5Gxxx devices)
150 (++) SRAM6 (available only for STM32U5Fxxx and STM32U5Gxxx devices)
151 (++) ICACHE
152 (++) DMA2DRAM (available only for STM32U575xx, STM32U585xx, STM32U59xxx,
153 STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices)
154 (++) PKA32RAM
155 (++) DCACHE1
156 (++) FMAC
157 (++) FDCAN
158 (++) USB
159 (++) DCACHE2 (available only for STM32U59xxx, STM32U5Axxx,
160 STM32U5Fxxx and STM32U5Gxxx devices)
161 (++) LTDC (available only for STM32U59xxx, STM32U5Axxx,
162 STM32U5Fxxx and STM32U5Gxxx devices)
163 (++) GFXMMU (available only for STM32U59xxx, STM32U5Axxx,
164 STM32U5Fxxx and STM32U5Gxxx devices)
165 (++) DSI (available only for STM32U59xxx, STM32U5Axxx,
166 STM32U5Fxxx and STM32U5Gxxx devices)
167 (++) JPEG (available only for STM32U5Fxxx and STM32U5Gxxx devices)
168
169 (#) Call HAL_PWREx_EnableRAMsContentRunRetention() and
170 HAL_PWREx_DisableRAMsContentRunRetention() to
171 enable / disable the RAMs content retention in Run mode.
172 (+) Retained RAM can be one of the following RAMs :
173 (++) SRAM1
174 (++) SRAM2
175 (++) SRAM3 (available only for STM32U575xx, STM32U585xx, STM32U59xxx,
176 STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices)
177 (++) SRAM4
178 (++) SRAM5 (available only for STM32U59xxx, STM32U5Axxx,
179 STM32U5Fxxx and STM32U5Gxxx devices)
180 (++) SRAM6 (available only for STM32U5Fxxx and STM32U5Gxxx devices)
181
182 (#) Call HAL_PWREx_EnableFlashFastWakeUp() and
183 HAL_PWREx_DisableFlashFastWakeUp() to enable / disable the flash memory
184 fast wakeup from Stop mode (Stop 0/1).
185
186 (#) Call HAL_PWREx_EnableSRAM4FastWakeUp() and
187 HAL_PWREx_DisableSRAM4FastWakeUp() to enable / disable the SRAM4 memory
188 fast wakeup from Stop mode (Stop 0/1/2).
189
190 (#) Call HAL_PWREx_EnableBkupRAMRetention() and
191 HAL_PWREx_DisableBkupRAMRetention() to enable / disable the Backup RAM
192 content retention in Standby, Shutdown and VBAT modes.
193
194 (#) Call HAL_PWREx_EnablePullUpPullDownConfig() and
195 HAL_PWREx_DisablePullUpPullDownConfig() to I/O enable / disable pull-up
196 and pull-down configuration.
197
198 (#) Call HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() to
199 apply respectively pull-up and pull-down to selected I/O.
200 Call HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() to
201 disable applied respectively pull-up and pull-down to selected I/O.
202
203 @endverbatim
204 ******************************************************************************
205 */
206
207 /* Includes ------------------------------------------------------------------*/
208 #include "stm32u5xx_hal.h"
209
210 /** @addtogroup STM32U5xx_HAL_Driver
211 * @{
212 */
213
214 /** @defgroup PWREx PWREx
215 * @brief PWR Extended HAL module driver
216 * @{
217 */
218
219 #if defined (HAL_PWR_MODULE_ENABLED)
220
221 /* Private typedef -----------------------------------------------------------*/
222 /* Private define ------------------------------------------------------------*/
223
224 /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
225 * @{
226 */
227 #if defined (PWR_PUCRJ_PU0)
228 /* PORTI pins mask */
229 #define PWR_PORTI_AVAILABLE_PINS (0xFFFFU)
230 /* PORTJ pins mask */
231 #define PWR_PORTJ_AVAILABLE_PINS (0x0FFFU)
232 #else
233 /* PORTI pins mask */
234 #define PWR_PORTI_AVAILABLE_PINS (0x00FFU)
235 #endif /* defined (PWR_PUCRJ_PU0) */
236
237 /* Time out value of flags setting */
238 #define PWR_FLAG_SETTING_DELAY (0x32U)
239
240 /** @defgroup PWR_PVM_Mode_Mask PWR PVM Mode Mask
241 * @{
242 */
243 #define PVM_RISING_EDGE (0x01U) /*!< Mask for rising edge set as PVM trigger */
244 #define PVM_FALLING_EDGE (0x02U) /*!< Mask for falling edge set as PVM trigger */
245 #define PVM_MODE_IT (0x04U) /*!< Mask for interruption yielded by PVM threshold crossing */
246 #define PVM_MODE_EVT (0x08U) /*!< Mask for event yielded by PVM threshold crossing */
247 /**
248 * @}
249 */
250
251 /**
252 * @}
253 */
254
255 /* Private macro -------------------------------------------------------------*/
256 /* Private variables ---------------------------------------------------------*/
257 /* Private function prototypes -----------------------------------------------*/
258 /* Exported functions --------------------------------------------------------*/
259
260 /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
261 * @{
262 */
263
264 /** @defgroup PWREx_Exported_Functions_Group1 Power Supply Control Functions
265 * @brief Power supply control functions
266 *
267 @verbatim
268 ===============================================================================
269 ##### Power supply control functions #####
270 ===============================================================================
271 [..]
272 This section provides functions allowing to control power supply.
273
274 [..]
275 (+) The STM32U5 Series devices embed two regulators : one LDO (linear
276 voltage regulator) and one SMPS (step down converter) in parallel to
277 provide the VCORE supply for digital peripherals, SRAM1, SRAM2, SRAM3
278 and SRAM4 and embedded Flash memory.
279
280 (+) The SMPS allows the power consumption to be reduced but some
281 peripherals can be perturbed by the noise generated by the SMPS,
282 requiring the application to switch to LDO when running this
283 peripheral in order to reach the best performances.
284
285 (+) The LDO and the SMPS regulators have two modes: Main regulator mode
286 (used when performance is needed), and Low-power regulator mode. LDO
287 or SMPS can be used in all voltage scaling ranges, and in all Stop
288 modes.
289
290 (+) After reset, the regulator is the LDO, in Range 4. Switching to SMPS
291 provides lower consumption in particular at high VDD voltage. It is
292 possible to switch from LDO to SMPS, or from SMPS to LDO on the fly in
293 any range, by configuring the REGSEL bit. It is recommended to switch
294 first to SMPS before changing the voltage range.
295
296 (+) When exiting the Stop or Standby modes, the regulator is the same than
297 when entering low power modes. The voltage range is the Range 4.
298
299 (+) Both regulators can provide four different voltages (voltage scaling)
300 and can operate in Stop modes.
301 Voltage scaling ranges can be one of the following values :
302 (++) voltage output scale 1 : 1V2
303 => Used when system clock frequency is up to 160 MHz
304 (++) voltage output scale 2 : 1V1
305 => Used when system clock frequency is up to 100 MHz
306 (++) voltage output scale 3 : 1V0
307 => Used when system clock frequency is up to 50 MHz
308 (++) voltage output scale 4 : 0V9
309 => Used when system clock frequency is up to 24 MHz
310
311 @endverbatim
312 * @{
313 */
314
315 /**
316 * @brief Configure the main internal regulator output voltage to achieve
317 * a tradeoff between performance and power consumption.
318 * @param VoltageScaling : Specifies the regulator output voltage scale.
319 * This parameter can be one of the following values :
320 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output scale 1.
321 * Provides a typical output voltage at 1.2 V.
322 * Used when system clock frequency is up to 160 MHz.
323 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output scale 2.
324 * Provides a typical output voltage at 1.1 V.
325 * Used when system clock frequency is up to 100 MHz.
326 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output scale 3.
327 * Provides a typical output voltage at 1.0 V.
328 * Used when system clock frequency is up to 50 MHz.
329 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE4 : Regulator voltage output scale 4.
330 * Provides a typical output voltage at 0.9 V.
331 * Used when system clock frequency is up to 24 MHz.
332 * @note Before moving to voltage scaling 2, it is mandatory to ensure that
333 * the system frequency is between 50 MHz and 100 MHz.
334 * @note Before moving to voltage scaling 3, it is mandatory to ensure that
335 * the system frequency is between 24 MHz and 50 MHz.
336 * @note Before moving to voltage scaling 4, it is mandatory to ensure that
337 * the system frequency is below 24 MHz.
338 * @retval HAL Status.
339 */
HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)340 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
341 {
342 uint32_t timeout;
343 uint32_t vos_old;
344
345 /* Check the parameter */
346 assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
347
348 /* Get the current voltage scale applied */
349 vos_old = READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOS);
350
351 /* No change, nothing to do */
352 if (vos_old == VoltageScaling)
353 {
354 /* Enable USB BOOST after wake up from Stop mode */
355 if (VoltageScaling > PWR_REGULATOR_VOLTAGE_SCALE3)
356 {
357 /* Enable USB BOOST */
358 SET_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN);
359 }
360
361 return HAL_OK;
362 }
363
364 /* Check voltage scaling level */
365 /*
366 * The Embedded power distribution (EPOD) must be enabled before switching to
367 * voltage scale 1 / 2 from voltage scale lower.
368 */
369 if (VoltageScaling > PWR_REGULATOR_VOLTAGE_SCALE3)
370 {
371 MODIFY_REG(PWR->VOSR, (PWR_VOSR_VOS | PWR_VOSR_BOOSTEN), (VoltageScaling | PWR_VOSR_BOOSTEN));
372 }
373 else
374 {
375 MODIFY_REG(PWR->VOSR, (PWR_VOSR_VOS | PWR_VOSR_BOOSTEN), VoltageScaling);
376 }
377
378 /* Wait until VOSRDY is raised */
379 timeout = ((PWR_FLAG_SETTING_DELAY * (SystemCoreClock / 1000U)) / 1000U) + 1U;
380 while (HAL_IS_BIT_CLR(PWR->VOSR, PWR_VOSR_VOSRDY) && (timeout != 0U))
381 {
382 timeout--;
383 }
384
385 /* Check time out */
386 if (timeout != 0U)
387 {
388 /* Wait until ACTVOSRDY is raised */
389 timeout = ((PWR_FLAG_SETTING_DELAY * (SystemCoreClock / 1000U)) / 1000U) + 1U;
390 while ((HAL_IS_BIT_CLR(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY)) && (timeout != 0U))
391 {
392 timeout--;
393 }
394 }
395
396 /* Check time out */
397 if (timeout == 0U)
398 {
399 return HAL_TIMEOUT;
400 }
401
402 return HAL_OK;
403 }
404
405 /**
406 * @brief Return Voltage Scaling Range.
407 * @retval Applied voltage scaling value.
408 */
HAL_PWREx_GetVoltageRange(void)409 uint32_t HAL_PWREx_GetVoltageRange(void)
410 {
411 return (PWR->SVMSR & PWR_SVMSR_ACTVOS);
412 }
413
414 /**
415 * @brief Configure the system Power Supply.
416 * @param SupplySource : Specifies the Power Supply source to set after a
417 * system startup.
418 * This parameter can be one of the following values :
419 * @arg PWR_LDO_SUPPLY : The LDO regulator supplies the Vcore Power Domains.
420 * @arg PWR_SMPS_SUPPLY : The SMPS regulator supplies the Vcore Power Domains.
421 * @retval HAL Status.
422 */
HAL_PWREx_ConfigSupply(uint32_t SupplySource)423 HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource)
424 {
425 uint32_t timeout;
426
427 /* Check the parameter */
428 assert_param(IS_PWR_SUPPLY(SupplySource));
429
430 /* Set maximum time out */
431 timeout = ((PWR_FLAG_SETTING_DELAY * (SystemCoreClock / 1000U)) / 1000U) + 1U;
432
433 /* Configure the LDO as system regulator supply */
434 if (SupplySource == PWR_LDO_SUPPLY)
435 {
436 /* Set the power supply configuration */
437 CLEAR_BIT(PWR->CR3, PWR_CR3_REGSEL);
438
439 /* Wait until system switch on new regulator */
440 while (HAL_IS_BIT_SET(PWR->SVMSR, PWR_SVMSR_REGS) && (timeout != 0U))
441 {
442 timeout--;
443 }
444 }
445 /* Configure the SMPS as system regulator supply */
446 else
447 {
448 /* Set the power supply configuration */
449 SET_BIT(PWR->CR3, PWR_CR3_REGSEL);
450
451 /* Wait until system switch on new regulator */
452 while (HAL_IS_BIT_CLR(PWR->SVMSR, PWR_SVMSR_REGS) && (timeout != 0U))
453 {
454 timeout--;
455 }
456 }
457
458 /* Check time out */
459 if (timeout == 0U)
460 {
461 return HAL_TIMEOUT;
462 }
463
464 return HAL_OK;
465 }
466
467 /**
468 * @brief Get the power supply configuration.
469 * @retval The supply configured.
470 */
HAL_PWREx_GetSupplyConfig(void)471 uint32_t HAL_PWREx_GetSupplyConfig(void)
472 {
473 return (PWR->SVMSR & PWR_SVMSR_REGS);
474 }
475
476 /**
477 * @brief Enable fast soft start for the current regulator.
478 * @retval None.
479 */
HAL_PWREx_EnableFastSoftStart(void)480 void HAL_PWREx_EnableFastSoftStart(void)
481 {
482 SET_BIT(PWR->CR3, PWR_CR3_FSTEN);
483 }
484
485 /**
486 * @brief Disable fast soft start for the current regulator.
487 * @retval None.
488 */
HAL_PWREx_DisableFastSoftStart(void)489 void HAL_PWREx_DisableFastSoftStart(void)
490 {
491 CLEAR_BIT(PWR->CR3, PWR_CR3_FSTEN);
492 }
493 /**
494 * @}
495 */
496
497
498 /** @defgroup PWREx_Exported_Functions_Group2 Low Power Control Functions
499 * @brief Low power control functions
500 *
501 @verbatim
502 ===============================================================================
503 ##### Low power control functions #####
504 ===============================================================================
505 [..]
506 This section provides functions allowing to control low power modes.
507
508 *** Low Power modes configuration ***
509 =====================================
510 [..]
511 This section presents 4 principles low power modes :
512 (+) Stop 1 mode : Cortex-M33 is stopped, clocks are stopped and the
513 regulator is in low power mode. Several peripheral can
514 operate in this mode.
515
516 (+) Stop 2 mode : Cortex-M33 is stopped, clocks are stopped and the
517 regulator is in low power mode. Only autonomous
518 peripherals can operate in this mode.
519
520 (+) Stop 3 mode : Cortex-M33 is stopped, clocks are stopped and the
521 regulator is in low power mode. No peripheral can
522 operate in this mode. Only RAMs content is preserved.
523
524 (+) Shutdown mode : All PWR domains enter Shutdown mode and the VCORE
525 supply regulator is powered off. The SRAMs and
526 register contents are lost except for registers in the
527 Backup domain.
528
529 *** Stop 1 mode ***
530 ===================
531 [..]
532 The Stop 1 mode is based on the Cortex-M33 Deepsleep mode combined with
533 the peripheral clock gating. The voltage regulator is configured in low
534 power mode. In Stop 1 mode, all clocks in the VCORE domain are stopped.
535 The PLL, MSIS, MSIK, HSI16 and HSE oscillators are disabled.
536 Some peripherals with the LPBAM capability can switch on HSI16 or MSIS or
537 MSIK for transferring data. All SRAMs and register contents are preserved,
538 but the SRAMs can be totally or partially switched off to further reduced
539 consumption.
540 The BOR is always available in Stop 1 mode.
541
542 (+) Entry:
543 The Stop 1 mode is entered by using the HAL_PWREx_EnterSTOP1Mode()
544 function.
545
546 (++) PWR_STOPENTRY_WFI: enter Stop 1 mode with WFI instruction.
547 (++) PWR_STOPENTRY_WFE: enter Stop 1 mode with WFE instruction.
548
549 (+) Exit:
550 Any EXTI line configured in interrupt mode (the corresponding EXTI
551 interrupt vector must be enabled in the NVIC). The interrupt source
552 can be external interrupts or peripherals with wakeup capability.
553 Any peripheral interrupt occurring when the AHB/APB clocks are present
554 due to an autonomous peripheral clock request (the peripheral vector
555 must be enabled in the NVIC)
556 Any EXTI line configured in event mode.
557
558 *** Stop 2 mode ***
559 ===================
560 [..]
561 The Stop 2 mode is based on the Cortex-M33 Deepsleep mode combined with
562 peripheral clock gating. In Stop 2 mode, all clocks in the VCORE domain
563 are stopped.
564 The PLL, MSIS, MSIK, HSI16 and HSE oscillators are disabled.
565 Some peripherals with the LPBAM capability can switch on HSI16 or MSIS or
566 MSIK for transferring data. All SRAMs and register contents are preserved,
567 but the SRAMs can be totally or partially switched off to further reduce
568 consumption.
569 The BOR is always available in Stop 2 mode.
570
571 (+) Entry:
572 The Stop 2 mode is entered by using the HAL_PWREx_EnterSTOP2Mode()
573 function.
574
575 (++) PWR_STOPENTRY_WFI: enter Stop 2 mode with WFI instruction.
576 (++) PWR_STOPENTRY_WFE: enter Stop 2 mode with WFE instruction.
577
578 (+) Exit:
579 Any EXTI line configured in interrupt mode (the corresponding EXTI
580 interrupt vector must be enabled in the NVIC). The interrupt source
581 can be external interrupts or peripherals with wakeup capability.
582 Any peripheral interrupt occurring when the AHB/APB clocks are present
583 due to an autonomous peripheral clock request (the peripheral vector
584 must be enabled in the NVIC)
585 Any EXTI line configured in event mode.
586
587 *** Stop 3 mode ***
588 ===================
589 [..]
590 The Stop 3 mode is based on the Cortex-M33 Deepsleep mode combined with
591 peripheral clock gating. In Stop 3 mode, all clocks in the VCORE domain
592 are stopped.
593 The PLL, MSIS, MSIK, HSI16 and HSE oscillators are disabled.
594 All SRAMs and register contents are preserved, but the SRAMs can be
595 totally or partially switched off to further reduce consumption.
596 The BOR is always available in Stop 3 mode.
597
598 (+) Entry:
599 The Stop 3 mode is entered by using the HAL_PWREx_EnterSTOP3Mode()
600 function.
601
602 (++) PWR_STOPENTRY_WFI: enter Stop 3 mode with WFI instruction.
603 (++) PWR_STOPENTRY_WFE: enter Stop 3 mode with WFE instruction.
604
605 (+) Exit:
606 WKUPx pin edge, RTC or TAMP event, external Reset in NRST pin, IWDG
607 Reset, BOR reset.
608
609 *** Shutdown mode ***
610 ====================
611 [..]
612 The lowest power consumption is reached in Shutdown mode. It is based on
613 the Deepsleep mode with the voltage regulator disabled. The VCORE domain
614 is consequently powered off.
615 The PLL, HSI16, MSIS, MSIK and HSE oscillators are also switched off.
616 The SRAMs and register contents are lost except for registers in the
617 Backup domain.
618 The BOR is not available in Shutdown mode.
619 No power voltage monitoring is possible in this mode, therefore the switch
620 to Backup domain is not supported.
621
622 (+) Entry:
623 The Shutdown mode is entered by using the HAL_PWREx_EnterSHUTDOWNMode()
624 function.
625
626 (+) Exit:
627 WKUPx pin edge, RTC/TAMP event, external Reset in NRST pin.
628
629 @endverbatim
630 * @{
631 */
632
633 /**
634 * @brief Enter the whole system to Stop 1 mode.
635 * @note Stop 1 offers the largest number of active peripherals and wakeup
636 * sources, a smaller wakeup time but a higher consumption.
637 * @note Stop mode achieves the lowest power consumption while retaining
638 * the content of SRAM and registers. All clocks in the VCORE domain
639 * are stopped. The PLL, the MSI (MSIS and MSIK) RC, the HSI16 RC and
640 * the HSE crystal oscillators are disabled. The LSE or LSI is still
641 * running.
642 * @note The system clock when exiting from Stop mode can be either MSIS up
643 * to 24 MHz or HSI16, depending on software configuration.
644 * @param STOPEntry : Specifies if Stop mode is entered with WFI or WFE
645 * instruction.
646 * This parameter can be one of the following values :
647 * @arg @ref PWR_STOPENTRY_WFI enter Stop mode with Wait
648 * For Interrupt request.
649 * @arg @ref PWR_STOPENTRY_WFE enter Stop mode with Wait
650 * For Event request.
651 * @retval None.
652 */
HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)653 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)
654 {
655 /* Check the parameters */
656 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
657
658 /* Stop 1 mode */
659 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_0);
660
661 /* Set SLEEPDEEP bit of Cortex System Control Register */
662 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
663
664 /* Select Stop mode entry */
665 if (STOPEntry == PWR_STOPENTRY_WFI)
666 {
667 /* Request Wait For Interrupt */
668 __WFI();
669 }
670 else
671 {
672 /* Request Wait For Event */
673 __SEV();
674 __WFE();
675 __WFE();
676 }
677
678 /* Reset SLEEPDEEP bit of Cortex System Control Register */
679 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
680 }
681
682 /**
683 * @brief Enter the whole system to Stop 2 mode.
684 * @note In Stop 2 mode, all clocks in the VCORE domain are stopped. The PLL,
685 * MSIS, MSIK, HSI16 and HSE oscillators are disabled.
686 * @note Stop mode achieves the lowest power consumption while retaining
687 * the content of SRAM and registers. All clocks in the VCORE domain
688 * are stopped. The PLL, the MSI (MSIS and MSIK) RC, the HSI16 RC and
689 * the HSE crystal oscillators are disabled. The LSE or LSI is still
690 * running.
691 * @note The system clock when exiting from Stop mode can be either MSIS up
692 * to 24 MHz or HSI16, depending on software configuration.
693 * @param STOPEntry : Specifies if Stop mode is entered with WFI or WFE
694 * instruction.
695 * This parameter can be one of the following values :
696 * @arg @ref PWR_STOPENTRY_WFI enter Stop mode with Wait
697 * For Interrupt request.
698 * @arg @ref PWR_STOPENTRY_WFE enter Stop mode with Wait
699 * For Event request.
700 * @retval None.
701 */
HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)702 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)
703 {
704 /* Check the parameters */
705 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
706
707 /* Stop 2 mode */
708 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_1);
709
710 /* Set SLEEPDEEP bit of Cortex System Control Register */
711 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
712
713 /* Select Stop mode entry */
714 if (STOPEntry == PWR_STOPENTRY_WFI)
715 {
716 /* Request Wait For Interrupt */
717 __WFI();
718 }
719 else
720 {
721 /* Request Wait For Event */
722 __SEV();
723 __WFE();
724 __WFE();
725 }
726
727 /* Reset SLEEPDEEP bit of Cortex System Control Register */
728 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
729 }
730
731 /**
732 * @brief Enter the whole system to Stop 3 mode.
733 * @note Stop 3 is the lowest power mode with full retention, but the
734 * functional peripherals and sources of wakeup are reduced to the same
735 * ones than in Standby mode.
736 * @note Stop mode achieves the lowest power consumption while retaining
737 * the content of SRAM and registers. All clocks in the VCORE domain
738 * are stopped. The PLL, the MSI (MSIS and MSIK) RC, the HSI16 RC and
739 * the HSE crystal oscillators are disabled. The LSE or LSI is still
740 * running.
741 * @note The system clock when exiting from Stop mode can be either MSIS up
742 * to 24 MHz or HSI16, depending on software configuration.
743 * @param STOPEntry : Specifies if Stop mode is entered with WFI or WFE
744 * instruction.
745 * This parameter can be one of the following values :
746 * @arg @ref PWR_STOPENTRY_WFI enter Stop mode with Wait
747 * For Interrupt request.
748 * @arg @ref PWR_STOPENTRY_WFE enter Stop mode with Wait
749 * For Event request.
750 * @retval None.
751 */
HAL_PWREx_EnterSTOP3Mode(uint8_t STOPEntry)752 void HAL_PWREx_EnterSTOP3Mode(uint8_t STOPEntry)
753 {
754 /* Check the parameter */
755 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
756
757 /* Set Stop mode 3 */
758 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1));
759
760 /* Set SLEEPDEEP bit of Cortex System Control Register */
761 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
762
763 /* Select Stop mode entry */
764 if (STOPEntry == PWR_STOPENTRY_WFI)
765 {
766 /* Request Wait For Interrupt */
767 __WFI();
768 }
769 else
770 {
771 /* Request Wait For Event */
772 __SEV();
773 __WFE();
774 __WFE();
775 }
776
777 /* Reset SLEEPDEEP bit of Cortex System Control Register */
778 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
779 }
780
781 /**
782 * @brief Enter the whole system to Shutdown mode.
783 * @note Shutdown mode allows the lowest power consumption. The internal
784 * regulator is switched off so that the VCORE domain is powered off.
785 * The PLL, the HSI16, the MSI (MSIS and MSIK), the LSI and the HSE
786 * oscillators are also switched off.
787 * @note The SRAMs and register contents are lost except for registers in the
788 * Backup domain. The BOR is not available in Shutdown mode. No power
789 * voltage monitoring is possible in this mode, therefore the switch to
790 * Backup domain is not supported.
791 * @retval None.
792 */
HAL_PWREx_EnterSHUTDOWNMode(void)793 void HAL_PWREx_EnterSHUTDOWNMode(void)
794 {
795 /* Set Shutdown mode */
796 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, (PWR_CR1_LPMS_1 | PWR_CR1_LPMS_2));
797
798 /* Set SLEEPDEEP bit of Cortex System Control Register */
799 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
800
801 /* This option is used to ensure that store operations are completed */
802 #if defined (__CC_ARM)
803 __force_stores();
804 #endif /* (__CC_ARM)*/
805 /* Request Wait For Interrupt */
806 __WFI();
807 }
808
809 /**
810 * @brief Configure the SRD domain when the System in Stop 0/1/2 mode.
811 * @param SRDState : Specifies the SRD state.
812 * This parameter can be one of the following values :
813 * @arg PWR_SRD_DOMAIN_STOP : SRD in Stop mode when system
814 * goes to Stop 0/1/2 mode
815 * @arg PWR_SRD_DOMAIN_RUN : SRD in Run mode when system
816 * goes to Stop 0/1/2 mode
817 * @retval None.
818 */
HAL_PWREx_ConfigSRDDomain(uint32_t SRDState)819 void HAL_PWREx_ConfigSRDDomain(uint32_t SRDState)
820 {
821 /* Check the parameter */
822 assert_param(IS_PWR_SRD_STATE(SRDState));
823
824 /* Config the SRD domain */
825 MODIFY_REG(PWR->CR2, PWR_CR2_SRDRUN, SRDState);
826 }
827
828 /**
829 * @brief Enable BOR ultra-low power mode.
830 * @note BOR operating can be in discontinuous (ultra-low power) mode in
831 * Stop 1, Stop 2, Stop 3 and Standby modes and when the regulator is
832 * in Range 4 (Run, Sleep or Stop 0 mode).
833 * @retval None.
834 */
HAL_PWREx_EnableUltraLowPowerMode(void)835 void HAL_PWREx_EnableUltraLowPowerMode(void)
836 {
837 SET_BIT(PWR->CR1, PWR_CR1_ULPMEN);
838 }
839
840 /**
841 * @brief Disable BOR ultra-low power mode.
842 * @retval None.
843 */
HAL_PWREx_DisableUltraLowPowerMode(void)844 void HAL_PWREx_DisableUltraLowPowerMode(void)
845 {
846 CLEAR_BIT(PWR->CR1, PWR_CR1_ULPMEN);
847 }
848
849 /**
850 * @brief This function handles the PWR Wake up from Stop 3 interrupt request.
851 * @note This API should be called under the PWR_S3WU_IRQHandler().
852 * @param WakeUpPin : Specifies the wakeup pin interrupt to be handled.
853 * This parameter can be a combination of @ref PWR_WakeUp_Pins.
854 * @retval None.
855 */
HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin)856 void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin)
857 {
858 /* Check PWR wake up line 1 */
859 if ((WakeUpPin & PWR_WAKEUP_PIN1) != 0U)
860 {
861 if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) != 0U)
862 {
863 /* Clear PWR wake up flag line 1 */
864 SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF1);
865
866 /* PWR S3WU interrupt user callback */
867 HAL_PWREx_S3WUCallback(WakeUpPin);
868 }
869 }
870
871 /* Check PWR wake up line 2 */
872 if ((WakeUpPin & PWR_WAKEUP_PIN2) != 0U)
873 {
874 if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) != 0U)
875 {
876 /* Clear PWR wake up flag line 2 */
877 SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF2);
878
879 /* PWR S3WU interrupt user callback */
880 HAL_PWREx_S3WUCallback(WakeUpPin);
881 }
882 }
883
884 /* Check PWR wake up line 3 */
885 if ((WakeUpPin & PWR_WAKEUP_PIN3) != 0U)
886 {
887 if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) != 0U)
888 {
889 /* Clear PWR wake up flag line 3 */
890 SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF3);
891
892 /* PWR S3WU interrupt user callback */
893 HAL_PWREx_S3WUCallback(WakeUpPin);
894 }
895 }
896
897 /* Check PWR wake up line 4 */
898 if ((WakeUpPin & PWR_WAKEUP_PIN4) != 0U)
899 {
900 if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) != 0U)
901 {
902 /* Clear PWR wake up flag line 4 */
903 SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF4);
904
905 /* PWR S3WU interrupt user callback */
906 HAL_PWREx_S3WUCallback(WakeUpPin);
907 }
908 }
909
910 /* Check PWR wake up line 5 */
911 if ((WakeUpPin & PWR_WAKEUP_PIN5) != 0U)
912 {
913 if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) != 0U)
914 {
915 /* Clear PWR wake up flag line 5 */
916 SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF5);
917
918 /* PWR S3WU interrupt user callback */
919 HAL_PWREx_S3WUCallback(WakeUpPin);
920 }
921 }
922
923 /* Check PWR wake up line 6 */
924 if ((WakeUpPin & PWR_WAKEUP_PIN6) != 0U)
925 {
926 if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) != 0U)
927 {
928 /* Clear PWR wake up flag line 6 */
929 SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF6);
930
931 /* PWR S3WU interrupt user callback */
932 HAL_PWREx_S3WUCallback(WakeUpPin);
933 }
934 }
935
936 /* Check PWR wake up line 7 */
937 if ((WakeUpPin & PWR_WAKEUP_PIN7) != 0U)
938 {
939 if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) != 0U)
940 {
941 /* Clear PWR wake up flag line 7 */
942 SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF7);
943
944 /* PWR S3WU interrupt user callback */
945 HAL_PWREx_S3WUCallback(WakeUpPin);
946 }
947 }
948
949 /* Check PWR wake up line 8 */
950 if ((WakeUpPin & PWR_WAKEUP_PIN8) != 0U)
951 {
952 if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) != 0U)
953 {
954 /* Clear PWR wake up flag line 8 */
955 SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF8);
956
957 /* PWR S3WU interrupt user callback */
958 HAL_PWREx_S3WUCallback(WakeUpPin);
959 }
960 }
961 }
962
963 /**
964 * @brief PWR S3WU interrupt callback.
965 * @param WakeUpPin : Specifies the wakeup pin interrupt to be handled.
966 * This parameter can be a combination of @ref PWR_WakeUp_Pins.
967 * @retval None.
968 */
HAL_PWREx_S3WUCallback(uint32_t WakeUpPin)969 __weak void HAL_PWREx_S3WUCallback(uint32_t WakeUpPin)
970 {
971 /* Prevent unused argument(s) compilation warning */
972 UNUSED(WakeUpPin);
973
974 /* NOTE : This function should not be modified; when the callback is needed,
975 HAL_PWREx_S3WU_IRQHandler() API can be implemented in the user file
976 */
977 }
978 /**
979 * @}
980 */
981
982 /** @defgroup PWREx_Exported_Functions_Group3 Voltage Monitoring Functions
983 * @brief Voltage monitoring functions
984 *
985 @verbatim
986 ===============================================================================
987 ##### Voltage Monitoring Functions #####
988 ===============================================================================
989 [..]
990 This section provides functions allowing voltage monitoring.
991
992 *** PVM configuration ***
993 =========================
994 [..]
995 (+) The supplies (VDDA, VDDIO2 and VDDUSB) can be independent from VDD and
996 can be monitored with four peripheral voltage monitoring (PVM):
997
998 (++) The UVM monitors the USB supply VDDUSB. VDDUSBRDY indicates if
999 the VDDUSB independent power supply is higher or lower than the
1000 VUVM threshold.
1001 (++) The IO2VM monitors the PG[15:2] supply VDDIO2. VDDIO2RDY
1002 indicates if the VDDIO2 independent power supply is higher or
1003 lower than the VIO2VM threshold.
1004 (++) The AVM1 monitors the analog supply VDDA. VDDA1RDY indicates if
1005 the VDDA independent power supply is higher or lower than the
1006 VAVM1 threshold.
1007 (++) The AVM2 monitors the analog supply VDDA. VDDA2RDY indicates if
1008 the VDDA independent power supply is higher or lower than the
1009 VAVM2 threshold.
1010
1011 (+) Each PVM output is connected to an EXTI line and can generate an
1012 interrupt if enabled through the EXTI registers. The PVMx output
1013 interrupt is generated when the independent power supply drops below
1014 the PVM threshold and/or when it rises above the PVM threshold,
1015 depending on EXTI line rising/falling edge configuration.
1016
1017 (+) Each PVM can remain active in Stop 0, Stop 1, Stop 2 modes, and the
1018 PVM interrupt can wake up from the Stop mode. The PVM is not
1019 functional in Stop 3 mode.
1020
1021 *** VBAT charging ***
1022 =====================
1023 [..]
1024 When VDD is present, it is possible to charge the external battery on VBAT
1025 through an internal resistance.
1026 The VBAT charging is done either through a 5 kOhm resistor or through a 1.5
1027 kOhm resistor depending on the VBRS bit value in the PWR_BDCR2 register.
1028 The battery charging is enabled by setting VBE bit in the PWR_BDCR2
1029 register. It is automatically disabled in VBAT mode.
1030
1031 *** Backup domain monitoring ***
1032 ================================
1033 [..]
1034 When the Backup domain voltage and temperature monitoring is enabled
1035 (MONEN = 1 in the PWR_BDCR1 register), the Backup domain voltage and the
1036 temperature are monitored.
1037 If the Backup domain voltage monitoring internal tamper is enabled in the
1038 TAMP peripheral (ITAMP1E = 1 in the TAMP_CR1 register), a tamper event is
1039 generated when the Backup domain voltage is above the functional range.
1040 In case the Backup domain voltage is below the functional range,
1041 a Brownout reset is generated, erasing all device including Backup domain.
1042
1043 *** Backup domain battery ***
1044 =============================
1045 [..]
1046 (+) To retain the content of the backup registers and supply the RTC
1047 function when VDD is turned off, the VBAT pin can be connected to an
1048 optional backup voltage supplied by a battery or by another source.
1049 The VBAT pin powers the RTC unit, the LSE oscillator and the PC13 to
1050 PC15 I/Os, allowing the RTC to operate even when the main power supply
1051 is turned off. The backup SRAM is optionally powered by VBAT pin when
1052 the BREN bit is set in the PWR Backup domain control register 1
1053 (PWR_BDCR1).
1054 The switch to the VBAT supply is controlled by the power down reset
1055 embedded in the Reset block.
1056
1057 (+) After exiting reset, the USB Type-C (dead battery) behavior is enabled,
1058 which may have a pull-down effect on CC1 and CC2 pins. It is
1059 recommended to disable it in all cases, either to stop this pull-down
1060 or to handover control to the UCPD (the UCPD must be initialized
1061 before doing the disable).
1062
1063 @endverbatim
1064 * @{
1065 */
1066
1067 /**
1068 * @brief Configure the voltage monitor threshold detected by the Peripheral
1069 * voltage monitoring (PVM).
1070 * @param pConfigPVM : Pointer to a PWR_PVMTypeDef structure that contains the
1071 * PVM configuration information (PVMType and EventMode).
1072 * @retval HAL Status.
1073 */
HAL_PWREx_ConfigPVM(PWR_PVMTypeDef * pConfigPVM)1074 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *pConfigPVM)
1075 {
1076 /* Check the PVM parameter */
1077 if (pConfigPVM == NULL)
1078 {
1079 return HAL_ERROR;
1080 }
1081
1082 /* Check the parameters */
1083 assert_param(IS_PWR_PVM_TYPE(pConfigPVM->PVMType));
1084 assert_param(IS_PWR_PVM_MODE(pConfigPVM->Mode));
1085
1086 /* Check the peripheral voltage monitor type */
1087 switch (pConfigPVM->PVMType)
1088 {
1089 case PWR_UVM: /* Independent USB voltage monitor */
1090
1091 /* Disable EXTI UVM event and interrupt */
1092 __HAL_PWR_UVM_EXTI_DISABLE_EVENT();
1093 __HAL_PWR_UVM_EXTI_DISABLE_IT();
1094 __HAL_PWR_UVM_EXTI_DISABLE_RISING_EDGE();
1095 __HAL_PWR_UVM_EXTI_DISABLE_FALLING_EDGE();
1096
1097 /* Configure the UVM in interrupt mode */
1098 if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
1099 {
1100 __HAL_PWR_UVM_EXTI_ENABLE_IT();
1101 }
1102
1103 /* Configure the UVM in event mode */
1104 if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
1105 {
1106 __HAL_PWR_UVM_EXTI_ENABLE_EVENT();
1107 }
1108
1109 /* Configure the UVM in rising edge */
1110 if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
1111 {
1112 __HAL_PWR_UVM_EXTI_ENABLE_RISING_EDGE();
1113 }
1114
1115 /* Configure the UVM in falling edge */
1116 if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
1117 {
1118 __HAL_PWR_UVM_EXTI_ENABLE_FALLING_EDGE();
1119 }
1120
1121 break;
1122
1123 case PWR_IO2VM: /* Independent I/Os voltage monitor */
1124
1125 /* Disable EXTI IO2VM event and interrupt */
1126 __HAL_PWR_IO2VM_EXTI_DISABLE_EVENT();
1127 __HAL_PWR_IO2VM_EXTI_DISABLE_IT();
1128 __HAL_PWR_IO2VM_EXTI_DISABLE_RISING_EDGE();
1129 __HAL_PWR_IO2VM_EXTI_DISABLE_FALLING_EDGE();
1130
1131 /* Configure the IO2VM in interrupt mode */
1132 if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
1133 {
1134 __HAL_PWR_IO2VM_EXTI_ENABLE_IT();
1135 }
1136
1137 /* Configure the IO2VM in event mode */
1138 if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
1139 {
1140 __HAL_PWR_IO2VM_EXTI_ENABLE_EVENT();
1141 }
1142
1143 /* Configure the IO2VM in rising edge */
1144 if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
1145 {
1146 __HAL_PWR_IO2VM_EXTI_ENABLE_RISING_EDGE();
1147 }
1148
1149 /* Configure the IO2VM in falling edge */
1150 if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
1151 {
1152 __HAL_PWR_IO2VM_EXTI_ENABLE_FALLING_EDGE();
1153 }
1154
1155 break;
1156
1157 case PWR_AVM1: /* VDDA Independent analog supply voltage monitor 1 (1.6V threshold) */
1158
1159 /* Disable EXTI AVM1 event and interrupt */
1160 __HAL_PWR_AVM1_EXTI_DISABLE_EVENT();
1161 __HAL_PWR_AVM1_EXTI_DISABLE_IT();
1162 __HAL_PWR_AVM1_EXTI_DISABLE_RISING_EDGE();
1163 __HAL_PWR_AVM1_EXTI_DISABLE_FALLING_EDGE();
1164
1165 /* Configure the AVM1 in interrupt mode */
1166 if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
1167 {
1168 __HAL_PWR_AVM1_EXTI_ENABLE_IT();
1169 }
1170
1171 /* Configure the AVM1 in event mode */
1172 if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
1173 {
1174 __HAL_PWR_AVM1_EXTI_ENABLE_EVENT();
1175 }
1176
1177 /* Configure the AVM1 in rising edge */
1178 if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
1179 {
1180 __HAL_PWR_AVM1_EXTI_ENABLE_RISING_EDGE();
1181 }
1182
1183 /* Configure the AVM1 in falling edge */
1184 if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
1185 {
1186 __HAL_PWR_AVM1_EXTI_ENABLE_FALLING_EDGE();
1187 }
1188
1189 break;
1190
1191 case PWR_AVM2: /* VDDA Independent analog supply voltage monitor 2 (1.8V threshold) */
1192
1193 /* Disable EXTI AVM2 event and interrupt */
1194 __HAL_PWR_AVM2_EXTI_DISABLE_EVENT();
1195 __HAL_PWR_AVM2_EXTI_DISABLE_IT();
1196 __HAL_PWR_AVM2_EXTI_DISABLE_RISING_EDGE();
1197 __HAL_PWR_AVM2_EXTI_DISABLE_FALLING_EDGE();
1198
1199 /* Configure the AVM2 in interrupt mode */
1200 if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
1201 {
1202 __HAL_PWR_AVM2_EXTI_ENABLE_IT();
1203 }
1204
1205 /* Configure the AVM2 in event mode */
1206 if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
1207 {
1208 __HAL_PWR_AVM2_EXTI_ENABLE_EVENT();
1209 }
1210
1211 /* Configure the AVM2 in rising edge */
1212 if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
1213 {
1214 __HAL_PWR_AVM2_EXTI_ENABLE_RISING_EDGE();
1215 }
1216
1217 /* Configure the AVM2 in falling edge */
1218 if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
1219 {
1220 __HAL_PWR_AVM2_EXTI_ENABLE_FALLING_EDGE();
1221 }
1222
1223 break;
1224
1225 default: /* No valid voltage monitor selected */
1226 return HAL_ERROR;
1227 break;
1228 }
1229
1230 return HAL_OK;
1231 }
1232
1233 /**
1234 * @brief Enable VDDUSB supply.
1235 * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply
1236 * is present for consumption saving.
1237 * @retval None.
1238 */
HAL_PWREx_EnableVddUSB(void)1239 void HAL_PWREx_EnableVddUSB(void)
1240 {
1241 SET_BIT(PWR->SVMCR, PWR_SVMCR_USV);
1242 }
1243
1244 /**
1245 * @brief Disable VDDUSB supply.
1246 * @retval None.
1247 */
HAL_PWREx_DisableVddUSB(void)1248 void HAL_PWREx_DisableVddUSB(void)
1249 {
1250 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_USV);
1251 }
1252
1253 /**
1254 * @brief Enable VDDIO2 supply.
1255 * @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply
1256 * is present for consumption saving.
1257 * @retval None.
1258 */
HAL_PWREx_EnableVddIO2(void)1259 void HAL_PWREx_EnableVddIO2(void)
1260 {
1261 SET_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV);
1262 }
1263
1264 /**
1265 * @brief Disable VDDIO2 supply.
1266 * @retval None.
1267 */
HAL_PWREx_DisableVddIO2(void)1268 void HAL_PWREx_DisableVddIO2(void)
1269 {
1270 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV);
1271 }
1272
1273 /**
1274 * @brief Enable VDDA supply.
1275 * @note Remove VDDA electrical and logical isolation, once VDDA supply is
1276 * present for consumption saving.
1277 * @retval None.
1278 */
HAL_PWREx_EnableVddA(void)1279 void HAL_PWREx_EnableVddA(void)
1280 {
1281 SET_BIT(PWR->SVMCR, PWR_SVMCR_ASV);
1282 }
1283
1284 /**
1285 * @brief Disable VDDA supply.
1286 * @retval None.
1287 */
HAL_PWREx_DisableVddA(void)1288 void HAL_PWREx_DisableVddA(void)
1289 {
1290 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_ASV);
1291 }
1292
1293 /**
1294 * @brief Enable the UVM Voltage Monitoring : VDDUSB versus 1.2 V.
1295 * @retval None.
1296 */
HAL_PWREx_EnableUVM(void)1297 void HAL_PWREx_EnableUVM(void)
1298 {
1299 SET_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN);
1300 }
1301
1302 /**
1303 * @brief Disable the UVM Voltage Monitoring : VDDUSB versus 1.2 V.
1304 * @retval None.
1305 */
HAL_PWREx_DisableUVM(void)1306 void HAL_PWREx_DisableUVM(void)
1307 {
1308 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN);
1309 }
1310
1311 /**
1312 * @brief Enable the IO2VM Voltage Monitoring : VDDIO2 versus 0.9 V.
1313 * @retval None.
1314 */
HAL_PWREx_EnableIO2VM(void)1315 void HAL_PWREx_EnableIO2VM(void)
1316 {
1317 SET_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN);
1318 }
1319
1320 /**
1321 * @brief Disable the IO2VM Voltage Monitoring : VDDIO2 versus 0.9 V.
1322 * @retval None.
1323 */
HAL_PWREx_DisableIO2VM(void)1324 void HAL_PWREx_DisableIO2VM(void)
1325 {
1326 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN);
1327 }
1328
1329 /**
1330 * @brief Enable the AVM1 Voltage Monitoring : VDDA versus 1.6 V.
1331 * @retval None.
1332 */
HAL_PWREx_EnableAVM1(void)1333 void HAL_PWREx_EnableAVM1(void)
1334 {
1335 SET_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN);
1336 }
1337
1338 /**
1339 * @brief Disable the AVM1 Voltage Monitoring : VDDA versus 1.6 V.
1340 * @retval None.
1341 */
HAL_PWREx_DisableAVM1(void)1342 void HAL_PWREx_DisableAVM1(void)
1343 {
1344 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN);
1345 }
1346
1347 /**
1348 * @brief Enable the AVM2 Voltage Monitoring : VDDA versus 1.8 V.
1349 * @retval None.
1350 */
HAL_PWREx_EnableAVM2(void)1351 void HAL_PWREx_EnableAVM2(void)
1352 {
1353 SET_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN);
1354 }
1355
1356 /**
1357 * @brief Disable the AVM2 Voltage Monitoring : VDDA versus 1.8 V.
1358 * @retval None.
1359 */
HAL_PWREx_DisableAVM2(void)1360 void HAL_PWREx_DisableAVM2(void)
1361 {
1362 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN);
1363 }
1364
1365 /**
1366 * @brief Enable the VBAT and temperature monitoring.
1367 * @retval None.
1368 */
HAL_PWREx_EnableMonitoring(void)1369 void HAL_PWREx_EnableMonitoring(void)
1370 {
1371 SET_BIT(PWR->BDCR1, PWR_BDCR1_MONEN);
1372 }
1373
1374 /**
1375 * @brief Disable the VBAT and temperature monitoring.
1376 * @retval None.
1377 */
HAL_PWREx_DisableMonitoring(void)1378 void HAL_PWREx_DisableMonitoring(void)
1379 {
1380 CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_MONEN);
1381 }
1382
1383 #if defined (PWR_VOSR_USBPWREN)
1384 /**
1385 * @brief Enable the internal USB HS transceiver supply.
1386 * @retval HAL status.
1387 */
HAL_PWREx_EnableUSBHSTranceiverSupply(void)1388 HAL_StatusTypeDef HAL_PWREx_EnableUSBHSTranceiverSupply(void)
1389 {
1390 uint32_t vos;
1391
1392 /* Get the system applied voltage scaling range */
1393 vos = HAL_PWREx_GetVoltageRange();
1394
1395 /* Check the system applied voltage scaling range */
1396 if ((vos == PWR_REGULATOR_VOLTAGE_SCALE1) || (vos == PWR_REGULATOR_VOLTAGE_SCALE2))
1397 {
1398 SET_BIT(PWR->VOSR, (PWR_VOSR_USBPWREN | PWR_VOSR_USBBOOSTEN));
1399 }
1400 else
1401 {
1402 return HAL_ERROR;
1403 }
1404
1405 return HAL_OK;
1406 }
1407
1408 /**
1409 * @brief Disable the internal USB HS transceiver supply.
1410 * @retval HAL status.
1411 */
HAL_PWREx_DisableUSBHSTranceiverSupply(void)1412 void HAL_PWREx_DisableUSBHSTranceiverSupply(void)
1413 {
1414 CLEAR_BIT(PWR->VOSR, (PWR_VOSR_USBPWREN | PWR_VOSR_USBBOOSTEN));
1415 }
1416 #endif /* defined (PWR_VOSR_USBPWREN) */
1417
1418 #if defined (PWR_CR1_FORCE_USBPWR)
1419 /**
1420 * @brief Enable OTG_HS PHY power during low power modes (Stop2, Stop3 and Standby).
1421 * @retval None.
1422 */
HAL_PWREx_EnableOTGHSPHYLowPowerRetention(void)1423 void HAL_PWREx_EnableOTGHSPHYLowPowerRetention(void)
1424 {
1425 /* Set FORCE_USBPWR bit */
1426 SET_BIT(PWR->CR1, PWR_CR1_FORCE_USBPWR);
1427 }
1428
1429 /**
1430 * @brief Disable OTG_HS PHY power during low power modes (Stop2, Stop3 and Standby).
1431 * @retval None.
1432 */
HAL_PWREx_DisableOTGHSPHYLowPowerRetention(void)1433 void HAL_PWREx_DisableOTGHSPHYLowPowerRetention(void)
1434 {
1435 /* Clear FORCE_USBPWR bit */
1436 CLEAR_BIT(PWR->CR1, PWR_CR1_FORCE_USBPWR);
1437 }
1438 #endif /* defined (PWR_CR1_FORCE_USBPWR) */
1439
1440 #if defined (PWR_VOSR_VDD11USBDIS)
1441 /**
1442 * @brief Enable the VDD11USB.
1443 * @retval None.
1444 */
HAL_PWREx_EnableVDD11USB(void)1445 void HAL_PWREx_EnableVDD11USB(void)
1446 {
1447 /* Clear VDD11USBDIS bit */
1448 CLEAR_BIT(PWR->VOSR, PWR_VOSR_VDD11USBDIS);
1449 }
1450
1451 /**
1452 * @brief Disable the VDD11USB.
1453 * @retval None.
1454 */
HAL_PWREx_DisableVDD11USB(void)1455 void HAL_PWREx_DisableVDD11USB(void)
1456 {
1457 /* Set VDD11USBDIS bit */
1458 SET_BIT(PWR->VOSR, PWR_VOSR_VDD11USBDIS);
1459 }
1460 #endif /* defined (PWR_VOSR_VDD11USBDIS) */
1461
1462 #ifdef UCPD1
1463 /**
1464 * @brief Enable UCPD configuration memorization in Standby mode.
1465 * @retval None.
1466 */
HAL_PWREx_EnableUCPDStandbyMode(void)1467 void HAL_PWREx_EnableUCPDStandbyMode(void)
1468 {
1469 SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY);
1470 }
1471
1472 /**
1473 * @brief Disable UCPD configuration memorization in Standby mode.
1474 * @note This function must be called on exiting the Standby mode and before
1475 * any UCPD configuration update.
1476 * @retval None.
1477 */
HAL_PWREx_DisableUCPDStandbyMode(void)1478 void HAL_PWREx_DisableUCPDStandbyMode(void)
1479 {
1480 CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY);
1481 }
1482
1483 /**
1484 * @brief Enable dead battery behavior.
1485 * @note After exiting reset, the USB Type-C (dead battery) behavior is
1486 * enabled, which may have a pull-down effect on CC1 and CC2 pins.
1487 * It is recommended to disable it in all cases, either to stop this
1488 * pull-down or to handover control to the UCPD (the UCPD must be
1489 * initialized before doing the disable).
1490 * @retval None.
1491 */
HAL_PWREx_EnableUCPDDeadBattery(void)1492 void HAL_PWREx_EnableUCPDDeadBattery(void)
1493 {
1494 CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS);
1495 }
1496
1497 /**
1498 * @brief Disable dead battery behavior.
1499 * @note After exiting reset, the USB Type-C (dead battery) behavior is
1500 * enabled, which may have a pull-down effect on CC1 and CC2 pins.
1501 * It is recommended to disable it in all cases, either to stop this
1502 * pull-down or to handover control to the UCPD (the UCPD must be
1503 * initialized before doing the disable).
1504 * @retval None.
1505 */
HAL_PWREx_DisableUCPDDeadBattery(void)1506 void HAL_PWREx_DisableUCPDDeadBattery(void)
1507 {
1508 SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS);
1509 }
1510 #endif /* UCPD1 */
1511
1512 /**
1513 * @brief Enable the Battery charging.
1514 * @note When VDD is present, charge the external battery through an internal
1515 * resistor.
1516 * @param ResistorValue : Specifies the charging resistor.
1517 * This parameter can be one of the following values :
1518 * @arg PWR_BATTERY_CHARGING_RESISTOR_5 : 5 KOhm resistor.
1519 * @arg PWR_BATTERY_CHARGING_RESISTOR_1_5 : 1.5 KOhm resistor.
1520 * @retval None.
1521 */
HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue)1522 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue)
1523 {
1524 /* Check the parameter */
1525 assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorValue));
1526
1527 /* Specify the charging resistor */
1528 MODIFY_REG(PWR->BDCR2, PWR_BDCR2_VBRS, ResistorValue);
1529
1530 /* Enable the Battery charging */
1531 SET_BIT(PWR->BDCR2, PWR_BDCR2_VBE);
1532 }
1533
1534 /**
1535 * @brief Disable the Battery charging.
1536 * @retval None.
1537 */
HAL_PWREx_DisableBatteryCharging(void)1538 void HAL_PWREx_DisableBatteryCharging(void)
1539 {
1540 CLEAR_BIT(PWR->BDCR2, PWR_BDCR2_VBE);
1541 }
1542
1543 /**
1544 * @brief This function handles the PWR PVD/PVM interrupt request.
1545 * @note This API should be called under the PVD_PVM_IRQHandler().
1546 * @retval None.
1547 */
HAL_PWREx_PVD_PVM_IRQHandler(void)1548 void HAL_PWREx_PVD_PVM_IRQHandler(void)
1549 {
1550 uint32_t rising_flag;
1551 uint32_t falling_flag;
1552
1553 /* Get pending flags */
1554 rising_flag = READ_REG(EXTI->RPR1);
1555 falling_flag = READ_REG(EXTI->FPR1);
1556
1557 /* Check PWR exti flags for PVD */
1558 if (((rising_flag | falling_flag) & PWR_EXTI_LINE_PVD) != 0U)
1559 {
1560 /* PWR PVD interrupt user callback */
1561 HAL_PWR_PVDCallback();
1562
1563 /* Clear PVD exti pending bit */
1564 WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD);
1565 WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD);
1566 }
1567
1568 /* Check PWR exti flags for UVM */
1569 if (((rising_flag | falling_flag) & PWR_EXTI_LINE_UVM) != 0U)
1570 {
1571 /* PWR UVM interrupt user callback */
1572 HAL_PWREx_UVMCallback();
1573
1574 /* Clear UVM exti pending bit */
1575 WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_UVM);
1576 WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_UVM);
1577 }
1578
1579 /* Check PWR exti flags for IO2VM */
1580 if (((rising_flag | falling_flag) & PWR_EXTI_LINE_IO2VM) != 0U)
1581 {
1582 /* PWR IO2VM interrupt user callback */
1583 HAL_PWREx_IO2VMCallback();
1584
1585 /* Clear IO2VM exti pending bit */
1586 WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_IO2VM);
1587 WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_IO2VM);
1588 }
1589
1590 /* Check PWR exti flags for AVM1 */
1591 if (((rising_flag | falling_flag) & PWR_EXTI_LINE_AVM1) != 0U)
1592 {
1593 /* PWR AVM1 interrupt user callback */
1594 HAL_PWREx_AVM1Callback();
1595
1596 /* Clear AVM1 exti pending bit */
1597 WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_AVM1);
1598 WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_AVM1);
1599 }
1600
1601 /* Check PWR exti flags for AVM2 */
1602 if (((rising_flag | falling_flag) & PWR_EXTI_LINE_AVM2) != 0U)
1603 {
1604 /* PWR AVM2 interrupt user callback */
1605 HAL_PWREx_AVM2Callback();
1606
1607 /* Clear AVM2 exti pending bit */
1608 WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_AVM2);
1609 WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_AVM2);
1610 }
1611 }
1612
1613 /**
1614 * @brief PWR UVM interrupt callback.
1615 * @retval None.
1616 */
HAL_PWREx_UVMCallback(void)1617 __weak void HAL_PWREx_UVMCallback(void)
1618 {
1619 /* NOTE : This function should not be modified; when the callback is needed,
1620 HAL_PWREx_UVMCallback() API can be implemented in the user file
1621 */
1622 }
1623
1624 /**
1625 * @brief PWR IO2VM interrupt callback.
1626 * @retval None.
1627 */
HAL_PWREx_IO2VMCallback(void)1628 __weak void HAL_PWREx_IO2VMCallback(void)
1629 {
1630 /* NOTE : This function should not be modified; when the callback is needed,
1631 HAL_PWREx_IO2VMCallback() API can be implemented in the user file
1632 */
1633 }
1634
1635 /**
1636 * @brief PWR AVM1 interrupt callback.
1637 * @retval None.
1638 */
HAL_PWREx_AVM1Callback(void)1639 __weak void HAL_PWREx_AVM1Callback(void)
1640 {
1641 /* NOTE : This function should not be modified; when the callback is needed,
1642 HAL_PWREx_AVM1Callback() API can be implemented in the user file
1643 */
1644 }
1645
1646 /**
1647 * @brief PWR AVM2 interrupt callback.
1648 * @retval None.
1649 */
HAL_PWREx_AVM2Callback(void)1650 __weak void HAL_PWREx_AVM2Callback(void)
1651 {
1652 /* NOTE : This function should not be modified; when the callback is needed,
1653 HAL_PWREx_AVM2Callback() API can be implemented in the user file
1654 */
1655 }
1656 /**
1657 * @}
1658 */
1659
1660 /** @defgroup PWREx_Exported_Functions_Group4 Memories Retention Functions
1661 * @brief Memories retention functions
1662 *
1663 @verbatim
1664 ===============================================================================
1665 ##### Memories Retention Functions #####
1666 ===============================================================================
1667 [..]
1668 Several STM32U5 devices RAMs are configurable to keep / lose RAMs content
1669 during Stop mode (Stop 0/1/2/3).
1670 (+) Retained content RAMs in Stop modes are :
1671 (++) SRAM1
1672 (++) SRAM2
1673 (++) SRAM3 (available only for STM32U575xx, STM32U585xx, STM32U59xxx,
1674 STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices)
1675 (++) SRAM4
1676 (++) ICACHE
1677 (++) DMA2DRAM (available only for STM32U575xx, STM32U585xx, STM32U59xxx,
1678 STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices)
1679 (++) PKA32RAM
1680 (++) DCACHE
1681 (++) FMAC
1682 (++) FDCAN
1683 (++) USB
1684
1685 [..]
1686 Several STM32U5 devices RAMs are configurable to keep / lose RAMs content
1687 during Run mode.
1688 (+) Retained content RAMs in Run modes are :
1689 (++) SRAM1
1690 (++) SRAM2
1691 (++) SRAM3 (available only for STM32U575xx, STM32U585xx, STM32U59xxx,
1692 STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices)
1693 (++) SRAM4
1694
1695 [..]
1696 SRAM2 is configurable to keep / lose its content in Stop 3 and Standby
1697 modes. The SRAM2 retention feature granularity is at pages level.
1698
1699 [..]
1700 BKPRAM is configurable to keep / lose its content in Standby, Shutdown and
1701 VBAT modes.
1702
1703 @endverbatim
1704 * @{
1705 */
1706
1707 /**
1708 * @brief Enable SRAM2 page(s) content retention in Stop 3 and Standby mode.
1709 * @note When RRSx bit is set, SRAM2 is powered by the low-power regulator in
1710 * Stop 3 and Standby mode and its content is kept.
1711 * @param SRAM2Pages : Specifies the SRAM2 pages.
1712 * This parameter can be one of the following values :
1713 * @arg PWR_SRAM2_PAGE1_STANDBY : SRAM2 page 1 retention.
1714 * @arg PWR_SRAM2_PAGE2_STANDBY : SRAM2 page 2 retention.
1715 * @arg PWR_SRAM2_FULL_STANDBY : SRAM2 page 1 and page 2 retention.
1716 * @retval None.
1717 */
HAL_PWREx_EnableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages)1718 void HAL_PWREx_EnableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages)
1719 {
1720 /* Check the parameters */
1721 assert_param(IS_PWR_SRAM2_STANDBY_RETENTION(SRAM2Pages));
1722
1723 /* Set RRSx bit(s) */
1724 SET_BIT(PWR->CR1, SRAM2Pages);
1725 }
1726
1727 /**
1728 * @brief Disable SRAM2 page(s) content retention in Stop 3 and Standby mode.
1729 * @note When RRSx bit is reset, SRAM2 is powered off in Stop 3 and Standby
1730 * mode and its content is lost.
1731 * @param SRAM2Pages : Specifies the SRAM2 pages.
1732 * This parameter can be one of the following values :
1733 * @arg PWR_SRAM2_PAGE1_STANDBY : SRAM2 page 1 retention.
1734 * @arg PWR_SRAM2_PAGE2_STANDBY : SRAM2 page 2 retention.
1735 * @arg PWR_SRAM2_FULL_STANDBY : SRAM2 page 1 and page 2 retention.
1736 * @retval None.
1737 */
HAL_PWREx_DisableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages)1738 void HAL_PWREx_DisableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages)
1739 {
1740 /* Check the parameters */
1741 assert_param(IS_PWR_SRAM2_STANDBY_RETENTION(SRAM2Pages));
1742
1743 /* Clear RRSx bit(s) */
1744 CLEAR_BIT(PWR->CR1, SRAM2Pages);
1745 }
1746
1747 /**
1748 * @brief Enable RAM page(s) content retention in Stop mode (Stop 0, 1, 2, 3).
1749 * @note When enabling content retention for a given RAM, memory kept powered
1750 * in Stop mode. (Not optimized power consumption)
1751 * @param RAMSelection: Specifies RAM page(s) to be retained in Stop mode.
1752 * This parameter can be one or a combination of the same
1753 * memory @ref PWREx_RAM_Contents_Stop_Retention.
1754 * @retval None.
1755 */
HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection)1756 void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection)
1757 {
1758 uint32_t dummy;
1759
1760 /* Check RAM ID */
1761 switch (RAMSelection & SRAM_ID_MASK)
1762 {
1763 /* SRAM 1 Stop retention */
1764 case SRAM1_ID:
1765 {
1766 /* Check the parameters */
1767 assert_param(IS_PWR_SRAM1_STOP_RETENTION(RAMSelection));
1768
1769 /* Calculate pages mask */
1770 dummy = (RAMSelection & ~SRAM_ID_MASK) & (PAGE01_ID | PAGE02_ID | PAGE03_ID);
1771 CLEAR_BIT(PWR->CR2, dummy);
1772
1773 #if defined (PWR_CR4_SRAM1PDS4)
1774 /* Calculate pages mask */
1775 dummy = ((RAMSelection & ~SRAM_ID_MASK) & ~(PAGE01_ID | PAGE02_ID | PAGE03_ID)) >> 0x03U;
1776 CLEAR_BIT(PWR->CR4, dummy);
1777 #endif /* defined (PWR_CR4_SRAM1PDS4) */
1778
1779 break;
1780 }
1781
1782 /* SRAM 2 Stop retention */
1783 case SRAM2_ID:
1784 {
1785 /* Check the parameters */
1786 assert_param(IS_PWR_SRAM2_STOP_RETENTION(RAMSelection));
1787
1788 /* Calculate pages mask */
1789 dummy = (RAMSelection & PWR_SRAM2_FULL_STOP) & ~SRAM_ID_MASK;
1790 CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM2PDS1_Pos));
1791
1792 break;
1793 }
1794
1795 #if defined (PWR_CR2_SRAM3PDS1)
1796 /* SRAM 3 Stop retention */
1797 case SRAM3_ID:
1798 {
1799 /* Check the parameters */
1800 assert_param(IS_PWR_SRAM3_STOP_RETENTION(RAMSelection));
1801
1802 /* Calculate pages mask */
1803 dummy = (RAMSelection & ~SRAM_ID_MASK) & (PAGE01_ID | PAGE02_ID | PAGE03_ID | PAGE04_ID |
1804 PAGE05_ID | PAGE06_ID | PAGE07_ID | PAGE08_ID);
1805 CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM3PDS1_Pos));
1806
1807 #if defined (PWR_CR4_SRAM3PDS9)
1808 /* Calculate pages mask */
1809 dummy = ((RAMSelection & ~SRAM_ID_MASK) & ~(PAGE01_ID | PAGE02_ID | PAGE03_ID | PAGE04_ID |
1810 PAGE05_ID | PAGE06_ID | PAGE07_ID | PAGE08_ID)) >> 0x08U;
1811 CLEAR_BIT(PWR->CR4, (dummy << PWR_CR4_SRAM3PDS9_Pos));
1812 #endif /* defined (PWR_CR4_SRAM3PDS9) */
1813
1814 break;
1815 }
1816 #endif /* PWR_CR2_SRAM3PDS1 */
1817
1818 /* SRAM 4 Stop retention */
1819 case SRAM4_ID:
1820 {
1821 /* Check the parameters */
1822 assert_param(IS_PWR_SRAM4_STOP_RETENTION(RAMSelection));
1823
1824 /* Calculate pages mask */
1825 dummy = (RAMSelection & PWR_SRAM4_FULL_STOP) & ~SRAM_ID_MASK;
1826 CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM4PDS_Pos));
1827
1828 break;
1829 }
1830
1831 /* ICACHE RAM Stop retention */
1832 case ICACHERAM_ID:
1833 {
1834 /* Check the parameters */
1835 assert_param(IS_PWR_ICACHE_STOP_RETENTION(RAMSelection));
1836
1837 /* Calculate pages mask */
1838 dummy = (RAMSelection & PWR_ICACHE_FULL_STOP) & ~SRAM_ID_MASK;
1839 CLEAR_BIT(PWR->CR2, dummy << PWR_CR2_ICRAMPDS_Pos);
1840
1841 break;
1842 }
1843
1844 /* DCACHE1 RAM Stop retention */
1845 case DCACHE1RAM_ID:
1846 {
1847 /* Check the parameters */
1848 assert_param(IS_PWR_DCACHE1_STOP_RETENTION(RAMSelection));
1849
1850 /* Calculate pages mask */
1851 dummy = (RAMSelection & PWR_DCACHE1_FULL_STOP) & ~SRAM_ID_MASK;
1852 CLEAR_BIT(PWR->CR2, dummy << PWR_CR2_DC1RAMPDS_Pos);
1853
1854 break;
1855 }
1856
1857 #if defined (PWR_CR2_DMA2DRAMPDS)
1858 /* DMA2D RAM Stop retention */
1859 case DMA2DRAM_ID:
1860 {
1861 /* Check the parameters */
1862 assert_param(IS_PWR_DMA2DRAM_STOP_RETENTION(RAMSelection));
1863
1864 /* Calculate pages mask */
1865 dummy = (RAMSelection & PWR_DMA2DRAM_FULL_STOP) & ~SRAM_ID_MASK;
1866 CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_DMA2DRAMPDS_Pos));
1867
1868 break;
1869 }
1870 #endif /* PWR_CR2_DMA2DRAMPDS */
1871
1872 /* FMAC, FDCAN and USB RAM Stop retention */
1873 case PERIPHRAM_ID:
1874 {
1875 /* Check the parameters */
1876 assert_param(IS_PWR_PERIPHRAM_STOP_RETENTION(RAMSelection));
1877
1878 /* Calculate pages mask */
1879 dummy = (RAMSelection & PWR_PERIPHRAM_FULL_STOP) & ~SRAM_ID_MASK;
1880 CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_PRAMPDS_Pos));
1881
1882 break;
1883 }
1884
1885 /* PKA32 RAM Stop retention */
1886 case PKARAM_ID:
1887 {
1888 /* Check the parameters */
1889 assert_param(IS_PWR_PKA32RAM_STOP_RETENTION(RAMSelection));
1890
1891 /* Calculate pages mask */
1892 dummy = (RAMSelection & PWR_PKA32RAM_FULL_STOP) & ~SRAM_ID_MASK;
1893 CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_PKARAMPDS_Pos));
1894
1895 break;
1896 }
1897
1898 #if defined (PWR_CR2_DC2RAMPDS)
1899 /* DCACHE2 RAM Stop retention */
1900 case DCACHE2RAM_ID:
1901 {
1902 /* Check the parameters */
1903 assert_param(IS_PWR_DCACHE2_STOP_RETENTION(RAMSelection));
1904
1905 /* Calculate pages mask */
1906 dummy = (RAMSelection & PWR_DCACHE2_FULL_STOP) & ~SRAM_ID_MASK;
1907 CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_DC2RAMPDS_Pos));
1908
1909 break;
1910 }
1911 #endif /* defined (PWR_CR2_DC2RAMPDS) */
1912
1913 #if defined (PWR_CR2_GPRAMPDS)
1914 /* LTDC and GFXMMU RAM Stop retention */
1915 case GRAPHIPRAM_ID:
1916 {
1917 /* Check the parameters */
1918 assert_param(IS_PWR_GRAPHICPRAM_STOP_RETENTION(RAMSelection));
1919
1920 /* Calculate pages mask */
1921 dummy = (RAMSelection & PWR_GRAPHICPRAM_FULL_STOP) & ~SRAM_ID_MASK;
1922 CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_GPRAMPDS_Pos));
1923
1924 break;
1925 }
1926 #endif /* defined (PWR_CR2_GPRAMPDS) */
1927
1928 #if defined (PWR_CR2_DSIRAMPDS)
1929 /* DSI RAM Stop retention */
1930 case DSIRAM_ID:
1931 {
1932 /* Check the parameters */
1933 assert_param(IS_PWR_DSIRAM_STOP_RETENTION(RAMSelection));
1934
1935 /* Calculate pages mask */
1936 dummy = (RAMSelection & PWR_DSIRAM_FULL_STOP) & ~SRAM_ID_MASK;
1937 CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_DSIRAMPDS_Pos));
1938
1939 break;
1940 }
1941 #endif /* defined (PWR_CR2_DSIRAMPDS) */
1942
1943 #if defined (PWR_CR2_JPEGRAMPDS)
1944 /* JPEG RAM Stop retention */
1945 case JPEGRAM_ID:
1946 {
1947 /* Check the parameters */
1948 assert_param(IS_PWR_JPEGRAM_STOP_RETENTION(RAMSelection));
1949
1950 /* Calculate pages mask */
1951 dummy = (RAMSelection & PWR_JPEGRAM_FULL_STOP) & ~SRAM_ID_MASK;
1952 CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_JPEGRAMPDS_Pos));
1953
1954 break;
1955 }
1956 #endif /* defined (PWR_CR2_JPEGRAMPDS) */
1957
1958 #if defined (PWR_CR4_SRAM5PDS1)
1959 /* SRAM 5 Stop retention */
1960 case SRAM5_ID:
1961 {
1962 /* Check the parameters */
1963 assert_param(IS_PWR_SRAM5_STOP_RETENTION(RAMSelection));
1964
1965 /* Calculate pages mask */
1966 dummy = ((RAMSelection & PWR_SRAM5_FULL_STOP) & ~SRAM_ID_MASK);
1967 CLEAR_BIT(PWR->CR4, (dummy << PWR_CR4_SRAM5PDS1_Pos));
1968
1969 break;
1970 }
1971 #endif /* defined (PWR_CR4_SRAM5PDS1) */
1972
1973 #if defined (PWR_CR5_SRAM6PDS1)
1974 /* SRAM 6 Stop retention */
1975 case SRAM6_ID:
1976 {
1977 /* Check the parameters */
1978 assert_param(IS_PWR_SRAM6_STOP_RETENTION(RAMSelection));
1979
1980 /* Calculate pages mask */
1981 dummy = ((RAMSelection & PWR_SRAM6_FULL_STOP) & ~SRAM_ID_MASK);
1982 CLEAR_BIT(PWR->CR5, (dummy << PWR_CR5_SRAM6PDS1_Pos));
1983
1984 break;
1985 }
1986 #endif /* defined (PWR_CR5_SRAM6PDS1) */
1987
1988 default:
1989 {
1990 return;
1991 break;
1992 }
1993 }
1994 }
1995
1996 /**
1997 * @brief Disable RAM page(s) content lost in Stop mode (Stop 0, 1, 2, 3).
1998 * @note When disabling content lost for a given RAM, memory powered down
1999 * in Stop mode. (Optimized power consumption)
2000 * @param RAMSelection: Specifies RAM page(s) to be lost in Stop mode.
2001 * This parameter can be one or a combination of the same
2002 * memory @ref PWREx_RAM_Contents_Stop_Retention.
2003 * @retval None.
2004 */
HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection)2005 void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection)
2006 {
2007 uint32_t dummy;
2008
2009 /* Check RAM ID */
2010 switch (RAMSelection & SRAM_ID_MASK)
2011 {
2012 /* SRAM 1 Stop retention */
2013 case SRAM1_ID:
2014 {
2015 /* Check the parameters */
2016 assert_param(IS_PWR_SRAM1_STOP_RETENTION(RAMSelection));
2017
2018 /* Calculate pages mask */
2019 dummy = (RAMSelection & ~SRAM_ID_MASK) & (PAGE01_ID | PAGE02_ID | PAGE03_ID);
2020 SET_BIT(PWR->CR2, dummy);
2021 #if defined (PWR_CR4_SRAM1PDS4)
2022 /* Calculate pages mask */
2023 dummy = ((RAMSelection & ~SRAM_ID_MASK) & ~(PAGE01_ID | PAGE02_ID | PAGE03_ID)) >> 0x03U;
2024 SET_BIT(PWR->CR4, dummy);
2025 #endif /* defined (PWR_CR4_SRAM1PDS4) */
2026
2027 break;
2028 }
2029
2030 /* SRAM 2 Stop retention */
2031 case SRAM2_ID:
2032 {
2033 /* Check the parameters */
2034 assert_param(IS_PWR_SRAM2_STOP_RETENTION(RAMSelection));
2035
2036 /* Calculate pages mask */
2037 dummy = (RAMSelection & PWR_SRAM2_FULL_STOP) & ~SRAM_ID_MASK;
2038 SET_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM2PDS1_Pos));
2039
2040 break;
2041 }
2042
2043 #if defined (PWR_CR2_SRAM3PDS1)
2044 /* SRAM 3 Stop retention */
2045 case SRAM3_ID:
2046 {
2047 /* Check the parameters */
2048 assert_param(IS_PWR_SRAM3_STOP_RETENTION(RAMSelection));
2049
2050 /* Calculate pages mask */
2051 dummy = (RAMSelection & ~SRAM_ID_MASK) & (PAGE01_ID | PAGE02_ID | PAGE03_ID | PAGE04_ID |
2052 PAGE05_ID | PAGE06_ID | PAGE07_ID | PAGE08_ID);
2053 SET_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM3PDS1_Pos));
2054
2055 #if defined (PWR_CR4_SRAM3PDS9)
2056 /* Calculate pages mask */
2057 dummy = ((RAMSelection & ~SRAM_ID_MASK) & ~(PAGE01_ID | PAGE02_ID | PAGE03_ID | PAGE04_ID |
2058 PAGE05_ID | PAGE06_ID | PAGE07_ID | PAGE08_ID)) >> 0x08U;
2059 SET_BIT(PWR->CR4, (dummy << PWR_CR4_SRAM3PDS9_Pos));
2060 #endif /* defined (PWR_CR4_SRAM3PDS9) */
2061
2062 break;
2063 }
2064 #endif /* PWR_CR2_SRAM3PDS1 */
2065
2066 /* SRAM 4 Stop retention */
2067 case SRAM4_ID:
2068 {
2069 /* Check the parameters */
2070 assert_param(IS_PWR_SRAM4_STOP_RETENTION(RAMSelection));
2071
2072 /* Calculate pages mask */
2073 dummy = (RAMSelection & PWR_SRAM4_FULL_STOP) & ~SRAM_ID_MASK;
2074 SET_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM4PDS_Pos));
2075
2076 break;
2077 }
2078
2079 /* ICACHE RAM Stop retention */
2080 case ICACHERAM_ID:
2081 {
2082 /* Check the parameters */
2083 assert_param(IS_PWR_ICACHE_STOP_RETENTION(RAMSelection));
2084
2085 /* Calculate pages mask */
2086 dummy = (RAMSelection & PWR_ICACHE_FULL_STOP) & ~SRAM_ID_MASK;
2087 SET_BIT(PWR->CR2, (dummy << PWR_CR2_ICRAMPDS_Pos));
2088
2089 break;
2090 }
2091
2092 /* DCACHE1 RAM Stop retention */
2093 case DCACHE1RAM_ID:
2094 {
2095 /* Check the parameters */
2096 assert_param(IS_PWR_DCACHE1_STOP_RETENTION(RAMSelection));
2097
2098 /* Calculate pages mask */
2099 dummy = (RAMSelection & PWR_DCACHE1_FULL_STOP) & ~SRAM_ID_MASK;
2100 SET_BIT(PWR->CR2, (dummy << PWR_CR2_DC1RAMPDS_Pos));
2101
2102 break;
2103 }
2104
2105 #if defined (PWR_CR2_DMA2DRAMPDS)
2106 /* DMA2D RAM Stop retention */
2107 case DMA2DRAM_ID:
2108 {
2109 /* Check the parameters */
2110 assert_param(IS_PWR_DMA2DRAM_STOP_RETENTION(RAMSelection));
2111
2112 /* Calculate pages mask */
2113 dummy = (RAMSelection & PWR_DMA2DRAM_FULL_STOP) & ~SRAM_ID_MASK;
2114 SET_BIT(PWR->CR2, (dummy << PWR_CR2_DMA2DRAMPDS_Pos));
2115
2116 break;
2117 }
2118 #endif /* PWR_CR2_DMA2DRAMPDS */
2119
2120 /* FMAC, FDCAN and USB RAM Stop retention */
2121 case PERIPHRAM_ID:
2122 {
2123 /* Check the parameters */
2124 assert_param(IS_PWR_PERIPHRAM_STOP_RETENTION(RAMSelection));
2125
2126 /* Calculate pages mask */
2127 dummy = (RAMSelection & PWR_PERIPHRAM_FULL_STOP) & ~SRAM_ID_MASK;
2128 SET_BIT(PWR->CR2, (dummy << PWR_CR2_PRAMPDS_Pos));
2129
2130 break;
2131 }
2132
2133 /* PKA32 RAM Stop retention */
2134 case PKARAM_ID:
2135 {
2136 /* Check the parameters */
2137 assert_param(IS_PWR_PKA32RAM_STOP_RETENTION(RAMSelection));
2138
2139 /* Calculate pages mask */
2140 dummy = (RAMSelection & PWR_PKA32RAM_FULL_STOP) & ~SRAM_ID_MASK;
2141 SET_BIT(PWR->CR2, (dummy << PWR_CR2_PKARAMPDS_Pos));
2142
2143 break;
2144 }
2145
2146 #if defined (PWR_CR2_DC2RAMPDS)
2147 /* DCACHE2 RAM Stop retention */
2148 case DCACHE2RAM_ID:
2149 {
2150 /* Check the parameters */
2151 assert_param(IS_PWR_DCACHE2_STOP_RETENTION(RAMSelection));
2152
2153 /* Calculate pages mask */
2154 dummy = (RAMSelection & PWR_DCACHE2_FULL_STOP) & ~SRAM_ID_MASK;
2155 SET_BIT(PWR->CR2, (dummy << PWR_CR2_DC2RAMPDS_Pos));
2156
2157 break;
2158 }
2159 #endif /* defined (PWR_CR2_DC2RAMPDS) */
2160
2161 #if defined (PWR_CR2_GPRAMPDS)
2162 /* LTDC and GFXMMU RAM Stop retention */
2163 case GRAPHIPRAM_ID:
2164 {
2165 /* Check the parameters */
2166 assert_param(IS_PWR_GRAPHICPRAM_STOP_RETENTION(RAMSelection));
2167
2168 /* Calculate pages mask */
2169 dummy = (RAMSelection & PWR_GRAPHICPRAM_FULL_STOP) & ~SRAM_ID_MASK;
2170 SET_BIT(PWR->CR2, (dummy << PWR_CR2_GPRAMPDS_Pos));
2171
2172 break;
2173 }
2174 #endif /* defined (PWR_CR2_GPRAMPDS) */
2175
2176 #if defined (PWR_CR2_DSIRAMPDS)
2177 /* DSI RAM Stop retention */
2178 case DSIRAM_ID:
2179 {
2180 /* Check the parameters */
2181 assert_param(IS_PWR_DSIRAM_STOP_RETENTION(RAMSelection));
2182
2183 /* Calculate pages mask */
2184 dummy = (RAMSelection & PWR_DSIRAM_FULL_STOP) & ~SRAM_ID_MASK;
2185 SET_BIT(PWR->CR2, (dummy << PWR_CR2_DSIRAMPDS_Pos));
2186
2187 break;
2188 }
2189 #endif /* defined (PWR_CR2_DSIRAMPDS) */
2190
2191 #if defined (PWR_CR2_JPEGRAMPDS)
2192 /* JPEG RAM Stop retention */
2193 case JPEGRAM_ID:
2194 {
2195 /* Check the parameters */
2196 assert_param(IS_PWR_JPEGRAM_STOP_RETENTION(RAMSelection));
2197
2198 /* Calculate pages mask */
2199 dummy = (RAMSelection & PWR_JPEGRAM_FULL_STOP) & ~SRAM_ID_MASK;
2200 SET_BIT(PWR->CR2, (dummy << PWR_CR2_JPEGRAMPDS_Pos));
2201
2202 break;
2203 }
2204 #endif /* defined (PWR_CR2_JPEGRAMPDS) */
2205
2206 #if defined (PWR_CR4_SRAM5PDS1)
2207 /* SRAM 5 Stop retention */
2208 case SRAM5_ID:
2209 {
2210 /* Check the parameters */
2211 assert_param(IS_PWR_SRAM5_STOP_RETENTION(RAMSelection));
2212
2213 /* Calculate pages mask */
2214 dummy = ((RAMSelection & PWR_SRAM5_FULL_STOP) & ~SRAM_ID_MASK);
2215 SET_BIT(PWR->CR4, (dummy << PWR_CR4_SRAM5PDS1_Pos));
2216
2217 break;
2218 }
2219 #endif /* defined (PWR_CR4_SRAM5PDS1) */
2220
2221 #if defined (PWR_CR5_SRAM6PDS1)
2222 /* SRAM 6 Stop retention */
2223 case SRAM6_ID:
2224 {
2225 /* Check the parameters */
2226 assert_param(IS_PWR_SRAM6_STOP_RETENTION(RAMSelection));
2227
2228 /* Calculate pages mask */
2229 dummy = ((RAMSelection & PWR_SRAM6_FULL_STOP) & ~SRAM_ID_MASK);
2230 SET_BIT(PWR->CR5, (dummy << PWR_CR5_SRAM6PDS1_Pos));
2231
2232 break;
2233 }
2234 #endif /* defined (PWR_CR5_SRAM6PDS1) */
2235
2236 default:
2237 {
2238 return;
2239 break;
2240 }
2241 }
2242 }
2243
2244 /**
2245 * @brief Enable RAMs full content retention in Run mode.
2246 * @param RAMSelection : Specifies the SRAM content to be retained in Run mode.
2247 * This parameter can be one or a combination of the following values :
2248 * @arg PWR_SRAM1_FULL_RUN : SRAM1 full content retention.
2249 * @arg PWR_SRAM2_FULL_RUN : SRAM2 full content retention.
2250 * @arg PWR_SRAM3_FULL_RUN : SRAM3 full content retention (available only for STM32U575xx,
2251 * STM32U585xx STM32U59xxx, STM32U5Axxx, STM32U5Fxxx
2252 and STM32U5Gxxx devices).
2253 * @arg PWR_SRAM4_FULL_RUN : SRAM4 full content retention.
2254 * @arg PWR_SRAM5_FULL_RUN : SRAM5 full content retention (available only for
2255 * STM32U59xxx, STM32U5Axxx, STM32U5Fxxx
2256 * and STM32U5Gxxx devices).
2257 * @arg PWR_SRAM6_FULL_RUN : SRAM6 full content retention (available only for
2258 * STM32U5Fxxx and STM32U5Gxxx devices).
2259 * @retval None.
2260 */
HAL_PWREx_EnableRAMsContentRunRetention(uint32_t RAMSelection)2261 void HAL_PWREx_EnableRAMsContentRunRetention(uint32_t RAMSelection)
2262 {
2263 /* Check the parameters */
2264 assert_param(IS_PWR_RAM_RUN_RETENTION(RAMSelection));
2265
2266 /* Enable RAM retention in Run mode */
2267 CLEAR_BIT(PWR->CR1, RAMSelection);
2268 }
2269
2270 /**
2271 * @brief Disable RAMs full content retention in Run mode.
2272 * @param RAMSelection : Specifies the SRAM content to be lost in Run mode.
2273 * This parameter can be one or a combination of the following values :
2274 * @arg PWR_SRAM1_FULL_RUN : SRAM1 full content lost.
2275 * @arg PWR_SRAM2_FULL_RUN : SRAM2 full content lost.
2276 * @arg PWR_SRAM3_FULL_RUN : SRAM3 full content lost (available only for STM32U575xx,
2277 * STM32U585xx STM32U59xxx, STM32U5Axxx, STM32U5Fxxx
2278 and STM32U5Gxxx devices).
2279 * @arg PWR_SRAM4_FULL_RUN : SRAM4 full content lost.
2280 * @arg PWR_SRAM5_FULL_RUN : SRAM5 full content retention (available only for
2281 * STM32U59xxx, STM32U5Axxx, STM32U5Fxxx
2282 * and STM32U5Gxxx devices).
2283 * @arg PWR_SRAM6_FULL_RUN : SRAM6 full content retention (available only for
2284 * STM32U5Fxxx and STM32U5Gxxx devices).
2285 * @retval None.
2286 */
HAL_PWREx_DisableRAMsContentRunRetention(uint32_t RAMSelection)2287 void HAL_PWREx_DisableRAMsContentRunRetention(uint32_t RAMSelection)
2288 {
2289 /* Check the parameters */
2290 assert_param(IS_PWR_RAM_RUN_RETENTION(RAMSelection));
2291
2292 /* Disable RAM retention in Run mode */
2293 SET_BIT(PWR->CR1, RAMSelection);
2294 }
2295
2296 /**
2297 * @brief Enable the Backup RAM retention in Standby, Shutdown and VBAT modes.
2298 * @note If BREN is reset, the backup RAM can still be used in Run, Sleep and
2299 * Stop modes. However, its content is lost in Standby, Shutdown and
2300 * VBAT modes.
2301 * @note This bit can be enabled only when LDO regulator is selected as
2302 * source supply.
2303 * @retval HAL Status.
2304 */
HAL_PWREx_EnableBkupRAMRetention(void)2305 HAL_StatusTypeDef HAL_PWREx_EnableBkupRAMRetention(void)
2306 {
2307 /*
2308 Backup RAM retention in Standby, Shutdown and VBAT should be enabled
2309 when the Vcore is alimented by the LDO regulator
2310 */
2311 if (HAL_PWREx_GetSupplyConfig() == PWR_LDO_SUPPLY)
2312 {
2313 SET_BIT(PWR->BDCR1, PWR_BDCR1_BREN);
2314 }
2315 /* SMPS regulator selected */
2316 else
2317 {
2318 return HAL_ERROR;
2319 }
2320
2321 return HAL_OK;
2322 }
2323
2324 /**
2325 * @brief Disable the Backup RAM retention in Standby, Shutdown and VBAT modes.
2326 * @note If BREN is reset, the backup RAM can still be used in Run, Sleep and
2327 * Stop modes. However, its content is lost in Standby, Shutdown and
2328 * VBAT modes. This bit can be writte
2329 * @retval None.
2330 */
HAL_PWREx_DisableBkupRAMRetention(void)2331 void HAL_PWREx_DisableBkupRAMRetention(void)
2332 {
2333 CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_BREN);
2334 }
2335
2336 /**
2337 * @brief Enable the flash memory fast wakeup from Stop 0 and Stop 1 modes.
2338 * @note This feature is used to obtain the best trade-off between low-power
2339 * consumption and wakeup time when exiting the Stop 0 or Stop 1 modes.
2340 * When this feature is enabled, the Flash memory remains in normal
2341 * mode in Stop 0 and Stop 1 modes, which offers a faster startup time
2342 * with higher consumption.
2343 * @retval None.
2344 */
HAL_PWREx_EnableFlashFastWakeUp(void)2345 void HAL_PWREx_EnableFlashFastWakeUp(void)
2346 {
2347 SET_BIT(PWR->CR2, PWR_CR2_FLASHFWU);
2348 }
2349
2350 /**
2351 * @brief Disable the Flash Power Down in Stop mode.
2352 * @note This feature is used to obtain the best trade-off between low-power
2353 * consumption and wakeup time when exiting the Stop 0 or Stop 1 modes.
2354 * When this feature is disabled, the Flash memory enters low-power
2355 * mode in Stop 0 and Stop 1 modes, which causes a slower startup time
2356 * with lower consumption.
2357 * @retval None.
2358 */
HAL_PWREx_DisableFlashFastWakeUp(void)2359 void HAL_PWREx_DisableFlashFastWakeUp(void)
2360 {
2361 CLEAR_BIT(PWR->CR2, PWR_CR2_FLASHFWU);
2362 }
2363
2364 /**
2365 * @brief Enable the SRAM4 memory fast wakeup from Stop 0, Stop 1 and Stop 2 modes.
2366 * @note This bit is used to obtain the best trade-off between low-power consumption
2367 * and wakeup time. SRAM4 wakeup time increases the wakeup time when exiting
2368 * Stop 0, Stop 1 and Stop 2 modes, and also increases the LPDMA access time
2369 * to SRAM4 during Stop modes.
2370 * @retval None.
2371 */
HAL_PWREx_EnableSRAM4FastWakeUp(void)2372 void HAL_PWREx_EnableSRAM4FastWakeUp(void)
2373 {
2374 SET_BIT(PWR->CR2, PWR_CR2_SRAM4FWU);
2375 }
2376
2377 /**
2378 * @brief Disable the SRAM4 memory fast wakeup from Stop 0, Stop 1 and Stop 2 modes.
2379 * @note This bit is used to obtain the best trade-off between low-power consumption
2380 * and wakeup time. SRAM4 wakeup time increases the wakeup time when exiting
2381 * Stop 0, Stop 1 and Stop 2 modes, and also increases the LPDMA access time
2382 * to SRAM4 during Stop modes.
2383 * @retval None.
2384 */
HAL_PWREx_DisableSRAM4FastWakeUp(void)2385 void HAL_PWREx_DisableSRAM4FastWakeUp(void)
2386 {
2387 CLEAR_BIT(PWR->CR2, PWR_CR2_SRAM4FWU);
2388 }
2389 /**
2390 * @}
2391 */
2392
2393 /** @defgroup PWREx_Exported_Functions_Group5 I/O Pull-Up Pull-Down Configuration Functions
2394 * @brief I/O pull-up / pull-down configuration functions
2395 *
2396 @verbatim
2397 ===============================================================================
2398 ##### I/O Pull-Up Pull-Down Configuration Functions #####
2399 ===============================================================================
2400 [..]
2401 In Standby and Shutdown mode, pull up and pull down can be configured to
2402 maintain an I/O in the selected state. If the APC bit in the PWR_APCR
2403 register is set, the I/Os can be configured either with a pull-up through
2404 PWR_PUCRx registers (x=A,B,C,D,E,F,G,H,I,J), or with a pull-down through
2405 PWR_PDCRx registers (x=A,B,C,D,E,F,G,H,I,J)), or can be kept in analog state
2406 if none of the PWR_PUCRx or PWR_PDCRx register is set.
2407 (+) Port J is available only for STM32U59xxx, STM32U5Axxx, STM32U5Fxxx
2408 and STM32U5Gxxx devices.
2409
2410 [..]
2411 The pull-down configuration has highest priority over pull-up
2412 configuration in case both PWR_PUCRx and PWR_PDCRx are set for the same
2413 I/O.
2414 This configuration is lost when exiting the Shutdown but not from Standby
2415 mode.
2416
2417 @endverbatim
2418 * @{
2419 */
2420
2421 /**
2422 * @brief Enable pull-up and pull-down configuration.
2423 * @note When APC bit is set, the I/O pull-up and pull-down configurations
2424 * defined in PWR_PUCRx and PWR_PDCRx registers are applied in Standby
2425 * and Shutdown modes.
2426 * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the
2427 * corresponding PDy bit of PWR_PDCRx register is also set (pull-down
2428 * configuration priority is higher). HAL_PWREx_EnableGPIOPullUp() and
2429 * HAL_PWREx_EnableGPIOPullDown() API's ensure there is no conflict
2430 * when setting PUy or PDy bit.
2431 * @retval None.
2432 */
HAL_PWREx_EnablePullUpPullDownConfig(void)2433 void HAL_PWREx_EnablePullUpPullDownConfig(void)
2434 {
2435 SET_BIT(PWR->APCR, PWR_APCR_APC);
2436 }
2437
2438 /**
2439 * @brief Disable pull-up and pull-down configuration.
2440 * @note When APC bit is cleared, the I/O pull-up and pull-down configurations
2441 * defined in PWR_PUCRx and PWR_PDCRx registers are not applied in
2442 * Standby and Shutdown modes.
2443 * @retval None.
2444 */
HAL_PWREx_DisablePullUpPullDownConfig(void)2445 void HAL_PWREx_DisablePullUpPullDownConfig(void)
2446 {
2447 CLEAR_BIT(PWR->APCR, PWR_APCR_APC);
2448 }
2449
2450 /**
2451 * @brief Enable GPIO pull-up state in Standby and Shutdown modes.
2452 * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O
2453 * in pull-up state in Standby and Shutdown modes.
2454 * @note This state is effective in Standby and Shutdown modes only if APC
2455 * bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
2456 * @note The configuration is lost when exiting the Shutdown mode due to the
2457 * power-on reset, maintained when exiting the Standby mode.
2458 * @note To avoid any conflict at Standby and Shutdown modes exits, the
2459 * corresponding PDy bit of PWR_PDCRx register is cleared unless it is
2460 * reserved.
2461 * @note Even if a PUy bit to set is reserved, the other PUy bits entered as
2462 * input parameter at the same time are set.
2463 * @param GPIO_Port : Specify the IO port.
2464 * This parameter can be a value of
2465 * @ref PWREx_GPIO_Port.
2466 * @param GPIO_Pin : Specify the I/O pins numbers.
2467 * This parameter can be a value of
2468 * @ref PWREx_GPIO_Pin_Mask.
2469 * @retval HAL Status.
2470 */
HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO_Port,uint32_t GPIO_Pin)2471 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin)
2472 {
2473 /* Check the parameters */
2474 assert_param(IS_PWR_GPIO_PORT(GPIO_Port));
2475 assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin));
2476
2477 /* Check GPIO port */
2478 switch (GPIO_Port)
2479 {
2480 case PWR_GPIO_A: /* Apply Pull Up to GPIO port A */
2481 SET_BIT(PWR->PUCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_14))));
2482 CLEAR_BIT(PWR->PDCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_13 | PWR_GPIO_BIT_15))));
2483 break;
2484
2485 case PWR_GPIO_B: /* Apply Pull Up to GPIO port B */
2486 SET_BIT(PWR->PUCRB, GPIO_Pin);
2487 CLEAR_BIT(PWR->PDCRB, (GPIO_Pin & (~(PWR_GPIO_BIT_4))));
2488 break;
2489
2490 case PWR_GPIO_C: /* Apply Pull Up to GPIO port C */
2491 SET_BIT(PWR->PUCRC, GPIO_Pin);
2492 CLEAR_BIT(PWR->PDCRC, GPIO_Pin);
2493 break;
2494
2495 case PWR_GPIO_D: /* Apply Pull Up to GPIO port D */
2496 SET_BIT(PWR->PUCRD, GPIO_Pin);
2497 CLEAR_BIT(PWR->PDCRD, GPIO_Pin);
2498 break;
2499
2500 case PWR_GPIO_E: /* Apply Pull Up to GPIO port E */
2501 SET_BIT(PWR->PUCRE, GPIO_Pin);
2502 CLEAR_BIT(PWR->PDCRE, GPIO_Pin);
2503 break;
2504
2505 #ifdef PWR_PUCRF_PU0
2506 case PWR_GPIO_F: /* Apply Pull Up to GPIO port F */
2507 SET_BIT(PWR->PUCRF, GPIO_Pin);
2508 CLEAR_BIT(PWR->PDCRF, GPIO_Pin);
2509 break;
2510 #endif /* PWR_PUCRF_PU0 */
2511
2512 case PWR_GPIO_G: /* Apply Pull Up to GPIO port G */
2513 SET_BIT(PWR->PUCRG, GPIO_Pin);
2514 CLEAR_BIT(PWR->PDCRG, GPIO_Pin);
2515 break;
2516
2517 case PWR_GPIO_H: /* Apply Pull Up to GPIO port H */
2518 SET_BIT(PWR->PUCRH, GPIO_Pin);
2519 CLEAR_BIT(PWR->PDCRH, GPIO_Pin);
2520 break;
2521
2522 #ifdef PWR_PUCRI_PU0
2523 case PWR_GPIO_I: /* Apply Pull Up to GPIO port I */
2524 SET_BIT(PWR->PUCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS));
2525 CLEAR_BIT(PWR->PDCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS));
2526 break;
2527 #endif /* PWR_PUCRI_PU0 */
2528
2529 #if defined (PWR_PUCRJ_PU0)
2530 case PWR_GPIO_J: /* Apply Pull Up to GPIO port J */
2531 SET_BIT(PWR->PUCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS));
2532 CLEAR_BIT(PWR->PDCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS));
2533 break;
2534 #endif /* defined (PWR_PUCRJ_PU0) */
2535
2536 default:
2537 return HAL_ERROR;
2538 break;
2539 }
2540
2541 return HAL_OK;
2542 }
2543
2544 /**
2545 * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes.
2546 * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure
2547 * the I/O in pull-up state in Standby and Shutdown modes.
2548 * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as
2549 * input parameter at the same time are reset.
2550 * @param GPIO_Port : Specify the IO port.
2551 * This parameter can be a value of
2552 * @ref PWREx_GPIO_Port.
2553 * @param GPIO_Pin : Specify the I/O pins numbers.
2554 * This parameter can be a value of
2555 * @ref PWREx_GPIO_Pin_Mask.
2556 * @retval HAL Status.
2557 */
HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO_Port,uint32_t GPIO_Pin)2558 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin)
2559 {
2560 /* Check the parameters */
2561 assert_param(IS_PWR_GPIO_PORT(GPIO_Port));
2562 assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin));
2563
2564 /* Check GPIO port */
2565 switch (GPIO_Port)
2566 {
2567 case PWR_GPIO_A: /* Disable Pull Up for GPIO port A */
2568 CLEAR_BIT(PWR->PUCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_14))));
2569 break;
2570
2571 case PWR_GPIO_B: /* Disable Pull Up for GPIO port B */
2572 CLEAR_BIT(PWR->PUCRB, GPIO_Pin);
2573 break;
2574
2575 case PWR_GPIO_C: /* Disable Pull Up for GPIO port C */
2576 CLEAR_BIT(PWR->PUCRC, GPIO_Pin);
2577 break;
2578
2579 case PWR_GPIO_D: /* Disable Pull Up for GPIO port D */
2580 CLEAR_BIT(PWR->PUCRD, GPIO_Pin);
2581 break;
2582
2583 case PWR_GPIO_E: /* Disable Pull Up for GPIO port E */
2584 CLEAR_BIT(PWR->PUCRE, GPIO_Pin);
2585 break;
2586
2587 #ifdef PWR_PUCRF_PU0
2588 case PWR_GPIO_F: /* Disable Pull Up for GPIO port F */
2589 CLEAR_BIT(PWR->PUCRF, GPIO_Pin);
2590 break;
2591 #endif /* PWR_PUCRF_PU0 */
2592
2593 case PWR_GPIO_G: /* Disable Pull Up for GPIO port G */
2594 CLEAR_BIT(PWR->PUCRG, GPIO_Pin);
2595 break;
2596
2597 case PWR_GPIO_H: /* Disable Pull Up for GPIO port H */
2598 CLEAR_BIT(PWR->PUCRH, GPIO_Pin);
2599 break;
2600
2601 #ifdef PWR_PUCRI_PU0
2602 case PWR_GPIO_I: /* Disable Pull Up for GPIO port I */
2603 CLEAR_BIT(PWR->PUCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS));
2604 break;
2605 #endif /* PWR_PUCRI_PU0 */
2606
2607 #if defined (PWR_PUCRJ_PU0)
2608 case PWR_GPIO_J: /* Disable Pull Up for GPIO port J */
2609 CLEAR_BIT(PWR->PUCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS));
2610 break;
2611 #endif /* defined (PWR_PUCRJ_PU0) */
2612
2613 default:
2614 return HAL_ERROR;
2615 break;
2616 }
2617
2618 return HAL_OK;
2619 }
2620
2621 /**
2622 * @brief Enable GPIO pull-down state in Standby and Shutdown modes.
2623 * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O
2624 * in pull-down state in Standby and Shutdown modes.
2625 * @note This state is effective in Standby and Shutdown modes only if APC bit
2626 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
2627 * @note The configuration is lost when exiting the Shutdown mode due to the
2628 * power-on reset, maintained when exiting the Standby mode.
2629 * @note To avoid any conflict at Standby and Shutdown modes exits, the
2630 * corresponding PUy bit of PWR_PUCRx register is cleared unless it is
2631 * reserved.
2632 * @note Even if a PDy bit to set is reserved, the other PDy bits entered as
2633 * input parameter at the same time are set.
2634 * @param GPIO_Port : Specify the IO port.
2635 * This parameter can be a value of
2636 * @ref PWREx_GPIO_Port.
2637 * @param GPIO_Pin : Specify the I/O pins numbers.
2638 * This parameter can be a value of
2639 * @ref PWREx_GPIO_Pin_Mask.
2640 * @retval HAL Status.
2641 */
HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO_Port,uint32_t GPIO_Pin)2642 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin)
2643 {
2644 /* Check the parameters */
2645 assert_param(IS_PWR_GPIO_PORT(GPIO_Port));
2646 assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin));
2647
2648 /* Check GPIO port */
2649 switch (GPIO_Port)
2650 {
2651 case PWR_GPIO_A: /* Apply Pull Down to GPIO port A */
2652 SET_BIT(PWR->PDCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_13 | PWR_GPIO_BIT_15))));
2653 CLEAR_BIT(PWR->PUCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_14))));
2654 break;
2655
2656 case PWR_GPIO_B: /* Apply Pull Down to GPIO port B */
2657 SET_BIT(PWR->PDCRB, (GPIO_Pin & (~(PWR_GPIO_BIT_4))));
2658 CLEAR_BIT(PWR->PUCRB, GPIO_Pin);
2659 break;
2660
2661 case PWR_GPIO_C: /* Apply Pull Down to GPIO port C */
2662 SET_BIT(PWR->PDCRC, GPIO_Pin);
2663 CLEAR_BIT(PWR->PUCRC, GPIO_Pin);
2664 break;
2665
2666 case PWR_GPIO_D: /* Apply Pull Down to GPIO port D */
2667 SET_BIT(PWR->PDCRD, GPIO_Pin);
2668 CLEAR_BIT(PWR->PUCRD, GPIO_Pin);
2669 break;
2670
2671 case PWR_GPIO_E: /* Apply Pull Down to GPIO port E */
2672 SET_BIT(PWR->PDCRE, GPIO_Pin);
2673 CLEAR_BIT(PWR->PUCRE, GPIO_Pin);
2674 break;
2675
2676 #ifdef PWR_PUCRF_PU0
2677 case PWR_GPIO_F: /* Apply Pull Down to GPIO port F */
2678 SET_BIT(PWR->PDCRF, GPIO_Pin);
2679 CLEAR_BIT(PWR->PUCRF, GPIO_Pin);
2680 break;
2681 #endif /* PWR_PUCRF_PU0 */
2682
2683 case PWR_GPIO_G: /* Apply Pull Down to GPIO port G */
2684 SET_BIT(PWR->PDCRG, GPIO_Pin);
2685 CLEAR_BIT(PWR->PUCRG, GPIO_Pin);
2686 break;
2687
2688 case PWR_GPIO_H: /* Apply Pull Down to GPIO port H */
2689 SET_BIT(PWR->PDCRH, GPIO_Pin);
2690 CLEAR_BIT(PWR->PUCRH, GPIO_Pin);
2691 break;
2692
2693 #ifdef PWR_PUCRI_PU0
2694 case PWR_GPIO_I: /* Apply Pull Down to GPIO port I */
2695 SET_BIT(PWR->PDCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS));
2696 CLEAR_BIT(PWR->PUCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS));
2697 break;
2698 #endif /* PWR_PUCRI_PU0 */
2699
2700 #if defined (PWR_PUCRJ_PU0)
2701 case PWR_GPIO_J: /* Apply Pull Down to GPIO port J */
2702 SET_BIT(PWR->PDCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS));
2703 CLEAR_BIT(PWR->PUCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS));
2704 break;
2705 #endif /* defined (PWR_PUCRJ_PU0) */
2706
2707 default:
2708 return HAL_ERROR;
2709 break;
2710 }
2711
2712 return HAL_OK;
2713 }
2714
2715 /**
2716 * @brief Disable GPIO pull-down state in Standby and Shutdown modes.
2717 * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O
2718 * in pull-down state in Standby and Shutdown modes.
2719 * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input
2720 * parameter at the same time are reset.
2721 * @param GPIO_Port : Specify the IO port.
2722 * This parameter can be a value of
2723 * @ref PWREx_GPIO_Port.
2724 * @param GPIO_Pin : Specify the I/O pins numbers.
2725 * This parameter can be a value of
2726 * @ref PWREx_GPIO_Pin_Mask.
2727 * @retval HAL Status.
2728 */
HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO_Port,uint32_t GPIO_Pin)2729 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin)
2730 {
2731 /* Check the parameters */
2732 assert_param(IS_PWR_GPIO_PORT(GPIO_Port));
2733 assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin));
2734
2735 /* Check GPIO port */
2736 switch (GPIO_Port)
2737 {
2738 case PWR_GPIO_A: /* Disable Pull Down for GPIO port A */
2739 CLEAR_BIT(PWR->PDCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_13 | PWR_GPIO_BIT_15))));
2740 break;
2741
2742 case PWR_GPIO_B: /* Disable Pull Down for GPIO port B */
2743 CLEAR_BIT(PWR->PDCRB, (GPIO_Pin & (~(PWR_GPIO_BIT_4))));
2744 break;
2745
2746 case PWR_GPIO_C: /* Disable Pull Down for GPIO port C */
2747 CLEAR_BIT(PWR->PDCRC, GPIO_Pin);
2748 break;
2749
2750 case PWR_GPIO_D: /* Disable Pull Down for GPIO port D */
2751 CLEAR_BIT(PWR->PDCRD, GPIO_Pin);
2752 break;
2753
2754 case PWR_GPIO_E: /* Disable Pull Down for GPIO port E */
2755 CLEAR_BIT(PWR->PDCRE, GPIO_Pin);
2756 break;
2757
2758 #ifdef PWR_PUCRF_PU0
2759 case PWR_GPIO_F: /* Disable Pull Down for GPIO port F */
2760 CLEAR_BIT(PWR->PDCRF, GPIO_Pin);
2761 break;
2762 #endif /* PWR_PUCRF_PU0 */
2763
2764 case PWR_GPIO_G: /* Disable Pull Down for GPIO port G */
2765 CLEAR_BIT(PWR->PDCRG, GPIO_Pin);
2766 break;
2767
2768 case PWR_GPIO_H: /* Disable Pull Down for GPIO port H */
2769 CLEAR_BIT(PWR->PDCRH, GPIO_Pin);
2770 break;
2771
2772 #ifdef PWR_PUCRI_PU0
2773 case PWR_GPIO_I: /* Disable Pull Down for GPIO port I */
2774 CLEAR_BIT(PWR->PDCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS));
2775 break;
2776 #endif /* PWR_PUCRI_PU0 */
2777
2778 #if defined (PWR_PUCRJ_PU0)
2779 case PWR_GPIO_J: /* Disable Pull Down for GPIO port J */
2780 CLEAR_BIT(PWR->PDCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS));
2781 break;
2782 #endif /* defined (PWR_PUCRJ_PU0) */
2783
2784 default:
2785 return HAL_ERROR;
2786 break;
2787 }
2788
2789 return HAL_OK;
2790 }
2791 /**
2792 * @}
2793 */
2794
2795 #endif /* defined (HAL_PWR_MODULE_ENABLED) */
2796
2797 /**
2798 * @}
2799 */
2800
2801 /**
2802 * @}
2803 */
2804
2805 /**
2806 * @}
2807 */
2808
