1 /**
2 ******************************************************************************
3 * @file stm32u5xx_ll_rng.h
4 * @author MCD Application Team
5 * @brief Header file of RNG LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32U5xx_LL_RNG_H
21 #define STM32U5xx_LL_RNG_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32u5xx.h"
29
30 /** @addtogroup STM32U5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (RNG)
35
36 /** @defgroup RNG_LL RNG
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private defines -----------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /* Private macros ------------------------------------------------------------*/
45
46 /* Exported types ------------------------------------------------------------*/
47 #if defined(USE_FULL_LL_DRIVER)
48 /** @defgroup RNG_LL_ES_Init_Struct RNG Exported Init structures
49 * @{
50 */
51
52
53 /**
54 * @brief LL RNG Init Structure Definition
55 */
56 typedef struct
57 {
58 uint32_t ClockErrorDetection; /*!< Clock error detection.
59 This parameter can be one value of @ref RNG_LL_CED.
60 This parameter can be modified using unitary
61 functions @ref LL_RNG_EnableClkErrorDetect(). */
62 } LL_RNG_InitTypeDef;
63
64 /**
65 * @}
66 */
67 #endif /* USE_FULL_LL_DRIVER */
68 /* Exported constants --------------------------------------------------------*/
69 /** @defgroup RNG_LL_Exported_Constants RNG Exported Constants
70 * @{
71 */
72
73 /** @defgroup RNG_LL_CED Clock Error Detection
74 * @{
75 */
76 #define LL_RNG_CED_ENABLE 0x00000000U /*!< Clock error detection enabled */
77 #define LL_RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection disabled */
78 /**
79 * @}
80 */
81 /** @defgroup RNG_LL_ARDIS Auto reset disable
82 * @{
83 */
84 #define LL_RNG_ARDIS_ENABLE 0x00000000U /*!< ARDIS enabled automatic reset to clear SECS bit*/
85 #define LL_RNG_ARDIS_DISABLE RNG_CR_ARDIS /*!< ARDIS disabled no automatic reset to clear SECS bit*/
86 /**
87 * @}
88 */
89
90 /** @defgroup RNG_LL_Clock_Divider_Factor Value used to configure an internal
91 * programmable divider acting on the incoming RNG clock
92 * @{
93 */
94 #define LL_RNG_CLKDIV_BY_1 (0x00000000UL) /*!< No clock division */
95 #define LL_RNG_CLKDIV_BY_2 (RNG_CR_CLKDIV_0) /*!< 2 RNG clock cycles per internal RNG clock */
96 #define LL_RNG_CLKDIV_BY_4 (RNG_CR_CLKDIV_1) /*!< 4 RNG clock cycles per internal RNG clock */
97 #define LL_RNG_CLKDIV_BY_8 (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 8 RNG clock cycles per internal RNG clock */
98 #define LL_RNG_CLKDIV_BY_16 (RNG_CR_CLKDIV_2) /*!< 16 RNG clock cycles per internal RNG clock */
99 #define LL_RNG_CLKDIV_BY_32 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) /*!< 32 RNG clock cycles per internal RNG clock */
100 #define LL_RNG_CLKDIV_BY_64 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) /*!< 64 RNG clock cycles per internal RNG clock */
101 #define LL_RNG_CLKDIV_BY_128 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 128 RNG clock cycles per internal RNG clock */
102 #define LL_RNG_CLKDIV_BY_256 (RNG_CR_CLKDIV_3) /*!< 256 RNG clock cycles per internal RNG clock */
103 #define LL_RNG_CLKDIV_BY_512 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0) /*!< 512 RNG clock cycles per internal RNG clock */
104 #define LL_RNG_CLKDIV_BY_1024 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1) /*!< 1024 RNG clock cycles per internal RNG clock */
105 #define LL_RNG_CLKDIV_BY_2048 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 2048 RNG clock cycles per internal RNG clock */
106 #define LL_RNG_CLKDIV_BY_4096 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2) /*!< 4096 RNG clock cycles per internal RNG clock */
107 #define LL_RNG_CLKDIV_BY_8192 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) /*!< 8192 RNG clock cycles per internal RNG clock */
108 #define LL_RNG_CLKDIV_BY_16384 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) /*!< 16384 RNG clock cycles per internal RNG clock */
109 #define LL_RNG_CLKDIV_BY_32768 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 32768 RNG clock cycles per internal RNG clock */
110 /**
111 * @}
112 */
113
114 /** @defgroup RNG_LL_NIST_Compliance NIST Compliance configuration
115 * @{
116 */
117 #define LL_RNG_NIST_COMPLIANT (0x00000000UL) /*!< Default NIST compliant configuration*/
118 #define LL_RNG_CUSTOM_NIST (RNG_CR_NISTC) /*!< Custom NIST configuration */
119
120 /**
121 * @}
122 */
123
124 /** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
125 * @brief Flags defines which can be used with LL_RNG_ReadReg function
126 * @{
127 */
128 #define LL_RNG_SR_DRDY RNG_SR_DRDY /*!< Register contains valid random data */
129 #define LL_RNG_SR_CECS RNG_SR_CECS /*!< Clock error current status */
130 #define LL_RNG_SR_SECS RNG_SR_SECS /*!< Seed error current status */
131 #define LL_RNG_SR_CEIS RNG_SR_CEIS /*!< Clock error interrupt status */
132 #define LL_RNG_SR_SEIS RNG_SR_SEIS /*!< Seed error interrupt status */
133 /**
134 * @}
135 */
136
137 /** @defgroup RNG_LL_EC_IT IT Defines
138 * @brief IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros
139 * @{
140 */
141 #define LL_RNG_CR_IE RNG_CR_IE /*!< RNG Interrupt enable */
142 /**
143 * @}
144 */
145
146 /**
147 * @}
148 */
149
150 /* Exported macro ------------------------------------------------------------*/
151 /** @defgroup RNG_LL_Exported_Macros RNG Exported Macros
152 * @{
153 */
154
155 /** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros
156 * @{
157 */
158
159 /**
160 * @brief Write a value in RNG register
161 * @param __INSTANCE__ RNG Instance
162 * @param __REG__ Register to be written
163 * @param __VALUE__ Value to be written in the register
164 * @retval None
165 */
166 #define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
167
168 /**
169 * @brief Read a value in RNG register
170 * @param __INSTANCE__ RNG Instance
171 * @param __REG__ Register to be read
172 * @retval Register value
173 */
174 #define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
175 /**
176 * @}
177 */
178
179 /**
180 * @}
181 */
182
183
184 /* Exported functions --------------------------------------------------------*/
185 /** @defgroup RNG_LL_Exported_Functions RNG Exported Functions
186 * @{
187 */
188 /** @defgroup RNG_LL_EF_Configuration RNG Configuration functions
189 * @{
190 */
191
192 /**
193 * @brief Enable Random Number Generation
194 * @rmtoll CR RNGEN LL_RNG_Enable
195 * @param RNGx RNG Instance
196 * @retval None
197 */
LL_RNG_Enable(RNG_TypeDef * RNGx)198 __STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx)
199 {
200 SET_BIT(RNGx->CR, RNG_CR_RNGEN);
201 }
202
203 /**
204 * @brief Disable Random Number Generation
205 * @rmtoll CR RNGEN LL_RNG_Disable
206 * @param RNGx RNG Instance
207 * @retval None
208 */
LL_RNG_Disable(RNG_TypeDef * RNGx)209 __STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
210 {
211 CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN);
212 }
213
214 /**
215 * @brief Check if Random Number Generator is enabled
216 * @rmtoll CR RNGEN LL_RNG_IsEnabled
217 * @param RNGx RNG Instance
218 * @retval State of bit (1 or 0).
219 */
LL_RNG_IsEnabled(const RNG_TypeDef * RNGx)220 __STATIC_INLINE uint32_t LL_RNG_IsEnabled(const RNG_TypeDef *RNGx)
221 {
222 return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL);
223 }
224
225 /**
226 * @brief Enable Clock Error Detection
227 * @rmtoll CR CED LL_RNG_EnableClkErrorDetect
228 * @param RNGx RNG Instance
229 * @retval None
230 */
LL_RNG_EnableClkErrorDetect(RNG_TypeDef * RNGx)231 __STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx)
232 {
233 CLEAR_BIT(RNGx->CR, RNG_CR_CED);
234 }
235
236 /**
237 * @brief Disable RNG Clock Error Detection
238 * @rmtoll CR CED LL_RNG_DisableClkErrorDetect
239 * @param RNGx RNG Instance
240 * @retval None
241 */
LL_RNG_DisableClkErrorDetect(RNG_TypeDef * RNGx)242 __STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx)
243 {
244 SET_BIT(RNGx->CR, RNG_CR_CED);
245 }
246
247 /**
248 * @brief Check if RNG Clock Error Detection is enabled
249 * @rmtoll CR CED LL_RNG_IsEnabledClkErrorDetect
250 * @param RNGx RNG Instance
251 * @retval State of bit (1 or 0).
252 */
LL_RNG_IsEnabledClkErrorDetect(const RNG_TypeDef * RNGx)253 __STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(const RNG_TypeDef *RNGx)
254 {
255 return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL);
256 }
257
258 /**
259 * @brief Set RNG Conditioning Soft Reset bit
260 * @rmtoll CR CONDRST LL_RNG_EnableCondReset
261 * @param RNGx RNG Instance
262 * @retval None
263 */
LL_RNG_EnableCondReset(RNG_TypeDef * RNGx)264 __STATIC_INLINE void LL_RNG_EnableCondReset(RNG_TypeDef *RNGx)
265 {
266 SET_BIT(RNGx->CR, RNG_CR_CONDRST);
267 }
268
269 /**
270 * @brief Reset RNG Conditioning Soft Reset bit
271 * @rmtoll CR CONDRST LL_RNG_DisableCondReset
272 * @param RNGx RNG Instance
273 * @retval None
274 */
LL_RNG_DisableCondReset(RNG_TypeDef * RNGx)275 __STATIC_INLINE void LL_RNG_DisableCondReset(RNG_TypeDef *RNGx)
276 {
277 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
278 }
279
280 /**
281 * @brief Check if RNG Conditioning Soft Reset bit is set
282 * @rmtoll CR CONDRST LL_RNG_IsEnabledCondReset
283 * @param RNGx RNG Instance
284 * @retval State of bit (1 or 0).
285 */
LL_RNG_IsEnabledCondReset(const RNG_TypeDef * RNGx)286 __STATIC_INLINE uint32_t LL_RNG_IsEnabledCondReset(const RNG_TypeDef *RNGx)
287 {
288 return ((READ_BIT(RNGx->CR, RNG_CR_CONDRST) == (RNG_CR_CONDRST)) ? 1UL : 0UL);
289 }
290
291 /**
292 * @brief Enable RNG Config Lock
293 * @rmtoll CR CONFIGLOCK LL_RNG_ConfigLock
294 * @param RNGx RNG Instance
295 * @retval None
296 */
LL_RNG_ConfigLock(RNG_TypeDef * RNGx)297 __STATIC_INLINE void LL_RNG_ConfigLock(RNG_TypeDef *RNGx)
298 {
299 SET_BIT(RNGx->CR, RNG_CR_CONFIGLOCK);
300 }
301
302 /**
303 * @brief Check if RNG Config Lock is enabled
304 * @rmtoll CR CONFIGLOCK LL_RNG_IsConfigLocked
305 * @param RNGx RNG Instance
306 * @retval State of bit (1 or 0).
307 */
LL_RNG_IsConfigLocked(const RNG_TypeDef * RNGx)308 __STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(const RNG_TypeDef *RNGx)
309 {
310 return ((READ_BIT(RNGx->CR, RNG_CR_CONFIGLOCK) == (RNG_CR_CONFIGLOCK)) ? 1UL : 0UL);
311 }
312
313 /**
314 * @brief Enable NIST Compliance
315 * @rmtoll CR NISTC LL_RNG_EnableNistCompliance
316 * @param RNGx RNG Instance
317 * @retval None
318 */
LL_RNG_EnableNistCompliance(RNG_TypeDef * RNGx)319 __STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx)
320 {
321 CLEAR_BIT(RNGx->CR, RNG_CR_NISTC);
322 }
323
324 /**
325 * @brief Disable NIST Compliance
326 * @rmtoll CR NISTC LL_RNG_DisableNistCompliance
327 * @param RNGx RNG Instance
328 * @retval None
329 */
LL_RNG_DisableNistCompliance(RNG_TypeDef * RNGx)330 __STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx)
331 {
332 SET_BIT(RNGx->CR, RNG_CR_NISTC);
333 }
334
335 /**
336 * @brief Check if NIST Compliance is enabled
337 * @rmtoll CR NISTC LL_RNG_IsEnabledNistCompliance
338 * @param RNGx RNG Instance
339 * @retval State of bit (1 or 0).
340 */
LL_RNG_IsEnabledNistCompliance(const RNG_TypeDef * RNGx)341 __STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(const RNG_TypeDef *RNGx)
342 {
343 return ((READ_BIT(RNGx->CR, RNG_CR_NISTC) != (RNG_CR_NISTC)) ? 1UL : 0UL);
344 }
345
346 /**
347 * @brief Set RNG Config1 Configuration field value
348 * @rmtoll CR RNG_CONFIG1 LL_RNG_SetConfig1
349 * @param RNGx RNG Instance
350 * @param Config1 Value between 0 and 0x3F
351 * @retval None
352 */
LL_RNG_SetConfig1(RNG_TypeDef * RNGx,uint32_t Config1)353 __STATIC_INLINE void LL_RNG_SetConfig1(RNG_TypeDef *RNGx, uint32_t Config1)
354 {
355 MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG1, Config1 << RNG_CR_RNG_CONFIG1_Pos);
356 }
357
358 /**
359 * @brief Get RNG Config1 Configuration field value
360 * @rmtoll CR RNG_CONFIG1 LL_RNG_GetConfig1
361 * @param RNGx RNG Instance
362 * @retval Returned Value expressed on 6 bits : Value between 0 and 0x3F
363 */
LL_RNG_GetConfig1(const RNG_TypeDef * RNGx)364 __STATIC_INLINE uint32_t LL_RNG_GetConfig1(const RNG_TypeDef *RNGx)
365 {
366 return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos);
367 }
368
369 /**
370 * @brief Set RNG Config2 Configuration field value
371 * @rmtoll CR RNG_CONFIG2 LL_RNG_SetConfig2
372 * @param RNGx RNG Instance
373 * @param Config2 Value between 0 and 0x7
374 * @retval None
375 */
LL_RNG_SetConfig2(RNG_TypeDef * RNGx,uint32_t Config2)376 __STATIC_INLINE void LL_RNG_SetConfig2(RNG_TypeDef *RNGx, uint32_t Config2)
377 {
378 MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG2, Config2 << RNG_CR_RNG_CONFIG2_Pos);
379 }
380
381 /**
382 * @brief Get RNG Config2 Configuration field value
383 * @rmtoll CR RNG_CONFIG2 LL_RNG_GetConfig2
384 * @param RNGx RNG Instance
385 * @retval Returned Value expressed on 3 bits : Value between 0 and 0x7
386 */
LL_RNG_GetConfig2(const RNG_TypeDef * RNGx)387 __STATIC_INLINE uint32_t LL_RNG_GetConfig2(const RNG_TypeDef *RNGx)
388 {
389 return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos);
390 }
391
392 /**
393 * @brief Set RNG Config3 Configuration field value
394 * @rmtoll CR RNG_CONFIG3 LL_RNG_SetConfig3
395 * @param RNGx RNG Instance
396 * @param Config3 Value between 0 and 0xF
397 * @retval None
398 */
LL_RNG_SetConfig3(RNG_TypeDef * RNGx,uint32_t Config3)399 __STATIC_INLINE void LL_RNG_SetConfig3(RNG_TypeDef *RNGx, uint32_t Config3)
400 {
401 MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG3, Config3 << RNG_CR_RNG_CONFIG3_Pos);
402 }
403
404 /**
405 * @brief Get RNG Config3 Configuration field value
406 * @rmtoll CR RNG_CONFIG3 LL_RNG_GetConfig3
407 * @param RNGx RNG Instance
408 * @retval Returned Value expressed on 4 bits : Value between 0 and 0xF
409 */
LL_RNG_GetConfig3(const RNG_TypeDef * RNGx)410 __STATIC_INLINE uint32_t LL_RNG_GetConfig3(const RNG_TypeDef *RNGx)
411 {
412 return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos);
413 }
414
415 /**
416 * @brief Set RNG Clock divider factor
417 * @rmtoll CR CLKDIV LL_RNG_SetClockDivider
418 * @param RNGx RNG Instance
419 * @param Divider can be one of the following values:
420 * @arg @ref LL_RNG_CLKDIV_BY_1
421 * @arg @ref LL_RNG_CLKDIV_BY_2
422 * @arg @ref LL_RNG_CLKDIV_BY_4
423 * @arg @ref LL_RNG_CLKDIV_BY_8
424 * @arg @ref LL_RNG_CLKDIV_BY_16
425 * @arg @ref LL_RNG_CLKDIV_BY_32
426 * @arg @ref LL_RNG_CLKDIV_BY_64
427 * @arg @ref LL_RNG_CLKDIV_BY_128
428 * @arg @ref LL_RNG_CLKDIV_BY_256
429 * @arg @ref LL_RNG_CLKDIV_BY_512
430 * @arg @ref LL_RNG_CLKDIV_BY_1024
431 * @arg @ref LL_RNG_CLKDIV_BY_2048
432 * @arg @ref LL_RNG_CLKDIV_BY_4096
433 * @arg @ref LL_RNG_CLKDIV_BY_8192
434 * @arg @ref LL_RNG_CLKDIV_BY_16384
435 * @arg @ref LL_RNG_CLKDIV_BY_32768
436 * @retval None
437 */
LL_RNG_SetClockDivider(RNG_TypeDef * RNGx,uint32_t Divider)438 __STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider)
439 {
440 MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV, Divider << RNG_CR_CLKDIV_Pos);
441 }
442
443 /**
444 * @brief Get RNG Clock divider factor
445 * @rmtoll CR CLKDIV LL_RNG_GetClockDivider
446 * @param RNGx RNG Instance
447 * @retval Returned value can be one of the following values:
448 * @arg @ref LL_RNG_CLKDIV_BY_1
449 * @arg @ref LL_RNG_CLKDIV_BY_2
450 * @arg @ref LL_RNG_CLKDIV_BY_4
451 * @arg @ref LL_RNG_CLKDIV_BY_8
452 * @arg @ref LL_RNG_CLKDIV_BY_16
453 * @arg @ref LL_RNG_CLKDIV_BY_32
454 * @arg @ref LL_RNG_CLKDIV_BY_64
455 * @arg @ref LL_RNG_CLKDIV_BY_128
456 * @arg @ref LL_RNG_CLKDIV_BY_256
457 * @arg @ref LL_RNG_CLKDIV_BY_512
458 * @arg @ref LL_RNG_CLKDIV_BY_1024
459 * @arg @ref LL_RNG_CLKDIV_BY_2048
460 * @arg @ref LL_RNG_CLKDIV_BY_4096
461 * @arg @ref LL_RNG_CLKDIV_BY_8192
462 * @arg @ref LL_RNG_CLKDIV_BY_16384
463 * @arg @ref LL_RNG_CLKDIV_BY_32768
464 */
LL_RNG_GetClockDivider(const RNG_TypeDef * RNGx)465 __STATIC_INLINE uint32_t LL_RNG_GetClockDivider(const RNG_TypeDef *RNGx)
466 {
467 return (uint32_t)READ_BIT(RNGx->CR, RNG_CR_CLKDIV);
468 }
469 /**
470 * @}
471 */
472
473 /** @defgroup RNG_LL_EF_FLAG_Management FLAG Management
474 * @{
475 */
476
477 /**
478 * @brief Indicate if the RNG Data ready Flag is set or not
479 * @rmtoll SR DRDY LL_RNG_IsActiveFlag_DRDY
480 * @param RNGx RNG Instance
481 * @retval State of bit (1 or 0).
482 */
LL_RNG_IsActiveFlag_DRDY(const RNG_TypeDef * RNGx)483 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(const RNG_TypeDef *RNGx)
484 {
485 return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL);
486 }
487
488 /**
489 * @brief Indicate if the Clock Error Current Status Flag is set or not
490 * @rmtoll SR CECS LL_RNG_IsActiveFlag_CECS
491 * @param RNGx RNG Instance
492 * @retval State of bit (1 or 0).
493 */
LL_RNG_IsActiveFlag_CECS(const RNG_TypeDef * RNGx)494 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(const RNG_TypeDef *RNGx)
495 {
496 return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL);
497 }
498
499 /**
500 * @brief Indicate if the Seed Error Current Status Flag is set or not
501 * @rmtoll SR SECS LL_RNG_IsActiveFlag_SECS
502 * @param RNGx RNG Instance
503 * @retval State of bit (1 or 0).
504 */
LL_RNG_IsActiveFlag_SECS(const RNG_TypeDef * RNGx)505 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(const RNG_TypeDef *RNGx)
506 {
507 return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL);
508 }
509
510 /**
511 * @brief Indicate if the Clock Error Interrupt Status Flag is set or not
512 * @rmtoll SR CEIS LL_RNG_IsActiveFlag_CEIS
513 * @param RNGx RNG Instance
514 * @retval State of bit (1 or 0).
515 */
LL_RNG_IsActiveFlag_CEIS(const RNG_TypeDef * RNGx)516 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(const RNG_TypeDef *RNGx)
517 {
518 return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL);
519 }
520
521 /**
522 * @brief Indicate if the Seed Error Interrupt Status Flag is set or not
523 * @rmtoll SR SEIS LL_RNG_IsActiveFlag_SEIS
524 * @param RNGx RNG Instance
525 * @retval State of bit (1 or 0).
526 */
LL_RNG_IsActiveFlag_SEIS(const RNG_TypeDef * RNGx)527 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(const RNG_TypeDef *RNGx)
528 {
529 return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL);
530 }
531
532 /**
533 * @brief Clear Clock Error interrupt Status (CEIS) Flag
534 * @rmtoll SR CEIS LL_RNG_ClearFlag_CEIS
535 * @param RNGx RNG Instance
536 * @retval None
537 */
LL_RNG_ClearFlag_CEIS(RNG_TypeDef * RNGx)538 __STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx)
539 {
540 WRITE_REG(RNGx->SR, ~RNG_SR_CEIS);
541 }
542
543 /**
544 * @brief Clear Seed Error interrupt Status (SEIS) Flag
545 * @rmtoll SR SEIS LL_RNG_ClearFlag_SEIS
546 * @param RNGx RNG Instance
547 * @retval None
548 */
LL_RNG_ClearFlag_SEIS(RNG_TypeDef * RNGx)549 __STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx)
550 {
551 WRITE_REG(RNGx->SR, ~RNG_SR_SEIS);
552 }
553
554 /**
555 * @}
556 */
557
558 /** @defgroup RNG_LL_EF_IT_Management IT Management
559 * @{
560 */
561
562 /**
563 * @brief Enable Random Number Generator Interrupt
564 * (applies for either Seed error, Clock Error or Data ready interrupts)
565 * @rmtoll CR IE LL_RNG_EnableIT
566 * @param RNGx RNG Instance
567 * @retval None
568 */
LL_RNG_EnableIT(RNG_TypeDef * RNGx)569 __STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx)
570 {
571 SET_BIT(RNGx->CR, RNG_CR_IE);
572 }
573
574 /**
575 * @brief Disable Random Number Generator Interrupt
576 * (applies for either Seed error, Clock Error or Data ready interrupts)
577 * @rmtoll CR IE LL_RNG_DisableIT
578 * @param RNGx RNG Instance
579 * @retval None
580 */
LL_RNG_DisableIT(RNG_TypeDef * RNGx)581 __STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
582 {
583 CLEAR_BIT(RNGx->CR, RNG_CR_IE);
584 }
585
586 /**
587 * @brief Check if Random Number Generator Interrupt is enabled
588 * (applies for either Seed error, Clock Error or Data ready interrupts)
589 * @rmtoll CR IE LL_RNG_IsEnabledIT
590 * @param RNGx RNG Instance
591 * @retval State of bit (1 or 0).
592 */
LL_RNG_IsEnabledIT(const RNG_TypeDef * RNGx)593 __STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(const RNG_TypeDef *RNGx)
594 {
595 return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL);
596 }
597
598 /**
599 * @}
600 */
601
602 /** @defgroup RNG_LL_EF_Data_Management Data Management
603 * @{
604 */
605
606 /**
607 * @brief Return32-bit Random Number value
608 * @rmtoll DR RNDATA LL_RNG_ReadRandData32
609 * @param RNGx RNG Instance
610 * @retval Generated 32-bit random value
611 */
LL_RNG_ReadRandData32(const RNG_TypeDef * RNGx)612 __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(const RNG_TypeDef *RNGx)
613 {
614 return (uint32_t)(READ_REG(RNGx->DR));
615 }
616
617 /**
618 * @}
619 */
620
621 /**
622 * @brief Enable Auto reset
623 * @rmtoll CR ARDIS LL_RNG_EnableArdis
624 * @param RNGx RNG Instance
625 * @retval None
626 */
LL_RNG_EnableArdis(RNG_TypeDef * RNGx)627 __STATIC_INLINE void LL_RNG_EnableArdis(RNG_TypeDef *RNGx)
628 {
629 CLEAR_BIT(RNGx->CR, RNG_CR_ARDIS);
630 }
631
632 /**
633 * @brief Disable Auto reset
634 * @rmtoll CR ARDIS LL_RNG_DisableArdis
635 * @param RNGx RNG Instance
636 * @retval None
637 */
LL_RNG_DisableArdis(RNG_TypeDef * RNGx)638 __STATIC_INLINE void LL_RNG_DisableArdis(RNG_TypeDef *RNGx)
639 {
640 SET_BIT(RNGx->CR, RNG_CR_ARDIS);
641 }
642
643 /**
644 * @brief Check if RNG Auto reset is enabled
645 * @rmtoll CR ARDIS LL_RNG_IsEnabledArdis
646 * @param RNGx RNG Instance
647 * @retval State of bit (1 or 0).
648 */
LL_RNG_IsEnabledArdis(const RNG_TypeDef * RNGx)649 __STATIC_INLINE uint32_t LL_RNG_IsEnabledArdis(const RNG_TypeDef *RNGx)
650 {
651 return ((READ_BIT(RNGx->CR, RNG_CR_ARDIS) != (RNG_CR_ARDIS)) ? 1UL : 0UL);
652 }
653
654 /** @defgroup RNG_LL_EF_Health_Test_Control Health Test Control
655 * @{
656 */
657
658 /**
659 * @brief Set RNG Health Test Control
660 * @rmtoll HTCR HTCFG LL_RNG_SetHealthConfig
661 * @param RNGx RNG Instance
662 * @param HTCFG can be values of 32 bits
663 * @retval None
664 */
LL_RNG_SetHealthConfig(RNG_TypeDef * RNGx,uint32_t HTCFG)665 __STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG)
666 {
667 WRITE_REG(RNGx->HTCR, HTCFG);
668 }
669
670 /**
671 * @brief Get RNG Health Test Control
672 * @rmtoll HTCR HTCFG LL_RNG_GetHealthConfig
673 * @param RNGx RNG Instance
674 * @retval Return 32-bit RNG Health Test configuration
675 */
LL_RNG_GetHealthConfig(const RNG_TypeDef * RNGx)676 __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(const RNG_TypeDef *RNGx)
677 {
678 return (uint32_t)READ_REG(RNGx->HTCR);
679 }
680
681 /**
682 * @}
683 */
684 #if defined(USE_FULL_LL_DRIVER)
685 /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
686 * @{
687 */
688 ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct);
689 void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct);
690 ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx);
691
692 /**
693 * @}
694 */
695 #endif /* USE_FULL_LL_DRIVER */
696
697 /**
698 * @}
699 */
700
701 /**
702 * @}
703 */
704
705 #endif /* RNG */
706
707 /**
708 * @}
709 */
710
711 #ifdef __cplusplus
712 }
713 #endif
714
715 #endif /* __STM32U5xx_LL_RNG_H */
716
