1 /**
2 ******************************************************************************
3 * @file stm32u5xx_ll_lptim.h
4 * @author MCD Application Team
5 * @brief Header file of LPTIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32U5xx_LL_LPTIM_H
21 #define STM32U5xx_LL_LPTIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32u5xx.h"
29
30 /** @addtogroup STM32U5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4)
35
36 /** @defgroup LPTIM_LL LPTIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup LPTIM_LL_Private_variables LPTIM Private variables
43 * @{
44 */
45
46 static const uint8_t LL_LPTIM_SHIFT_TAB_CCxP[] =
47 {
48 0U, /* CC1P */
49 16U /* CC2P */
50 };
51
52 static const uint8_t LL_LPTIM_SHIFT_TAB_ICxF[] =
53 {
54 0U, /* IC1F */
55 16U /* IC2F */
56 };
57
58 static const uint8_t LL_LPTIM_SHIFT_TAB_ICxPSC[] =
59 {
60 0U, /* IC1PSC */
61 16U /* IC2PSC */
62 };
63
64 static const uint8_t LL_LPTIM_SHIFT_TAB_CCxSEL[] =
65 {
66 0U, /* CC1SEL */
67 16U /* CC2SEL */
68 };
69
70 static const uint8_t LL_LPTIM_SHIFT_TAB_CCxE[] =
71 {
72 LPTIM_CCMR1_CC1E_Pos, /* CC1E */
73 LPTIM_CCMR1_CC2E_Pos /* CC2E */
74 };
75
76 static const uint8_t LL_LPTIM_OFFSET_TAB_ICx[8][4] =
77 {
78 {2, 7, 9, 13},
79 {3, 5, 6, 8},
80 {2, 3, 4, 5},
81 {2, 2, 3, 3},
82 {2, 2, 2, 2},
83 {2, 2, 2, 2},
84 {2, 2, 2, 2},
85 {2, 2, 2, 2}
86
87 };
88
89 /**
90 * @}
91 */
92
93 /* Private constants ---------------------------------------------------------*/
94 /** Legacy definitions for compatibility purpose
95 @cond 0
96 */
97 #define LL_LPTIM_SetCompareCH1 LL_LPTIM_OC_SetCompareCH1
98 #define LL_LPTIM_SetCompareCH2 LL_LPTIM_OC_SetCompareCH2
99 #define LL_LPTIM_GetCompareCH1 LL_LPTIM_OC_GetCompareCH1
100 #define LL_LPTIM_GetCompareCH2 LL_LPTIM_OC_GetCompareCH2
101 /**
102 @endcond
103 */
104
105 /* Private macros ------------------------------------------------------------*/
106 #if defined(USE_FULL_LL_DRIVER)
107 /** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
108 * @{
109 */
110 /**
111 * @}
112 */
113 #endif /*USE_FULL_LL_DRIVER*/
114
115 /* Exported types ------------------------------------------------------------*/
116 #if defined(USE_FULL_LL_DRIVER)
117 /** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
118 * @{
119 */
120
121 /**
122 * @brief LPTIM Init structure definition
123 */
124 typedef struct
125 {
126 uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
127 This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
128
129 This feature can be modified afterwards using unitary
130 function @ref LL_LPTIM_SetClockSource().*/
131
132 uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
133 This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
134
135 This feature can be modified afterwards using using unitary
136 function @ref LL_LPTIM_SetPrescaler().*/
137
138 uint32_t Waveform; /*!< Specifies the waveform shape.
139 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
140
141 This feature can be modified afterwards using unitary
142 function @ref LL_LPTIM_SetWaveform().*/
143 } LL_LPTIM_InitTypeDef;
144
145 /**
146 * @}
147 */
148 #endif /* USE_FULL_LL_DRIVER */
149
150 /* Exported constants --------------------------------------------------------*/
151 /** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
152 * @{
153 */
154
155 /** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
156 * @brief Flags defines which can be used with LL_LPTIM_ReadReg function
157 * @{
158 */
159 #define LL_LPTIM_ISR_CMP1OK LPTIM_ISR_CMP1OK /*!< Compare register 1 update OK */
160 #define LL_LPTIM_ISR_CMP2OK LPTIM_ISR_CMP2OK /*!< Compare register 2 update OK */
161 #define LL_LPTIM_ISR_CC1IF LPTIM_ISR_CC1IF /*!< Capture/Compare 1 interrupt flag */
162 #define LL_LPTIM_ISR_CC2IF LPTIM_ISR_CC2IF /*!< Capture/Compare 2 interrupt flag */
163 #define LL_LPTIM_ISR_CC1OF LPTIM_ISR_CC1OF /*!< Capture/Compare 1 over-capture flag */
164 #define LL_LPTIM_ISR_CC2OF LPTIM_ISR_CC2OF /*!< Capture/Compare 2 over-capture flag */
165 #define LL_LPTIM_ISR_DIEROK LPTIM_ISR_DIEROK /*!< Interrupt enable register update OK */
166 #define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */
167 #define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */
168 #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */
169 #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */
170 #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */
171 #define LL_LPTIM_ISR_UE LPTIM_ISR_UE /*!< Update event */
172 #define LL_LPTIM_ISR_REPOK LPTIM_ISR_REPOK /*!< Repetition register update OK */
173 /**
174 * @}
175 */
176
177 /** @defgroup LPTIM_LL_EC_IT IT Defines
178 * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
179 * @{
180 */
181 #define LL_LPTIM_DIER_CMP1OKIE LPTIM_DIER_CMP1OKIE /*!< Compare register 1 update OK */
182 #define LL_LPTIM_DIER_CMP2OKIE LPTIM_DIER_CMP2OKIE /*!< Compare register 2 update OK */
183 #define LL_LPTIM_DIER_CC1IFIE LPTIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt flag */
184 #define LL_LPTIM_DIER_CC2IFIE LPTIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt flag */
185 #define LL_LPTIM_DIER_CC1OFIE LPTIM_DIER_CC1OIE /*!< Capture/Compare 1 over-capture flag */
186 #define LL_LPTIM_DIER_CC2OFIE LPTIM_DIER_CC2OIE /*!< Capture/Compare 2 over-capture flag */
187 #define LL_LPTIM_DIER_ARRMIE LPTIM_DIER_ARRMIE /*!< Autoreload match */
188 #define LL_LPTIM_DIER_EXTTRIGIE LPTIM_DIER_EXTTRIGIE /*!< External trigger edge event */
189 #define LL_LPTIM_DIER_ARROKIE LPTIM_DIER_ARROKIE /*!< Autoreload register update OK */
190 #define LL_LPTIM_DIER_UPIE LPTIM_DIER_UPIE /*!< Counter direction change down to up */
191 #define LL_LPTIM_DIER_DOWNIE LPTIM_DIER_DOWNIE /*!< Counter direction change up to down */
192 #define LL_LPTIM_DIER_UEIE LPTIM_DIER_UEIE /*!< Update event */
193 #define LL_LPTIM_DIER_REPOKIE LPTIM_DIER_REPOKIE /*!< Repetition register update OK */
194 /**
195 * @}
196 */
197
198 /** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
199 * @{
200 */
201 #define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
202 #define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
203 /**
204 * @}
205 */
206
207 /** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
208 * @{
209 */
210 #define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /*!<Preload is disabled: registers are updated after each APB bus write access*/
211 #define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
212 /**
213 * @}
214 */
215
216 /** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
217 * @{
218 */
219 #define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!<The counter is incremented following each internal clock pulse*/
220 #define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
221 /**
222 * @}
223 */
224
225 /** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
226 * @{
227 */
228 #define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINUOUS or SINGLE*/
229 #define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
230 /**
231 * @}
232 */
233
234 /** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
235 * @{
236 */
237 #define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CCRx registers*/
238 #define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CCMR1_CC1P_0 /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CCx registers*/
239 /**
240 * @}
241 */
242
243 /** @defgroup TIM_LL_EC_CHANNEL Channel
244 * @{
245 */
246 #define LL_LPTIM_CHANNEL_CH1 0x00000000U /*!< LPTIM input/output channel 1 */
247 #define LL_LPTIM_CHANNEL_CH2 0x00000001U /*!< LPTIM input/output channel 2 */
248 /**
249 * @}
250 */
251
252 /** @defgroup LPTIM_LL_EC_LPTIM_IC_PRESCALER Input Capture Prescaler
253 * @{
254 */
255 #define LL_LPTIM_ICPSC_DIV1 0x00000000UL /*!< Capture performed each time an edge is detected on the capture input */
256 #define LL_LPTIM_ICPSC_DIV2 LPTIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */
257 #define LL_LPTIM_ICPSC_DIV4 LPTIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */
258 #define LL_LPTIM_ICPSC_DIV8 (LPTIM_CCMR1_IC1PSC_0|LPTIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 8 events */
259 /**
260 * @}
261 */
262
263 /** @defgroup LPTIM_LL_EC_LPTIM_IC_FILTER Input Capture Filter
264 * @{
265 */
266 #define LL_LPTIM_ICFLT_CLOCK_DIV1 0x00000000UL /*!< any external input capture signal level change is considered as a valid transition */
267 #define LL_LPTIM_ICFLT_CLOCK_DIV2 LPTIM_CCMR1_IC1F_0 /*!< external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition */
268 #define LL_LPTIM_ICFLT_CLOCK_DIV4 LPTIM_CCMR1_IC1F_1 /*!< external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition */
269 #define LL_LPTIM_ICFLT_CLOCK_DIV8 (LPTIM_CCMR1_IC1F_0|LPTIM_CCMR1_IC1F_1) /*!< external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition */
270 /**
271 * @}
272 */
273
274 /** @defgroup LPTIM_LL_EC_LPTIM_IC_POLARITY Input Capture Polarity
275 * @{
276 */
277 #define LL_LPTIM_ICPOLARITY_RISING 0x00000000UL /*!< Capture/Compare input rising polarity */
278 #define LL_LPTIM_ICPOLARITY_FALLING LPTIM_CCMR1_CC1P_0 /*!< Capture/Compare input falling polarity */
279 #define LL_LPTIM_ICPOLARITY_RISING_FALLING (LPTIM_CCMR1_CC1P_0|LPTIM_CCMR1_CC1P_1) /*!< Capture/Compare input rising and falling polarities */
280 /**
281 * @}
282 */
283 /** @defgroup LPTIM_LL_EC_LPTIM_IC_Selection Input Capture selection
284 * @{
285 */
286 #define LL_LPTIM_CCMODE_OUTPUT_PWM 0x00000000UL /*!< Select PWM mode */
287 #define LL_LPTIM_CCMODE_INPUTCAPTURE LPTIM_CCMR1_CC1SEL /*!< Select Input Capture mode*/
288 /**
289 * @}
290 */
291
292 /** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
293 * @{
294 */
295 #define LL_LPTIM_PRESCALER_DIV1 0x00000000U /*!<Prescaler division factor is set to 1*/
296 #define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 /*!<Prescaler division factor is set to 2*/
297 #define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 /*!<Prescaler division factor is set to 4*/
298 #define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
299 #define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 /*!<Prescaler division factor is set to 16*/
300 #define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
301 #define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
302 #define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC /*!<Prescaler division factor is set to 128*/
303 /**
304 * @}
305 */
306
307 /** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
308 * @{
309 */
310 #define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/
311 #define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/
312 #define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/
313 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
314 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to RTC Tamper 2*/
315 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 3*/
316 #define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP1 output*/
317 #define LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL /*!<External input trigger is connected to COMP2 output*/
318 #define LL_LPTIM_TRIG_SOURCE_LPDMA_CH0_TCF (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to LPDMA CH0 transfer complete */
319 #define LL_LPTIM_TRIG_SOURCE_LPDMA_CH1_TCF LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to LPDMA CH1 transfer complete */
320 #define LL_LPTIM_TRIG_SOURCE_LPDMA_CH2_TCF (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to LPDMA CH2 transfer complete */
321 #define LL_LPTIM_TRIG_SOURCE_GPDMA_CH0_TCF LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to GPDMA CH0 transfer complete */
322 #define LL_LPTIM_TRIG_SOURCE_GPDMA_CH4_TCF (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to GPDMA CH4 transfer complete */
323 /**
324 * @}
325 */
326
327 /** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
328 * @{
329 */
330 #define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U /*!<Any trigger active level change is considered as a valid trigger*/
331 #define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
332 #define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
333 #define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
334 /**
335 * @}
336 */
337
338 /** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
339 * @{
340 */
341 #define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
342 #define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
343 #define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /*!<LPTIM counter starts when a rising or a falling edge is detected*/
344 /**
345 * @}
346 */
347
348 /** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
349 * @{
350 */
351 #define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
352 #define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
353 /**
354 * @}
355 */
356
357 /** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
358 * @{
359 */
360 #define LL_LPTIM_CLK_FILTER_NONE 0x00000000U /*!<Any external clock signal level change is considered as a valid transition*/
361 #define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
362 #define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
363 #define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
364 /**
365 * @}
366 */
367
368 /** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
369 * @{
370 */
371 #define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
372 #define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
373 #define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
374 /**
375 * @}
376 */
377
378 /** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
379 * @{
380 */
381 #define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
382 #define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
383 #define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
384 /**
385 * @}
386 */
387
388 /** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
389 * @{
390 */
391 #define LL_LPTIM_INPUT1_SRC_GPIO 0x00000000UL /*!< For LPTIM1, LPTIM2, LPTIM3 and LPTIM4 */
392 #define LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_CFGR2_IN1SEL_0 /*!< For LPTIM1, LPTIM2, LPTIM3 and LPTIM4 */
393 #define LL_LPTIM_INPUT1_SRC_COMP2 LPTIM_CFGR2_IN1SEL_1 /*!< For LPTIM1 and LPTIM2 */
394 /**
395 * @}
396 */
397
398 /** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source
399 * @{
400 */
401 #define LL_LPTIM_INPUT2_SRC_GPIO 0x00000000UL /*!< For LPTIM1 and LPTIM2 */
402 #define LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_CFGR2_IN2SEL_0 /*!< For LPTIM1 and LPTIM2 */
403 /**
404 * @}
405 */
406
407 /** @defgroup LPTIM_EC_LPTIM1_IC1_RMP LPTIM1 Input Ch1 Remap
408 * @{
409 */
410 #define LL_LPTIM_LPTIM1_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */
411 #define LL_LPTIM_LPTIM1_IC1_RMP_COMP1 LPTIM_CFGR2_IC1SEL_0 /*!< IC1 connected to COMP1 */
412 #define LL_LPTIM_LPTIM1_IC1_RMP_COMP2 LPTIM_CFGR2_IC1SEL_1 /*!< IC1 connected to COMP2 */
413 /**
414 * @}
415 */
416
417 /** @defgroup LPTIM_EC_LPTIM1_IC2_RMP LPTIM1 Input Ch2 Remap
418 * @{
419 */
420 #define LL_LPTIM_LPTIM1_IC2_RMP_GPIO 0x00000000UL /*!< IC2 connected to GPIO */
421 #define LL_LPTIM_LPTIM1_IC2_RMP_LSI LPTIM_CFGR2_IC2SEL_0 /*!< IC2 connected to LSI */
422 #define LL_LPTIM_LPTIM1_IC2_RMP_LSE LPTIM_CFGR2_IC2SEL_1 /*!< IC2 connected to LSE */
423 /**
424 * @}
425 */
426
427 /** @defgroup LPTIM_EC_LPTIM2_IC1_RMP LPTIM2 Input Ch1 Remap
428 * @{
429 */
430 #define LL_LPTIM_LPTIM2_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */
431 #define LL_LPTIM_LPTIM2_IC1_RMP_COMP1 LPTIM_CFGR2_IC1SEL_0 /*!< IC1 connected to COMP1 */
432 #define LL_LPTIM_LPTIM2_IC1_RMP_COMP2 LPTIM_CFGR2_IC1SEL_1 /*!< IC1 connected to COMP2 */
433 /**
434 * @}
435 */
436
437 /** @defgroup LPTIM_EC_LPTIM2_IC2_RMP LPTIM2 Input Ch2 Remap
438 * @{
439 */
440 #define LL_LPTIM_LPTIM2_IC2_RMP_GPIO 0x00000000UL /*!< IC2 connected to GPIO */
441 #define LL_LPTIM_LPTIM2_IC2_RMP_HSI LPTIM_CFGR2_IC2SEL_0 /*!< IC2 connected to HSI */
442 #define LL_LPTIM_LPTIM2_IC2_RMP_MSIS_1024 LPTIM_CFGR2_IC2SEL_1 /*!< IC2 connected to MSIS/1024 */
443 #define LL_LPTIM_LPTIM2_IC2_RMP_MSIS_4 (LPTIM_CFGR2_IC2SEL_1|LPTIM_CFGR2_IC2SEL_0) /*!< IC2 connected to MSIS/4 */
444 /**
445 * @}
446 */
447
448 /** @defgroup LPTIM_EC_LPTIM3_IC1_RMP LPTIM3 Input Ch1 Remap
449 * @{
450 */
451 #define LL_LPTIM_LPTIM3_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */
452 #define LL_LPTIM_LPTIM3_IC1_RMP_COMP1 LPTIM_CFGR2_IC1SEL_0 /*!< IC1 connected to COMP1 */
453 #define LL_LPTIM_LPTIM3_IC1_RMP_COMP2 LPTIM_CFGR2_IC1SEL_1 /*!< IC1 connected to COMP2 */
454 /**
455 * @}
456 */
457
458
459 /**
460 * @}
461 */
462
463 /* Exported macro ------------------------------------------------------------*/
464 /** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
465 * @{
466 */
467
468 /** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
469 * @{
470 */
471
472 /**
473 * @brief Write a value in LPTIM register
474 * @param __INSTANCE__ LPTIM Instance
475 * @param __REG__ Register to be written
476 * @param __VALUE__ Value to be written in the register
477 * @retval None
478 */
479 #define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
480
481 /**
482 * @brief Read a value in LPTIM register
483 * @param __INSTANCE__ LPTIM Instance
484 * @param __REG__ Register to be read
485 * @retval Register value
486 */
487 #define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
488
489 /**
490 * @brief LPTimer Input Capture Get Offset(in counter step unit)
491 * @note The real capture value corresponding to the input capture trigger can be calculated using
492 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
493 * The Offset value is depending on the glitch filter value for the channel
494 * and the value of the prescaler for the kernel clock.
495 * Please check Errata Sheet V1_8 for more details under "variable latency
496 * on input capture channel" section.
497 * @param __PSC__ This parameter can be one of the following values:
498 * @arg @ref LL_LPTIM_PRESCALER_DIV1
499 * @arg @ref LL_LPTIM_PRESCALER_DIV2
500 * @arg @ref LL_LPTIM_PRESCALER_DIV4
501 * @arg @ref LL_LPTIM_PRESCALER_DIV8
502 * @arg @ref LL_LPTIM_PRESCALER_DIV16
503 * @arg @ref LL_LPTIM_PRESCALER_DIV32
504 * @arg @ref LL_LPTIM_PRESCALER_DIV64
505 * @arg @ref LL_LPTIM_PRESCALER_DIV128
506 * @param __FLT__ This parameter can be one of the following values:
507 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
508 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
509 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
510 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
511 * @retval offset value
512 */
513 #define LL_LPTIM_IC_GET_OFFSET(__PSC__, __FLT__) LL_LPTIM_OFFSET_TAB_ICx\
514 [((__PSC__) & LPTIM_CFGR_PRESC_Msk) >> LPTIM_CFGR_PRESC_Pos]\
515 [((__FLT__) & LPTIM_CCMR1_IC1F_Msk) >> LPTIM_CCMR1_IC1F_Pos]
516 /**
517 * @}
518 */
519
520 /**
521 * @}
522 */
523
524 /* Exported functions --------------------------------------------------------*/
525 /** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
526 * @{
527 */
528
529 /** Legacy definitions for compatibility purpose
530 @cond 0
531 */
532 #define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM
533 #define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1
534 #define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2
535 #define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O
536 #define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O
537 #define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM
538 /**
539 @endcond
540 */
541
542 #if defined(USE_FULL_LL_DRIVER)
543 /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
544 * @{
545 */
546
547 ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx);
548 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
549 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
550 /**
551 * @}
552 */
553 #endif /* USE_FULL_LL_DRIVER */
554
555 /** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
556 * @{
557 */
558
559 /**
560 * @brief Enable the LPTIM instance
561 * @note After setting the ENABLE bit, a delay of two counter clock is needed
562 * before the LPTIM instance is actually enabled.
563 * @rmtoll CR ENABLE LL_LPTIM_Enable
564 * @param LPTIMx Low-Power Timer instance
565 * @retval None
566 */
LL_LPTIM_Enable(LPTIM_TypeDef * LPTIMx)567 __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
568 {
569 SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
570 }
571
572 /**
573 * @brief Disable the LPTIM instance
574 * @rmtoll CR ENABLE LL_LPTIM_Disable
575 * @param LPTIMx Low-Power Timer instance
576 * @retval None
577 */
LL_LPTIM_Disable(LPTIM_TypeDef * LPTIMx)578 __STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
579 {
580 CLEAR_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
581 }
582
583 /**
584 * @brief Indicates whether the LPTIM instance is enabled.
585 * @rmtoll CR ENABLE LL_LPTIM_IsEnabled
586 * @param LPTIMx Low-Power Timer instance
587 * @retval State of bit (1 or 0).
588 */
LL_LPTIM_IsEnabled(const LPTIM_TypeDef * LPTIMx)589 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *LPTIMx)
590 {
591 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
592 }
593
594 /**
595 * @brief Starts the LPTIM counter in the desired mode.
596 * @note LPTIM instance must be enabled before starting the counter.
597 * @note It is possible to change on the fly from One Shot mode to
598 * Continuous mode.
599 * @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n
600 * CR SNGSTRT LL_LPTIM_StartCounter
601 * @param LPTIMx Low-Power Timer instance
602 * @param OperatingMode This parameter can be one of the following values:
603 * @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
604 * @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
605 * @retval None
606 */
LL_LPTIM_StartCounter(LPTIM_TypeDef * LPTIMx,uint32_t OperatingMode)607 __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
608 {
609 MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
610 }
611
612 /**
613 * @brief Enable reset after read.
614 * @note After calling this function any read access to LPTIM_CNT
615 * register will asynchronously reset the LPTIM_CNT register content.
616 * @rmtoll CR RSTARE LL_LPTIM_EnableResetAfterRead
617 * @param LPTIMx Low-Power Timer instance
618 * @retval None
619 */
LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef * LPTIMx)620 __STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx)
621 {
622 SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
623 }
624
625 /**
626 * @brief Disable reset after read.
627 * @rmtoll CR RSTARE LL_LPTIM_DisableResetAfterRead
628 * @param LPTIMx Low-Power Timer instance
629 * @retval None
630 */
LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef * LPTIMx)631 __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)
632 {
633 CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
634 }
635
636 /**
637 * @brief Indicate whether the reset after read feature is enabled.
638 * @rmtoll CR RSTARE LL_LPTIM_IsEnabledResetAfterRead
639 * @param LPTIMx Low-Power Timer instance
640 * @retval State of bit (1 or 0).
641 */
LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef * LPTIMx)642 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef *LPTIMx)
643 {
644 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL));
645 }
646
647 /**
648 * @brief Reset of the LPTIM_CNT counter register (synchronous).
649 * @note Due to the synchronous nature of this reset, it only takes
650 * place after a synchronization delay of 3 LPTIM core clock cycles
651 * (LPTIM core clock may be different from APB clock).
652 * @note COUNTRST is automatically cleared by hardware
653 * @rmtoll CR COUNTRST LL_LPTIM_ResetCounter\n
654 * @param LPTIMx Low-Power Timer instance
655 * @retval None
656 */
LL_LPTIM_ResetCounter(LPTIM_TypeDef * LPTIMx)657 __STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx)
658 {
659 SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST);
660 }
661
662 /**
663 * @brief Set the LPTIM registers update mode (enable/disable register preload)
664 * @note This function must be called when the LPTIM instance is disabled.
665 * @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode
666 * @param LPTIMx Low-Power Timer instance
667 * @param UpdateMode This parameter can be one of the following values:
668 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
669 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
670 * @retval None
671 */
LL_LPTIM_SetUpdateMode(LPTIM_TypeDef * LPTIMx,uint32_t UpdateMode)672 __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
673 {
674 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
675 }
676
677 /**
678 * @brief Get the LPTIM registers update mode
679 * @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode
680 * @param LPTIMx Low-Power Timer instance
681 * @retval Returned value can be one of the following values:
682 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
683 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
684 */
LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef * LPTIMx)685 __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *LPTIMx)
686 {
687 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
688 }
689
690 /**
691 * @brief Set the auto reload value
692 * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
693 * @note After a write to the LPTIMx_ARR register a new write operation to the
694 * same register can only be performed when the previous write operation
695 * is completed. Any successive write before the ARROK flag is set, will
696 * lead to unpredictable results.
697 * @note autoreload value be strictly greater than the compare value.
698 * @rmtoll ARR ARR LL_LPTIM_SetAutoReload
699 * @param LPTIMx Low-Power Timer instance
700 * @param AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
701 * @retval None
702 */
LL_LPTIM_SetAutoReload(LPTIM_TypeDef * LPTIMx,uint32_t AutoReload)703 __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
704 {
705 MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
706 }
707
708 /**
709 * @brief Get actual auto reload value
710 * @rmtoll ARR ARR LL_LPTIM_GetAutoReload
711 * @param LPTIMx Low-Power Timer instance
712 * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
713 */
LL_LPTIM_GetAutoReload(const LPTIM_TypeDef * LPTIMx)714 __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *LPTIMx)
715 {
716 return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
717 }
718
719 /**
720 * @brief Set the repetition value
721 * @note The LPTIMx_RCR register content must only be modified when the LPTIM is enabled
722 * @rmtoll RCR REP LL_LPTIM_SetRepetition
723 * @param LPTIMx Low-Power Timer instance
724 * @param Repetition Value between Min_Data=0x00 and Max_Data=0xFF
725 * @retval None
726 */
LL_LPTIM_SetRepetition(LPTIM_TypeDef * LPTIMx,uint32_t Repetition)727 __STATIC_INLINE void LL_LPTIM_SetRepetition(LPTIM_TypeDef *LPTIMx, uint32_t Repetition)
728 {
729 MODIFY_REG(LPTIMx->RCR, LPTIM_RCR_REP, Repetition);
730 }
731
732 /**
733 * @brief Get the repetition value
734 * @rmtoll RCR REP LL_LPTIM_GetRepetition
735 * @param LPTIMx Low-Power Timer instance
736 * @retval Repetition Value between Min_Data=0x00 and Max_Data=0xFF
737 */
LL_LPTIM_GetRepetition(const LPTIM_TypeDef * LPTIMx)738 __STATIC_INLINE uint32_t LL_LPTIM_GetRepetition(const LPTIM_TypeDef *LPTIMx)
739 {
740 return (uint32_t)(READ_BIT(LPTIMx->RCR, LPTIM_RCR_REP));
741 }
742
743 /**
744 * @brief Enable capture/compare channel.
745 * @rmtoll CCMR1 CC1E LL_LPTIM_CC_EnableChannel\n
746 * CCMR1 CC2E LL_LPTIM_CC_EnableChannel
747 * @param LPTIMx LPTimer instance
748 * @param Channel This parameter can be one of the following values:
749 * @arg @ref LL_LPTIM_CHANNEL_CH1
750 * @arg @ref LL_LPTIM_CHANNEL_CH2
751 * @retval None
752 */
LL_LPTIM_CC_EnableChannel(LPTIM_TypeDef * LPTIMx,uint32_t Channel)753 __STATIC_INLINE void LL_LPTIM_CC_EnableChannel(LPTIM_TypeDef *LPTIMx, uint32_t Channel)
754 {
755 SET_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]);
756 }
757
758 /**
759 * @brief Disable capture/compare channel.
760 * @rmtoll CCMR1 CC1E LL_LPTIM_CC_DisableChannel\n
761 * CCMR1 CC2E LL_LPTIM_CC_DisableChannel
762 * @param LPTIMx LPTimer instance
763 * @param Channel This parameter can be one of the following values:
764 * @arg @ref LL_LPTIM_CHANNEL_CH1
765 * @arg @ref LL_LPTIM_CHANNEL_CH2
766 * @retval None
767 */
LL_LPTIM_CC_DisableChannel(LPTIM_TypeDef * LPTIMx,uint32_t Channel)768 __STATIC_INLINE void LL_LPTIM_CC_DisableChannel(LPTIM_TypeDef *LPTIMx, uint32_t Channel)
769 {
770 CLEAR_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]);
771 }
772
773 /**
774 * @brief Indicate whether channel is enabled.
775 * @rmtoll CCMR1 CC1E LL_LPTIM_CC_IsEnabledChannel\n
776 * CCMR1 CC2E LL_LPTIM_CC_IsEnabledChannel
777 * @param LPTIMx LPTimer instance
778 * @param Channel This parameter can be one of the following values:
779 * @arg @ref LL_LPTIM_CHANNEL_CH1
780 * @arg @ref LL_LPTIM_CHANNEL_CH2
781 * @retval State of bit (1 or 0).
782 */
LL_LPTIM_CC_IsEnabledChannel(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)783 __STATIC_INLINE uint32_t LL_LPTIM_CC_IsEnabledChannel(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
784 {
785 return ((READ_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]) == \
786 (0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel])) ? 1UL : 0UL);
787
788 }
789
790 /**
791 * @brief Set the compare value
792 * @note After a write to the LPTIMx_CCR1 register a new write operation to the
793 * same register can only be performed when the previous write operation
794 * is completed. Any successive write before the CMP1OK flag is set, will
795 * lead to unpredictable results.
796 * @rmtoll CCR1 CCR1 LL_LPTIM_OC_SetCompareCH1
797 * @param LPTIMx Low-Power Timer instance
798 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
799 * @retval None
800 */
LL_LPTIM_OC_SetCompareCH1(LPTIM_TypeDef * LPTIMx,uint32_t CompareValue)801 __STATIC_INLINE void LL_LPTIM_OC_SetCompareCH1(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
802 {
803 MODIFY_REG(LPTIMx->CCR1, LPTIM_CCR1_CCR1, CompareValue);
804 }
805
806 /**
807 * @brief Get actual compare value
808 * @rmtoll CCR1 CCR1 LL_LPTIM_OC_GetCompareCH1
809 * @param LPTIMx Low-Power Timer instance
810 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
811 */
LL_LPTIM_OC_GetCompareCH1(const LPTIM_TypeDef * LPTIMx)812 __STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareCH1(const LPTIM_TypeDef *LPTIMx)
813 {
814 return (uint32_t)(READ_BIT(LPTIMx->CCR1, LPTIM_CCR1_CCR1));
815 }
816
817 /**
818 * @brief Set the compare value
819 * @note After a write to the LPTIMx_CCR2 register a new write operation to the
820 * same register can only be performed when the previous write operation
821 * is completed. Any successive write before the CMP2OK flag is set, will
822 * lead to unpredictable results.
823 * @rmtoll CCR2 CCR2 LL_LPTIM_OC_SetCompareCH2
824 * @param LPTIMx Low-Power Timer instance
825 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
826 * @retval None
827 */
LL_LPTIM_OC_SetCompareCH2(LPTIM_TypeDef * LPTIMx,uint32_t CompareValue)828 __STATIC_INLINE void LL_LPTIM_OC_SetCompareCH2(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
829 {
830 MODIFY_REG(LPTIMx->CCR2, LPTIM_CCR2_CCR2, CompareValue);
831 }
832
833 /**
834 * @brief Get actual compare value
835 * @rmtoll CCR2 CCR2 LL_LPTIM_OC_GetCompareCH2
836 * @param LPTIMx Low-Power Timer instance
837 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
838 */
LL_LPTIM_OC_GetCompareCH2(const LPTIM_TypeDef * LPTIMx)839 __STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareCH2(const LPTIM_TypeDef *LPTIMx)
840 {
841 return (uint32_t)(READ_BIT(LPTIMx->CCR2, LPTIM_CCR2_CCR2));
842 }
843
844 /**
845 * @brief Get actual counter value
846 * @note When the LPTIM instance is running with an asynchronous clock, reading
847 * the LPTIMx_CNT register may return unreliable values. So in this case
848 * it is necessary to perform two consecutive read accesses and verify
849 * that the two returned values are identical.
850 * @rmtoll CNT CNT LL_LPTIM_GetCounter
851 * @param LPTIMx Low-Power Timer instance
852 * @retval Counter value
853 */
LL_LPTIM_GetCounter(const LPTIM_TypeDef * LPTIMx)854 __STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *LPTIMx)
855 {
856 return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
857 }
858
859 /**
860 * @brief Set the counter mode (selection of the LPTIM counter clock source).
861 * @note The counter mode can be set only when the LPTIM instance is disabled.
862 * @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode
863 * @param LPTIMx Low-Power Timer instance
864 * @param CounterMode This parameter can be one of the following values:
865 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
866 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
867 * @retval None
868 */
LL_LPTIM_SetCounterMode(LPTIM_TypeDef * LPTIMx,uint32_t CounterMode)869 __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
870 {
871 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
872 }
873
874 /**
875 * @brief Get the counter mode
876 * @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode
877 * @param LPTIMx Low-Power Timer instance
878 * @retval Returned value can be one of the following values:
879 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
880 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
881 */
LL_LPTIM_GetCounterMode(const LPTIM_TypeDef * LPTIMx)882 __STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *LPTIMx)
883 {
884 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
885 }
886
887 /**
888 * @brief Set waveform shape
889 * @rmtoll CFGR WAVE LL_LPTIM_SetWaveform
890 * @param LPTIMx Low-Power Timer instance
891 * @param Waveform This parameter can be one of the following values:
892 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
893 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
894 * @retval None
895 */
LL_LPTIM_SetWaveform(LPTIM_TypeDef * LPTIMx,uint32_t Waveform)896 __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
897 {
898 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
899 }
900
901 /**
902 * @brief Get actual waveform shape
903 * @rmtoll CFGR WAVE LL_LPTIM_GetWaveform
904 * @param LPTIMx Low-Power Timer instance
905 * @retval Returned value can be one of the following values:
906 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
907 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
908 */
LL_LPTIM_GetWaveform(const LPTIM_TypeDef * LPTIMx)909 __STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *LPTIMx)
910 {
911 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
912 }
913
914 /**
915 * @brief Set the polarity of an output channel.
916 * @rmtoll CCMR1 CC1P LL_LPTIM_OC_SetPolarity\n
917 * @rmtoll CCMR1 CC2P LL_LPTIM_OC_SetPolarity\n
918 * @param LPTIMx Low-Power Timer instance
919 * @param Channel This parameter can be one of the following values:
920 * @arg @ref LL_LPTIM_CHANNEL_CH1
921 * @arg @ref LL_LPTIM_CHANNEL_CH2
922 * @param Polarity This parameter can be one of the following values:
923 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
924 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
925 * @retval None
926 */
LL_LPTIM_OC_SetPolarity(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Polarity)927 __STATIC_INLINE void LL_LPTIM_OC_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Polarity)
928 {
929 if (LPTIMx == LPTIM4)
930 {
931 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, ((Polarity >> LPTIM_CCMR1_CC1P_Pos) << LPTIM_CFGR_WAVPOL_Pos));
932 }
933 else
934 {
935 MODIFY_REG(LPTIMx->CCMR1, (LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel]),
936 (Polarity << LL_LPTIM_SHIFT_TAB_CCxP[Channel]));
937 }
938 }
939
940 /**
941 * @brief Get the polarity of an output channel.
942 * @rmtoll CCMR1 CC1P LL_LPTIM_OC_GetPolarity\n
943 * @rmtoll CCMR1 CC2P LL_LPTIM_OC_GetPolarity\n
944 * @param LPTIMx Low-Power Timer instance
945 * @param Channel This parameter can be one of the following values:
946 * @arg @ref LL_LPTIM_CHANNEL_CH1
947 * @arg @ref LL_LPTIM_CHANNEL_CH2
948 * @retval Returned value can be one of the following values:
949 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
950 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
951 */
LL_LPTIM_OC_GetPolarity(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)952 __STATIC_INLINE uint32_t LL_LPTIM_OC_GetPolarity(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
953 {
954 if (LPTIMx == LPTIM4)
955 {
956 return (uint32_t)((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL) >> LPTIM_CFGR_WAVPOL_Pos) << LPTIM_CCMR1_CC1P_Pos);
957 }
958 else
959 {
960 return (uint32_t)(READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel]) >> \
961 LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
962 }
963 }
964
965 /**
966 * @brief Set actual prescaler division ratio.
967 * @note This function must be called when the LPTIM instance is disabled.
968 * @note When the LPTIM is configured to be clocked by an internal clock source
969 * and the LPTIM counter is configured to be updated by active edges
970 * detected on the LPTIM external Input1, the internal clock provided to
971 * the LPTIM must be not be prescaled.
972 * @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler
973 * @param LPTIMx Low-Power Timer instance
974 * @param Prescaler This parameter can be one of the following values:
975 * @arg @ref LL_LPTIM_PRESCALER_DIV1
976 * @arg @ref LL_LPTIM_PRESCALER_DIV2
977 * @arg @ref LL_LPTIM_PRESCALER_DIV4
978 * @arg @ref LL_LPTIM_PRESCALER_DIV8
979 * @arg @ref LL_LPTIM_PRESCALER_DIV16
980 * @arg @ref LL_LPTIM_PRESCALER_DIV32
981 * @arg @ref LL_LPTIM_PRESCALER_DIV64
982 * @arg @ref LL_LPTIM_PRESCALER_DIV128
983 * @retval None
984 */
LL_LPTIM_SetPrescaler(LPTIM_TypeDef * LPTIMx,uint32_t Prescaler)985 __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
986 {
987 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
988 }
989
990 /**
991 * @brief Get actual prescaler division ratio.
992 * @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler
993 * @param LPTIMx Low-Power Timer instance
994 * @retval Returned value can be one of the following values:
995 * @arg @ref LL_LPTIM_PRESCALER_DIV1
996 * @arg @ref LL_LPTIM_PRESCALER_DIV2
997 * @arg @ref LL_LPTIM_PRESCALER_DIV4
998 * @arg @ref LL_LPTIM_PRESCALER_DIV8
999 * @arg @ref LL_LPTIM_PRESCALER_DIV16
1000 * @arg @ref LL_LPTIM_PRESCALER_DIV32
1001 * @arg @ref LL_LPTIM_PRESCALER_DIV64
1002 * @arg @ref LL_LPTIM_PRESCALER_DIV128
1003 */
LL_LPTIM_GetPrescaler(const LPTIM_TypeDef * LPTIMx)1004 __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *LPTIMx)
1005 {
1006 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
1007 }
1008
1009 /**
1010 * @brief Set LPTIM input 1 source (default GPIO).
1011 * @rmtoll CFGR2 IN1SEL LL_LPTIM_SetInput1Src
1012 * @param LPTIMx Low-Power Timer instance
1013 * @param Src This parameter can be one of the following values:
1014 * @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
1015 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1
1016 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP2 (*)
1017 * (*) Value not defined for all devices
1018 * @retval None
1019 */
LL_LPTIM_SetInput1Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)1020 __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
1021 {
1022 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN1SEL, Src);
1023 }
1024
1025 /**
1026 * @brief Set LPTIM input 2 source (default GPIO).
1027 * @rmtoll CFGR2 IN2SEL LL_LPTIM_SetInput2Src
1028 * @param LPTIMx Low-Power Timer instance
1029 * @param Src This parameter can be one of the following values:
1030 * @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
1031 * @arg @ref LL_LPTIM_INPUT2_SRC_COMP2
1032 * @retval None
1033 */
LL_LPTIM_SetInput2Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)1034 __STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
1035 {
1036 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN2SEL, Src);
1037 }
1038
1039 /**
1040 * @brief Set LPTIM input source (default GPIO).
1041 * @rmtoll CFGR2 IC1SEL LL_LPTIM_SetRemap
1042 * @rmtoll CFGR2 IC2SEL LL_LPTIM_SetRemap
1043 * @param LPTIMx Low-Power Timer instance
1044 * @param Src This parameter can be one of the following values:
1045 * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_GPIO
1046 * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_COMP1
1047 * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_COMP2
1048 * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_GPIO
1049 * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_LSI
1050 * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_LSE
1051 * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_GPIO
1052 * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_COMP1
1053 * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_COMP2
1054 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_GPIO
1055 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_HSI
1056 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_MSIS_1024
1057 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_MSIS_4
1058 * @arg @ref LL_LPTIM_LPTIM3_IC1_RMP_GPIO
1059 * @arg @ref LL_LPTIM_LPTIM3_IC1_RMP_COMP1
1060 * @arg @ref LL_LPTIM_LPTIM3_IC1_RMP_COMP2
1061 * @retval None
1062 */
LL_LPTIM_SetRemap(LPTIM_TypeDef * LPTIMx,uint32_t Src)1063 __STATIC_INLINE void LL_LPTIM_SetRemap(LPTIM_TypeDef *LPTIMx, uint32_t Src)
1064 {
1065 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IC1SEL | LPTIM_CFGR2_IC2SEL, Src);
1066 }
1067
1068 /**
1069 * @brief Set the polarity of IC channel 1.
1070 * @rmtoll CCMR1 CC1P LL_LPTIM_IC_SetPolarity\n
1071 * @rmtoll CCMR1 CC2P LL_LPTIM_IC_SetPolarity\n
1072 * @param LPTIMx Low-Power Timer instance
1073 * @param Channel This parameter can be one of the following values:
1074 * @arg @ref LL_LPTIM_CHANNEL_CH1
1075 * @arg @ref LL_LPTIM_CHANNEL_CH2
1076 * @param Polarity This parameter can be one of the following values:
1077 * @arg @ref LL_LPTIM_ICPOLARITY_RISING
1078 * @arg @ref LL_LPTIM_ICPOLARITY_FALLING
1079 * @arg @ref LL_LPTIM_ICPOLARITY_RISING_FALLING
1080 * @retval None
1081 */
LL_LPTIM_IC_SetPolarity(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Polarity)1082 __STATIC_INLINE void LL_LPTIM_IC_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Polarity)
1083 {
1084 MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel],
1085 Polarity << LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
1086 }
1087
1088 /**
1089 * @brief Get the polarity of IC channels.
1090 * @rmtoll CCMR1 CC1P LL_LPTIM_IC_GetPolarity\n
1091 * @rmtoll CCMR1 CC2P LL_LPTIM_IC_GetPolarity\n
1092 * @param LPTIMx Low-Power Timer instance
1093 * @param Channel This parameter can be one of the following values:
1094 * @arg @ref LL_LPTIM_CHANNEL_CH1
1095 * @arg @ref LL_LPTIM_CHANNEL_CH2
1096 * @retval Returned value can be one of the following values:
1097 * @arg @ref LL_LPTIM_ICPOLARITY_RISING
1098 * @arg @ref LL_LPTIM_ICPOLARITY_FALLING
1099 * @arg @ref LL_LPTIM_ICPOLARITY_RISING_FALLING
1100 */
LL_LPTIM_IC_GetPolarity(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1101 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetPolarity(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1102 {
1103 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel])) >> \
1104 LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
1105
1106 }
1107
1108 /**
1109 * @brief Set the filter of IC channels.
1110 * @rmtoll CCMR1 IC1F LL_LPTIM_IC_SetFilter\n
1111 * @rmtoll CCMR1 IC2F LL_LPTIM_IC_SetFilter\n
1112 * @param LPTIMx Low-Power Timer instance
1113 * @param Channel This parameter can be one of the following values:
1114 * @arg @ref LL_LPTIM_CHANNEL_CH1
1115 * @arg @ref LL_LPTIM_CHANNEL_CH2
1116 * @param Filter This parameter can be one of the following values:
1117 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
1118 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
1119 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
1120 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
1121 * @retval None
1122 */
LL_LPTIM_IC_SetFilter(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Filter)1123 __STATIC_INLINE void LL_LPTIM_IC_SetFilter(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Filter)
1124 {
1125 MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_IC1F << LL_LPTIM_SHIFT_TAB_ICxF[Channel],
1126 Filter << LL_LPTIM_SHIFT_TAB_ICxF[Channel]);
1127 }
1128
1129 /**
1130 * @brief Get the filter of IC channels.
1131 * @rmtoll CCMR1 IC1F LL_LPTIM_IC_GetFilter\n
1132 * @rmtoll CCMR1 IC2F LL_LPTIM_IC_GetFilter\n
1133 * @param LPTIMx Low-Power Timer instance
1134 * @param Channel This parameter can be one of the following values:
1135 * @arg @ref LL_LPTIM_CHANNEL_CH1
1136 * @arg @ref LL_LPTIM_CHANNEL_CH2
1137 * @retval Returned value can be one of the following values:
1138 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
1139 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
1140 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
1141 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
1142 */
LL_LPTIM_IC_GetFilter(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1143 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetFilter(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1144 {
1145 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_IC1F << LL_LPTIM_SHIFT_TAB_ICxF[Channel])) >> \
1146 LL_LPTIM_SHIFT_TAB_ICxF[Channel]);
1147 }
1148
1149 /**
1150 * @brief Set the prescaler of IC channels.
1151 * @rmtoll CCMR1 IC1PSC LL_LPTIM_IC_SetPrescaler\n
1152 * @rmtoll CCMR1 IC2PSC LL_LPTIM_IC_SetPrescaler\n
1153 * @param LPTIMx Low-Power Timer instance
1154 * @param Channel This parameter can be one of the following values:
1155 * @arg @ref LL_LPTIM_CHANNEL_CH1
1156 * @arg @ref LL_LPTIM_CHANNEL_CH2
1157 * @param Prescaler This parameter can be one of the following values:
1158 * @arg @ref LL_LPTIM_ICPSC_DIV1
1159 * @arg @ref LL_LPTIM_ICPSC_DIV2
1160 * @arg @ref LL_LPTIM_ICPSC_DIV4
1161 * @arg @ref LL_LPTIM_ICPSC_DIV8
1162 * @retval None
1163 */
LL_LPTIM_IC_SetPrescaler(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Prescaler)1164 __STATIC_INLINE void LL_LPTIM_IC_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Prescaler)
1165 {
1166 MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_IC1PSC << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel],
1167 Prescaler << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel]);
1168 }
1169
1170 /**
1171 * @brief Get the prescaler of IC channels.
1172 * @rmtoll CCMR1 IC1PSC LL_LPTIM_IC_GetPrescaler\n
1173 * @rmtoll CCMR1 IC2PSC LL_LPTIM_IC_GetPrescaler\n
1174 * @param LPTIMx Low-Power Timer instance
1175 * @param Channel This parameter can be one of the following values:
1176 * @arg @ref LL_LPTIM_CHANNEL_CH1
1177 * @arg @ref LL_LPTIM_CHANNEL_CH2
1178 * @retval Returned value can be one of the following values:
1179 * @arg @ref LL_LPTIM_ICPSC_DIV1
1180 * @arg @ref LL_LPTIM_ICPSC_DIV2
1181 * @arg @ref LL_LPTIM_ICPSC_DIV4
1182 * @arg @ref LL_LPTIM_ICPSC_DIV8
1183 */
LL_LPTIM_IC_GetPrescaler(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1184 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetPrescaler(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1185 {
1186 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_IC1PSC << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel])) >> \
1187 LL_LPTIM_SHIFT_TAB_ICxPSC[Channel]);
1188 }
1189
1190 /**
1191 * @brief Set the Channel Mode.
1192 * @rmtoll CCMR1 CC1SEL LL_LPTIM_CC_SetChannelMode\n
1193 * CCMR1 CC2SEL LL_LPTIM_CC_SetChannelMode
1194 * @param LPTIMx Low-Power Timer instance
1195 * @param Channel This parameter can be one of the following values:
1196 * @arg @ref LL_LPTIM_CHANNEL_CH1
1197 * @arg @ref LL_LPTIM_CHANNEL_CH2
1198 * @param CCMode This parameter can be one of the following values:
1199 * @arg @ref LL_LPTIM_CCMODE_OUTPUT_PWM
1200 * @arg @ref LL_LPTIM_CCMODE_INPUTCAPTURE
1201 * @retval None
1202 */
LL_LPTIM_CC_SetChannelMode(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t CCMode)1203 __STATIC_INLINE void LL_LPTIM_CC_SetChannelMode(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t CCMode)
1204 {
1205 SET_BIT(LPTIMx->CCMR1, CCMode << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]);
1206 }
1207
1208 /**
1209 * @brief Get the Channel Mode.
1210 * @rmtoll CCMR1 CC1SEL LL_LPTIM_CC_GetChannelMode\n
1211 * CCMR1 CC2SEL LL_LPTIM_CC_GetChannelMode
1212 * @param LPTIMx Low-Power Timer instance
1213 * @param Channel This parameter can be one of the following values:
1214 * @arg @ref LL_LPTIM_CHANNEL_CH1
1215 * @arg @ref LL_LPTIM_CHANNEL_CH2
1216 * @retval Returned value can be one of the following values:
1217 * @arg @ref LL_LPTIM_CCMODE_OUTPUT_PWM
1218 * @arg @ref LL_LPTIM_CCMODE_INPUTCAPTURE
1219 */
LL_LPTIM_CC_GetChannelMode(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1220 __STATIC_INLINE uint32_t LL_LPTIM_CC_GetChannelMode(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1221 {
1222 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1SEL << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel])) >> \
1223 LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]);
1224 }
1225
1226 /**
1227 * @brief Get captured value for input channel 1.
1228 * @rmtoll CCR1 CCR1 LL_LPTIM_IC_GetCaptureCH1
1229 * @note The real capture value corresponding to the input capture trigger can be calculated using
1230 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
1231 * where offset can be retrieved by calling @ref LL_LPTIM_IC_GET_OFFSET
1232 * @param LPTIMx Low-Power Timer instance
1233 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
1234 */
LL_LPTIM_IC_GetCaptureCH1(const LPTIM_TypeDef * LPTIMx)1235 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH1(const LPTIM_TypeDef *LPTIMx)
1236 {
1237 return (uint32_t)(READ_BIT(LPTIMx->CCR1, LPTIM_CCR1_CCR1));
1238 }
1239
1240 /**
1241 * @brief Get captured value for input channel 2.
1242 * @rmtoll CCR2 CCR2 LL_LPTIM_IC_GetCaptureCH2
1243 * @note The real capture value corresponding to the input capture trigger can be calculated using
1244 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
1245 * where offset can be retrieved by calling @ref LL_LPTIM_IC_GET_OFFSET
1246 * @param LPTIMx Low-Power Timer instance
1247 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
1248 */
LL_LPTIM_IC_GetCaptureCH2(const LPTIM_TypeDef * LPTIMx)1249 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH2(const LPTIM_TypeDef *LPTIMx)
1250 {
1251 return (uint32_t)(READ_BIT(LPTIMx->CCR2, LPTIM_CCR2_CCR2));
1252 }
1253
1254 /**
1255 * @}
1256 */
1257
1258 /** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
1259 * @{
1260 */
1261
1262 /**
1263 * @brief Enable the timeout function
1264 * @note This function must be called when the LPTIM instance is disabled.
1265 * @note The first trigger event will start the timer, any successive trigger
1266 * event will reset the counter and the timer will restart.
1267 * @note The timeout value corresponds to the compare value; if no trigger
1268 * occurs within the expected time frame, the MCU is waked-up by the
1269 * compare match event.
1270 * @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout
1271 * @param LPTIMx Low-Power Timer instance
1272 * @retval None
1273 */
LL_LPTIM_EnableTimeout(LPTIM_TypeDef * LPTIMx)1274 __STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
1275 {
1276 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
1277 }
1278
1279 /**
1280 * @brief Disable the timeout function
1281 * @note This function must be called when the LPTIM instance is disabled.
1282 * @note A trigger event arriving when the timer is already started will be
1283 * ignored.
1284 * @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout
1285 * @param LPTIMx Low-Power Timer instance
1286 * @retval None
1287 */
LL_LPTIM_DisableTimeout(LPTIM_TypeDef * LPTIMx)1288 __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
1289 {
1290 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
1291 }
1292
1293 /**
1294 * @brief Indicate whether the timeout function is enabled.
1295 * @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
1296 * @param LPTIMx Low-Power Timer instance
1297 * @retval State of bit (1 or 0).
1298 */
LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef * LPTIMx)1299 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *LPTIMx)
1300 {
1301 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
1302 }
1303
1304 /**
1305 * @brief Start the LPTIM counter
1306 * @note This function must be called when the LPTIM instance is disabled.
1307 * @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw
1308 * @param LPTIMx Low-Power Timer instance
1309 * @retval None
1310 */
LL_LPTIM_TrigSw(LPTIM_TypeDef * LPTIMx)1311 __STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
1312 {
1313 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
1314 }
1315
1316 /**
1317 * @brief Configure the external trigger used as a trigger event for the LPTIM.
1318 * @note This function must be called when the LPTIM instance is disabled.
1319 * @note An internal clock source must be present when a digital filter is
1320 * required for the trigger.
1321 * @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n
1322 * CFGR TRGFLT LL_LPTIM_ConfigTrigger\n
1323 * CFGR TRIGEN LL_LPTIM_ConfigTrigger
1324 * @param LPTIMx Low-Power Timer instance
1325 * @param Source This parameter can be one of the following values:
1326 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
1327 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
1328 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
1329 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
1330 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
1331 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
1332 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
1333 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
1334 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPDMA_CH0_TCF
1335 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPDMA_CH1_TCF
1336 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPDMA_CH2_TCF
1337 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPDMA_CH0_TCF
1338 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPDMA_CH4_TCF
1339 * @param Filter This parameter can be one of the following values:
1340 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
1341 * @arg @ref LL_LPTIM_TRIG_FILTER_2
1342 * @arg @ref LL_LPTIM_TRIG_FILTER_4
1343 * @arg @ref LL_LPTIM_TRIG_FILTER_8
1344 * @param Polarity This parameter can be one of the following values:
1345 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
1346 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
1347 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
1348 * @retval None
1349 */
LL_LPTIM_ConfigTrigger(LPTIM_TypeDef * LPTIMx,uint32_t Source,uint32_t Filter,uint32_t Polarity)1350 __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
1351 {
1352 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
1353 }
1354
1355 /**
1356 * @brief Get actual external trigger source.
1357 * @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource
1358 * @param LPTIMx Low-Power Timer instance
1359 * @retval Returned value can be one of the following values:
1360 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
1361 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
1362 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
1363 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
1364 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
1365 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
1366 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
1367 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
1368 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPDMA_CH0_TCF
1369 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPDMA_CH1_TCF
1370 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPDMA_CH2_TCF
1371 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPDMA_CH0_TCF
1372 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPDMA_CH4_TCF
1373 */
LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef * LPTIMx)1374 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *LPTIMx)
1375 {
1376 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
1377 }
1378
1379 /**
1380 * @brief Get actual external trigger filter.
1381 * @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter
1382 * @param LPTIMx Low-Power Timer instance
1383 * @retval Returned value can be one of the following values:
1384 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
1385 * @arg @ref LL_LPTIM_TRIG_FILTER_2
1386 * @arg @ref LL_LPTIM_TRIG_FILTER_4
1387 * @arg @ref LL_LPTIM_TRIG_FILTER_8
1388 */
LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef * LPTIMx)1389 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *LPTIMx)
1390 {
1391 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
1392 }
1393
1394 /**
1395 * @brief Get actual external trigger polarity.
1396 * @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
1397 * @param LPTIMx Low-Power Timer instance
1398 * @retval Returned value can be one of the following values:
1399 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
1400 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
1401 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
1402 */
LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef * LPTIMx)1403 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *LPTIMx)
1404 {
1405 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
1406 }
1407
1408 /**
1409 * @}
1410 */
1411
1412 /** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
1413 * @{
1414 */
1415
1416 /**
1417 * @brief Set the source of the clock used by the LPTIM instance.
1418 * @note This function must be called when the LPTIM instance is disabled.
1419 * @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource
1420 * @param LPTIMx Low-Power Timer instance
1421 * @param ClockSource This parameter can be one of the following values:
1422 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
1423 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
1424 * @retval None
1425 */
LL_LPTIM_SetClockSource(LPTIM_TypeDef * LPTIMx,uint32_t ClockSource)1426 __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
1427 {
1428 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
1429 }
1430
1431 /**
1432 * @brief Get actual LPTIM instance clock source.
1433 * @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource
1434 * @param LPTIMx Low-Power Timer instance
1435 * @retval Returned value can be one of the following values:
1436 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
1437 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
1438 */
LL_LPTIM_GetClockSource(const LPTIM_TypeDef * LPTIMx)1439 __STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *LPTIMx)
1440 {
1441 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
1442 }
1443
1444 /**
1445 * @brief Configure the active edge or edges used by the counter when
1446 the LPTIM is clocked by an external clock source.
1447 * @note This function must be called when the LPTIM instance is disabled.
1448 * @note When both external clock signal edges are considered active ones,
1449 * the LPTIM must also be clocked by an internal clock source with a
1450 * frequency equal to at least four times the external clock frequency.
1451 * @note An internal clock source must be present when a digital filter is
1452 * required for external clock.
1453 * @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n
1454 * CFGR CKPOL LL_LPTIM_ConfigClock
1455 * @param LPTIMx Low-Power Timer instance
1456 * @param ClockFilter This parameter can be one of the following values:
1457 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
1458 * @arg @ref LL_LPTIM_CLK_FILTER_2
1459 * @arg @ref LL_LPTIM_CLK_FILTER_4
1460 * @arg @ref LL_LPTIM_CLK_FILTER_8
1461 * @param ClockPolarity This parameter can be one of the following values:
1462 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
1463 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
1464 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
1465 * @retval None
1466 */
LL_LPTIM_ConfigClock(LPTIM_TypeDef * LPTIMx,uint32_t ClockFilter,uint32_t ClockPolarity)1467 __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
1468 {
1469 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
1470 }
1471
1472 /**
1473 * @brief Get actual clock polarity
1474 * @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity
1475 * @param LPTIMx Low-Power Timer instance
1476 * @retval Returned value can be one of the following values:
1477 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
1478 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
1479 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
1480 */
LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef * LPTIMx)1481 __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *LPTIMx)
1482 {
1483 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
1484 }
1485
1486 /**
1487 * @brief Get actual clock digital filter
1488 * @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter
1489 * @param LPTIMx Low-Power Timer instance
1490 * @retval Returned value can be one of the following values:
1491 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
1492 * @arg @ref LL_LPTIM_CLK_FILTER_2
1493 * @arg @ref LL_LPTIM_CLK_FILTER_4
1494 * @arg @ref LL_LPTIM_CLK_FILTER_8
1495 */
LL_LPTIM_GetClockFilter(const LPTIM_TypeDef * LPTIMx)1496 __STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *LPTIMx)
1497 {
1498 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
1499 }
1500
1501 /**
1502 * @}
1503 */
1504
1505 /** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
1506 * @{
1507 */
1508
1509 /**
1510 * @brief Configure the encoder mode.
1511 * @note This function must be called when the LPTIM instance is disabled.
1512 * @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode
1513 * @param LPTIMx Low-Power Timer instance
1514 * @param EncoderMode This parameter can be one of the following values:
1515 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1516 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1517 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1518 * @retval None
1519 */
LL_LPTIM_SetEncoderMode(LPTIM_TypeDef * LPTIMx,uint32_t EncoderMode)1520 __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
1521 {
1522 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
1523 }
1524
1525 /**
1526 * @brief Get actual encoder mode.
1527 * @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode
1528 * @param LPTIMx Low-Power Timer instance
1529 * @retval Returned value can be one of the following values:
1530 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1531 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1532 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1533 */
LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef * LPTIMx)1534 __STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *LPTIMx)
1535 {
1536 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
1537 }
1538
1539 /**
1540 * @brief Enable the encoder mode
1541 * @note This function must be called when the LPTIM instance is disabled.
1542 * @note In this mode the LPTIM instance must be clocked by an internal clock
1543 * source. Also, the prescaler division ratio must be equal to 1.
1544 * @note LPTIM instance must be configured in continuous mode prior enabling
1545 * the encoder mode.
1546 * @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode
1547 * @param LPTIMx Low-Power Timer instance
1548 * @retval None
1549 */
LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef * LPTIMx)1550 __STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
1551 {
1552 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1553 }
1554
1555 /**
1556 * @brief Disable the encoder mode
1557 * @note This function must be called when the LPTIM instance is disabled.
1558 * @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode
1559 * @param LPTIMx Low-Power Timer instance
1560 * @retval None
1561 */
LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef * LPTIMx)1562 __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
1563 {
1564 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1565 }
1566
1567 /**
1568 * @brief Indicates whether the LPTIM operates in encoder mode.
1569 * @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode
1570 * @param LPTIMx Low-Power Timer instance
1571 * @retval State of bit (1 or 0).
1572 */
LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef * LPTIMx)1573 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *LPTIMx)
1574 {
1575 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
1576 }
1577
1578 /**
1579 * @}
1580 */
1581
1582 /** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
1583 * @{
1584 */
1585
1586 /**
1587 * @brief Clear the compare match flag for channel 1 (CC1CF)
1588 * @rmtoll ICR CC1CF LL_LPTIM_ClearFlag_CC1
1589 * @param LPTIMx Low-Power Timer instance
1590 * @retval None
1591 */
LL_LPTIM_ClearFlag_CC1(LPTIM_TypeDef * LPTIMx)1592 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC1(LPTIM_TypeDef *LPTIMx)
1593 {
1594 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC1CF);
1595 }
1596
1597 /**
1598 * @brief Inform application whether a capture/compare interrupt has occurred for channel 1.
1599 * @rmtoll ISR CC1IF LL_LPTIM_IsActiveFlag_CC1
1600 * @param LPTIMx Low-Power Timer instance
1601 * @retval State of bit (1 or 0).
1602 */
LL_LPTIM_IsActiveFlag_CC1(const LPTIM_TypeDef * LPTIMx)1603 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1(const LPTIM_TypeDef *LPTIMx)
1604 {
1605 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC1IF) == LPTIM_ISR_CC1IF) ? 1UL : 0UL));
1606 }
1607
1608 /**
1609 * @brief Clear the compare match flag for channel 2 (CC2CF)
1610 * @rmtoll ICR CC2CF LL_LPTIM_ClearFlag_CC2
1611 * @param LPTIMx Low-Power Timer instance
1612 * @retval None
1613 */
LL_LPTIM_ClearFlag_CC2(LPTIM_TypeDef * LPTIMx)1614 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC2(LPTIM_TypeDef *LPTIMx)
1615 {
1616 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC2CF);
1617 }
1618
1619 /**
1620 * @brief Inform application whether a capture/compare interrupt has occurred for channel 2.
1621 * @rmtoll ISR CC2IF LL_LPTIM_IsActiveFlag_CC2
1622 * @param LPTIMx Low-Power Timer instance
1623 * @retval State of bit (1 or 0).
1624 */
LL_LPTIM_IsActiveFlag_CC2(const LPTIM_TypeDef * LPTIMx)1625 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2(const LPTIM_TypeDef *LPTIMx)
1626 {
1627 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2IF) == LPTIM_ISR_CC2IF) ? 1UL : 0UL));
1628 }
1629
1630 /**
1631 * @brief Clear the Capture/Compare 1 over-capture flag for channel 1 (CC1OCF)
1632 * @rmtoll ICR CC1OCF LL_LPTIM_ClearFlag_CC1O
1633 * @param LPTIMx Low-Power Timer instance
1634 * @retval None
1635 */
LL_LPTIM_ClearFlag_CC1O(LPTIM_TypeDef * LPTIMx)1636 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC1O(LPTIM_TypeDef *LPTIMx)
1637 {
1638 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC1OCF);
1639 }
1640
1641 /**
1642 * @brief Inform application whether a Capture/Compare 1 over-capture has occurred for channel 1.
1643 * @rmtoll ISR CC1OF LL_LPTIM_IsActiveFlag_CC1O
1644 * @param LPTIMx Low-Power Timer instance
1645 * @retval State of bit (1 or 0).
1646 */
LL_LPTIM_IsActiveFlag_CC1O(const LPTIM_TypeDef * LPTIMx)1647 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1O(const LPTIM_TypeDef *LPTIMx)
1648 {
1649 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC1OF) == LPTIM_ISR_CC1OF) ? 1UL : 0UL));
1650 }
1651
1652 /**
1653 * @brief Clear the Capture/Compare 2 over-capture flag for channel 2 (CC2OCF)
1654 * @rmtoll ICR CC2OCF LL_LPTIM_ClearFlag_CC2O
1655 * @param LPTIMx Low-Power Timer instance
1656 * @retval None
1657 */
LL_LPTIM_ClearFlag_CC2O(LPTIM_TypeDef * LPTIMx)1658 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC2O(LPTIM_TypeDef *LPTIMx)
1659 {
1660 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC2OCF);
1661 }
1662
1663 /**
1664 * @brief Inform application whether a Capture/Compare 2 over-capture has occurred for channel 2.
1665 * @rmtoll ISR CC2OF LL_LPTIM_IsActiveFlag_CC2O
1666 * @param LPTIMx Low-Power Timer instance
1667 * @retval State of bit (1 or 0).
1668 */
LL_LPTIM_IsActiveFlag_CC2O(const LPTIM_TypeDef * LPTIMx)1669 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2O(const LPTIM_TypeDef *LPTIMx)
1670 {
1671 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2OF) == LPTIM_ISR_CC2OF) ? 1UL : 0UL));
1672 }
1673 /**
1674 * @brief Clear the autoreload match flag (ARRMCF)
1675 * @rmtoll ICR ARRMCF LL_LPTIM_ClearFlag_ARRM
1676 * @param LPTIMx Low-Power Timer instance
1677 * @retval None
1678 */
LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef * LPTIMx)1679 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef *LPTIMx)
1680 {
1681 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
1682 }
1683
1684 /**
1685 * @brief Inform application whether a autoreload match interrupt has occurred.
1686 * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
1687 * @param LPTIMx Low-Power Timer instance
1688 * @retval State of bit (1 or 0).
1689 */
LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef * LPTIMx)1690 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *LPTIMx)
1691 {
1692 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
1693 }
1694
1695 /**
1696 * @brief Clear the external trigger valid edge flag(EXTTRIGCF).
1697 * @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
1698 * @param LPTIMx Low-Power Timer instance
1699 * @retval None
1700 */
LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef * LPTIMx)1701 __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1702 {
1703 SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
1704 }
1705
1706 /**
1707 * @brief Inform application whether a valid edge on the selected external trigger input has occurred.
1708 * @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
1709 * @param LPTIMx Low-Power Timer instance
1710 * @retval State of bit (1 or 0).
1711 */
LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef * LPTIMx)1712 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
1713 {
1714 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
1715 }
1716
1717 /**
1718 * @brief Clear the compare register update interrupt flag (CMP1OKCF).
1719 * @rmtoll ICR CMP1OKCF LL_LPTIM_ClearFlag_CMP1OK
1720 * @param LPTIMx Low-Power Timer instance
1721 * @retval None
1722 */
LL_LPTIM_ClearFlag_CMP1OK(LPTIM_TypeDef * LPTIMx)1723 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMP1OK(LPTIM_TypeDef *LPTIMx)
1724 {
1725 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMP1OKCF);
1726 }
1727
1728 /**
1729 * @brief Informs application whether the APB bus write operation to the LPTIMx_CCR1 register has been successfully
1730 completed. If so, a new one can be initiated.
1731 * @rmtoll ISR CMP1OK LL_LPTIM_IsActiveFlag_CMP1OK
1732 * @param LPTIMx Low-Power Timer instance
1733 * @retval State of bit (1 or 0).
1734 */
LL_LPTIM_IsActiveFlag_CMP1OK(const LPTIM_TypeDef * LPTIMx)1735 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP1OK(const LPTIM_TypeDef *LPTIMx)
1736 {
1737 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMP1OK) == LPTIM_ISR_CMP1OK) ? 1UL : 0UL));
1738 }
1739
1740 /**
1741 * @brief Clear the compare register update interrupt flag (CMP2OKCF).
1742 * @rmtoll ICR CMP2OKCF LL_LPTIM_ClearFlag_CMP2OK
1743 * @param LPTIMx Low-Power Timer instance
1744 * @retval None
1745 */
LL_LPTIM_ClearFlag_CMP2OK(LPTIM_TypeDef * LPTIMx)1746 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMP2OK(LPTIM_TypeDef *LPTIMx)
1747 {
1748 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMP2OKCF);
1749 }
1750
1751 /**
1752 * @brief Informs application whether the APB bus write operation to the LPTIMx_CCR2 register has been successfully
1753 completed. If so, a new one can be initiated.
1754 * @rmtoll ISR CMP2OK LL_LPTIM_IsActiveFlag_CMP2OK
1755 * @param LPTIMx Low-Power Timer instance
1756 * @retval State of bit (1 or 0).
1757 */
LL_LPTIM_IsActiveFlag_CMP2OK(const LPTIM_TypeDef * LPTIMx)1758 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP2OK(const LPTIM_TypeDef *LPTIMx)
1759 {
1760 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMP2OK) == LPTIM_ISR_CMP2OK) ? 1UL : 0UL));
1761 }
1762
1763 /**
1764 * @brief Clear the interrupt register update interrupt flag (DIEROKCF).
1765 * @rmtoll ICR DIEROKCF LL_LPTIM_ClearFlag_DIEROK
1766 * @param LPTIMx Low-Power Timer instance
1767 * @retval None
1768 */
LL_LPTIM_ClearFlag_DIEROK(LPTIM_TypeDef * LPTIMx)1769 __STATIC_INLINE void LL_LPTIM_ClearFlag_DIEROK(LPTIM_TypeDef *LPTIMx)
1770 {
1771 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DIEROKCF);
1772 }
1773
1774 /**
1775 * @brief Informs application whether the APB bus write operation to the LPTIMx_DIER register has been successfully
1776 completed. If so, a new one can be initiated.
1777 * @rmtoll ISR DIEROK LL_LPTIM_IsActiveFlag_DIEROK
1778 * @param LPTIMx Low-Power Timer instance
1779 * @retval State of bit (1 or 0).
1780 */
LL_LPTIM_IsActiveFlag_DIEROK(const LPTIM_TypeDef * LPTIMx)1781 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DIEROK(const LPTIM_TypeDef *LPTIMx)
1782 {
1783 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DIEROK) == (LPTIM_ISR_DIEROK)) ? 1UL : 0UL);
1784 }
1785
1786 /**
1787 * @brief Clear the autoreload register update interrupt flag (ARROKCF).
1788 * @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
1789 * @param LPTIMx Low-Power Timer instance
1790 * @retval None
1791 */
LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef * LPTIMx)1792 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
1793 {
1794 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
1795 }
1796
1797 /**
1798 * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully
1799 completed. If so, a new one can be initiated.
1800 * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
1801 * @param LPTIMx Low-Power Timer instance
1802 * @retval State of bit (1 or 0).
1803 */
LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef * LPTIMx)1804 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *LPTIMx)
1805 {
1806 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
1807 }
1808
1809 /**
1810 * @brief Clear the counter direction change to up interrupt flag (UPCF).
1811 * @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP
1812 * @param LPTIMx Low-Power Timer instance
1813 * @retval None
1814 */
LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef * LPTIMx)1815 __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
1816 {
1817 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
1818 }
1819
1820 /**
1821 * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance
1822 operates in encoder mode).
1823 * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP
1824 * @param LPTIMx Low-Power Timer instance
1825 * @retval State of bit (1 or 0).
1826 */
LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef * LPTIMx)1827 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *LPTIMx)
1828 {
1829 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
1830 }
1831
1832 /**
1833 * @brief Clear the counter direction change to down interrupt flag (DOWNCF).
1834 * @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
1835 * @param LPTIMx Low-Power Timer instance
1836 * @retval None
1837 */
LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef * LPTIMx)1838 __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
1839 {
1840 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
1841 }
1842
1843 /**
1844 * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance
1845 operates in encoder mode).
1846 * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
1847 * @param LPTIMx Low-Power Timer instance
1848 * @retval State of bit (1 or 0).
1849 */
LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef * LPTIMx)1850 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *LPTIMx)
1851 {
1852 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
1853 }
1854
1855 /**
1856 * @brief Clear the repetition register update interrupt flag (REPOKCF).
1857 * @rmtoll ICR REPOKCF LL_LPTIM_ClearFlag_REPOK
1858 * @param LPTIMx Low-Power Timer instance
1859 * @retval None
1860 */
LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef * LPTIMx)1861 __STATIC_INLINE void LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef *LPTIMx)
1862 {
1863 SET_BIT(LPTIMx->ICR, LPTIM_ICR_REPOKCF);
1864 }
1865
1866 /**
1867 * @brief Informs application whether the APB bus write operation to the LPTIMx_RCR register has been successfully
1868 completed; If so, a new one can be initiated.
1869 * @rmtoll ISR REPOK LL_LPTIM_IsActiveFlag_REPOK
1870 * @param LPTIMx Low-Power Timer instance
1871 * @retval State of bit (1 or 0).
1872 */
LL_LPTIM_IsActiveFlag_REPOK(const LPTIM_TypeDef * LPTIMx)1873 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_REPOK(const LPTIM_TypeDef *LPTIMx)
1874 {
1875 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_REPOK) == (LPTIM_ISR_REPOK)) ? 1UL : 0UL);
1876 }
1877
1878 /**
1879 * @brief Clear the update event flag (UECF).
1880 * @rmtoll ICR UECF LL_LPTIM_ClearFlag_UE
1881 * @param LPTIMx Low-Power Timer instance
1882 * @retval None
1883 */
LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef * LPTIMx)1884 __STATIC_INLINE void LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef *LPTIMx)
1885 {
1886 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UECF);
1887 }
1888
1889 /**
1890 * @brief Informs application whether the LPTIMx update event has occurred.
1891 * @rmtoll ISR UE LL_LPTIM_IsActiveFlag_UE
1892 * @param LPTIMx Low-Power Timer instance
1893 * @retval State of bit (1 or 0).
1894 */
LL_LPTIM_IsActiveFlag_UE(const LPTIM_TypeDef * LPTIMx)1895 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UE(const LPTIM_TypeDef *LPTIMx)
1896 {
1897 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UE) == (LPTIM_ISR_UE)) ? 1UL : 0UL);
1898 }
1899
1900 /**
1901 * @}
1902 */
1903
1904 /** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
1905 * @{
1906 */
1907 /**
1908 * @brief Enable capture/compare 1 interrupt (CC1IE).
1909 * @rmtoll DIER CC1IE LL_LPTIM_EnableIT_CC1
1910 * @param LPTIMx Low-Power Timer instance
1911 * @retval None
1912 */
LL_LPTIM_EnableIT_CC1(LPTIM_TypeDef * LPTIMx)1913 __STATIC_INLINE void LL_LPTIM_EnableIT_CC1(LPTIM_TypeDef *LPTIMx)
1914 {
1915 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE);
1916 }
1917
1918 /**
1919 * @brief Disable capture/compare 1 interrupt (CC1IE).
1920 * @rmtoll DIER CC1IE LL_LPTIM_DisableIT_CC1
1921 * @param LPTIMx Low-Power Timer instance
1922 * @retval None
1923 */
LL_LPTIM_DisableIT_CC1(LPTIM_TypeDef * LPTIMx)1924 __STATIC_INLINE void LL_LPTIM_DisableIT_CC1(LPTIM_TypeDef *LPTIMx)
1925 {
1926 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE);
1927 }
1928
1929 /**
1930 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
1931 * @rmtoll DIER CC1IE LL_LPTIM_IsEnabledIT_CC1
1932 * @param LPTIMx Low-Power Timer instance
1933 * @retval State of bit (1 or 0).
1934 */
LL_LPTIM_IsEnabledIT_CC1(const LPTIM_TypeDef * LPTIMx)1935 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1(const LPTIM_TypeDef *LPTIMx)
1936 {
1937 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE) == LPTIM_DIER_CC1IE) ? 1UL : 0UL));
1938 }
1939
1940 /**
1941 * @brief Enable capture/compare 1 interrupt (CC2IE).
1942 * @rmtoll DIER CC2IE LL_LPTIM_EnableIT_CC2
1943 * @param LPTIMx Low-Power Timer instance
1944 * @retval None
1945 */
LL_LPTIM_EnableIT_CC2(LPTIM_TypeDef * LPTIMx)1946 __STATIC_INLINE void LL_LPTIM_EnableIT_CC2(LPTIM_TypeDef *LPTIMx)
1947 {
1948 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE);
1949 }
1950
1951 /**
1952 * @brief Disable capture/compare 2 interrupt (CC2IE).
1953 * @rmtoll DIER CC2IE LL_LPTIM_DisableIT_CC2
1954 * @param LPTIMx Low-Power Timer instance
1955 * @retval None
1956 */
LL_LPTIM_DisableIT_CC2(LPTIM_TypeDef * LPTIMx)1957 __STATIC_INLINE void LL_LPTIM_DisableIT_CC2(LPTIM_TypeDef *LPTIMx)
1958 {
1959 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE);
1960 }
1961
1962 /**
1963 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
1964 * @rmtoll DIER CC2IE LL_LPTIM_IsEnabledIT_CC2
1965 * @param LPTIMx Low-Power Timer instance
1966 * @retval State of bit (1 or 0).
1967 */
LL_LPTIM_IsEnabledIT_CC2(const LPTIM_TypeDef * LPTIMx)1968 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2(const LPTIM_TypeDef *LPTIMx)
1969 {
1970 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE) == LPTIM_DIER_CC2IE) ? 1UL : 0UL));
1971 }
1972
1973 /**
1974 * @brief Enable capture/compare 1 over-capture interrupt (CC1OIE).
1975 * @rmtoll DIER CC1OIE LL_LPTIM_EnableIT_CC1O
1976 * @param LPTIMx Low-Power Timer instance
1977 * @retval None
1978 */
LL_LPTIM_EnableIT_CC1O(LPTIM_TypeDef * LPTIMx)1979 __STATIC_INLINE void LL_LPTIM_EnableIT_CC1O(LPTIM_TypeDef *LPTIMx)
1980 {
1981 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE);
1982 }
1983
1984 /**
1985 * @brief Disable capture/compare 1 over-capture interrupt (CC1OIE).
1986 * @rmtoll DIER CC1OIE LL_LPTIM_DisableIT_CC1O
1987 * @param LPTIMx Low-Power Timer instance
1988 * @retval None
1989 */
LL_LPTIM_DisableIT_CC1O(LPTIM_TypeDef * LPTIMx)1990 __STATIC_INLINE void LL_LPTIM_DisableIT_CC1O(LPTIM_TypeDef *LPTIMx)
1991 {
1992 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE);
1993 }
1994
1995 /**
1996 * @brief Indicates whether the capture/compare 1 over-capture interrupt (CC1OIE) is enabled.
1997 * @rmtoll DIER CC1OIE LL_LPTIM_IsEnabledIT_CC1O
1998 * @param LPTIMx Low-Power Timer instance
1999 * @retval State of bit (1 or 0).
2000 */
LL_LPTIM_IsEnabledIT_CC1O(const LPTIM_TypeDef * LPTIMx)2001 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1O(const LPTIM_TypeDef *LPTIMx)
2002 {
2003 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE) == LPTIM_DIER_CC1OIE) ? 1UL : 0UL));
2004 }
2005
2006 /**
2007 * @brief Enable capture/compare 1 over-capture interrupt (CC2OIE).
2008 * @rmtoll DIER CC2OIE LL_LPTIM_EnableIT_CC2O
2009 * @param LPTIMx Low-Power Timer instance
2010 * @retval None
2011 */
LL_LPTIM_EnableIT_CC2O(LPTIM_TypeDef * LPTIMx)2012 __STATIC_INLINE void LL_LPTIM_EnableIT_CC2O(LPTIM_TypeDef *LPTIMx)
2013 {
2014 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE);
2015 }
2016
2017 /**
2018 * @brief Disable capture/compare 1 over-capture interrupt (CC2OIE).
2019 * @rmtoll DIER CC2OIE LL_LPTIM_DisableIT_CC2O
2020 * @param LPTIMx Low-Power Timer instance
2021 * @retval None
2022 */
LL_LPTIM_DisableIT_CC2O(LPTIM_TypeDef * LPTIMx)2023 __STATIC_INLINE void LL_LPTIM_DisableIT_CC2O(LPTIM_TypeDef *LPTIMx)
2024 {
2025 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE);
2026 }
2027
2028 /**
2029 * @brief Indicates whether the capture/compare 2 over-capture interrupt (CC2OIE) is enabled.
2030 * @rmtoll DIER CC2OIE LL_LPTIM_IsEnabledIT_CC2O
2031 * @param LPTIMx Low-Power Timer instance
2032 * @retval State of bit (1 or 0).
2033 */
LL_LPTIM_IsEnabledIT_CC2O(const LPTIM_TypeDef * LPTIMx)2034 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2O(const LPTIM_TypeDef *LPTIMx)
2035 {
2036 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE) == LPTIM_DIER_CC2OIE) ? 1UL : 0UL));
2037 }
2038
2039 /**
2040 * @brief Enable autoreload match interrupt (ARRMIE).
2041 * @rmtoll DIER ARRMIE LL_LPTIM_EnableIT_ARRM
2042 * @param LPTIMx Low-Power Timer instance
2043 * @retval None
2044 */
LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef * LPTIMx)2045 __STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
2046 {
2047 SET_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE);
2048 }
2049
2050 /**
2051 * @brief Disable autoreload match interrupt (ARRMIE).
2052 * @rmtoll DIER ARRMIE LL_LPTIM_DisableIT_ARRM
2053 * @param LPTIMx Low-Power Timer instance
2054 * @retval None
2055 */
LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef * LPTIMx)2056 __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
2057 {
2058 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE);
2059 }
2060
2061 /**
2062 * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
2063 * @rmtoll DIER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
2064 * @param LPTIMx Low-Power Timer instance
2065 * @retval State of bit (1 or 0).
2066 */
LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef * LPTIMx)2067 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *LPTIMx)
2068 {
2069 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE) == LPTIM_DIER_ARRMIE) ? 1UL : 0UL));
2070 }
2071
2072 /**
2073 * @brief Enable external trigger valid edge interrupt (EXTTRIGIE).
2074 * @rmtoll DIER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
2075 * @param LPTIMx Low-Power Timer instance
2076 * @retval None
2077 */
LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)2078 __STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
2079 {
2080 SET_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE);
2081 }
2082
2083 /**
2084 * @brief Disable external trigger valid edge interrupt (EXTTRIGIE).
2085 * @rmtoll DIER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
2086 * @param LPTIMx Low-Power Timer instance
2087 * @retval None
2088 */
LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)2089 __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
2090 {
2091 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE);
2092 }
2093
2094 /**
2095 * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
2096 * @rmtoll DIER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
2097 * @param LPTIMx Low-Power Timer instance
2098 * @retval State of bit (1 or 0).
2099 */
LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef * LPTIMx)2100 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
2101 {
2102 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE) == LPTIM_DIER_EXTTRIGIE) ? 1UL : 0UL));
2103 }
2104
2105 /**
2106 * @brief Enable compare register write completed interrupt (CMP1OKIE).
2107 * @rmtoll IER CMP1OKIE LL_LPTIM_EnableIT_CMP1OK
2108 * @param LPTIMx Low-Power Timer instance
2109 * @retval None
2110 */
LL_LPTIM_EnableIT_CMP1OK(LPTIM_TypeDef * LPTIMx)2111 __STATIC_INLINE void LL_LPTIM_EnableIT_CMP1OK(LPTIM_TypeDef *LPTIMx)
2112 {
2113 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE);
2114 }
2115
2116 /**
2117 * @brief Disable compare register write completed interrupt (CMP1OKIE).
2118 * @rmtoll IER CMPO1KIE LL_LPTIM_DisableIT_CMP1OK
2119 * @param LPTIMx Low-Power Timer instance
2120 * @retval None
2121 */
LL_LPTIM_DisableIT_CMP1OK(LPTIM_TypeDef * LPTIMx)2122 __STATIC_INLINE void LL_LPTIM_DisableIT_CMP1OK(LPTIM_TypeDef *LPTIMx)
2123 {
2124 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE);
2125 }
2126
2127 /**
2128 * @brief Indicates whether the compare register write completed interrupt (CMP1OKIE) is enabled.
2129 * @rmtoll IER CMP1OKIE LL_LPTIM_IsEnabledIT_CMP1OK
2130 * @param LPTIMx Low-Power Timer instance
2131 * @retval State of bit (1 or 0).
2132 */
LL_LPTIM_IsEnabledIT_CMP1OK(const LPTIM_TypeDef * LPTIMx)2133 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP1OK(const LPTIM_TypeDef *LPTIMx)
2134 {
2135 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE) == LPTIM_DIER_CMP1OKIE) ? 1UL : 0UL));
2136 }
2137
2138 /**
2139 * @brief Enable compare register write completed interrupt (CMP2OKIE).
2140 * @rmtoll IER CMP2OKIE LL_LPTIM_EnableIT_CMP2OK
2141 * @param LPTIMx Low-Power Timer instance
2142 * @retval None
2143 */
LL_LPTIM_EnableIT_CMP2OK(LPTIM_TypeDef * LPTIMx)2144 __STATIC_INLINE void LL_LPTIM_EnableIT_CMP2OK(LPTIM_TypeDef *LPTIMx)
2145 {
2146 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE);
2147 }
2148
2149 /**
2150 * @brief Disable compare register write completed interrupt (CMP2OKIE).
2151 * @rmtoll IER CMP2OKIE LL_LPTIM_DisableIT_CMP2OK
2152 * @param LPTIMx Low-Power Timer instance
2153 * @retval None
2154 */
LL_LPTIM_DisableIT_CMP2OK(LPTIM_TypeDef * LPTIMx)2155 __STATIC_INLINE void LL_LPTIM_DisableIT_CMP2OK(LPTIM_TypeDef *LPTIMx)
2156 {
2157 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE);
2158 }
2159
2160 /**
2161 * @brief Indicates whether the compare register write completed interrupt (CMP2OKIE) is enabled.
2162 * @rmtoll IER CMP2OKIE LL_LPTIM_IsEnabledIT_CMP2OK
2163 * @param LPTIMx Low-Power Timer instance
2164 * @retval State of bit (1 or 0).
2165 */
LL_LPTIM_IsEnabledIT_CMP2OK(const LPTIM_TypeDef * LPTIMx)2166 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP2OK(const LPTIM_TypeDef *LPTIMx)
2167 {
2168 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE) == LPTIM_DIER_CMP2OKIE) ? 1UL : 0UL));
2169 }
2170
2171 /**
2172 * @brief Enable autoreload register write completed interrupt (ARROKIE).
2173 * @rmtoll DIER ARROKIE LL_LPTIM_EnableIT_ARROK
2174 * @param LPTIMx Low-Power Timer instance
2175 * @retval None
2176 */
LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef * LPTIMx)2177 __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
2178 {
2179 SET_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE);
2180 }
2181
2182 /**
2183 * @brief Disable autoreload register write completed interrupt (ARROKIE).
2184 * @rmtoll DIER ARROKIE LL_LPTIM_DisableIT_ARROK
2185 * @param LPTIMx Low-Power Timer instance
2186 * @retval None
2187 */
LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef * LPTIMx)2188 __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
2189 {
2190 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE);
2191 }
2192
2193 /**
2194 * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
2195 * @rmtoll DIER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
2196 * @param LPTIMx Low-Power Timer instance
2197 * @retval State of bit(1 or 0).
2198 */
LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef * LPTIMx)2199 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *LPTIMx)
2200 {
2201 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE) == LPTIM_DIER_ARROKIE) ? 1UL : 0UL));
2202 }
2203
2204 /**
2205 * @brief Enable direction change to up interrupt (UPIE).
2206 * @rmtoll DIER UPIE LL_LPTIM_EnableIT_UP
2207 * @param LPTIMx Low-Power Timer instance
2208 * @retval None
2209 */
LL_LPTIM_EnableIT_UP(LPTIM_TypeDef * LPTIMx)2210 __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
2211 {
2212 SET_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE);
2213 }
2214
2215 /**
2216 * @brief Disable direction change to up interrupt (UPIE).
2217 * @rmtoll DIER UPIE LL_LPTIM_DisableIT_UP
2218 * @param LPTIMx Low-Power Timer instance
2219 * @retval None
2220 */
LL_LPTIM_DisableIT_UP(LPTIM_TypeDef * LPTIMx)2221 __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
2222 {
2223 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE);
2224 }
2225
2226 /**
2227 * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
2228 * @rmtoll DIER UPIE LL_LPTIM_IsEnabledIT_UP
2229 * @param LPTIMx Low-Power Timer instance
2230 * @retval State of bit(1 or 0).
2231 */
LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef * LPTIMx)2232 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *LPTIMx)
2233 {
2234 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE) == LPTIM_DIER_UPIE) ? 1UL : 0UL));
2235 }
2236
2237 /**
2238 * @brief Enable direction change to down interrupt (DOWNIE).
2239 * @rmtoll DIER DOWNIE LL_LPTIM_EnableIT_DOWN
2240 * @param LPTIMx Low-Power Timer instance
2241 * @retval None
2242 */
LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef * LPTIMx)2243 __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
2244 {
2245 SET_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE);
2246 }
2247
2248 /**
2249 * @brief Disable direction change to down interrupt (DOWNIE).
2250 * @rmtoll DIER DOWNIE LL_LPTIM_DisableIT_DOWN
2251 * @param LPTIMx Low-Power Timer instance
2252 * @retval None
2253 */
LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef * LPTIMx)2254 __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
2255 {
2256 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE);
2257 }
2258
2259 /**
2260 * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
2261 * @rmtoll DIER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
2262 * @param LPTIMx Low-Power Timer instance
2263 * @retval State of bit(1 or 0).
2264 */
LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef * LPTIMx)2265 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *LPTIMx)
2266 {
2267 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE) == LPTIM_DIER_DOWNIE) ? 1UL : 0UL);
2268 }
2269
2270 /**
2271 * @brief Enable repetition register update successfully completed interrupt (REPOKIE).
2272 * @rmtoll DIER REPOKIE LL_LPTIM_EnableIT_REPOK
2273 * @param LPTIMx Low-Power Timer instance
2274 * @retval None
2275 */
LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef * LPTIMx)2276 __STATIC_INLINE void LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef *LPTIMx)
2277 {
2278 SET_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE);
2279 }
2280
2281 /**
2282 * @brief Disable repetition register update successfully completed interrupt (REPOKIE).
2283 * @rmtoll DIER REPOKIE LL_LPTIM_DisableIT_REPOK
2284 * @param LPTIMx Low-Power Timer instance
2285 * @retval None
2286 */
LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef * LPTIMx)2287 __STATIC_INLINE void LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef *LPTIMx)
2288 {
2289 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE);
2290 }
2291
2292 /**
2293 * @brief Indicates whether the repetition register update successfully completed interrupt (REPOKIE) is enabled.
2294 * @rmtoll DIER REPOKIE LL_LPTIM_IsEnabledIT_REPOK
2295 * @param LPTIMx Low-Power Timer instance
2296 * @retval State of bit(1 or 0).
2297 */
LL_LPTIM_IsEnabledIT_REPOK(const LPTIM_TypeDef * LPTIMx)2298 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_REPOK(const LPTIM_TypeDef *LPTIMx)
2299 {
2300 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE) == (LPTIM_DIER_REPOKIE)) ? 1UL : 0UL);
2301 }
2302
2303 /**
2304 * @brief Enable update event interrupt (UEIE).
2305 * @rmtoll DIER UEIE LL_LPTIM_EnableIT_UE
2306 * @param LPTIMx Low-Power Timer instance
2307 * @retval None
2308 */
LL_LPTIM_EnableIT_UE(LPTIM_TypeDef * LPTIMx)2309 __STATIC_INLINE void LL_LPTIM_EnableIT_UE(LPTIM_TypeDef *LPTIMx)
2310 {
2311 SET_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE);
2312 }
2313
2314 /**
2315 * @brief Disable update event interrupt (UEIE).
2316 * @rmtoll DIER UEIE LL_LPTIM_DisableIT_UE
2317 * @param LPTIMx Low-Power Timer instance
2318 * @retval None
2319 */
LL_LPTIM_DisableIT_UE(LPTIM_TypeDef * LPTIMx)2320 __STATIC_INLINE void LL_LPTIM_DisableIT_UE(LPTIM_TypeDef *LPTIMx)
2321 {
2322 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE);
2323 }
2324
2325 /**
2326 * @brief Indicates whether the update event interrupt (UEIE) is enabled.
2327 * @rmtoll DIER UEIE LL_LPTIM_IsEnabledIT_UE
2328 * @param LPTIMx Low-Power Timer instance
2329 *@ retval State of bit(1 or 0).
2330 */
LL_LPTIM_IsEnabledIT_UE(const LPTIM_TypeDef * LPTIMx)2331 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UE(const LPTIM_TypeDef *LPTIMx)
2332 {
2333 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE) == (LPTIM_DIER_UEIE)) ? 1UL : 0UL);
2334 }
2335 /**
2336 * @}
2337 */
2338
2339
2340 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
2341 * @{
2342 */
2343 /**
2344 * @brief Enable update DMA request.
2345 * @rmtoll DIER UEDE LL_LPTIM_EnableDMAReq_UPDATE
2346 * @param LPTIMx Low-Power Timer instance
2347 * @retval None
2348 */
LL_LPTIM_EnableDMAReq_UPDATE(LPTIM_TypeDef * LPTIMx)2349 __STATIC_INLINE void LL_LPTIM_EnableDMAReq_UPDATE(LPTIM_TypeDef *LPTIMx)
2350 {
2351 SET_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE);
2352 }
2353
2354 /**
2355 * @brief Disable update DMA request.
2356 * @rmtoll DIER UEDE LL_LPTIM_DisableDMAReq_UPDATE
2357 * @param LPTIMx Low-Power Timer instance
2358 * @retval None
2359 */
LL_LPTIM_DisableDMAReq_UPDATE(LPTIM_TypeDef * LPTIMx)2360 __STATIC_INLINE void LL_LPTIM_DisableDMAReq_UPDATE(LPTIM_TypeDef *LPTIMx)
2361 {
2362 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE);
2363 }
2364
2365 /**
2366 * @brief Indicates whether the update DMA request is enabled.
2367 * @rmtoll DIER UEDE LL_LPTIM_IsEnabledDMAReq_UPDATE
2368 * @param LPTIMx Low-Power Timer instance
2369 * @retval State of bit (1 or 0).
2370 */
LL_LPTIM_IsEnabledDMAReq_UPDATE(const LPTIM_TypeDef * LPTIMx)2371 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_UPDATE(const LPTIM_TypeDef *LPTIMx)
2372 {
2373 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE) == (LPTIM_DIER_UEDE)) ? 1UL : 0UL);
2374 }
2375
2376 /**
2377 * @brief Enable capture/compare 1 DMA request (CC1DE).
2378 * @rmtoll DIER CC1DE LL_LPTIM_EnableDMAReq_CC1
2379 * @param LPTIMx Low-Power Timer instance
2380 * @retval None
2381 */
LL_LPTIM_EnableDMAReq_CC1(LPTIM_TypeDef * LPTIMx)2382 __STATIC_INLINE void LL_LPTIM_EnableDMAReq_CC1(LPTIM_TypeDef *LPTIMx)
2383 {
2384 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE);
2385 }
2386
2387 /**
2388 * @brief Disable capture/compare 1 DMA request (CC1DE).
2389 * @rmtoll DIER CC1DE LL_LPTIM_DisableDMAReq_CC1
2390 * @param LPTIMx Low-Power Timer instance
2391 * @retval None
2392 */
LL_LPTIM_DisableDMAReq_CC1(LPTIM_TypeDef * LPTIMx)2393 __STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC1(LPTIM_TypeDef *LPTIMx)
2394 {
2395 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE);
2396 }
2397
2398 /**
2399 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
2400 * @rmtoll DIER CC1DE LL_LPTIM_IsEnabledDMAReq_CC1
2401 * @param LPTIMx Low-Power Timer instance
2402 * @retval State of bit (1 or 0).
2403 */
LL_LPTIM_IsEnabledDMAReq_CC1(const LPTIM_TypeDef * LPTIMx)2404 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC1(const LPTIM_TypeDef *LPTIMx)
2405 {
2406 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE) == (LPTIM_DIER_CC1DE)) ? 1UL : 0UL);
2407 }
2408
2409 /**
2410 * @brief Enable capture/compare 2 DMA request (CC2DE).
2411 * @rmtoll DIER CC2DE LL_LPTIM_EnableDMAReq_CC2
2412 * @param LPTIMx Low-Power Timer instance
2413 * @retval None
2414 */
LL_LPTIM_EnableDMAReq_CC2(LPTIM_TypeDef * LPTIMx)2415 __STATIC_INLINE void LL_LPTIM_EnableDMAReq_CC2(LPTIM_TypeDef *LPTIMx)
2416 {
2417 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE);
2418 }
2419
2420 /**
2421 * @brief Disable capture/compare 2 DMA request (CC2DE).
2422 * @rmtoll DIER CC2DE LL_LPTIM_DisableDMAReq_CC2
2423 * @param LPTIMx Low-Power Timer instance
2424 * @retval None
2425 */
LL_LPTIM_DisableDMAReq_CC2(LPTIM_TypeDef * LPTIMx)2426 __STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC2(LPTIM_TypeDef *LPTIMx)
2427 {
2428 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE);
2429 }
2430
2431 /**
2432 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
2433 * @rmtoll DIER CC2DE LL_LPTIM_IsEnabledDMAReq_CC2
2434 * @param LPTIMx Low-Power Timer instance
2435 * @retval State of bit (1 or 0).
2436 */
LL_LPTIM_IsEnabledDMAReq_CC2(const LPTIM_TypeDef * LPTIMx)2437 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC2(const LPTIM_TypeDef *LPTIMx)
2438 {
2439 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE) == (LPTIM_DIER_CC2DE)) ? 1UL : 0UL);
2440 }
2441
2442 /**
2443 * @}
2444 */
2445 /**
2446 * @}
2447 */
2448
2449 /**
2450 * @}
2451 */
2452
2453 #endif /* LPTIM1 || LPTIM2 || LPTIM3 || LPTIM4 */
2454
2455 /**
2456 * @}
2457 */
2458
2459 #ifdef __cplusplus
2460 }
2461 #endif
2462
2463 #endif /* STM32U5xx_LL_LPTIM_H */
2464
