1 /** 2 ****************************************************************************** 3 * @file stm32l5xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef STM32L5xx_HAL_RCC_EX_H 20 #define STM32L5xx_HAL_RCC_EX_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32l5xx_hal_def.h" 28 29 /** @addtogroup STM32L5xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup RCCEx 34 * @{ 35 */ 36 37 /* Exported types ------------------------------------------------------------*/ 38 39 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief PLLSAI1 Clock structure definition 45 */ 46 typedef struct 47 { 48 49 uint32_t PLLSAI1Source; /*!< PLLSAI1Source: PLLSAI1 entry clock source. 50 This parameter must be a value of @ref RCC_PLLSAI1_Clock_Source */ 51 52 uint32_t PLLSAI1M; /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock. 53 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ 54 55 uint32_t PLLSAI1N; /*!< PLLSAI1N: specifies the multiplication factor for PLLSAI1 VCO output clock. 56 This parameter must be a number between 8 and 86 or 127 depending on devices. */ 57 58 uint32_t PLLSAI1P; /*!< PLLSAI1P: specifies the division factor for SAI clock. 59 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 60 61 uint32_t PLLSAI1Q; /*!< PLLSAI1Q: specifies the division factor for USB/RNG/SDMMC1 clock. 62 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ 63 64 uint32_t PLLSAI1R; /*!< PLLSAI1R: specifies the division factor for ADC clock. 65 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ 66 67 uint32_t PLLSAI1ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI1 output clock to be enabled. 68 This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */ 69 } RCC_PLLSAI1InitTypeDef; 70 71 /** 72 * @brief PLLSAI2 Clock structure definition 73 */ 74 typedef struct 75 { 76 77 uint32_t PLLSAI2Source; /*!< PLLSAI2Source: PLLSAI2 entry clock source. 78 This parameter must be a value of @ref RCC_PLLSAI2_Clock_Source */ 79 80 uint32_t PLLSAI2M; /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock. 81 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ 82 83 uint32_t PLLSAI2N; /*!< PLLSAI2N: specifies the multiplication factor for PLLSAI2 VCO output clock. 84 This parameter must be a number between 8 and 86 or 127 depending on devices. */ 85 86 uint32_t PLLSAI2P; /*!< PLLSAI2P: specifies the division factor for SAI clock. 87 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 88 89 uint32_t PLLSAI2ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI2 output clock to be enabled. 90 This parameter must be a value of @ref RCC_PLLSAI2_Clock_Output */ 91 } RCC_PLLSAI2InitTypeDef; 92 93 /** 94 * @brief RCC extended clocks structure definition 95 */ 96 typedef struct 97 { 98 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 99 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 100 101 RCC_PLLSAI1InitTypeDef PLLSAI1; /*!< PLLSAI1 structure parameters. 102 This parameter will be used only when PLLSAI1 is selected as Clock Source for SAI1, USB/RNG/SDMMC1 or ADC */ 103 104 RCC_PLLSAI2InitTypeDef PLLSAI2; /*!< PLLSAI2 structure parameters. 105 This parameter will be used only when PLLSAI2 is selected as Clock Source for SAI2 or ADC */ 106 107 uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. 108 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 109 110 uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. 111 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ 112 113 uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source. 114 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ 115 116 uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source. 117 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ 118 119 uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source. 120 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ 121 122 uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. 123 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ 124 125 uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. 126 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ 127 128 uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source. 129 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ 130 131 uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. 132 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ 133 134 uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source. 135 This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ 136 137 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. 138 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 139 140 uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source. 141 This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ 142 143 uint32_t Lptim3ClockSelection; /*!< Specifies LPTIM3 clock source. 144 This parameter can be a value of @ref RCCEx_LPTIM3_Clock_Source */ 145 146 uint32_t FdcanClockSelection; /*!< Specifies FDCAN kernel clock source. 147 This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source */ 148 149 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. 150 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ 151 152 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source. 153 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ 154 155 #if defined(USB) 156 157 uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for SDMMC1 and RNG). 158 This parameter can be a value of @ref RCCEx_USB_Clock_Source */ 159 160 #endif /* USB */ 161 162 uint32_t Sdmmc1ClockSelection; /*!< Specifies SDMMC1 clock source (warning: same source for USB and RNG). 163 This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ 164 165 uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB and SDMMC1). 166 This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ 167 168 uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source. 169 This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ 170 171 uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 clock source. 172 This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source */ 173 174 uint32_t Dfsdm1AudioClockSelection; /*!< Specifies DFSDM1 audio clock source. 175 This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */ 176 177 uint32_t OspiClockSelection; /*!< Specifies OctoSPI clock source. 178 This parameter can be a value of @ref RCCEx_OSPI_Clock_Source */ 179 180 uint32_t RTCClockSelection; /*!< Specifies RTC clock source. 181 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 182 } RCC_PeriphCLKInitTypeDef; 183 184 185 #if defined(CRS) 186 187 /** 188 * @brief RCC_CRS Init structure definition 189 */ 190 typedef struct 191 { 192 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. 193 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ 194 195 uint32_t Source; /*!< Specifies the SYNC signal source. 196 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ 197 198 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. 199 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ 200 201 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. 202 It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) 203 This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ 204 205 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. 206 This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ 207 208 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. 209 This parameter must be a number between 0 and 0x7F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ 210 211 } RCC_CRSInitTypeDef; 212 213 /** 214 * @brief RCC_CRS Synchronization structure definition 215 */ 216 typedef struct 217 { 218 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. 219 This parameter must be a number between 0 and 0xFFFF */ 220 221 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. 222 This parameter must be a number between 0 and 0x7F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ 223 224 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter 225 value latched in the time of the last SYNC event. 226 This parameter must be a number between 0 and 0xFFFF */ 227 228 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the 229 frequency error counter latched in the time of the last SYNC event. 230 It shows whether the actual frequency is below or above the target. 231 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ 232 233 } RCC_CRSSynchroInfoTypeDef; 234 235 #endif /* CRS */ 236 /** 237 * @} 238 */ 239 240 /* Exported constants --------------------------------------------------------*/ 241 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 242 * @{ 243 */ 244 245 /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source 246 * @{ 247 */ 248 #define RCC_LSCOSOURCE_LSI 0U /*!< LSI selection for low speed clock output */ 249 #define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */ 250 /** 251 * @} 252 */ 253 254 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection 255 * @{ 256 */ 257 #define RCC_PERIPHCLK_USART1 0x00000001U 258 #define RCC_PERIPHCLK_USART2 0x00000002U 259 #define RCC_PERIPHCLK_USART3 0x00000004U 260 #define RCC_PERIPHCLK_UART4 0x00000008U 261 #define RCC_PERIPHCLK_UART5 0x00000010U 262 #define RCC_PERIPHCLK_LPUART1 0x00000020U 263 #define RCC_PERIPHCLK_I2C1 0x00000040U 264 #define RCC_PERIPHCLK_I2C2 0x00000080U 265 #define RCC_PERIPHCLK_I2C3 0x00000100U 266 #define RCC_PERIPHCLK_LPTIM1 0x00000200U 267 #define RCC_PERIPHCLK_LPTIM2 0x00000400U 268 #define RCC_PERIPHCLK_SAI1 0x00000800U 269 #define RCC_PERIPHCLK_SAI2 0x00001000U 270 #if defined(USB) 271 #define RCC_PERIPHCLK_USB 0x00002000U 272 #endif /* USB */ 273 #define RCC_PERIPHCLK_ADC 0x00004000U 274 #define RCC_PERIPHCLK_DFSDM1 0x00010000U 275 #define RCC_PERIPHCLK_RTC 0x00020000U 276 #define RCC_PERIPHCLK_RNG 0x00040000U 277 #define RCC_PERIPHCLK_SDMMC1 0x00080000U 278 #define RCC_PERIPHCLK_I2C4 0x00100000U 279 #define RCC_PERIPHCLK_DFSDM1AUDIO 0x00200000U 280 #define RCC_PERIPHCLK_LPTIM3 0x00400000U 281 #define RCC_PERIPHCLK_OSPI 0x01000000U 282 #define RCC_PERIPHCLK_FDCAN 0x02000000U 283 /** 284 * @} 285 */ 286 287 288 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source 289 * @{ 290 */ 291 #define RCC_USART1CLKSOURCE_PCLK2 0U /*!< PCLK2 */ 292 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR1_USART1SEL_0 /*!< System clock */ 293 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR1_USART1SEL_1 /*!< HSI */ 294 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR1_USART1SEL_0 | RCC_CCIPR1_USART1SEL_1) /*!< LSE */ 295 /** 296 * @} 297 */ 298 299 /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source 300 * @{ 301 */ 302 #define RCC_USART2CLKSOURCE_PCLK1 0U /*!< PCLK1 */ 303 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR1_USART2SEL_0 /*!< System clock */ 304 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR1_USART2SEL_1 /*!< HSI */ 305 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR1_USART2SEL_0 | RCC_CCIPR1_USART2SEL_1) /*!< LSE */ 306 /** 307 * @} 308 */ 309 310 /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source 311 * @{ 312 */ 313 #define RCC_USART3CLKSOURCE_PCLK1 0U /*!< PCLK1 */ 314 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR1_USART3SEL_0 /*!< System clock */ 315 #define RCC_USART3CLKSOURCE_HSI RCC_CCIPR1_USART3SEL_1 /*!< HSI */ 316 #define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR1_USART3SEL_0 | RCC_CCIPR1_USART3SEL_1) /*!< LSE */ 317 /** 318 * @} 319 */ 320 321 /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source 322 * @{ 323 */ 324 #define RCC_UART4CLKSOURCE_PCLK1 0U /*!< PCLK1 */ 325 #define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR1_UART4SEL_0 /*!< System clock */ 326 #define RCC_UART4CLKSOURCE_HSI RCC_CCIPR1_UART4SEL_1 /*!< HSI */ 327 #define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR1_UART4SEL_0 | RCC_CCIPR1_UART4SEL_1) /*!< LSE */ 328 /** 329 * @} 330 */ 331 332 /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source 333 * @{ 334 */ 335 #define RCC_UART5CLKSOURCE_PCLK1 0U /*!< PCLK1 */ 336 #define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR1_UART5SEL_0 /*!< System clock */ 337 #define RCC_UART5CLKSOURCE_HSI RCC_CCIPR1_UART5SEL_1 /*!< HSI */ 338 #define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR1_UART5SEL_0 | RCC_CCIPR1_UART5SEL_1) /*!< LSE */ 339 /** 340 * @} 341 */ 342 343 /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source 344 * @{ 345 */ 346 #define RCC_LPUART1CLKSOURCE_PCLK1 0U /*!< PCLK1 */ 347 #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR1_LPUART1SEL_0 /*!< System clock */ 348 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR1_LPUART1SEL_1 /*!< HSI */ 349 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR1_LPUART1SEL_0 | RCC_CCIPR1_LPUART1SEL_1) /*!< LSE */ 350 /** 351 * @} 352 */ 353 354 /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source 355 * @{ 356 */ 357 #define RCC_I2C1CLKSOURCE_PCLK1 0U /*!< PCLK1 */ 358 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR1_I2C1SEL_0 /*!< System clock */ 359 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR1_I2C1SEL_1 /*!< HSI */ 360 /** 361 * @} 362 */ 363 364 /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source 365 * @{ 366 */ 367 #define RCC_I2C2CLKSOURCE_PCLK1 0U /*!< PCLK1 */ 368 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR1_I2C2SEL_0 /*!< System clock */ 369 #define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR1_I2C2SEL_1 /*!< HSI */ 370 /** 371 * @} 372 */ 373 374 /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source 375 * @{ 376 */ 377 #define RCC_I2C3CLKSOURCE_PCLK1 0U /*!< PCLK1 */ 378 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR1_I2C3SEL_0 /*!< System clock */ 379 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR1_I2C3SEL_1 /*!< HSI */ 380 /** 381 * @} 382 */ 383 384 /** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source 385 * @{ 386 */ 387 #define RCC_I2C4CLKSOURCE_PCLK1 0U /*!< PCLK1 */ 388 #define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR2_I2C4SEL_0 /*!< System clock */ 389 #define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR2_I2C4SEL_1 /*!< HSI */ 390 /** 391 * @} 392 */ 393 394 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source 395 * @{ 396 */ 397 #define RCC_SAI1CLKSOURCE_PLLSAI1 0U /*!< PLLSAI1 "P" clock (PLLSAI1CLK) */ 398 #define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI1SEL_0 /*!< PLLSAI2 "P" clock (PLLSAI2CLK) */ 399 #define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR2_SAI1SEL_1 /*!< PLL "P" clock (PLLSAI3CLK) */ 400 #define RCC_SAI1CLKSOURCE_PIN (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0) /*!< External clock SAI1_EXTCLK */ 401 #define RCC_SAI1CLKSOURCE_HSI RCC_CCIPR2_SAI1SEL_2 /*!< HSI */ 402 /** 403 * @} 404 */ 405 406 /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source 407 * @{ 408 */ 409 #define RCC_SAI2CLKSOURCE_PLLSAI1 0U /*!< PLLSAI1 "P" clock (PLLSAI1CLK) */ 410 #define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI2SEL_0 /*!< PLLSAI2 "P" clock (PLLSAI2CLK) */ 411 #define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR2_SAI2SEL_1 /*!< PLL "P" clock (PLLSAI3CLK) */ 412 #define RCC_SAI2CLKSOURCE_PIN (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0) /*!< External clock SAI1_EXTCLK */ 413 #define RCC_SAI2CLKSOURCE_HSI RCC_CCIPR2_SAI2SEL_2 /*!< HSI */ 414 /** 415 * @} 416 */ 417 418 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source 419 * @{ 420 */ 421 #define RCC_LPTIM1CLKSOURCE_PCLK1 0U /*!< PCLK1 */ 422 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR1_LPTIM1SEL_0 /*!< LSI */ 423 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR1_LPTIM1SEL_1 /*!< HSI */ 424 #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR1_LPTIM1SEL /*!< LSE */ 425 /** 426 * @} 427 */ 428 429 /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source 430 * @{ 431 */ 432 #define RCC_LPTIM2CLKSOURCE_PCLK1 0U /*!< PCLK1 */ 433 #define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR1_LPTIM2SEL_0 /*!< LSI */ 434 #define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR1_LPTIM2SEL_1 /*!< HSI */ 435 #define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR1_LPTIM2SEL /*!< LSE */ 436 /** 437 * @} 438 */ 439 440 /** @defgroup RCCEx_LPTIM3_Clock_Source LPTIM3 Clock Source 441 * @{ 442 */ 443 #define RCC_LPTIM3CLKSOURCE_PCLK1 0U /*!< PCLK1 */ 444 #define RCC_LPTIM3CLKSOURCE_LSI RCC_CCIPR1_LPTIM3SEL_0 /*!< LSI */ 445 #define RCC_LPTIM3CLKSOURCE_HSI RCC_CCIPR1_LPTIM3SEL_1 /*!< HSI */ 446 #define RCC_LPTIM3CLKSOURCE_LSE RCC_CCIPR1_LPTIM3SEL /*!< LSE */ 447 /** 448 * @} 449 */ 450 451 /** @defgroup RCCEx_FDCAN_Clock_Source FDCAN Kernel Clock Source 452 * @{ 453 */ 454 #define RCC_FDCANCLKSOURCE_HSE 0U /*!< LSE */ 455 #define RCC_FDCANCLKSOURCE_PLL RCC_CCIPR1_FDCANSEL_0 /*!< PLL "Q" clock (PLL48M1CLK) */ 456 #define RCC_FDCANCLKSOURCE_PLLSAI1 RCC_CCIPR1_FDCANSEL_1 /*!< PLLSAI1 "P" clock (PLLSAI1CLK) */ 457 /** 458 * @} 459 */ 460 461 /** @defgroup RCCEx_SDMMC1_Clock_Source SDMMC1 Clock Source 462 * @{ 463 */ 464 #define RCC_SDMMC1CLKSOURCE_HSI48 0U /*!< HSI48 via internal multiplexer */ 465 #define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR1_CLK48MSEL_0 /*!< PLLSAI1 "Q" clock (PLL48M2CLK) via internal multiplexer */ 466 #define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR1_CLK48MSEL_1 /*!< PLL "Q" clock (PLL48M1CLK) via internal multiplexer */ 467 #define RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR1_CLK48MSEL /*!< MSI via internal multiplexer */ 468 #define RCC_SDMMC1CLKSOURCE_PLLP RCC_CCIPR2_SDMMCSEL /*!< PLL "Q" clock (PLLSAI3CLK) */ 469 /** 470 * @} 471 */ 472 473 /** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source 474 * @{ 475 */ 476 #define RCC_RNGCLKSOURCE_HSI48 0U /*!< HSI48 */ 477 #define RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR1_CLK48MSEL_0 /*!< PLLSAI1 "Q" clock (PLL48M2CLK) */ 478 #define RCC_RNGCLKSOURCE_PLL RCC_CCIPR1_CLK48MSEL_1 /*!< PLL "Q" clock (PLL48M1CLK) */ 479 #define RCC_RNGCLKSOURCE_MSI RCC_CCIPR1_CLK48MSEL /*!< MSI */ 480 /** 481 * @} 482 */ 483 484 #if defined(USB) 485 /** @defgroup RCCEx_USB_Clock_Source USB Clock Source 486 * @{ 487 */ 488 #define RCC_USBCLKSOURCE_HSI48 0U /*!< HSI48 */ 489 #define RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR1_CLK48MSEL_0 /*!< PLLSAI1 "Q" clock (PLL48M2CLK) */ 490 #define RCC_USBCLKSOURCE_PLL RCC_CCIPR1_CLK48MSEL_1 /*!< PLL "Q" clock (PLL48M1CLK) */ 491 #define RCC_USBCLKSOURCE_MSI RCC_CCIPR1_CLK48MSEL /*!< MSI */ 492 /** 493 * @} 494 */ 495 #endif /* USB */ 496 497 /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source 498 * @{ 499 */ 500 #define RCC_ADCCLKSOURCE_NONE 0U /*!< No clock */ 501 #define RCC_ADCCLKSOURCE_PLLSAI1 RCC_CCIPR1_ADCSEL_0 /*!< PLLSAI "R" clock (PLLADC1CLK) */ 502 #define RCC_ADCCLKSOURCE_SYSCLK RCC_CCIPR1_ADCSEL /*!< System clock */ 503 /** 504 * @} 505 */ 506 507 /** @defgroup RCCEx_DFSDM1_Clock_Source DFSDM1 Clock Source 508 * @{ 509 */ 510 #define RCC_DFSDM1CLKSOURCE_PCLK2 0U /*!< PCLK2 */ 511 #define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR2_DFSDMSEL /*!< System clock */ 512 /** 513 * @} 514 */ 515 516 /** @defgroup RCCEx_DFSDM1_Audio_Clock_Source DFSDM1 Audio Clock Source 517 * @{ 518 */ 519 #define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 0U /*!< SAI1 clock */ 520 #define RCC_DFSDM1AUDIOCLKSOURCE_HSI RCC_CCIPR2_ADFSDMSEL_0 /*!< HSI */ 521 #define RCC_DFSDM1AUDIOCLKSOURCE_MSI RCC_CCIPR2_ADFSDMSEL_1 /*!< MSI */ 522 /** 523 * @} 524 */ 525 526 /** @defgroup RCCEx_OSPI_Clock_Source OctoSPI Clock Source 527 * @{ 528 */ 529 #define RCC_OSPICLKSOURCE_SYSCLK 0U /*!< System clock */ 530 #define RCC_OSPICLKSOURCE_MSI RCC_CCIPR2_OSPISEL_0 /*!< MSI */ 531 #define RCC_OSPICLKSOURCE_PLL RCC_CCIPR2_OSPISEL_1 /*!< PLL "Q" clock (PLL48M1CLK) */ 532 /** 533 * @} 534 */ 535 536 537 /** @defgroup RCCEx_SecureMode RCCEx Secure Mode 538 * @note Only available when system implements security (TZEN=1) 539 * @{ 540 */ 541 #define RCC_SECURE_NONE 0U /*!< No security on RCC resources (default) */ 542 #define RCC_SECURE_ALL 0x1FFFU /*!< Security on all RCC resources */ 543 544 #define RCC_SECURE_HSI RCC_SECCFGR_HSISEC /*!< HSI clock configuration security */ 545 #define RCC_SECURE_HSE RCC_SECCFGR_HSESEC /*!< HSE clock configuration security */ 546 #define RCC_SECURE_MSI RCC_SECCFGR_MSISEC /*!< MSI clock configuration security */ 547 #define RCC_SECURE_LSI RCC_SECCFGR_LSISEC /*!< LSI clock configuration security */ 548 #define RCC_SECURE_SYSCLK RCC_SECCFGR_SYSCLKSEC /*!< SYSCLK clock; STOPWUCK and MCO output configuration security */ 549 #define RCC_SECURE_PRESCALERS RCC_SECCFGR_PRESCSEC /*!< AHBx/APBx prescaler configuration security */ 550 #define RCC_SECURE_PLL RCC_SECCFGR_PLLSEC /*!< main PLL clock configuration security */ 551 #define RCC_SECURE_PLLSAI1 RCC_SECCFGR_PLLSAI1SEC /*!< PLLSAI1 clock configuration security */ 552 #define RCC_SECURE_PLLSAI2 RCC_SECCFGR_PLLSAI2SEC /*!< PLLSAI2 clock configuration security */ 553 #define RCC_SECURE_CLK48M RCC_SECCFGR_CLK48MSEC /*!< 48MHz clock source selection security */ 554 #define RCC_SECURE_HSI48 RCC_SECCFGR_HSI48SEC /*!< HSI48 clock configuration security */ 555 #define RCC_SECURE_RESET_FLAGS RCC_SECCFGR_RMVFSEC /*!< Remove reset flag security */ 556 /** 557 * @} 558 */ 559 560 #if defined(CRS) 561 562 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status 563 * @{ 564 */ 565 #define RCC_CRS_NONE 0x00000000U 566 #define RCC_CRS_TIMEOUT 0x00000001U 567 #define RCC_CRS_SYNCOK 0x00000002U 568 #define RCC_CRS_SYNCWARN 0x00000004U 569 #define RCC_CRS_SYNCERR 0x00000008U 570 #define RCC_CRS_SYNCMISS 0x00000010U 571 #define RCC_CRS_TRIMOVF 0x00000020U 572 /** 573 * @} 574 */ 575 576 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource 577 * @{ 578 */ 579 #define RCC_CRS_SYNC_SOURCE_GPIO 0U /*!< Synchro Signal source GPIO */ 580 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ 581 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ 582 /** 583 * @} 584 */ 585 586 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider 587 * @{ 588 */ 589 #define RCC_CRS_SYNC_DIV1 0U /*!< Synchro Signal not divided (default) */ 590 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ 591 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ 592 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ 593 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ 594 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ 595 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ 596 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ 597 /** 598 * @} 599 */ 600 601 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity 602 * @{ 603 */ 604 #define RCC_CRS_SYNC_POLARITY_RISING 0U /*!< Synchro Active on rising edge (default) */ 605 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ 606 /** 607 * @} 608 */ 609 610 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault 611 * @{ 612 */ 613 #define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds 614 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ 615 /** 616 * @} 617 */ 618 619 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault 620 * @{ 621 */ 622 #define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /*!< Default Frequency error limit */ 623 /** 624 * @} 625 */ 626 627 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault 628 * @{ 629 */ 630 #define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U /*!< The default value is 64, which corresponds to the middle of the trimming interval. 631 The trimming step is specified in the product datasheet. A higher TRIM value corresponds 632 to a higher output frequency */ 633 /** 634 * @} 635 */ 636 637 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection 638 * @{ 639 */ 640 #define RCC_CRS_FREQERRORDIR_UP 0U /*!< Upcounting direction, the actual frequency is above the target */ 641 #define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ 642 /** 643 * @} 644 */ 645 646 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources 647 * @{ 648 */ 649 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ 650 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ 651 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ 652 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ 653 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ 654 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ 655 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ 656 657 /** 658 * @} 659 */ 660 661 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags 662 * @{ 663 */ 664 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ 665 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ 666 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ 667 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ 668 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ 669 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ 670 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ 671 672 /** 673 * @} 674 */ 675 676 #endif /* CRS */ 677 678 /** 679 * @} 680 */ 681 682 /* Exported macros -----------------------------------------------------------*/ 683 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 684 * @{ 685 */ 686 687 688 /** 689 * @brief Macro to configure the PLLSAI1 clock multiplication and division factors. 690 * 691 * @note This macro must be used only when the PLLSAI1 is disabled. 692 * @note This macro preserves the PLLSAI1's output clocks enable state. 693 * 694 * @param __PLLSAI1SOURCE__ specifies the PLLSAI1 entry clock source. 695 * This parameter can be one of the following values: 696 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLLSAI1 clock entry 697 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLLSAI1 clock entry 698 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLLSAI1 clock entry 699 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLLSAI1 clock entry 700 * 701 * @param __PLLSAI1M__ specifies the division factor of PLLSAI1 input clock. 702 * This parameter must be a number between Min_Data = 1 and Max_Data = 16. 703 * 704 * @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock. 705 * This parameter must be a number between Min_Data = 8 and Max_Data = 86. 706 * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO 707 * output frequency is between 64 and 344 MHz. 708 * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N 709 * 710 * @param __PLLSAI1P__ specifies the division factor for SAI clock. 711 * This parameter must be a number between Min_Data = 2 to Max_Data = 31. 712 * SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P 713 * 714 * @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock. 715 * This parameter must be in the range (2, 4, 6 or 8). 716 * USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q 717 * 718 * @param __PLLSAI1R__ specifies the division factor for SAR ADC clock. 719 * This parameter must be in the range (2, 4, 6 or 8). 720 * ADC clock frequency = f(PLLSAI1) / PLLSAI1R 721 * 722 * @retval None 723 */ 724 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1SOURCE__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ 725 MODIFY_REG(RCC->PLLSAI1CFGR, \ 726 (RCC_PLLSAI1CFGR_PLLSAI1SRC | RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | \ 727 RCC_PLLSAI1CFGR_PLLSAI1P | RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R | \ 728 RCC_PLLSAI1CFGR_PLLSAI1PDIV), \ 729 ((__PLLSAI1SOURCE__) | \ 730 (((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) | \ 731 ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ 732 ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ 733 ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ 734 ((__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))) 735 736 /** 737 * @brief Macro to configure the PLLSAI1 clock multiplication factor N. 738 * 739 * @note This function must be used only when the PLLSAI1 is disabled. 740 * @note PLLSAI1 clock source is common with the main PLL (configured through 741 * __HAL_RCC_PLL_CONFIG() macro) 742 * 743 * @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock. 744 * This parameter must be a number between 8 and 86. 745 * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO 746 * output frequency is between 64 and 344 MHz. 747 * Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N 748 * 749 * @retval None 750 */ 751 #define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \ 752 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) 753 754 /** @brief Macro to configure the PLLSAI1 input clock division factor M. 755 * 756 * @note This function must be used only when the PLLSAI1 is disabled. 757 * @note PLLSAI1 clock source is common with the main PLL (configured through 758 * __HAL_RCC_PLL_CONFIG() macro) 759 * 760 * @param __PLLSAI1M__ specifies the division factor for PLLSAI1 clock. 761 * This parameter must be a number between Min_Data = 1 and Max_Data = 16. 762 * 763 * @retval None 764 */ 765 #define __HAL_RCC_PLLSAI1_DIVM_CONFIG(__PLLSAI1M__) \ 766 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M, ((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) 767 768 /** @brief Macro to configure the PLLSAI1 clock division factor P. 769 * 770 * @note This function must be used only when the PLLSAI1 is disabled. 771 * @note PLLSAI1 clock source is common with the main PLL (configured through 772 * __HAL_RCC_PLL_CONFIG() macro) 773 * 774 * @param __PLLSAI1P__ specifies the division factor for SAI clock. 775 * This parameter must be a number in the range (2 to 31). 776 * Use to set SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P 777 * 778 * @retval None 779 */ 780 #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \ 781 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) 782 783 /** @brief Macro to configure the PLLSAI1 clock division factor Q. 784 * 785 * @note This function must be used only when the PLLSAI1 is disabled. 786 * @note PLLSAI1 clock source is common with the main PLL (configured through 787 * __HAL_RCC_PLL_CONFIG() macro) 788 * 789 * @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock. 790 * This parameter must be in the range (2, 4, 6 or 8). 791 * Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q 792 * 793 * @retval None 794 */ 795 #define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \ 796 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) 797 798 /** @brief Macro to configure the PLLSAI1 clock division factor R. 799 * 800 * @note This function must be used only when the PLLSAI1 is disabled. 801 * @note PLLSAI1 clock source is common with the main PLL (configured through 802 * __HAL_RCC_PLL_CONFIG() macro) 803 * 804 * @param __PLLSAI1R__ specifies the division factor for ADC clock. 805 * This parameter must be in the range (2, 4, 6 or 8) 806 * Use to set ADC clock frequency = f(PLLSAI1) / PLLSAI1R 807 * 808 * @retval None 809 */ 810 #define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \ 811 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) 812 813 /** 814 * @brief Macros to enable or disable the PLLSAI1. 815 * @note The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes. 816 * @retval None 817 */ 818 819 #define __HAL_RCC_PLLSAI1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON) 820 821 #define __HAL_RCC_PLLSAI1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON) 822 823 /** 824 * @brief Macros to enable or disable each clock output (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1). 825 * @note Enabling and disabling those clocks can be done without the need to stop the PLL. 826 * This is mainly used to save Power. 827 * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output. 828 * This parameter can be one or a combination of the following values: 829 * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve 830 * high-quality audio performance on SAI interface in case. 831 * @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB FS (48 MHz), 832 * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz). 833 * @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral. 834 * @retval None 835 */ 836 837 #define __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) 838 839 #define __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) 840 841 /** 842 * @brief Macro to get clock output enable status (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1). 843 * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output. 844 * This parameter can be one of the following values: 845 * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve 846 * high-quality audio performance on SAI interface in case. 847 * @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB FS (48 MHz), 848 * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz). 849 * @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral. 850 * @retval SET / RESET 851 */ 852 #define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) 853 854 /** 855 * @brief Macro to configure the PLLSAI2 clock multiplication and division factors. 856 * 857 * @note This macro must be used only when the PLLSAIS is disabled. 858 * @note This macro preserves the PLLSAI2's output clocks enable state. 859 * 860 * @param __PLLSAI2SOURCE__ specifies the PLLSAI1 entry clock source. 861 * This parameter can be one of the following values: 862 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLLSAI2 clock entry 863 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLLSAI2 clock entry 864 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLLSAI2 clock entry 865 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLLSAI2 clock entry 866 * 867 * @param __PLLSAI2M__ specifies the division factor of PLLSAI2 input clock. 868 * This parameter must be a number between Min_Data = 1 and Max_Data = 16. 869 * 870 * @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock. 871 * This parameter must be a number between Min_Data = 8 and Max_Data = 86. 872 * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO 873 * output frequency is between 64 and 344 MHz. 874 * 875 * @param __PLLSAI2P__ specifies the division factor for SAI clock. 876 * This parameter must be a number between Min_Data = 2 and Max_Data = 31. 877 * SAI2 clock frequency = f(PLLSAI2) / PLLSAI2P 878 * 879 * @retval None 880 */ 881 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2SOURCE__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__) \ 882 MODIFY_REG(RCC->PLLSAI2CFGR, \ 883 (RCC_PLLSAI2CFGR_PLLSAI2SRC | RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | \ 884 RCC_PLLSAI2CFGR_PLLSAI2P | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \ 885 ((__PLLSAI2SOURCE__) | \ 886 (((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) | \ 887 ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ 888 ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))) 889 890 /** 891 * @brief Macro to configure the PLLSAI2 clock multiplication factor N. 892 * 893 * @note This function must be used only when the PLLSAI2 is disabled. 894 * @note PLLSAI2 clock source is common with the main PLL (configured through 895 * __HAL_RCC_PLL_CONFIG() macro) 896 * 897 * @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock. 898 * This parameter must be a number between 8 and 86. 899 * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO 900 * output frequency is between 64 and 344 MHz. 901 * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI2N 902 * 903 * @retval None 904 */ 905 #define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \ 906 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) 907 908 /** @brief Macro to configure the PLLSAI2 input clock division factor M. 909 * 910 * @note This function must be used only when the PLLSAI2 is disabled. 911 * @note PLLSAI2 clock source is common with the main PLL (configured through 912 * __HAL_RCC_PLL_CONFIG() macro) 913 * 914 * @param __PLLSAI2M__ specifies the division factor for PLLSAI2 clock. 915 * This parameter must be a number between Min_Data = 1 and Max_Data = 16. 916 * 917 * @retval None 918 */ 919 920 #define __HAL_RCC_PLLSAI2_DIVM_CONFIG(__PLLSAI2M__) \ 921 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M, ((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) 922 923 /** @brief Macro to configure the PLLSAI2 clock division factor P. 924 * 925 * @note This function must be used only when the PLLSAI2 is disabled. 926 * @note PLLSAI2 clock source is common with the main PLL (configured through 927 * __HAL_RCC_PLL_CONFIG() macro) 928 * 929 * @param __PLLSAI2P__ specifies the division factor. 930 * This parameter must be a number in the range (7 or 17). 931 * Use to set SAI2 clock frequency = f(PLLSAI2) / __PLLSAI2P__ 932 * 933 * @retval None 934 */ 935 #define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \ 936 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) 937 938 /** 939 * @brief Macros to enable or disable the PLLSAI2. 940 * @note The PLLSAI2 is disabled by hardware when entering STOP and STANDBY modes. 941 * @retval None 942 */ 943 944 #define __HAL_RCC_PLLSAI2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON) 945 946 #define __HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON) 947 948 /** 949 * @brief Macros to enable or disable each clock output (PLLSAI2_SAI2). 950 * @note Enabling and disabling those clocks can be done without the need to stop the PLL. 951 * This is mainly used to save Power. 952 * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output. 953 * This parameter can be one or a combination of the following values: 954 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve 955 * high-quality audio performance on SAI interface in case. 956 * @retval None 957 */ 958 959 #define __HAL_RCC_PLLSAI2CLKOUT_ENABLE(__PLLSAI2_CLOCKOUT__) SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) 960 961 #define __HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) 962 963 /** 964 * @brief Macro to get clock output enable status (PLLSAI2_SAI2). 965 * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output. 966 * This parameter can be one of the following values: 967 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve 968 * high-quality audio performance on SAI interface in case. 969 * @retval SET / RESET 970 */ 971 #define __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__) READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) 972 973 /** 974 * @brief Macro to configure the SAI1 clock source. 975 * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived 976 * from the PLLSAI1, system PLL or external clock (through a dedicated pin). 977 * This parameter can be one of the following values: 978 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK) 979 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) 980 * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK) 981 * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) 982 * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI16 983 * 984 * @note HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLLSAI2. 985 * 986 * @retval None 987 */ 988 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ 989 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__)) 990 991 /** @brief Macro to get the SAI1 clock source. 992 * @retval The clock source can be one of the following values: 993 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK) 994 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) 995 * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK) 996 * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) 997 * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI16 998 * 999 * @note Despite returned values RCC_SAI1CLKSOURCE_PLLSAI1 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1 1000 * clock source when PLLs are disabled for devices without PLLSAI2. 1001 * 1002 */ 1003 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL))) 1004 1005 /** 1006 * @brief Macro to configure the SAI2 clock source. 1007 * @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. This clock is derived 1008 * from the PLLSAI2, system PLL or external clock (through a dedicated pin). 1009 * This parameter can be one of the following values: 1010 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK) 1011 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK) 1012 * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK) 1013 * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK) 1014 * @arg @ref RCC_SAI2CLKSOURCE_HSI SAI2 clock = HSI16 1015 * 1016 * @retval None 1017 */ 1018 #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ 1019 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__)) 1020 1021 /** @brief Macro to get the SAI2 clock source. 1022 * @retval The clock source can be one of the following values: 1023 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK) 1024 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK) 1025 * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK) 1026 * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK) 1027 * @arg @ref RCC_SAI2CLKSOURCE_HSI SAI2 clock = HSI16 1028 */ 1029 #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL))) 1030 1031 /** @brief Macro to configure the I2C1 clock (I2C1CLK). 1032 * 1033 * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. 1034 * This parameter can be one of the following values: 1035 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 1036 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 1037 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 1038 * @retval None 1039 */ 1040 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ 1041 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) 1042 1043 /** @brief Macro to get the I2C1 clock source. 1044 * @retval The clock source can be one of the following values: 1045 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 1046 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 1047 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 1048 */ 1049 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_I2C1SEL))) 1050 1051 /** @brief Macro to configure the I2C2 clock (I2C2CLK). 1052 * 1053 * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. 1054 * This parameter can be one of the following values: 1055 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock 1056 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 1057 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock 1058 * @retval None 1059 */ 1060 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ 1061 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) 1062 1063 /** @brief Macro to get the I2C2 clock source. 1064 * @retval The clock source can be one of the following values: 1065 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock 1066 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 1067 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock 1068 */ 1069 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_I2C2SEL))) 1070 1071 /** @brief Macro to configure the I2C3 clock (I2C3CLK). 1072 * 1073 * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. 1074 * This parameter can be one of the following values: 1075 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock 1076 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 1077 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock 1078 * @retval None 1079 */ 1080 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ 1081 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) 1082 1083 /** @brief Macro to get the I2C3 clock source. 1084 * @retval The clock source can be one of the following values: 1085 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock 1086 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 1087 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock 1088 */ 1089 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_I2C3SEL))) 1090 1091 /** @brief Macro to configure the I2C4 clock (I2C4CLK). 1092 * 1093 * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. 1094 * This parameter can be one of the following values: 1095 * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock 1096 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock 1097 * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock 1098 * @retval None 1099 */ 1100 #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ 1101 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__)) 1102 1103 /** @brief Macro to get the I2C4 clock source. 1104 * @retval The clock source can be one of the following values: 1105 * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock 1106 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock 1107 * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock 1108 */ 1109 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL))) 1110 1111 1112 /** @brief Macro to configure the USART1 clock (USART1CLK). 1113 * 1114 * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. 1115 * This parameter can be one of the following values: 1116 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 1117 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 1118 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 1119 * @arg @ref RCC_USART1CLKSOURCE_LSE SE selected as USART1 clock 1120 * @retval None 1121 */ 1122 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ 1123 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) 1124 1125 /** @brief Macro to get the USART1 clock source. 1126 * @retval The clock source can be one of the following values: 1127 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 1128 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 1129 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 1130 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 1131 */ 1132 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART1SEL))) 1133 1134 /** @brief Macro to configure the USART2 clock (USART2CLK). 1135 * 1136 * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. 1137 * This parameter can be one of the following values: 1138 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 1139 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 1140 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 1141 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 1142 * @retval None 1143 */ 1144 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ 1145 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) 1146 1147 /** @brief Macro to get the USART2 clock source. 1148 * @retval The clock source can be one of the following values: 1149 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 1150 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 1151 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 1152 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 1153 */ 1154 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART2SEL))) 1155 1156 /** @brief Macro to configure the USART3 clock (USART3CLK). 1157 * 1158 * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. 1159 * This parameter can be one of the following values: 1160 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock 1161 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 1162 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock 1163 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 1164 * @retval None 1165 */ 1166 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ 1167 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) 1168 1169 /** @brief Macro to get the USART3 clock source. 1170 * @retval The clock source can be one of the following values: 1171 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock 1172 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 1173 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock 1174 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 1175 */ 1176 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART3SEL))) 1177 1178 /** @brief Macro to configure the UART4 clock (UART4CLK). 1179 * 1180 * @param __UART4_CLKSOURCE__ specifies the UART4 clock source. 1181 * This parameter can be one of the following values: 1182 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock 1183 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock 1184 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock 1185 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock 1186 * @retval None 1187 */ 1188 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ 1189 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__)) 1190 1191 /** @brief Macro to get the UART4 clock source. 1192 * @retval The clock source can be one of the following values: 1193 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock 1194 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock 1195 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock 1196 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock 1197 */ 1198 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART4SEL))) 1199 1200 /** @brief Macro to configure the UART5 clock (UART5CLK). 1201 * 1202 * @param __UART5_CLKSOURCE__ specifies the UART5 clock source. 1203 * This parameter can be one of the following values: 1204 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock 1205 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock 1206 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock 1207 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock 1208 * @retval None 1209 */ 1210 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ 1211 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__)) 1212 1213 /** @brief Macro to get the UART5 clock source. 1214 * @retval The clock source can be one of the following values: 1215 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock 1216 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock 1217 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock 1218 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock 1219 */ 1220 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART5SEL))) 1221 1222 /** @brief Macro to configure the LPUART1 clock (LPUART1CLK). 1223 * 1224 * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. 1225 * This parameter can be one of the following values: 1226 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 1227 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 1228 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 1229 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 1230 * @retval None 1231 */ 1232 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ 1233 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__)) 1234 1235 /** @brief Macro to get the LPUART1 clock source. 1236 * @retval The clock source can be one of the following values: 1237 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 1238 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 1239 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 1240 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 1241 */ 1242 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_LPUART1SEL))) 1243 1244 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). 1245 * 1246 * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. 1247 * This parameter can be one of the following values: 1248 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock 1249 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI LSI selected as LPTIM1 clock 1250 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI HSI selected as LPTIM1 clock 1251 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 1252 * @retval None 1253 */ 1254 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ 1255 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) 1256 1257 /** @brief Macro to get the LPTIM1 clock source. 1258 * @retval The clock source can be one of the following values: 1259 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock 1260 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI LSI selected as LPTIM1 clock 1261 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI HSI selected as LPTIM1 clock 1262 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 1263 */ 1264 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_LPTIM1SEL))) 1265 1266 /** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). 1267 * 1268 * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source. 1269 * This parameter can be one of the following values: 1270 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock 1271 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI LSI selected as LPTIM2 clock 1272 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI HSI selected as LPTIM2 clock 1273 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock 1274 * @retval None 1275 */ 1276 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ 1277 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__)) 1278 1279 /** @brief Macro to get the LPTIM2 clock source. 1280 * @retval The clock source can be one of the following values: 1281 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock 1282 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock 1283 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI HSI selected as LPTIM2 clock 1284 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock 1285 */ 1286 #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_LPTIM2SEL))) 1287 1288 /** @brief Macro to configure the LPTIM3 clock (LPTIM3CLK). 1289 * 1290 * @param __LPTIM3_CLKSOURCE__ specifies the LPTIM3 clock source. 1291 * This parameter can be one of the following values: 1292 * @arg @ref RCC_LPTIM3CLKSOURCE_PCLK1 PCLK1 selected as LPTIM3 clock 1293 * @arg @ref RCC_LPTIM3CLKSOURCE_LSI LSI selected as LPTIM3 clock 1294 * @arg @ref RCC_LPTIM3CLKSOURCE_HSI HSI selected as LPTIM3 clock 1295 * @arg @ref RCC_LPTIM3CLKSOURCE_LSE LSE selected as LPTIM3 clock 1296 * @retval None 1297 */ 1298 #define __HAL_RCC_LPTIM3_CONFIG(__LPTIM3_CLKSOURCE__) \ 1299 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPTIM3SEL, (uint32_t)(__LPTIM3_CLKSOURCE__)) 1300 1301 /** @brief Macro to get the LPTIM3 clock source. 1302 * @retval The clock source can be one of the following values: 1303 * @arg @ref RCC_LPTIM3CLKSOURCE_PCLK1 PCLK1 selected as LPTIM3 clock 1304 * @arg @ref RCC_LPTIM3CLKSOURCE_LSI LSI selected as LPTIM3 clock 1305 * @arg @ref RCC_LPTIM3CLKSOURCE_HSI HSI selected as LPTIM3 clock 1306 * @arg @ref RCC_LPTIM3CLKSOURCE_LSE LSE selected as LPTIM3 clock 1307 */ 1308 #define __HAL_RCC_GET_LPTIM3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_LPTIM3SEL))) 1309 1310 /** @brief Macro to configure the FDCAN kernel clock (FDCANCLK). 1311 * 1312 * @param __FDCAN_CLKSOURCE__ specifies the FDCAN kernel clock source. 1313 * This parameter can be one of the following values: 1314 * @arg @ref RCC_FDCANCLKSOURCE_HSE HSE selected as FDCAN kernel clock 1315 * @arg @ref RCC_FDCANCLKSOURCE_PLL PLL Clock selected as FDCAN kernel clock 1316 * @arg @ref RCC_FDCANCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as FDCAN kernel clock 1317 * @retval None 1318 */ 1319 #define __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__) \ 1320 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__)) 1321 1322 /** @brief Macro to get the FDCAN clock source. 1323 * @retval The clock source can be one of the following values: 1324 * @arg @ref RCC_FDCANCLKSOURCE_HSE HSE selected as FDCAN kernel clock 1325 * @arg @ref RCC_FDCANCLKSOURCE_PLL PLL Clock selected as FDCAN kernel clock 1326 * @arg @ref RCC_FDCANCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as FDCAN kernel clock 1327 */ 1328 #define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_FDCANSEL))) 1329 1330 /** @brief Macro to configure the SDMMC1 clock. 1331 * 1332 * @param __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source. 1333 * This parameter can be one of the following values: 1334 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock via internal multiplexer 1335 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock via internal multiplexer 1336 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" Clock selected as SDMMC1 clock via internal multiplexer 1337 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock via internal multiplexer 1338 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLP PLL "P" Clock selected as SDMMC1 clock 1339 * @retval None 1340 */ 1341 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ 1342 do \ 1343 { \ 1344 if((__SDMMC1_CLKSOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) \ 1345 { \ 1346 SET_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \ 1347 } \ 1348 else \ 1349 { \ 1350 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL, (uint32_t)(__SDMMC1_CLKSOURCE__)); \ 1351 CLEAR_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \ 1352 } \ 1353 } while(0) 1354 1355 /** @brief Macro to get the SDMMC1 clock. 1356 * @retval The clock source can be one of the following values: 1357 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock via internal multiplexer 1358 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock via internal multiplexer 1359 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock via internal multiplexer 1360 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock via internal multiplexer 1361 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLP PLL "P" clock (PLLSAI3CLK) selected as SDMMC1 clock 1362 */ 1363 #define __HAL_RCC_GET_SDMMC1_SOURCE() \ 1364 ((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL) != 0U) ? RCC_SDMMC1CLKSOURCE_PLLP : ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL)))) 1365 1366 /** @brief Macro to configure the RNG clock. 1367 * 1368 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. 1369 * 1370 * @param __RNG_CLKSOURCE__ specifies the RNG clock source. 1371 * This parameter can be one of the following values: 1372 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock 1373 * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock 1374 * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as RNG clock 1375 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL Clock selected as RNG clock 1376 * @retval None 1377 */ 1378 #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ 1379 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL, (uint32_t)(__RNG_CLKSOURCE__)) 1380 1381 /** @brief Macro to get the RNG clock. 1382 * @retval The clock source can be one of the following values: 1383 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock 1384 * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock 1385 * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock 1386 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as RNG clock 1387 */ 1388 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL))) 1389 1390 #if defined(USB) 1391 1392 /** @brief Macro to configure the USB clock (USBCLK). 1393 * 1394 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. 1395 * 1396 * @param __USB_CLKSOURCE__ specifies the USB clock source. 1397 * This parameter can be one of the following values: 1398 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock 1399 * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock 1400 * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock 1401 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock 1402 * @retval None 1403 */ 1404 #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \ 1405 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL, (uint32_t)(__USB_CLKSOURCE__)) 1406 1407 /** @brief Macro to get the USB clock source. 1408 * @retval The clock source can be one of the following values: 1409 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock 1410 * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock 1411 * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock 1412 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock 1413 */ 1414 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL))) 1415 1416 #endif /* USB */ 1417 1418 /** @brief Macro to configure the ADC interface clock. 1419 * @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source. 1420 * This parameter can be one of the following values: 1421 * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock 1422 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock 1423 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock 1424 * @retval None 1425 */ 1426 #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \ 1427 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__)) 1428 1429 /** @brief Macro to get the ADC clock source. 1430 * @retval The clock source can be one of the following values: 1431 * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock 1432 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock 1433 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock 1434 */ 1435 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ADCSEL))) 1436 1437 /** @brief Macro to configure the DFSDM1 clock. 1438 * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. 1439 * This parameter can be one of the following values: 1440 * @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2 PCLK2 Clock selected as DFSDM1 clock 1441 * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock 1442 * @retval None 1443 */ 1444 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ 1445 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDMSEL, (uint32_t)(__DFSDM1_CLKSOURCE__)) 1446 1447 /** @brief Macro to get the DFSDM1 clock source. 1448 * @retval The clock source can be one of the following values: 1449 * @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2 PCLK2 Clock selected as DFSDM1 clock 1450 * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock 1451 */ 1452 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DFSDMSEL))) 1453 1454 /** @brief Macro to configure the DFSDM1 audio clock. 1455 * @param __DFSDM1AUDIO_CLKSOURCE__ specifies the DFSDM1 audio clock source. 1456 * This parameter can be one of the following values: 1457 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_SAI1 SAI1 clock selected as DFSDM1 audio clock 1458 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI HSI clock selected as DFSDM1 audio clock 1459 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI MSI clock selected as DFSDM1 audio clock 1460 * @retval None 1461 */ 1462 #define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \ 1463 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDMSEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__)) 1464 1465 /** @brief Macro to get the DFSDM1 audio clock source. 1466 * @retval The clock source can be one of the following values: 1467 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_SAI1 SAI1 clock selected as DFSDM1 audio clock 1468 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI HSI clock selected as DFSDM1 audio clock 1469 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI MSI clock selected as DFSDM1 audio clock 1470 */ 1471 #define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ADFSDMSEL))) 1472 1473 /** @brief Macro to configure the OctoSPI clock. 1474 * @param __OSPI_CLKSOURCE__ specifies the OctoSPI clock source. 1475 * This parameter can be one of the following values: 1476 * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock 1477 * @arg @ref RCC_OSPICLKSOURCE_MSI MSI clock selected as OctoSPI clock 1478 * @arg @ref RCC_OSPICLKSOURCE_PLL PLL Q divider clock selected as OctoSPI clock 1479 * @retval None 1480 */ 1481 #define __HAL_RCC_OSPI_CONFIG(__OSPI_CLKSOURCE__) \ 1482 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, (uint32_t)(__OSPI_CLKSOURCE__)) 1483 1484 /** @brief Macro to get the OctoSPI clock source. 1485 * @retval The clock source can be one of the following values: 1486 * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock 1487 * @arg @ref RCC_OSPICLKSOURCE_MSI MSI clock selected as OctoSPI clock 1488 * @arg @ref RCC_OSPICLKSOURCE_PLL PLL Q divider clock selected as OctoSPI clock 1489 */ 1490 #define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_OSPISEL))) 1491 1492 /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management 1493 * @brief macros to manage the specified RCC Flags and interrupts. 1494 * @{ 1495 */ 1496 1497 /** @brief Enable PLLSAI1RDY interrupt. 1498 * @retval None 1499 */ 1500 #define __HAL_RCC_PLLSAI1_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) 1501 1502 /** @brief Disable PLLSAI1RDY interrupt. 1503 * @retval None 1504 */ 1505 #define __HAL_RCC_PLLSAI1_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) 1506 1507 /** @brief Clear the PLLSAI1RDY interrupt pending bit. 1508 * @retval None 1509 */ 1510 #define __HAL_RCC_PLLSAI1_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI1RDYC) 1511 1512 /** @brief Check whether PLLSAI1RDY interrupt has occurred or not. 1513 * @retval TRUE or FALSE. 1514 */ 1515 #define __HAL_RCC_PLLSAI1_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF) 1516 1517 /** @brief Check whether the PLLSAI1RDY flag is set or not. 1518 * @retval TRUE or FALSE. 1519 */ 1520 #define __HAL_RCC_PLLSAI1_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY)) 1521 1522 /** @brief Enable PLLSAI2RDY interrupt. 1523 * @retval None 1524 */ 1525 #define __HAL_RCC_PLLSAI2_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) 1526 1527 /** @brief Disable PLLSAI2RDY interrupt. 1528 * @retval None 1529 */ 1530 #define __HAL_RCC_PLLSAI2_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) 1531 1532 /** @brief Clear the PLLSAI2RDY interrupt pending bit. 1533 * @retval None 1534 */ 1535 #define __HAL_RCC_PLLSAI2_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI2RDYC) 1536 1537 /** @brief Check whether the PLLSAI2RDY interrupt has occurred or not. 1538 * @retval TRUE or FALSE. 1539 */ 1540 #define __HAL_RCC_PLLSAI2_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF) 1541 1542 /** @brief Check whether the PLLSAI2RDY flag is set or not. 1543 * @retval TRUE or FALSE. 1544 */ 1545 #define __HAL_RCC_PLLSAI2_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY)) 1546 1547 1548 /** @defgroup RCCEx_Security_Extensions RCCEx Security Extensions 1549 * @{ 1550 */ 1551 /* Clock/System Security status */ 1552 #define __HAL_RCC_HSI_IS_SECURITY_ENABLED() (READ_BIT(RCC->SECSR, RCC_SECSR_HSISECF) != 0U) 1553 1554 #define __HAL_RCC_HSE_IS_SECURITY_ENABLED() (READ_BIT(RCC->SECSR, RCC_SECSR_HSESECF) != 0U) 1555 1556 #define __HAL_RCC_MSI_IS_SECURITY_ENABLED() (READ_BIT(RCC->SECSR, RCC_SECSR_MSISECF) != 0U) 1557 1558 #define __HAL_RCC_LSI_IS_SECURITY_ENABLED() (READ_BIT(RCC->SECSR, RCC_SECSR_LSISECF) != 0U) 1559 1560 #define __HAL_RCC_LSE_IS_SECURITY_ENABLED() (READ_BIT(RCC->SECSR, RCC_SECSR_LSESECF) != 0U) 1561 1562 #define __HAL_RCC_HSI48_IS_SECURITY_ENABLED() (READ_BIT(RCC->SECSR, RCC_SECSR_HSI48SECF) != 0U) 1563 1564 #define __HAL_RCC_SYSCLK_IS_SECURITY_ENABLED() (READ_BIT(RCC->SECSR, RCC_SECSR_CKSYSSECF) != 0U) 1565 1566 #define __HAL_RCC_PRESCALER_IS_SECURITY_ENABLED() (READ_BIT(RCC->SECSR, RCC_SECSR_PRESCSECF) != 0U) 1567 1568 #define __HAL_RCC_PLL_IS_SECURITY_ENABLED() (READ_BIT(RCC->SECSR, RCC_SECSR_PLLSECF) != 0U) 1569 1570 #define __HAL_RCC_PLLSAI1_IS_SECURITY_ENABLED() (READ_BIT(RCC->SECSR, RCC_SECSR_PLLSAI1SECF) != 0U) 1571 1572 #define __HAL_RCC_PLLSAI2_IS_SECURITY_ENABLED() (READ_BIT(RCC->SECSR, RCC_SECSR_PLLSAI2SECF) != 0U) 1573 1574 #define __HAL_RCC_CLK48_IS_SECURITY_ENABLED() (READ_BIT(RCC->SECSR, RCC_SECSR_SEL48SECF) != 0U) 1575 1576 #define __HAL_RCC_RMVF_IS_SECURITY_ENABLED() (READ_BIT(RCC->SECSR, RCC_SECSR_RMVFSECF) != 0U) 1577 1578 /* Peripheral Security status */ 1579 #define __HAL_RCC_DMA1_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB1SECSR, RCC_AHB1SECSR_DMA1SECF) != 0U) 1580 1581 #define __HAL_RCC_DMA2_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB1SECSR, RCC_AHB1SECSR_DMA2SECF) != 0U) 1582 1583 #define __HAL_RCC_DMAMUX1_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB1SECSR, RCC_AHB1SECSR_DMAMUX1SECF) != 0U) 1584 1585 #define __HAL_RCC_FLASH_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB1SECSR, RCC_AHB1SECSR_FLASHSECF) != 0U) 1586 1587 #define __HAL_RCC_SRAM1_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB1SECSR, RCC_AHB1SECSR_SRAM1SECF) != 0U) 1588 1589 #define __HAL_RCC_CRC_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB1SECSR, RCC_AHB1SECSR_CRCSECF) != 0U) 1590 1591 #define __HAL_RCC_TSC_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB1SECSR, RCC_AHB1SECSR_TSCSECF) != 0U) 1592 1593 #define __HAL_RCC_GTZC_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB1SECSR, RCC_AHB1SECSR_GTZCSECF) != 0U) 1594 1595 #define __HAL_RCC_ICACHE_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB1SECSR, RCC_AHB1SECSR_ICACHESECF) != 0U) 1596 1597 #define __HAL_RCC_GPIOA_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB2SECSR, RCC_AHB2SECSR_GPIOASECF) != 0U) 1598 1599 #define __HAL_RCC_GPIOB_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB2SECSR, RCC_AHB2SECSR_GPIOBSECF) != 0U) 1600 1601 #define __HAL_RCC_GPIOC_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB2SECSR, RCC_AHB2SECSR_GPIOCSECF) != 0U) 1602 1603 #define __HAL_RCC_GPIOD_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB2SECSR, RCC_AHB2SECSR_GPIODSECF) != 0U) 1604 1605 #define __HAL_RCC_GPIOE_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB2SECSR, RCC_AHB2SECSR_GPIOESECF) != 0U) 1606 1607 #define __HAL_RCC_GPIOF_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB2SECSR, RCC_AHB2SECSR_GPIOFSECF) != 0U) 1608 1609 #define __HAL_RCC_GPIOG_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB2SECSR, RCC_AHB2SECSR_GPIOGSECF) != 0U) 1610 1611 #define __HAL_RCC_GPIOH_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB2SECSR, RCC_AHB2SECSR_GPIOHSECF) != 0U) 1612 1613 #define __HAL_RCC_SRAM2_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB2SECSR, RCC_AHB2SECSR_SRAM2SECF) != 0U) 1614 1615 #define __HAL_RCC_ADC_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB2SECSR, RCC_AHB2SECSR_ADCSECF) != 0U) 1616 1617 #define __HAL_RCC_AES_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB2SECSR, RCC_AHB2SECSR_AESSECF) != 0U) 1618 1619 #define __HAL_RCC_HASH_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB2SECSR, RCC_AHB2SECSR_HASHSECF) != 0U) 1620 1621 #define __HAL_RCC_RNG_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB2SECSR, RCC_AHB2SECSR_RNGSECF) != 0U) 1622 1623 #define __HAL_RCC_PKA_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB2SECSR, RCC_AHB2SECSR_PKASECF) != 0U) 1624 1625 #define __HAL_RCC_OTFDEC1_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB2SECSR, RCC_AHB2SECSR_OTFDEC1SECF) != 0U) 1626 1627 #define __HAL_RCC_SDMMC1_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB2SECSR, RCC_AHB2SECSR_SDMMC1SECF) != 0U) 1628 1629 #define __HAL_RCC_FMC_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB3SECSR, RCC_AHB3SECSR_FMCSECF) != 0U) 1630 1631 #define __HAL_RCC_OSPI1_IS_SECURITY_ENABLED() (READ_BIT(RCC->AHB3SECSR, RCC_AHB3SECSR_OSPI1SECF) != 0U) 1632 1633 #define __HAL_RCC_TIM2_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_TIM2SECF) != 0U) 1634 1635 #define __HAL_RCC_TIM3_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_TIM3SECF) != 0U) 1636 1637 #define __HAL_RCC_TIM4_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_TIM4SECF) != 0U) 1638 1639 #define __HAL_RCC_TIM5_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_TIM5SECF) != 0U) 1640 1641 #define __HAL_RCC_TIM6_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_TIM6SECF) != 0U) 1642 1643 #define __HAL_RCC_TIM7_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_TIM7SECF) != 0U) 1644 1645 #define __HAL_RCC_RTCAPB_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_RTCAPBSECF) != 0U) 1646 1647 #define __HAL_RCC_WWDG_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_WWDGSECF) != 0U) 1648 1649 #define __HAL_RCC_SPI2_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_SPI2SECF) != 0U) 1650 1651 #define __HAL_RCC_SPI3_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_SPI3SECF) != 0U) 1652 1653 #define __HAL_RCC_USART2_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_USART2SECF) != 0U) 1654 1655 #define __HAL_RCC_USART3_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_USART3SECF) != 0U) 1656 1657 #define __HAL_RCC_UART4_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_UART4SECF) != 0U) 1658 1659 #define __HAL_RCC_UART5_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_UART5SECF) != 0U) 1660 1661 #define __HAL_RCC_I2C1_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_I2C1SECF) != 0U) 1662 1663 #define __HAL_RCC_I2C2_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_I2C2SECF) != 0U) 1664 1665 #define __HAL_RCC_I2C3_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_I2C3SECF) != 0U) 1666 1667 #define __HAL_RCC_CRS_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_CRSSECF) != 0U) 1668 1669 #define __HAL_RCC_PWR_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_PWRSECF) != 0U) 1670 1671 #define __HAL_RCC_DAC1_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_DAC1SECF) != 0U) 1672 1673 #define __HAL_RCC_OPAMP_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_OPAMPSECF) != 0U) 1674 1675 #define __HAL_RCC_LPTIM1_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR1, RCC_APB1SECSR1_LPTIM1SECF) != 0U) 1676 1677 #define __HAL_RCC_LPUART1_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR2, RCC_APB1SECSR2_LPUART1SECF) != 0U) 1678 1679 #define __HAL_RCC_I2C4_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR2, RCC_APB1SECSR2_I2C4SECF) != 0U) 1680 1681 #define __HAL_RCC_LPTIM2_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR2, RCC_APB1SECSR2_LPTIM2SECF) != 0U) 1682 1683 #define __HAL_RCC_LPTIM3_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR2, RCC_APB1SECSR2_LPTIM3SECF) != 0U) 1684 1685 #define __HAL_RCC_FDCAN1_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR2, RCC_APB1SECSR2_FDCAN1SECF) != 0U) 1686 1687 #if defined(USB) 1688 #define __HAL_RCC_USB_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR2, RCC_APB1SECSR2_USBFSSECF) != 0U) 1689 #endif /* USB */ 1690 1691 #define __HAL_RCC_UCPD1_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB1SECSR2, RCC_APB1SECSR2_UCPD1SECF) != 0U) 1692 1693 #define __HAL_RCC_SYSCFG_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB2SECSR, RCC_APB2SECSR_SYSCFGSECF) != 0U) 1694 1695 #define __HAL_RCC_TIM1_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB2SECSR, RCC_APB2SECSR_TIM1SECF) != 0U) 1696 1697 #define __HAL_RCC_SPI1_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB2SECSR, RCC_APB2SECSR_SPI1SECF) != 0U) 1698 1699 #define __HAL_RCC_TIM8_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB2SECSR, RCC_APB2SECSR_TIM8SECF) != 0U) 1700 1701 #define __HAL_RCC_USART1_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB2SECSR, RCC_APB2SECSR_USART1SECF) != 0U) 1702 1703 #define __HAL_RCC_TIM15_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB2SECSR, RCC_APB2SECSR_TIM15SECF) != 0U) 1704 1705 #define __HAL_RCC_TIM16_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB2SECSR, RCC_APB2SECSR_TIM16SECF) != 0U) 1706 1707 #define __HAL_RCC_TIM17_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB2SECSR, RCC_APB2SECSR_TIM17SECF) != 0U) 1708 1709 #define __HAL_RCC_SAI1_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB2SECSR, RCC_APB2SECSR_SAI1SECF) != 0U) 1710 1711 #define __HAL_RCC_SAI2_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB2SECSR, RCC_APB2SECSR_SAI2SECF) != 0U) 1712 1713 #define __HAL_RCC_DFSDM1_IS_SECURITY_ENABLED() (READ_BIT(RCC->APB2SECSR, RCC_APB2SECSR_DFSDM1SECF) != 0U) 1714 /** 1715 * @} 1716 */ 1717 1718 1719 #if defined(CRS) 1720 1721 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features 1722 * @{ 1723 */ 1724 1725 /** 1726 * @brief Enable the specified CRS interrupts. 1727 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. 1728 * This parameter can be any combination of the following values: 1729 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1730 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1731 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1732 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1733 * @retval None 1734 */ 1735 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) 1736 1737 /** 1738 * @brief Disable the specified CRS interrupts. 1739 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. 1740 * This parameter can be any combination of the following values: 1741 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1742 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1743 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1744 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1745 * @retval None 1746 */ 1747 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) 1748 1749 /** @brief Check whether the CRS interrupt has occurred or not. 1750 * @param __INTERRUPT__ specifies the CRS interrupt source to check. 1751 * This parameter can be one of the following values: 1752 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1753 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1754 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1755 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1756 * @retval The new state of __INTERRUPT__ (0 or 1). 1757 */ 1758 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? 1U : 0U) 1759 1760 /** @brief Clear the CRS interrupt pending bits 1761 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1762 * This parameter can be any combination of the following values: 1763 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1764 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1765 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1766 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1767 * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt 1768 * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt 1769 * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt 1770 */ 1771 /* CRS IT Error Mask */ 1772 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF\ 1773 | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) 1774 1775 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ 1776 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ 1777 { \ 1778 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ 1779 } \ 1780 else \ 1781 { \ 1782 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ 1783 } \ 1784 } while(0) 1785 1786 /** 1787 * @brief Check whether the specified CRS flag is set or not. 1788 * @param __FLAG__ specifies the flag to check. 1789 * This parameter can be one of the following values: 1790 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 1791 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 1792 * @arg @ref RCC_CRS_FLAG_ERR Error 1793 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 1794 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 1795 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 1796 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 1797 * @retval The new state of _FLAG_ (TRUE or FALSE). 1798 */ 1799 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) 1800 1801 /** 1802 * @brief Clear the CRS specified FLAG. 1803 * @param __FLAG__ specifies the flag to clear. 1804 * This parameter can be one of the following values: 1805 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 1806 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 1807 * @arg @ref RCC_CRS_FLAG_ERR Error 1808 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 1809 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 1810 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 1811 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 1812 * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR 1813 * @retval None 1814 */ 1815 1816 /* CRS Flag Error Mask */ 1817 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF\ 1818 | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) 1819 1820 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ 1821 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ 1822 { \ 1823 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ 1824 } \ 1825 else \ 1826 { \ 1827 WRITE_REG(CRS->ICR, (__FLAG__)); \ 1828 } \ 1829 } while(0) 1830 1831 /** 1832 * @brief Enable the oscillator clock for frequency error counter. 1833 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. 1834 * @retval None 1835 */ 1836 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) 1837 1838 /** 1839 * @brief Disable the oscillator clock for frequency error counter. 1840 * @retval None 1841 */ 1842 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) 1843 1844 /** 1845 * @brief Enable the automatic hardware adjustment of TRIM bits. 1846 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. 1847 * @retval None 1848 */ 1849 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 1850 1851 /** 1852 * @brief Enable or disable the automatic hardware adjustment of TRIM bits. 1853 * @retval None 1854 */ 1855 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 1856 1857 /** 1858 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies 1859 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency 1860 * of the synchronization source after prescaling. It is then decreased by one in order to 1861 * reach the expected synchronization on the zero value. The formula is the following: 1862 * RELOAD = (fTARGET / fSYNC) -1 1863 * @param __FTARGET__ Target frequency (value in Hz). 1864 * @param __FSYNC__ Synchronization signal frequency (value in Hz). 1865 * @retval None 1866 */ 1867 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) 1868 1869 /** 1870 * @} 1871 */ 1872 1873 #endif /* CRS */ 1874 1875 /** 1876 * @} 1877 */ 1878 1879 /* Exported functions --------------------------------------------------------*/ 1880 /** @addtogroup RCCEx_Exported_Functions 1881 * @{ 1882 */ 1883 1884 /** @addtogroup RCCEx_Exported_Functions_Group1 1885 * @{ 1886 */ 1887 1888 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 1889 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 1890 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 1891 1892 /** 1893 * @} 1894 */ 1895 1896 /** @addtogroup RCCEx_Exported_Functions_Group2 1897 * @{ 1898 */ 1899 1900 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init); 1901 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void); 1902 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init); 1903 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void); 1904 1905 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); 1906 void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange); 1907 void HAL_RCCEx_EnableLSECSS(void); 1908 void HAL_RCCEx_DisableLSECSS(void); 1909 void HAL_RCCEx_LSECSS_IRQHandler(void); 1910 void HAL_RCCEx_LSECSS_Callback(void); 1911 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); 1912 void HAL_RCCEx_DisableLSCO(void); 1913 void HAL_RCCEx_EnableMSIPLLMode(void); 1914 void HAL_RCCEx_DisableMSIPLLMode(void); 1915 1916 /** 1917 * @} 1918 */ 1919 1920 #if defined(CRS) 1921 1922 /** @addtogroup RCCEx_Exported_Functions_Group3 1923 * @{ 1924 */ 1925 1926 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); 1927 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); 1928 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); 1929 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); 1930 void HAL_RCCEx_CRS_IRQHandler(void); 1931 void HAL_RCCEx_CRS_SyncOkCallback(void); 1932 void HAL_RCCEx_CRS_SyncWarnCallback(void); 1933 void HAL_RCCEx_CRS_ExpectedSyncCallback(void); 1934 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); 1935 1936 /** 1937 * @} 1938 */ 1939 1940 #endif /* CRS */ 1941 1942 /** 1943 * @} 1944 */ 1945 1946 /* Private constants ---------------------------------------------------------*/ 1947 /** @addtogroup RCCEx_Private_Constants 1948 * @{ 1949 */ 1950 /* Define used for IS_RCC_* macros below */ 1951 #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 1952 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 | \ 1953 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 1954 RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ 1955 RCC_PERIPHCLK_LPTIM3 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ 1956 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \ 1957 RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | \ 1958 RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN) 1959 1960 /** 1961 * @} 1962 */ 1963 1964 /* Private macros ------------------------------------------------------------*/ 1965 /** @addtogroup RCCEx_Private_Macros 1966 * @{ 1967 */ 1968 1969 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ 1970 ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) 1971 1972 #define IS_RCC_PERIPHCLOCK(__SELECTION__) ((((__SELECTION__) & RCC_PERIPHCLOCK_ALL) != 0x00u) && \ 1973 (((__SELECTION__) & ~RCC_PERIPHCLOCK_ALL) == 0x00u)) 1974 1975 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ 1976 (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ 1977 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ 1978 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ 1979 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) 1980 1981 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ 1982 (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ 1983 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ 1984 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ 1985 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) 1986 1987 #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ 1988 (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ 1989 ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \ 1990 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \ 1991 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI)) 1992 1993 #define IS_RCC_UART4CLKSOURCE(__SOURCE__) \ 1994 (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \ 1995 ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \ 1996 ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \ 1997 ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI)) 1998 1999 #define IS_RCC_UART5CLKSOURCE(__SOURCE__) \ 2000 (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \ 2001 ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \ 2002 ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \ 2003 ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI)) 2004 2005 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ 2006 (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ 2007 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ 2008 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ 2009 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) 2010 2011 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ 2012 (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ 2013 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ 2014 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) 2015 2016 #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ 2017 (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ 2018 ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \ 2019 ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)) 2020 2021 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \ 2022 (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ 2023 ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ 2024 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) 2025 2026 #define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \ 2027 (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \ 2028 ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \ 2029 ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI)) 2030 2031 #define IS_RCC_SAI1CLK(__SOURCE__) \ 2032 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ 2033 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \ 2034 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ 2035 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \ 2036 ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI)) 2037 2038 #define IS_RCC_SAI2CLK(__SOURCE__) \ 2039 (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \ 2040 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \ 2041 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \ 2042 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \ 2043 ((__SOURCE__) == RCC_SAI2CLKSOURCE_HSI)) 2044 2045 #define IS_RCC_LPTIM1CLK(__SOURCE__) \ 2046 (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ 2047 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ 2048 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ 2049 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) 2050 2051 #define IS_RCC_LPTIM2CLK(__SOURCE__) \ 2052 (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \ 2053 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ 2054 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \ 2055 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)) 2056 2057 #define IS_RCC_LPTIM3CLK(__SOURCE__) \ 2058 (((__SOURCE__) == RCC_LPTIM3CLKSOURCE_PCLK1) || \ 2059 ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSI) || \ 2060 ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_HSI) || \ 2061 ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSE)) 2062 2063 #define IS_RCC_FDCANCLK(__SOURCE__) \ 2064 (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \ 2065 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) || \ 2066 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLLSAI1)) 2067 2068 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ 2069 (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \ 2070 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \ 2071 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \ 2072 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI) || \ 2073 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP)) 2074 2075 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ 2076 (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ 2077 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \ 2078 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ 2079 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI)) 2080 2081 #if defined(USB) 2082 2083 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ 2084 (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ 2085 ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \ 2086 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ 2087 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) 2088 2089 #endif /* USB */ 2090 2091 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ 2092 (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ 2093 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \ 2094 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) 2095 2096 #define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) \ 2097 (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \ 2098 ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK)) 2099 2100 #define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) \ 2101 (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \ 2102 ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_HSI) || \ 2103 ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_MSI)) 2104 2105 #define IS_RCC_OSPICLKSOURCE(__SOURCE__) \ 2106 (((__SOURCE__) == RCC_OSPICLKSOURCE_SYSCLK) || \ 2107 ((__SOURCE__) == RCC_OSPICLKSOURCE_MSI) || \ 2108 ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL)) 2109 2110 #define IS_RCC_PLLSAI1SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__) 2111 2112 #define IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) 2113 2114 #define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) 2115 2116 #define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) 2117 2118 #define IS_RCC_PLLSAI1Q_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 2119 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 2120 2121 #define IS_RCC_PLLSAI1R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 2122 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 2123 2124 #define IS_RCC_PLLSAI2SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__) 2125 2126 #define IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) 2127 2128 #define IS_RCC_PLLSAI2N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) 2129 2130 #define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) 2131 2132 #if defined(CRS) 2133 2134 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ 2135 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ 2136 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) 2137 2138 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ 2139 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ 2140 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ 2141 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) 2142 2143 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ 2144 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) 2145 2146 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) 2147 2148 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) 2149 2150 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x7FU)) 2151 2152 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ 2153 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) 2154 2155 #endif /* CRS */ 2156 2157 /** 2158 * @} 2159 */ 2160 2161 /** 2162 * @} 2163 */ 2164 2165 /** 2166 * @} 2167 */ 2168 2169 /** 2170 * @} 2171 */ 2172 2173 #ifdef __cplusplus 2174 } 2175 #endif 2176 2177 #endif /* STM32L5xx_HAL_RCC_EX_H */ 2178 2179
