1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_ll_sdmmc.h 4 * @author MCD Application Team 5 * @brief Header file of SDMMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32L4xx_LL_SDMMC_H 21 #define STM32L4xx_LL_SDMMC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 #if defined(SDMMC1) 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include "stm32l4xx_hal_def.h" 31 32 /** @addtogroup STM32L4xx_Driver 33 * @{ 34 */ 35 36 /** @addtogroup SDMMC_LL 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief SDMMC Configuration Structure definition 47 */ 48 typedef struct 49 { 50 uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. 51 This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ 52 53 #if !defined(STM32L4P5xx) && !defined(STM32L4Q5xx) && !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) 54 uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is 55 enabled or disabled. 56 This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */ 57 #endif /* !STM32L4P5xx && !STM32L4Q5xx && !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ 58 59 uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or 60 disabled when the bus is idle. 61 This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */ 62 63 uint32_t BusWide; /*!< Specifies the SDMMC bus width. 64 This parameter can be a value of @ref SDMMC_LL_Bus_Wide */ 65 66 uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled. 67 This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */ 68 69 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller. 70 This parameter can be a value between Min_Data = 0 and Max_Data = 1023 */ 71 72 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 73 uint32_t Transceiver; /*!< Specifies whether external Transceiver is enabled or disabled. 74 This parameter can be a value of @ref SDMMC_LL_Transceiver */ 75 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 76 77 }SDMMC_InitTypeDef; 78 79 80 /** 81 * @brief SDMMC Command Control structure 82 */ 83 typedef struct 84 { 85 uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent 86 to a card as part of a command message. If a command 87 contains an argument, it must be loaded into this register 88 before writing the command to the command register. */ 89 90 uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and 91 Max_Data = 64 */ 92 93 uint32_t Response; /*!< Specifies the SDMMC response type. 94 This parameter can be a value of @ref SDMMC_LL_Response_Type */ 95 96 uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is 97 enabled or disabled. 98 This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */ 99 100 uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM) 101 is enabled or disabled. 102 This parameter can be a value of @ref SDMMC_LL_CPSM_State */ 103 }SDMMC_CmdInitTypeDef; 104 105 106 /** 107 * @brief SDMMC Data Control structure 108 */ 109 typedef struct 110 { 111 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ 112 113 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ 114 115 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. 116 This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */ 117 118 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer 119 is a read or write. 120 This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */ 121 122 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. 123 This parameter can be a value of @ref SDMMC_LL_Transfer_Type */ 124 125 uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM) 126 is enabled or disabled. 127 This parameter can be a value of @ref SDMMC_LL_DPSM_State */ 128 }SDMMC_DataInitTypeDef; 129 130 /** 131 * @} 132 */ 133 134 /* Exported constants --------------------------------------------------------*/ 135 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants 136 * @{ 137 */ 138 #define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 139 #define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /*!< Command response received (but CRC check failed) */ 140 #define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /*!< Data block sent/received (CRC check failed) */ 141 #define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /*!< Command response timeout */ 142 #define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /*!< Data timeout */ 143 #define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */ 144 #define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */ 145 #define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */ 146 #define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the 147 number of transferred bytes does not match the block length */ 148 #define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */ 149 #define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */ 150 #define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */ 151 #define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock 152 command or if there was an attempt to access a locked card */ 153 #define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */ 154 #define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */ 155 #define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */ 156 #define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /*!< Internal card controller error */ 157 #define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /*!< General or unknown error */ 158 #define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /*!< The card could not sustain data reading in stream rmode */ 159 #define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /*!< The card could not sustain data programming in stream mode */ 160 #define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */ 161 #define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */ 162 #define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */ 163 #define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out 164 of erase sequence command was received */ 165 #define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */ 166 #define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */ 167 #define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /*!< Error when addressed block is out of range */ 168 #define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /*!< Error when command request is not applicable */ 169 #define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /*!< the used parameter is not valid */ 170 #define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /*!< Error when feature is not insupported */ 171 #define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /*!< Error when transfer process is busy */ 172 #define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */ 173 #define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */ 174 175 /** 176 * @brief SDMMC Commands Index 177 */ 178 #define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */ 179 #define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */ 180 #define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ 181 #define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */ 182 #define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */ 183 #define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its 184 operating condition register (OCR) content in the response on the CMD line. */ 185 #define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ 186 #define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */ 187 #define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information 188 and asks the card whether card supports voltage. */ 189 #define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ 190 #define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */ 191 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 192 #define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U) /*!< SD card Voltage switch to 1.8V mode. */ 193 #else 194 #define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11U) /*!< SD card doesn't support it. */ 195 #endif 196 #define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */ 197 #define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */ 198 #define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */ 199 #define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */ 200 #define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands 201 (read, write, lock). Default block length is fixed to 512 Bytes. Not effective 202 for SDHS and SDXC. */ 203 #define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 204 fixed 512 bytes in case of SDHC and SDXC. */ 205 #define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by 206 STOP_TRANSMISSION command. */ 207 #define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ 208 #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */ 209 #define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */ 210 #define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 211 fixed 512 bytes in case of SDHC and SDXC. */ 212 #define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ 213 #define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */ 214 #define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */ 215 #define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */ 216 #define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */ 217 #define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */ 218 #define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */ 219 #define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */ 220 #define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command 221 system set by switch function command (CMD6). */ 222 #define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. 223 Reserved for each command system set by switch function command (CMD6). */ 224 #define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */ 225 #define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */ 226 #define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */ 227 #define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by 228 the SET_BLOCK_LEN command. */ 229 #define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather 230 than a standard command. */ 231 #define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card 232 for general purpose/application specific commands. */ 233 #define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */ 234 235 /** 236 * @brief Following commands are SD Card Specific commands. 237 * SDMMC_APP_CMD should be sent before sending these commands. 238 */ 239 #define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus 240 widths are given in SCR register. */ 241 #define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */ 242 #define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 243 32bit+CRC data block. */ 244 #define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to 245 send its operating condition register (OCR) content in the response on the CMD line. */ 246 #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ 247 #define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */ 248 #define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */ 249 #define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */ 250 251 /** 252 * @brief Following commands are MMC Specific commands. 253 */ 254 #define SDMMC_CMD_MMC_SLEEP_AWAKE ((uint8_t)5U) /*!< Toggle the device between Sleep state and Standby state. */ 255 256 /** 257 * @brief Following commands are SD Card Specific security commands. 258 * SDMMC_CMD_APP_CMD should be sent before sending these commands. 259 */ 260 #define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U) 261 #define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U) 262 #define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U) 263 #define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U) 264 #define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U) 265 #define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U) 266 #define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U) 267 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U) 268 #define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U) 269 #define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U) 270 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U) 271 272 /** 273 * @brief Masks for errors Card Status R1 (OCR Register) 274 */ 275 #define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U) 276 #define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U) 277 #define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U) 278 #define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U) 279 #define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U) 280 #define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U) 281 #define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U) 282 #define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U) 283 #define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U) 284 #define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U) 285 #define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U) 286 #define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U) 287 #define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U) 288 #define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U) 289 #define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U) 290 #define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U) 291 #define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U) 292 #define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U) 293 #define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U) 294 #define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U) 295 296 /** 297 * @brief Masks for R6 Response 298 */ 299 #define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U) 300 #define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U) 301 #define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U) 302 303 #define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U) 304 #define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U) 305 #define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U) 306 #define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU) 307 #define SD_SWITCH_1_8V_CAPACITY ((uint32_t)0x01000000U) 308 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 309 #define SDMMC_DDR50_SWITCH_PATTERN ((uint32_t)0x80FFFF04U) 310 #define SDMMC_SDR104_SWITCH_PATTERN ((uint32_t)0x80FF1F03U) 311 #define SDMMC_SDR50_SWITCH_PATTERN ((uint32_t)0x80FF1F02U) 312 #define SDMMC_SDR25_SWITCH_PATTERN ((uint32_t)0x80FFFF01U) 313 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 314 315 #define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU) 316 317 #define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU) 318 319 #define SDMMC_ALLZERO ((uint32_t)0x00000000U) 320 321 #define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U) 322 #define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U) 323 #define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U) 324 325 #define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) 326 327 #define SDMMC_0TO7BITS ((uint32_t)0x000000FFU) 328 #define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U) 329 #define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U) 330 #define SDMMC_24TO31BITS ((uint32_t)0xFF000000U) 331 #define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU) 332 333 #define SDMMC_HALFFIFO ((uint32_t)0x00000008U) 334 #define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U) 335 336 /** 337 * @brief Command Class supported 338 */ 339 #define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U) 340 341 #define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */ 342 #define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */ 343 #define SDMMC_STOPTRANSFERTIMEOUT ((uint32_t)100000000U) /* Timeout for STOP TRANSMISSION command */ 344 345 /** @defgroup SDMMC_LL_Clock_Edge Clock Edge 346 * @{ 347 */ 348 #define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000U) 349 #define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE 350 351 #define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \ 352 ((EDGE) == SDMMC_CLOCK_EDGE_FALLING)) 353 /** 354 * @} 355 */ 356 357 #if !defined(STM32L4P5xx) && !defined(STM32L4Q5xx) && !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) 358 /** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass 359 * @{ 360 */ 361 #define SDMMC_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000U) 362 #define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS 363 364 #define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \ 365 ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE)) 366 /** 367 * @} 368 */ 369 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 370 371 /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving 372 * @{ 373 */ 374 #define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U) 375 #define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV 376 377 #define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \ 378 ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE)) 379 /** 380 * @} 381 */ 382 383 /** @defgroup SDMMC_LL_Bus_Wide Bus Width 384 * @{ 385 */ 386 #define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000U) 387 #define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0 388 #define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1 389 390 #define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \ 391 ((WIDE) == SDMMC_BUS_WIDE_4B) || \ 392 ((WIDE) == SDMMC_BUS_WIDE_8B)) 393 /** 394 * @} 395 */ 396 397 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 398 /** @defgroup SDMMC_LL_Speed_Mode 399 * @{ 400 */ 401 #define SDMMC_SPEED_MODE_AUTO ((uint32_t)0x00000000U) 402 #define SDMMC_SPEED_MODE_DEFAULT ((uint32_t)0x00000001U) 403 #define SDMMC_SPEED_MODE_HIGH ((uint32_t)0x00000002U) 404 #define SDMMC_SPEED_MODE_ULTRA ((uint32_t)0x00000003U) 405 #define SDMMC_SPEED_MODE_DDR ((uint32_t)0x00000004U) 406 407 #define IS_SDMMC_SPEED_MODE(MODE) (((MODE) == SDMMC_SPEED_MODE_AUTO) || \ 408 ((MODE) == SDMMC_SPEED_MODE_DEFAULT) || \ 409 ((MODE) == SDMMC_SPEED_MODE_HIGH) || \ 410 ((MODE) == SDMMC_SPEED_MODE_ULTRA) || \ 411 ((MODE) == SDMMC_SPEED_MODE_DDR)) 412 413 /** 414 * @} 415 */ 416 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 417 418 /** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control 419 * @{ 420 */ 421 #define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U) 422 #define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN 423 424 #define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \ 425 ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE)) 426 /** 427 * @} 428 */ 429 430 /** @defgroup SDMMC_LL_Clock_Division Clock Division 431 * @{ 432 */ 433 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 434 /* SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV] */ 435 #define IS_SDMMC_CLKDIV(DIV) ((DIV) < 0x400U) 436 #else 437 #define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFFU) 438 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 439 /** 440 * @} 441 */ 442 443 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 444 /** @defgroup SDMMC_LL_Transceiver Transceiver 445 * @{ 446 */ 447 #define SDMMC_TRANSCEIVER_DISABLE ((uint32_t)0x00000000U) 448 #define SDMMC_TRANSCEIVER_ENABLE ((uint32_t)0x00000001U) 449 450 #define IS_SDMMC_TRANSCEIVER(MODE) (((MODE) == SDMMC_TRANSCEIVER_DISABLE) || \ 451 ((MODE) == SDMMC_TRANSCEIVER_ENABLE)) 452 /** 453 * @} 454 */ 455 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 456 457 /** @defgroup SDMMC_LL_Command_Index Command Index 458 * @{ 459 */ 460 #define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40U) 461 /** 462 * @} 463 */ 464 465 /** @defgroup SDMMC_LL_Response_Type Response Type 466 * @{ 467 */ 468 #define SDMMC_RESPONSE_NO ((uint32_t)0x00000000U) 469 #define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0 470 #define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP 471 472 #define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \ 473 ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \ 474 ((RESPONSE) == SDMMC_RESPONSE_LONG)) 475 /** 476 * @} 477 */ 478 479 /** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt 480 * @{ 481 */ 482 #define SDMMC_WAIT_NO ((uint32_t)0x00000000U) 483 #define SDMMC_WAIT_IT SDMMC_CMD_WAITINT 484 #define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND 485 486 #define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \ 487 ((WAIT) == SDMMC_WAIT_IT) || \ 488 ((WAIT) == SDMMC_WAIT_PEND)) 489 /** 490 * @} 491 */ 492 493 /** @defgroup SDMMC_LL_CPSM_State CPSM State 494 * @{ 495 */ 496 #define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000U) 497 #define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN 498 499 #define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \ 500 ((CPSM) == SDMMC_CPSM_ENABLE)) 501 /** 502 * @} 503 */ 504 505 /** @defgroup SDMMC_LL_Response_Registers Response Register 506 * @{ 507 */ 508 #define SDMMC_RESP1 ((uint32_t)0x00000000U) 509 #define SDMMC_RESP2 ((uint32_t)0x00000004U) 510 #define SDMMC_RESP3 ((uint32_t)0x00000008U) 511 #define SDMMC_RESP4 ((uint32_t)0x0000000CU) 512 513 #define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \ 514 ((RESP) == SDMMC_RESP2) || \ 515 ((RESP) == SDMMC_RESP3) || \ 516 ((RESP) == SDMMC_RESP4)) 517 518 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 519 /** @defgroup SDMMC_Internal_DMA_Mode SDMMC Internal DMA Mode 520 * @{ 521 */ 522 #define SDMMC_DISABLE_IDMA ((uint32_t)0x00000000) 523 #define SDMMC_ENABLE_IDMA_SINGLE_BUFF (SDMMC_IDMA_IDMAEN) 524 #define SDMMC_ENABLE_IDMA_DOUBLE_BUFF0 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE) 525 #define SDMMC_ENABLE_IDMA_DOUBLE_BUFF1 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE | SDMMC_IDMA_IDMABACT) 526 527 /** 528 * @} 529 */ 530 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 531 532 /** @defgroup SDMMC_LL_Data_Length Data Length 533 * @{ 534 */ 535 #define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU) 536 /** 537 * @} 538 */ 539 540 /** @defgroup SDMMC_LL_Data_Block_Size Data Block Size 541 * @{ 542 */ 543 #define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U) 544 #define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0 545 #define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1 546 #define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1) 547 #define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2 548 #define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2) 549 #define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) 550 #define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) 551 #define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3 552 #define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3) 553 #define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 554 #define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 555 #define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 556 #define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 557 #define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 558 559 #define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \ 560 ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \ 561 ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \ 562 ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \ 563 ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \ 564 ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \ 565 ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \ 566 ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \ 567 ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \ 568 ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \ 569 ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \ 570 ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \ 571 ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \ 572 ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \ 573 ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) 574 /** 575 * @} 576 */ 577 578 /** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction 579 * @{ 580 */ 581 #define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U) 582 #define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR 583 584 #define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \ 585 ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)) 586 /** 587 * @} 588 */ 589 590 /** @defgroup SDMMC_LL_Transfer_Type Transfer Type 591 * @{ 592 */ 593 #define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U) 594 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 595 #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE_1 596 #else 597 #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE 598 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 599 600 #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \ 601 ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) 602 /** 603 * @} 604 */ 605 606 /** @defgroup SDMMC_LL_DPSM_State DPSM State 607 * @{ 608 */ 609 #define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000U) 610 #define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN 611 612 #define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\ 613 ((DPSM) == SDMMC_DPSM_ENABLE)) 614 /** 615 * @} 616 */ 617 618 /** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode 619 * @{ 620 */ 621 #define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U) 622 #define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD) 623 624 #define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \ 625 ((MODE) == SDMMC_READ_WAIT_MODE_DATA2)) 626 /** 627 * @} 628 */ 629 630 /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources 631 * @{ 632 */ 633 #define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE 634 #define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE 635 #define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE 636 #define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE 637 #define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE 638 #define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE 639 #define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE 640 #define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE 641 #define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE 642 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 643 #define SDMMC_IT_DHOLD SDMMC_MASK_DHOLDIE 644 #endif 645 #define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE 646 #if !defined(STM32L4P5xx) && !defined(STM32L4Q5xx) && !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) 647 #define SDMMC_IT_CMDACT SDMMC_MASK_CMDACTIE 648 #define SDMMC_IT_TXACT SDMMC_MASK_TXACTIE 649 #define SDMMC_IT_RXACT SDMMC_MASK_RXACTIE 650 #else 651 #define SDMMC_IT_DABORT SDMMC_MASK_DABORTIE 652 #endif 653 #define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE 654 #define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE 655 #if !defined(STM32L4P5xx) && !defined(STM32L4Q5xx) && !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) 656 #define SDMMC_IT_TXFIFOF SDMMC_MASK_TXFIFOFIE 657 #endif 658 #define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE 659 #define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE 660 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 661 #define SDMMC_IT_BUSYD0END SDMMC_MASK_BUSYD0ENDIE 662 #else 663 #define SDMMC_IT_RXFIFOE SDMMC_MASK_RXFIFOEIE 664 #define SDMMC_IT_TXDAVL SDMMC_MASK_TXDAVLIE 665 #define SDMMC_IT_RXDAVL SDMMC_MASK_RXDAVLIE 666 #endif 667 #define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE 668 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 669 #define SDMMC_IT_ACKFAIL SDMMC_MASK_ACKFAILIE 670 #define SDMMC_IT_ACKTIMEOUT SDMMC_MASK_ACKTIMEOUTIE 671 #define SDMMC_IT_VSWEND SDMMC_MASK_VSWENDIE 672 #define SDMMC_IT_CKSTOP SDMMC_MASK_CKSTOPIE 673 #define SDMMC_IT_IDMABTC SDMMC_MASK_IDMABTCIE 674 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 675 /** 676 * @} 677 */ 678 679 /** @defgroup SDMMC_LL_Flags Flags 680 * @{ 681 */ 682 #define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL 683 #define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL 684 #define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT 685 #define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT 686 #define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR 687 #define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR 688 #define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND 689 #define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT 690 #define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND 691 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 692 #define SDMMC_FLAG_DHOLD SDMMC_STA_DHOLD 693 #endif 694 #define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND 695 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 696 #define SDMMC_FLAG_DABORT SDMMC_STA_DABORT 697 #define SDMMC_FLAG_DPSMACT SDMMC_STA_DPSMACT 698 #define SDMMC_FLAG_CMDACT SDMMC_STA_CPSMACT 699 #else 700 #define SDMMC_FLAG_CMDACT SDMMC_STA_CMDACT 701 #define SDMMC_FLAG_TXACT SDMMC_STA_TXACT 702 #define SDMMC_FLAG_RXACT SDMMC_STA_RXACT 703 #endif 704 #define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE 705 #define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF 706 #define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF 707 #define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF 708 #define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE 709 #define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE 710 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 711 #define SDMMC_FLAG_BUSYD0 SDMMC_STA_BUSYD0 712 #define SDMMC_FLAG_BUSYD0END SDMMC_STA_BUSYD0END 713 #else 714 #define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL 715 #define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL 716 #endif 717 #define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT 718 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 719 #define SDMMC_FLAG_ACKFAIL SDMMC_STA_ACKFAIL 720 #define SDMMC_FLAG_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT 721 #define SDMMC_FLAG_VSWEND SDMMC_STA_VSWEND 722 #define SDMMC_FLAG_CKSTOP SDMMC_STA_CKSTOP 723 #define SDMMC_FLAG_IDMATE SDMMC_STA_IDMATE 724 #define SDMMC_FLAG_IDMABTC SDMMC_STA_IDMABTC 725 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 726 727 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 728 #define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ 729 SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ 730 SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ 731 SDMMC_FLAG_DHOLD | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT |\ 732 SDMMC_FLAG_BUSYD0END | SDMMC_FLAG_SDIOIT | SDMMC_FLAG_ACKFAIL |\ 733 SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND | SDMMC_FLAG_CKSTOP |\ 734 SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)) 735 736 #define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\ 737 SDMMC_FLAG_CMDSENT | SDMMC_FLAG_BUSYD0END)) 738 739 #define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\ 740 SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DHOLD |\ 741 SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT | SDMMC_FLAG_IDMATE |\ 742 SDMMC_FLAG_IDMABTC)) 743 744 #else 745 #define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ 746 SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ 747 SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ 748 SDMMC_FLAG_DBCKEND | SDMMC_FLAG_SDIOIT)) 749 750 #define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\ 751 SDMMC_FLAG_CMDSENT)) 752 753 #define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\ 754 SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DBCKEND)) 755 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 756 757 /** 758 * @} 759 */ 760 761 /** 762 * @} 763 */ 764 765 /* Exported macro ------------------------------------------------------------*/ 766 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros 767 * @{ 768 */ 769 770 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions 771 * @brief SDMMC_LL registers bit address in the alias region 772 * @{ 773 */ 774 /* ---------------------- SDMMC registers bit mask --------------------------- */ 775 /* --- CLKCR Register ---*/ 776 /* CLKCR register clear mask */ 777 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 778 #define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\ 779 SDMMC_CLKCR_WIDBUS |\ 780 SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN |\ 781 SDMMC_CLKCR_DDR | SDMMC_CLKCR_BUSSPEED |\ 782 SDMMC_CLKCR_SELCLKRX)) 783 #else 784 #define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\ 785 SDMMC_CLKCR_BYPASS | SDMMC_CLKCR_WIDBUS |\ 786 SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN)) 787 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 788 789 /* --- DCTRL Register ---*/ 790 /* SDMMC DCTRL Clear Mask */ 791 #define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN | SDMMC_DCTRL_DTDIR |\ 792 SDMMC_DCTRL_DTMODE | SDMMC_DCTRL_DBLOCKSIZE)) 793 794 /* --- CMD Register ---*/ 795 /* CMD Register clear mask */ 796 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 797 #define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\ 798 SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\ 799 SDMMC_CMD_CPSMEN | SDMMC_CMD_CMDSUSPEND)) 800 #else 801 #define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\ 802 SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\ 803 SDMMC_CMD_CPSMEN | SDMMC_CMD_SDIOSUSPEND)) 804 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 805 806 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 807 /* SDMMC Initialization Frequency (400KHz max) for Peripheral CLK 110MHz*/ 808 #define SDMMC_INIT_CLK_DIV ((uint8_t)0x8A) 809 810 /* SDMMC Default Speed Frequency (25Mhz max) for Peripheral CLK 110MHz*/ 811 #define SDMMC_NSPEED_CLK_DIV ((uint8_t)0x3) 812 813 /* SDMMC High Speed Frequency (50Mhz max) for Peripheral CLK 110MHz*/ 814 #define SDMMC_HSPEED_CLK_DIV ((uint8_t)0x2) 815 816 /* SDMMC Data Transfer Frequency (25MHz max) */ 817 #define SDMMC_TRANSFER_CLK_DIV SDMMC_NSPEED_CLK_DIV 818 #else 819 /* SDMMC Initialization Frequency (400KHz max) */ 820 #define SDMMC_INIT_CLK_DIV ((uint8_t)0x76) /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */ 821 822 /* SDMMC Data Transfer Frequency (25MHz max) */ 823 #define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0) /* 48MHz / (SDMMC_TRANSFER_CLK_DIV + 2) < 25MHz */ 824 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 825 826 /** 827 * @} 828 */ 829 830 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration 831 * @brief macros to handle interrupts and specific clock configurations 832 * @{ 833 */ 834 835 #if !defined(STM32L4P5xx) && !defined(STM32L4Q5xx) && !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) 836 /** 837 * @brief Enable the SDMMC device. 838 * @param __INSTANCE__ SDMMC Instance 839 * @retval None 840 */ 841 #define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN) 842 843 /** 844 * @brief Disable the SDMMC device. 845 * @param __INSTANCE__ SDMMC Instance 846 * @retval None 847 */ 848 #define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN) 849 850 /** 851 * @brief Enable the SDMMC DMA transfer. 852 * @param __INSTANCE__ SDMMC Instance 853 * @retval None 854 */ 855 #define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN) 856 857 /** 858 * @brief Disable the SDMMC DMA transfer. 859 * @param __INSTANCE__ SDMMC Instance 860 * @retval None 861 */ 862 #define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN) 863 #endif /* !STM32L4P5xx && !STM32L4Q5xx && !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ 864 865 /** 866 * @brief Enable the SDMMC device interrupt. 867 * @param __INSTANCE__ Pointer to SDMMC register base 868 * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled. 869 * This parameter can be one or a combination of the following values: 870 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 871 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 872 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 873 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 874 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 875 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 876 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 877 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 878 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 879 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 880 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 881 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 882 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt 883 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt 884 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt 885 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 886 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 887 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt 888 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 889 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 890 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt 891 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt 892 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt 893 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 894 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 895 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 896 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 897 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 898 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 899 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 900 * @retval None 901 */ 902 #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) 903 904 /** 905 * @brief Disable the SDMMC device interrupt. 906 * @param __INSTANCE__ Pointer to SDMMC register base 907 * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled. 908 * This parameter can be one or a combination of the following values: 909 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 910 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 911 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 912 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 913 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 914 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 915 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 916 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 917 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 918 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 919 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 920 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 921 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt 922 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt 923 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt 924 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 925 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 926 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt 927 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 928 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 929 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt 930 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt 931 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt 932 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 933 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 934 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 935 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 936 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 937 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 938 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 939 * @retval None 940 */ 941 #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) 942 943 /** 944 * @brief Checks whether the specified SDMMC flag is set or not. 945 * @param __INSTANCE__ Pointer to SDMMC register base 946 * @param __FLAG__ specifies the flag to check. 947 * This parameter can be one of the following values: 948 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) 949 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 950 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout 951 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout 952 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error 953 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error 954 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) 955 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) 956 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) 957 * @arg SDMMC_FLAG_DHOLD: Data transfer Hold 958 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) 959 * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 960 * @arg SDMMC_FLAG_DPSMACT: Data path state machine active 961 * @arg SDMMC_FLAG_CPSMACT: Command path state machine active 962 * @arg SDMMC_FLAG_CMDACT: Command transfer in progress 963 * @arg SDMMC_FLAG_TXACT: Data transmit in progress 964 * @arg SDMMC_FLAG_RXACT: Data receive in progress 965 * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty 966 * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full 967 * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full 968 * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full 969 * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty 970 * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty 971 * @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO 972 * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO 973 * @arg SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy) 974 * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected 975 * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received 976 * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received 977 * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout 978 * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion 979 * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure 980 * @arg SDMMC_FLAG_IDMATE: IDMA transfer error 981 * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete 982 * @retval The new state of SDMMC_FLAG (SET or RESET). 983 */ 984 #define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U) 985 986 987 /** 988 * @brief Clears the SDMMC pending flags. 989 * @param __INSTANCE__ Pointer to SDMMC register base 990 * @param __FLAG__ specifies the flag to clear. 991 * This parameter can be one or a combination of the following values: 992 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) 993 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 994 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout 995 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout 996 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error 997 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error 998 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) 999 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) 1000 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) 1001 * @arg SDMMC_FLAG_DHOLD: Data transfer Hold 1002 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) 1003 * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 1004 * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected 1005 * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received 1006 * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received 1007 * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout 1008 * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion 1009 * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure 1010 * @arg SDMMC_FLAG_IDMATE: IDMA transfer error 1011 * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete 1012 * @retval None 1013 */ 1014 #define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) 1015 1016 /** 1017 * @brief Checks whether the specified SDMMC interrupt has occurred or not. 1018 * @param __INSTANCE__ Pointer to SDMMC register base 1019 * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. 1020 * This parameter can be one of the following values: 1021 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 1022 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 1023 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 1024 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 1025 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 1026 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 1027 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 1028 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 1029 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 1030 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 1031 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 1032 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 1033 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt 1034 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt 1035 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt 1036 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 1037 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 1038 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt 1039 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 1040 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 1041 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt 1042 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt 1043 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt 1044 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 1045 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 1046 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 1047 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 1048 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 1049 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 1050 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 1051 * @retval The new state of SDMMC_IT (SET or RESET). 1052 */ 1053 #define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) 1054 1055 /** 1056 * @brief Clears the SDMMC's interrupt pending bits. 1057 * @param __INSTANCE__ Pointer to SDMMC register base 1058 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1059 * This parameter can be one or a combination of the following values: 1060 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 1061 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 1062 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 1063 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 1064 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 1065 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 1066 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 1067 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 1068 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 1069 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 1070 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 1071 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 1072 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 1073 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 1074 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 1075 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 1076 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 1077 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 1078 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 1079 * @retval None 1080 */ 1081 #define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) 1082 1083 /** 1084 * @brief Enable Start the SD I/O Read Wait operation. 1085 * @param __INSTANCE__ Pointer to SDMMC register base 1086 * @retval None 1087 */ 1088 #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART) 1089 1090 /** 1091 * @brief Disable Start the SD I/O Read Wait operations. 1092 * @param __INSTANCE__ Pointer to SDMMC register base 1093 * @retval None 1094 */ 1095 #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART) 1096 1097 /** 1098 * @brief Enable Start the SD I/O Read Wait operation. 1099 * @param __INSTANCE__ Pointer to SDMMC register base 1100 * @retval None 1101 */ 1102 #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP) 1103 1104 /** 1105 * @brief Disable Stop the SD I/O Read Wait operations. 1106 * @param __INSTANCE__ Pointer to SDMMC register base 1107 * @retval None 1108 */ 1109 #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP) 1110 1111 /** 1112 * @brief Enable the SD I/O Mode Operation. 1113 * @param __INSTANCE__ Pointer to SDMMC register base 1114 * @retval None 1115 */ 1116 #define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN) 1117 1118 /** 1119 * @brief Disable the SD I/O Mode Operation. 1120 * @param __INSTANCE__ Pointer to SDMMC register base 1121 * @retval None 1122 */ 1123 #define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN) 1124 1125 /** 1126 * @brief Enable the SD I/O Suspend command sending. 1127 * @param __INSTANCE__ Pointer to SDMMC register base 1128 * @retval None 1129 */ 1130 #if !defined(STM32L4P5xx) && !defined(STM32L4Q5xx) && !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) 1131 #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND) 1132 #else 1133 #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSUSPEND) 1134 #endif /* !STM32L4P5xx && !STM32L4Q5xx && !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ 1135 1136 /** 1137 * @brief Disable the SD I/O Suspend command sending. 1138 * @param __INSTANCE__ Pointer to SDMMC register base 1139 * @retval None 1140 */ 1141 #if !defined(STM32L4P5xx) && !defined(STM32L4Q5xx) && !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) 1142 #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND) 1143 #else 1144 #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSUSPEND) 1145 #endif /* !STM32L4P5xx && !STM32L4Q5xx && !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ 1146 1147 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 1148 /** 1149 * @brief Enable the CMDTRANS mode. 1150 * @param __INSTANCE__ Pointer to SDMMC register base 1151 * @retval None 1152 */ 1153 #define __SDMMC_CMDTRANS_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDTRANS) 1154 1155 /** 1156 * @brief Disable the CMDTRANS mode. 1157 * @param __INSTANCE__ Pointer to SDMMC register base 1158 * @retval None 1159 */ 1160 #define __SDMMC_CMDTRANS_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDTRANS) 1161 1162 /** 1163 * @brief Enable the CMDSTOP mode. 1164 * @param __INSTANCE__ Pointer to SDMMC register base 1165 * @retval None 1166 */ 1167 #define __SDMMC_CMDSTOP_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSTOP) 1168 1169 /** 1170 * @brief Disable the CMDSTOP mode. 1171 * @param __INSTANCE__ Pointer to SDMMC register base 1172 * @retval None 1173 */ 1174 #define __SDMMC_CMDSTOP_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSTOP) 1175 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 1176 1177 /** 1178 * @} 1179 */ 1180 1181 /** 1182 * @} 1183 */ 1184 1185 /* Exported functions --------------------------------------------------------*/ 1186 /** @addtogroup SDMMC_LL_Exported_Functions 1187 * @{ 1188 */ 1189 1190 /* Initialization/de-initialization functions **********************************/ 1191 /** @addtogroup HAL_SDMMC_LL_Group1 1192 * @{ 1193 */ 1194 HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init); 1195 /** 1196 * @} 1197 */ 1198 1199 /* I/O operation functions *****************************************************/ 1200 /** @addtogroup HAL_SDMMC_LL_Group2 1201 * @{ 1202 */ 1203 uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx); 1204 HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData); 1205 /** 1206 * @} 1207 */ 1208 1209 /* Peripheral Control functions ************************************************/ 1210 /** @addtogroup HAL_SDMMC_LL_Group3 1211 * @{ 1212 */ 1213 HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx); 1214 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 1215 HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx); 1216 #endif /* !STM32L4P5xx && !STM32L4Q5xx && !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ 1217 HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx); 1218 uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx); 1219 1220 /* Command path state machine (CPSM) management functions */ 1221 HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command); 1222 uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx); 1223 uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response); 1224 1225 /* Data path state machine (DPSM) management functions */ 1226 HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data); 1227 uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx); 1228 uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx); 1229 1230 /* SDMMC Cards mode management functions */ 1231 HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode); 1232 1233 /* SDMMC Commands management functions */ 1234 uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize); 1235 uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); 1236 uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); 1237 uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd); 1238 uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd); 1239 uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd); 1240 uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd); 1241 uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); 1242 uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); 1243 uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx, uint32_t EraseType); 1244 uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx); 1245 uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr); 1246 uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx); 1247 uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx); 1248 uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1249 uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1250 uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth); 1251 uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx); 1252 uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx); 1253 uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1254 uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA); 1255 uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA); 1256 uint32_t SDMMC_CmdSleepMmc(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1257 uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1258 uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx); 1259 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 1260 uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx); 1261 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 1262 uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1263 uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1264 uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1265 1266 /* SDMMC Responses management functions */ 1267 uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout); 1268 uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx); 1269 uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx); 1270 uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx); 1271 uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA); 1272 1273 /** 1274 * @} 1275 */ 1276 1277 /** 1278 * @} 1279 */ 1280 1281 /** 1282 * @} 1283 */ 1284 1285 /** 1286 * @} 1287 */ 1288 1289 /** 1290 * @} 1291 */ 1292 1293 /** 1294 * @} 1295 */ 1296 #endif /* SDMMC1 */ 1297 1298 #ifdef __cplusplus 1299 } 1300 #endif 1301 1302 #endif /* STM32L4xx_LL_SDMMC_H */ 1303
