1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef STM32L4xx_HAL_RCC_H 20 #define STM32L4xx_HAL_RCC_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32l4xx_hal_def.h" 28 29 /** @addtogroup STM32L4xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup RCC 34 * @{ 35 */ 36 37 /* Exported types ------------------------------------------------------------*/ 38 /** @defgroup RCC_Exported_Types RCC Exported Types 39 * @{ 40 */ 41 42 /** 43 * @brief RCC PLL configuration structure definition 44 */ 45 typedef struct 46 { 47 uint32_t PLLState; /*!< The new state of the PLL. 48 This parameter can be a value of @ref RCC_PLL_Config */ 49 50 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. 51 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 52 53 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. 54 This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. 55 This parameter must be a number between Min_Data = 1 and Max_Data = 8 on the other devices */ 56 57 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. 58 This parameter must be a number between Min_Data = 8 and Max_Data = 86 */ 59 60 #if defined(RCC_PLLP_SUPPORT) 61 uint32_t PLLP; /*!< PLLP: Division factor for SAI clock. 62 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 63 #endif /* RCC_PLLP_SUPPORT */ 64 65 uint32_t PLLQ; /*!< PLLQ: Division factor for SDMMC1, RNG and USB clocks. 66 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ 67 68 uint32_t PLLR; /*!< PLLR: Division for the main system clock. 69 User have to set the PLLR parameter correctly to not exceed max frequency 120MHZ 70 on STM32L4Rx/STM32L4Sx devices else 80MHz on the other devices. 71 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ 72 73 }RCC_PLLInitTypeDef; 74 75 /** 76 * @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition 77 */ 78 typedef struct 79 { 80 uint32_t OscillatorType; /*!< The oscillators to be configured. 81 This parameter can be a value of @ref RCC_Oscillator_Type */ 82 83 uint32_t HSEState; /*!< The new state of the HSE. 84 This parameter can be a value of @ref RCC_HSE_Config */ 85 86 uint32_t LSEState; /*!< The new state of the LSE. 87 This parameter can be a value of @ref RCC_LSE_Config */ 88 89 uint32_t HSIState; /*!< The new state of the HSI. 90 This parameter can be a value of @ref RCC_HSI_Config */ 91 92 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 93 This parameter must be a number between Min_Data = 0 and Max_Data = 31 on 94 STM32L43x/STM32L44x/STM32L47x/STM32L48x devices. 95 This parameter must be a number between Min_Data = 0 and Max_Data = 127 on 96 the other devices */ 97 98 uint32_t LSIState; /*!< The new state of the LSI. 99 This parameter can be a value of @ref RCC_LSI_Config */ 100 #if defined(RCC_CSR_LSIPREDIV) 101 102 uint32_t LSIDiv; /*!< The division factor of the LSI. 103 This parameter can be a value of @ref RCC_LSI_Div */ 104 #endif /* RCC_CSR_LSIPREDIV */ 105 106 uint32_t MSIState; /*!< The new state of the MSI. 107 This parameter can be a value of @ref RCC_MSI_Config */ 108 109 uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT). 110 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 111 112 uint32_t MSIClockRange; /*!< The MSI frequency range. 113 This parameter can be a value of @ref RCC_MSI_Clock_Range */ 114 115 uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32L43x/STM32L44x/STM32L49x/STM32L4Ax devices). 116 This parameter can be a value of @ref RCC_HSI48_Config */ 117 118 RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ 119 120 }RCC_OscInitTypeDef; 121 122 /** 123 * @brief RCC System, AHB and APB busses clock configuration structure definition 124 */ 125 typedef struct 126 { 127 uint32_t ClockType; /*!< The clock to be configured. 128 This parameter can be a value of @ref RCC_System_Clock_Type */ 129 130 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). 131 This parameter can be a value of @ref RCC_System_Clock_Source */ 132 133 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 134 This parameter can be a value of @ref RCC_AHB_Clock_Source */ 135 136 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 137 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 138 139 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 140 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 141 142 }RCC_ClkInitTypeDef; 143 144 /** 145 * @} 146 */ 147 148 /* Exported constants --------------------------------------------------------*/ 149 /** @defgroup RCC_Exported_Constants RCC Exported Constants 150 * @{ 151 */ 152 153 /** @defgroup RCC_Timeout_Value Timeout Values 154 * @{ 155 */ 156 #define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ 157 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 158 /** 159 * @} 160 */ 161 162 /** @defgroup RCC_Oscillator_Type Oscillator Type 163 * @{ 164 */ 165 #define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */ 166 #define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */ 167 #define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */ 168 #define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */ 169 #define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */ 170 #define RCC_OSCILLATORTYPE_MSI 0x00000010U /*!< MSI to configure */ 171 #if defined(RCC_HSI48_SUPPORT) 172 #define RCC_OSCILLATORTYPE_HSI48 0x00000020U /*!< HSI48 to configure */ 173 #endif /* RCC_HSI48_SUPPORT */ 174 /** 175 * @} 176 */ 177 178 /** @defgroup RCC_HSE_Config HSE Config 179 * @{ 180 */ 181 #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ 182 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 183 #define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */ 184 /** 185 * @} 186 */ 187 188 /** @defgroup RCC_LSE_Config LSE Config 189 * @{ 190 */ 191 #define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ 192 #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ 193 #define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ 194 #if defined(RCC_BDCR_LSESYSDIS) 195 #define RCC_LSE_ON_RTC_ONLY (RCC_BDCR_LSESYSDIS | RCC_BDCR_LSEON) /*!< LSE clock activation without propagation to system */ 196 #define RCC_LSE_BYPASS_RTC_ONLY (RCC_BDCR_LSEBYP | RCC_BDCR_LSESYSDIS | RCC_BDCR_LSEON) /*!< External clock source for LSE clock without propagation to system */ 197 #endif /* RCC_BDCR_LSESYSDIS */ 198 /** 199 * @} 200 */ 201 202 /** @defgroup RCC_HSI_Config HSI Config 203 * @{ 204 */ 205 #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ 206 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 207 208 #if defined(RCC_ICSCR_HSITRIM_6) 209 #define RCC_HSICALIBRATION_DEFAULT 0x40U /*!< Default HSI calibration trimming value 64 on devices other than STM32L43x/STM32L44x/STM32L47x/STM32L48x */ 210 #else 211 #define RCC_HSICALIBRATION_DEFAULT 0x10U /*!< Default HSI calibration trimming value 16 on STM32L43x/STM32L44x/STM32L47x/STM32L48x devices */ 212 #endif /* RCC_ICSCR_HSITRIM_6 */ 213 /** 214 * @} 215 */ 216 217 /** @defgroup RCC_LSI_Config LSI Config 218 * @{ 219 */ 220 #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ 221 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ 222 /** 223 * @} 224 */ 225 #if defined(RCC_CSR_LSIPREDIV) 226 227 /** @defgroup RCC_LSI_Div LSI Div 228 * @{ 229 */ 230 #define RCC_LSI_DIV1 0x00000000U /*!< LSI clock not divided */ 231 #define RCC_LSI_DIV128 RCC_CSR_LSIPREDIV /*!< LSI clock divided by 128 */ 232 /** 233 * @} 234 */ 235 #endif /* RCC_CSR_LSIPREDIV */ 236 237 /** @defgroup RCC_MSI_Config MSI Config 238 * @{ 239 */ 240 #define RCC_MSI_OFF 0x00000000U /*!< MSI clock deactivation */ 241 #define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */ 242 243 #define RCC_MSICALIBRATION_DEFAULT 0U /*!< Default MSI calibration trimming value */ 244 /** 245 * @} 246 */ 247 248 #if defined(RCC_HSI48_SUPPORT) 249 /** @defgroup RCC_HSI48_Config HSI48 Config 250 * @{ 251 */ 252 #define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ 253 #define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */ 254 /** 255 * @} 256 */ 257 #else 258 /** @defgroup RCC_HSI48_Config HSI48 Config 259 * @{ 260 */ 261 #define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ 262 /** 263 * @} 264 */ 265 #endif /* RCC_HSI48_SUPPORT */ 266 267 /** @defgroup RCC_PLL_Config PLL Config 268 * @{ 269 */ 270 #define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */ 271 #define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ 272 #define RCC_PLL_ON 0x00000002U /*!< PLL activation */ 273 /** 274 * @} 275 */ 276 277 #if defined(RCC_PLLP_SUPPORT) 278 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider 279 * @{ 280 */ 281 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 282 #define RCC_PLLP_DIV2 0x00000002U /*!< PLLP division factor = 2 */ 283 #define RCC_PLLP_DIV3 0x00000003U /*!< PLLP division factor = 3 */ 284 #define RCC_PLLP_DIV4 0x00000004U /*!< PLLP division factor = 4 */ 285 #define RCC_PLLP_DIV5 0x00000005U /*!< PLLP division factor = 5 */ 286 #define RCC_PLLP_DIV6 0x00000006U /*!< PLLP division factor = 6 */ 287 #define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */ 288 #define RCC_PLLP_DIV8 0x00000008U /*!< PLLP division factor = 8 */ 289 #define RCC_PLLP_DIV9 0x00000009U /*!< PLLP division factor = 9 */ 290 #define RCC_PLLP_DIV10 0x0000000AU /*!< PLLP division factor = 10 */ 291 #define RCC_PLLP_DIV11 0x0000000BU /*!< PLLP division factor = 11 */ 292 #define RCC_PLLP_DIV12 0x0000000CU /*!< PLLP division factor = 12 */ 293 #define RCC_PLLP_DIV13 0x0000000DU /*!< PLLP division factor = 13 */ 294 #define RCC_PLLP_DIV14 0x0000000EU /*!< PLLP division factor = 14 */ 295 #define RCC_PLLP_DIV15 0x0000000FU /*!< PLLP division factor = 15 */ 296 #define RCC_PLLP_DIV16 0x00000010U /*!< PLLP division factor = 16 */ 297 #define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */ 298 #define RCC_PLLP_DIV18 0x00000012U /*!< PLLP division factor = 18 */ 299 #define RCC_PLLP_DIV19 0x00000013U /*!< PLLP division factor = 19 */ 300 #define RCC_PLLP_DIV20 0x00000014U /*!< PLLP division factor = 20 */ 301 #define RCC_PLLP_DIV21 0x00000015U /*!< PLLP division factor = 21 */ 302 #define RCC_PLLP_DIV22 0x00000016U /*!< PLLP division factor = 22 */ 303 #define RCC_PLLP_DIV23 0x00000017U /*!< PLLP division factor = 23 */ 304 #define RCC_PLLP_DIV24 0x00000018U /*!< PLLP division factor = 24 */ 305 #define RCC_PLLP_DIV25 0x00000019U /*!< PLLP division factor = 25 */ 306 #define RCC_PLLP_DIV26 0x0000001AU /*!< PLLP division factor = 26 */ 307 #define RCC_PLLP_DIV27 0x0000001BU /*!< PLLP division factor = 27 */ 308 #define RCC_PLLP_DIV28 0x0000001CU /*!< PLLP division factor = 28 */ 309 #define RCC_PLLP_DIV29 0x0000001DU /*!< PLLP division factor = 29 */ 310 #define RCC_PLLP_DIV30 0x0000001EU /*!< PLLP division factor = 30 */ 311 #define RCC_PLLP_DIV31 0x0000001FU /*!< PLLP division factor = 31 */ 312 #else 313 #define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */ 314 #define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */ 315 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ 316 /** 317 * @} 318 */ 319 #endif /* RCC_PLLP_SUPPORT */ 320 321 /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider 322 * @{ 323 */ 324 #define RCC_PLLQ_DIV2 0x00000002U /*!< PLLQ division factor = 2 */ 325 #define RCC_PLLQ_DIV4 0x00000004U /*!< PLLQ division factor = 4 */ 326 #define RCC_PLLQ_DIV6 0x00000006U /*!< PLLQ division factor = 6 */ 327 #define RCC_PLLQ_DIV8 0x00000008U /*!< PLLQ division factor = 8 */ 328 /** 329 * @} 330 */ 331 332 /** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider 333 * @{ 334 */ 335 #define RCC_PLLR_DIV2 0x00000002U /*!< PLLR division factor = 2 */ 336 #define RCC_PLLR_DIV4 0x00000004U /*!< PLLR division factor = 4 */ 337 #define RCC_PLLR_DIV6 0x00000006U /*!< PLLR division factor = 6 */ 338 #define RCC_PLLR_DIV8 0x00000008U /*!< PLLR division factor = 8 */ 339 /** 340 * @} 341 */ 342 343 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source 344 * @{ 345 */ 346 #define RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as PLL entry clock source */ 347 #define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /*!< MSI clock selected as PLL entry clock source */ 348 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */ 349 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ 350 /** 351 * @} 352 */ 353 354 /** @defgroup RCC_PLL_Clock_Output PLL Clock Output 355 * @{ 356 */ 357 #if defined(RCC_PLLSAI2_SUPPORT) 358 #define RCC_PLL_SAI3CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI3CLK selection from main PLL (for devices with PLLSAI2) */ 359 #elif defined(RCC_PLLSAI1_SUPPORT) 360 #define RCC_PLL_SAI2CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI2CLK selection from main PLL (for devices without PLLSAI2) */ 361 #endif /* RCC_PLLSAI2_SUPPORT */ 362 #define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /*!< PLL48M1CLK selection from main PLL */ 363 #define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /*!< PLLCLK selection from main PLL */ 364 /** 365 * @} 366 */ 367 #if defined(RCC_PLLSAI1_SUPPORT) 368 369 /** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output 370 * @{ 371 */ 372 #define RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLSAI1PEN /*!< PLLSAI1CLK selection from PLLSAI1 */ 373 #define RCC_PLLSAI1_48M2CLK RCC_PLLSAI1CFGR_PLLSAI1QEN /*!< PLL48M2CLK selection from PLLSAI1 */ 374 #define RCC_PLLSAI1_ADC1CLK RCC_PLLSAI1CFGR_PLLSAI1REN /*!< PLLADC1CLK selection from PLLSAI1 */ 375 /** 376 * @} 377 */ 378 #endif /* RCC_PLLSAI1_SUPPORT */ 379 380 #if defined(RCC_PLLSAI2_SUPPORT) 381 382 /** @defgroup RCC_PLLSAI2_Clock_Output PLLSAI2 Clock Output 383 * @{ 384 */ 385 #define RCC_PLLSAI2_SAI2CLK RCC_PLLSAI2CFGR_PLLSAI2PEN /*!< PLLSAI2CLK selection from PLLSAI2 */ 386 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) 387 #define RCC_PLLSAI2_DSICLK RCC_PLLSAI2CFGR_PLLSAI2QEN /*!< PLLDSICLK selection from PLLSAI2 */ 388 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ 389 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) 390 #define RCC_PLLSAI2_ADC2CLK RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLADC2CLK selection from PLLSAI2 */ 391 #else 392 #define RCC_PLLSAI2_LTDCCLK RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLLTDCCLK selection from PLLSAI2 */ 393 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ 394 /** 395 * @} 396 */ 397 398 #endif /* RCC_PLLSAI2_SUPPORT */ 399 400 /** @defgroup RCC_MSI_Clock_Range MSI Clock Range 401 * @{ 402 */ 403 #define RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */ 404 #define RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */ 405 #define RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */ 406 #define RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */ 407 #define RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */ 408 #define RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */ 409 #define RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */ 410 #define RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */ 411 #define RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */ 412 #define RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */ 413 #define RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */ 414 #define RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */ 415 /** 416 * @} 417 */ 418 419 /** @defgroup RCC_System_Clock_Type System Clock Type 420 * @{ 421 */ 422 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ 423 #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ 424 #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ 425 #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ 426 /** 427 * @} 428 */ 429 430 /** @defgroup RCC_System_Clock_Source System Clock Source 431 * @{ 432 */ 433 #define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */ 434 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ 435 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ 436 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ 437 /** 438 * @} 439 */ 440 441 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 442 * @{ 443 */ 444 #define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */ 445 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ 446 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ 447 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ 448 /** 449 * @} 450 */ 451 452 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source 453 * @{ 454 */ 455 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ 456 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ 457 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ 458 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ 459 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ 460 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ 461 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ 462 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ 463 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ 464 /** 465 * @} 466 */ 467 468 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source 469 * @{ 470 */ 471 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ 472 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ 473 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ 474 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ 475 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ 476 /** 477 * @} 478 */ 479 480 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 481 * @{ 482 */ 483 #define RCC_RTCCLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ 484 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ 485 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ 486 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ 487 /** 488 * @} 489 */ 490 491 /** @defgroup RCC_MCO_Index MCO Index 492 * @{ 493 */ 494 #define RCC_MCO1 0x00000000U 495 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ 496 /** 497 * @} 498 */ 499 500 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source 501 * @{ 502 */ 503 #define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */ 504 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ 505 #define RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */ 506 #define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */ 507 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */ 508 #define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< PLLCLK selection as MCO1 source */ 509 #define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */ 510 #define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */ 511 #if defined(RCC_HSI48_SUPPORT) 512 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source (STM32L43x/STM32L44x devices) */ 513 #endif /* RCC_HSI48_SUPPORT */ 514 /** 515 * @} 516 */ 517 518 /** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler 519 * @{ 520 */ 521 #define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */ 522 #define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */ 523 #define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */ 524 #define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */ 525 #define RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */ 526 /** 527 * @} 528 */ 529 530 /** @defgroup RCC_Interrupt Interrupts 531 * @{ 532 */ 533 #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ 534 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ 535 #define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */ 536 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */ 537 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ 538 #define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ 539 #if defined(RCC_PLLSAI1_SUPPORT) 540 #define RCC_IT_PLLSAI1RDY RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */ 541 #endif /* RCC_PLLSAI1_SUPPORT */ 542 #if defined(RCC_PLLSAI2_SUPPORT) 543 #define RCC_IT_PLLSAI2RDY RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */ 544 #endif /* RCC_PLLSAI2_SUPPORT */ 545 #define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ 546 #define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ 547 #if defined(RCC_HSI48_SUPPORT) 548 #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ 549 #endif /* RCC_HSI48_SUPPORT */ 550 /** 551 * @} 552 */ 553 554 /** @defgroup RCC_Flag Flags 555 * Elements values convention: XXXYYYYYb 556 * - YYYYY : Flag position in the register 557 * - XXX : Register index 558 * - 001: CR register 559 * - 010: BDCR register 560 * - 011: CSR register 561 * - 100: CRRCR register 562 * @{ 563 */ 564 /* Flags in the CR register */ 565 #define RCC_FLAG_MSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos) /*!< MSI Ready flag */ 566 #define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ 567 #define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ 568 #define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */ 569 #if defined(RCC_PLLSAI1_SUPPORT) 570 #define RCC_FLAG_PLLSAI1RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos) /*!< PLLSAI1 Ready flag */ 571 #endif /* RCC_PLLSAI1_SUPPORT */ 572 #if defined(RCC_PLLSAI2_SUPPORT) 573 #define RCC_FLAG_PLLSAI2RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI2RDY_Pos) /*!< PLLSAI2 Ready flag */ 574 #endif /* RCC_PLLSAI2_SUPPORT */ 575 576 /* Flags in the BDCR register */ 577 #define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */ 578 #define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */ 579 580 /* Flags in the CSR register */ 581 #define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */ 582 #define RCC_FLAG_FWRST ((CSR_REG_INDEX << 5U) | RCC_CSR_FWRSTF_Pos) /*!< Firewall reset flag */ 583 #define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */ 584 #define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */ 585 #define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */ 586 #define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */ 587 #define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */ 588 #define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ 589 #define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ 590 591 #if defined(RCC_HSI48_SUPPORT) 592 /* Flags in the CRRCR register */ 593 #define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */ 594 #endif /* RCC_HSI48_SUPPORT */ 595 /** 596 * @} 597 */ 598 599 /** @defgroup RCC_LSEDrive_Config LSE Drive Config 600 * @{ 601 */ 602 #define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */ 603 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ 604 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ 605 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ 606 /** 607 * @} 608 */ 609 610 /** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock 611 * @{ 612 */ 613 #define RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */ 614 #define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */ 615 /** 616 * @} 617 */ 618 619 /** 620 * @} 621 */ 622 623 /* Exported macros -----------------------------------------------------------*/ 624 625 /** @defgroup RCC_Exported_Macros RCC Exported Macros 626 * @{ 627 */ 628 629 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 630 * @brief Enable or disable the AHB1 peripheral clock. 631 * @note After reset, the peripheral clock (used for registers read/write access) 632 * is disabled and the application software has to enable this clock before 633 * using it. 634 * @{ 635 */ 636 637 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ 638 __IO uint32_t tmpreg; \ 639 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ 640 /* Delay after an RCC peripheral clock enabling */ \ 641 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ 642 UNUSED(tmpreg); \ 643 } while(0) 644 645 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ 646 __IO uint32_t tmpreg; \ 647 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ 648 /* Delay after an RCC peripheral clock enabling */ \ 649 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ 650 UNUSED(tmpreg); \ 651 } while(0) 652 653 #if defined(DMAMUX1) 654 #define __HAL_RCC_DMAMUX1_CLK_ENABLE() do { \ 655 __IO uint32_t tmpreg; \ 656 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ 657 /* Delay after an RCC peripheral clock enabling */ \ 658 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ 659 UNUSED(tmpreg); \ 660 } while(0) 661 #endif /* DMAMUX1 */ 662 663 #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ 664 __IO uint32_t tmpreg; \ 665 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 666 /* Delay after an RCC peripheral clock enabling */ \ 667 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 668 UNUSED(tmpreg); \ 669 } while(0) 670 671 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 672 __IO uint32_t tmpreg; \ 673 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 674 /* Delay after an RCC peripheral clock enabling */ \ 675 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 676 UNUSED(tmpreg); \ 677 } while(0) 678 679 #define __HAL_RCC_TSC_CLK_ENABLE() do { \ 680 __IO uint32_t tmpreg; \ 681 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 682 /* Delay after an RCC peripheral clock enabling */ \ 683 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 684 UNUSED(tmpreg); \ 685 } while(0) 686 687 #if defined(DMA2D) 688 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ 689 __IO uint32_t tmpreg; \ 690 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ 691 /* Delay after an RCC peripheral clock enabling */ \ 692 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ 693 UNUSED(tmpreg); \ 694 } while(0) 695 #endif /* DMA2D */ 696 697 #if defined(GFXMMU) 698 #define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \ 699 __IO uint32_t tmpreg; \ 700 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ 701 /* Delay after an RCC peripheral clock enabling */ \ 702 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ 703 UNUSED(tmpreg); \ 704 } while(0) 705 #endif /* GFXMMU */ 706 707 708 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) 709 710 #define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) 711 712 #if defined(DMAMUX1) 713 #define __HAL_RCC_DMAMUX1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) 714 #endif /* DMAMUX1 */ 715 716 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) 717 718 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) 719 720 #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) 721 722 #if defined(DMA2D) 723 #define __HAL_RCC_DMA2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) 724 #endif /* DMA2D */ 725 726 #if defined(GFXMMU) 727 #define __HAL_RCC_GFXMMU_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) 728 #endif /* GFXMMU */ 729 730 /** 731 * @} 732 */ 733 734 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 735 * @brief Enable or disable the AHB2 peripheral clock. 736 * @note After reset, the peripheral clock (used for registers read/write access) 737 * is disabled and the application software has to enable this clock before 738 * using it. 739 * @{ 740 */ 741 742 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 743 __IO uint32_t tmpreg; \ 744 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ 745 /* Delay after an RCC peripheral clock enabling */ \ 746 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ 747 UNUSED(tmpreg); \ 748 } while(0) 749 750 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 751 __IO uint32_t tmpreg; \ 752 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ 753 /* Delay after an RCC peripheral clock enabling */ \ 754 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ 755 UNUSED(tmpreg); \ 756 } while(0) 757 758 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 759 __IO uint32_t tmpreg; \ 760 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ 761 /* Delay after an RCC peripheral clock enabling */ \ 762 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ 763 UNUSED(tmpreg); \ 764 } while(0) 765 766 #if defined(GPIOD) 767 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 768 __IO uint32_t tmpreg; \ 769 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ 770 /* Delay after an RCC peripheral clock enabling */ \ 771 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ 772 UNUSED(tmpreg); \ 773 } while(0) 774 #endif /* GPIOD */ 775 776 #if defined(GPIOE) 777 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 778 __IO uint32_t tmpreg; \ 779 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ 780 /* Delay after an RCC peripheral clock enabling */ \ 781 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ 782 UNUSED(tmpreg); \ 783 } while(0) 784 #endif /* GPIOE */ 785 786 #if defined(GPIOF) 787 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 788 __IO uint32_t tmpreg; \ 789 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ 790 /* Delay after an RCC peripheral clock enabling */ \ 791 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ 792 UNUSED(tmpreg); \ 793 } while(0) 794 #endif /* GPIOF */ 795 796 #if defined(GPIOG) 797 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 798 __IO uint32_t tmpreg; \ 799 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ 800 /* Delay after an RCC peripheral clock enabling */ \ 801 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ 802 UNUSED(tmpreg); \ 803 } while(0) 804 #endif /* GPIOG */ 805 806 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ 807 __IO uint32_t tmpreg; \ 808 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ 809 /* Delay after an RCC peripheral clock enabling */ \ 810 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ 811 UNUSED(tmpreg); \ 812 } while(0) 813 814 #if defined(GPIOI) 815 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ 816 __IO uint32_t tmpreg; \ 817 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \ 818 /* Delay after an RCC peripheral clock enabling */ \ 819 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \ 820 UNUSED(tmpreg); \ 821 } while(0) 822 #endif /* GPIOI */ 823 824 #if defined(USB_OTG_FS) 825 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ 826 __IO uint32_t tmpreg; \ 827 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \ 828 /* Delay after an RCC peripheral clock enabling */ \ 829 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \ 830 UNUSED(tmpreg); \ 831 } while(0) 832 #endif /* USB_OTG_FS */ 833 834 #define __HAL_RCC_ADC_CLK_ENABLE() do { \ 835 __IO uint32_t tmpreg; \ 836 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \ 837 /* Delay after an RCC peripheral clock enabling */ \ 838 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \ 839 UNUSED(tmpreg); \ 840 } while(0) 841 842 #if defined(DCMI) 843 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ 844 __IO uint32_t tmpreg; \ 845 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \ 846 /* Delay after an RCC peripheral clock enabling */ \ 847 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \ 848 UNUSED(tmpreg); \ 849 } while(0) 850 #endif /* DCMI */ 851 852 #if defined(PKA) 853 #define __HAL_RCC_PKA_CLK_ENABLE() do { \ 854 __IO uint32_t tmpreg; \ 855 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \ 856 /* Delay after an RCC peripheral clock enabling */ \ 857 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \ 858 UNUSED(tmpreg); \ 859 } while(0) 860 #endif /* PKA */ 861 862 #if defined(AES) 863 #define __HAL_RCC_AES_CLK_ENABLE() do { \ 864 __IO uint32_t tmpreg; \ 865 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ 866 /* Delay after an RCC peripheral clock enabling */ \ 867 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ 868 UNUSED(tmpreg); \ 869 } while(0) 870 #endif /* AES */ 871 872 #if defined(HASH) 873 #define __HAL_RCC_HASH_CLK_ENABLE() do { \ 874 __IO uint32_t tmpreg; \ 875 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ 876 /* Delay after an RCC peripheral clock enabling */ \ 877 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ 878 UNUSED(tmpreg); \ 879 } while(0) 880 #endif /* HASH */ 881 882 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 883 __IO uint32_t tmpreg; \ 884 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ 885 /* Delay after an RCC peripheral clock enabling */ \ 886 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ 887 UNUSED(tmpreg); \ 888 } while(0) 889 890 #if defined(OCTOSPIM) 891 #define __HAL_RCC_OSPIM_CLK_ENABLE() do { \ 892 __IO uint32_t tmpreg; \ 893 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \ 894 /* Delay after an RCC peripheral clock enabling */ \ 895 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \ 896 UNUSED(tmpreg); \ 897 } while(0) 898 #endif /* OCTOSPIM */ 899 900 #if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN) 901 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ 902 __IO uint32_t tmpreg; \ 903 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \ 904 /* Delay after an RCC peripheral clock enabling */ \ 905 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \ 906 UNUSED(tmpreg); \ 907 } while(0) 908 #endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */ 909 910 #if defined(SDMMC2) 911 #define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ 912 __IO uint32_t tmpreg; \ 913 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN); \ 914 /* Delay after an RCC peripheral clock enabling */ \ 915 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN); \ 916 UNUSED(tmpreg); \ 917 } while(0) 918 #endif /* SDMMC2 */ 919 920 921 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) 922 923 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) 924 925 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) 926 927 #if defined(GPIOD) 928 #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) 929 #endif /* GPIOD */ 930 931 #if defined(GPIOE) 932 #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) 933 #endif /* GPIOE */ 934 935 #if defined(GPIOF) 936 #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) 937 #endif /* GPIOF */ 938 939 #if defined(GPIOG) 940 #define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) 941 #endif /* GPIOG */ 942 943 #define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) 944 945 #if defined(GPIOI) 946 #define __HAL_RCC_GPIOI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) 947 #endif /* GPIOI */ 948 949 #if defined(USB_OTG_FS) 950 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); 951 #endif /* USB_OTG_FS */ 952 953 #define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) 954 955 #if defined(DCMI) 956 #define __HAL_RCC_DCMI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) 957 #endif /* DCMI */ 958 959 #if defined(PKA) 960 #define __HAL_RCC_PKA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) 961 #endif /* PKA */ 962 963 #if defined(AES) 964 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); 965 #endif /* AES */ 966 967 #if defined(HASH) 968 #define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) 969 #endif /* HASH */ 970 971 #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) 972 973 #if defined(OCTOSPIM) 974 #define __HAL_RCC_OSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN) 975 #endif /* OCTOSPIM */ 976 977 #if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN) 978 #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN) 979 #endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */ 980 981 #if defined(SDMMC2) 982 #define __HAL_RCC_SDMMC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN) 983 #endif /* SDMMC2 */ 984 985 /** 986 * @} 987 */ 988 989 /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 990 * @brief Enable or disable the AHB3 peripheral clock. 991 * @note After reset, the peripheral clock (used for registers read/write access) 992 * is disabled and the application software has to enable this clock before 993 * using it. 994 * @{ 995 */ 996 997 #if defined(FMC_BANK1) 998 #define __HAL_RCC_FMC_CLK_ENABLE() do { \ 999 __IO uint32_t tmpreg; \ 1000 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ 1001 /* Delay after an RCC peripheral clock enabling */ \ 1002 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ 1003 UNUSED(tmpreg); \ 1004 } while(0) 1005 #endif /* FMC_BANK1 */ 1006 1007 #if defined(QUADSPI) 1008 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ 1009 __IO uint32_t tmpreg; \ 1010 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \ 1011 /* Delay after an RCC peripheral clock enabling */ \ 1012 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \ 1013 UNUSED(tmpreg); \ 1014 } while(0) 1015 #endif /* QUADSPI */ 1016 1017 #if defined(OCTOSPI1) 1018 #define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ 1019 __IO uint32_t tmpreg; \ 1020 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \ 1021 /* Delay after an RCC peripheral clock enabling */ \ 1022 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \ 1023 UNUSED(tmpreg); \ 1024 } while(0) 1025 #endif /* OCTOSPI1 */ 1026 1027 #if defined(OCTOSPI2) 1028 #define __HAL_RCC_OSPI2_CLK_ENABLE() do { \ 1029 __IO uint32_t tmpreg; \ 1030 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \ 1031 /* Delay after an RCC peripheral clock enabling */ \ 1032 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \ 1033 UNUSED(tmpreg); \ 1034 } while(0) 1035 #endif /* OCTOSPI2 */ 1036 1037 #if defined(FMC_BANK1) 1038 #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) 1039 #endif /* FMC_BANK1 */ 1040 1041 #if defined(QUADSPI) 1042 #define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) 1043 #endif /* QUADSPI */ 1044 1045 #if defined(OCTOSPI1) 1046 #define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN) 1047 #endif /* OCTOSPI1 */ 1048 1049 #if defined(OCTOSPI2) 1050 #define __HAL_RCC_OSPI2_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN) 1051 #endif /* OCTOSPI2 */ 1052 1053 /** 1054 * @} 1055 */ 1056 1057 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 1058 * @brief Enable or disable the APB1 peripheral clock. 1059 * @note After reset, the peripheral clock (used for registers read/write access) 1060 * is disabled and the application software has to enable this clock before 1061 * using it. 1062 * @{ 1063 */ 1064 1065 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 1066 __IO uint32_t tmpreg; \ 1067 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ 1068 /* Delay after an RCC peripheral clock enabling */ \ 1069 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ 1070 UNUSED(tmpreg); \ 1071 } while(0) 1072 1073 #if defined(TIM3) 1074 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 1075 __IO uint32_t tmpreg; \ 1076 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ 1077 /* Delay after an RCC peripheral clock enabling */ \ 1078 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ 1079 UNUSED(tmpreg); \ 1080 } while(0) 1081 #endif /* TIM3 */ 1082 1083 #if defined(TIM4) 1084 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 1085 __IO uint32_t tmpreg; \ 1086 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ 1087 /* Delay after an RCC peripheral clock enabling */ \ 1088 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ 1089 UNUSED(tmpreg); \ 1090 } while(0) 1091 #endif /* TIM4 */ 1092 1093 #if defined(TIM5) 1094 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 1095 __IO uint32_t tmpreg; \ 1096 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ 1097 /* Delay after an RCC peripheral clock enabling */ \ 1098 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ 1099 UNUSED(tmpreg); \ 1100 } while(0) 1101 #endif /* TIM5 */ 1102 1103 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 1104 __IO uint32_t tmpreg; \ 1105 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ 1106 /* Delay after an RCC peripheral clock enabling */ \ 1107 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ 1108 UNUSED(tmpreg); \ 1109 } while(0) 1110 1111 #if defined(TIM7) 1112 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 1113 __IO uint32_t tmpreg; \ 1114 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ 1115 /* Delay after an RCC peripheral clock enabling */ \ 1116 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ 1117 UNUSED(tmpreg); \ 1118 } while(0) 1119 #endif /* TIM7 */ 1120 1121 #if defined(LCD) 1122 #define __HAL_RCC_LCD_CLK_ENABLE() do { \ 1123 __IO uint32_t tmpreg; \ 1124 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \ 1125 /* Delay after an RCC peripheral clock enabling */ \ 1126 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \ 1127 UNUSED(tmpreg); \ 1128 } while(0) 1129 #endif /* LCD */ 1130 1131 #if defined(RCC_APB1ENR1_RTCAPBEN) 1132 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ 1133 __IO uint32_t tmpreg; \ 1134 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ 1135 /* Delay after an RCC peripheral clock enabling */ \ 1136 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ 1137 UNUSED(tmpreg); \ 1138 } while(0) 1139 #endif /* RCC_APB1ENR1_RTCAPBEN */ 1140 1141 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 1142 __IO uint32_t tmpreg; \ 1143 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ 1144 /* Delay after an RCC peripheral clock enabling */ \ 1145 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ 1146 UNUSED(tmpreg); \ 1147 } while(0) 1148 1149 #if defined(SPI2) 1150 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 1151 __IO uint32_t tmpreg; \ 1152 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ 1153 /* Delay after an RCC peripheral clock enabling */ \ 1154 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ 1155 UNUSED(tmpreg); \ 1156 } while(0) 1157 #endif /* SPI2 */ 1158 1159 #if defined(SPI3) 1160 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 1161 __IO uint32_t tmpreg; \ 1162 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ 1163 /* Delay after an RCC peripheral clock enabling */ \ 1164 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ 1165 UNUSED(tmpreg); \ 1166 } while(0) 1167 #endif /* SPI3 */ 1168 1169 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 1170 __IO uint32_t tmpreg; \ 1171 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ 1172 /* Delay after an RCC peripheral clock enabling */ \ 1173 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ 1174 UNUSED(tmpreg); \ 1175 } while(0) 1176 1177 #if defined(USART3) 1178 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 1179 __IO uint32_t tmpreg; \ 1180 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ 1181 /* Delay after an RCC peripheral clock enabling */ \ 1182 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ 1183 UNUSED(tmpreg); \ 1184 } while(0) 1185 #endif /* USART3 */ 1186 1187 #if defined(UART4) 1188 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 1189 __IO uint32_t tmpreg; \ 1190 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ 1191 /* Delay after an RCC peripheral clock enabling */ \ 1192 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ 1193 UNUSED(tmpreg); \ 1194 } while(0) 1195 #endif /* UART4 */ 1196 1197 #if defined(UART5) 1198 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 1199 __IO uint32_t tmpreg; \ 1200 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ 1201 /* Delay after an RCC peripheral clock enabling */ \ 1202 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ 1203 UNUSED(tmpreg); \ 1204 } while(0) 1205 #endif /* UART5 */ 1206 1207 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 1208 __IO uint32_t tmpreg; \ 1209 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ 1210 /* Delay after an RCC peripheral clock enabling */ \ 1211 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ 1212 UNUSED(tmpreg); \ 1213 } while(0) 1214 1215 #if defined(I2C2) 1216 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 1217 __IO uint32_t tmpreg; \ 1218 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ 1219 /* Delay after an RCC peripheral clock enabling */ \ 1220 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ 1221 UNUSED(tmpreg); \ 1222 } while(0) 1223 #endif /* I2C2 */ 1224 1225 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 1226 __IO uint32_t tmpreg; \ 1227 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ 1228 /* Delay after an RCC peripheral clock enabling */ \ 1229 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ 1230 UNUSED(tmpreg); \ 1231 } while(0) 1232 1233 #if defined(I2C4) 1234 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \ 1235 __IO uint32_t tmpreg; \ 1236 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ 1237 /* Delay after an RCC peripheral clock enabling */ \ 1238 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ 1239 UNUSED(tmpreg); \ 1240 } while(0) 1241 #endif /* I2C4 */ 1242 1243 #if defined(CRS) 1244 #define __HAL_RCC_CRS_CLK_ENABLE() do { \ 1245 __IO uint32_t tmpreg; \ 1246 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ 1247 /* Delay after an RCC peripheral clock enabling */ \ 1248 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ 1249 UNUSED(tmpreg); \ 1250 } while(0) 1251 #endif /* CRS */ 1252 1253 #if defined(CAN1) 1254 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 1255 __IO uint32_t tmpreg; \ 1256 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \ 1257 /* Delay after an RCC peripheral clock enabling */ \ 1258 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \ 1259 UNUSED(tmpreg); \ 1260 } while(0) 1261 #endif /* CAN1 */ 1262 1263 #if defined(CAN2) 1264 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ 1265 __IO uint32_t tmpreg; \ 1266 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \ 1267 /* Delay after an RCC peripheral clock enabling */ \ 1268 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \ 1269 UNUSED(tmpreg); \ 1270 } while(0) 1271 #endif /* CAN2 */ 1272 1273 #if defined(USB) 1274 #define __HAL_RCC_USB_CLK_ENABLE() do { \ 1275 __IO uint32_t tmpreg; \ 1276 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \ 1277 /* Delay after an RCC peripheral clock enabling */ \ 1278 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \ 1279 UNUSED(tmpreg); \ 1280 } while(0) 1281 #endif /* USB */ 1282 1283 #define __HAL_RCC_PWR_CLK_ENABLE() do { \ 1284 __IO uint32_t tmpreg; \ 1285 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ 1286 /* Delay after an RCC peripheral clock enabling */ \ 1287 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ 1288 UNUSED(tmpreg); \ 1289 } while(0) 1290 1291 #if defined(DAC1) 1292 #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ 1293 __IO uint32_t tmpreg; \ 1294 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \ 1295 /* Delay after an RCC peripheral clock enabling */ \ 1296 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \ 1297 UNUSED(tmpreg); \ 1298 } while(0) 1299 #endif /* DAC1 */ 1300 1301 #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ 1302 __IO uint32_t tmpreg; \ 1303 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \ 1304 /* Delay after an RCC peripheral clock enabling */ \ 1305 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \ 1306 UNUSED(tmpreg); \ 1307 } while(0) 1308 1309 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 1310 __IO uint32_t tmpreg; \ 1311 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ 1312 /* Delay after an RCC peripheral clock enabling */ \ 1313 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ 1314 UNUSED(tmpreg); \ 1315 } while(0) 1316 1317 #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ 1318 __IO uint32_t tmpreg; \ 1319 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ 1320 /* Delay after an RCC peripheral clock enabling */ \ 1321 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ 1322 UNUSED(tmpreg); \ 1323 } while(0) 1324 1325 #if defined(SWPMI1) 1326 #define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \ 1327 __IO uint32_t tmpreg; \ 1328 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \ 1329 /* Delay after an RCC peripheral clock enabling */ \ 1330 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \ 1331 UNUSED(tmpreg); \ 1332 } while(0) 1333 #endif /* SWPMI1 */ 1334 1335 #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ 1336 __IO uint32_t tmpreg; \ 1337 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ 1338 /* Delay after an RCC peripheral clock enabling */ \ 1339 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ 1340 UNUSED(tmpreg); \ 1341 } while(0) 1342 1343 1344 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) 1345 1346 #if defined(TIM3) 1347 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) 1348 #endif /* TIM3 */ 1349 1350 #if defined(TIM4) 1351 #define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) 1352 #endif /* TIM4 */ 1353 1354 #if defined(TIM5) 1355 #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) 1356 #endif /* TIM5 */ 1357 1358 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) 1359 1360 #if defined(TIM7) 1361 #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) 1362 #endif /* TIM7 */ 1363 1364 #if defined(LCD) 1365 #define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); 1366 #endif /* LCD */ 1367 1368 #if defined(RCC_APB1ENR1_RTCAPBEN) 1369 #define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); 1370 #endif /* RCC_APB1ENR1_RTCAPBEN */ 1371 1372 #if defined(SPI2) 1373 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) 1374 #endif /* SPI2 */ 1375 1376 #if defined(SPI3) 1377 #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) 1378 #endif /* SPI3 */ 1379 1380 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) 1381 1382 #if defined(USART3) 1383 #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) 1384 #endif /* USART3 */ 1385 1386 #if defined(UART4) 1387 #define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) 1388 #endif /* UART4 */ 1389 1390 #if defined(UART5) 1391 #define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) 1392 #endif /* UART5 */ 1393 1394 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) 1395 1396 #if defined(I2C2) 1397 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) 1398 #endif /* I2C2 */ 1399 1400 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) 1401 1402 #if defined(I2C4) 1403 #define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) 1404 #endif /* I2C4 */ 1405 1406 #if defined(CRS) 1407 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); 1408 #endif /* CRS */ 1409 1410 #if defined(CAN1) 1411 #define __HAL_RCC_CAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) 1412 #endif /* CAN1 */ 1413 1414 #if defined(CAN2) 1415 #define __HAL_RCC_CAN2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) 1416 #endif /* CAN2 */ 1417 1418 #if defined(USB) 1419 #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); 1420 #endif /* USB */ 1421 1422 #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) 1423 1424 #if defined(DAC1) 1425 #define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) 1426 #endif /* DAC1 */ 1427 1428 #define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) 1429 1430 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) 1431 1432 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) 1433 1434 #if defined(SWPMI1) 1435 #define __HAL_RCC_SWPMI1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) 1436 #endif /* SWPMI1 */ 1437 1438 #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) 1439 1440 /** 1441 * @} 1442 */ 1443 1444 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 1445 * @brief Enable or disable the APB2 peripheral clock. 1446 * @note After reset, the peripheral clock (used for registers read/write access) 1447 * is disabled and the application software has to enable this clock before 1448 * using it. 1449 * @{ 1450 */ 1451 1452 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ 1453 __IO uint32_t tmpreg; \ 1454 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ 1455 /* Delay after an RCC peripheral clock enabling */ \ 1456 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ 1457 UNUSED(tmpreg); \ 1458 } while(0) 1459 1460 #define __HAL_RCC_FIREWALL_CLK_ENABLE() do { \ 1461 __IO uint32_t tmpreg; \ 1462 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \ 1463 /* Delay after an RCC peripheral clock enabling */ \ 1464 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \ 1465 UNUSED(tmpreg); \ 1466 } while(0) 1467 1468 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) 1469 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ 1470 __IO uint32_t tmpreg; \ 1471 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \ 1472 /* Delay after an RCC peripheral clock enabling */ \ 1473 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \ 1474 UNUSED(tmpreg); \ 1475 } while(0) 1476 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ 1477 1478 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 1479 __IO uint32_t tmpreg; \ 1480 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 1481 /* Delay after an RCC peripheral clock enabling */ \ 1482 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 1483 UNUSED(tmpreg); \ 1484 } while(0) 1485 1486 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 1487 __IO uint32_t tmpreg; \ 1488 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 1489 /* Delay after an RCC peripheral clock enabling */ \ 1490 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 1491 UNUSED(tmpreg); \ 1492 } while(0) 1493 1494 #if defined(TIM8) 1495 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 1496 __IO uint32_t tmpreg; \ 1497 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ 1498 /* Delay after an RCC peripheral clock enabling */ \ 1499 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ 1500 UNUSED(tmpreg); \ 1501 } while(0) 1502 #endif /* TIM8 */ 1503 1504 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 1505 __IO uint32_t tmpreg; \ 1506 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 1507 /* Delay after an RCC peripheral clock enabling */ \ 1508 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 1509 UNUSED(tmpreg); \ 1510 } while(0) 1511 1512 1513 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ 1514 __IO uint32_t tmpreg; \ 1515 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ 1516 /* Delay after an RCC peripheral clock enabling */ \ 1517 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ 1518 UNUSED(tmpreg); \ 1519 } while(0) 1520 1521 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ 1522 __IO uint32_t tmpreg; \ 1523 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 1524 /* Delay after an RCC peripheral clock enabling */ \ 1525 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 1526 UNUSED(tmpreg); \ 1527 } while(0) 1528 1529 #if defined(TIM17) 1530 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ 1531 __IO uint32_t tmpreg; \ 1532 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 1533 /* Delay after an RCC peripheral clock enabling */ \ 1534 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 1535 UNUSED(tmpreg); \ 1536 } while(0) 1537 #endif /* TIM17 */ 1538 1539 #if defined(SAI1) 1540 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 1541 __IO uint32_t tmpreg; \ 1542 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 1543 /* Delay after an RCC peripheral clock enabling */ \ 1544 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 1545 UNUSED(tmpreg); \ 1546 } while(0) 1547 #endif /* SAI1 */ 1548 1549 #if defined(SAI2) 1550 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ 1551 __IO uint32_t tmpreg; \ 1552 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ 1553 /* Delay after an RCC peripheral clock enabling */ \ 1554 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ 1555 UNUSED(tmpreg); \ 1556 } while(0) 1557 #endif /* SAI2 */ 1558 1559 #if defined(DFSDM1_Filter0) 1560 #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ 1561 __IO uint32_t tmpreg; \ 1562 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \ 1563 /* Delay after an RCC peripheral clock enabling */ \ 1564 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \ 1565 UNUSED(tmpreg); \ 1566 } while(0) 1567 #endif /* DFSDM1_Filter0 */ 1568 1569 #if defined(LTDC) 1570 #define __HAL_RCC_LTDC_CLK_ENABLE() do { \ 1571 __IO uint32_t tmpreg; \ 1572 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ 1573 /* Delay after an RCC peripheral clock enabling */ \ 1574 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ 1575 UNUSED(tmpreg); \ 1576 } while(0) 1577 #endif /* LTDC */ 1578 1579 #if defined(DSI) 1580 #define __HAL_RCC_DSI_CLK_ENABLE() do { \ 1581 __IO uint32_t tmpreg; \ 1582 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \ 1583 /* Delay after an RCC peripheral clock enabling */ \ 1584 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \ 1585 UNUSED(tmpreg); \ 1586 } while(0) 1587 #endif /* DSI */ 1588 1589 1590 #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) 1591 1592 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) 1593 #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) 1594 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ 1595 1596 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) 1597 1598 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) 1599 1600 #if defined(TIM8) 1601 #define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) 1602 #endif /* TIM8 */ 1603 1604 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) 1605 1606 #define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) 1607 1608 #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) 1609 1610 #if defined(TIM17) 1611 #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) 1612 #endif /* TIM17 */ 1613 1614 #if defined(SAI1) 1615 #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) 1616 #endif /* SAI1 */ 1617 1618 #if defined(SAI2) 1619 #define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) 1620 #endif /* SAI2 */ 1621 1622 #if defined(DFSDM1_Filter0) 1623 #define __HAL_RCC_DFSDM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) 1624 #endif /* DFSDM1_Filter0 */ 1625 1626 #if defined(LTDC) 1627 #define __HAL_RCC_LTDC_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) 1628 #endif /* LTDC */ 1629 1630 #if defined(DSI) 1631 #define __HAL_RCC_DSI_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) 1632 #endif /* DSI */ 1633 1634 /** 1635 * @} 1636 */ 1637 1638 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status 1639 * @brief Check whether the AHB1 peripheral clock is enabled or not. 1640 * @note After reset, the peripheral clock (used for registers read/write access) 1641 * is disabled and the application software has to enable this clock before 1642 * using it. 1643 * @{ 1644 */ 1645 1646 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != 0U) 1647 1648 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != 0U) 1649 1650 #if defined(DMAMUX1) 1651 #define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != 0U) 1652 #endif /* DMAMUX1 */ 1653 1654 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U) 1655 1656 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U) 1657 1658 #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != 0U) 1659 1660 #if defined(DMA2D) 1661 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != 0U) 1662 #endif /* DMA2D */ 1663 1664 #if defined(GFXMMU) 1665 #define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) != 0U) 1666 #endif /* GFXMMU */ 1667 1668 1669 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == 0U) 1670 1671 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == 0U) 1672 1673 #if defined(DMAMUX1) 1674 #define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == 0U) 1675 #endif /* DMAMUX1 */ 1676 1677 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U) 1678 1679 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U) 1680 1681 #define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == 0U) 1682 1683 #if defined(DMA2D) 1684 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == 0U) 1685 #endif /* DMA2D */ 1686 1687 #if defined(GFXMMU) 1688 #define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) == 0U) 1689 #endif /* GFXMMU */ 1690 1691 /** 1692 * @} 1693 */ 1694 1695 /** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status 1696 * @brief Check whether the AHB2 peripheral clock is enabled or not. 1697 * @note After reset, the peripheral clock (used for registers read/write access) 1698 * is disabled and the application software has to enable this clock before 1699 * using it. 1700 * @{ 1701 */ 1702 1703 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U) 1704 1705 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U) 1706 1707 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U) 1708 1709 #if defined(GPIOD) 1710 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U) 1711 #endif /* GPIOD */ 1712 1713 #if defined(GPIOE) 1714 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U) 1715 #endif /* GPIOE */ 1716 1717 #if defined(GPIOF) 1718 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U) 1719 #endif /* GPIOF */ 1720 1721 #if defined(GPIOG) 1722 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U) 1723 #endif /* GPIOG */ 1724 1725 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != 0U) 1726 1727 #if defined(GPIOI) 1728 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) != 0U) 1729 #endif /* GPIOI */ 1730 1731 #if defined(USB_OTG_FS) 1732 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != 0U) 1733 #endif /* USB_OTG_FS */ 1734 1735 #define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != 0U) 1736 1737 #if defined(DCMI) 1738 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) != 0U) 1739 #endif /* DCMI */ 1740 1741 #if defined(PKA) 1742 #define __HAL_RCC_PKA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) != 0U) 1743 #endif /* PKA */ 1744 1745 #if defined(AES) 1746 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U) 1747 #endif /* AES */ 1748 1749 #if defined(HASH) 1750 #define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != 0U) 1751 #endif /* HASH */ 1752 1753 #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U) 1754 1755 #if defined(OCTOSPIM) 1756 #define __HAL_RCC_OSPIM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN) != 0U) 1757 #endif /* OCTOSPIM */ 1758 1759 #if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN) 1760 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN) != 0U) 1761 #endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */ 1762 1763 #if defined(SDMMC2) 1764 #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN) != 0U) 1765 #endif /* SDMMC2 */ 1766 1767 1768 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U) 1769 1770 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U) 1771 1772 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U) 1773 1774 #if defined(GPIOD) 1775 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U) 1776 #endif /* GPIOD */ 1777 1778 #if defined(GPIOE) 1779 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U) 1780 #endif /* GPIOE */ 1781 1782 #if defined(GPIOF) 1783 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U) 1784 #endif /* GPIOF */ 1785 1786 #if defined(GPIOG) 1787 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U) 1788 #endif /* GPIOG */ 1789 1790 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == 0U) 1791 1792 #if defined(GPIOI) 1793 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) == 0U) 1794 #endif /* GPIOI */ 1795 1796 #if defined(USB_OTG_FS) 1797 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == 0U) 1798 #endif /* USB_OTG_FS */ 1799 1800 #define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == 0U) 1801 1802 #if defined(DCMI) 1803 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) == 0U) 1804 #endif /* DCMI */ 1805 1806 #if defined(PKA) 1807 #define __HAL_RCC_PKA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) == 0U) 1808 #endif /* PKA */ 1809 1810 #if defined(AES) 1811 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U) 1812 #endif /* AES */ 1813 1814 #if defined(HASH) 1815 #define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) == 0U) 1816 #endif /* HASH */ 1817 1818 #define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U) 1819 1820 #if defined(OCTOSPIM) 1821 #define __HAL_RCC_OSPIM_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN) == 0U) 1822 #endif /* OCTOSPIM */ 1823 1824 #if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN) 1825 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN) == 0U) 1826 #endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */ 1827 1828 #if defined(SDMMC2) 1829 #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN) == 0U) 1830 #endif /* SDMMC2 */ 1831 1832 /** 1833 * @} 1834 */ 1835 1836 /** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status 1837 * @brief Check whether the AHB3 peripheral clock is enabled or not. 1838 * @note After reset, the peripheral clock (used for registers read/write access) 1839 * is disabled and the application software has to enable this clock before 1840 * using it. 1841 * @{ 1842 */ 1843 1844 #if defined(FMC_BANK1) 1845 #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != 0U) 1846 #endif /* FMC_BANK1 */ 1847 1848 #if defined(QUADSPI) 1849 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != 0U) 1850 #endif /* QUADSPI */ 1851 1852 #if defined(OCTOSPI1) 1853 #define __HAL_RCC_OSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN) != 0U) 1854 #endif /* OCTOSPI1 */ 1855 1856 #if defined(OCTOSPI2) 1857 #define __HAL_RCC_OSPI2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN) != 0U) 1858 #endif /* OCTOSPI2 */ 1859 1860 #if defined(FMC_BANK1) 1861 #define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) 1862 #endif /* FMC_BANK1 */ 1863 1864 #if defined(QUADSPI) 1865 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == 0U) 1866 #endif /* QUADSPI */ 1867 1868 #if defined(OCTOSPI1) 1869 #define __HAL_RCC_OSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN) == 0U) 1870 #endif /* OCTOSPI1 */ 1871 1872 #if defined(OCTOSPI2) 1873 #define __HAL_RCC_OSPI2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN) == 0U) 1874 #endif /* OCTOSPI2 */ 1875 1876 /** 1877 * @} 1878 */ 1879 1880 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status 1881 * @brief Check whether the APB1 peripheral clock is enabled or not. 1882 * @note After reset, the peripheral clock (used for registers read/write access) 1883 * is disabled and the application software has to enable this clock before 1884 * using it. 1885 * @{ 1886 */ 1887 1888 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U) 1889 1890 #if defined(TIM3) 1891 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U) 1892 #endif /* TIM3 */ 1893 1894 #if defined(TIM4) 1895 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U) 1896 #endif /* TIM4 */ 1897 1898 #if defined(TIM5) 1899 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U) 1900 #endif /* TIM5 */ 1901 1902 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U) 1903 1904 #if defined(TIM7) 1905 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U) 1906 #endif /* TIM7 */ 1907 1908 #if defined(LCD) 1909 #define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != 0U) 1910 #endif /* LCD */ 1911 1912 #if defined(RCC_APB1ENR1_RTCAPBEN) 1913 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != 0U) 1914 #endif /* RCC_APB1ENR1_RTCAPBEN */ 1915 1916 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U) 1917 1918 #if defined(SPI2) 1919 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U) 1920 #endif /* SPI2 */ 1921 1922 #if defined(SPI3) 1923 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != 0U) 1924 #endif /* SPI3 */ 1925 1926 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U) 1927 1928 #if defined(USART3) 1929 #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U) 1930 #endif /* USART3 */ 1931 1932 #if defined(UART4) 1933 #define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U) 1934 #endif /* UART4 */ 1935 1936 #if defined(UART5) 1937 #define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U) 1938 #endif /* UART5 */ 1939 1940 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U) 1941 1942 #if defined(I2C2) 1943 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U) 1944 #endif /* I2C2 */ 1945 1946 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != 0U) 1947 1948 #if defined(I2C4) 1949 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U) 1950 #endif /* I2C4 */ 1951 1952 #if defined(CRS) 1953 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U) 1954 #endif /* CRS */ 1955 1956 #if defined(CAN1) 1957 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != 0U) 1958 #endif /* CAN1 */ 1959 1960 #if defined(CAN2) 1961 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) != 0U) 1962 #endif /* CAN2 */ 1963 1964 #if defined(USB) 1965 #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) != 0U) 1966 #endif /* USB */ 1967 1968 #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != 0U) 1969 1970 #if defined(DAC1) 1971 #define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != 0U) 1972 #endif /* DAC1 */ 1973 1974 #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != 0U) 1975 1976 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != 0U) 1977 1978 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != 0U) 1979 1980 #if defined(SWPMI1) 1981 #define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != 0U) 1982 #endif /* SWPMI1 */ 1983 1984 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != 0U) 1985 1986 1987 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U) 1988 1989 #if defined(TIM3) 1990 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U) 1991 #endif /* TIM3 */ 1992 1993 #if defined(TIM4) 1994 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U) 1995 #endif /* TIM4 */ 1996 1997 #if defined(TIM5) 1998 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U) 1999 #endif /* TIM5 */ 2000 2001 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U) 2002 2003 #if defined(TIM7) 2004 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U) 2005 #endif /* TIM7 */ 2006 2007 #if defined(LCD) 2008 #define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == 0U) 2009 #endif /* LCD */ 2010 2011 #if defined(RCC_APB1ENR1_RTCAPBEN) 2012 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == 0U) 2013 #endif /* RCC_APB1ENR1_RTCAPBEN */ 2014 2015 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == 0U) 2016 2017 #if defined(SPI2) 2018 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U) 2019 #endif /* SPI2 */ 2020 2021 #if defined(SPI3) 2022 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == 0U) 2023 #endif /* SPI3 */ 2024 2025 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U) 2026 2027 #if defined(USART3) 2028 #define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U) 2029 #endif /* USART3 */ 2030 2031 #if defined(UART4) 2032 #define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U) 2033 #endif /* UART4 */ 2034 2035 #if defined(UART5) 2036 #define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == 0U) 2037 #endif /* UART5 */ 2038 2039 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U) 2040 2041 #if defined(I2C2) 2042 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U) 2043 #endif /* I2C2 */ 2044 2045 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == 0U) 2046 2047 #if defined(I2C4) 2048 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U) 2049 #endif /* I2C4 */ 2050 2051 #if defined(CRS) 2052 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U) 2053 #endif /* CRS */ 2054 2055 #if defined(CAN1) 2056 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == 0U) 2057 #endif /* CAN1 */ 2058 2059 #if defined(CAN2) 2060 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) == 0U) 2061 #endif /* CAN2 */ 2062 2063 #if defined(USB) 2064 #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) == 0U) 2065 #endif /* USB */ 2066 2067 #define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == 0U) 2068 2069 #if defined(DAC1) 2070 #define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == 0U) 2071 #endif /* DAC1 */ 2072 2073 #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == 0U) 2074 2075 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == 0U) 2076 2077 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == 0U) 2078 2079 #if defined(SWPMI1) 2080 #define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == 0U) 2081 #endif /* SWPMI1 */ 2082 2083 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == 0U) 2084 2085 /** 2086 * @} 2087 */ 2088 2089 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status 2090 * @brief Check whether the APB2 peripheral clock is enabled or not. 2091 * @note After reset, the peripheral clock (used for registers read/write access) 2092 * is disabled and the application software has to enable this clock before 2093 * using it. 2094 * @{ 2095 */ 2096 2097 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U) 2098 2099 #define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != 0U) 2100 2101 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) 2102 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != 0U) 2103 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ 2104 2105 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U) 2106 2107 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U) 2108 2109 #if defined(TIM8) 2110 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U) 2111 #endif /* TIM8 */ 2112 2113 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U) 2114 2115 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U) 2116 2117 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U) 2118 2119 #if defined(TIM17) 2120 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U) 2121 #endif /* TIM17 */ 2122 2123 #if defined(SAI1) 2124 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U) 2125 #endif /* SAI1 */ 2126 2127 #if defined(SAI2) 2128 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U) 2129 #endif /* SAI2 */ 2130 2131 #if defined(DFSDM1_Filter0) 2132 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != 0U) 2133 #endif /* DFSDM1_Filter0 */ 2134 2135 #if defined(LTDC) 2136 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) != 0U) 2137 #endif /* LTDC */ 2138 2139 #if defined(DSI) 2140 #define __HAL_RCC_DSI_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) != 0U) 2141 #endif /* DSI */ 2142 2143 2144 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U) 2145 2146 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) 2147 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == 0U) 2148 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ 2149 2150 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U) 2151 2152 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U) 2153 2154 #if defined(TIM8) 2155 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U) 2156 #endif /* TIM8 */ 2157 2158 #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U) 2159 2160 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U) 2161 2162 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U) 2163 2164 #if defined(TIM17) 2165 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U) 2166 #endif /* TIM17 */ 2167 2168 #if defined(SAI1) 2169 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U) 2170 #endif /* SAI1 */ 2171 2172 #if defined(SAI2) 2173 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == 0U) 2174 #endif /* SAI2 */ 2175 2176 #if defined(DFSDM1_Filter0) 2177 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == 0U) 2178 #endif /* DFSDM1_Filter0 */ 2179 2180 #if defined(LTDC) 2181 #define __HAL_RCC_LTDC_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) == 0U) 2182 #endif /* LTDC */ 2183 2184 #if defined(DSI) 2185 #define __HAL_RCC_DSI_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) == 0U) 2186 #endif /* DSI */ 2187 2188 /** 2189 * @} 2190 */ 2191 2192 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset 2193 * @brief Force or release AHB1 peripheral reset. 2194 * @{ 2195 */ 2196 #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFUL) 2197 2198 #define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST) 2199 2200 #define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) 2201 2202 #if defined(DMAMUX1) 2203 #define __HAL_RCC_DMAMUX1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST) 2204 #endif /* DMAMUX1 */ 2205 2206 #define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) 2207 2208 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 2209 2210 #define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) 2211 2212 #if defined(DMA2D) 2213 #define __HAL_RCC_DMA2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) 2214 #endif /* DMA2D */ 2215 2216 #if defined(GFXMMU) 2217 #define __HAL_RCC_GFXMMU_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST) 2218 #endif /* GFXMMU */ 2219 2220 2221 #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000UL) 2222 2223 #define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST) 2224 2225 #define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) 2226 2227 #if defined(DMAMUX1) 2228 #define __HAL_RCC_DMAMUX1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST) 2229 #endif /* DMAMUX1 */ 2230 2231 #define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) 2232 2233 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 2234 2235 #define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) 2236 2237 #if defined(DMA2D) 2238 #define __HAL_RCC_DMA2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) 2239 #endif /* DMA2D */ 2240 2241 #if defined(GFXMMU) 2242 #define __HAL_RCC_GFXMMU_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST) 2243 #endif /* GFXMMU */ 2244 2245 /** 2246 * @} 2247 */ 2248 2249 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset 2250 * @brief Force or release AHB2 peripheral reset. 2251 * @{ 2252 */ 2253 #define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFUL) 2254 2255 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) 2256 2257 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) 2258 2259 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) 2260 2261 #if defined(GPIOD) 2262 #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) 2263 #endif /* GPIOD */ 2264 2265 #if defined(GPIOE) 2266 #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) 2267 #endif /* GPIOE */ 2268 2269 #if defined(GPIOF) 2270 #define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) 2271 #endif /* GPIOF */ 2272 2273 #if defined(GPIOG) 2274 #define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) 2275 #endif /* GPIOG */ 2276 2277 #define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) 2278 2279 #if defined(GPIOI) 2280 #define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST) 2281 #endif /* GPIOI */ 2282 2283 #if defined(USB_OTG_FS) 2284 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST) 2285 #endif /* USB_OTG_FS */ 2286 2287 #define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST) 2288 2289 #if defined(DCMI) 2290 #define __HAL_RCC_DCMI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST) 2291 #endif /* DCMI */ 2292 2293 #if defined(PKA) 2294 #define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST) 2295 #endif /* PKA */ 2296 2297 #if defined(AES) 2298 #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) 2299 #endif /* AES */ 2300 2301 #if defined(HASH) 2302 #define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) 2303 #endif /* HASH */ 2304 2305 #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) 2306 2307 #if defined(OCTOSPIM) 2308 #define __HAL_RCC_OSPIM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST) 2309 #endif /* OCTOSPIM */ 2310 2311 #if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST) 2312 #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST) 2313 #endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */ 2314 2315 #if defined(SDMMC2) 2316 #define __HAL_RCC_SDMMC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC2RST) 2317 #endif /* SDMMC2 */ 2318 2319 2320 #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000UL) 2321 2322 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) 2323 2324 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) 2325 2326 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) 2327 2328 #if defined(GPIOD) 2329 #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) 2330 #endif /* GPIOD */ 2331 2332 #if defined(GPIOE) 2333 #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) 2334 #endif /* GPIOE */ 2335 2336 #if defined(GPIOF) 2337 #define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) 2338 #endif /* GPIOF */ 2339 2340 #if defined(GPIOG) 2341 #define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) 2342 #endif /* GPIOG */ 2343 2344 #define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) 2345 2346 #if defined(GPIOI) 2347 #define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST) 2348 #endif /* GPIOI */ 2349 2350 #if defined(USB_OTG_FS) 2351 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST) 2352 #endif /* USB_OTG_FS */ 2353 2354 #define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST) 2355 2356 #if defined(DCMI) 2357 #define __HAL_RCC_DCMI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST) 2358 #endif /* DCMI */ 2359 2360 #if defined(PKA) 2361 #define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST) 2362 #endif /* PKA */ 2363 2364 #if defined(AES) 2365 #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) 2366 #endif /* AES */ 2367 2368 #if defined(HASH) 2369 #define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) 2370 #endif /* HASH */ 2371 2372 #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) 2373 2374 #if defined(OCTOSPIM) 2375 #define __HAL_RCC_OSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST) 2376 #endif /* OCTOSPIM */ 2377 2378 #if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST) 2379 #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST) 2380 #endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */ 2381 2382 #if defined(SDMMC2) 2383 #define __HAL_RCC_SDMMC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC2RST) 2384 #endif /* SDMMC2 */ 2385 2386 /** 2387 * @} 2388 */ 2389 2390 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset 2391 * @brief Force or release AHB3 peripheral reset. 2392 * @{ 2393 */ 2394 #define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFUL) 2395 2396 #if defined(FMC_BANK1) 2397 #define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST) 2398 #endif /* FMC_BANK1 */ 2399 2400 #if defined(QUADSPI) 2401 #define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST) 2402 #endif /* QUADSPI */ 2403 2404 #if defined(OCTOSPI1) 2405 #define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST) 2406 #endif /* OCTOSPI1 */ 2407 2408 #if defined(OCTOSPI2) 2409 #define __HAL_RCC_OSPI2_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST) 2410 #endif /* OCTOSPI2 */ 2411 2412 #define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000UL) 2413 2414 #if defined(FMC_BANK1) 2415 #define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST) 2416 #endif /* FMC_BANK1 */ 2417 2418 #if defined(QUADSPI) 2419 #define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST) 2420 #endif /* QUADSPI */ 2421 2422 #if defined(OCTOSPI1) 2423 #define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST) 2424 #endif /* OCTOSPI1 */ 2425 2426 #if defined(OCTOSPI2) 2427 #define __HAL_RCC_OSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST) 2428 #endif /* OCTOSPI2 */ 2429 2430 /** 2431 * @} 2432 */ 2433 2434 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset 2435 * @brief Force or release APB1 peripheral reset. 2436 * @{ 2437 */ 2438 #define __HAL_RCC_APB1_FORCE_RESET() do { \ 2439 WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFUL); \ 2440 WRITE_REG(RCC->APB1RSTR2, 0xFFFFFFFFUL); \ 2441 } while(0) 2442 2443 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) 2444 2445 #if defined(TIM3) 2446 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) 2447 #endif /* TIM3 */ 2448 2449 #if defined(TIM4) 2450 #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) 2451 #endif /* TIM4 */ 2452 2453 #if defined(TIM5) 2454 #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) 2455 #endif /* TIM5 */ 2456 2457 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) 2458 2459 #if defined(TIM7) 2460 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) 2461 #endif /* TIM7 */ 2462 2463 #if defined(LCD) 2464 #define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST) 2465 #endif /* LCD */ 2466 2467 #if defined(SPI2) 2468 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) 2469 #endif /* SPI2 */ 2470 2471 #if defined(SPI3) 2472 #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) 2473 #endif /* SPI3 */ 2474 2475 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) 2476 2477 #if defined(USART3) 2478 #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) 2479 #endif /* USART3 */ 2480 2481 #if defined(UART4) 2482 #define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) 2483 #endif /* UART4 */ 2484 2485 #if defined(UART5) 2486 #define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) 2487 #endif /* UART5 */ 2488 2489 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) 2490 2491 #if defined(I2C2) 2492 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) 2493 #endif /* I2C2 */ 2494 2495 #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) 2496 2497 #if defined(I2C4) 2498 #define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) 2499 #endif /* I2C4 */ 2500 2501 #if defined(CRS) 2502 #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) 2503 #endif /* CRS */ 2504 2505 #if defined(CAN1) 2506 #define __HAL_RCC_CAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST) 2507 #endif /* CAN1 */ 2508 2509 #if defined(CAN2) 2510 #define __HAL_RCC_CAN2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST) 2511 #endif /* CAN2 */ 2512 2513 #if defined(USB) 2514 #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST) 2515 #endif /* USB */ 2516 2517 #define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) 2518 2519 #if defined(DAC1) 2520 #define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST) 2521 #endif /* DAC1 */ 2522 2523 #define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST) 2524 2525 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) 2526 2527 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST) 2528 2529 #if defined(SWPMI1) 2530 #define __HAL_RCC_SWPMI1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST) 2531 #endif /* SWPMI1 */ 2532 2533 #define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) 2534 2535 2536 #define __HAL_RCC_APB1_RELEASE_RESET() do { \ 2537 WRITE_REG(RCC->APB1RSTR1, 0x00000000UL); \ 2538 WRITE_REG(RCC->APB1RSTR2, 0x00000000UL); \ 2539 } while(0) 2540 2541 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) 2542 2543 #if defined(TIM3) 2544 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) 2545 #endif /* TIM3 */ 2546 2547 #if defined(TIM4) 2548 #define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) 2549 #endif /* TIM4 */ 2550 2551 #if defined(TIM5) 2552 #define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) 2553 #endif /* TIM5 */ 2554 2555 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) 2556 2557 #if defined(TIM7) 2558 #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) 2559 #endif /* TIM7 */ 2560 2561 #if defined(LCD) 2562 #define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST) 2563 #endif /* LCD */ 2564 2565 #if defined(SPI2) 2566 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) 2567 #endif /* SPI2 */ 2568 2569 #if defined(SPI3) 2570 #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) 2571 #endif /* SPI3 */ 2572 2573 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) 2574 2575 #if defined(USART3) 2576 #define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) 2577 #endif /* USART3 */ 2578 2579 #if defined(UART4) 2580 #define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) 2581 #endif /* UART4 */ 2582 2583 #if defined(UART5) 2584 #define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) 2585 #endif /* UART5 */ 2586 2587 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) 2588 2589 #if defined(I2C2) 2590 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) 2591 #endif /* I2C2 */ 2592 2593 #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) 2594 2595 #if defined(I2C4) 2596 #define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) 2597 #endif /* I2C4 */ 2598 2599 #if defined(CRS) 2600 #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) 2601 #endif /* CRS */ 2602 2603 #if defined(CAN1) 2604 #define __HAL_RCC_CAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST) 2605 #endif /* CAN1 */ 2606 2607 #if defined(CAN2) 2608 #define __HAL_RCC_CAN2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST) 2609 #endif /* CAN2 */ 2610 2611 #if defined(USB) 2612 #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST) 2613 #endif /* USB */ 2614 2615 #define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) 2616 2617 #if defined(DAC1) 2618 #define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST) 2619 #endif /* DAC1 */ 2620 2621 #define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST) 2622 2623 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) 2624 2625 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST) 2626 2627 #if defined(SWPMI1) 2628 #define __HAL_RCC_SWPMI1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST) 2629 #endif /* SWPMI1 */ 2630 2631 #define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) 2632 2633 /** 2634 * @} 2635 */ 2636 2637 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset 2638 * @brief Force or release APB2 peripheral reset. 2639 * @{ 2640 */ 2641 #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFUL) 2642 2643 #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) 2644 2645 #if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST) 2646 #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST) 2647 #endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */ 2648 2649 #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 2650 2651 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 2652 2653 #if defined(TIM8) 2654 #define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) 2655 #endif /* TIM8 */ 2656 2657 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 2658 2659 #define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 2660 2661 #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 2662 2663 #if defined(TIM17) 2664 #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 2665 #endif /* TIM17 */ 2666 2667 #if defined(SAI1) 2668 #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 2669 #endif /* SAI1 */ 2670 2671 #if defined(SAI2) 2672 #define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) 2673 #endif /* SAI2 */ 2674 2675 #if defined(DFSDM1_Filter0) 2676 #define __HAL_RCC_DFSDM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST) 2677 #endif /* DFSDM1_Filter0 */ 2678 2679 #if defined(LTDC) 2680 #define __HAL_RCC_LTDC_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) 2681 #endif /* LTDC */ 2682 2683 #if defined(DSI) 2684 #define __HAL_RCC_DSI_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST) 2685 #endif /* DSI */ 2686 2687 2688 #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000UL) 2689 2690 #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) 2691 2692 #if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST) 2693 #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST) 2694 #endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */ 2695 2696 #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 2697 2698 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 2699 2700 #if defined(TIM8) 2701 #define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) 2702 #endif /* TIM8 */ 2703 2704 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 2705 2706 #define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 2707 2708 #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 2709 2710 #if defined(TIM17) 2711 #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 2712 #endif /* TIM17 */ 2713 2714 #if defined(SAI1) 2715 #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 2716 #endif /* SAI1 */ 2717 2718 #if defined(SAI2) 2719 #define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) 2720 #endif /* SAI2 */ 2721 2722 #if defined(DFSDM1_Filter0) 2723 #define __HAL_RCC_DFSDM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST) 2724 #endif /* DFSDM1_Filter0 */ 2725 2726 #if defined(LTDC) 2727 #define __HAL_RCC_LTDC_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) 2728 #endif /* LTDC */ 2729 2730 #if defined(DSI) 2731 #define __HAL_RCC_DSI_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST) 2732 #endif /* DSI */ 2733 2734 /** 2735 * @} 2736 */ 2737 2738 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable 2739 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 2740 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2741 * power consumption. 2742 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2743 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2744 * @{ 2745 */ 2746 2747 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) 2748 2749 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) 2750 2751 #if defined(DMAMUX1) 2752 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) 2753 #endif /* DMAMUX1 */ 2754 2755 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) 2756 2757 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) 2758 2759 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) 2760 2761 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) 2762 2763 #if defined(DMA2D) 2764 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) 2765 #endif /* DMA2D */ 2766 2767 #if defined(GFXMMU) 2768 #define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) 2769 #endif /* GFXMMU */ 2770 2771 2772 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) 2773 2774 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) 2775 2776 #if defined(DMAMUX1) 2777 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) 2778 #endif /* DMAMUX1 */ 2779 2780 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) 2781 2782 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) 2783 2784 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) 2785 2786 #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) 2787 2788 #if defined(DMA2D) 2789 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) 2790 #endif /* DMA2D */ 2791 2792 #if defined(GFXMMU) 2793 #define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) 2794 #endif /* GFXMMU */ 2795 2796 /** 2797 * @} 2798 */ 2799 2800 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable 2801 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 2802 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2803 * power consumption. 2804 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2805 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2806 * @{ 2807 */ 2808 2809 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) 2810 2811 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) 2812 2813 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) 2814 2815 #if defined(GPIOD) 2816 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) 2817 #endif /* GPIOD */ 2818 2819 #if defined(GPIOE) 2820 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) 2821 #endif /* GPIOE */ 2822 2823 #if defined(GPIOF) 2824 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) 2825 #endif /* GPIOF */ 2826 2827 #if defined(GPIOG) 2828 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) 2829 #endif /* GPIOG */ 2830 2831 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) 2832 2833 #if defined(GPIOI) 2834 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) 2835 #endif /* GPIOI */ 2836 2837 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) 2838 2839 #if defined(SRAM3) 2840 #define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) 2841 #endif /* SRAM3 */ 2842 2843 #if defined(USB_OTG_FS) 2844 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) 2845 #endif /* USB_OTG_FS */ 2846 2847 #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) 2848 2849 #if defined(DCMI) 2850 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) 2851 #endif /* DCMI */ 2852 2853 #if defined(PKA) 2854 #define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) 2855 #endif /* PKA */ 2856 2857 #if defined(AES) 2858 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) 2859 #endif /* AES */ 2860 2861 #if defined(HASH) 2862 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) 2863 #endif /* HASH */ 2864 2865 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) 2866 2867 #if defined(OCTOSPIM) 2868 #define __HAL_RCC_OSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) 2869 #endif /* OCTOSPIM */ 2870 2871 #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) 2872 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) 2873 #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ 2874 2875 #if defined(SDMMC2) 2876 #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC2SMEN) 2877 #endif /* SDMMC2 */ 2878 2879 2880 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) 2881 2882 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) 2883 2884 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) 2885 2886 #if defined(GPIOD) 2887 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) 2888 #endif /* GPIOD */ 2889 2890 #if defined(GPIOE) 2891 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) 2892 #endif /* GPIOE */ 2893 2894 #if defined(GPIOF) 2895 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) 2896 #endif /* GPIOF */ 2897 2898 #if defined(GPIOG) 2899 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) 2900 #endif /* GPIOG */ 2901 2902 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) 2903 2904 #if defined(GPIOI) 2905 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) 2906 #endif /* GPIOI */ 2907 2908 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) 2909 2910 #if defined(SRAM3) 2911 #define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) 2912 #endif /* SRAM3 */ 2913 2914 #if defined(USB_OTG_FS) 2915 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) 2916 #endif /* USB_OTG_FS */ 2917 2918 #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) 2919 2920 #if defined(DCMI) 2921 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) 2922 #endif /* DCMI */ 2923 2924 #if defined(PKA) 2925 #define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) 2926 #endif /* PKA */ 2927 2928 #if defined(AES) 2929 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) 2930 #endif /* AES */ 2931 2932 #if defined(HASH) 2933 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) 2934 #endif /* HASH */ 2935 2936 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) 2937 2938 #if defined(OCTOSPIM) 2939 #define __HAL_RCC_OSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) 2940 #endif /* OCTOSPIM */ 2941 2942 #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) 2943 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) 2944 #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ 2945 2946 #if defined(SDMMC2) 2947 #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC2SMEN) 2948 #endif /* SDMMC2 */ 2949 2950 /** 2951 * @} 2952 */ 2953 2954 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable 2955 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 2956 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2957 * power consumption. 2958 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2959 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2960 * @{ 2961 */ 2962 2963 #if defined(QUADSPI) 2964 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) 2965 #endif /* QUADSPI */ 2966 2967 #if defined(OCTOSPI1) 2968 #define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) 2969 #endif /* OCTOSPI1 */ 2970 2971 #if defined(OCTOSPI2) 2972 #define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) 2973 #endif /* OCTOSPI2 */ 2974 2975 #if defined(FMC_BANK1) 2976 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) 2977 #endif /* FMC_BANK1 */ 2978 2979 #if defined(QUADSPI) 2980 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) 2981 #endif /* QUADSPI */ 2982 2983 #if defined(OCTOSPI1) 2984 #define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) 2985 #endif /* OCTOSPI1 */ 2986 2987 #if defined(OCTOSPI2) 2988 #define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) 2989 #endif /* OCTOSPI2 */ 2990 2991 #if defined(FMC_BANK1) 2992 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) 2993 #endif /* FMC_BANK1 */ 2994 2995 /** 2996 * @} 2997 */ 2998 2999 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable 3000 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 3001 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3002 * power consumption. 3003 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3004 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3005 * @{ 3006 */ 3007 3008 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) 3009 3010 #if defined(TIM3) 3011 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) 3012 #endif /* TIM3 */ 3013 3014 #if defined(TIM4) 3015 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) 3016 #endif /* TIM4 */ 3017 3018 #if defined(TIM5) 3019 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) 3020 #endif /* TIM5 */ 3021 3022 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) 3023 3024 #if defined(TIM7) 3025 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) 3026 #endif /* TIM7 */ 3027 3028 #if defined(LCD) 3029 #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) 3030 #endif /* LCD */ 3031 3032 #if defined(RCC_APB1SMENR1_RTCAPBSMEN) 3033 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) 3034 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */ 3035 3036 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) 3037 3038 #if defined(SPI2) 3039 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) 3040 #endif /* SPI2 */ 3041 3042 #if defined(SPI3) 3043 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) 3044 #endif /* SPI3 */ 3045 3046 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) 3047 3048 #if defined(USART3) 3049 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) 3050 #endif /* USART3 */ 3051 3052 #if defined(UART4) 3053 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) 3054 #endif /* UART4 */ 3055 3056 #if defined(UART5) 3057 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) 3058 #endif /* UART5 */ 3059 3060 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) 3061 3062 #if defined(I2C2) 3063 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) 3064 #endif /* I2C2 */ 3065 3066 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) 3067 3068 #if defined(I2C4) 3069 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) 3070 #endif /* I2C4 */ 3071 3072 #if defined(CRS) 3073 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) 3074 #endif /* CRS */ 3075 3076 #if defined(CAN1) 3077 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) 3078 #endif /* CAN1 */ 3079 3080 #if defined(CAN2) 3081 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) 3082 #endif /* CAN2 */ 3083 3084 #if defined(USB) 3085 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) 3086 #endif /* USB */ 3087 3088 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) 3089 3090 #if defined(DAC1) 3091 #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) 3092 #endif /* DAC1 */ 3093 3094 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) 3095 3096 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) 3097 3098 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) 3099 3100 #if defined(SWPMI1) 3101 #define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) 3102 #endif /* SWPMI1 */ 3103 3104 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) 3105 3106 3107 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) 3108 3109 #if defined(TIM3) 3110 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) 3111 #endif /* TIM3 */ 3112 3113 #if defined(TIM4) 3114 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) 3115 #endif /* TIM4 */ 3116 3117 #if defined(TIM5) 3118 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) 3119 #endif /* TIM5 */ 3120 3121 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) 3122 3123 #if defined(TIM7) 3124 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) 3125 #endif /* TIM7 */ 3126 3127 #if defined(LCD) 3128 #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) 3129 #endif /* LCD */ 3130 3131 #if defined(RCC_APB1SMENR1_RTCAPBSMEN) 3132 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) 3133 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */ 3134 3135 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) 3136 3137 #if defined(SPI2) 3138 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) 3139 #endif /* SPI2 */ 3140 3141 #if defined(SPI3) 3142 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) 3143 #endif /* SPI3 */ 3144 3145 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) 3146 3147 #if defined(USART3) 3148 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) 3149 #endif /* USART3 */ 3150 3151 #if defined(UART4) 3152 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) 3153 #endif /* UART4 */ 3154 3155 #if defined(UART5) 3156 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) 3157 #endif /* UART5 */ 3158 3159 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) 3160 3161 #if defined(I2C2) 3162 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) 3163 #endif /* I2C2 */ 3164 3165 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) 3166 3167 #if defined(I2C4) 3168 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) 3169 #endif /* I2C4 */ 3170 3171 #if defined(CRS) 3172 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) 3173 #endif /* CRS */ 3174 3175 #if defined(CAN1) 3176 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) 3177 #endif /* CAN1 */ 3178 3179 #if defined(CAN2) 3180 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) 3181 #endif /* CAN2 */ 3182 3183 #if defined(USB) 3184 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) 3185 #endif /* USB */ 3186 3187 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) 3188 3189 #if defined(DAC1) 3190 #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) 3191 #endif /* DAC1 */ 3192 3193 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) 3194 3195 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) 3196 3197 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) 3198 3199 #if defined(SWPMI1) 3200 #define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) 3201 #endif /* SWPMI1 */ 3202 3203 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) 3204 3205 /** 3206 * @} 3207 */ 3208 3209 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable 3210 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 3211 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3212 * power consumption. 3213 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3214 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3215 * @{ 3216 */ 3217 3218 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) 3219 3220 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) 3221 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) 3222 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ 3223 3224 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) 3225 3226 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) 3227 3228 #if defined(TIM8) 3229 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) 3230 #endif /* TIM8 */ 3231 3232 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) 3233 3234 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) 3235 3236 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) 3237 3238 #if defined(TIM17) 3239 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) 3240 #endif /* TIM17 */ 3241 3242 #if defined(SAI1) 3243 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) 3244 #endif /* SAI1 */ 3245 3246 #if defined(SAI2) 3247 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) 3248 #endif /* SAI2 */ 3249 3250 #if defined(DFSDM1_Filter0) 3251 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) 3252 #endif /* DFSDM1_Filter0 */ 3253 3254 #if defined(LTDC) 3255 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) 3256 #endif /* LTDC */ 3257 3258 #if defined(DSI) 3259 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) 3260 #endif /* DSI */ 3261 3262 3263 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) 3264 3265 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) 3266 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) 3267 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ 3268 3269 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) 3270 3271 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) 3272 3273 #if defined(TIM8) 3274 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) 3275 #endif /* TIM8 */ 3276 3277 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) 3278 3279 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) 3280 3281 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) 3282 3283 #if defined(TIM17) 3284 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) 3285 #endif /* TIM17 */ 3286 3287 #if defined(SAI1) 3288 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) 3289 #endif /* SAI1 */ 3290 3291 #if defined(SAI2) 3292 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) 3293 #endif /* SAI2 */ 3294 3295 #if defined(DFSDM1_Filter0) 3296 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) 3297 #endif /* DFSDM1_Filter0 */ 3298 3299 #if defined(LTDC) 3300 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) 3301 #endif /* LTDC */ 3302 3303 #if defined(DSI) 3304 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) 3305 #endif /* DSI */ 3306 3307 /** 3308 * @} 3309 */ 3310 3311 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status 3312 * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not. 3313 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3314 * power consumption. 3315 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3316 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3317 * @{ 3318 */ 3319 3320 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != 0U) 3321 3322 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != 0U) 3323 3324 #if defined(DMAMUX1) 3325 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != 0U) 3326 #endif /* DMAMUX1 */ 3327 3328 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U) 3329 3330 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != 0U) 3331 3332 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U) 3333 3334 #define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != 0U) 3335 3336 #if defined(DMA2D) 3337 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) != 0U) 3338 #endif /* DMA2D */ 3339 3340 #if defined(GFXMMU) 3341 #define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) != 0U) 3342 #endif /* GFXMMU */ 3343 3344 3345 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == 0U) 3346 3347 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == 0U) 3348 3349 #if defined(DMAMUX1) 3350 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == 0U) 3351 #endif /* DMAMUX1 */ 3352 3353 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == 0U) 3354 3355 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == 0U) 3356 3357 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == 0U) 3358 3359 #define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == 0U) 3360 3361 #if defined(DMA2D) 3362 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) == 0U) 3363 #endif /* DMA2D */ 3364 3365 #if defined(GFXMMU) 3366 #define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) == 0U) 3367 #endif /* GFXMMU */ 3368 3369 /** 3370 * @} 3371 */ 3372 3373 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status 3374 * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 3375 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3376 * power consumption. 3377 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3378 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3379 * @{ 3380 */ 3381 3382 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != 0U) 3383 3384 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != 0U) 3385 3386 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != 0U) 3387 3388 #if defined(GPIOD) 3389 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != 0U) 3390 #endif /* GPIOD */ 3391 3392 #if defined(GPIOE) 3393 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != 0U) 3394 #endif /* GPIOE */ 3395 3396 #if defined(GPIOF) 3397 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != 0U) 3398 #endif /* GPIOF */ 3399 3400 #if defined(GPIOG) 3401 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != 0U) 3402 #endif /* GPIOG */ 3403 3404 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != 0U) 3405 3406 #if defined(GPIOI) 3407 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) != 0U) 3408 #endif /* GPIOI */ 3409 3410 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U) 3411 3412 #if defined(SRAM3) 3413 #define __HAL_RCC_SRAM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) != 0U) 3414 #endif /* SRAM3 */ 3415 3416 #if defined(USB_OTG_FS) 3417 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != 0U) 3418 #endif /* USB_OTG_FS */ 3419 3420 #define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != 0U) 3421 3422 #if defined(DCMI) 3423 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) != 0U) 3424 #endif /* DCMI */ 3425 3426 #if defined(PKA) 3427 #define __HAL_RCC_PKA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) != 0U) 3428 #endif /* PKA */ 3429 3430 #if defined(AES) 3431 #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != 0U) 3432 #endif /* AES */ 3433 3434 #if defined(HASH) 3435 #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) != 0U) 3436 #endif /* HASH */ 3437 3438 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U) 3439 3440 #if defined(OCTOSPIM) 3441 #define __HAL_RCC_OSPIM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) != 0U) 3442 #endif /* OCTOSPIM */ 3443 3444 #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) 3445 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) != 0U) 3446 #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ 3447 3448 #if defined(SDMMC2) 3449 #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC2SMEN) != 0U) 3450 #endif /* SDMMC2 */ 3451 3452 3453 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == 0U) 3454 3455 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == 0U) 3456 3457 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == 0U) 3458 3459 #if defined(GPIOD) 3460 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == 0U) 3461 #endif /* GPIOD */ 3462 3463 #if defined(GPIOE) 3464 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == 0U) 3465 #endif /* GPIOE */ 3466 3467 #if defined(GPIOF) 3468 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == 0U) 3469 #endif /* GPIOF */ 3470 3471 #if defined(GPIOG) 3472 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == 0U) 3473 #endif /* GPIOG */ 3474 3475 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == 0U) 3476 3477 #if defined(GPIOI) 3478 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) == 0U) 3479 #endif /* GPIOI */ 3480 3481 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == 0U) 3482 3483 #if defined(SRAM3) 3484 #define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) == 0U) 3485 #endif /* SRAM3 */ 3486 3487 #if defined(USB_OTG_FS) 3488 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == 0U) 3489 #endif /* USB_OTG_FS */ 3490 3491 #define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == 0U) 3492 3493 #if defined(DCMI) 3494 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) == 0U) 3495 #endif /* DCMI */ 3496 3497 #if defined(PKA) 3498 #define __HAL_RCC_PKA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) == 0U) 3499 #endif /* PKA */ 3500 3501 #if defined(AES) 3502 #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == 0U) 3503 #endif /* AES */ 3504 3505 #if defined(HASH) 3506 #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) == 0U) 3507 #endif /* HASH */ 3508 3509 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == 0U) 3510 3511 #if defined(OCTOSPIM) 3512 #define __HAL_RCC_OSPIM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) == 0U) 3513 #endif /* OCTOSPIM */ 3514 3515 #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) 3516 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) == 0U) 3517 #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ 3518 3519 #if defined(SDMMC2) 3520 #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC2SMEN) == 0U) 3521 #endif /* SDMMC2 */ 3522 3523 /** 3524 * @} 3525 */ 3526 3527 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status 3528 * @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not. 3529 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3530 * power consumption. 3531 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3532 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3533 * @{ 3534 */ 3535 3536 #if defined(QUADSPI) 3537 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != 0U) 3538 #endif /* QUADSPI */ 3539 3540 #if defined(OCTOSPI1) 3541 #define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) != 0U) 3542 #endif /* OCTOSPI1 */ 3543 3544 #if defined(OCTOSPI2) 3545 #define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) != 0U) 3546 #endif /* OCTOSPI2 */ 3547 3548 #if defined(FMC_BANK1) 3549 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != 0U) 3550 #endif /* FMC_BANK1 */ 3551 3552 3553 #if defined(QUADSPI) 3554 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == 0U) 3555 #endif /* QUADSPI */ 3556 3557 #if defined(OCTOSPI1) 3558 #define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) == 0U) 3559 #endif /* OCTOSPI1 */ 3560 3561 #if defined(OCTOSPI2) 3562 #define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) == 0U) 3563 #endif /* OCTOSPI2 */ 3564 3565 #if defined(FMC_BANK1) 3566 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == 0U) 3567 #endif /* FMC_BANK1 */ 3568 3569 /** 3570 * @} 3571 */ 3572 3573 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status 3574 * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not. 3575 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3576 * power consumption. 3577 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3578 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3579 * @{ 3580 */ 3581 3582 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != 0U) 3583 3584 #if defined(TIM3) 3585 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U) 3586 #endif /* TIM3 */ 3587 3588 #if defined(TIM4) 3589 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != 0U) 3590 #endif /* TIM4 */ 3591 3592 #if defined(TIM5) 3593 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != 0U) 3594 #endif /* TIM5 */ 3595 3596 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != 0U) 3597 3598 #if defined(TIM7) 3599 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != 0U) 3600 #endif /* TIM7 */ 3601 3602 #if defined(LCD) 3603 #define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != 0U) 3604 #endif /* LCD */ 3605 3606 #if defined(RCC_APB1SMENR1_RTCAPBSMEN) 3607 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != 0U) 3608 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */ 3609 3610 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U) 3611 3612 #if defined(SPI2) 3613 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != 0U) 3614 #endif /* SPI2 */ 3615 3616 #if defined(SPI3) 3617 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != 0U) 3618 #endif /* SPI3 */ 3619 3620 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U) 3621 3622 #if defined(USART3) 3623 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != 0U) 3624 #endif /* USART3 */ 3625 3626 #if defined(UART4) 3627 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != 0U) 3628 #endif /* UART4 */ 3629 3630 #if defined(UART5) 3631 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != 0U) 3632 #endif /* UART5 */ 3633 3634 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U) 3635 3636 #if defined(I2C2) 3637 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != 0U) 3638 #endif /* I2C2 */ 3639 3640 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != 0U) 3641 3642 #if defined(I2C4) 3643 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != 0U) 3644 #endif /* I2C4 */ 3645 3646 #if defined(CRS) 3647 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != 0U) 3648 #endif /* CRS */ 3649 3650 #if defined(CAN1) 3651 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != 0U) 3652 #endif /* CAN1 */ 3653 3654 #if defined(CAN2) 3655 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) != 0U) 3656 #endif /* CAN2 */ 3657 3658 #if defined(USB) 3659 #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) != 0U) 3660 #endif /* USB */ 3661 3662 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != 0U) 3663 3664 #if defined(DAC1) 3665 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != 0U) 3666 #endif /* DAC1 */ 3667 3668 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != 0U) 3669 3670 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != 0U) 3671 3672 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != 0U) 3673 3674 #if defined(SWPMI1) 3675 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != 0U) 3676 #endif /* SWPMI1 */ 3677 3678 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != 0U) 3679 3680 3681 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == 0U) 3682 3683 #if defined(TIM3) 3684 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == 0U) 3685 #endif /* TIM3 */ 3686 3687 #if defined(TIM4) 3688 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == 0U) 3689 #endif /* TIM4 */ 3690 3691 #if defined(TIM5) 3692 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == 0U) 3693 #endif /* TIM5 */ 3694 3695 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == 0U) 3696 3697 #if defined(TIM7) 3698 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == 0U) 3699 #endif /* TIM7 */ 3700 3701 #if defined(LCD) 3702 #define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == 0U) 3703 #endif /* LCD */ 3704 3705 #if defined(RCC_APB1SMENR1_RTCAPBSMEN) 3706 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == 0U) 3707 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */ 3708 3709 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == 0U) 3710 3711 #if defined(SPI2) 3712 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == 0U) 3713 #endif /* SPI2 */ 3714 3715 #if defined(SPI3) 3716 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == 0U) 3717 #endif /* SPI3 */ 3718 3719 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == 0U) 3720 3721 #if defined(USART3) 3722 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == 0U) 3723 #endif /* USART3 */ 3724 3725 #if defined(UART4) 3726 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == 0U) 3727 #endif /* UART4 */ 3728 3729 #if defined(UART5) 3730 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == 0U) 3731 #endif /* UART5 */ 3732 3733 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == 0U) 3734 3735 #if defined(I2C2) 3736 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == 0U) 3737 #endif /* I2C2 */ 3738 3739 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == 0U) 3740 3741 #if defined(I2C4) 3742 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == 0U) 3743 #endif /* I2C4 */ 3744 3745 #if defined(CRS) 3746 #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == 0U) 3747 #endif /* CRS */ 3748 3749 #if defined(CAN1) 3750 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == 0U) 3751 #endif /* CAN1 */ 3752 3753 #if defined(CAN2) 3754 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) == 0U) 3755 #endif /* CAN2 */ 3756 3757 #if defined(USB) 3758 #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) == 0U) 3759 #endif /* USB */ 3760 3761 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == 0U) 3762 3763 #if defined(DAC1) 3764 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == 0U) 3765 #endif /* DAC1 */ 3766 3767 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == 0U) 3768 3769 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == 0U) 3770 3771 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == 0U) 3772 3773 #if defined(SWPMI1) 3774 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == 0U) 3775 #endif /* SWPMI1 */ 3776 3777 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == 0U) 3778 3779 /** 3780 * @} 3781 */ 3782 3783 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status 3784 * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 3785 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3786 * power consumption. 3787 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3788 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3789 * @{ 3790 */ 3791 3792 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U) 3793 3794 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) 3795 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != 0U) 3796 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ 3797 3798 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != 0U) 3799 3800 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U) 3801 3802 #if defined(TIM8) 3803 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != 0U) 3804 #endif /* TIM8 */ 3805 3806 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U) 3807 3808 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != 0U) 3809 3810 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != 0U) 3811 3812 #if defined(TIM17) 3813 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != 0U) 3814 #endif /* TIM17 */ 3815 3816 #if defined(SAI1) 3817 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U) 3818 #endif /* SAI1 */ 3819 3820 #if defined(SAI2) 3821 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != 0U) 3822 #endif /* SAI2 */ 3823 3824 #if defined(DFSDM1_Filter0) 3825 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != 0U) 3826 #endif /* DFSDM1_Filter0 */ 3827 3828 #if defined(LTDC) 3829 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) != 0U) 3830 #endif /* LTDC */ 3831 3832 #if defined(DSI) 3833 #define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) != 0U) 3834 #endif /* DSI */ 3835 3836 3837 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U) 3838 3839 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) 3840 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == 0U) 3841 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ 3842 3843 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == 0U) 3844 3845 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == 0U) 3846 3847 #if defined(TIM8) 3848 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == 0U) 3849 #endif /* TIM8 */ 3850 3851 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == 0U) 3852 3853 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == 0U) 3854 3855 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == 0U) 3856 3857 #if defined(TIM17) 3858 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == 0U) 3859 #endif /* TIM17 */ 3860 3861 #if defined(SAI1) 3862 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == 0U) 3863 #endif /* SAI1 */ 3864 3865 #if defined(SAI2) 3866 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == 0U) 3867 #endif /* SAI2 */ 3868 3869 #if defined(DFSDM1_Filter0) 3870 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == 0U) 3871 #endif /* DFSDM1_Filter0 */ 3872 3873 #if defined(LTDC) 3874 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) == 0U) 3875 #endif /* LTDC */ 3876 3877 #if defined(DSI) 3878 #define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) == 0U) 3879 #endif /* DSI */ 3880 3881 /** 3882 * @} 3883 */ 3884 3885 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset 3886 * @{ 3887 */ 3888 3889 /** @brief Macros to force or release the Backup domain reset. 3890 * @note This function resets the RTC peripheral (including the backup registers) 3891 * and the RTC clock source selection in RCC_CSR register. 3892 * @note The BKPSRAM is not affected by this reset. 3893 * @retval None 3894 */ 3895 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) 3896 3897 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) 3898 3899 /** 3900 * @} 3901 */ 3902 3903 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 3904 * @{ 3905 */ 3906 3907 /** @brief Macros to enable or disable the RTC clock. 3908 * @note As the RTC is in the Backup domain and write access is denied to 3909 * this domain after reset, you have to enable write access using 3910 * HAL_PWR_EnableBkUpAccess() function before to configure the RTC 3911 * (to be done once after reset). 3912 * @note These macros must be used after the RTC clock source was selected. 3913 * @retval None 3914 */ 3915 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 3916 3917 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 3918 3919 /** 3920 * @} 3921 */ 3922 3923 /** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI). 3924 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 3925 * It is used (enabled by hardware) as system clock source after startup 3926 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 3927 * of the HSE used directly or indirectly as system clock (if the Clock 3928 * Security System CSS is enabled). 3929 * @note HSI can not be stopped if it is used as system clock source. In this case, 3930 * you have to select another source of the system clock then stop the HSI. 3931 * @note After enabling the HSI, the application software should wait on HSIRDY 3932 * flag to be set indicating that HSI clock is stable and can be used as 3933 * system clock source. 3934 * This parameter can be: ENABLE or DISABLE. 3935 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 3936 * clock cycles. 3937 * @retval None 3938 */ 3939 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) 3940 3941 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) 3942 3943 /** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value. 3944 * @note The calibration is used to compensate for the variations in voltage 3945 * and temperature that influence the frequency of the internal HSI RC. 3946 * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value 3947 * (default is RCC_HSICALIBRATION_DEFAULT). 3948 * This parameter must be a number between 0 and 31 on STM32L43x/STM32L44x/STM32L47x/STM32L48x 3949 * or between 0 and 127 on other devices. 3950 * @retval None 3951 */ 3952 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ 3953 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos) 3954 3955 /** 3956 * @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI) 3957 * in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup. 3958 * @note The enable of this function has not effect on the HSION bit. 3959 * This parameter can be: ENABLE or DISABLE. 3960 * @retval None 3961 */ 3962 #define __HAL_RCC_HSIAUTOMATIC_START_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIASFS) 3963 3964 #define __HAL_RCC_HSIAUTOMATIC_START_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS) 3965 3966 /** 3967 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) 3968 * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. 3969 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication 3970 * speed because of the HSI startup time. 3971 * @note The enable of this function has not effect on the HSION bit. 3972 * This parameter can be: ENABLE or DISABLE. 3973 * @retval None 3974 */ 3975 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) 3976 3977 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) 3978 3979 /** 3980 * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI). 3981 * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. 3982 * It is used (enabled by hardware) as system clock source after 3983 * startup from Reset, wakeup from STOP and STANDBY mode, or in case 3984 * of failure of the HSE used directly or indirectly as system clock 3985 * (if the Clock Security System CSS is enabled). 3986 * @note MSI can not be stopped if it is used as system clock source. 3987 * In this case, you have to select another source of the system 3988 * clock then stop the MSI. 3989 * @note After enabling the MSI, the application software should wait on 3990 * MSIRDY flag to be set indicating that MSI clock is stable and can 3991 * be used as system clock source. 3992 * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator 3993 * clock cycles. 3994 * @retval None 3995 */ 3996 #define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION) 3997 3998 #define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION) 3999 4000 /** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value. 4001 * @note The calibration is used to compensate for the variations in voltage 4002 * and temperature that influence the frequency of the internal MSI RC. 4003 * Refer to the Application Note AN3300 for more details on how to 4004 * calibrate the MSI. 4005 * @param __MSICALIBRATIONVALUE__ specifies the calibration trimming value 4006 * (default is RCC_MSICALIBRATION_DEFAULT). 4007 * This parameter must be a number between 0 and 255. 4008 * @retval None 4009 */ 4010 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \ 4011 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (__MSICALIBRATIONVALUE__) << RCC_ICSCR_MSITRIM_Pos) 4012 4013 /** 4014 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode 4015 * @note After restart from Reset , the MSI clock is around 4 MHz. 4016 * After stop the startup clock can be MSI (at any of its possible 4017 * frequencies, the one that was used before entering stop mode) or HSI. 4018 * After Standby its frequency can be selected between 4 possible values 4019 * (1, 2, 4 or 8 MHz). 4020 * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready 4021 * (MSIRDY=1). 4022 * @note The MSI clock range after reset can be modified on the fly. 4023 * @param __MSIRANGEVALUE__ specifies the MSI clock range. 4024 * This parameter must be one of the following values: 4025 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz 4026 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz 4027 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz 4028 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz 4029 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 4030 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 4031 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) 4032 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 4033 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz 4034 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz 4035 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz 4036 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz 4037 * @retval None 4038 */ 4039 #define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \ 4040 do { \ 4041 SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \ 4042 MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \ 4043 } while(0) 4044 4045 /** 4046 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode 4047 * After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz). 4048 * @param __MSIRANGEVALUE__ specifies the MSI clock range. 4049 * This parameter must be one of the following values: 4050 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 4051 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 4052 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) 4053 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 4054 * @retval None 4055 */ 4056 #define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \ 4057 MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U) 4058 4059 /** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode 4060 * @retval MSI clock range. 4061 * This parameter must be one of the following values: 4062 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz 4063 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz 4064 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz 4065 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz 4066 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 4067 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 4068 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) 4069 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 4070 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz 4071 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz 4072 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz 4073 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz 4074 */ 4075 #define __HAL_RCC_GET_MSI_RANGE() \ 4076 ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != 0U) ? \ 4077 READ_BIT(RCC->CR, RCC_CR_MSIRANGE) : \ 4078 (READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4U)) 4079 4080 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). 4081 * @note After enabling the LSI, the application software should wait on 4082 * LSIRDY flag to be set indicating that LSI clock is stable and can 4083 * be used to clock the IWDG and/or the RTC. 4084 * @note LSI can not be disabled if the IWDG is running. 4085 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 4086 * clock cycles. 4087 * @retval None 4088 */ 4089 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) 4090 4091 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) 4092 4093 /** 4094 * @brief Macro to configure the External High Speed oscillator (HSE). 4095 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 4096 * supported by this macro. User should request a transition to HSE Off 4097 * first and then HSE On or HSE Bypass. 4098 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 4099 * software should wait on HSERDY flag to be set indicating that HSE clock 4100 * is stable and can be used to clock the PLL and/or system clock. 4101 * @note HSE state can not be changed if it is used directly or through the 4102 * PLL as system clock. In this case, you have to select another source 4103 * of the system clock then change the HSE state (ex. disable it). 4104 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 4105 * @note This function reset the CSSON bit, so if the clock security system(CSS) 4106 * was previously enabled you have to enable it again after calling this 4107 * function. 4108 * @param __STATE__ specifies the new state of the HSE. 4109 * This parameter can be one of the following values: 4110 * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after 4111 * 6 HSE oscillator clock cycles. 4112 * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. 4113 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. 4114 * @retval None 4115 */ 4116 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 4117 do { \ 4118 if((__STATE__) == RCC_HSE_ON) \ 4119 { \ 4120 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 4121 } \ 4122 else if((__STATE__) == RCC_HSE_BYPASS) \ 4123 { \ 4124 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 4125 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 4126 } \ 4127 else \ 4128 { \ 4129 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 4130 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 4131 } \ 4132 } while(0) 4133 4134 /** 4135 * @brief Macro to configure the External Low Speed oscillator (LSE). 4136 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not 4137 * supported by this macro. User should request a transition to LSE Off 4138 * first and then LSE On or LSE Bypass. 4139 * @note As the LSE is in the Backup domain and write access is denied to 4140 * this domain after reset, you have to enable write access using 4141 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 4142 * (to be done once after reset). 4143 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 4144 * software should wait on LSERDY flag to be set indicating that LSE clock 4145 * is stable and can be used to clock the RTC. 4146 * @param __STATE__ specifies the new state of the LSE. 4147 * This parameter can be one of the following values: 4148 * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after 4149 * 6 LSE oscillator clock cycles. 4150 * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. 4151 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. 4152 * @retval None 4153 */ 4154 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 4155 do { \ 4156 if((__STATE__) == RCC_LSE_ON) \ 4157 { \ 4158 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 4159 } \ 4160 else if((__STATE__) == RCC_LSE_BYPASS) \ 4161 { \ 4162 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 4163 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 4164 } \ 4165 else \ 4166 { \ 4167 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 4168 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 4169 } \ 4170 } while(0) 4171 4172 #if defined(RCC_HSI48_SUPPORT) 4173 4174 /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). 4175 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. 4176 * @note After enabling the HSI48, the application software should wait on HSI48RDY 4177 * flag to be set indicating that HSI48 clock is stable. 4178 * This parameter can be: ENABLE or DISABLE. 4179 * @retval None 4180 */ 4181 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) 4182 4183 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) 4184 4185 #endif /* RCC_HSI48_SUPPORT */ 4186 4187 /** @brief Macros to configure the RTC clock (RTCCLK). 4188 * @note As the RTC clock configuration bits are in the Backup domain and write 4189 * access is denied to this domain after reset, you have to enable write 4190 * access using the Power Backup Access macro before to configure 4191 * the RTC clock source (to be done once after reset). 4192 * @note Once the RTC clock is configured it cannot be changed unless the 4193 * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by 4194 * a Power On Reset (POR). 4195 * 4196 * @param __RTC_CLKSOURCE__ specifies the RTC clock source. 4197 * This parameter can be one of the following values: 4198 * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. 4199 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 4200 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 4201 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 4202 * 4203 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 4204 * work in STOP and STANDBY modes, and can be used as wakeup source. 4205 * However, when the HSE clock is used as RTC clock source, the RTC 4206 * cannot be used in STOP and STANDBY modes. 4207 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 4208 * RTC clock source). 4209 * @retval None 4210 */ 4211 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ 4212 MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) 4213 4214 4215 /** @brief Macro to get the RTC clock source. 4216 * @retval The returned value can be one of the following: 4217 * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. 4218 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 4219 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 4220 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 4221 */ 4222 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) 4223 4224 /** @brief Macros to enable or disable the main PLL. 4225 * @note After enabling the main PLL, the application software should wait on 4226 * PLLRDY flag to be set indicating that PLL clock is stable and can 4227 * be used as system clock source. 4228 * @note The main PLL can not be disabled if it is used as system clock source 4229 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 4230 * @retval None 4231 */ 4232 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) 4233 4234 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) 4235 4236 /** @brief Macro to configure the PLL clock source. 4237 * @note This function must be used only when the main PLL is disabled. 4238 * @param __PLLSOURCE__ specifies the PLL entry clock source. 4239 * This parameter can be one of the following values: 4240 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry 4241 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 4242 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 4243 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 4244 * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2). 4245 * @retval None 4246 * 4247 */ 4248 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \ 4249 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) 4250 4251 /** @brief Macro to configure the PLL source division factor M. 4252 * @note This function must be used only when the main PLL is disabled. 4253 * @param __PLLM__ specifies the division factor for PLL VCO input clock 4254 * This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. 4255 * This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices. 4256 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 4257 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency 4258 * of 16 MHz to limit PLL jitter. 4259 * @retval None 4260 * 4261 */ 4262 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \ 4263 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U) 4264 4265 /** 4266 * @brief Macro to configure the main PLL clock source, multiplication and division factors. 4267 * @note This function must be used only when the main PLL is disabled. 4268 * 4269 * @param __PLLSOURCE__ specifies the PLL entry clock source. 4270 * This parameter can be one of the following values: 4271 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry 4272 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 4273 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 4274 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 4275 * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2). 4276 * 4277 * @param __PLLM__ specifies the division factor for PLL VCO input clock. 4278 * This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. 4279 * This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices. 4280 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 4281 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency 4282 * of 16 MHz to limit PLL jitter. 4283 * 4284 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock. 4285 * This parameter must be a number between 8 and 86. 4286 * @note You have to set the PLLN parameter correctly to ensure that the VCO 4287 * output frequency is between 64 and 344 MHz. 4288 * 4289 * @param __PLLP__ specifies the division factor for SAI clock when SAI available on device. 4290 * This parameter must be a number in the range (7 or 17) for STM32L47x/STM32L48x 4291 * else (2 to 31). 4292 * 4293 * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC1 and RNG clocks. 4294 * This parameter must be in the range (2, 4, 6 or 8). 4295 * @note If the USB OTG FS is used in your application, you have to set the 4296 * PLLQ parameter correctly to have 48 MHz clock for the USB. However, 4297 * the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work 4298 * correctly. 4299 * @param __PLLR__ specifies the division factor for the main system clock. 4300 * @note You have to set the PLLR parameter correctly to not exceed 80MHZ. 4301 * This parameter must be in the range (2, 4, 6 or 8). 4302 * @retval None 4303 */ 4304 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 4305 4306 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ 4307 MODIFY_REG(RCC->PLLCFGR, \ 4308 (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \ 4309 RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLPDIV), \ 4310 ((__PLLSOURCE__) | \ 4311 (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \ 4312 ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ 4313 ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \ 4314 ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \ 4315 ((uint32_t)(__PLLP__) << RCC_PLLCFGR_PLLPDIV_Pos))) 4316 4317 #elif defined(RCC_PLLP_SUPPORT) 4318 4319 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ 4320 MODIFY_REG(RCC->PLLCFGR, \ 4321 (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \ 4322 RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLP), \ 4323 ((__PLLSOURCE__) | \ 4324 (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \ 4325 ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ 4326 ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \ 4327 ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \ 4328 (((__PLLP__) >> 4U) << RCC_PLLCFGR_PLLP_Pos))) 4329 4330 #else 4331 4332 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLQ__,__PLLR__ ) \ 4333 MODIFY_REG(RCC->PLLCFGR, \ 4334 (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \ 4335 RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR), \ 4336 ((__PLLSOURCE__) | \ 4337 (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \ 4338 ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ 4339 ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \ 4340 ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos))) 4341 4342 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ 4343 4344 /** @brief Macro to get the oscillator used as PLL clock source. 4345 * @retval The oscillator used as PLL clock source. The returned value can be one 4346 * of the following: 4347 * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. 4348 * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source. 4349 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. 4350 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. 4351 */ 4352 #define __HAL_RCC_GET_PLL_OSCSOURCE() (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)) 4353 4354 /** 4355 * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) 4356 * @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime 4357 * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot 4358 * be stopped if used as System Clock. 4359 * @param __PLLCLOCKOUT__ specifies the PLL clock to be output. 4360 * This parameter can be one or a combination of the following values: 4361 * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve 4362 * high-quality audio performance on SAI interface in case. 4363 * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz), 4364 * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). 4365 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz) 4366 * @retval None 4367 */ 4368 #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 4369 4370 #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 4371 4372 /** 4373 * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) 4374 * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked. 4375 * This parameter can be one of the following values: 4376 * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve 4377 * high-quality audio performance on SAI interface in case. 4378 * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz), 4379 * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). 4380 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz) 4381 * @retval SET / RESET 4382 */ 4383 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 4384 4385 /** 4386 * @brief Macro to configure the system clock source. 4387 * @param __SYSCLKSOURCE__ specifies the system clock source. 4388 * This parameter can be one of the following values: 4389 * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source. 4390 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. 4391 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. 4392 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. 4393 * @retval None 4394 */ 4395 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ 4396 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) 4397 4398 /** @brief Macro to get the clock source used as system clock. 4399 * @retval The clock source used as system clock. The returned value can be one 4400 * of the following: 4401 * - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock. 4402 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. 4403 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. 4404 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. 4405 */ 4406 #define __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS)) 4407 4408 /** 4409 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. 4410 * @note As the LSE is in the Backup domain and write access is denied to 4411 * this domain after reset, you have to enable write access using 4412 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 4413 * (to be done once after reset). 4414 * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. 4415 * This parameter can be one of the following values: 4416 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. 4417 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. 4418 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. 4419 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. 4420 * @retval None 4421 */ 4422 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ 4423 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__)) 4424 4425 /** 4426 * @brief Macro to configure the wake up from stop clock. 4427 * @param __STOPWUCLK__ specifies the clock source used after wake up from stop. 4428 * This parameter can be one of the following values: 4429 * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source 4430 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source 4431 * @retval None 4432 */ 4433 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \ 4434 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__)) 4435 4436 4437 /** @brief Macro to configure the MCO clock. 4438 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 4439 * This parameter can be one of the following values: 4440 * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled 4441 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source 4442 * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source 4443 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source 4444 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee 4445 * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source 4446 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source 4447 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source 4448 @if STM32L443xx 4449 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 4450 @endif 4451 @if STM32L4A6xx 4452 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 4453 @endif 4454 * @param __MCODIV__ specifies the MCO clock prescaler. 4455 * This parameter can be one of the following values: 4456 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 4457 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 4458 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 4459 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 4460 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 4461 */ 4462 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 4463 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 4464 4465 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 4466 * @brief macros to manage the specified RCC Flags and interrupts. 4467 * @{ 4468 */ 4469 4470 /** @brief Enable RCC interrupt(s). 4471 * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be enabled. 4472 * This parameter can be any combination of the following values: 4473 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4474 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4475 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt 4476 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4477 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4478 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 4479 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1 4480 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 4481 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 4482 @if STM32L443xx 4483 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 4484 @endif 4485 @if STM32L4A6xx 4486 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 4487 @endif 4488 * @retval None 4489 */ 4490 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) 4491 4492 /** @brief Disable RCC interrupt(s). 4493 * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be disabled. 4494 * This parameter can be any combination of the following values: 4495 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4496 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4497 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt 4498 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4499 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4500 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 4501 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1 4502 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 4503 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 4504 @if STM32L443xx 4505 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 4506 @endif 4507 @if STM32L4A6xx 4508 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 4509 @endif 4510 * @retval None 4511 */ 4512 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) 4513 4514 /** @brief Clear the RCC's interrupt pending bits. 4515 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 4516 * This parameter can be any combination of the following values: 4517 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4518 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4519 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 4520 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4521 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4522 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 4523 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1 4524 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 4525 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt 4526 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 4527 @if STM32L443xx 4528 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 4529 @endif 4530 @if STM32L4A6xx 4531 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 4532 @endif 4533 * @retval None 4534 */ 4535 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) 4536 4537 /** @brief Check whether the RCC interrupt has occurred or not. 4538 * @param __INTERRUPT__ specifies the RCC interrupt source to check. 4539 * This parameter can be one of the following values: 4540 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4541 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4542 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 4543 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4544 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4545 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 4546 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1 4547 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 4548 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt 4549 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 4550 @if STM32L443xx 4551 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 4552 @endif 4553 @if STM32L4A6xx 4554 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 4555 @endif 4556 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 4557 */ 4558 #define __HAL_RCC_GET_IT(__INTERRUPT__) (READ_BIT(RCC->CIFR, (__INTERRUPT__)) == (__INTERRUPT__)) 4559 4560 /** @brief Set RMVF bit to clear the reset flags. 4561 * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, 4562 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. 4563 * @retval None 4564 */ 4565 #define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF) 4566 4567 /** @brief Check whether the selected RCC flag is set or not. 4568 * @param __FLAG__ specifies the flag to check. 4569 * This parameter can be one of the following values: 4570 * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready 4571 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready 4572 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready 4573 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready 4574 * @arg @ref RCC_FLAG_PLLSAI1RDY PLLSAI1 clock ready for devices with PLLSAI1 4575 * @arg @ref RCC_FLAG_PLLSAI2RDY PLLSAI2 clock ready for devices with PLLSAI2 4576 @if STM32L443xx 4577 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 4578 @endif 4579 @if STM32L4A6xx 4580 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 4581 @endif 4582 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready 4583 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection 4584 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready 4585 * @arg @ref RCC_FLAG_BORRST BOR reset 4586 * @arg @ref RCC_FLAG_OBLRST OBLRST reset 4587 * @arg @ref RCC_FLAG_PINRST Pin reset 4588 * @arg @ref RCC_FLAG_FWRST FIREWALL reset 4589 * @arg @ref RCC_FLAG_SFTRST Software reset 4590 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset 4591 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset 4592 * @arg @ref RCC_FLAG_LPWRRST Low Power reset 4593 * @retval The new state of __FLAG__ (TRUE or FALSE). 4594 */ 4595 #if defined(RCC_HSI48_SUPPORT) 4596 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ 4597 ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \ 4598 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ 4599 ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ 4600 (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) 4601 #else 4602 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ 4603 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ 4604 ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) & \ 4605 (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) 4606 #endif /* RCC_HSI48_SUPPORT */ 4607 4608 /** 4609 * @} 4610 */ 4611 4612 /** 4613 * @} 4614 */ 4615 4616 /* Private constants ---------------------------------------------------------*/ 4617 /** @defgroup RCC_Private_Constants RCC Private Constants 4618 * @{ 4619 */ 4620 /* Defines used for Flags */ 4621 #define CR_REG_INDEX 1U 4622 #define BDCR_REG_INDEX 2U 4623 #define CSR_REG_INDEX 3U 4624 #if defined(RCC_HSI48_SUPPORT) 4625 #define CRRCR_REG_INDEX 4U 4626 #endif /* RCC_HSI48_SUPPORT */ 4627 4628 #define RCC_FLAG_MASK 0x1FU 4629 4630 /* Defines Oscillator Masks */ 4631 #if defined(RCC_HSI48_SUPPORT) 4632 #define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE) /*!< All Oscillator to configure */ 4633 #else 4634 #define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE) /*!< All Oscillator to configure */ 4635 #endif /* RCC_HSI48_SUPPORT */ 4636 4637 /** @defgroup RCC_Reset_Flag Reset Flag 4638 * @{ 4639 */ 4640 #define RCC_RESET_FLAG_OBL RCC_CSR_OBLRSTF /*!< Option Byte Loader reset flag */ 4641 #define RCC_RESET_FLAG_PIN RCC_CSR_PINRSTF /*!< PIN reset flag */ 4642 #define RCC_RESET_FLAG_PWR RCC_CSR_BORRSTF /*!< BOR or POR/PDR reset flag */ 4643 #define RCC_RESET_FLAG_SW RCC_CSR_SFTRSTF /*!< Software Reset flag */ 4644 #define RCC_RESET_FLAG_IWDG RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ 4645 #define RCC_RESET_FLAG_WWDG RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ 4646 #define RCC_RESET_FLAG_LPWR RCC_CSR_LPWRRSTF /*!< Low power reset flag */ 4647 #define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \ 4648 RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | \ 4649 RCC_RESET_FLAG_LPWR) 4650 /** 4651 * @} 4652 */ 4653 4654 /** 4655 * @} 4656 */ 4657 4658 /* Private macros ------------------------------------------------------------*/ 4659 /** @addtogroup RCC_Private_Macros 4660 * @{ 4661 */ 4662 4663 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 4664 (((__OSCILLATOR__) & ~RCC_OSCILLATORTYPE_ALL) == 0x00U)) 4665 4666 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ 4667 ((__HSE__) == RCC_HSE_BYPASS)) 4668 4669 #if defined(RCC_BDCR_LSESYSDIS) 4670 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || ((__LSE__) == RCC_LSE_BYPASS_RTC_ONLY) || \ 4671 ((__LSE__) == RCC_LSE_ON_RTC_ONLY) || ((__LSE__) == RCC_LSE_BYPASS)) 4672 #else 4673 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ 4674 ((__LSE__) == RCC_LSE_BYPASS)) 4675 #endif /* RCC_BDCR_LSESYSDIS */ 4676 4677 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) 4678 4679 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos)) 4680 4681 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) 4682 4683 #if defined(RCC_CSR_LSIPREDIV) 4684 #define IS_RCC_LSIDIV(__LSIDIV__) (((__LSIDIV__) == RCC_LSI_DIV1) || ((__LSIDIV__) == RCC_LSI_DIV128)) 4685 #endif /* RCC_CSR_LSIPREDIV */ 4686 4687 #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) 4688 4689 #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 255U) 4690 4691 #if defined(RCC_HSI48_SUPPORT) 4692 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) 4693 #endif /* RCC_HSI48_SUPPORT */ 4694 4695 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \ 4696 ((__PLL__) == RCC_PLL_ON)) 4697 4698 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \ 4699 ((__SOURCE__) == RCC_PLLSOURCE_MSI) || \ 4700 ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ 4701 ((__SOURCE__) == RCC_PLLSOURCE_HSE)) 4702 4703 #if defined(RCC_PLLM_DIV_1_16_SUPPORT) 4704 #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) 4705 #else 4706 #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) 4707 #endif /*RCC_PLLM_DIV_1_16_SUPPORT */ 4708 4709 #define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) 4710 4711 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 4712 #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) 4713 #else 4714 #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U)) 4715 #endif /*RCC_PLLP_DIV_2_31_SUPPORT */ 4716 4717 #define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 4718 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 4719 4720 #define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 4721 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 4722 4723 #if defined(RCC_PLLSAI1_SUPPORT) 4724 #define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) || \ 4725 (((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK) || \ 4726 (((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \ 4727 (((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK)) == 0U)) 4728 #endif /* RCC_PLLSAI1_SUPPORT */ 4729 4730 #if defined(RCC_PLLSAI2_SUPPORT) 4731 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) 4732 #define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \ 4733 (((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \ 4734 (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_ADC2CLK)) == 0U)) 4735 #elif defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 4736 #define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \ 4737 (((__VALUE__) & RCC_PLLSAI2_DSICLK) == RCC_PLLSAI2_DSICLK) || \ 4738 (((__VALUE__) & RCC_PLLSAI2_LTDCCLK) == RCC_PLLSAI2_LTDCCLK)) && \ 4739 (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_DSICLK|RCC_PLLSAI2_LTDCCLK)) == 0U)) 4740 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ 4741 #endif /* RCC_PLLSAI2_SUPPORT */ 4742 4743 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ 4744 ((__RANGE__) == RCC_MSIRANGE_1) || \ 4745 ((__RANGE__) == RCC_MSIRANGE_2) || \ 4746 ((__RANGE__) == RCC_MSIRANGE_3) || \ 4747 ((__RANGE__) == RCC_MSIRANGE_4) || \ 4748 ((__RANGE__) == RCC_MSIRANGE_5) || \ 4749 ((__RANGE__) == RCC_MSIRANGE_6) || \ 4750 ((__RANGE__) == RCC_MSIRANGE_7) || \ 4751 ((__RANGE__) == RCC_MSIRANGE_8) || \ 4752 ((__RANGE__) == RCC_MSIRANGE_9) || \ 4753 ((__RANGE__) == RCC_MSIRANGE_10) || \ 4754 ((__RANGE__) == RCC_MSIRANGE_11)) 4755 4756 #define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) || \ 4757 ((__RANGE__) == RCC_MSIRANGE_5) || \ 4758 ((__RANGE__) == RCC_MSIRANGE_6) || \ 4759 ((__RANGE__) == RCC_MSIRANGE_7)) 4760 4761 #define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= 15U)) 4762 4763 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \ 4764 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ 4765 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ 4766 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) 4767 4768 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ 4769 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ 4770 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ 4771 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ 4772 ((__HCLK__) == RCC_SYSCLK_DIV512)) 4773 4774 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ 4775 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ 4776 ((__PCLK__) == RCC_HCLK_DIV16)) 4777 4778 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \ 4779 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ 4780 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ 4781 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) 4782 4783 #define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1) 4784 4785 #if defined(RCC_HSI48_SUPPORT) 4786 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ 4787 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 4788 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ 4789 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ 4790 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ 4791 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ 4792 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ 4793 ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ 4794 ((__SOURCE__) == RCC_MCO1SOURCE_HSI48)) 4795 #else 4796 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ 4797 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 4798 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ 4799 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ 4800 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ 4801 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ 4802 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ 4803 ((__SOURCE__) == RCC_MCO1SOURCE_LSE)) 4804 #endif /* RCC_HSI48_SUPPORT */ 4805 4806 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ 4807 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ 4808 ((__DIV__) == RCC_MCODIV_16)) 4809 4810 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ 4811 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ 4812 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ 4813 ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) 4814 4815 #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \ 4816 ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) 4817 /** 4818 * @} 4819 */ 4820 4821 /* Include RCC HAL Extended module */ 4822 #include "stm32l4xx_hal_rcc_ex.h" 4823 4824 /* Exported functions --------------------------------------------------------*/ 4825 /** @addtogroup RCC_Exported_Functions 4826 * @{ 4827 */ 4828 4829 4830 /** @addtogroup RCC_Exported_Functions_Group1 4831 * @{ 4832 */ 4833 4834 /* Initialization and de-initialization functions ******************************/ 4835 HAL_StatusTypeDef HAL_RCC_DeInit(void); 4836 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 4837 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); 4838 4839 /** 4840 * @} 4841 */ 4842 4843 /** @addtogroup RCC_Exported_Functions_Group2 4844 * @{ 4845 */ 4846 4847 /* Peripheral Control functions ************************************************/ 4848 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 4849 void HAL_RCC_EnableCSS(void); 4850 uint32_t HAL_RCC_GetSysClockFreq(void); 4851 uint32_t HAL_RCC_GetHCLKFreq(void); 4852 uint32_t HAL_RCC_GetPCLK1Freq(void); 4853 uint32_t HAL_RCC_GetPCLK2Freq(void); 4854 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 4855 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 4856 /* CSS NMI IRQ handler */ 4857 void HAL_RCC_NMI_IRQHandler(void); 4858 /* User Callbacks in non blocking mode (IT mode) */ 4859 void HAL_RCC_CSSCallback(void); 4860 4861 uint32_t HAL_RCC_GetResetSource(void); 4862 /** 4863 * @} 4864 */ 4865 4866 /** 4867 * @} 4868 */ 4869 4870 /** 4871 * @} 4872 */ 4873 4874 /** 4875 * @} 4876 */ 4877 4878 #ifdef __cplusplus 4879 } 4880 #endif 4881 4882 #endif /* STM32L4xx_HAL_RCC_H */ 4883 4884
