1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_pcd.h 4 * @author MCD Application Team 5 * @brief Header file of PCD HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32L4xx_HAL_PCD_H 21 #define STM32L4xx_HAL_PCD_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32l4xx_ll_usb.h" 29 30 #if defined (USB) || defined (USB_OTG_FS) 31 32 /** @addtogroup STM32L4xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup PCD 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup PCD_Exported_Types PCD Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief PCD State structure definition 47 */ 48 typedef enum 49 { 50 HAL_PCD_STATE_RESET = 0x00, 51 HAL_PCD_STATE_READY = 0x01, 52 HAL_PCD_STATE_ERROR = 0x02, 53 HAL_PCD_STATE_BUSY = 0x03, 54 HAL_PCD_STATE_TIMEOUT = 0x04 55 } PCD_StateTypeDef; 56 57 /* Device LPM suspend state */ 58 typedef enum 59 { 60 LPM_L0 = 0x00, /* on */ 61 LPM_L1 = 0x01, /* LPM L1 sleep */ 62 LPM_L2 = 0x02, /* suspend */ 63 LPM_L3 = 0x03, /* off */ 64 } PCD_LPM_StateTypeDef; 65 66 typedef enum 67 { 68 PCD_LPM_L0_ACTIVE = 0x00, /* on */ 69 PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */ 70 } PCD_LPM_MsgTypeDef; 71 72 typedef enum 73 { 74 PCD_BCD_ERROR = 0xFF, 75 PCD_BCD_CONTACT_DETECTION = 0xFE, 76 PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD, 77 PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC, 78 PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB, 79 PCD_BCD_DISCOVERY_COMPLETED = 0x00, 80 81 } PCD_BCD_MsgTypeDef; 82 83 #if defined (USB) 84 85 #endif /* defined (USB) */ 86 #if defined (USB_OTG_FS) 87 typedef USB_OTG_GlobalTypeDef PCD_TypeDef; 88 typedef USB_OTG_CfgTypeDef PCD_InitTypeDef; 89 typedef USB_OTG_EPTypeDef PCD_EPTypeDef; 90 #endif /* defined (USB_OTG_FS) */ 91 #if defined (USB) 92 typedef USB_TypeDef PCD_TypeDef; 93 typedef USB_CfgTypeDef PCD_InitTypeDef; 94 typedef USB_EPTypeDef PCD_EPTypeDef; 95 #endif /* defined (USB) */ 96 97 /** 98 * @brief PCD Handle Structure definition 99 */ 100 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) 101 typedef struct __PCD_HandleTypeDef 102 #else 103 typedef struct 104 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ 105 { 106 PCD_TypeDef *Instance; /*!< Register base address */ 107 PCD_InitTypeDef Init; /*!< PCD required parameters */ 108 __IO uint8_t USB_Address; /*!< USB Address */ 109 #if defined (USB_OTG_FS) 110 PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */ 111 PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */ 112 #endif /* defined (USB_OTG_FS) */ 113 #if defined (USB) 114 PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */ 115 PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */ 116 #endif /* defined (USB) */ 117 HAL_LockTypeDef Lock; /*!< PCD peripheral status */ 118 __IO PCD_StateTypeDef State; /*!< PCD communication state */ 119 __IO uint32_t ErrorCode; /*!< PCD Error code */ 120 uint32_t Setup[12]; /*!< Setup packet buffer */ 121 PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ 122 uint32_t BESL; 123 uint32_t FrameNumber; /*!< Store Current Frame number */ 124 125 126 uint32_t lpm_active; /*!< Enable or disable the Link Power Management . 127 This parameter can be set to ENABLE or DISABLE */ 128 129 uint32_t battery_charging_active; /*!< Enable or disable Battery charging. 130 This parameter can be set to ENABLE or DISABLE */ 131 void *pData; /*!< Pointer to upper stack Handler */ 132 133 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) 134 void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD SOF callback */ 135 void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Setup Stage callback */ 136 void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Reset callback */ 137 void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Suspend callback */ 138 void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Resume callback */ 139 void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Connect callback */ 140 void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Disconnect callback */ 141 142 void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data OUT Stage callback */ 143 void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data IN Stage callback */ 144 void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO OUT Incomplete callback */ 145 void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO IN Incomplete callback */ 146 void (* BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< USB OTG PCD BCD callback */ 147 void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< USB OTG PCD LPM callback */ 148 149 void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp Init callback */ 150 void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp DeInit callback */ 151 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ 152 } PCD_HandleTypeDef; 153 154 /** 155 * @} 156 */ 157 158 /* Include PCD HAL Extended module */ 159 #include "stm32l4xx_hal_pcd_ex.h" 160 161 /* Exported constants --------------------------------------------------------*/ 162 /** @defgroup PCD_Exported_Constants PCD Exported Constants 163 * @{ 164 */ 165 166 /** @defgroup PCD_Speed PCD Speed 167 * @{ 168 */ 169 #define PCD_SPEED_FULL USBD_FS_SPEED 170 /** 171 * @} 172 */ 173 174 /** @defgroup PCD_PHY_Module PCD PHY Module 175 * @{ 176 */ 177 #define PCD_PHY_ULPI 1U 178 #define PCD_PHY_EMBEDDED 2U 179 #define PCD_PHY_UTMI 3U 180 /** 181 * @} 182 */ 183 184 /** @defgroup PCD_Error_Code_definition PCD Error Code definition 185 * @brief PCD Error Code definition 186 * @{ 187 */ 188 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) 189 #define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */ 190 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ 191 192 /** 193 * @} 194 */ 195 196 /** 197 * @} 198 */ 199 200 /* Exported macros -----------------------------------------------------------*/ 201 /** @defgroup PCD_Exported_Macros PCD Exported Macros 202 * @brief macros to handle interrupts and specific clock configurations 203 * @{ 204 */ 205 #if defined (USB_OTG_FS) 206 #define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) 207 #define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) 208 209 #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \ 210 ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) 211 212 #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__)) 213 #define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) 214 215 #define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \ 216 *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK) 217 218 #define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) \ 219 *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK 220 221 #define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) \ 222 ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U) 223 224 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE 225 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE) 226 #endif /* defined (USB_OTG_FS) */ 227 228 #if defined (USB) 229 #define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) 230 #define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) 231 #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\ 232 & (__INTERRUPT__)) == (__INTERRUPT__)) 233 234 #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR)\ 235 &= (uint16_t)(~(__INTERRUPT__))) 236 237 #define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE 238 #define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE) 239 #endif /* defined (USB) */ 240 241 /** 242 * @} 243 */ 244 245 /* Exported functions --------------------------------------------------------*/ 246 /** @addtogroup PCD_Exported_Functions PCD Exported Functions 247 * @{ 248 */ 249 250 /* Initialization/de-initialization functions ********************************/ 251 /** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions 252 * @{ 253 */ 254 HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd); 255 HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd); 256 void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd); 257 void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd); 258 259 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) 260 /** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition 261 * @brief HAL USB OTG PCD Callback ID enumeration definition 262 * @{ 263 */ 264 typedef enum 265 { 266 HAL_PCD_SOF_CB_ID = 0x01, /*!< USB PCD SOF callback ID */ 267 HAL_PCD_SETUPSTAGE_CB_ID = 0x02, /*!< USB PCD Setup Stage callback ID */ 268 HAL_PCD_RESET_CB_ID = 0x03, /*!< USB PCD Reset callback ID */ 269 HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */ 270 HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */ 271 HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */ 272 HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */ 273 274 HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */ 275 HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */ 276 277 } HAL_PCD_CallbackIDTypeDef; 278 /** 279 * @} 280 */ 281 282 /** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition 283 * @brief HAL USB OTG PCD Callback pointer definition 284 * @{ 285 */ 286 287 typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd); /*!< pointer to a common USB OTG PCD callback function */ 288 typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data OUT Stage callback */ 289 typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data IN Stage callback */ 290 typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */ 291 typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO IN Incomplete callback */ 292 typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< pointer to USB OTG PCD LPM callback */ 293 typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< pointer to USB OTG PCD BCD callback */ 294 295 /** 296 * @} 297 */ 298 299 HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, 300 pPCD_CallbackTypeDef pCallback); 301 302 HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID); 303 304 HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, 305 pPCD_DataOutStageCallbackTypeDef pCallback); 306 307 HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd); 308 309 HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, 310 pPCD_DataInStageCallbackTypeDef pCallback); 311 312 HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd); 313 314 HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, 315 pPCD_IsoOutIncpltCallbackTypeDef pCallback); 316 317 HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd); 318 319 HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, 320 pPCD_IsoInIncpltCallbackTypeDef pCallback); 321 322 HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd); 323 324 HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback); 325 HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd); 326 327 HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback); 328 HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd); 329 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ 330 /** 331 * @} 332 */ 333 334 /* I/O operation functions ***************************************************/ 335 /* Non-Blocking mode: Interrupt */ 336 /** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions 337 * @{ 338 */ 339 HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd); 340 HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd); 341 void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd); 342 343 void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd); 344 void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd); 345 void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd); 346 void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd); 347 void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd); 348 void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd); 349 void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd); 350 351 void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); 352 void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); 353 void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); 354 void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); 355 /** 356 * @} 357 */ 358 359 /* Peripheral Control functions **********************************************/ 360 /** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions 361 * @{ 362 */ 363 HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); 364 HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); 365 HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address); 366 HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); 367 HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); 368 HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); 369 HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); 370 HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); 371 HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); 372 HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); 373 HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); 374 HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); 375 HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); 376 uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); 377 /** 378 * @} 379 */ 380 381 /* Peripheral State functions ************************************************/ 382 /** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions 383 * @{ 384 */ 385 PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); 386 /** 387 * @} 388 */ 389 390 /** 391 * @} 392 */ 393 394 /* Private constants ---------------------------------------------------------*/ 395 /** @defgroup PCD_Private_Constants PCD Private Constants 396 * @{ 397 */ 398 /** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt 399 * @{ 400 */ 401 #if defined (USB_OTG_FS) 402 #define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 17) /*!< USB FS EXTI Line WakeUp Interrupt */ 403 #endif /* defined (USB_OTG_FS) */ 404 405 #if defined (USB) 406 #define USB_WAKEUP_EXTI_LINE (0x1U << 17) /*!< USB FS EXTI Line WakeUp Interrupt */ 407 #endif /* defined (USB) */ 408 409 /** 410 * @} 411 */ 412 #if defined (USB) 413 /** @defgroup PCD_EP0_MPS PCD EP0 MPS 414 * @{ 415 */ 416 #define PCD_EP0MPS_64 EP_MPS_64 417 #define PCD_EP0MPS_32 EP_MPS_32 418 #define PCD_EP0MPS_16 EP_MPS_16 419 #define PCD_EP0MPS_08 EP_MPS_8 420 /** 421 * @} 422 */ 423 424 /** @defgroup PCD_ENDP PCD ENDP 425 * @{ 426 */ 427 #define PCD_ENDP0 0U 428 #define PCD_ENDP1 1U 429 #define PCD_ENDP2 2U 430 #define PCD_ENDP3 3U 431 #define PCD_ENDP4 4U 432 #define PCD_ENDP5 5U 433 #define PCD_ENDP6 6U 434 #define PCD_ENDP7 7U 435 /** 436 * @} 437 */ 438 439 /** @defgroup PCD_ENDP_Kind PCD Endpoint Kind 440 * @{ 441 */ 442 #define PCD_SNG_BUF 0U 443 #define PCD_DBL_BUF 1U 444 /** 445 * @} 446 */ 447 #endif /* defined (USB) */ 448 /** 449 * @} 450 */ 451 452 #if defined (USB_OTG_FS) 453 #ifndef USB_OTG_DOEPINT_OTEPSPR 454 #define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */ 455 #endif /* defined USB_OTG_DOEPINT_OTEPSPR */ 456 457 #ifndef USB_OTG_DOEPMSK_OTEPSPRM 458 #define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */ 459 #endif /* defined USB_OTG_DOEPMSK_OTEPSPRM */ 460 461 #ifndef USB_OTG_DOEPINT_NAK 462 #define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */ 463 #endif /* defined USB_OTG_DOEPINT_NAK */ 464 465 #ifndef USB_OTG_DOEPMSK_NAKM 466 #define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */ 467 #endif /* defined USB_OTG_DOEPMSK_NAKM */ 468 469 #ifndef USB_OTG_DOEPINT_STPKTRX 470 #define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */ 471 #endif /* defined USB_OTG_DOEPINT_STPKTRX */ 472 473 #ifndef USB_OTG_DOEPMSK_NYETM 474 #define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */ 475 #endif /* defined USB_OTG_DOEPMSK_NYETM */ 476 #endif /* defined (USB_OTG_FS) */ 477 478 /* Private macros ------------------------------------------------------------*/ 479 /** @defgroup PCD_Private_Macros PCD Private Macros 480 * @{ 481 */ 482 #if defined (USB) 483 /******************** Bit definition for USB_COUNTn_RX register *************/ 484 #define USB_CNTRX_NBLK_MSK (0x1FU << 10) 485 #define USB_CNTRX_BLSIZE (0x1U << 15) 486 487 /* SetENDPOINT */ 488 #define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) \ 489 (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue)) 490 491 /* GetENDPOINT */ 492 #define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U))) 493 494 /* ENDPOINT transfer */ 495 #define USB_EP0StartXfer USB_EPStartXfer 496 497 /** 498 * @brief sets the type in the endpoint register(bits EP_TYPE[1:0]) 499 * @param USBx USB peripheral instance register address. 500 * @param bEpNum Endpoint Number. 501 * @param wType Endpoint Type. 502 * @retval None 503 */ 504 #define PCD_SET_EPTYPE(USBx, bEpNum, wType) \ 505 (PCD_SET_ENDPOINT((USBx), (bEpNum), \ 506 ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX))) 507 508 509 /** 510 * @brief gets the type in the endpoint register(bits EP_TYPE[1:0]) 511 * @param USBx USB peripheral instance register address. 512 * @param bEpNum Endpoint Number. 513 * @retval Endpoint Type 514 */ 515 #define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD) 516 517 /** 518 * @brief free buffer used from the application realizing it to the line 519 * toggles bit SW_BUF in the double buffered endpoint register 520 * @param USBx USB device. 521 * @param bEpNum, bDir 522 * @retval None 523 */ 524 #define PCD_FREE_USER_BUFFER(USBx, bEpNum, bDir) \ 525 do { \ 526 if ((bDir) == 0U) \ 527 { \ 528 /* OUT double buffered endpoint */ \ 529 PCD_TX_DTOG((USBx), (bEpNum)); \ 530 } \ 531 else if ((bDir) == 1U) \ 532 { \ 533 /* IN double buffered endpoint */ \ 534 PCD_RX_DTOG((USBx), (bEpNum)); \ 535 } \ 536 } while(0) 537 538 /** 539 * @brief sets the status for tx transfer (bits STAT_TX[1:0]). 540 * @param USBx USB peripheral instance register address. 541 * @param bEpNum Endpoint Number. 542 * @param wState new state 543 * @retval None 544 */ 545 #define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) \ 546 do { \ 547 uint16_t _wRegVal; \ 548 \ 549 _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \ 550 /* toggle first bit ? */ \ 551 if ((USB_EPTX_DTOG1 & (wState))!= 0U) \ 552 { \ 553 _wRegVal ^= USB_EPTX_DTOG1; \ 554 } \ 555 /* toggle second bit ? */ \ 556 if ((USB_EPTX_DTOG2 & (wState))!= 0U) \ 557 { \ 558 _wRegVal ^= USB_EPTX_DTOG2; \ 559 } \ 560 PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ 561 } while(0) /* PCD_SET_EP_TX_STATUS */ 562 563 /** 564 * @brief sets the status for rx transfer (bits STAT_TX[1:0]) 565 * @param USBx USB peripheral instance register address. 566 * @param bEpNum Endpoint Number. 567 * @param wState new state 568 * @retval None 569 */ 570 #define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) \ 571 do { \ 572 uint16_t _wRegVal; \ 573 \ 574 _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \ 575 /* toggle first bit ? */ \ 576 if ((USB_EPRX_DTOG1 & (wState))!= 0U) \ 577 { \ 578 _wRegVal ^= USB_EPRX_DTOG1; \ 579 } \ 580 /* toggle second bit ? */ \ 581 if ((USB_EPRX_DTOG2 & (wState))!= 0U) \ 582 { \ 583 _wRegVal ^= USB_EPRX_DTOG2; \ 584 } \ 585 PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ 586 } while(0) /* PCD_SET_EP_RX_STATUS */ 587 588 /** 589 * @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0]) 590 * @param USBx USB peripheral instance register address. 591 * @param bEpNum Endpoint Number. 592 * @param wStaterx new state. 593 * @param wStatetx new state. 594 * @retval None 595 */ 596 #define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) \ 597 do { \ 598 uint16_t _wRegVal; \ 599 \ 600 _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \ 601 /* toggle first bit ? */ \ 602 if ((USB_EPRX_DTOG1 & (wStaterx))!= 0U) \ 603 { \ 604 _wRegVal ^= USB_EPRX_DTOG1; \ 605 } \ 606 /* toggle second bit ? */ \ 607 if ((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \ 608 { \ 609 _wRegVal ^= USB_EPRX_DTOG2; \ 610 } \ 611 /* toggle first bit ? */ \ 612 if ((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \ 613 { \ 614 _wRegVal ^= USB_EPTX_DTOG1; \ 615 } \ 616 /* toggle second bit ? */ \ 617 if ((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \ 618 { \ 619 _wRegVal ^= USB_EPTX_DTOG2; \ 620 } \ 621 \ 622 PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ 623 } while(0) /* PCD_SET_EP_TXRX_STATUS */ 624 625 /** 626 * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0] 627 * /STAT_RX[1:0]) 628 * @param USBx USB peripheral instance register address. 629 * @param bEpNum Endpoint Number. 630 * @retval status 631 */ 632 #define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT) 633 #define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT) 634 635 /** 636 * @brief sets directly the VALID tx/rx-status into the endpoint register 637 * @param USBx USB peripheral instance register address. 638 * @param bEpNum Endpoint Number. 639 * @retval None 640 */ 641 #define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID)) 642 #define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID)) 643 644 /** 645 * @brief checks stall condition in an endpoint. 646 * @param USBx USB peripheral instance register address. 647 * @param bEpNum Endpoint Number. 648 * @retval TRUE = endpoint in stall condition. 649 */ 650 #define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) == USB_EP_TX_STALL) 651 #define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) == USB_EP_RX_STALL) 652 653 /** 654 * @brief set & clear EP_KIND bit. 655 * @param USBx USB peripheral instance register address. 656 * @param bEpNum Endpoint Number. 657 * @retval None 658 */ 659 #define PCD_SET_EP_KIND(USBx, bEpNum) \ 660 do { \ 661 uint16_t _wRegVal; \ 662 \ 663 _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ 664 \ 665 PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \ 666 } while(0) /* PCD_SET_EP_KIND */ 667 668 #define PCD_CLEAR_EP_KIND(USBx, bEpNum) \ 669 do { \ 670 uint16_t _wRegVal; \ 671 \ 672 _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \ 673 \ 674 PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ 675 } while(0) /* PCD_CLEAR_EP_KIND */ 676 677 /** 678 * @brief Sets/clears directly STATUS_OUT bit in the endpoint register. 679 * @param USBx USB peripheral instance register address. 680 * @param bEpNum Endpoint Number. 681 * @retval None 682 */ 683 #define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) 684 #define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) 685 686 /** 687 * @brief Sets/clears directly EP_KIND bit in the endpoint register. 688 * @param USBx USB peripheral instance register address. 689 * @param bEpNum Endpoint Number. 690 * @retval None 691 */ 692 #define PCD_SET_BULK_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) 693 #define PCD_CLEAR_BULK_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) 694 695 /** 696 * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. 697 * @param USBx USB peripheral instance register address. 698 * @param bEpNum Endpoint Number. 699 * @retval None 700 */ 701 #define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) \ 702 do { \ 703 uint16_t _wRegVal; \ 704 \ 705 _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \ 706 \ 707 PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \ 708 } while(0) /* PCD_CLEAR_RX_EP_CTR */ 709 710 #define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) \ 711 do { \ 712 uint16_t _wRegVal; \ 713 \ 714 _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \ 715 \ 716 PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX)); \ 717 } while(0) /* PCD_CLEAR_TX_EP_CTR */ 718 719 /** 720 * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. 721 * @param USBx USB peripheral instance register address. 722 * @param bEpNum Endpoint Number. 723 * @retval None 724 */ 725 #define PCD_RX_DTOG(USBx, bEpNum) \ 726 do { \ 727 uint16_t _wEPVal; \ 728 \ 729 _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ 730 \ 731 PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \ 732 } while(0) /* PCD_RX_DTOG */ 733 734 #define PCD_TX_DTOG(USBx, bEpNum) \ 735 do { \ 736 uint16_t _wEPVal; \ 737 \ 738 _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ 739 \ 740 PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_TX)); \ 741 } while(0) /* PCD_TX_DTOG */ 742 /** 743 * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. 744 * @param USBx USB peripheral instance register address. 745 * @param bEpNum Endpoint Number. 746 * @retval None 747 */ 748 #define PCD_CLEAR_RX_DTOG(USBx, bEpNum) \ 749 do { \ 750 uint16_t _wRegVal; \ 751 \ 752 _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \ 753 \ 754 if ((_wRegVal & USB_EP_DTOG_RX) != 0U)\ 755 { \ 756 PCD_RX_DTOG((USBx), (bEpNum)); \ 757 } \ 758 } while(0) /* PCD_CLEAR_RX_DTOG */ 759 760 #define PCD_CLEAR_TX_DTOG(USBx, bEpNum) \ 761 do { \ 762 uint16_t _wRegVal; \ 763 \ 764 _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \ 765 \ 766 if ((_wRegVal & USB_EP_DTOG_TX) != 0U)\ 767 { \ 768 PCD_TX_DTOG((USBx), (bEpNum)); \ 769 } \ 770 } while(0) /* PCD_CLEAR_TX_DTOG */ 771 772 /** 773 * @brief Sets address in an endpoint register. 774 * @param USBx USB peripheral instance register address. 775 * @param bEpNum Endpoint Number. 776 * @param bAddr Address. 777 * @retval None 778 */ 779 #define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) \ 780 do { \ 781 uint16_t _wRegVal; \ 782 \ 783 _wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \ 784 \ 785 PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ 786 } while(0) /* PCD_SET_EP_ADDRESS */ 787 788 /** 789 * @brief Gets address in an endpoint register. 790 * @param USBx USB peripheral instance register address. 791 * @param bEpNum Endpoint Number. 792 * @retval None 793 */ 794 #define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD)) 795 796 #define PCD_EP_TX_CNT(USBx, bEpNum) \ 797 ((uint16_t *)((((uint32_t)(USBx)->BTABLE + \ 798 ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U))) 799 800 #define PCD_EP_RX_CNT(USBx, bEpNum) \ 801 ((uint16_t *)((((uint32_t)(USBx)->BTABLE + \ 802 ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U))) 803 804 805 /** 806 * @brief sets address of the tx/rx buffer. 807 * @param USBx USB peripheral instance register address. 808 * @param bEpNum Endpoint Number. 809 * @param wAddr address to be set (must be word aligned). 810 * @retval None 811 */ 812 #define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) \ 813 do { \ 814 __IO uint16_t *_wRegVal; \ 815 uint32_t _wRegBase = (uint32_t)USBx; \ 816 \ 817 _wRegBase += (uint32_t)(USBx)->BTABLE; \ 818 _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \ 819 *_wRegVal = ((wAddr) >> 1) << 1; \ 820 } while(0) /* PCD_SET_EP_TX_ADDRESS */ 821 822 #define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) \ 823 do { \ 824 __IO uint16_t *_wRegVal; \ 825 uint32_t _wRegBase = (uint32_t)USBx; \ 826 \ 827 _wRegBase += (uint32_t)(USBx)->BTABLE; \ 828 _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \ 829 *_wRegVal = ((wAddr) >> 1) << 1; \ 830 } while(0) /* PCD_SET_EP_RX_ADDRESS */ 831 832 /** 833 * @brief Gets address of the tx/rx buffer. 834 * @param USBx USB peripheral instance register address. 835 * @param bEpNum Endpoint Number. 836 * @retval address of the buffer. 837 */ 838 #define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum))) 839 #define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum))) 840 841 /** 842 * @brief Sets counter of rx buffer with no. of blocks. 843 * @param pdwReg Register pointer 844 * @param wCount Counter. 845 * @param wNBlocks no. of Blocks. 846 * @retval None 847 */ 848 #define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) \ 849 do { \ 850 (wNBlocks) = (wCount) >> 5; \ 851 if (((wCount) & 0x1fU) == 0U) \ 852 { \ 853 (wNBlocks)--; \ 854 } \ 855 *(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \ 856 } while(0) /* PCD_CALC_BLK32 */ 857 858 #define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) \ 859 do { \ 860 (wNBlocks) = (wCount) >> 1; \ 861 if (((wCount) & 0x1U) != 0U) \ 862 { \ 863 (wNBlocks)++; \ 864 } \ 865 *(pdwReg) = (uint16_t)((wNBlocks) << 10); \ 866 } while(0) /* PCD_CALC_BLK2 */ 867 868 #define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \ 869 do { \ 870 uint32_t wNBlocks; \ 871 \ 872 if ((wCount) > 62U) \ 873 { \ 874 PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ 875 } \ 876 else \ 877 { \ 878 if ((wCount) == 0U) \ 879 { \ 880 *(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \ 881 *(pdwReg) |= USB_CNTRX_BLSIZE; \ 882 } \ 883 else \ 884 { \ 885 PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ 886 } \ 887 } \ 888 } while(0) /* PCD_SET_EP_CNT_RX_REG */ 889 890 #define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) \ 891 do { \ 892 uint32_t _wRegBase = (uint32_t)(USBx); \ 893 __IO uint16_t *pdwReg; \ 894 \ 895 _wRegBase += (uint32_t)(USBx)->BTABLE; \ 896 pdwReg = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \ 897 PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \ 898 } while(0) 899 900 /** 901 * @brief sets counter for the tx/rx buffer. 902 * @param USBx USB peripheral instance register address. 903 * @param bEpNum Endpoint Number. 904 * @param wCount Counter value. 905 * @retval None 906 */ 907 #define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) \ 908 do { \ 909 uint32_t _wRegBase = (uint32_t)(USBx); \ 910 __IO uint16_t *_wRegVal; \ 911 \ 912 _wRegBase += (uint32_t)(USBx)->BTABLE; \ 913 _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \ 914 *_wRegVal = (uint16_t)(wCount); \ 915 } while(0) 916 917 #define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) \ 918 do { \ 919 uint32_t _wRegBase = (uint32_t)(USBx); \ 920 __IO uint16_t *_wRegVal; \ 921 \ 922 _wRegBase += (uint32_t)(USBx)->BTABLE; \ 923 _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \ 924 PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \ 925 } while(0) 926 927 /** 928 * @brief gets counter of the tx buffer. 929 * @param USBx USB peripheral instance register address. 930 * @param bEpNum Endpoint Number. 931 * @retval Counter value 932 */ 933 #define PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU) 934 #define PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU) 935 936 /** 937 * @brief Sets buffer 0/1 address in a double buffer endpoint. 938 * @param USBx USB peripheral instance register address. 939 * @param bEpNum Endpoint Number. 940 * @param wBuf0Addr buffer 0 address. 941 * @retval Counter value 942 */ 943 #define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) \ 944 do { \ 945 PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \ 946 } while(0) /* PCD_SET_EP_DBUF0_ADDR */ 947 948 #define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) \ 949 do { \ 950 PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \ 951 } while(0) /* PCD_SET_EP_DBUF1_ADDR */ 952 953 /** 954 * @brief Sets addresses in a double buffer endpoint. 955 * @param USBx USB peripheral instance register address. 956 * @param bEpNum Endpoint Number. 957 * @param wBuf0Addr: buffer 0 address. 958 * @param wBuf1Addr = buffer 1 address. 959 * @retval None 960 */ 961 #define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) \ 962 do { \ 963 PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \ 964 PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \ 965 } while(0) /* PCD_SET_EP_DBUF_ADDR */ 966 967 /** 968 * @brief Gets buffer 0/1 address of a double buffer endpoint. 969 * @param USBx USB peripheral instance register address. 970 * @param bEpNum Endpoint Number. 971 * @retval None 972 */ 973 #define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum))) 974 #define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum))) 975 976 /** 977 * @brief Gets buffer 0/1 address of a double buffer endpoint. 978 * @param USBx USB peripheral instance register address. 979 * @param bEpNum Endpoint Number. 980 * @param bDir endpoint dir EP_DBUF_OUT = OUT 981 * EP_DBUF_IN = IN 982 * @param wCount: Counter value 983 * @retval None 984 */ 985 #define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) \ 986 do { \ 987 if ((bDir) == 0U) \ 988 /* OUT endpoint */ \ 989 { \ 990 PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum), (wCount)); \ 991 } \ 992 else \ 993 { \ 994 if ((bDir) == 1U) \ 995 { \ 996 /* IN endpoint */ \ 997 PCD_SET_EP_TX_CNT((USBx), (bEpNum), (wCount)); \ 998 } \ 999 } \ 1000 } while(0) /* SetEPDblBuf0Count*/ 1001 1002 #define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) \ 1003 do { \ 1004 uint32_t _wBase = (uint32_t)(USBx); \ 1005 __IO uint16_t *_wEPRegVal; \ 1006 \ 1007 if ((bDir) == 0U) \ 1008 { \ 1009 /* OUT endpoint */ \ 1010 PCD_SET_EP_RX_CNT((USBx), (bEpNum), (wCount)); \ 1011 } \ 1012 else \ 1013 { \ 1014 if ((bDir) == 1U) \ 1015 { \ 1016 /* IN endpoint */ \ 1017 _wBase += (uint32_t)(USBx)->BTABLE; \ 1018 _wEPRegVal = (__IO uint16_t *)(_wBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \ 1019 *_wEPRegVal = (uint16_t)(wCount); \ 1020 } \ 1021 } \ 1022 } while(0) /* SetEPDblBuf1Count */ 1023 1024 #define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) \ 1025 do { \ 1026 PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \ 1027 PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \ 1028 } while(0) /* PCD_SET_EP_DBUF_CNT */ 1029 1030 /** 1031 * @brief Gets buffer 0/1 rx/tx counter for double buffering. 1032 * @param USBx USB peripheral instance register address. 1033 * @param bEpNum Endpoint Number. 1034 * @retval None 1035 */ 1036 #define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum))) 1037 #define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum))) 1038 1039 #endif /* defined (USB) */ 1040 1041 /** 1042 * @} 1043 */ 1044 1045 /** 1046 * @} 1047 */ 1048 1049 /** 1050 * @} 1051 */ 1052 #endif /* defined (USB) || defined (USB_OTG_FS) */ 1053 1054 #ifdef __cplusplus 1055 } 1056 #endif 1057 1058 #endif /* STM32L4xx_HAL_PCD_H */ 1059
