1 /** 2 ****************************************************************************** 3 * @file stm32l152xb.h 4 * @author MCD Application Team 5 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 6 * This file contains all the peripheral register's definitions, bits 7 * definitions and memory mapping for STM32L1xx devices. 8 * 9 * This file contains: 10 * - Data structures and the address mapping for all peripherals 11 * - Peripheral's registers declarations and bits definition 12 * - Macros to access peripheral�s registers hardware 13 * 14 ****************************************************************************** 15 * @attention 16 * 17 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 18 * All rights reserved.</center></h2> 19 * 20 * This software component is licensed by ST under BSD 3-Clause license, 21 * the "License"; You may not use this file except in compliance with the 22 * License. You may obtain a copy of the License at: 23 * opensource.org/licenses/BSD-3-Clause 24 * 25 ****************************************************************************** 26 */ 27 28 /** @addtogroup CMSIS 29 * @{ 30 */ 31 32 /** @addtogroup stm32l152xb 33 * @{ 34 */ 35 36 #ifndef __STM32L152xB_H 37 #define __STM32L152xB_H 38 39 #ifdef __cplusplus 40 extern "C" { 41 #endif 42 43 44 /** @addtogroup Configuration_section_for_CMSIS 45 * @{ 46 */ 47 /** 48 * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 49 */ 50 #define __CM3_REV 0x200U /*!< Cortex-M3 Revision r2p0 */ 51 #define __MPU_PRESENT 1U /*!< STM32L1xx provides MPU */ 52 #define __NVIC_PRIO_BITS 4U /*!< STM32L1xx uses 4 Bits for the Priority Levels */ 53 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ 54 55 /** 56 * @} 57 */ 58 59 /** @addtogroup Peripheral_interrupt_number_definition 60 * @{ 61 */ 62 63 /** 64 * @brief STM32L1xx Interrupt Number Definition, according to the selected device 65 * in @ref Library_configuration_section 66 */ 67 68 /*!< Interrupt Number Definition */ 69 typedef enum 70 { 71 /****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ 72 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 73 HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ 74 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ 75 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ 76 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ 77 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ 78 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ 79 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ 80 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ 81 82 /****** STM32L specific Interrupt Numbers ***********************************************************/ 83 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 84 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ 85 TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ 86 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ 87 FLASH_IRQn = 4, /*!< FLASH global Interrupt */ 88 RCC_IRQn = 5, /*!< RCC global Interrupt */ 89 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ 90 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ 91 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ 92 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ 93 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ 94 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ 95 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ 96 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ 97 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ 98 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ 99 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ 100 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ 101 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ 102 USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ 103 USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */ 104 DAC_IRQn = 21, /*!< DAC Interrupt */ 105 COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */ 106 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ 107 LCD_IRQn = 24, /*!< LCD Interrupt */ 108 TIM9_IRQn = 25, /*!< TIM9 global Interrupt */ 109 TIM10_IRQn = 26, /*!< TIM10 global Interrupt */ 110 TIM11_IRQn = 27, /*!< TIM11 global Interrupt */ 111 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ 112 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ 113 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ 114 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ 115 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ 116 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ 117 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ 118 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ 119 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ 120 USART1_IRQn = 37, /*!< USART1 global Interrupt */ 121 USART2_IRQn = 38, /*!< USART2 global Interrupt */ 122 USART3_IRQn = 39, /*!< USART3 global Interrupt */ 123 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ 124 RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ 125 USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */ 126 TIM6_IRQn = 43, /*!< TIM6 global Interrupt */ 127 TIM7_IRQn = 44, /*!< TIM7 global Interrupt */ 128 } IRQn_Type; 129 130 /** 131 * @} 132 */ 133 134 #include "core_cm3.h" 135 #include "system_stm32l1xx.h" 136 #include <stdint.h> 137 138 /** @addtogroup Peripheral_registers_structures 139 * @{ 140 */ 141 142 /** 143 * @brief Analog to Digital Converter 144 */ 145 146 typedef struct 147 { 148 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ 149 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ 150 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ 151 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ 152 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ 153 __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */ 154 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */ 155 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */ 156 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */ 157 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */ 158 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */ 159 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */ 160 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ 161 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ 162 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ 163 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ 164 __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */ 165 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */ 166 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */ 167 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */ 168 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */ 169 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */ 170 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */ 171 uint32_t RESERVED; /*!< Reserved, Address offset: 0x5C */ 172 } ADC_TypeDef; 173 174 typedef struct 175 { 176 __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ 177 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ 178 } ADC_Common_TypeDef; 179 180 /** 181 * @brief Comparator 182 */ 183 184 typedef struct 185 { 186 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ 187 } COMP_TypeDef; 188 189 typedef struct 190 { 191 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ 192 } COMP_Common_TypeDef; 193 194 /** 195 * @brief CRC calculation unit 196 */ 197 198 typedef struct 199 { 200 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ 201 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ 202 uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ 203 uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ 204 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ 205 } CRC_TypeDef; 206 207 /** 208 * @brief Digital to Analog Converter 209 */ 210 211 typedef struct 212 { 213 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ 214 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ 215 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ 216 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ 217 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ 218 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ 219 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ 220 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ 221 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ 222 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ 223 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ 224 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ 225 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ 226 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ 227 } DAC_TypeDef; 228 229 /** 230 * @brief Debug MCU 231 */ 232 233 typedef struct 234 { 235 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ 236 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ 237 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ 238 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ 239 }DBGMCU_TypeDef; 240 241 /** 242 * @brief DMA Controller 243 */ 244 245 typedef struct 246 { 247 __IO uint32_t CCR; /*!< DMA channel x configuration register */ 248 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ 249 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ 250 __IO uint32_t CMAR; /*!< DMA channel x memory address register */ 251 } DMA_Channel_TypeDef; 252 253 typedef struct 254 { 255 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ 256 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ 257 } DMA_TypeDef; 258 259 /** 260 * @brief External Interrupt/Event Controller 261 */ 262 263 typedef struct 264 { 265 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */ 266 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */ 267 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */ 268 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */ 269 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */ 270 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */ 271 } EXTI_TypeDef; 272 273 /** 274 * @brief FLASH Registers 275 */ 276 typedef struct 277 { 278 __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */ 279 __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */ 280 __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */ 281 __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */ 282 __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */ 283 __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */ 284 __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */ 285 __IO uint32_t OBR; /*!< Option byte register, Address offset: 0x1c */ 286 __IO uint32_t WRPR1; /*!< Write protection register 1, Address offset: 0x20 */ 287 } FLASH_TypeDef; 288 289 /** 290 * @brief Option Bytes Registers 291 */ 292 typedef struct 293 { 294 __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */ 295 __IO uint32_t USER; /*!< user register, Address offset: 0x04 */ 296 __IO uint32_t WRP01; /*!< write protection register 0 1, Address offset: 0x08 */ 297 __IO uint32_t WRP23; /*!< write protection register 2 3, Address offset: 0x0C */ 298 } OB_TypeDef; 299 300 /** 301 * @brief General Purpose IO 302 */ 303 304 typedef struct 305 { 306 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ 307 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ 308 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ 309 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ 310 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ 311 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ 312 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */ 313 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ 314 __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */ 315 } GPIO_TypeDef; 316 317 /** 318 * @brief SysTem Configuration 319 */ 320 321 typedef struct 322 { 323 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ 324 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ 325 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ 326 } SYSCFG_TypeDef; 327 328 /** 329 * @brief Inter-integrated Circuit Interface 330 */ 331 332 typedef struct 333 { 334 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ 335 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ 336 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ 337 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ 338 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */ 339 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ 340 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ 341 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ 342 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ 343 } I2C_TypeDef; 344 345 /** 346 * @brief Independent WATCHDOG 347 */ 348 349 typedef struct 350 { 351 __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ 352 __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ 353 __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ 354 __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ 355 } IWDG_TypeDef; 356 357 /** 358 * @brief LCD 359 */ 360 361 typedef struct 362 { 363 __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ 364 __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ 365 __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ 366 __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ 367 uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ 368 __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ 369 } LCD_TypeDef; 370 371 /** 372 * @brief Power Control 373 */ 374 375 typedef struct 376 { 377 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ 378 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ 379 } PWR_TypeDef; 380 381 /** 382 * @brief Reset and Clock Control 383 */ 384 385 typedef struct 386 { 387 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ 388 __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */ 389 __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x08 */ 390 __IO uint32_t CIR; /*!< RCC Clock interrupt register, Address offset: 0x0C */ 391 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x10 */ 392 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x14 */ 393 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x18 */ 394 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x1C */ 395 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x20 */ 396 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x24 */ 397 __IO uint32_t AHBLPENR; /*!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 */ 398 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C */ 399 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 */ 400 __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x34 */ 401 } RCC_TypeDef; 402 403 /** 404 * @brief Routing Interface 405 */ 406 407 typedef struct 408 { 409 __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ 410 __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ 411 __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ 412 __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ 413 __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ 414 __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ 415 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */ 416 } RI_TypeDef; 417 418 /** 419 * @brief Real-Time Clock 420 */ 421 typedef struct 422 { 423 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ 424 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ 425 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ 426 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ 427 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ 428 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ 429 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ 430 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ 431 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ 432 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ 433 uint32_t RESERVED1; /*!< Reserved, 0x28 */ 434 uint32_t RESERVED2; /*!< Reserved, 0x2C */ 435 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ 436 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ 437 uint32_t RESERVED3; /*!< Reserved, 0x38 */ 438 uint32_t RESERVED4; /*!< Reserved, 0x3C */ 439 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ 440 uint32_t RESERVED5; /*!< Reserved, 0x44 */ 441 uint32_t RESERVED6; /*!< Reserved, 0x48 */ 442 uint32_t RESERVED7; /*!< Reserved, 0x4C */ 443 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ 444 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ 445 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ 446 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ 447 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ 448 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ 449 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ 450 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ 451 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ 452 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ 453 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ 454 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ 455 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ 456 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ 457 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ 458 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ 459 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ 460 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ 461 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ 462 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ 463 } RTC_TypeDef; 464 465 /** 466 * @brief Serial Peripheral Interface 467 */ 468 469 typedef struct 470 { 471 __IO uint32_t CR1; /*!< SPI Control register 1 Address offset: 0x00 */ 472 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ 473 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ 474 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ 475 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register Address offset: 0x10 */ 476 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register Address offset: 0x14 */ 477 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register Address offset: 0x18 */ 478 } SPI_TypeDef; 479 480 /** 481 * @brief TIM 482 */ 483 typedef struct 484 { 485 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ 486 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ 487 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ 488 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ 489 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ 490 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ 491 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ 492 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ 493 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ 494 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ 495 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ 496 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ 497 uint32_t RESERVED12; /*!< Reserved, 0x30 */ 498 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ 499 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ 500 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ 501 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ 502 uint32_t RESERVED17; /*!< Reserved, 0x44 */ 503 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ 504 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ 505 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ 506 } TIM_TypeDef; 507 /** 508 * @brief Universal Synchronous Asynchronous Receiver Transmitter 509 */ 510 511 typedef struct 512 { 513 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ 514 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ 515 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ 516 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ 517 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ 518 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ 519 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ 520 } USART_TypeDef; 521 522 /** 523 * @brief Universal Serial Bus Full Speed Device 524 */ 525 526 typedef struct 527 { 528 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ 529 __IO uint16_t RESERVED0; /*!< Reserved */ 530 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ 531 __IO uint16_t RESERVED1; /*!< Reserved */ 532 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ 533 __IO uint16_t RESERVED2; /*!< Reserved */ 534 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ 535 __IO uint16_t RESERVED3; /*!< Reserved */ 536 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ 537 __IO uint16_t RESERVED4; /*!< Reserved */ 538 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ 539 __IO uint16_t RESERVED5; /*!< Reserved */ 540 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ 541 __IO uint16_t RESERVED6; /*!< Reserved */ 542 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ 543 __IO uint16_t RESERVED7[17]; /*!< Reserved */ 544 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ 545 __IO uint16_t RESERVED8; /*!< Reserved */ 546 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ 547 __IO uint16_t RESERVED9; /*!< Reserved */ 548 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ 549 __IO uint16_t RESERVEDA; /*!< Reserved */ 550 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ 551 __IO uint16_t RESERVEDB; /*!< Reserved */ 552 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ 553 __IO uint16_t RESERVEDC; /*!< Reserved */ 554 } USB_TypeDef; 555 556 /** 557 * @brief Window WATCHDOG 558 */ 559 typedef struct 560 { 561 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ 562 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ 563 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ 564 } WWDG_TypeDef; 565 566 /** 567 * @brief Universal Serial Bus Full Speed Device 568 */ 569 /** 570 * @} 571 */ 572 573 /** @addtogroup Peripheral_memory_map 574 * @{ 575 */ 576 577 #define FLASH_BASE (0x08000000UL) /*!< FLASH base address in the alias region */ 578 #define FLASH_EEPROM_BASE (FLASH_BASE + 0x80000UL) /*!< FLASH EEPROM base address in the alias region */ 579 #define SRAM_BASE (0x20000000UL) /*!< SRAM base address in the alias region */ 580 #define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address in the alias region */ 581 #define SRAM_BB_BASE (0x22000000UL) /*!< SRAM base address in the bit-band region */ 582 #define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ 583 #define FLASH_END (0x0801FFFFUL) /*!< Program end FLASH address for Cat1 & Cat2 */ 584 #define FLASH_EEPROM_END (0x08080FFFUL) /*!< FLASH EEPROM end address (4KB) */ 585 586 /*!< Peripheral memory map */ 587 #define APB1PERIPH_BASE PERIPH_BASE 588 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) 589 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) 590 591 /*!< APB1 peripherals */ 592 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) 593 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL) 594 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL) 595 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL) 596 #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400UL) 597 #define LCD_BASE (APB1PERIPH_BASE + 0x00002400UL) 598 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) 599 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL) 600 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL) 601 #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL) 602 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL) 603 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800UL) 604 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) 605 #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL) 606 607 /* USB device FS */ 608 #define USB_BASE (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */ 609 #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */ 610 611 /* USB device FS SRAM */ 612 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000UL) 613 #define DAC_BASE (APB1PERIPH_BASE + 0x00007400UL) 614 #define COMP_BASE (APB1PERIPH_BASE + 0x00007C00UL) 615 #define RI_BASE (APB1PERIPH_BASE + 0x00007C04UL) 616 617 /*!< APB2 peripherals */ 618 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000UL) 619 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL) 620 #define TIM9_BASE (APB2PERIPH_BASE + 0x00000800UL) 621 #define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00UL) 622 #define TIM11_BASE (APB2PERIPH_BASE + 0x00001000UL) 623 #define ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL) 624 #define ADC_BASE (APB2PERIPH_BASE + 0x00002700UL) 625 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL) 626 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL) 627 628 /*!< AHB peripherals */ 629 #define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000UL) 630 #define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400UL) 631 #define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800UL) 632 #define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00UL) 633 #define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000UL) 634 #define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400UL) 635 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) 636 #define RCC_BASE (AHBPERIPH_BASE + 0x00003800UL) 637 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00UL) /*!< FLASH registers base address */ 638 #define OB_BASE (0x1FF80000UL) /*!< FLASH Option Bytes base address */ 639 #define FLASHSIZE_BASE (0x1FF8004CUL) /*!< FLASH Size register base address for Cat.1 and Cat.2 devices */ 640 #define UID_BASE (0x1FF80050UL) /*!< Unique device ID register base address for Cat.1 and Cat.2 devices */ 641 #define DMA1_BASE (AHBPERIPH_BASE + 0x00006000UL) 642 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) 643 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) 644 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) 645 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) 646 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) 647 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) 648 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) 649 #define DBGMCU_BASE (0xE0042000UL) /*!< Debug MCU registers base address */ 650 651 /** 652 * @} 653 */ 654 655 /** @addtogroup Peripheral_declaration 656 * @{ 657 */ 658 659 #define TIM2 ((TIM_TypeDef *) TIM2_BASE) 660 #define TIM3 ((TIM_TypeDef *) TIM3_BASE) 661 #define TIM4 ((TIM_TypeDef *) TIM4_BASE) 662 #define TIM6 ((TIM_TypeDef *) TIM6_BASE) 663 #define TIM7 ((TIM_TypeDef *) TIM7_BASE) 664 #define LCD ((LCD_TypeDef *) LCD_BASE) 665 #define RTC ((RTC_TypeDef *) RTC_BASE) 666 #define WWDG ((WWDG_TypeDef *) WWDG_BASE) 667 #define IWDG ((IWDG_TypeDef *) IWDG_BASE) 668 #define SPI2 ((SPI_TypeDef *) SPI2_BASE) 669 #define USART2 ((USART_TypeDef *) USART2_BASE) 670 #define USART3 ((USART_TypeDef *) USART3_BASE) 671 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) 672 #define I2C2 ((I2C_TypeDef *) I2C2_BASE) 673 /* USB device FS */ 674 #define USB ((USB_TypeDef *) USB_BASE) 675 /* USB device FS SRAM */ 676 #define PWR ((PWR_TypeDef *) PWR_BASE) 677 678 #define DAC1 ((DAC_TypeDef *) DAC_BASE) 679 /* Legacy define */ 680 #define DAC DAC1 681 682 #define COMP ((COMP_TypeDef *) COMP_BASE) /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */ 683 #define COMP1 ((COMP_TypeDef *) COMP_BASE) /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */ 684 #define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */ 685 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP_BASE) /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */ 686 687 #define RI ((RI_TypeDef *) RI_BASE) 688 689 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) 690 #define EXTI ((EXTI_TypeDef *) EXTI_BASE) 691 #define TIM9 ((TIM_TypeDef *) TIM9_BASE) 692 #define TIM10 ((TIM_TypeDef *) TIM10_BASE) 693 #define TIM11 ((TIM_TypeDef *) TIM11_BASE) 694 695 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) 696 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE) 697 /* Legacy defines */ 698 #define ADC ADC1_COMMON 699 700 #define SPI1 ((SPI_TypeDef *) SPI1_BASE) 701 #define USART1 ((USART_TypeDef *) USART1_BASE) 702 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 703 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 704 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 705 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) 706 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) 707 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) 708 #define CRC ((CRC_TypeDef *) CRC_BASE) 709 #define RCC ((RCC_TypeDef *) RCC_BASE) 710 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) 711 #define OB ((OB_TypeDef *) OB_BASE) 712 #define DMA1 ((DMA_TypeDef *) DMA1_BASE) 713 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) 714 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) 715 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) 716 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) 717 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) 718 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) 719 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) 720 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) 721 722 /** 723 * @} 724 */ 725 726 /** @addtogroup Exported_constants 727 * @{ 728 */ 729 730 /** @addtogroup Hardware_Constant_Definition 731 * @{ 732 */ 733 #define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */ 734 735 /** 736 * @} 737 */ 738 739 /** @addtogroup Peripheral_Registers_Bits_Definition 740 * @{ 741 */ 742 743 /******************************************************************************/ 744 /* Peripheral Registers Bits Definition */ 745 /******************************************************************************/ 746 /******************************************************************************/ 747 /* */ 748 /* Analog to Digital Converter (ADC) */ 749 /* */ 750 /******************************************************************************/ 751 #define VREFINT_CAL_ADDR_CMSIS 0x1FF80078 /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ 752 #define TEMPSENSOR_CAL1_ADDR_CMSIS 0x1FF8007A /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ 753 #define TEMPSENSOR_CAL2_ADDR_CMSIS 0x1FF8007E /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ 754 755 /******************** Bit definition for ADC_SR register ********************/ 756 #define ADC_SR_AWD_Pos (0U) 757 #define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */ 758 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */ 759 #define ADC_SR_EOCS_Pos (1U) 760 #define ADC_SR_EOCS_Msk (0x1UL << ADC_SR_EOCS_Pos) /*!< 0x00000002 */ 761 #define ADC_SR_EOCS ADC_SR_EOCS_Msk /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */ 762 #define ADC_SR_JEOS_Pos (2U) 763 #define ADC_SR_JEOS_Msk (0x1UL << ADC_SR_JEOS_Pos) /*!< 0x00000004 */ 764 #define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ 765 #define ADC_SR_JSTRT_Pos (3U) 766 #define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ 767 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */ 768 #define ADC_SR_STRT_Pos (4U) 769 #define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000010 */ 770 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */ 771 #define ADC_SR_OVR_Pos (5U) 772 #define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos) /*!< 0x00000020 */ 773 #define ADC_SR_OVR ADC_SR_OVR_Msk /*!< ADC group regular overrun flag */ 774 #define ADC_SR_ADONS_Pos (6U) 775 #define ADC_SR_ADONS_Msk (0x1UL << ADC_SR_ADONS_Pos) /*!< 0x00000040 */ 776 #define ADC_SR_ADONS ADC_SR_ADONS_Msk /*!< ADC ready flag */ 777 #define ADC_SR_RCNR_Pos (8U) 778 #define ADC_SR_RCNR_Msk (0x1UL << ADC_SR_RCNR_Pos) /*!< 0x00000100 */ 779 #define ADC_SR_RCNR ADC_SR_RCNR_Msk /*!< ADC group regular not ready flag */ 780 #define ADC_SR_JCNR_Pos (9U) 781 #define ADC_SR_JCNR_Msk (0x1UL << ADC_SR_JCNR_Pos) /*!< 0x00000200 */ 782 #define ADC_SR_JCNR ADC_SR_JCNR_Msk /*!< ADC group injected not ready flag */ 783 784 /* Legacy defines */ 785 #define ADC_SR_EOC (ADC_SR_EOCS) 786 #define ADC_SR_JEOC (ADC_SR_JEOS) 787 788 /******************* Bit definition for ADC_CR1 register ********************/ 789 #define ADC_CR1_AWDCH_Pos (0U) 790 #define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ 791 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ 792 #define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ 793 #define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ 794 #define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ 795 #define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ 796 #define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ 797 798 #define ADC_CR1_EOCSIE_Pos (5U) 799 #define ADC_CR1_EOCSIE_Msk (0x1UL << ADC_CR1_EOCSIE_Pos) /*!< 0x00000020 */ 800 #define ADC_CR1_EOCSIE ADC_CR1_EOCSIE_Msk /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */ 801 #define ADC_CR1_AWDIE_Pos (6U) 802 #define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ 803 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */ 804 #define ADC_CR1_JEOSIE_Pos (7U) 805 #define ADC_CR1_JEOSIE_Msk (0x1UL << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */ 806 #define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ 807 #define ADC_CR1_SCAN_Pos (8U) 808 #define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ 809 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */ 810 #define ADC_CR1_AWDSGL_Pos (9U) 811 #define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ 812 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ 813 #define ADC_CR1_JAUTO_Pos (10U) 814 #define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ 815 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ 816 #define ADC_CR1_DISCEN_Pos (11U) 817 #define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ 818 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ 819 #define ADC_CR1_JDISCEN_Pos (12U) 820 #define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ 821 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ 822 823 #define ADC_CR1_DISCNUM_Pos (13U) 824 #define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ 825 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ 826 #define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ 827 #define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ 828 #define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ 829 830 #define ADC_CR1_PDD_Pos (16U) 831 #define ADC_CR1_PDD_Msk (0x1UL << ADC_CR1_PDD_Pos) /*!< 0x00010000 */ 832 #define ADC_CR1_PDD ADC_CR1_PDD_Msk /*!< ADC power down during auto delay phase */ 833 #define ADC_CR1_PDI_Pos (17U) 834 #define ADC_CR1_PDI_Msk (0x1UL << ADC_CR1_PDI_Pos) /*!< 0x00020000 */ 835 #define ADC_CR1_PDI ADC_CR1_PDI_Msk /*!< ADC power down during idle phase */ 836 837 #define ADC_CR1_JAWDEN_Pos (22U) 838 #define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ 839 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ 840 #define ADC_CR1_AWDEN_Pos (23U) 841 #define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ 842 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ 843 844 #define ADC_CR1_RES_Pos (24U) 845 #define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos) /*!< 0x03000000 */ 846 #define ADC_CR1_RES ADC_CR1_RES_Msk /*!< ADC resolution */ 847 #define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos) /*!< 0x01000000 */ 848 #define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos) /*!< 0x02000000 */ 849 850 #define ADC_CR1_OVRIE_Pos (26U) 851 #define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */ 852 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!< ADC group regular overrun interrupt */ 853 854 /* Legacy defines */ 855 #define ADC_CR1_EOCIE (ADC_CR1_EOCSIE) 856 #define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE) 857 858 /******************* Bit definition for ADC_CR2 register ********************/ 859 #define ADC_CR2_ADON_Pos (0U) 860 #define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ 861 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */ 862 #define ADC_CR2_CONT_Pos (1U) 863 #define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ 864 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */ 865 866 #define ADC_CR2_DELS_Pos (4U) 867 #define ADC_CR2_DELS_Msk (0x7UL << ADC_CR2_DELS_Pos) /*!< 0x00000070 */ 868 #define ADC_CR2_DELS ADC_CR2_DELS_Msk /*!< ADC auto delay selection */ 869 #define ADC_CR2_DELS_0 (0x1UL << ADC_CR2_DELS_Pos) /*!< 0x00000010 */ 870 #define ADC_CR2_DELS_1 (0x2UL << ADC_CR2_DELS_Pos) /*!< 0x00000020 */ 871 #define ADC_CR2_DELS_2 (0x4UL << ADC_CR2_DELS_Pos) /*!< 0x00000040 */ 872 873 #define ADC_CR2_DMA_Pos (8U) 874 #define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ 875 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */ 876 #define ADC_CR2_DDS_Pos (9U) 877 #define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos) /*!< 0x00000200 */ 878 #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!< ADC DMA transfer configuration */ 879 #define ADC_CR2_EOCS_Pos (10U) 880 #define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */ 881 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */ 882 #define ADC_CR2_ALIGN_Pos (11U) 883 #define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ 884 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */ 885 886 #define ADC_CR2_JEXTSEL_Pos (16U) 887 #define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */ 888 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */ 889 #define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */ 890 #define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */ 891 #define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */ 892 #define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */ 893 894 #define ADC_CR2_JEXTEN_Pos (20U) 895 #define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */ 896 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ 897 #define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */ 898 #define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */ 899 900 #define ADC_CR2_JSWSTART_Pos (22U) 901 #define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */ 902 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */ 903 904 #define ADC_CR2_EXTSEL_Pos (24U) 905 #define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */ 906 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */ 907 #define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */ 908 #define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */ 909 #define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */ 910 #define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */ 911 912 #define ADC_CR2_EXTEN_Pos (28U) 913 #define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */ 914 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!< ADC group regular external trigger polarity */ 915 #define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */ 916 #define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */ 917 918 #define ADC_CR2_SWSTART_Pos (30U) 919 #define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */ 920 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */ 921 922 /****************** Bit definition for ADC_SMPR1 register *******************/ 923 #define ADC_SMPR1_SMP20_Pos (0U) 924 #define ADC_SMPR1_SMP20_Msk (0x7UL << ADC_SMPR1_SMP20_Pos) /*!< 0x00000007 */ 925 #define ADC_SMPR1_SMP20 ADC_SMPR1_SMP20_Msk /*!< ADC channel 20 sampling time selection */ 926 #define ADC_SMPR1_SMP20_0 (0x1UL << ADC_SMPR1_SMP20_Pos) /*!< 0x00000001 */ 927 #define ADC_SMPR1_SMP20_1 (0x2UL << ADC_SMPR1_SMP20_Pos) /*!< 0x00000002 */ 928 #define ADC_SMPR1_SMP20_2 (0x4UL << ADC_SMPR1_SMP20_Pos) /*!< 0x00000004 */ 929 930 #define ADC_SMPR1_SMP21_Pos (3U) 931 #define ADC_SMPR1_SMP21_Msk (0x7UL << ADC_SMPR1_SMP21_Pos) /*!< 0x00000038 */ 932 #define ADC_SMPR1_SMP21 ADC_SMPR1_SMP21_Msk /*!< ADC channel 21 sampling time selection */ 933 #define ADC_SMPR1_SMP21_0 (0x1UL << ADC_SMPR1_SMP21_Pos) /*!< 0x00000008 */ 934 #define ADC_SMPR1_SMP21_1 (0x2UL << ADC_SMPR1_SMP21_Pos) /*!< 0x00000010 */ 935 #define ADC_SMPR1_SMP21_2 (0x4UL << ADC_SMPR1_SMP21_Pos) /*!< 0x00000020 */ 936 937 #define ADC_SMPR1_SMP22_Pos (6U) 938 #define ADC_SMPR1_SMP22_Msk (0x7UL << ADC_SMPR1_SMP22_Pos) /*!< 0x000001C0 */ 939 #define ADC_SMPR1_SMP22 ADC_SMPR1_SMP22_Msk /*!< ADC channel 22 sampling time selection */ 940 #define ADC_SMPR1_SMP22_0 (0x1UL << ADC_SMPR1_SMP22_Pos) /*!< 0x00000040 */ 941 #define ADC_SMPR1_SMP22_1 (0x2UL << ADC_SMPR1_SMP22_Pos) /*!< 0x00000080 */ 942 #define ADC_SMPR1_SMP22_2 (0x4UL << ADC_SMPR1_SMP22_Pos) /*!< 0x00000100 */ 943 944 #define ADC_SMPR1_SMP23_Pos (9U) 945 #define ADC_SMPR1_SMP23_Msk (0x7UL << ADC_SMPR1_SMP23_Pos) /*!< 0x00000E00 */ 946 #define ADC_SMPR1_SMP23 ADC_SMPR1_SMP23_Msk /*!< ADC channel 23 sampling time selection */ 947 #define ADC_SMPR1_SMP23_0 (0x1UL << ADC_SMPR1_SMP23_Pos) /*!< 0x00000200 */ 948 #define ADC_SMPR1_SMP23_1 (0x2UL << ADC_SMPR1_SMP23_Pos) /*!< 0x00000400 */ 949 #define ADC_SMPR1_SMP23_2 (0x4UL << ADC_SMPR1_SMP23_Pos) /*!< 0x00000800 */ 950 951 #define ADC_SMPR1_SMP24_Pos (12U) 952 #define ADC_SMPR1_SMP24_Msk (0x7UL << ADC_SMPR1_SMP24_Pos) /*!< 0x00007000 */ 953 #define ADC_SMPR1_SMP24 ADC_SMPR1_SMP24_Msk /*!< ADC channel 24 sampling time selection */ 954 #define ADC_SMPR1_SMP24_0 (0x1UL << ADC_SMPR1_SMP24_Pos) /*!< 0x00001000 */ 955 #define ADC_SMPR1_SMP24_1 (0x2UL << ADC_SMPR1_SMP24_Pos) /*!< 0x00002000 */ 956 #define ADC_SMPR1_SMP24_2 (0x4UL << ADC_SMPR1_SMP24_Pos) /*!< 0x00004000 */ 957 958 #define ADC_SMPR1_SMP25_Pos (15U) 959 #define ADC_SMPR1_SMP25_Msk (0x7UL << ADC_SMPR1_SMP25_Pos) /*!< 0x00038000 */ 960 #define ADC_SMPR1_SMP25 ADC_SMPR1_SMP25_Msk /*!< ADC channel 25 sampling time selection */ 961 #define ADC_SMPR1_SMP25_0 (0x1UL << ADC_SMPR1_SMP25_Pos) /*!< 0x00008000 */ 962 #define ADC_SMPR1_SMP25_1 (0x2UL << ADC_SMPR1_SMP25_Pos) /*!< 0x00010000 */ 963 #define ADC_SMPR1_SMP25_2 (0x4UL << ADC_SMPR1_SMP25_Pos) /*!< 0x00020000 */ 964 965 #define ADC_SMPR1_SMP26_Pos (18U) 966 #define ADC_SMPR1_SMP26_Msk (0x7UL << ADC_SMPR1_SMP26_Pos) /*!< 0x001C0000 */ 967 #define ADC_SMPR1_SMP26 ADC_SMPR1_SMP26_Msk /*!< ADC channel 26 sampling time selection */ 968 #define ADC_SMPR1_SMP26_0 (0x1UL << ADC_SMPR1_SMP26_Pos) /*!< 0x00040000 */ 969 #define ADC_SMPR1_SMP26_1 (0x2UL << ADC_SMPR1_SMP26_Pos) /*!< 0x00080000 */ 970 #define ADC_SMPR1_SMP26_2 (0x4UL << ADC_SMPR1_SMP26_Pos) /*!< 0x00100000 */ 971 972 /****************** Bit definition for ADC_SMPR2 register *******************/ 973 #define ADC_SMPR2_SMP10_Pos (0U) 974 #define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ 975 #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ 976 #define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ 977 #define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ 978 #define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ 979 980 #define ADC_SMPR2_SMP11_Pos (3U) 981 #define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ 982 #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ 983 #define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ 984 #define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ 985 #define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ 986 987 #define ADC_SMPR2_SMP12_Pos (6U) 988 #define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ 989 #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ 990 #define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ 991 #define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ 992 #define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ 993 994 #define ADC_SMPR2_SMP13_Pos (9U) 995 #define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ 996 #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ 997 #define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ 998 #define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ 999 #define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ 1000 1001 #define ADC_SMPR2_SMP14_Pos (12U) 1002 #define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ 1003 #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ 1004 #define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ 1005 #define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ 1006 #define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ 1007 1008 #define ADC_SMPR2_SMP15_Pos (15U) 1009 #define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ 1010 #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 5 sampling time selection */ 1011 #define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ 1012 #define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ 1013 #define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ 1014 1015 #define ADC_SMPR2_SMP16_Pos (18U) 1016 #define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ 1017 #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ 1018 #define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ 1019 #define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ 1020 #define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ 1021 1022 #define ADC_SMPR2_SMP17_Pos (21U) 1023 #define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ 1024 #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ 1025 #define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ 1026 #define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ 1027 #define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ 1028 1029 #define ADC_SMPR2_SMP18_Pos (24U) 1030 #define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ 1031 #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ 1032 #define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ 1033 #define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ 1034 #define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ 1035 1036 #define ADC_SMPR2_SMP19_Pos (27U) 1037 #define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ 1038 #define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC channel 19 sampling time selection */ 1039 #define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ 1040 #define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ 1041 #define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ 1042 1043 /****************** Bit definition for ADC_SMPR3 register *******************/ 1044 #define ADC_SMPR3_SMP0_Pos (0U) 1045 #define ADC_SMPR3_SMP0_Msk (0x7UL << ADC_SMPR3_SMP0_Pos) /*!< 0x00000007 */ 1046 #define ADC_SMPR3_SMP0 ADC_SMPR3_SMP0_Msk /*!< ADC channel 0 sampling time selection */ 1047 #define ADC_SMPR3_SMP0_0 (0x1UL << ADC_SMPR3_SMP0_Pos) /*!< 0x00000001 */ 1048 #define ADC_SMPR3_SMP0_1 (0x2UL << ADC_SMPR3_SMP0_Pos) /*!< 0x00000002 */ 1049 #define ADC_SMPR3_SMP0_2 (0x4UL << ADC_SMPR3_SMP0_Pos) /*!< 0x00000004 */ 1050 1051 #define ADC_SMPR3_SMP1_Pos (3U) 1052 #define ADC_SMPR3_SMP1_Msk (0x7UL << ADC_SMPR3_SMP1_Pos) /*!< 0x00000038 */ 1053 #define ADC_SMPR3_SMP1 ADC_SMPR3_SMP1_Msk /*!< ADC channel 1 sampling time selection */ 1054 #define ADC_SMPR3_SMP1_0 (0x1UL << ADC_SMPR3_SMP1_Pos) /*!< 0x00000008 */ 1055 #define ADC_SMPR3_SMP1_1 (0x2UL << ADC_SMPR3_SMP1_Pos) /*!< 0x00000010 */ 1056 #define ADC_SMPR3_SMP1_2 (0x4UL << ADC_SMPR3_SMP1_Pos) /*!< 0x00000020 */ 1057 1058 #define ADC_SMPR3_SMP2_Pos (6U) 1059 #define ADC_SMPR3_SMP2_Msk (0x7UL << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */ 1060 #define ADC_SMPR3_SMP2 ADC_SMPR3_SMP2_Msk /*!< ADC channel 2 sampling time selection */ 1061 #define ADC_SMPR3_SMP2_0 (0x1UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */ 1062 #define ADC_SMPR3_SMP2_1 (0x2UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */ 1063 #define ADC_SMPR3_SMP2_2 (0x4UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */ 1064 1065 #define ADC_SMPR3_SMP3_Pos (9U) 1066 #define ADC_SMPR3_SMP3_Msk (0x7UL << ADC_SMPR3_SMP3_Pos) /*!< 0x00000E00 */ 1067 #define ADC_SMPR3_SMP3 ADC_SMPR3_SMP3_Msk /*!< ADC channel 3 sampling time selection */ 1068 #define ADC_SMPR3_SMP3_0 (0x1UL << ADC_SMPR3_SMP3_Pos) /*!< 0x00000200 */ 1069 #define ADC_SMPR3_SMP3_1 (0x2UL << ADC_SMPR3_SMP3_Pos) /*!< 0x00000400 */ 1070 #define ADC_SMPR3_SMP3_2 (0x4UL << ADC_SMPR3_SMP3_Pos) /*!< 0x00000800 */ 1071 1072 #define ADC_SMPR3_SMP4_Pos (12U) 1073 #define ADC_SMPR3_SMP4_Msk (0x7UL << ADC_SMPR3_SMP4_Pos) /*!< 0x00007000 */ 1074 #define ADC_SMPR3_SMP4 ADC_SMPR3_SMP4_Msk /*!< ADC channel 4 sampling time selection */ 1075 #define ADC_SMPR3_SMP4_0 (0x1UL << ADC_SMPR3_SMP4_Pos) /*!< 0x00001000 */ 1076 #define ADC_SMPR3_SMP4_1 (0x2UL << ADC_SMPR3_SMP4_Pos) /*!< 0x00002000 */ 1077 #define ADC_SMPR3_SMP4_2 (0x4UL << ADC_SMPR3_SMP4_Pos) /*!< 0x00004000 */ 1078 1079 #define ADC_SMPR3_SMP5_Pos (15U) 1080 #define ADC_SMPR3_SMP5_Msk (0x7UL << ADC_SMPR3_SMP5_Pos) /*!< 0x00038000 */ 1081 #define ADC_SMPR3_SMP5 ADC_SMPR3_SMP5_Msk /*!< ADC channel 5 sampling time selection */ 1082 #define ADC_SMPR3_SMP5_0 (0x1UL << ADC_SMPR3_SMP5_Pos) /*!< 0x00008000 */ 1083 #define ADC_SMPR3_SMP5_1 (0x2UL << ADC_SMPR3_SMP5_Pos) /*!< 0x00010000 */ 1084 #define ADC_SMPR3_SMP5_2 (0x4UL << ADC_SMPR3_SMP5_Pos) /*!< 0x00020000 */ 1085 1086 #define ADC_SMPR3_SMP6_Pos (18U) 1087 #define ADC_SMPR3_SMP6_Msk (0x7UL << ADC_SMPR3_SMP6_Pos) /*!< 0x001C0000 */ 1088 #define ADC_SMPR3_SMP6 ADC_SMPR3_SMP6_Msk /*!< ADC channel 6 sampling time selection */ 1089 #define ADC_SMPR3_SMP6_0 (0x1UL << ADC_SMPR3_SMP6_Pos) /*!< 0x00040000 */ 1090 #define ADC_SMPR3_SMP6_1 (0x2UL << ADC_SMPR3_SMP6_Pos) /*!< 0x00080000 */ 1091 #define ADC_SMPR3_SMP6_2 (0x4UL << ADC_SMPR3_SMP6_Pos) /*!< 0x00100000 */ 1092 1093 #define ADC_SMPR3_SMP7_Pos (21U) 1094 #define ADC_SMPR3_SMP7_Msk (0x7UL << ADC_SMPR3_SMP7_Pos) /*!< 0x00E00000 */ 1095 #define ADC_SMPR3_SMP7 ADC_SMPR3_SMP7_Msk /*!< ADC channel 7 sampling time selection */ 1096 #define ADC_SMPR3_SMP7_0 (0x1UL << ADC_SMPR3_SMP7_Pos) /*!< 0x00200000 */ 1097 #define ADC_SMPR3_SMP7_1 (0x2UL << ADC_SMPR3_SMP7_Pos) /*!< 0x00400000 */ 1098 #define ADC_SMPR3_SMP7_2 (0x4UL << ADC_SMPR3_SMP7_Pos) /*!< 0x00800000 */ 1099 1100 #define ADC_SMPR3_SMP8_Pos (24U) 1101 #define ADC_SMPR3_SMP8_Msk (0x7UL << ADC_SMPR3_SMP8_Pos) /*!< 0x07000000 */ 1102 #define ADC_SMPR3_SMP8 ADC_SMPR3_SMP8_Msk /*!< ADC channel 8 sampling time selection */ 1103 #define ADC_SMPR3_SMP8_0 (0x1UL << ADC_SMPR3_SMP8_Pos) /*!< 0x01000000 */ 1104 #define ADC_SMPR3_SMP8_1 (0x2UL << ADC_SMPR3_SMP8_Pos) /*!< 0x02000000 */ 1105 #define ADC_SMPR3_SMP8_2 (0x4UL << ADC_SMPR3_SMP8_Pos) /*!< 0x04000000 */ 1106 1107 #define ADC_SMPR3_SMP9_Pos (27U) 1108 #define ADC_SMPR3_SMP9_Msk (0x7UL << ADC_SMPR3_SMP9_Pos) /*!< 0x38000000 */ 1109 #define ADC_SMPR3_SMP9 ADC_SMPR3_SMP9_Msk /*!< ADC channel 9 sampling time selection */ 1110 #define ADC_SMPR3_SMP9_0 (0x1UL << ADC_SMPR3_SMP9_Pos) /*!< 0x08000000 */ 1111 #define ADC_SMPR3_SMP9_1 (0x2UL << ADC_SMPR3_SMP9_Pos) /*!< 0x10000000 */ 1112 #define ADC_SMPR3_SMP9_2 (0x4UL << ADC_SMPR3_SMP9_Pos) /*!< 0x20000000 */ 1113 1114 /****************** Bit definition for ADC_JOFR1 register *******************/ 1115 #define ADC_JOFR1_JOFFSET1_Pos (0U) 1116 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ 1117 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */ 1118 1119 /****************** Bit definition for ADC_JOFR2 register *******************/ 1120 #define ADC_JOFR2_JOFFSET2_Pos (0U) 1121 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ 1122 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */ 1123 1124 /****************** Bit definition for ADC_JOFR3 register *******************/ 1125 #define ADC_JOFR3_JOFFSET3_Pos (0U) 1126 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ 1127 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */ 1128 1129 /****************** Bit definition for ADC_JOFR4 register *******************/ 1130 #define ADC_JOFR4_JOFFSET4_Pos (0U) 1131 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ 1132 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */ 1133 1134 /******************* Bit definition for ADC_HTR register ********************/ 1135 #define ADC_HTR_HT_Pos (0U) 1136 #define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ 1137 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */ 1138 1139 /******************* Bit definition for ADC_LTR register ********************/ 1140 #define ADC_LTR_LT_Pos (0U) 1141 #define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ 1142 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */ 1143 1144 /******************* Bit definition for ADC_SQR1 register *******************/ 1145 #define ADC_SQR1_L_Pos (20U) 1146 #define ADC_SQR1_L_Msk (0x1FUL << ADC_SQR1_L_Pos) /*!< 0x01F00000 */ 1147 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ 1148 #define ADC_SQR1_L_0 (0x01UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */ 1149 #define ADC_SQR1_L_1 (0x02UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */ 1150 #define ADC_SQR1_L_2 (0x04UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */ 1151 #define ADC_SQR1_L_3 (0x08UL << ADC_SQR1_L_Pos) /*!< 0x00800000 */ 1152 #define ADC_SQR1_L_4 (0x10UL << ADC_SQR1_L_Pos) /*!< 0x01000000 */ 1153 1154 #define ADC_SQR1_SQ27_Pos (10U) 1155 #define ADC_SQR1_SQ27_Msk (0x1FUL << ADC_SQR1_SQ27_Pos) /*!< 0x00007C00 */ 1156 #define ADC_SQR1_SQ27 ADC_SQR1_SQ27_Msk /*!< ADC group regular sequencer rank 27 */ 1157 #define ADC_SQR1_SQ27_0 (0x01UL << ADC_SQR1_SQ27_Pos) /*!< 0x00000400 */ 1158 #define ADC_SQR1_SQ27_1 (0x02UL << ADC_SQR1_SQ27_Pos) /*!< 0x00000800 */ 1159 #define ADC_SQR1_SQ27_2 (0x04UL << ADC_SQR1_SQ27_Pos) /*!< 0x00001000 */ 1160 #define ADC_SQR1_SQ27_3 (0x08UL << ADC_SQR1_SQ27_Pos) /*!< 0x00002000 */ 1161 #define ADC_SQR1_SQ27_4 (0x10UL << ADC_SQR1_SQ27_Pos) /*!< 0x00004000 */ 1162 1163 #define ADC_SQR1_SQ26_Pos (5U) 1164 #define ADC_SQR1_SQ26_Msk (0x1FUL << ADC_SQR1_SQ26_Pos) /*!< 0x000003E0 */ 1165 #define ADC_SQR1_SQ26 ADC_SQR1_SQ26_Msk /*!< ADC group regular sequencer rank 26 */ 1166 #define ADC_SQR1_SQ26_0 (0x01UL << ADC_SQR1_SQ26_Pos) /*!< 0x00000020 */ 1167 #define ADC_SQR1_SQ26_1 (0x02UL << ADC_SQR1_SQ26_Pos) /*!< 0x00000040 */ 1168 #define ADC_SQR1_SQ26_2 (0x04UL << ADC_SQR1_SQ26_Pos) /*!< 0x00000080 */ 1169 #define ADC_SQR1_SQ26_3 (0x08UL << ADC_SQR1_SQ26_Pos) /*!< 0x00000100 */ 1170 #define ADC_SQR1_SQ26_4 (0x10UL << ADC_SQR1_SQ26_Pos) /*!< 0x00000200 */ 1171 1172 #define ADC_SQR1_SQ25_Pos (0U) 1173 #define ADC_SQR1_SQ25_Msk (0x1FUL << ADC_SQR1_SQ25_Pos) /*!< 0x0000001F */ 1174 #define ADC_SQR1_SQ25 ADC_SQR1_SQ25_Msk /*!< ADC group regular sequencer rank 25 */ 1175 #define ADC_SQR1_SQ25_0 (0x01UL << ADC_SQR1_SQ25_Pos) /*!< 0x00000001 */ 1176 #define ADC_SQR1_SQ25_1 (0x02UL << ADC_SQR1_SQ25_Pos) /*!< 0x00000002 */ 1177 #define ADC_SQR1_SQ25_2 (0x04UL << ADC_SQR1_SQ25_Pos) /*!< 0x00000004 */ 1178 #define ADC_SQR1_SQ25_3 (0x08UL << ADC_SQR1_SQ25_Pos) /*!< 0x00000008 */ 1179 #define ADC_SQR1_SQ25_4 (0x10UL << ADC_SQR1_SQ25_Pos) /*!< 0x00000010 */ 1180 1181 /******************* Bit definition for ADC_SQR2 register *******************/ 1182 #define ADC_SQR2_SQ19_Pos (0U) 1183 #define ADC_SQR2_SQ19_Msk (0x1FUL << ADC_SQR2_SQ19_Pos) /*!< 0x0000001F */ 1184 #define ADC_SQR2_SQ19 ADC_SQR2_SQ19_Msk /*!< ADC group regular sequencer rank 19 */ 1185 #define ADC_SQR2_SQ19_0 (0x01UL << ADC_SQR2_SQ19_Pos) /*!< 0x00000001 */ 1186 #define ADC_SQR2_SQ19_1 (0x02UL << ADC_SQR2_SQ19_Pos) /*!< 0x00000002 */ 1187 #define ADC_SQR2_SQ19_2 (0x04UL << ADC_SQR2_SQ19_Pos) /*!< 0x00000004 */ 1188 #define ADC_SQR2_SQ19_3 (0x08UL << ADC_SQR2_SQ19_Pos) /*!< 0x00000008 */ 1189 #define ADC_SQR2_SQ19_4 (0x10UL << ADC_SQR2_SQ19_Pos) /*!< 0x00000010 */ 1190 1191 #define ADC_SQR2_SQ20_Pos (5U) 1192 #define ADC_SQR2_SQ20_Msk (0x1FUL << ADC_SQR2_SQ20_Pos) /*!< 0x000003E0 */ 1193 #define ADC_SQR2_SQ20 ADC_SQR2_SQ20_Msk /*!< ADC group regular sequencer rank 20 */ 1194 #define ADC_SQR2_SQ20_0 (0x01UL << ADC_SQR2_SQ20_Pos) /*!< 0x00000020 */ 1195 #define ADC_SQR2_SQ20_1 (0x02UL << ADC_SQR2_SQ20_Pos) /*!< 0x00000040 */ 1196 #define ADC_SQR2_SQ20_2 (0x04UL << ADC_SQR2_SQ20_Pos) /*!< 0x00000080 */ 1197 #define ADC_SQR2_SQ20_3 (0x08UL << ADC_SQR2_SQ20_Pos) /*!< 0x00000100 */ 1198 #define ADC_SQR2_SQ20_4 (0x10UL << ADC_SQR2_SQ20_Pos) /*!< 0x00000200 */ 1199 1200 #define ADC_SQR2_SQ21_Pos (10U) 1201 #define ADC_SQR2_SQ21_Msk (0x1FUL << ADC_SQR2_SQ21_Pos) /*!< 0x00007C00 */ 1202 #define ADC_SQR2_SQ21 ADC_SQR2_SQ21_Msk /*!< ADC group regular sequencer rank 21 */ 1203 #define ADC_SQR2_SQ21_0 (0x01UL << ADC_SQR2_SQ21_Pos) /*!< 0x00000400 */ 1204 #define ADC_SQR2_SQ21_1 (0x02UL << ADC_SQR2_SQ21_Pos) /*!< 0x00000800 */ 1205 #define ADC_SQR2_SQ21_2 (0x04UL << ADC_SQR2_SQ21_Pos) /*!< 0x00001000 */ 1206 #define ADC_SQR2_SQ21_3 (0x08UL << ADC_SQR2_SQ21_Pos) /*!< 0x00002000 */ 1207 #define ADC_SQR2_SQ21_4 (0x10UL << ADC_SQR2_SQ21_Pos) /*!< 0x00004000 */ 1208 1209 #define ADC_SQR2_SQ22_Pos (15U) 1210 #define ADC_SQR2_SQ22_Msk (0x1FUL << ADC_SQR2_SQ22_Pos) /*!< 0x000F8000 */ 1211 #define ADC_SQR2_SQ22 ADC_SQR2_SQ22_Msk /*!< ADC group regular sequencer rank 22 */ 1212 #define ADC_SQR2_SQ22_0 (0x01UL << ADC_SQR2_SQ22_Pos) /*!< 0x00008000 */ 1213 #define ADC_SQR2_SQ22_1 (0x02UL << ADC_SQR2_SQ22_Pos) /*!< 0x00010000 */ 1214 #define ADC_SQR2_SQ22_2 (0x04UL << ADC_SQR2_SQ22_Pos) /*!< 0x00020000 */ 1215 #define ADC_SQR2_SQ22_3 (0x08UL << ADC_SQR2_SQ22_Pos) /*!< 0x00040000 */ 1216 #define ADC_SQR2_SQ22_4 (0x10UL << ADC_SQR2_SQ22_Pos) /*!< 0x00080000 */ 1217 1218 #define ADC_SQR2_SQ23_Pos (20U) 1219 #define ADC_SQR2_SQ23_Msk (0x1FUL << ADC_SQR2_SQ23_Pos) /*!< 0x01F00000 */ 1220 #define ADC_SQR2_SQ23 ADC_SQR2_SQ23_Msk /*!< ADC group regular sequencer rank 23 */ 1221 #define ADC_SQR2_SQ23_0 (0x01UL << ADC_SQR2_SQ23_Pos) /*!< 0x00100000 */ 1222 #define ADC_SQR2_SQ23_1 (0x02UL << ADC_SQR2_SQ23_Pos) /*!< 0x00200000 */ 1223 #define ADC_SQR2_SQ23_2 (0x04UL << ADC_SQR2_SQ23_Pos) /*!< 0x00400000 */ 1224 #define ADC_SQR2_SQ23_3 (0x08UL << ADC_SQR2_SQ23_Pos) /*!< 0x00800000 */ 1225 #define ADC_SQR2_SQ23_4 (0x10UL << ADC_SQR2_SQ23_Pos) /*!< 0x01000000 */ 1226 1227 #define ADC_SQR2_SQ24_Pos (25U) 1228 #define ADC_SQR2_SQ24_Msk (0x1FUL << ADC_SQR2_SQ24_Pos) /*!< 0x3E000000 */ 1229 #define ADC_SQR2_SQ24 ADC_SQR2_SQ24_Msk /*!< ADC group regular sequencer rank 24 */ 1230 #define ADC_SQR2_SQ24_0 (0x01UL << ADC_SQR2_SQ24_Pos) /*!< 0x02000000 */ 1231 #define ADC_SQR2_SQ24_1 (0x02UL << ADC_SQR2_SQ24_Pos) /*!< 0x04000000 */ 1232 #define ADC_SQR2_SQ24_2 (0x04UL << ADC_SQR2_SQ24_Pos) /*!< 0x08000000 */ 1233 #define ADC_SQR2_SQ24_3 (0x08UL << ADC_SQR2_SQ24_Pos) /*!< 0x10000000 */ 1234 #define ADC_SQR2_SQ24_4 (0x10UL << ADC_SQR2_SQ24_Pos) /*!< 0x20000000 */ 1235 1236 /******************* Bit definition for ADC_SQR3 register *******************/ 1237 #define ADC_SQR3_SQ13_Pos (0U) 1238 #define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x0000001F */ 1239 #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ 1240 #define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00000001 */ 1241 #define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00000002 */ 1242 #define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00000004 */ 1243 #define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00000008 */ 1244 #define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00000010 */ 1245 1246 #define ADC_SQR3_SQ14_Pos (5U) 1247 #define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x000003E0 */ 1248 #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ 1249 #define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x00000020 */ 1250 #define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x00000040 */ 1251 #define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x00000080 */ 1252 #define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x00000100 */ 1253 #define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x00000200 */ 1254 1255 #define ADC_SQR3_SQ15_Pos (10U) 1256 #define ADC_SQR3_SQ15_Msk (0x1FUL << ADC_SQR3_SQ15_Pos) /*!< 0x00007C00 */ 1257 #define ADC_SQR3_SQ15 ADC_SQR3_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ 1258 #define ADC_SQR3_SQ15_0 (0x01UL << ADC_SQR3_SQ15_Pos) /*!< 0x00000400 */ 1259 #define ADC_SQR3_SQ15_1 (0x02UL << ADC_SQR3_SQ15_Pos) /*!< 0x00000800 */ 1260 #define ADC_SQR3_SQ15_2 (0x04UL << ADC_SQR3_SQ15_Pos) /*!< 0x00001000 */ 1261 #define ADC_SQR3_SQ15_3 (0x08UL << ADC_SQR3_SQ15_Pos) /*!< 0x00002000 */ 1262 #define ADC_SQR3_SQ15_4 (0x10UL << ADC_SQR3_SQ15_Pos) /*!< 0x00004000 */ 1263 1264 #define ADC_SQR3_SQ16_Pos (15U) 1265 #define ADC_SQR3_SQ16_Msk (0x1FUL << ADC_SQR3_SQ16_Pos) /*!< 0x000F8000 */ 1266 #define ADC_SQR3_SQ16 ADC_SQR3_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ 1267 #define ADC_SQR3_SQ16_0 (0x01UL << ADC_SQR3_SQ16_Pos) /*!< 0x00008000 */ 1268 #define ADC_SQR3_SQ16_1 (0x02UL << ADC_SQR3_SQ16_Pos) /*!< 0x00010000 */ 1269 #define ADC_SQR3_SQ16_2 (0x04UL << ADC_SQR3_SQ16_Pos) /*!< 0x00020000 */ 1270 #define ADC_SQR3_SQ16_3 (0x08UL << ADC_SQR3_SQ16_Pos) /*!< 0x00040000 */ 1271 #define ADC_SQR3_SQ16_4 (0x10UL << ADC_SQR3_SQ16_Pos) /*!< 0x00080000 */ 1272 1273 #define ADC_SQR3_SQ17_Pos (20U) 1274 #define ADC_SQR3_SQ17_Msk (0x1FUL << ADC_SQR3_SQ17_Pos) /*!< 0x01F00000 */ 1275 #define ADC_SQR3_SQ17 ADC_SQR3_SQ17_Msk /*!< ADC group regular sequencer rank 17 */ 1276 #define ADC_SQR3_SQ17_0 (0x01UL << ADC_SQR3_SQ17_Pos) /*!< 0x00100000 */ 1277 #define ADC_SQR3_SQ17_1 (0x02UL << ADC_SQR3_SQ17_Pos) /*!< 0x00200000 */ 1278 #define ADC_SQR3_SQ17_2 (0x04UL << ADC_SQR3_SQ17_Pos) /*!< 0x00400000 */ 1279 #define ADC_SQR3_SQ17_3 (0x08UL << ADC_SQR3_SQ17_Pos) /*!< 0x00800000 */ 1280 #define ADC_SQR3_SQ17_4 (0x10UL << ADC_SQR3_SQ17_Pos) /*!< 0x01000000 */ 1281 1282 #define ADC_SQR3_SQ18_Pos (25U) 1283 #define ADC_SQR3_SQ18_Msk (0x1FUL << ADC_SQR3_SQ18_Pos) /*!< 0x3E000000 */ 1284 #define ADC_SQR3_SQ18 ADC_SQR3_SQ18_Msk /*!< ADC group regular sequencer rank 18 */ 1285 #define ADC_SQR3_SQ18_0 (0x01UL << ADC_SQR3_SQ18_Pos) /*!< 0x02000000 */ 1286 #define ADC_SQR3_SQ18_1 (0x02UL << ADC_SQR3_SQ18_Pos) /*!< 0x04000000 */ 1287 #define ADC_SQR3_SQ18_2 (0x04UL << ADC_SQR3_SQ18_Pos) /*!< 0x08000000 */ 1288 #define ADC_SQR3_SQ18_3 (0x08UL << ADC_SQR3_SQ18_Pos) /*!< 0x10000000 */ 1289 #define ADC_SQR3_SQ18_4 (0x10UL << ADC_SQR3_SQ18_Pos) /*!< 0x20000000 */ 1290 1291 /******************* Bit definition for ADC_SQR4 register *******************/ 1292 #define ADC_SQR4_SQ7_Pos (0U) 1293 #define ADC_SQR4_SQ7_Msk (0x1FUL << ADC_SQR4_SQ7_Pos) /*!< 0x0000001F */ 1294 #define ADC_SQR4_SQ7 ADC_SQR4_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ 1295 #define ADC_SQR4_SQ7_0 (0x01UL << ADC_SQR4_SQ7_Pos) /*!< 0x00000001 */ 1296 #define ADC_SQR4_SQ7_1 (0x02UL << ADC_SQR4_SQ7_Pos) /*!< 0x00000002 */ 1297 #define ADC_SQR4_SQ7_2 (0x04UL << ADC_SQR4_SQ7_Pos) /*!< 0x00000004 */ 1298 #define ADC_SQR4_SQ7_3 (0x08UL << ADC_SQR4_SQ7_Pos) /*!< 0x00000008 */ 1299 #define ADC_SQR4_SQ7_4 (0x10UL << ADC_SQR4_SQ7_Pos) /*!< 0x00000010 */ 1300 1301 #define ADC_SQR4_SQ8_Pos (5U) 1302 #define ADC_SQR4_SQ8_Msk (0x1FUL << ADC_SQR4_SQ8_Pos) /*!< 0x000003E0 */ 1303 #define ADC_SQR4_SQ8 ADC_SQR4_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ 1304 #define ADC_SQR4_SQ8_0 (0x01UL << ADC_SQR4_SQ8_Pos) /*!< 0x00000020 */ 1305 #define ADC_SQR4_SQ8_1 (0x02UL << ADC_SQR4_SQ8_Pos) /*!< 0x00000040 */ 1306 #define ADC_SQR4_SQ8_2 (0x04UL << ADC_SQR4_SQ8_Pos) /*!< 0x00000080 */ 1307 #define ADC_SQR4_SQ8_3 (0x08UL << ADC_SQR4_SQ8_Pos) /*!< 0x00000100 */ 1308 #define ADC_SQR4_SQ8_4 (0x10UL << ADC_SQR4_SQ8_Pos) /*!< 0x00000200 */ 1309 1310 #define ADC_SQR4_SQ9_Pos (10U) 1311 #define ADC_SQR4_SQ9_Msk (0x1FUL << ADC_SQR4_SQ9_Pos) /*!< 0x00007C00 */ 1312 #define ADC_SQR4_SQ9 ADC_SQR4_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ 1313 #define ADC_SQR4_SQ9_0 (0x01UL << ADC_SQR4_SQ9_Pos) /*!< 0x00000400 */ 1314 #define ADC_SQR4_SQ9_1 (0x02UL << ADC_SQR4_SQ9_Pos) /*!< 0x00000800 */ 1315 #define ADC_SQR4_SQ9_2 (0x04UL << ADC_SQR4_SQ9_Pos) /*!< 0x00001000 */ 1316 #define ADC_SQR4_SQ9_3 (0x08UL << ADC_SQR4_SQ9_Pos) /*!< 0x00002000 */ 1317 #define ADC_SQR4_SQ9_4 (0x10UL << ADC_SQR4_SQ9_Pos) /*!< 0x00004000 */ 1318 1319 #define ADC_SQR4_SQ10_Pos (15U) 1320 #define ADC_SQR4_SQ10_Msk (0x1FUL << ADC_SQR4_SQ10_Pos) /*!< 0x000F8000 */ 1321 #define ADC_SQR4_SQ10 ADC_SQR4_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ 1322 #define ADC_SQR4_SQ10_0 (0x01UL << ADC_SQR4_SQ10_Pos) /*!< 0x00008000 */ 1323 #define ADC_SQR4_SQ10_1 (0x02UL << ADC_SQR4_SQ10_Pos) /*!< 0x00010000 */ 1324 #define ADC_SQR4_SQ10_2 (0x04UL << ADC_SQR4_SQ10_Pos) /*!< 0x00020000 */ 1325 #define ADC_SQR4_SQ10_3 (0x08UL << ADC_SQR4_SQ10_Pos) /*!< 0x00040000 */ 1326 #define ADC_SQR4_SQ10_4 (0x10UL << ADC_SQR4_SQ10_Pos) /*!< 0x00080000 */ 1327 1328 #define ADC_SQR4_SQ11_Pos (20U) 1329 #define ADC_SQR4_SQ11_Msk (0x1FUL << ADC_SQR4_SQ11_Pos) /*!< 0x01F00000 */ 1330 #define ADC_SQR4_SQ11 ADC_SQR4_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ 1331 #define ADC_SQR4_SQ11_0 (0x01UL << ADC_SQR4_SQ11_Pos) /*!< 0x00100000 */ 1332 #define ADC_SQR4_SQ11_1 (0x02UL << ADC_SQR4_SQ11_Pos) /*!< 0x00200000 */ 1333 #define ADC_SQR4_SQ11_2 (0x04UL << ADC_SQR4_SQ11_Pos) /*!< 0x00400000 */ 1334 #define ADC_SQR4_SQ11_3 (0x08UL << ADC_SQR4_SQ11_Pos) /*!< 0x00800000 */ 1335 #define ADC_SQR4_SQ11_4 (0x10UL << ADC_SQR4_SQ11_Pos) /*!< 0x01000000 */ 1336 1337 #define ADC_SQR4_SQ12_Pos (25U) 1338 #define ADC_SQR4_SQ12_Msk (0x1FUL << ADC_SQR4_SQ12_Pos) /*!< 0x3E000000 */ 1339 #define ADC_SQR4_SQ12 ADC_SQR4_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ 1340 #define ADC_SQR4_SQ12_0 (0x01UL << ADC_SQR4_SQ12_Pos) /*!< 0x02000000 */ 1341 #define ADC_SQR4_SQ12_1 (0x02UL << ADC_SQR4_SQ12_Pos) /*!< 0x04000000 */ 1342 #define ADC_SQR4_SQ12_2 (0x04UL << ADC_SQR4_SQ12_Pos) /*!< 0x08000000 */ 1343 #define ADC_SQR4_SQ12_3 (0x08UL << ADC_SQR4_SQ12_Pos) /*!< 0x10000000 */ 1344 #define ADC_SQR4_SQ12_4 (0x10UL << ADC_SQR4_SQ12_Pos) /*!< 0x20000000 */ 1345 1346 /******************* Bit definition for ADC_SQR5 register *******************/ 1347 #define ADC_SQR5_SQ1_Pos (0U) 1348 #define ADC_SQR5_SQ1_Msk (0x1FUL << ADC_SQR5_SQ1_Pos) /*!< 0x0000001F */ 1349 #define ADC_SQR5_SQ1 ADC_SQR5_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ 1350 #define ADC_SQR5_SQ1_0 (0x01UL << ADC_SQR5_SQ1_Pos) /*!< 0x00000001 */ 1351 #define ADC_SQR5_SQ1_1 (0x02UL << ADC_SQR5_SQ1_Pos) /*!< 0x00000002 */ 1352 #define ADC_SQR5_SQ1_2 (0x04UL << ADC_SQR5_SQ1_Pos) /*!< 0x00000004 */ 1353 #define ADC_SQR5_SQ1_3 (0x08UL << ADC_SQR5_SQ1_Pos) /*!< 0x00000008 */ 1354 #define ADC_SQR5_SQ1_4 (0x10UL << ADC_SQR5_SQ1_Pos) /*!< 0x00000010 */ 1355 1356 #define ADC_SQR5_SQ2_Pos (5U) 1357 #define ADC_SQR5_SQ2_Msk (0x1FUL << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */ 1358 #define ADC_SQR5_SQ2 ADC_SQR5_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ 1359 #define ADC_SQR5_SQ2_0 (0x01UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */ 1360 #define ADC_SQR5_SQ2_1 (0x02UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */ 1361 #define ADC_SQR5_SQ2_2 (0x04UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */ 1362 #define ADC_SQR5_SQ2_3 (0x08UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */ 1363 #define ADC_SQR5_SQ2_4 (0x10UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */ 1364 1365 #define ADC_SQR5_SQ3_Pos (10U) 1366 #define ADC_SQR5_SQ3_Msk (0x1FUL << ADC_SQR5_SQ3_Pos) /*!< 0x00007C00 */ 1367 #define ADC_SQR5_SQ3 ADC_SQR5_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ 1368 #define ADC_SQR5_SQ3_0 (0x01UL << ADC_SQR5_SQ3_Pos) /*!< 0x00000400 */ 1369 #define ADC_SQR5_SQ3_1 (0x02UL << ADC_SQR5_SQ3_Pos) /*!< 0x00000800 */ 1370 #define ADC_SQR5_SQ3_2 (0x04UL << ADC_SQR5_SQ3_Pos) /*!< 0x00001000 */ 1371 #define ADC_SQR5_SQ3_3 (0x08UL << ADC_SQR5_SQ3_Pos) /*!< 0x00002000 */ 1372 #define ADC_SQR5_SQ3_4 (0x10UL << ADC_SQR5_SQ3_Pos) /*!< 0x00004000 */ 1373 1374 #define ADC_SQR5_SQ4_Pos (15U) 1375 #define ADC_SQR5_SQ4_Msk (0x1FUL << ADC_SQR5_SQ4_Pos) /*!< 0x000F8000 */ 1376 #define ADC_SQR5_SQ4 ADC_SQR5_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ 1377 #define ADC_SQR5_SQ4_0 (0x01UL << ADC_SQR5_SQ4_Pos) /*!< 0x00008000 */ 1378 #define ADC_SQR5_SQ4_1 (0x02UL << ADC_SQR5_SQ4_Pos) /*!< 0x00010000 */ 1379 #define ADC_SQR5_SQ4_2 (0x04UL << ADC_SQR5_SQ4_Pos) /*!< 0x00020000 */ 1380 #define ADC_SQR5_SQ4_3 (0x08UL << ADC_SQR5_SQ4_Pos) /*!< 0x00040000 */ 1381 #define ADC_SQR5_SQ4_4 (0x10UL << ADC_SQR5_SQ4_Pos) /*!< 0x00080000 */ 1382 1383 #define ADC_SQR5_SQ5_Pos (20U) 1384 #define ADC_SQR5_SQ5_Msk (0x1FUL << ADC_SQR5_SQ5_Pos) /*!< 0x01F00000 */ 1385 #define ADC_SQR5_SQ5 ADC_SQR5_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ 1386 #define ADC_SQR5_SQ5_0 (0x01UL << ADC_SQR5_SQ5_Pos) /*!< 0x00100000 */ 1387 #define ADC_SQR5_SQ5_1 (0x02UL << ADC_SQR5_SQ5_Pos) /*!< 0x00200000 */ 1388 #define ADC_SQR5_SQ5_2 (0x04UL << ADC_SQR5_SQ5_Pos) /*!< 0x00400000 */ 1389 #define ADC_SQR5_SQ5_3 (0x08UL << ADC_SQR5_SQ5_Pos) /*!< 0x00800000 */ 1390 #define ADC_SQR5_SQ5_4 (0x10UL << ADC_SQR5_SQ5_Pos) /*!< 0x01000000 */ 1391 1392 #define ADC_SQR5_SQ6_Pos (25U) 1393 #define ADC_SQR5_SQ6_Msk (0x1FUL << ADC_SQR5_SQ6_Pos) /*!< 0x3E000000 */ 1394 #define ADC_SQR5_SQ6 ADC_SQR5_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ 1395 #define ADC_SQR5_SQ6_0 (0x01UL << ADC_SQR5_SQ6_Pos) /*!< 0x02000000 */ 1396 #define ADC_SQR5_SQ6_1 (0x02UL << ADC_SQR5_SQ6_Pos) /*!< 0x04000000 */ 1397 #define ADC_SQR5_SQ6_2 (0x04UL << ADC_SQR5_SQ6_Pos) /*!< 0x08000000 */ 1398 #define ADC_SQR5_SQ6_3 (0x08UL << ADC_SQR5_SQ6_Pos) /*!< 0x10000000 */ 1399 #define ADC_SQR5_SQ6_4 (0x10UL << ADC_SQR5_SQ6_Pos) /*!< 0x20000000 */ 1400 1401 1402 /******************* Bit definition for ADC_JSQR register *******************/ 1403 #define ADC_JSQR_JSQ1_Pos (0U) 1404 #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ 1405 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ 1406 #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ 1407 #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ 1408 #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ 1409 #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ 1410 #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ 1411 1412 #define ADC_JSQR_JSQ2_Pos (5U) 1413 #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ 1414 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ 1415 #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ 1416 #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ 1417 #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ 1418 #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ 1419 #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ 1420 1421 #define ADC_JSQR_JSQ3_Pos (10U) 1422 #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ 1423 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ 1424 #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ 1425 #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ 1426 #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ 1427 #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ 1428 #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ 1429 1430 #define ADC_JSQR_JSQ4_Pos (15U) 1431 #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ 1432 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ 1433 #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ 1434 #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ 1435 #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ 1436 #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ 1437 #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ 1438 1439 #define ADC_JSQR_JL_Pos (20U) 1440 #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ 1441 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ 1442 #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ 1443 #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ 1444 1445 /******************* Bit definition for ADC_JDR1 register *******************/ 1446 #define ADC_JDR1_JDATA_Pos (0U) 1447 #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ 1448 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ 1449 1450 /******************* Bit definition for ADC_JDR2 register *******************/ 1451 #define ADC_JDR2_JDATA_Pos (0U) 1452 #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ 1453 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ 1454 1455 /******************* Bit definition for ADC_JDR3 register *******************/ 1456 #define ADC_JDR3_JDATA_Pos (0U) 1457 #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ 1458 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ 1459 1460 /******************* Bit definition for ADC_JDR4 register *******************/ 1461 #define ADC_JDR4_JDATA_Pos (0U) 1462 #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ 1463 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ 1464 1465 /******************** Bit definition for ADC_DR register ********************/ 1466 #define ADC_DR_DATA_Pos (0U) 1467 #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ 1468 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ 1469 1470 /******************* Bit definition for ADC_CSR register ********************/ 1471 #define ADC_CSR_AWD1_Pos (0U) 1472 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */ 1473 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!< ADC multimode master analog watchdog 1 flag */ 1474 #define ADC_CSR_EOCS1_Pos (1U) 1475 #define ADC_CSR_EOCS1_Msk (0x1UL << ADC_CSR_EOCS1_Pos) /*!< 0x00000002 */ 1476 #define ADC_CSR_EOCS1 ADC_CSR_EOCS1_Msk /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */ 1477 #define ADC_CSR_JEOS1_Pos (2U) 1478 #define ADC_CSR_JEOS1_Msk (0x1UL << ADC_CSR_JEOS1_Pos) /*!< 0x00000004 */ 1479 #define ADC_CSR_JEOS1 ADC_CSR_JEOS1_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ 1480 #define ADC_CSR_JSTRT1_Pos (3U) 1481 #define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */ 1482 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!< ADC multimode master group injected conversion start flag */ 1483 #define ADC_CSR_STRT1_Pos (4U) 1484 #define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */ 1485 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!< ADC multimode master group regular conversion start flag */ 1486 #define ADC_CSR_OVR1_Pos (5U) 1487 #define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */ 1488 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!< ADC multimode master group regular overrun flag */ 1489 #define ADC_CSR_ADONS1_Pos (6U) 1490 #define ADC_CSR_ADONS1_Msk (0x1UL << ADC_CSR_ADONS1_Pos) /*!< 0x00000040 */ 1491 #define ADC_CSR_ADONS1 ADC_CSR_ADONS1_Msk /*!< ADC multimode master ready flag */ 1492 1493 /* Legacy defines */ 1494 #define ADC_CSR_EOC1 (ADC_CSR_EOCS1) 1495 #define ADC_CSR_JEOC1 (ADC_CSR_JEOS1) 1496 1497 /******************* Bit definition for ADC_CCR register ********************/ 1498 #define ADC_CCR_ADCPRE_Pos (16U) 1499 #define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */ 1500 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!< ADC clock source asynchronous prescaler */ 1501 #define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */ 1502 #define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */ 1503 #define ADC_CCR_TSVREFE_Pos (23U) 1504 #define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */ 1505 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */ 1506 1507 /******************************************************************************/ 1508 /* */ 1509 /* Analog Comparators (COMP) */ 1510 /* */ 1511 /******************************************************************************/ 1512 1513 /****************** Bit definition for COMP_CSR register ********************/ 1514 #define COMP_CSR_10KPU (0x00000001U) /*!< Comparator 1 input plus 10K pull-up resistor */ 1515 #define COMP_CSR_400KPU (0x00000002U) /*!< Comparator 1 input plus 400K pull-up resistor */ 1516 #define COMP_CSR_10KPD (0x00000004U) /*!< Comparator 1 input plus 10K pull-down resistor */ 1517 #define COMP_CSR_400KPD (0x00000008U) /*!< Comparator 1 input plus 400K pull-down resistor */ 1518 #define COMP_CSR_CMP1EN_Pos (4U) 1519 #define COMP_CSR_CMP1EN_Msk (0x1UL << COMP_CSR_CMP1EN_Pos) /*!< 0x00000010 */ 1520 #define COMP_CSR_CMP1EN COMP_CSR_CMP1EN_Msk /*!< Comparator 1 enable */ 1521 #define COMP_CSR_CMP1OUT_Pos (7U) 1522 #define COMP_CSR_CMP1OUT_Msk (0x1UL << COMP_CSR_CMP1OUT_Pos) /*!< 0x00000080 */ 1523 #define COMP_CSR_CMP1OUT COMP_CSR_CMP1OUT_Msk /*!< Comparator 1 output level */ 1524 #define COMP_CSR_SPEED_Pos (12U) 1525 #define COMP_CSR_SPEED_Msk (0x1UL << COMP_CSR_SPEED_Pos) /*!< 0x00001000 */ 1526 #define COMP_CSR_SPEED COMP_CSR_SPEED_Msk /*!< Comparator 2 power mode */ 1527 #define COMP_CSR_CMP2OUT_Pos (13U) 1528 #define COMP_CSR_CMP2OUT_Msk (0x1UL << COMP_CSR_CMP2OUT_Pos) /*!< 0x00002000 */ 1529 #define COMP_CSR_CMP2OUT COMP_CSR_CMP2OUT_Msk /*!< Comparator 2 output level */ 1530 1531 #define COMP_CSR_WNDWE_Pos (17U) 1532 #define COMP_CSR_WNDWE_Msk (0x1UL << COMP_CSR_WNDWE_Pos) /*!< 0x00020000 */ 1533 #define COMP_CSR_WNDWE COMP_CSR_WNDWE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ 1534 1535 #define COMP_CSR_INSEL_Pos (18U) 1536 #define COMP_CSR_INSEL_Msk (0x7UL << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */ 1537 #define COMP_CSR_INSEL COMP_CSR_INSEL_Msk /*!< Comparator 2 input minus selection */ 1538 #define COMP_CSR_INSEL_0 (0x1UL << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */ 1539 #define COMP_CSR_INSEL_1 (0x2UL << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */ 1540 #define COMP_CSR_INSEL_2 (0x4UL << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */ 1541 #define COMP_CSR_OUTSEL_Pos (21U) 1542 #define COMP_CSR_OUTSEL_Msk (0x7UL << COMP_CSR_OUTSEL_Pos) /*!< 0x00E00000 */ 1543 #define COMP_CSR_OUTSEL COMP_CSR_OUTSEL_Msk /*!< Comparator 2 output redirection */ 1544 #define COMP_CSR_OUTSEL_0 (0x1UL << COMP_CSR_OUTSEL_Pos) /*!< 0x00200000 */ 1545 #define COMP_CSR_OUTSEL_1 (0x2UL << COMP_CSR_OUTSEL_Pos) /*!< 0x00400000 */ 1546 #define COMP_CSR_OUTSEL_2 (0x4UL << COMP_CSR_OUTSEL_Pos) /*!< 0x00800000 */ 1547 1548 /* Bits present in COMP register but not related to comparator */ 1549 /* (or partially related to comparator, in addition to other peripherals) */ 1550 #define COMP_CSR_VREFOUTEN_Pos (16U) 1551 #define COMP_CSR_VREFOUTEN_Msk (0x1UL << COMP_CSR_VREFOUTEN_Pos) /*!< 0x00010000 */ 1552 #define COMP_CSR_VREFOUTEN COMP_CSR_VREFOUTEN_Msk /*!< VrefInt output enable on GPIO group 3 */ 1553 1554 /******************************************************************************/ 1555 /* */ 1556 /* CRC calculation unit (CRC) */ 1557 /* */ 1558 /******************************************************************************/ 1559 1560 /******************* Bit definition for CRC_DR register *********************/ 1561 #define CRC_DR_DR_Pos (0U) 1562 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ 1563 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ 1564 1565 /******************* Bit definition for CRC_IDR register ********************/ 1566 #define CRC_IDR_IDR_Pos (0U) 1567 #define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ 1568 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ 1569 1570 /******************** Bit definition for CRC_CR register ********************/ 1571 #define CRC_CR_RESET_Pos (0U) 1572 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ 1573 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */ 1574 1575 /******************************************************************************/ 1576 /* */ 1577 /* Digital to Analog Converter (DAC) */ 1578 /* */ 1579 /******************************************************************************/ 1580 1581 /******************** Bit definition for DAC_CR register ********************/ 1582 #define DAC_CR_EN1_Pos (0U) 1583 #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ 1584 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */ 1585 #define DAC_CR_BOFF1_Pos (1U) 1586 #define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */ 1587 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */ 1588 #define DAC_CR_TEN1_Pos (2U) 1589 #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */ 1590 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */ 1591 1592 #define DAC_CR_TSEL1_Pos (3U) 1593 #define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */ 1594 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */ 1595 #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ 1596 #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ 1597 #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ 1598 1599 #define DAC_CR_WAVE1_Pos (6U) 1600 #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ 1601 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ 1602 #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ 1603 #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ 1604 1605 #define DAC_CR_MAMP1_Pos (8U) 1606 #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ 1607 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ 1608 #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ 1609 #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ 1610 #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ 1611 #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ 1612 1613 #define DAC_CR_DMAEN1_Pos (12U) 1614 #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ 1615 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */ 1616 #define DAC_CR_DMAUDRIE1_Pos (13U) 1617 #define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ 1618 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA Interrupt enable */ 1619 #define DAC_CR_EN2_Pos (16U) 1620 #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ 1621 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */ 1622 #define DAC_CR_BOFF2_Pos (17U) 1623 #define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */ 1624 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */ 1625 #define DAC_CR_TEN2_Pos (18U) 1626 #define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00040000 */ 1627 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */ 1628 1629 #define DAC_CR_TSEL2_Pos (19U) 1630 #define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */ 1631 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */ 1632 #define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */ 1633 #define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */ 1634 #define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */ 1635 1636 #define DAC_CR_WAVE2_Pos (22U) 1637 #define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */ 1638 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ 1639 #define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */ 1640 #define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */ 1641 1642 #define DAC_CR_MAMP2_Pos (24U) 1643 #define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */ 1644 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ 1645 #define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */ 1646 #define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */ 1647 #define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */ 1648 #define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */ 1649 1650 #define DAC_CR_DMAEN2_Pos (28U) 1651 #define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */ 1652 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */ 1653 #define DAC_CR_DMAUDRIE2_Pos (29U) 1654 #define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */ 1655 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable */ 1656 /***************** Bit definition for DAC_SWTRIGR register ******************/ 1657 #define DAC_SWTRIGR_SWTRIG1_Pos (0U) 1658 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ 1659 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */ 1660 #define DAC_SWTRIGR_SWTRIG2_Pos (1U) 1661 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */ 1662 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */ 1663 1664 /***************** Bit definition for DAC_DHR12R1 register ******************/ 1665 #define DAC_DHR12R1_DACC1DHR_Pos (0U) 1666 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ 1667 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */ 1668 1669 /***************** Bit definition for DAC_DHR12L1 register ******************/ 1670 #define DAC_DHR12L1_DACC1DHR_Pos (4U) 1671 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ 1672 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */ 1673 1674 /****************** Bit definition for DAC_DHR8R1 register ******************/ 1675 #define DAC_DHR8R1_DACC1DHR_Pos (0U) 1676 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ 1677 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */ 1678 1679 /***************** Bit definition for DAC_DHR12R2 register ******************/ 1680 #define DAC_DHR12R2_DACC2DHR_Pos (0U) 1681 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */ 1682 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */ 1683 1684 /***************** Bit definition for DAC_DHR12L2 register ******************/ 1685 #define DAC_DHR12L2_DACC2DHR_Pos (4U) 1686 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */ 1687 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */ 1688 1689 /****************** Bit definition for DAC_DHR8R2 register ******************/ 1690 #define DAC_DHR8R2_DACC2DHR_Pos (0U) 1691 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */ 1692 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */ 1693 1694 /***************** Bit definition for DAC_DHR12RD register ******************/ 1695 #define DAC_DHR12RD_DACC1DHR_Pos (0U) 1696 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */ 1697 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */ 1698 #define DAC_DHR12RD_DACC2DHR_Pos (16U) 1699 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */ 1700 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */ 1701 1702 /***************** Bit definition for DAC_DHR12LD register ******************/ 1703 #define DAC_DHR12LD_DACC1DHR_Pos (4U) 1704 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */ 1705 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */ 1706 #define DAC_DHR12LD_DACC2DHR_Pos (20U) 1707 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */ 1708 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */ 1709 1710 /****************** Bit definition for DAC_DHR8RD register ******************/ 1711 #define DAC_DHR8RD_DACC1DHR_Pos (0U) 1712 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */ 1713 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */ 1714 #define DAC_DHR8RD_DACC2DHR_Pos (8U) 1715 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */ 1716 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */ 1717 1718 /******************* Bit definition for DAC_DOR1 register *******************/ 1719 #define DAC_DOR1_DACC1DOR_Pos (0U) 1720 #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ 1721 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */ 1722 1723 /******************* Bit definition for DAC_DOR2 register *******************/ 1724 #define DAC_DOR2_DACC2DOR_Pos (0U) 1725 #define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */ 1726 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */ 1727 1728 /******************** Bit definition for DAC_SR register ********************/ 1729 #define DAC_SR_DMAUDR1_Pos (13U) 1730 #define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ 1731 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */ 1732 #define DAC_SR_DMAUDR2_Pos (29U) 1733 #define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */ 1734 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */ 1735 1736 /******************************************************************************/ 1737 /* */ 1738 /* Debug MCU (DBGMCU) */ 1739 /* */ 1740 /******************************************************************************/ 1741 1742 /**************** Bit definition for DBGMCU_IDCODE register *****************/ 1743 #define DBGMCU_IDCODE_DEV_ID_Pos (0U) 1744 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ 1745 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */ 1746 1747 #define DBGMCU_IDCODE_REV_ID_Pos (16U) 1748 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ 1749 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ 1750 #define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */ 1751 #define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */ 1752 #define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */ 1753 #define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */ 1754 #define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */ 1755 #define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */ 1756 #define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */ 1757 #define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */ 1758 #define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */ 1759 #define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */ 1760 #define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */ 1761 #define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */ 1762 #define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */ 1763 #define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */ 1764 #define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */ 1765 #define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */ 1766 1767 /****************** Bit definition for DBGMCU_CR register *******************/ 1768 #define DBGMCU_CR_DBG_SLEEP_Pos (0U) 1769 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ 1770 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */ 1771 #define DBGMCU_CR_DBG_STOP_Pos (1U) 1772 #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ 1773 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */ 1774 #define DBGMCU_CR_DBG_STANDBY_Pos (2U) 1775 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ 1776 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */ 1777 #define DBGMCU_CR_TRACE_IOEN_Pos (5U) 1778 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */ 1779 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */ 1780 1781 #define DBGMCU_CR_TRACE_MODE_Pos (6U) 1782 #define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ 1783 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ 1784 #define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ 1785 #define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ 1786 1787 /****************** Bit definition for DBGMCU_APB1_FZ register **************/ 1788 1789 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U) 1790 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ 1791 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */ 1792 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U) 1793 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ 1794 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */ 1795 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U) 1796 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */ 1797 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */ 1798 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U) 1799 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ 1800 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */ 1801 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U) 1802 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ 1803 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */ 1804 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) 1805 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ 1806 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */ 1807 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) 1808 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ 1809 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */ 1810 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U) 1811 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */ 1812 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */ 1813 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U) 1814 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */ 1815 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */ 1816 1817 /****************** Bit definition for DBGMCU_APB2_FZ register **************/ 1818 1819 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (2U) 1820 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */ 1821 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */ 1822 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (3U) 1823 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */ 1824 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */ 1825 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (4U) 1826 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */ 1827 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */ 1828 1829 /******************************************************************************/ 1830 /* */ 1831 /* DMA Controller (DMA) */ 1832 /* */ 1833 /******************************************************************************/ 1834 1835 /******************* Bit definition for DMA_ISR register ********************/ 1836 #define DMA_ISR_GIF1_Pos (0U) 1837 #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ 1838 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ 1839 #define DMA_ISR_TCIF1_Pos (1U) 1840 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ 1841 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ 1842 #define DMA_ISR_HTIF1_Pos (2U) 1843 #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ 1844 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ 1845 #define DMA_ISR_TEIF1_Pos (3U) 1846 #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ 1847 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ 1848 #define DMA_ISR_GIF2_Pos (4U) 1849 #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ 1850 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ 1851 #define DMA_ISR_TCIF2_Pos (5U) 1852 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ 1853 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ 1854 #define DMA_ISR_HTIF2_Pos (6U) 1855 #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ 1856 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ 1857 #define DMA_ISR_TEIF2_Pos (7U) 1858 #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ 1859 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ 1860 #define DMA_ISR_GIF3_Pos (8U) 1861 #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ 1862 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ 1863 #define DMA_ISR_TCIF3_Pos (9U) 1864 #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ 1865 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ 1866 #define DMA_ISR_HTIF3_Pos (10U) 1867 #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ 1868 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ 1869 #define DMA_ISR_TEIF3_Pos (11U) 1870 #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ 1871 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ 1872 #define DMA_ISR_GIF4_Pos (12U) 1873 #define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ 1874 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ 1875 #define DMA_ISR_TCIF4_Pos (13U) 1876 #define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ 1877 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ 1878 #define DMA_ISR_HTIF4_Pos (14U) 1879 #define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ 1880 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ 1881 #define DMA_ISR_TEIF4_Pos (15U) 1882 #define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ 1883 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ 1884 #define DMA_ISR_GIF5_Pos (16U) 1885 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ 1886 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ 1887 #define DMA_ISR_TCIF5_Pos (17U) 1888 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ 1889 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ 1890 #define DMA_ISR_HTIF5_Pos (18U) 1891 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ 1892 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ 1893 #define DMA_ISR_TEIF5_Pos (19U) 1894 #define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ 1895 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ 1896 #define DMA_ISR_GIF6_Pos (20U) 1897 #define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ 1898 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ 1899 #define DMA_ISR_TCIF6_Pos (21U) 1900 #define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ 1901 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ 1902 #define DMA_ISR_HTIF6_Pos (22U) 1903 #define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ 1904 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ 1905 #define DMA_ISR_TEIF6_Pos (23U) 1906 #define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ 1907 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ 1908 #define DMA_ISR_GIF7_Pos (24U) 1909 #define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ 1910 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ 1911 #define DMA_ISR_TCIF7_Pos (25U) 1912 #define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ 1913 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ 1914 #define DMA_ISR_HTIF7_Pos (26U) 1915 #define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ 1916 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ 1917 #define DMA_ISR_TEIF7_Pos (27U) 1918 #define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ 1919 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ 1920 1921 /******************* Bit definition for DMA_IFCR register *******************/ 1922 #define DMA_IFCR_CGIF1_Pos (0U) 1923 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ 1924 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ 1925 #define DMA_IFCR_CTCIF1_Pos (1U) 1926 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ 1927 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ 1928 #define DMA_IFCR_CHTIF1_Pos (2U) 1929 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ 1930 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ 1931 #define DMA_IFCR_CTEIF1_Pos (3U) 1932 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ 1933 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ 1934 #define DMA_IFCR_CGIF2_Pos (4U) 1935 #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ 1936 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ 1937 #define DMA_IFCR_CTCIF2_Pos (5U) 1938 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ 1939 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ 1940 #define DMA_IFCR_CHTIF2_Pos (6U) 1941 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ 1942 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ 1943 #define DMA_IFCR_CTEIF2_Pos (7U) 1944 #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ 1945 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ 1946 #define DMA_IFCR_CGIF3_Pos (8U) 1947 #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ 1948 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ 1949 #define DMA_IFCR_CTCIF3_Pos (9U) 1950 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ 1951 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ 1952 #define DMA_IFCR_CHTIF3_Pos (10U) 1953 #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ 1954 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ 1955 #define DMA_IFCR_CTEIF3_Pos (11U) 1956 #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ 1957 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ 1958 #define DMA_IFCR_CGIF4_Pos (12U) 1959 #define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ 1960 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ 1961 #define DMA_IFCR_CTCIF4_Pos (13U) 1962 #define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ 1963 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ 1964 #define DMA_IFCR_CHTIF4_Pos (14U) 1965 #define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ 1966 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ 1967 #define DMA_IFCR_CTEIF4_Pos (15U) 1968 #define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ 1969 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ 1970 #define DMA_IFCR_CGIF5_Pos (16U) 1971 #define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ 1972 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ 1973 #define DMA_IFCR_CTCIF5_Pos (17U) 1974 #define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ 1975 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ 1976 #define DMA_IFCR_CHTIF5_Pos (18U) 1977 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ 1978 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ 1979 #define DMA_IFCR_CTEIF5_Pos (19U) 1980 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ 1981 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ 1982 #define DMA_IFCR_CGIF6_Pos (20U) 1983 #define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ 1984 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ 1985 #define DMA_IFCR_CTCIF6_Pos (21U) 1986 #define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ 1987 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ 1988 #define DMA_IFCR_CHTIF6_Pos (22U) 1989 #define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ 1990 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ 1991 #define DMA_IFCR_CTEIF6_Pos (23U) 1992 #define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ 1993 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ 1994 #define DMA_IFCR_CGIF7_Pos (24U) 1995 #define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ 1996 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ 1997 #define DMA_IFCR_CTCIF7_Pos (25U) 1998 #define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ 1999 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ 2000 #define DMA_IFCR_CHTIF7_Pos (26U) 2001 #define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ 2002 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ 2003 #define DMA_IFCR_CTEIF7_Pos (27U) 2004 #define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ 2005 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ 2006 2007 /******************* Bit definition for DMA_CCR register *******************/ 2008 #define DMA_CCR_EN_Pos (0U) 2009 #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ 2010 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable*/ 2011 #define DMA_CCR_TCIE_Pos (1U) 2012 #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ 2013 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ 2014 #define DMA_CCR_HTIE_Pos (2U) 2015 #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ 2016 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ 2017 #define DMA_CCR_TEIE_Pos (3U) 2018 #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ 2019 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ 2020 #define DMA_CCR_DIR_Pos (4U) 2021 #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ 2022 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ 2023 #define DMA_CCR_CIRC_Pos (5U) 2024 #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ 2025 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ 2026 #define DMA_CCR_PINC_Pos (6U) 2027 #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ 2028 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ 2029 #define DMA_CCR_MINC_Pos (7U) 2030 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ 2031 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ 2032 2033 #define DMA_CCR_PSIZE_Pos (8U) 2034 #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ 2035 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ 2036 #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ 2037 #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ 2038 2039 #define DMA_CCR_MSIZE_Pos (10U) 2040 #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ 2041 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ 2042 #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ 2043 #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ 2044 2045 #define DMA_CCR_PL_Pos (12U) 2046 #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ 2047 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */ 2048 #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ 2049 #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ 2050 2051 #define DMA_CCR_MEM2MEM_Pos (14U) 2052 #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ 2053 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ 2054 2055 /****************** Bit definition generic for DMA_CNDTR register *******************/ 2056 #define DMA_CNDTR_NDT_Pos (0U) 2057 #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ 2058 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ 2059 2060 /****************** Bit definition for DMA_CNDTR1 register ******************/ 2061 #define DMA_CNDTR1_NDT_Pos (0U) 2062 #define DMA_CNDTR1_NDT_Msk (0xFFFFUL << DMA_CNDTR1_NDT_Pos) /*!< 0x0000FFFF */ 2063 #define DMA_CNDTR1_NDT DMA_CNDTR1_NDT_Msk /*!< Number of data to Transfer */ 2064 2065 /****************** Bit definition for DMA_CNDTR2 register ******************/ 2066 #define DMA_CNDTR2_NDT_Pos (0U) 2067 #define DMA_CNDTR2_NDT_Msk (0xFFFFUL << DMA_CNDTR2_NDT_Pos) /*!< 0x0000FFFF */ 2068 #define DMA_CNDTR2_NDT DMA_CNDTR2_NDT_Msk /*!< Number of data to Transfer */ 2069 2070 /****************** Bit definition for DMA_CNDTR3 register ******************/ 2071 #define DMA_CNDTR3_NDT_Pos (0U) 2072 #define DMA_CNDTR3_NDT_Msk (0xFFFFUL << DMA_CNDTR3_NDT_Pos) /*!< 0x0000FFFF */ 2073 #define DMA_CNDTR3_NDT DMA_CNDTR3_NDT_Msk /*!< Number of data to Transfer */ 2074 2075 /****************** Bit definition for DMA_CNDTR4 register ******************/ 2076 #define DMA_CNDTR4_NDT_Pos (0U) 2077 #define DMA_CNDTR4_NDT_Msk (0xFFFFUL << DMA_CNDTR4_NDT_Pos) /*!< 0x0000FFFF */ 2078 #define DMA_CNDTR4_NDT DMA_CNDTR4_NDT_Msk /*!< Number of data to Transfer */ 2079 2080 /****************** Bit definition for DMA_CNDTR5 register ******************/ 2081 #define DMA_CNDTR5_NDT_Pos (0U) 2082 #define DMA_CNDTR5_NDT_Msk (0xFFFFUL << DMA_CNDTR5_NDT_Pos) /*!< 0x0000FFFF */ 2083 #define DMA_CNDTR5_NDT DMA_CNDTR5_NDT_Msk /*!< Number of data to Transfer */ 2084 2085 /****************** Bit definition for DMA_CNDTR6 register ******************/ 2086 #define DMA_CNDTR6_NDT_Pos (0U) 2087 #define DMA_CNDTR6_NDT_Msk (0xFFFFUL << DMA_CNDTR6_NDT_Pos) /*!< 0x0000FFFF */ 2088 #define DMA_CNDTR6_NDT DMA_CNDTR6_NDT_Msk /*!< Number of data to Transfer */ 2089 2090 /****************** Bit definition for DMA_CNDTR7 register ******************/ 2091 #define DMA_CNDTR7_NDT_Pos (0U) 2092 #define DMA_CNDTR7_NDT_Msk (0xFFFFUL << DMA_CNDTR7_NDT_Pos) /*!< 0x0000FFFF */ 2093 #define DMA_CNDTR7_NDT DMA_CNDTR7_NDT_Msk /*!< Number of data to Transfer */ 2094 2095 /****************** Bit definition generic for DMA_CPAR register ********************/ 2096 #define DMA_CPAR_PA_Pos (0U) 2097 #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ 2098 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ 2099 2100 /****************** Bit definition for DMA_CPAR1 register *******************/ 2101 #define DMA_CPAR1_PA_Pos (0U) 2102 #define DMA_CPAR1_PA_Msk (0xFFFFFFFFUL << DMA_CPAR1_PA_Pos) /*!< 0xFFFFFFFF */ 2103 #define DMA_CPAR1_PA DMA_CPAR1_PA_Msk /*!< Peripheral Address */ 2104 2105 /****************** Bit definition for DMA_CPAR2 register *******************/ 2106 #define DMA_CPAR2_PA_Pos (0U) 2107 #define DMA_CPAR2_PA_Msk (0xFFFFFFFFUL << DMA_CPAR2_PA_Pos) /*!< 0xFFFFFFFF */ 2108 #define DMA_CPAR2_PA DMA_CPAR2_PA_Msk /*!< Peripheral Address */ 2109 2110 /****************** Bit definition for DMA_CPAR3 register *******************/ 2111 #define DMA_CPAR3_PA_Pos (0U) 2112 #define DMA_CPAR3_PA_Msk (0xFFFFFFFFUL << DMA_CPAR3_PA_Pos) /*!< 0xFFFFFFFF */ 2113 #define DMA_CPAR3_PA DMA_CPAR3_PA_Msk /*!< Peripheral Address */ 2114 2115 2116 /****************** Bit definition for DMA_CPAR4 register *******************/ 2117 #define DMA_CPAR4_PA_Pos (0U) 2118 #define DMA_CPAR4_PA_Msk (0xFFFFFFFFUL << DMA_CPAR4_PA_Pos) /*!< 0xFFFFFFFF */ 2119 #define DMA_CPAR4_PA DMA_CPAR4_PA_Msk /*!< Peripheral Address */ 2120 2121 /****************** Bit definition for DMA_CPAR5 register *******************/ 2122 #define DMA_CPAR5_PA_Pos (0U) 2123 #define DMA_CPAR5_PA_Msk (0xFFFFFFFFUL << DMA_CPAR5_PA_Pos) /*!< 0xFFFFFFFF */ 2124 #define DMA_CPAR5_PA DMA_CPAR5_PA_Msk /*!< Peripheral Address */ 2125 2126 /****************** Bit definition for DMA_CPAR6 register *******************/ 2127 #define DMA_CPAR6_PA_Pos (0U) 2128 #define DMA_CPAR6_PA_Msk (0xFFFFFFFFUL << DMA_CPAR6_PA_Pos) /*!< 0xFFFFFFFF */ 2129 #define DMA_CPAR6_PA DMA_CPAR6_PA_Msk /*!< Peripheral Address */ 2130 2131 2132 /****************** Bit definition for DMA_CPAR7 register *******************/ 2133 #define DMA_CPAR7_PA_Pos (0U) 2134 #define DMA_CPAR7_PA_Msk (0xFFFFFFFFUL << DMA_CPAR7_PA_Pos) /*!< 0xFFFFFFFF */ 2135 #define DMA_CPAR7_PA DMA_CPAR7_PA_Msk /*!< Peripheral Address */ 2136 2137 /****************** Bit definition generic for DMA_CMAR register ********************/ 2138 #define DMA_CMAR_MA_Pos (0U) 2139 #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ 2140 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ 2141 2142 /****************** Bit definition for DMA_CMAR1 register *******************/ 2143 #define DMA_CMAR1_MA_Pos (0U) 2144 #define DMA_CMAR1_MA_Msk (0xFFFFFFFFUL << DMA_CMAR1_MA_Pos) /*!< 0xFFFFFFFF */ 2145 #define DMA_CMAR1_MA DMA_CMAR1_MA_Msk /*!< Memory Address */ 2146 2147 /****************** Bit definition for DMA_CMAR2 register *******************/ 2148 #define DMA_CMAR2_MA_Pos (0U) 2149 #define DMA_CMAR2_MA_Msk (0xFFFFFFFFUL << DMA_CMAR2_MA_Pos) /*!< 0xFFFFFFFF */ 2150 #define DMA_CMAR2_MA DMA_CMAR2_MA_Msk /*!< Memory Address */ 2151 2152 /****************** Bit definition for DMA_CMAR3 register *******************/ 2153 #define DMA_CMAR3_MA_Pos (0U) 2154 #define DMA_CMAR3_MA_Msk (0xFFFFFFFFUL << DMA_CMAR3_MA_Pos) /*!< 0xFFFFFFFF */ 2155 #define DMA_CMAR3_MA DMA_CMAR3_MA_Msk /*!< Memory Address */ 2156 2157 2158 /****************** Bit definition for DMA_CMAR4 register *******************/ 2159 #define DMA_CMAR4_MA_Pos (0U) 2160 #define DMA_CMAR4_MA_Msk (0xFFFFFFFFUL << DMA_CMAR4_MA_Pos) /*!< 0xFFFFFFFF */ 2161 #define DMA_CMAR4_MA DMA_CMAR4_MA_Msk /*!< Memory Address */ 2162 2163 /****************** Bit definition for DMA_CMAR5 register *******************/ 2164 #define DMA_CMAR5_MA_Pos (0U) 2165 #define DMA_CMAR5_MA_Msk (0xFFFFFFFFUL << DMA_CMAR5_MA_Pos) /*!< 0xFFFFFFFF */ 2166 #define DMA_CMAR5_MA DMA_CMAR5_MA_Msk /*!< Memory Address */ 2167 2168 /****************** Bit definition for DMA_CMAR6 register *******************/ 2169 #define DMA_CMAR6_MA_Pos (0U) 2170 #define DMA_CMAR6_MA_Msk (0xFFFFFFFFUL << DMA_CMAR6_MA_Pos) /*!< 0xFFFFFFFF */ 2171 #define DMA_CMAR6_MA DMA_CMAR6_MA_Msk /*!< Memory Address */ 2172 2173 /****************** Bit definition for DMA_CMAR7 register *******************/ 2174 #define DMA_CMAR7_MA_Pos (0U) 2175 #define DMA_CMAR7_MA_Msk (0xFFFFFFFFUL << DMA_CMAR7_MA_Pos) /*!< 0xFFFFFFFF */ 2176 #define DMA_CMAR7_MA DMA_CMAR7_MA_Msk /*!< Memory Address */ 2177 2178 /******************************************************************************/ 2179 /* */ 2180 /* External Interrupt/Event Controller (EXTI) */ 2181 /* */ 2182 /******************************************************************************/ 2183 2184 /******************* Bit definition for EXTI_IMR register *******************/ 2185 #define EXTI_IMR_MR0_Pos (0U) 2186 #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ 2187 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ 2188 #define EXTI_IMR_MR1_Pos (1U) 2189 #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ 2190 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ 2191 #define EXTI_IMR_MR2_Pos (2U) 2192 #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ 2193 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ 2194 #define EXTI_IMR_MR3_Pos (3U) 2195 #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ 2196 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ 2197 #define EXTI_IMR_MR4_Pos (4U) 2198 #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ 2199 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ 2200 #define EXTI_IMR_MR5_Pos (5U) 2201 #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ 2202 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ 2203 #define EXTI_IMR_MR6_Pos (6U) 2204 #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ 2205 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ 2206 #define EXTI_IMR_MR7_Pos (7U) 2207 #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ 2208 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ 2209 #define EXTI_IMR_MR8_Pos (8U) 2210 #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ 2211 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ 2212 #define EXTI_IMR_MR9_Pos (9U) 2213 #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ 2214 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ 2215 #define EXTI_IMR_MR10_Pos (10U) 2216 #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ 2217 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ 2218 #define EXTI_IMR_MR11_Pos (11U) 2219 #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ 2220 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ 2221 #define EXTI_IMR_MR12_Pos (12U) 2222 #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ 2223 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ 2224 #define EXTI_IMR_MR13_Pos (13U) 2225 #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ 2226 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ 2227 #define EXTI_IMR_MR14_Pos (14U) 2228 #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ 2229 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ 2230 #define EXTI_IMR_MR15_Pos (15U) 2231 #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ 2232 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ 2233 #define EXTI_IMR_MR16_Pos (16U) 2234 #define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ 2235 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ 2236 #define EXTI_IMR_MR17_Pos (17U) 2237 #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ 2238 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ 2239 #define EXTI_IMR_MR18_Pos (18U) 2240 #define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ 2241 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ 2242 #define EXTI_IMR_MR19_Pos (19U) 2243 #define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */ 2244 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */ 2245 #define EXTI_IMR_MR20_Pos (20U) 2246 #define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */ 2247 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */ 2248 #define EXTI_IMR_MR21_Pos (21U) 2249 #define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */ 2250 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */ 2251 #define EXTI_IMR_MR22_Pos (22U) 2252 #define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */ 2253 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */ 2254 /* Catgeroy 1 & 2 */ 2255 2256 /* References Defines */ 2257 #define EXTI_IMR_IM0 EXTI_IMR_MR0 2258 #define EXTI_IMR_IM1 EXTI_IMR_MR1 2259 #define EXTI_IMR_IM2 EXTI_IMR_MR2 2260 #define EXTI_IMR_IM3 EXTI_IMR_MR3 2261 #define EXTI_IMR_IM4 EXTI_IMR_MR4 2262 #define EXTI_IMR_IM5 EXTI_IMR_MR5 2263 #define EXTI_IMR_IM6 EXTI_IMR_MR6 2264 #define EXTI_IMR_IM7 EXTI_IMR_MR7 2265 #define EXTI_IMR_IM8 EXTI_IMR_MR8 2266 #define EXTI_IMR_IM9 EXTI_IMR_MR9 2267 #define EXTI_IMR_IM10 EXTI_IMR_MR10 2268 #define EXTI_IMR_IM11 EXTI_IMR_MR11 2269 #define EXTI_IMR_IM12 EXTI_IMR_MR12 2270 #define EXTI_IMR_IM13 EXTI_IMR_MR13 2271 #define EXTI_IMR_IM14 EXTI_IMR_MR14 2272 #define EXTI_IMR_IM15 EXTI_IMR_MR15 2273 #define EXTI_IMR_IM16 EXTI_IMR_MR16 2274 #define EXTI_IMR_IM17 EXTI_IMR_MR17 2275 #define EXTI_IMR_IM18 EXTI_IMR_MR18 2276 #define EXTI_IMR_IM19 EXTI_IMR_MR19 2277 #define EXTI_IMR_IM20 EXTI_IMR_MR20 2278 #define EXTI_IMR_IM21 EXTI_IMR_MR21 2279 #define EXTI_IMR_IM22 EXTI_IMR_MR22 2280 /* Catgeroy 1 & 2 */ 2281 #define EXTI_IMR_IM_Pos (0U) 2282 #define EXTI_IMR_IM_Msk (0x7FFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */ 2283 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */ 2284 2285 /******************* Bit definition for EXTI_EMR register *******************/ 2286 #define EXTI_EMR_MR0_Pos (0U) 2287 #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ 2288 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ 2289 #define EXTI_EMR_MR1_Pos (1U) 2290 #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ 2291 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ 2292 #define EXTI_EMR_MR2_Pos (2U) 2293 #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ 2294 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ 2295 #define EXTI_EMR_MR3_Pos (3U) 2296 #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ 2297 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ 2298 #define EXTI_EMR_MR4_Pos (4U) 2299 #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ 2300 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ 2301 #define EXTI_EMR_MR5_Pos (5U) 2302 #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ 2303 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ 2304 #define EXTI_EMR_MR6_Pos (6U) 2305 #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ 2306 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ 2307 #define EXTI_EMR_MR7_Pos (7U) 2308 #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ 2309 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ 2310 #define EXTI_EMR_MR8_Pos (8U) 2311 #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ 2312 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ 2313 #define EXTI_EMR_MR9_Pos (9U) 2314 #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ 2315 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ 2316 #define EXTI_EMR_MR10_Pos (10U) 2317 #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ 2318 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ 2319 #define EXTI_EMR_MR11_Pos (11U) 2320 #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ 2321 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ 2322 #define EXTI_EMR_MR12_Pos (12U) 2323 #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ 2324 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ 2325 #define EXTI_EMR_MR13_Pos (13U) 2326 #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ 2327 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ 2328 #define EXTI_EMR_MR14_Pos (14U) 2329 #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ 2330 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ 2331 #define EXTI_EMR_MR15_Pos (15U) 2332 #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ 2333 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ 2334 #define EXTI_EMR_MR16_Pos (16U) 2335 #define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ 2336 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ 2337 #define EXTI_EMR_MR17_Pos (17U) 2338 #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ 2339 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ 2340 #define EXTI_EMR_MR18_Pos (18U) 2341 #define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ 2342 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ 2343 #define EXTI_EMR_MR19_Pos (19U) 2344 #define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */ 2345 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */ 2346 #define EXTI_EMR_MR20_Pos (20U) 2347 #define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */ 2348 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */ 2349 #define EXTI_EMR_MR21_Pos (21U) 2350 #define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */ 2351 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */ 2352 #define EXTI_EMR_MR22_Pos (22U) 2353 #define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */ 2354 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */ 2355 2356 /* References Defines */ 2357 #define EXTI_EMR_EM0 EXTI_EMR_MR0 2358 #define EXTI_EMR_EM1 EXTI_EMR_MR1 2359 #define EXTI_EMR_EM2 EXTI_EMR_MR2 2360 #define EXTI_EMR_EM3 EXTI_EMR_MR3 2361 #define EXTI_EMR_EM4 EXTI_EMR_MR4 2362 #define EXTI_EMR_EM5 EXTI_EMR_MR5 2363 #define EXTI_EMR_EM6 EXTI_EMR_MR6 2364 #define EXTI_EMR_EM7 EXTI_EMR_MR7 2365 #define EXTI_EMR_EM8 EXTI_EMR_MR8 2366 #define EXTI_EMR_EM9 EXTI_EMR_MR9 2367 #define EXTI_EMR_EM10 EXTI_EMR_MR10 2368 #define EXTI_EMR_EM11 EXTI_EMR_MR11 2369 #define EXTI_EMR_EM12 EXTI_EMR_MR12 2370 #define EXTI_EMR_EM13 EXTI_EMR_MR13 2371 #define EXTI_EMR_EM14 EXTI_EMR_MR14 2372 #define EXTI_EMR_EM15 EXTI_EMR_MR15 2373 #define EXTI_EMR_EM16 EXTI_EMR_MR16 2374 #define EXTI_EMR_EM17 EXTI_EMR_MR17 2375 #define EXTI_EMR_EM18 EXTI_EMR_MR18 2376 #define EXTI_EMR_EM19 EXTI_EMR_MR19 2377 #define EXTI_EMR_EM20 EXTI_EMR_MR20 2378 #define EXTI_EMR_EM21 EXTI_EMR_MR21 2379 #define EXTI_EMR_EM22 EXTI_EMR_MR22 2380 2381 /****************** Bit definition for EXTI_RTSR register *******************/ 2382 #define EXTI_RTSR_TR0_Pos (0U) 2383 #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ 2384 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ 2385 #define EXTI_RTSR_TR1_Pos (1U) 2386 #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ 2387 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ 2388 #define EXTI_RTSR_TR2_Pos (2U) 2389 #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ 2390 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ 2391 #define EXTI_RTSR_TR3_Pos (3U) 2392 #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ 2393 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ 2394 #define EXTI_RTSR_TR4_Pos (4U) 2395 #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ 2396 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ 2397 #define EXTI_RTSR_TR5_Pos (5U) 2398 #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ 2399 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ 2400 #define EXTI_RTSR_TR6_Pos (6U) 2401 #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ 2402 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ 2403 #define EXTI_RTSR_TR7_Pos (7U) 2404 #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ 2405 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ 2406 #define EXTI_RTSR_TR8_Pos (8U) 2407 #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ 2408 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ 2409 #define EXTI_RTSR_TR9_Pos (9U) 2410 #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ 2411 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ 2412 #define EXTI_RTSR_TR10_Pos (10U) 2413 #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ 2414 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ 2415 #define EXTI_RTSR_TR11_Pos (11U) 2416 #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ 2417 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ 2418 #define EXTI_RTSR_TR12_Pos (12U) 2419 #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ 2420 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ 2421 #define EXTI_RTSR_TR13_Pos (13U) 2422 #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ 2423 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ 2424 #define EXTI_RTSR_TR14_Pos (14U) 2425 #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ 2426 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ 2427 #define EXTI_RTSR_TR15_Pos (15U) 2428 #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ 2429 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ 2430 #define EXTI_RTSR_TR16_Pos (16U) 2431 #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ 2432 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ 2433 #define EXTI_RTSR_TR17_Pos (17U) 2434 #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ 2435 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ 2436 #define EXTI_RTSR_TR18_Pos (18U) 2437 #define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */ 2438 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */ 2439 #define EXTI_RTSR_TR19_Pos (19U) 2440 #define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */ 2441 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */ 2442 #define EXTI_RTSR_TR20_Pos (20U) 2443 #define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */ 2444 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */ 2445 #define EXTI_RTSR_TR21_Pos (21U) 2446 #define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */ 2447 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */ 2448 #define EXTI_RTSR_TR22_Pos (22U) 2449 #define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */ 2450 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */ 2451 2452 /* References Defines */ 2453 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0 2454 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1 2455 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2 2456 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3 2457 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4 2458 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5 2459 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6 2460 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7 2461 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8 2462 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9 2463 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10 2464 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11 2465 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12 2466 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13 2467 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14 2468 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15 2469 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16 2470 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17 2471 #define EXTI_RTSR_RT18 EXTI_RTSR_TR18 2472 #define EXTI_RTSR_RT19 EXTI_RTSR_TR19 2473 #define EXTI_RTSR_RT20 EXTI_RTSR_TR20 2474 #define EXTI_RTSR_RT21 EXTI_RTSR_TR21 2475 #define EXTI_RTSR_RT22 EXTI_RTSR_TR22 2476 2477 /****************** Bit definition for EXTI_FTSR register *******************/ 2478 #define EXTI_FTSR_TR0_Pos (0U) 2479 #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ 2480 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ 2481 #define EXTI_FTSR_TR1_Pos (1U) 2482 #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ 2483 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ 2484 #define EXTI_FTSR_TR2_Pos (2U) 2485 #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ 2486 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ 2487 #define EXTI_FTSR_TR3_Pos (3U) 2488 #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ 2489 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ 2490 #define EXTI_FTSR_TR4_Pos (4U) 2491 #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ 2492 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ 2493 #define EXTI_FTSR_TR5_Pos (5U) 2494 #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ 2495 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ 2496 #define EXTI_FTSR_TR6_Pos (6U) 2497 #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ 2498 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ 2499 #define EXTI_FTSR_TR7_Pos (7U) 2500 #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ 2501 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ 2502 #define EXTI_FTSR_TR8_Pos (8U) 2503 #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ 2504 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ 2505 #define EXTI_FTSR_TR9_Pos (9U) 2506 #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ 2507 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ 2508 #define EXTI_FTSR_TR10_Pos (10U) 2509 #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ 2510 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ 2511 #define EXTI_FTSR_TR11_Pos (11U) 2512 #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ 2513 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ 2514 #define EXTI_FTSR_TR12_Pos (12U) 2515 #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ 2516 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ 2517 #define EXTI_FTSR_TR13_Pos (13U) 2518 #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ 2519 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ 2520 #define EXTI_FTSR_TR14_Pos (14U) 2521 #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ 2522 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ 2523 #define EXTI_FTSR_TR15_Pos (15U) 2524 #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ 2525 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ 2526 #define EXTI_FTSR_TR16_Pos (16U) 2527 #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ 2528 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ 2529 #define EXTI_FTSR_TR17_Pos (17U) 2530 #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ 2531 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ 2532 #define EXTI_FTSR_TR18_Pos (18U) 2533 #define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */ 2534 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */ 2535 #define EXTI_FTSR_TR19_Pos (19U) 2536 #define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */ 2537 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */ 2538 #define EXTI_FTSR_TR20_Pos (20U) 2539 #define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */ 2540 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */ 2541 #define EXTI_FTSR_TR21_Pos (21U) 2542 #define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */ 2543 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */ 2544 #define EXTI_FTSR_TR22_Pos (22U) 2545 #define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */ 2546 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */ 2547 2548 /* References Defines */ 2549 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0 2550 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1 2551 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2 2552 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3 2553 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4 2554 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5 2555 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6 2556 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7 2557 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8 2558 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9 2559 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10 2560 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11 2561 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12 2562 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13 2563 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14 2564 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15 2565 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16 2566 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17 2567 #define EXTI_FTSR_FT18 EXTI_FTSR_TR18 2568 #define EXTI_FTSR_FT19 EXTI_FTSR_TR19 2569 #define EXTI_FTSR_FT20 EXTI_FTSR_TR20 2570 #define EXTI_FTSR_FT21 EXTI_FTSR_TR21 2571 #define EXTI_FTSR_FT22 EXTI_FTSR_TR22 2572 2573 /****************** Bit definition for EXTI_SWIER register ******************/ 2574 #define EXTI_SWIER_SWIER0_Pos (0U) 2575 #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ 2576 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ 2577 #define EXTI_SWIER_SWIER1_Pos (1U) 2578 #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ 2579 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ 2580 #define EXTI_SWIER_SWIER2_Pos (2U) 2581 #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ 2582 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ 2583 #define EXTI_SWIER_SWIER3_Pos (3U) 2584 #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ 2585 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ 2586 #define EXTI_SWIER_SWIER4_Pos (4U) 2587 #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ 2588 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ 2589 #define EXTI_SWIER_SWIER5_Pos (5U) 2590 #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ 2591 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ 2592 #define EXTI_SWIER_SWIER6_Pos (6U) 2593 #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ 2594 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ 2595 #define EXTI_SWIER_SWIER7_Pos (7U) 2596 #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ 2597 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ 2598 #define EXTI_SWIER_SWIER8_Pos (8U) 2599 #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ 2600 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ 2601 #define EXTI_SWIER_SWIER9_Pos (9U) 2602 #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ 2603 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ 2604 #define EXTI_SWIER_SWIER10_Pos (10U) 2605 #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ 2606 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ 2607 #define EXTI_SWIER_SWIER11_Pos (11U) 2608 #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ 2609 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ 2610 #define EXTI_SWIER_SWIER12_Pos (12U) 2611 #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ 2612 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ 2613 #define EXTI_SWIER_SWIER13_Pos (13U) 2614 #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ 2615 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ 2616 #define EXTI_SWIER_SWIER14_Pos (14U) 2617 #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ 2618 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ 2619 #define EXTI_SWIER_SWIER15_Pos (15U) 2620 #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ 2621 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ 2622 #define EXTI_SWIER_SWIER16_Pos (16U) 2623 #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ 2624 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ 2625 #define EXTI_SWIER_SWIER17_Pos (17U) 2626 #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ 2627 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ 2628 #define EXTI_SWIER_SWIER18_Pos (18U) 2629 #define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */ 2630 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */ 2631 #define EXTI_SWIER_SWIER19_Pos (19U) 2632 #define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */ 2633 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */ 2634 #define EXTI_SWIER_SWIER20_Pos (20U) 2635 #define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */ 2636 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */ 2637 #define EXTI_SWIER_SWIER21_Pos (21U) 2638 #define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */ 2639 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */ 2640 #define EXTI_SWIER_SWIER22_Pos (22U) 2641 #define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */ 2642 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */ 2643 2644 /* References Defines */ 2645 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 2646 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 2647 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 2648 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 2649 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 2650 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 2651 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 2652 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 2653 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 2654 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 2655 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 2656 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 2657 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 2658 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 2659 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 2660 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 2661 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 2662 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 2663 #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18 2664 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19 2665 #define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20 2666 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21 2667 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22 2668 2669 /******************* Bit definition for EXTI_PR register ********************/ 2670 #define EXTI_PR_PR0_Pos (0U) 2671 #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ 2672 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ 2673 #define EXTI_PR_PR1_Pos (1U) 2674 #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ 2675 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ 2676 #define EXTI_PR_PR2_Pos (2U) 2677 #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ 2678 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ 2679 #define EXTI_PR_PR3_Pos (3U) 2680 #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ 2681 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ 2682 #define EXTI_PR_PR4_Pos (4U) 2683 #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ 2684 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ 2685 #define EXTI_PR_PR5_Pos (5U) 2686 #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ 2687 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ 2688 #define EXTI_PR_PR6_Pos (6U) 2689 #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ 2690 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ 2691 #define EXTI_PR_PR7_Pos (7U) 2692 #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ 2693 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ 2694 #define EXTI_PR_PR8_Pos (8U) 2695 #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ 2696 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ 2697 #define EXTI_PR_PR9_Pos (9U) 2698 #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ 2699 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ 2700 #define EXTI_PR_PR10_Pos (10U) 2701 #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ 2702 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ 2703 #define EXTI_PR_PR11_Pos (11U) 2704 #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ 2705 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ 2706 #define EXTI_PR_PR12_Pos (12U) 2707 #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ 2708 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ 2709 #define EXTI_PR_PR13_Pos (13U) 2710 #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ 2711 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ 2712 #define EXTI_PR_PR14_Pos (14U) 2713 #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ 2714 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ 2715 #define EXTI_PR_PR15_Pos (15U) 2716 #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ 2717 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ 2718 #define EXTI_PR_PR16_Pos (16U) 2719 #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ 2720 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ 2721 #define EXTI_PR_PR17_Pos (17U) 2722 #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ 2723 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ 2724 #define EXTI_PR_PR18_Pos (18U) 2725 #define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos) /*!< 0x00040000 */ 2726 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */ 2727 #define EXTI_PR_PR19_Pos (19U) 2728 #define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos) /*!< 0x00080000 */ 2729 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */ 2730 #define EXTI_PR_PR20_Pos (20U) 2731 #define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos) /*!< 0x00100000 */ 2732 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */ 2733 #define EXTI_PR_PR21_Pos (21U) 2734 #define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos) /*!< 0x00200000 */ 2735 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */ 2736 #define EXTI_PR_PR22_Pos (22U) 2737 #define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos) /*!< 0x00400000 */ 2738 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */ 2739 2740 /* References Defines */ 2741 #define EXTI_PR_PIF0 EXTI_PR_PR0 2742 #define EXTI_PR_PIF1 EXTI_PR_PR1 2743 #define EXTI_PR_PIF2 EXTI_PR_PR2 2744 #define EXTI_PR_PIF3 EXTI_PR_PR3 2745 #define EXTI_PR_PIF4 EXTI_PR_PR4 2746 #define EXTI_PR_PIF5 EXTI_PR_PR5 2747 #define EXTI_PR_PIF6 EXTI_PR_PR6 2748 #define EXTI_PR_PIF7 EXTI_PR_PR7 2749 #define EXTI_PR_PIF8 EXTI_PR_PR8 2750 #define EXTI_PR_PIF9 EXTI_PR_PR9 2751 #define EXTI_PR_PIF10 EXTI_PR_PR10 2752 #define EXTI_PR_PIF11 EXTI_PR_PR11 2753 #define EXTI_PR_PIF12 EXTI_PR_PR12 2754 #define EXTI_PR_PIF13 EXTI_PR_PR13 2755 #define EXTI_PR_PIF14 EXTI_PR_PR14 2756 #define EXTI_PR_PIF15 EXTI_PR_PR15 2757 #define EXTI_PR_PIF16 EXTI_PR_PR16 2758 #define EXTI_PR_PIF17 EXTI_PR_PR17 2759 #define EXTI_PR_PIF18 EXTI_PR_PR18 2760 #define EXTI_PR_PIF19 EXTI_PR_PR19 2761 #define EXTI_PR_PIF20 EXTI_PR_PR20 2762 #define EXTI_PR_PIF21 EXTI_PR_PR21 2763 #define EXTI_PR_PIF22 EXTI_PR_PR22 2764 2765 /******************************************************************************/ 2766 /* */ 2767 /* FLASH, DATA EEPROM and Option Bytes Registers */ 2768 /* (FLASH, DATA_EEPROM, OB) */ 2769 /* */ 2770 /******************************************************************************/ 2771 /* 2772 * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie) 2773 */ 2774 #define FLASH_CUT1 2775 2776 /******************* Bit definition for FLASH_ACR register ******************/ 2777 #define FLASH_ACR_LATENCY_Pos (0U) 2778 #define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ 2779 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ 2780 #define FLASH_ACR_PRFTEN_Pos (1U) 2781 #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */ 2782 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */ 2783 #define FLASH_ACR_ACC64_Pos (2U) 2784 #define FLASH_ACR_ACC64_Msk (0x1UL << FLASH_ACR_ACC64_Pos) /*!< 0x00000004 */ 2785 #define FLASH_ACR_ACC64 FLASH_ACR_ACC64_Msk /*!< Access 64 bits */ 2786 #define FLASH_ACR_SLEEP_PD_Pos (3U) 2787 #define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */ 2788 #define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */ 2789 #define FLASH_ACR_RUN_PD_Pos (4U) 2790 #define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */ 2791 #define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */ 2792 2793 /******************* Bit definition for FLASH_PECR register ******************/ 2794 #define FLASH_PECR_PELOCK_Pos (0U) 2795 #define FLASH_PECR_PELOCK_Msk (0x1UL << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */ 2796 #define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */ 2797 #define FLASH_PECR_PRGLOCK_Pos (1U) 2798 #define FLASH_PECR_PRGLOCK_Msk (0x1UL << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */ 2799 #define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */ 2800 #define FLASH_PECR_OPTLOCK_Pos (2U) 2801 #define FLASH_PECR_OPTLOCK_Msk (0x1UL << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */ 2802 #define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */ 2803 #define FLASH_PECR_PROG_Pos (3U) 2804 #define FLASH_PECR_PROG_Msk (0x1UL << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */ 2805 #define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */ 2806 #define FLASH_PECR_DATA_Pos (4U) 2807 #define FLASH_PECR_DATA_Msk (0x1UL << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */ 2808 #define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */ 2809 #define FLASH_PECR_FTDW_Pos (8U) 2810 #define FLASH_PECR_FTDW_Msk (0x1UL << FLASH_PECR_FTDW_Pos) /*!< 0x00000100 */ 2811 #define FLASH_PECR_FTDW FLASH_PECR_FTDW_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */ 2812 #define FLASH_PECR_ERASE_Pos (9U) 2813 #define FLASH_PECR_ERASE_Msk (0x1UL << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */ 2814 #define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */ 2815 #define FLASH_PECR_FPRG_Pos (10U) 2816 #define FLASH_PECR_FPRG_Msk (0x1UL << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */ 2817 #define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */ 2818 #define FLASH_PECR_EOPIE_Pos (16U) 2819 #define FLASH_PECR_EOPIE_Msk (0x1UL << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */ 2820 #define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */ 2821 #define FLASH_PECR_ERRIE_Pos (17U) 2822 #define FLASH_PECR_ERRIE_Msk (0x1UL << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */ 2823 #define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */ 2824 #define FLASH_PECR_OBL_LAUNCH_Pos (18U) 2825 #define FLASH_PECR_OBL_LAUNCH_Msk (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */ 2826 #define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */ 2827 2828 /****************** Bit definition for FLASH_PDKEYR register ******************/ 2829 #define FLASH_PDKEYR_PDKEYR_Pos (0U) 2830 #define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */ 2831 #define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */ 2832 2833 /****************** Bit definition for FLASH_PEKEYR register ******************/ 2834 #define FLASH_PEKEYR_PEKEYR_Pos (0U) 2835 #define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */ 2836 #define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */ 2837 2838 /****************** Bit definition for FLASH_PRGKEYR register ******************/ 2839 #define FLASH_PRGKEYR_PRGKEYR_Pos (0U) 2840 #define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */ 2841 #define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */ 2842 2843 /****************** Bit definition for FLASH_OPTKEYR register ******************/ 2844 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U) 2845 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ 2846 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */ 2847 2848 /****************** Bit definition for FLASH_SR register *******************/ 2849 #define FLASH_SR_BSY_Pos (0U) 2850 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ 2851 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ 2852 #define FLASH_SR_EOP_Pos (1U) 2853 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000002 */ 2854 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/ 2855 #define FLASH_SR_ENDHV_Pos (2U) 2856 #define FLASH_SR_ENDHV_Msk (0x1UL << FLASH_SR_ENDHV_Pos) /*!< 0x00000004 */ 2857 #define FLASH_SR_ENDHV FLASH_SR_ENDHV_Msk /*!< End of high voltage */ 2858 #define FLASH_SR_READY_Pos (3U) 2859 #define FLASH_SR_READY_Msk (0x1UL << FLASH_SR_READY_Pos) /*!< 0x00000008 */ 2860 #define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */ 2861 2862 #define FLASH_SR_WRPERR_Pos (8U) 2863 #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */ 2864 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protected error */ 2865 #define FLASH_SR_PGAERR_Pos (9U) 2866 #define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */ 2867 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */ 2868 #define FLASH_SR_SIZERR_Pos (10U) 2869 #define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */ 2870 #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */ 2871 #define FLASH_SR_OPTVERR_Pos (11U) 2872 #define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */ 2873 #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option validity error */ 2874 2875 /****************** Bit definition for FLASH_OBR register *******************/ 2876 #define FLASH_OBR_RDPRT_Pos (0U) 2877 #define FLASH_OBR_RDPRT_Msk (0xFFUL << FLASH_OBR_RDPRT_Pos) /*!< 0x000000FF */ 2878 #define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read Protection */ 2879 #define FLASH_OBR_BOR_LEV_Pos (16U) 2880 #define FLASH_OBR_BOR_LEV_Msk (0xFUL << FLASH_OBR_BOR_LEV_Pos) /*!< 0x000F0000 */ 2881 #define FLASH_OBR_BOR_LEV FLASH_OBR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/ 2882 #define FLASH_OBR_USER_Pos (20U) 2883 #define FLASH_OBR_USER_Msk (0x7UL << FLASH_OBR_USER_Pos) /*!< 0x00700000 */ 2884 #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */ 2885 #define FLASH_OBR_IWDG_SW_Pos (20U) 2886 #define FLASH_OBR_IWDG_SW_Msk (0x1UL << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00100000 */ 2887 #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG_SW */ 2888 #define FLASH_OBR_nRST_STOP_Pos (21U) 2889 #define FLASH_OBR_nRST_STOP_Msk (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */ 2890 #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */ 2891 #define FLASH_OBR_nRST_STDBY_Pos (22U) 2892 #define FLASH_OBR_nRST_STDBY_Msk (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */ 2893 #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */ 2894 2895 /****************** Bit definition for FLASH_WRPR register ******************/ 2896 #define FLASH_WRPR1_WRP_Pos (0U) 2897 #define FLASH_WRPR1_WRP_Msk (0xFFFFFFFFUL << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */ 2898 #define FLASH_WRPR1_WRP FLASH_WRPR1_WRP_Msk /*!< Write Protect sectors 0 to 31 */ 2899 2900 /******************************************************************************/ 2901 /* */ 2902 /* General Purpose I/O */ 2903 /* */ 2904 /******************************************************************************/ 2905 /****************** Bits definition for GPIO_MODER register *****************/ 2906 #define GPIO_MODER_MODER0_Pos (0U) 2907 #define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ 2908 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk 2909 #define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ 2910 #define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ 2911 2912 #define GPIO_MODER_MODER1_Pos (2U) 2913 #define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ 2914 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk 2915 #define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ 2916 #define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ 2917 2918 #define GPIO_MODER_MODER2_Pos (4U) 2919 #define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ 2920 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk 2921 #define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ 2922 #define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ 2923 2924 #define GPIO_MODER_MODER3_Pos (6U) 2925 #define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ 2926 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk 2927 #define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ 2928 #define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ 2929 2930 #define GPIO_MODER_MODER4_Pos (8U) 2931 #define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ 2932 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk 2933 #define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ 2934 #define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ 2935 2936 #define GPIO_MODER_MODER5_Pos (10U) 2937 #define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ 2938 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk 2939 #define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ 2940 #define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ 2941 2942 #define GPIO_MODER_MODER6_Pos (12U) 2943 #define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ 2944 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk 2945 #define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ 2946 #define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ 2947 2948 #define GPIO_MODER_MODER7_Pos (14U) 2949 #define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ 2950 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk 2951 #define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ 2952 #define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ 2953 2954 #define GPIO_MODER_MODER8_Pos (16U) 2955 #define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ 2956 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk 2957 #define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ 2958 #define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ 2959 2960 #define GPIO_MODER_MODER9_Pos (18U) 2961 #define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ 2962 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk 2963 #define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ 2964 #define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ 2965 2966 #define GPIO_MODER_MODER10_Pos (20U) 2967 #define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ 2968 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk 2969 #define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ 2970 #define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ 2971 2972 #define GPIO_MODER_MODER11_Pos (22U) 2973 #define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ 2974 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk 2975 #define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ 2976 #define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ 2977 2978 #define GPIO_MODER_MODER12_Pos (24U) 2979 #define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ 2980 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk 2981 #define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ 2982 #define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ 2983 2984 #define GPIO_MODER_MODER13_Pos (26U) 2985 #define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ 2986 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk 2987 #define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ 2988 #define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ 2989 2990 #define GPIO_MODER_MODER14_Pos (28U) 2991 #define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ 2992 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk 2993 #define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ 2994 #define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ 2995 2996 #define GPIO_MODER_MODER15_Pos (30U) 2997 #define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ 2998 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk 2999 #define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ 3000 #define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ 3001 3002 /****************** Bits definition for GPIO_OTYPER register ****************/ 3003 #define GPIO_OTYPER_OT_0 (0x00000001U) 3004 #define GPIO_OTYPER_OT_1 (0x00000002U) 3005 #define GPIO_OTYPER_OT_2 (0x00000004U) 3006 #define GPIO_OTYPER_OT_3 (0x00000008U) 3007 #define GPIO_OTYPER_OT_4 (0x00000010U) 3008 #define GPIO_OTYPER_OT_5 (0x00000020U) 3009 #define GPIO_OTYPER_OT_6 (0x00000040U) 3010 #define GPIO_OTYPER_OT_7 (0x00000080U) 3011 #define GPIO_OTYPER_OT_8 (0x00000100U) 3012 #define GPIO_OTYPER_OT_9 (0x00000200U) 3013 #define GPIO_OTYPER_OT_10 (0x00000400U) 3014 #define GPIO_OTYPER_OT_11 (0x00000800U) 3015 #define GPIO_OTYPER_OT_12 (0x00001000U) 3016 #define GPIO_OTYPER_OT_13 (0x00002000U) 3017 #define GPIO_OTYPER_OT_14 (0x00004000U) 3018 #define GPIO_OTYPER_OT_15 (0x00008000U) 3019 3020 /****************** Bits definition for GPIO_OSPEEDR register ***************/ 3021 #define GPIO_OSPEEDER_OSPEEDR0_Pos (0U) 3022 #define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */ 3023 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk 3024 #define GPIO_OSPEEDER_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */ 3025 #define GPIO_OSPEEDER_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */ 3026 3027 #define GPIO_OSPEEDER_OSPEEDR1_Pos (2U) 3028 #define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */ 3029 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk 3030 #define GPIO_OSPEEDER_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */ 3031 #define GPIO_OSPEEDER_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */ 3032 3033 #define GPIO_OSPEEDER_OSPEEDR2_Pos (4U) 3034 #define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */ 3035 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk 3036 #define GPIO_OSPEEDER_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */ 3037 #define GPIO_OSPEEDER_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */ 3038 3039 #define GPIO_OSPEEDER_OSPEEDR3_Pos (6U) 3040 #define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */ 3041 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk 3042 #define GPIO_OSPEEDER_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */ 3043 #define GPIO_OSPEEDER_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */ 3044 3045 #define GPIO_OSPEEDER_OSPEEDR4_Pos (8U) 3046 #define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */ 3047 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk 3048 #define GPIO_OSPEEDER_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */ 3049 #define GPIO_OSPEEDER_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */ 3050 3051 #define GPIO_OSPEEDER_OSPEEDR5_Pos (10U) 3052 #define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */ 3053 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk 3054 #define GPIO_OSPEEDER_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */ 3055 #define GPIO_OSPEEDER_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */ 3056 3057 #define GPIO_OSPEEDER_OSPEEDR6_Pos (12U) 3058 #define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */ 3059 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk 3060 #define GPIO_OSPEEDER_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */ 3061 #define GPIO_OSPEEDER_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */ 3062 3063 #define GPIO_OSPEEDER_OSPEEDR7_Pos (14U) 3064 #define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */ 3065 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk 3066 #define GPIO_OSPEEDER_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */ 3067 #define GPIO_OSPEEDER_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */ 3068 3069 #define GPIO_OSPEEDER_OSPEEDR8_Pos (16U) 3070 #define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */ 3071 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk 3072 #define GPIO_OSPEEDER_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */ 3073 #define GPIO_OSPEEDER_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */ 3074 3075 #define GPIO_OSPEEDER_OSPEEDR9_Pos (18U) 3076 #define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */ 3077 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk 3078 #define GPIO_OSPEEDER_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */ 3079 #define GPIO_OSPEEDER_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */ 3080 3081 #define GPIO_OSPEEDER_OSPEEDR10_Pos (20U) 3082 #define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */ 3083 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk 3084 #define GPIO_OSPEEDER_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */ 3085 #define GPIO_OSPEEDER_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */ 3086 3087 #define GPIO_OSPEEDER_OSPEEDR11_Pos (22U) 3088 #define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */ 3089 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk 3090 #define GPIO_OSPEEDER_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */ 3091 #define GPIO_OSPEEDER_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */ 3092 3093 #define GPIO_OSPEEDER_OSPEEDR12_Pos (24U) 3094 #define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */ 3095 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk 3096 #define GPIO_OSPEEDER_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */ 3097 #define GPIO_OSPEEDER_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */ 3098 3099 #define GPIO_OSPEEDER_OSPEEDR13_Pos (26U) 3100 #define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */ 3101 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk 3102 #define GPIO_OSPEEDER_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */ 3103 #define GPIO_OSPEEDER_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */ 3104 3105 #define GPIO_OSPEEDER_OSPEEDR14_Pos (28U) 3106 #define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */ 3107 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk 3108 #define GPIO_OSPEEDER_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */ 3109 #define GPIO_OSPEEDER_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */ 3110 3111 #define GPIO_OSPEEDER_OSPEEDR15_Pos (30U) 3112 #define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */ 3113 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk 3114 #define GPIO_OSPEEDER_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */ 3115 #define GPIO_OSPEEDER_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */ 3116 3117 /****************** Bits definition for GPIO_PUPDR register *****************/ 3118 #define GPIO_PUPDR_PUPDR0_Pos (0U) 3119 #define GPIO_PUPDR_PUPDR0_Msk (0x3UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */ 3120 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk 3121 #define GPIO_PUPDR_PUPDR0_0 (0x1UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */ 3122 #define GPIO_PUPDR_PUPDR0_1 (0x2UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */ 3123 3124 #define GPIO_PUPDR_PUPDR1_Pos (2U) 3125 #define GPIO_PUPDR_PUPDR1_Msk (0x3UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */ 3126 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk 3127 #define GPIO_PUPDR_PUPDR1_0 (0x1UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */ 3128 #define GPIO_PUPDR_PUPDR1_1 (0x2UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */ 3129 3130 #define GPIO_PUPDR_PUPDR2_Pos (4U) 3131 #define GPIO_PUPDR_PUPDR2_Msk (0x3UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */ 3132 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk 3133 #define GPIO_PUPDR_PUPDR2_0 (0x1UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */ 3134 #define GPIO_PUPDR_PUPDR2_1 (0x2UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */ 3135 3136 #define GPIO_PUPDR_PUPDR3_Pos (6U) 3137 #define GPIO_PUPDR_PUPDR3_Msk (0x3UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */ 3138 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk 3139 #define GPIO_PUPDR_PUPDR3_0 (0x1UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */ 3140 #define GPIO_PUPDR_PUPDR3_1 (0x2UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */ 3141 3142 #define GPIO_PUPDR_PUPDR4_Pos (8U) 3143 #define GPIO_PUPDR_PUPDR4_Msk (0x3UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */ 3144 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk 3145 #define GPIO_PUPDR_PUPDR4_0 (0x1UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */ 3146 #define GPIO_PUPDR_PUPDR4_1 (0x2UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */ 3147 3148 #define GPIO_PUPDR_PUPDR5_Pos (10U) 3149 #define GPIO_PUPDR_PUPDR5_Msk (0x3UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */ 3150 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk 3151 #define GPIO_PUPDR_PUPDR5_0 (0x1UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */ 3152 #define GPIO_PUPDR_PUPDR5_1 (0x2UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */ 3153 3154 #define GPIO_PUPDR_PUPDR6_Pos (12U) 3155 #define GPIO_PUPDR_PUPDR6_Msk (0x3UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */ 3156 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk 3157 #define GPIO_PUPDR_PUPDR6_0 (0x1UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */ 3158 #define GPIO_PUPDR_PUPDR6_1 (0x2UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */ 3159 3160 #define GPIO_PUPDR_PUPDR7_Pos (14U) 3161 #define GPIO_PUPDR_PUPDR7_Msk (0x3UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */ 3162 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk 3163 #define GPIO_PUPDR_PUPDR7_0 (0x1UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */ 3164 #define GPIO_PUPDR_PUPDR7_1 (0x2UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */ 3165 3166 #define GPIO_PUPDR_PUPDR8_Pos (16U) 3167 #define GPIO_PUPDR_PUPDR8_Msk (0x3UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */ 3168 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk 3169 #define GPIO_PUPDR_PUPDR8_0 (0x1UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */ 3170 #define GPIO_PUPDR_PUPDR8_1 (0x2UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */ 3171 3172 #define GPIO_PUPDR_PUPDR9_Pos (18U) 3173 #define GPIO_PUPDR_PUPDR9_Msk (0x3UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */ 3174 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk 3175 #define GPIO_PUPDR_PUPDR9_0 (0x1UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */ 3176 #define GPIO_PUPDR_PUPDR9_1 (0x2UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */ 3177 3178 #define GPIO_PUPDR_PUPDR10_Pos (20U) 3179 #define GPIO_PUPDR_PUPDR10_Msk (0x3UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */ 3180 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk 3181 #define GPIO_PUPDR_PUPDR10_0 (0x1UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */ 3182 #define GPIO_PUPDR_PUPDR10_1 (0x2UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */ 3183 3184 #define GPIO_PUPDR_PUPDR11_Pos (22U) 3185 #define GPIO_PUPDR_PUPDR11_Msk (0x3UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */ 3186 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk 3187 #define GPIO_PUPDR_PUPDR11_0 (0x1UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */ 3188 #define GPIO_PUPDR_PUPDR11_1 (0x2UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */ 3189 3190 #define GPIO_PUPDR_PUPDR12_Pos (24U) 3191 #define GPIO_PUPDR_PUPDR12_Msk (0x3UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */ 3192 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk 3193 #define GPIO_PUPDR_PUPDR12_0 (0x1UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */ 3194 #define GPIO_PUPDR_PUPDR12_1 (0x2UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */ 3195 3196 #define GPIO_PUPDR_PUPDR13_Pos (26U) 3197 #define GPIO_PUPDR_PUPDR13_Msk (0x3UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */ 3198 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk 3199 #define GPIO_PUPDR_PUPDR13_0 (0x1UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */ 3200 #define GPIO_PUPDR_PUPDR13_1 (0x2UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */ 3201 3202 #define GPIO_PUPDR_PUPDR14_Pos (28U) 3203 #define GPIO_PUPDR_PUPDR14_Msk (0x3UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */ 3204 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk 3205 #define GPIO_PUPDR_PUPDR14_0 (0x1UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */ 3206 #define GPIO_PUPDR_PUPDR14_1 (0x2UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */ 3207 #define GPIO_PUPDR_PUPDR15_Pos (30U) 3208 #define GPIO_PUPDR_PUPDR15_Msk (0x3UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */ 3209 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk 3210 #define GPIO_PUPDR_PUPDR15_0 (0x1UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */ 3211 #define GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ 3212 3213 /****************** Bits definition for GPIO_IDR register *******************/ 3214 #define GPIO_IDR_IDR_0 (0x00000001U) 3215 #define GPIO_IDR_IDR_1 (0x00000002U) 3216 #define GPIO_IDR_IDR_2 (0x00000004U) 3217 #define GPIO_IDR_IDR_3 (0x00000008U) 3218 #define GPIO_IDR_IDR_4 (0x00000010U) 3219 #define GPIO_IDR_IDR_5 (0x00000020U) 3220 #define GPIO_IDR_IDR_6 (0x00000040U) 3221 #define GPIO_IDR_IDR_7 (0x00000080U) 3222 #define GPIO_IDR_IDR_8 (0x00000100U) 3223 #define GPIO_IDR_IDR_9 (0x00000200U) 3224 #define GPIO_IDR_IDR_10 (0x00000400U) 3225 #define GPIO_IDR_IDR_11 (0x00000800U) 3226 #define GPIO_IDR_IDR_12 (0x00001000U) 3227 #define GPIO_IDR_IDR_13 (0x00002000U) 3228 #define GPIO_IDR_IDR_14 (0x00004000U) 3229 #define GPIO_IDR_IDR_15 (0x00008000U) 3230 3231 /****************** Bits definition for GPIO_ODR register *******************/ 3232 #define GPIO_ODR_ODR_0 (0x00000001U) 3233 #define GPIO_ODR_ODR_1 (0x00000002U) 3234 #define GPIO_ODR_ODR_2 (0x00000004U) 3235 #define GPIO_ODR_ODR_3 (0x00000008U) 3236 #define GPIO_ODR_ODR_4 (0x00000010U) 3237 #define GPIO_ODR_ODR_5 (0x00000020U) 3238 #define GPIO_ODR_ODR_6 (0x00000040U) 3239 #define GPIO_ODR_ODR_7 (0x00000080U) 3240 #define GPIO_ODR_ODR_8 (0x00000100U) 3241 #define GPIO_ODR_ODR_9 (0x00000200U) 3242 #define GPIO_ODR_ODR_10 (0x00000400U) 3243 #define GPIO_ODR_ODR_11 (0x00000800U) 3244 #define GPIO_ODR_ODR_12 (0x00001000U) 3245 #define GPIO_ODR_ODR_13 (0x00002000U) 3246 #define GPIO_ODR_ODR_14 (0x00004000U) 3247 #define GPIO_ODR_ODR_15 (0x00008000U) 3248 3249 /****************** Bits definition for GPIO_BSRR register ******************/ 3250 #define GPIO_BSRR_BS_0 (0x00000001U) 3251 #define GPIO_BSRR_BS_1 (0x00000002U) 3252 #define GPIO_BSRR_BS_2 (0x00000004U) 3253 #define GPIO_BSRR_BS_3 (0x00000008U) 3254 #define GPIO_BSRR_BS_4 (0x00000010U) 3255 #define GPIO_BSRR_BS_5 (0x00000020U) 3256 #define GPIO_BSRR_BS_6 (0x00000040U) 3257 #define GPIO_BSRR_BS_7 (0x00000080U) 3258 #define GPIO_BSRR_BS_8 (0x00000100U) 3259 #define GPIO_BSRR_BS_9 (0x00000200U) 3260 #define GPIO_BSRR_BS_10 (0x00000400U) 3261 #define GPIO_BSRR_BS_11 (0x00000800U) 3262 #define GPIO_BSRR_BS_12 (0x00001000U) 3263 #define GPIO_BSRR_BS_13 (0x00002000U) 3264 #define GPIO_BSRR_BS_14 (0x00004000U) 3265 #define GPIO_BSRR_BS_15 (0x00008000U) 3266 #define GPIO_BSRR_BR_0 (0x00010000U) 3267 #define GPIO_BSRR_BR_1 (0x00020000U) 3268 #define GPIO_BSRR_BR_2 (0x00040000U) 3269 #define GPIO_BSRR_BR_3 (0x00080000U) 3270 #define GPIO_BSRR_BR_4 (0x00100000U) 3271 #define GPIO_BSRR_BR_5 (0x00200000U) 3272 #define GPIO_BSRR_BR_6 (0x00400000U) 3273 #define GPIO_BSRR_BR_7 (0x00800000U) 3274 #define GPIO_BSRR_BR_8 (0x01000000U) 3275 #define GPIO_BSRR_BR_9 (0x02000000U) 3276 #define GPIO_BSRR_BR_10 (0x04000000U) 3277 #define GPIO_BSRR_BR_11 (0x08000000U) 3278 #define GPIO_BSRR_BR_12 (0x10000000U) 3279 #define GPIO_BSRR_BR_13 (0x20000000U) 3280 #define GPIO_BSRR_BR_14 (0x40000000U) 3281 #define GPIO_BSRR_BR_15 (0x80000000U) 3282 3283 /****************** Bit definition for GPIO_LCKR register ********************/ 3284 #define GPIO_LCKR_LCK0_Pos (0U) 3285 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ 3286 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk 3287 #define GPIO_LCKR_LCK1_Pos (1U) 3288 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ 3289 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk 3290 #define GPIO_LCKR_LCK2_Pos (2U) 3291 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ 3292 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk 3293 #define GPIO_LCKR_LCK3_Pos (3U) 3294 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ 3295 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk 3296 #define GPIO_LCKR_LCK4_Pos (4U) 3297 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ 3298 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk 3299 #define GPIO_LCKR_LCK5_Pos (5U) 3300 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ 3301 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk 3302 #define GPIO_LCKR_LCK6_Pos (6U) 3303 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ 3304 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk 3305 #define GPIO_LCKR_LCK7_Pos (7U) 3306 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ 3307 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk 3308 #define GPIO_LCKR_LCK8_Pos (8U) 3309 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ 3310 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk 3311 #define GPIO_LCKR_LCK9_Pos (9U) 3312 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ 3313 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk 3314 #define GPIO_LCKR_LCK10_Pos (10U) 3315 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ 3316 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk 3317 #define GPIO_LCKR_LCK11_Pos (11U) 3318 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ 3319 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk 3320 #define GPIO_LCKR_LCK12_Pos (12U) 3321 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ 3322 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk 3323 #define GPIO_LCKR_LCK13_Pos (13U) 3324 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ 3325 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk 3326 #define GPIO_LCKR_LCK14_Pos (14U) 3327 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ 3328 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk 3329 #define GPIO_LCKR_LCK15_Pos (15U) 3330 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ 3331 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk 3332 #define GPIO_LCKR_LCKK_Pos (16U) 3333 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ 3334 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk 3335 3336 /****************** Bit definition for GPIO_AFRL register ********************/ 3337 #define GPIO_AFRL_AFSEL0_Pos (0U) 3338 #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ 3339 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk 3340 #define GPIO_AFRL_AFSEL1_Pos (4U) 3341 #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ 3342 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk 3343 #define GPIO_AFRL_AFSEL2_Pos (8U) 3344 #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ 3345 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk 3346 #define GPIO_AFRL_AFSEL3_Pos (12U) 3347 #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ 3348 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk 3349 #define GPIO_AFRL_AFSEL4_Pos (16U) 3350 #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ 3351 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk 3352 #define GPIO_AFRL_AFSEL5_Pos (20U) 3353 #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ 3354 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk 3355 #define GPIO_AFRL_AFSEL6_Pos (24U) 3356 #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ 3357 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk 3358 #define GPIO_AFRL_AFSEL7_Pos (28U) 3359 #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ 3360 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk 3361 3362 /****************** Bit definition for GPIO_AFRH register ********************/ 3363 #define GPIO_AFRH_AFSEL8_Pos (0U) 3364 #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ 3365 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk 3366 #define GPIO_AFRH_AFSEL9_Pos (4U) 3367 #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ 3368 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk 3369 #define GPIO_AFRH_AFSEL10_Pos (8U) 3370 #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ 3371 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk 3372 #define GPIO_AFRH_AFSEL11_Pos (12U) 3373 #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ 3374 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk 3375 #define GPIO_AFRH_AFSEL12_Pos (16U) 3376 #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ 3377 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk 3378 #define GPIO_AFRH_AFSEL13_Pos (20U) 3379 #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ 3380 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk 3381 #define GPIO_AFRH_AFSEL14_Pos (24U) 3382 #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ 3383 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk 3384 #define GPIO_AFRH_AFSEL15_Pos (28U) 3385 #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ 3386 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk 3387 3388 /******************************************************************************/ 3389 /* */ 3390 /* Inter-integrated Circuit Interface (I2C) */ 3391 /* */ 3392 /******************************************************************************/ 3393 3394 /******************* Bit definition for I2C_CR1 register ********************/ 3395 #define I2C_CR1_PE_Pos (0U) 3396 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ 3397 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */ 3398 #define I2C_CR1_SMBUS_Pos (1U) 3399 #define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */ 3400 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */ 3401 #define I2C_CR1_SMBTYPE_Pos (3U) 3402 #define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */ 3403 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */ 3404 #define I2C_CR1_ENARP_Pos (4U) 3405 #define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */ 3406 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */ 3407 #define I2C_CR1_ENPEC_Pos (5U) 3408 #define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */ 3409 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */ 3410 #define I2C_CR1_ENGC_Pos (6U) 3411 #define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */ 3412 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */ 3413 #define I2C_CR1_NOSTRETCH_Pos (7U) 3414 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */ 3415 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */ 3416 #define I2C_CR1_START_Pos (8U) 3417 #define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos) /*!< 0x00000100 */ 3418 #define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */ 3419 #define I2C_CR1_STOP_Pos (9U) 3420 #define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos) /*!< 0x00000200 */ 3421 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */ 3422 #define I2C_CR1_ACK_Pos (10U) 3423 #define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos) /*!< 0x00000400 */ 3424 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */ 3425 #define I2C_CR1_POS_Pos (11U) 3426 #define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos) /*!< 0x00000800 */ 3427 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */ 3428 #define I2C_CR1_PEC_Pos (12U) 3429 #define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos) /*!< 0x00001000 */ 3430 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */ 3431 #define I2C_CR1_ALERT_Pos (13U) 3432 #define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */ 3433 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */ 3434 #define I2C_CR1_SWRST_Pos (15U) 3435 #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */ 3436 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */ 3437 3438 /******************* Bit definition for I2C_CR2 register ********************/ 3439 #define I2C_CR2_FREQ_Pos (0U) 3440 #define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */ 3441 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ 3442 #define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */ 3443 #define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */ 3444 #define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */ 3445 #define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */ 3446 #define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */ 3447 #define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */ 3448 3449 #define I2C_CR2_ITERREN_Pos (8U) 3450 #define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */ 3451 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */ 3452 #define I2C_CR2_ITEVTEN_Pos (9U) 3453 #define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */ 3454 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */ 3455 #define I2C_CR2_ITBUFEN_Pos (10U) 3456 #define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */ 3457 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */ 3458 #define I2C_CR2_DMAEN_Pos (11U) 3459 #define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */ 3460 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */ 3461 #define I2C_CR2_LAST_Pos (12U) 3462 #define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos) /*!< 0x00001000 */ 3463 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */ 3464 3465 /******************* Bit definition for I2C_OAR1 register *******************/ 3466 #define I2C_OAR1_ADD1_7 (0x000000FEU) /*!< Interface Address */ 3467 #define I2C_OAR1_ADD8_9 (0x00000300U) /*!< Interface Address */ 3468 3469 #define I2C_OAR1_ADD0_Pos (0U) 3470 #define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */ 3471 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */ 3472 #define I2C_OAR1_ADD1_Pos (1U) 3473 #define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */ 3474 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */ 3475 #define I2C_OAR1_ADD2_Pos (2U) 3476 #define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */ 3477 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */ 3478 #define I2C_OAR1_ADD3_Pos (3U) 3479 #define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */ 3480 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */ 3481 #define I2C_OAR1_ADD4_Pos (4U) 3482 #define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */ 3483 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */ 3484 #define I2C_OAR1_ADD5_Pos (5U) 3485 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */ 3486 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */ 3487 #define I2C_OAR1_ADD6_Pos (6U) 3488 #define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */ 3489 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */ 3490 #define I2C_OAR1_ADD7_Pos (7U) 3491 #define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */ 3492 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */ 3493 #define I2C_OAR1_ADD8_Pos (8U) 3494 #define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */ 3495 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */ 3496 #define I2C_OAR1_ADD9_Pos (9U) 3497 #define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */ 3498 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */ 3499 3500 #define I2C_OAR1_ADDMODE_Pos (15U) 3501 #define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */ 3502 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */ 3503 3504 /******************* Bit definition for I2C_OAR2 register *******************/ 3505 #define I2C_OAR2_ENDUAL_Pos (0U) 3506 #define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */ 3507 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */ 3508 #define I2C_OAR2_ADD2_Pos (1U) 3509 #define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */ 3510 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */ 3511 3512 /******************** Bit definition for I2C_DR register ********************/ 3513 #define I2C_DR_DR_Pos (0U) 3514 #define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos) /*!< 0x000000FF */ 3515 #define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */ 3516 3517 /******************* Bit definition for I2C_SR1 register ********************/ 3518 #define I2C_SR1_SB_Pos (0U) 3519 #define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos) /*!< 0x00000001 */ 3520 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */ 3521 #define I2C_SR1_ADDR_Pos (1U) 3522 #define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */ 3523 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */ 3524 #define I2C_SR1_BTF_Pos (2U) 3525 #define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos) /*!< 0x00000004 */ 3526 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */ 3527 #define I2C_SR1_ADD10_Pos (3U) 3528 #define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */ 3529 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */ 3530 #define I2C_SR1_STOPF_Pos (4U) 3531 #define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */ 3532 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */ 3533 #define I2C_SR1_RXNE_Pos (6U) 3534 #define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */ 3535 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */ 3536 #define I2C_SR1_TXE_Pos (7U) 3537 #define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos) /*!< 0x00000080 */ 3538 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */ 3539 #define I2C_SR1_BERR_Pos (8U) 3540 #define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos) /*!< 0x00000100 */ 3541 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */ 3542 #define I2C_SR1_ARLO_Pos (9U) 3543 #define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */ 3544 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */ 3545 #define I2C_SR1_AF_Pos (10U) 3546 #define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos) /*!< 0x00000400 */ 3547 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */ 3548 #define I2C_SR1_OVR_Pos (11U) 3549 #define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos) /*!< 0x00000800 */ 3550 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */ 3551 #define I2C_SR1_PECERR_Pos (12U) 3552 #define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */ 3553 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */ 3554 #define I2C_SR1_TIMEOUT_Pos (14U) 3555 #define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */ 3556 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */ 3557 #define I2C_SR1_SMBALERT_Pos (15U) 3558 #define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */ 3559 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */ 3560 3561 /******************* Bit definition for I2C_SR2 register ********************/ 3562 #define I2C_SR2_MSL_Pos (0U) 3563 #define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos) /*!< 0x00000001 */ 3564 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */ 3565 #define I2C_SR2_BUSY_Pos (1U) 3566 #define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */ 3567 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */ 3568 #define I2C_SR2_TRA_Pos (2U) 3569 #define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos) /*!< 0x00000004 */ 3570 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */ 3571 #define I2C_SR2_GENCALL_Pos (4U) 3572 #define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */ 3573 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */ 3574 #define I2C_SR2_SMBDEFAULT_Pos (5U) 3575 #define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */ 3576 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */ 3577 #define I2C_SR2_SMBHOST_Pos (6U) 3578 #define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */ 3579 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */ 3580 #define I2C_SR2_DUALF_Pos (7U) 3581 #define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */ 3582 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */ 3583 #define I2C_SR2_PEC_Pos (8U) 3584 #define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */ 3585 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */ 3586 3587 /******************* Bit definition for I2C_CCR register ********************/ 3588 #define I2C_CCR_CCR_Pos (0U) 3589 #define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */ 3590 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */ 3591 #define I2C_CCR_DUTY_Pos (14U) 3592 #define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */ 3593 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */ 3594 #define I2C_CCR_FS_Pos (15U) 3595 #define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos) /*!< 0x00008000 */ 3596 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */ 3597 3598 /****************** Bit definition for I2C_TRISE register *******************/ 3599 #define I2C_TRISE_TRISE_Pos (0U) 3600 #define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */ 3601 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ 3602 3603 /******************************************************************************/ 3604 /* */ 3605 /* Independent WATCHDOG (IWDG) */ 3606 /* */ 3607 /******************************************************************************/ 3608 3609 /******************* Bit definition for IWDG_KR register ********************/ 3610 #define IWDG_KR_KEY_Pos (0U) 3611 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ 3612 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ 3613 3614 /******************* Bit definition for IWDG_PR register ********************/ 3615 #define IWDG_PR_PR_Pos (0U) 3616 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */ 3617 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ 3618 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */ 3619 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */ 3620 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */ 3621 3622 /******************* Bit definition for IWDG_RLR register *******************/ 3623 #define IWDG_RLR_RL_Pos (0U) 3624 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ 3625 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ 3626 3627 /******************* Bit definition for IWDG_SR register ********************/ 3628 #define IWDG_SR_PVU_Pos (0U) 3629 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ 3630 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ 3631 #define IWDG_SR_RVU_Pos (1U) 3632 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ 3633 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ 3634 3635 /******************************************************************************/ 3636 /* */ 3637 /* LCD Controller (LCD) */ 3638 /* */ 3639 /******************************************************************************/ 3640 3641 /******************* Bit definition for LCD_CR register *********************/ 3642 #define LCD_CR_LCDEN_Pos (0U) 3643 #define LCD_CR_LCDEN_Msk (0x1UL << LCD_CR_LCDEN_Pos) /*!< 0x00000001 */ 3644 #define LCD_CR_LCDEN LCD_CR_LCDEN_Msk /*!< LCD Enable Bit */ 3645 #define LCD_CR_VSEL_Pos (1U) 3646 #define LCD_CR_VSEL_Msk (0x1UL << LCD_CR_VSEL_Pos) /*!< 0x00000002 */ 3647 #define LCD_CR_VSEL LCD_CR_VSEL_Msk /*!< Voltage source selector Bit */ 3648 3649 #define LCD_CR_DUTY_Pos (2U) 3650 #define LCD_CR_DUTY_Msk (0x7UL << LCD_CR_DUTY_Pos) /*!< 0x0000001C */ 3651 #define LCD_CR_DUTY LCD_CR_DUTY_Msk /*!< DUTY[2:0] bits (Duty selector) */ 3652 #define LCD_CR_DUTY_0 (0x1UL << LCD_CR_DUTY_Pos) /*!< 0x00000004 */ 3653 #define LCD_CR_DUTY_1 (0x2UL << LCD_CR_DUTY_Pos) /*!< 0x00000008 */ 3654 #define LCD_CR_DUTY_2 (0x4UL << LCD_CR_DUTY_Pos) /*!< 0x00000010 */ 3655 3656 #define LCD_CR_BIAS_Pos (5U) 3657 #define LCD_CR_BIAS_Msk (0x3UL << LCD_CR_BIAS_Pos) /*!< 0x00000060 */ 3658 #define LCD_CR_BIAS LCD_CR_BIAS_Msk /*!< BIAS[1:0] bits (Bias selector) */ 3659 #define LCD_CR_BIAS_0 (0x1UL << LCD_CR_BIAS_Pos) /*!< 0x00000020 */ 3660 #define LCD_CR_BIAS_1 (0x2UL << LCD_CR_BIAS_Pos) /*!< 0x00000040 */ 3661 3662 #define LCD_CR_MUX_SEG_Pos (7U) 3663 #define LCD_CR_MUX_SEG_Msk (0x1UL << LCD_CR_MUX_SEG_Pos) /*!< 0x00000080 */ 3664 #define LCD_CR_MUX_SEG LCD_CR_MUX_SEG_Msk /*!< Mux Segment Enable Bit */ 3665 3666 /******************* Bit definition for LCD_FCR register ********************/ 3667 #define LCD_FCR_HD_Pos (0U) 3668 #define LCD_FCR_HD_Msk (0x1UL << LCD_FCR_HD_Pos) /*!< 0x00000001 */ 3669 #define LCD_FCR_HD LCD_FCR_HD_Msk /*!< High Drive Enable Bit */ 3670 #define LCD_FCR_SOFIE_Pos (1U) 3671 #define LCD_FCR_SOFIE_Msk (0x1UL << LCD_FCR_SOFIE_Pos) /*!< 0x00000002 */ 3672 #define LCD_FCR_SOFIE LCD_FCR_SOFIE_Msk /*!< Start of Frame Interrupt Enable Bit */ 3673 #define LCD_FCR_UDDIE_Pos (3U) 3674 #define LCD_FCR_UDDIE_Msk (0x1UL << LCD_FCR_UDDIE_Pos) /*!< 0x00000008 */ 3675 #define LCD_FCR_UDDIE LCD_FCR_UDDIE_Msk /*!< Update Display Done Interrupt Enable Bit */ 3676 3677 #define LCD_FCR_PON_Pos (4U) 3678 #define LCD_FCR_PON_Msk (0x7UL << LCD_FCR_PON_Pos) /*!< 0x00000070 */ 3679 #define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */ 3680 #define LCD_FCR_PON_0 (0x1UL << LCD_FCR_PON_Pos) /*!< 0x00000010 */ 3681 #define LCD_FCR_PON_1 (0x2UL << LCD_FCR_PON_Pos) /*!< 0x00000020 */ 3682 #define LCD_FCR_PON_2 (0x4UL << LCD_FCR_PON_Pos) /*!< 0x00000040 */ 3683 3684 #define LCD_FCR_DEAD_Pos (7U) 3685 #define LCD_FCR_DEAD_Msk (0x7UL << LCD_FCR_DEAD_Pos) /*!< 0x00000380 */ 3686 #define LCD_FCR_DEAD LCD_FCR_DEAD_Msk /*!< DEAD[2:0] bits (DEAD Time) */ 3687 #define LCD_FCR_DEAD_0 (0x1UL << LCD_FCR_DEAD_Pos) /*!< 0x00000080 */ 3688 #define LCD_FCR_DEAD_1 (0x2UL << LCD_FCR_DEAD_Pos) /*!< 0x00000100 */ 3689 #define LCD_FCR_DEAD_2 (0x4UL << LCD_FCR_DEAD_Pos) /*!< 0x00000200 */ 3690 3691 #define LCD_FCR_CC_Pos (10U) 3692 #define LCD_FCR_CC_Msk (0x7UL << LCD_FCR_CC_Pos) /*!< 0x00001C00 */ 3693 #define LCD_FCR_CC LCD_FCR_CC_Msk /*!< CC[2:0] bits (Contrast Control) */ 3694 #define LCD_FCR_CC_0 (0x1UL << LCD_FCR_CC_Pos) /*!< 0x00000400 */ 3695 #define LCD_FCR_CC_1 (0x2UL << LCD_FCR_CC_Pos) /*!< 0x00000800 */ 3696 #define LCD_FCR_CC_2 (0x4UL << LCD_FCR_CC_Pos) /*!< 0x00001000 */ 3697 3698 #define LCD_FCR_BLINKF_Pos (13U) 3699 #define LCD_FCR_BLINKF_Msk (0x7UL << LCD_FCR_BLINKF_Pos) /*!< 0x0000E000 */ 3700 #define LCD_FCR_BLINKF LCD_FCR_BLINKF_Msk /*!< BLINKF[2:0] bits (Blink Frequency) */ 3701 #define LCD_FCR_BLINKF_0 (0x1UL << LCD_FCR_BLINKF_Pos) /*!< 0x00002000 */ 3702 #define LCD_FCR_BLINKF_1 (0x2UL << LCD_FCR_BLINKF_Pos) /*!< 0x00004000 */ 3703 #define LCD_FCR_BLINKF_2 (0x4UL << LCD_FCR_BLINKF_Pos) /*!< 0x00008000 */ 3704 3705 #define LCD_FCR_BLINK_Pos (16U) 3706 #define LCD_FCR_BLINK_Msk (0x3UL << LCD_FCR_BLINK_Pos) /*!< 0x00030000 */ 3707 #define LCD_FCR_BLINK LCD_FCR_BLINK_Msk /*!< BLINK[1:0] bits (Blink Enable) */ 3708 #define LCD_FCR_BLINK_0 (0x1UL << LCD_FCR_BLINK_Pos) /*!< 0x00010000 */ 3709 #define LCD_FCR_BLINK_1 (0x2UL << LCD_FCR_BLINK_Pos) /*!< 0x00020000 */ 3710 3711 #define LCD_FCR_DIV_Pos (18U) 3712 #define LCD_FCR_DIV_Msk (0xFUL << LCD_FCR_DIV_Pos) /*!< 0x003C0000 */ 3713 #define LCD_FCR_DIV LCD_FCR_DIV_Msk /*!< DIV[3:0] bits (Divider) */ 3714 #define LCD_FCR_PS_Pos (22U) 3715 #define LCD_FCR_PS_Msk (0xFUL << LCD_FCR_PS_Pos) /*!< 0x03C00000 */ 3716 #define LCD_FCR_PS LCD_FCR_PS_Msk /*!< PS[3:0] bits (Prescaler) */ 3717 3718 /******************* Bit definition for LCD_SR register *********************/ 3719 #define LCD_SR_ENS_Pos (0U) 3720 #define LCD_SR_ENS_Msk (0x1UL << LCD_SR_ENS_Pos) /*!< 0x00000001 */ 3721 #define LCD_SR_ENS LCD_SR_ENS_Msk /*!< LCD Enabled Bit */ 3722 #define LCD_SR_SOF_Pos (1U) 3723 #define LCD_SR_SOF_Msk (0x1UL << LCD_SR_SOF_Pos) /*!< 0x00000002 */ 3724 #define LCD_SR_SOF LCD_SR_SOF_Msk /*!< Start Of Frame Flag Bit */ 3725 #define LCD_SR_UDR_Pos (2U) 3726 #define LCD_SR_UDR_Msk (0x1UL << LCD_SR_UDR_Pos) /*!< 0x00000004 */ 3727 #define LCD_SR_UDR LCD_SR_UDR_Msk /*!< Update Display Request Bit */ 3728 #define LCD_SR_UDD_Pos (3U) 3729 #define LCD_SR_UDD_Msk (0x1UL << LCD_SR_UDD_Pos) /*!< 0x00000008 */ 3730 #define LCD_SR_UDD LCD_SR_UDD_Msk /*!< Update Display Done Flag Bit */ 3731 #define LCD_SR_RDY_Pos (4U) 3732 #define LCD_SR_RDY_Msk (0x1UL << LCD_SR_RDY_Pos) /*!< 0x00000010 */ 3733 #define LCD_SR_RDY LCD_SR_RDY_Msk /*!< Ready Flag Bit */ 3734 #define LCD_SR_FCRSR_Pos (5U) 3735 #define LCD_SR_FCRSR_Msk (0x1UL << LCD_SR_FCRSR_Pos) /*!< 0x00000020 */ 3736 #define LCD_SR_FCRSR LCD_SR_FCRSR_Msk /*!< LCD FCR Register Synchronization Flag Bit */ 3737 3738 /******************* Bit definition for LCD_CLR register ********************/ 3739 #define LCD_CLR_SOFC_Pos (1U) 3740 #define LCD_CLR_SOFC_Msk (0x1UL << LCD_CLR_SOFC_Pos) /*!< 0x00000002 */ 3741 #define LCD_CLR_SOFC LCD_CLR_SOFC_Msk /*!< Start Of Frame Flag Clear Bit */ 3742 #define LCD_CLR_UDDC_Pos (3U) 3743 #define LCD_CLR_UDDC_Msk (0x1UL << LCD_CLR_UDDC_Pos) /*!< 0x00000008 */ 3744 #define LCD_CLR_UDDC LCD_CLR_UDDC_Msk /*!< Update Display Done Flag Clear Bit */ 3745 3746 /******************* Bit definition for LCD_RAM register ********************/ 3747 #define LCD_RAM_SEGMENT_DATA_Pos (0U) 3748 #define LCD_RAM_SEGMENT_DATA_Msk (0xFFFFFFFFUL << LCD_RAM_SEGMENT_DATA_Pos) /*!< 0xFFFFFFFF */ 3749 #define LCD_RAM_SEGMENT_DATA LCD_RAM_SEGMENT_DATA_Msk /*!< Segment Data Bits */ 3750 3751 /******************************************************************************/ 3752 /* */ 3753 /* Power Control (PWR) */ 3754 /* */ 3755 /******************************************************************************/ 3756 3757 #define PWR_PVD_SUPPORT /*!< PWR feature available only on specific devices: Power Voltage Detection feature */ 3758 3759 /******************** Bit definition for PWR_CR register ********************/ 3760 #define PWR_CR_LPSDSR_Pos (0U) 3761 #define PWR_CR_LPSDSR_Msk (0x1UL << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */ 3762 #define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */ 3763 #define PWR_CR_PDDS_Pos (1U) 3764 #define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ 3765 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ 3766 #define PWR_CR_CWUF_Pos (2U) 3767 #define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ 3768 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ 3769 #define PWR_CR_CSBF_Pos (3U) 3770 #define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ 3771 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ 3772 #define PWR_CR_PVDE_Pos (4U) 3773 #define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ 3774 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ 3775 3776 #define PWR_CR_PLS_Pos (5U) 3777 #define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ 3778 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ 3779 #define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */ 3780 #define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */ 3781 #define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */ 3782 3783 /*!< PVD level configuration */ 3784 #define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */ 3785 #define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */ 3786 #define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */ 3787 #define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */ 3788 #define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */ 3789 #define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */ 3790 #define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */ 3791 #define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */ 3792 3793 #define PWR_CR_DBP_Pos (8U) 3794 #define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */ 3795 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ 3796 #define PWR_CR_ULP_Pos (9U) 3797 #define PWR_CR_ULP_Msk (0x1UL << PWR_CR_ULP_Pos) /*!< 0x00000200 */ 3798 #define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */ 3799 #define PWR_CR_FWU_Pos (10U) 3800 #define PWR_CR_FWU_Msk (0x1UL << PWR_CR_FWU_Pos) /*!< 0x00000400 */ 3801 #define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */ 3802 3803 #define PWR_CR_VOS_Pos (11U) 3804 #define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos) /*!< 0x00001800 */ 3805 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */ 3806 #define PWR_CR_VOS_0 (0x1UL << PWR_CR_VOS_Pos) /*!< 0x00000800 */ 3807 #define PWR_CR_VOS_1 (0x2UL << PWR_CR_VOS_Pos) /*!< 0x00001000 */ 3808 #define PWR_CR_LPRUN_Pos (14U) 3809 #define PWR_CR_LPRUN_Msk (0x1UL << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */ 3810 #define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */ 3811 3812 /******************* Bit definition for PWR_CSR register ********************/ 3813 #define PWR_CSR_WUF_Pos (0U) 3814 #define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ 3815 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ 3816 #define PWR_CSR_SBF_Pos (1U) 3817 #define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ 3818 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ 3819 #define PWR_CSR_PVDO_Pos (2U) 3820 #define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ 3821 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ 3822 #define PWR_CSR_VREFINTRDYF_Pos (3U) 3823 #define PWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */ 3824 #define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */ 3825 #define PWR_CSR_VOSF_Pos (4U) 3826 #define PWR_CSR_VOSF_Msk (0x1UL << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */ 3827 #define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */ 3828 #define PWR_CSR_REGLPF_Pos (5U) 3829 #define PWR_CSR_REGLPF_Msk (0x1UL << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */ 3830 #define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */ 3831 3832 #define PWR_CSR_EWUP1_Pos (8U) 3833 #define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */ 3834 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */ 3835 #define PWR_CSR_EWUP2_Pos (9U) 3836 #define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */ 3837 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */ 3838 #define PWR_CSR_EWUP3_Pos (10U) 3839 #define PWR_CSR_EWUP3_Msk (0x1UL << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */ 3840 #define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */ 3841 3842 /******************************************************************************/ 3843 /* */ 3844 /* Reset and Clock Control (RCC) */ 3845 /* */ 3846 /******************************************************************************/ 3847 /******************** Bit definition for RCC_CR register ********************/ 3848 #define RCC_CR_HSION_Pos (0U) 3849 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */ 3850 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ 3851 #define RCC_CR_HSIRDY_Pos (1U) 3852 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ 3853 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ 3854 3855 #define RCC_CR_MSION_Pos (8U) 3856 #define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000100 */ 3857 #define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */ 3858 #define RCC_CR_MSIRDY_Pos (9U) 3859 #define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */ 3860 #define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */ 3861 3862 #define RCC_CR_HSEON_Pos (16U) 3863 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ 3864 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ 3865 #define RCC_CR_HSERDY_Pos (17U) 3866 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ 3867 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ 3868 #define RCC_CR_HSEBYP_Pos (18U) 3869 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ 3870 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ 3871 3872 #define RCC_CR_PLLON_Pos (24U) 3873 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ 3874 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ 3875 #define RCC_CR_PLLRDY_Pos (25U) 3876 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ 3877 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ 3878 #define RCC_CR_CSSON_Pos (28U) 3879 #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x10000000 */ 3880 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */ 3881 3882 #define RCC_CR_RTCPRE_Pos (29U) 3883 #define RCC_CR_RTCPRE_Msk (0x3UL << RCC_CR_RTCPRE_Pos) /*!< 0x60000000 */ 3884 #define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC/LCD Prescaler */ 3885 #define RCC_CR_RTCPRE_0 (0x20000000U) /*!< Bit0 */ 3886 #define RCC_CR_RTCPRE_1 (0x40000000U) /*!< Bit1 */ 3887 3888 /******************** Bit definition for RCC_ICSCR register *****************/ 3889 #define RCC_ICSCR_HSICAL_Pos (0U) 3890 #define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */ 3891 #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ 3892 #define RCC_ICSCR_HSITRIM_Pos (8U) 3893 #define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */ 3894 #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ 3895 3896 #define RCC_ICSCR_MSIRANGE_Pos (13U) 3897 #define RCC_ICSCR_MSIRANGE_Msk (0x7UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */ 3898 #define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */ 3899 #define RCC_ICSCR_MSIRANGE_0 (0x0UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */ 3900 #define RCC_ICSCR_MSIRANGE_1 (0x1UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */ 3901 #define RCC_ICSCR_MSIRANGE_2 (0x2UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */ 3902 #define RCC_ICSCR_MSIRANGE_3 (0x3UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */ 3903 #define RCC_ICSCR_MSIRANGE_4 (0x4UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */ 3904 #define RCC_ICSCR_MSIRANGE_5 (0x5UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */ 3905 #define RCC_ICSCR_MSIRANGE_6 (0x6UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */ 3906 #define RCC_ICSCR_MSICAL_Pos (16U) 3907 #define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */ 3908 #define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */ 3909 #define RCC_ICSCR_MSITRIM_Pos (24U) 3910 #define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */ 3911 #define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */ 3912 3913 /******************** Bit definition for RCC_CFGR register ******************/ 3914 #define RCC_CFGR_SW_Pos (0U) 3915 #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ 3916 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ 3917 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ 3918 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ 3919 3920 /*!< SW configuration */ 3921 #define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */ 3922 #define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */ 3923 #define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */ 3924 #define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */ 3925 3926 #define RCC_CFGR_SWS_Pos (2U) 3927 #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ 3928 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ 3929 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ 3930 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ 3931 3932 /*!< SWS configuration */ 3933 #define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */ 3934 #define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */ 3935 #define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */ 3936 #define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */ 3937 3938 #define RCC_CFGR_HPRE_Pos (4U) 3939 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ 3940 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ 3941 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ 3942 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ 3943 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ 3944 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ 3945 3946 /*!< HPRE configuration */ 3947 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */ 3948 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */ 3949 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */ 3950 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */ 3951 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */ 3952 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */ 3953 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */ 3954 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */ 3955 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */ 3956 3957 #define RCC_CFGR_PPRE1_Pos (8U) 3958 #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ 3959 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ 3960 #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ 3961 #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ 3962 #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ 3963 3964 /*!< PPRE1 configuration */ 3965 #define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */ 3966 #define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */ 3967 #define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */ 3968 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */ 3969 #define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */ 3970 3971 #define RCC_CFGR_PPRE2_Pos (11U) 3972 #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ 3973 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ 3974 #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ 3975 #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ 3976 #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ 3977 3978 /*!< PPRE2 configuration */ 3979 #define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */ 3980 #define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */ 3981 #define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */ 3982 #define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */ 3983 #define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */ 3984 3985 /*!< PLL entry clock source*/ 3986 #define RCC_CFGR_PLLSRC_Pos (16U) 3987 #define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ 3988 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ 3989 3990 #define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */ 3991 #define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */ 3992 3993 3994 /*!< PLLMUL configuration */ 3995 #define RCC_CFGR_PLLMUL_Pos (18U) 3996 #define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */ 3997 #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ 3998 #define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */ 3999 #define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */ 4000 #define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */ 4001 #define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */ 4002 4003 /*!< PLLMUL configuration */ 4004 #define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */ 4005 #define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */ 4006 #define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */ 4007 #define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */ 4008 #define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */ 4009 #define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */ 4010 #define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */ 4011 #define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */ 4012 #define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */ 4013 4014 /*!< PLLDIV configuration */ 4015 #define RCC_CFGR_PLLDIV_Pos (22U) 4016 #define RCC_CFGR_PLLDIV_Msk (0x3UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */ 4017 #define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */ 4018 #define RCC_CFGR_PLLDIV_0 (0x1UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */ 4019 #define RCC_CFGR_PLLDIV_1 (0x2UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */ 4020 4021 4022 /*!< PLLDIV configuration */ 4023 #define RCC_CFGR_PLLDIV1 (0x00000000U) /*!< PLL clock output = CKVCO / 1 */ 4024 #define RCC_CFGR_PLLDIV2_Pos (22U) 4025 #define RCC_CFGR_PLLDIV2_Msk (0x1UL << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */ 4026 #define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */ 4027 #define RCC_CFGR_PLLDIV3_Pos (23U) 4028 #define RCC_CFGR_PLLDIV3_Msk (0x1UL << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */ 4029 #define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */ 4030 #define RCC_CFGR_PLLDIV4_Pos (22U) 4031 #define RCC_CFGR_PLLDIV4_Msk (0x3UL << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */ 4032 #define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */ 4033 4034 4035 #define RCC_CFGR_MCOSEL_Pos (24U) 4036 #define RCC_CFGR_MCOSEL_Msk (0x7UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x07000000 */ 4037 #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */ 4038 #define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */ 4039 #define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */ 4040 #define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */ 4041 4042 /*!< MCO configuration */ 4043 #define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */ 4044 #define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U) 4045 #define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */ 4046 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected */ 4047 #define RCC_CFGR_MCOSEL_HSI_Pos (25U) 4048 #define RCC_CFGR_MCOSEL_HSI_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */ 4049 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */ 4050 #define RCC_CFGR_MCOSEL_MSI_Pos (24U) 4051 #define RCC_CFGR_MCOSEL_MSI_Msk (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */ 4052 #define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */ 4053 #define RCC_CFGR_MCOSEL_HSE_Pos (26U) 4054 #define RCC_CFGR_MCOSEL_HSE_Msk (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */ 4055 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */ 4056 #define RCC_CFGR_MCOSEL_PLL_Pos (24U) 4057 #define RCC_CFGR_MCOSEL_PLL_Msk (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */ 4058 #define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */ 4059 #define RCC_CFGR_MCOSEL_LSI_Pos (25U) 4060 #define RCC_CFGR_MCOSEL_LSI_Msk (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */ 4061 #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */ 4062 #define RCC_CFGR_MCOSEL_LSE_Pos (24U) 4063 #define RCC_CFGR_MCOSEL_LSE_Msk (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */ 4064 #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */ 4065 4066 #define RCC_CFGR_MCOPRE_Pos (28U) 4067 #define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */ 4068 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */ 4069 #define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */ 4070 #define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */ 4071 #define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */ 4072 4073 /*!< MCO Prescaler configuration */ 4074 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */ 4075 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */ 4076 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */ 4077 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */ 4078 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */ 4079 4080 /* Legacy aliases */ 4081 #define RCC_CFGR_MCO_DIV1 RCC_CFGR_MCOPRE_DIV1 4082 #define RCC_CFGR_MCO_DIV2 RCC_CFGR_MCOPRE_DIV2 4083 #define RCC_CFGR_MCO_DIV4 RCC_CFGR_MCOPRE_DIV4 4084 #define RCC_CFGR_MCO_DIV8 RCC_CFGR_MCOPRE_DIV8 4085 #define RCC_CFGR_MCO_DIV16 RCC_CFGR_MCOPRE_DIV16 4086 #define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK 4087 #define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK 4088 #define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI 4089 #define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI 4090 #define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE 4091 #define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL 4092 #define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI 4093 #define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE 4094 4095 /*!<****************** Bit definition for RCC_CIR register ********************/ 4096 #define RCC_CIR_LSIRDYF_Pos (0U) 4097 #define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ 4098 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ 4099 #define RCC_CIR_LSERDYF_Pos (1U) 4100 #define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ 4101 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ 4102 #define RCC_CIR_HSIRDYF_Pos (2U) 4103 #define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ 4104 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ 4105 #define RCC_CIR_HSERDYF_Pos (3U) 4106 #define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ 4107 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ 4108 #define RCC_CIR_PLLRDYF_Pos (4U) 4109 #define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ 4110 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ 4111 #define RCC_CIR_MSIRDYF_Pos (5U) 4112 #define RCC_CIR_MSIRDYF_Msk (0x1UL << RCC_CIR_MSIRDYF_Pos) /*!< 0x00000020 */ 4113 #define RCC_CIR_MSIRDYF RCC_CIR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */ 4114 #define RCC_CIR_CSSF_Pos (7U) 4115 #define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ 4116 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ 4117 4118 #define RCC_CIR_LSIRDYIE_Pos (8U) 4119 #define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ 4120 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ 4121 #define RCC_CIR_LSERDYIE_Pos (9U) 4122 #define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ 4123 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ 4124 #define RCC_CIR_HSIRDYIE_Pos (10U) 4125 #define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ 4126 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ 4127 #define RCC_CIR_HSERDYIE_Pos (11U) 4128 #define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ 4129 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ 4130 #define RCC_CIR_PLLRDYIE_Pos (12U) 4131 #define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ 4132 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ 4133 #define RCC_CIR_MSIRDYIE_Pos (13U) 4134 #define RCC_CIR_MSIRDYIE_Msk (0x1UL << RCC_CIR_MSIRDYIE_Pos) /*!< 0x00002000 */ 4135 #define RCC_CIR_MSIRDYIE RCC_CIR_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */ 4136 4137 #define RCC_CIR_LSIRDYC_Pos (16U) 4138 #define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ 4139 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ 4140 #define RCC_CIR_LSERDYC_Pos (17U) 4141 #define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ 4142 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ 4143 #define RCC_CIR_HSIRDYC_Pos (18U) 4144 #define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ 4145 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ 4146 #define RCC_CIR_HSERDYC_Pos (19U) 4147 #define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ 4148 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ 4149 #define RCC_CIR_PLLRDYC_Pos (20U) 4150 #define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ 4151 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ 4152 #define RCC_CIR_MSIRDYC_Pos (21U) 4153 #define RCC_CIR_MSIRDYC_Msk (0x1UL << RCC_CIR_MSIRDYC_Pos) /*!< 0x00200000 */ 4154 #define RCC_CIR_MSIRDYC RCC_CIR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */ 4155 #define RCC_CIR_CSSC_Pos (23U) 4156 #define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ 4157 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ 4158 4159 /***************** Bit definition for RCC_AHBRSTR register ******************/ 4160 #define RCC_AHBRSTR_GPIOARST_Pos (0U) 4161 #define RCC_AHBRSTR_GPIOARST_Msk (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */ 4162 #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIO port A reset */ 4163 #define RCC_AHBRSTR_GPIOBRST_Pos (1U) 4164 #define RCC_AHBRSTR_GPIOBRST_Msk (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */ 4165 #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIO port B reset */ 4166 #define RCC_AHBRSTR_GPIOCRST_Pos (2U) 4167 #define RCC_AHBRSTR_GPIOCRST_Msk (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */ 4168 #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIO port C reset */ 4169 #define RCC_AHBRSTR_GPIODRST_Pos (3U) 4170 #define RCC_AHBRSTR_GPIODRST_Msk (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */ 4171 #define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIO port D reset */ 4172 #define RCC_AHBRSTR_GPIOERST_Pos (4U) 4173 #define RCC_AHBRSTR_GPIOERST_Msk (0x1UL << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00000010 */ 4174 #define RCC_AHBRSTR_GPIOERST RCC_AHBRSTR_GPIOERST_Msk /*!< GPIO port E reset */ 4175 #define RCC_AHBRSTR_GPIOHRST_Pos (5U) 4176 #define RCC_AHBRSTR_GPIOHRST_Msk (0x1UL << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */ 4177 #define RCC_AHBRSTR_GPIOHRST RCC_AHBRSTR_GPIOHRST_Msk /*!< GPIO port H reset */ 4178 #define RCC_AHBRSTR_CRCRST_Pos (12U) 4179 #define RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */ 4180 #define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */ 4181 #define RCC_AHBRSTR_FLITFRST_Pos (15U) 4182 #define RCC_AHBRSTR_FLITFRST_Msk (0x1UL << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */ 4183 #define RCC_AHBRSTR_FLITFRST RCC_AHBRSTR_FLITFRST_Msk /*!< FLITF reset */ 4184 #define RCC_AHBRSTR_DMA1RST_Pos (24U) 4185 #define RCC_AHBRSTR_DMA1RST_Msk (0x1UL << RCC_AHBRSTR_DMA1RST_Pos) /*!< 0x01000000 */ 4186 #define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMA1RST_Msk /*!< DMA1 reset */ 4187 4188 /***************** Bit definition for RCC_APB2RSTR register *****************/ 4189 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) 4190 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ 4191 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< System Configuration SYSCFG reset */ 4192 #define RCC_APB2RSTR_TIM9RST_Pos (2U) 4193 #define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */ 4194 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk /*!< TIM9 reset */ 4195 #define RCC_APB2RSTR_TIM10RST_Pos (3U) 4196 #define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */ 4197 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk /*!< TIM10 reset */ 4198 #define RCC_APB2RSTR_TIM11RST_Pos (4U) 4199 #define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */ 4200 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk /*!< TIM11 reset */ 4201 #define RCC_APB2RSTR_ADC1RST_Pos (9U) 4202 #define RCC_APB2RSTR_ADC1RST_Msk (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */ 4203 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC1 reset */ 4204 #define RCC_APB2RSTR_SPI1RST_Pos (12U) 4205 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ 4206 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ 4207 #define RCC_APB2RSTR_USART1RST_Pos (14U) 4208 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ 4209 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ 4210 4211 /***************** Bit definition for RCC_APB1RSTR register *****************/ 4212 #define RCC_APB1RSTR_TIM2RST_Pos (0U) 4213 #define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ 4214 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ 4215 #define RCC_APB1RSTR_TIM3RST_Pos (1U) 4216 #define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ 4217 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ 4218 #define RCC_APB1RSTR_TIM4RST_Pos (2U) 4219 #define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */ 4220 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */ 4221 #define RCC_APB1RSTR_TIM6RST_Pos (4U) 4222 #define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ 4223 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */ 4224 #define RCC_APB1RSTR_TIM7RST_Pos (5U) 4225 #define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ 4226 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */ 4227 #define RCC_APB1RSTR_LCDRST_Pos (9U) 4228 #define RCC_APB1RSTR_LCDRST_Msk (0x1UL << RCC_APB1RSTR_LCDRST_Pos) /*!< 0x00000200 */ 4229 #define RCC_APB1RSTR_LCDRST RCC_APB1RSTR_LCDRST_Msk /*!< LCD reset */ 4230 #define RCC_APB1RSTR_WWDGRST_Pos (11U) 4231 #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ 4232 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ 4233 #define RCC_APB1RSTR_SPI2RST_Pos (14U) 4234 #define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ 4235 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */ 4236 #define RCC_APB1RSTR_USART2RST_Pos (17U) 4237 #define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ 4238 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ 4239 #define RCC_APB1RSTR_USART3RST_Pos (18U) 4240 #define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ 4241 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ 4242 #define RCC_APB1RSTR_I2C1RST_Pos (21U) 4243 #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ 4244 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ 4245 #define RCC_APB1RSTR_I2C2RST_Pos (22U) 4246 #define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ 4247 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ 4248 #define RCC_APB1RSTR_USBRST_Pos (23U) 4249 #define RCC_APB1RSTR_USBRST_Msk (0x1UL << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ 4250 #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB reset */ 4251 #define RCC_APB1RSTR_PWRRST_Pos (28U) 4252 #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ 4253 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */ 4254 #define RCC_APB1RSTR_DACRST_Pos (29U) 4255 #define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */ 4256 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC interface reset */ 4257 #define RCC_APB1RSTR_COMPRST_Pos (31U) 4258 #define RCC_APB1RSTR_COMPRST_Msk (0x1UL << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */ 4259 #define RCC_APB1RSTR_COMPRST RCC_APB1RSTR_COMPRST_Msk /*!< Comparator interface reset */ 4260 4261 /****************** Bit definition for RCC_AHBENR register ******************/ 4262 #define RCC_AHBENR_GPIOAEN_Pos (0U) 4263 #define RCC_AHBENR_GPIOAEN_Msk (0x1UL << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00000001 */ 4264 #define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk /*!< GPIO port A clock enable */ 4265 #define RCC_AHBENR_GPIOBEN_Pos (1U) 4266 #define RCC_AHBENR_GPIOBEN_Msk (0x1UL << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00000002 */ 4267 #define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk /*!< GPIO port B clock enable */ 4268 #define RCC_AHBENR_GPIOCEN_Pos (2U) 4269 #define RCC_AHBENR_GPIOCEN_Msk (0x1UL << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00000004 */ 4270 #define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk /*!< GPIO port C clock enable */ 4271 #define RCC_AHBENR_GPIODEN_Pos (3U) 4272 #define RCC_AHBENR_GPIODEN_Msk (0x1UL << RCC_AHBENR_GPIODEN_Pos) /*!< 0x00000008 */ 4273 #define RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk /*!< GPIO port D clock enable */ 4274 #define RCC_AHBENR_GPIOEEN_Pos (4U) 4275 #define RCC_AHBENR_GPIOEEN_Msk (0x1UL << RCC_AHBENR_GPIOEEN_Pos) /*!< 0x00000010 */ 4276 #define RCC_AHBENR_GPIOEEN RCC_AHBENR_GPIOEEN_Msk /*!< GPIO port E clock enable */ 4277 #define RCC_AHBENR_GPIOHEN_Pos (5U) 4278 #define RCC_AHBENR_GPIOHEN_Msk (0x1UL << RCC_AHBENR_GPIOHEN_Pos) /*!< 0x00000020 */ 4279 #define RCC_AHBENR_GPIOHEN RCC_AHBENR_GPIOHEN_Msk /*!< GPIO port H clock enable */ 4280 #define RCC_AHBENR_CRCEN_Pos (12U) 4281 #define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */ 4282 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ 4283 #define RCC_AHBENR_FLITFEN_Pos (15U) 4284 #define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00008000 */ 4285 #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable (has effect only when 4286 the Flash memory is in power down mode) */ 4287 #define RCC_AHBENR_DMA1EN_Pos (24U) 4288 #define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos) /*!< 0x01000000 */ 4289 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */ 4290 4291 /****************** Bit definition for RCC_APB2ENR register *****************/ 4292 #define RCC_APB2ENR_SYSCFGEN_Pos (0U) 4293 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */ 4294 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< System Configuration SYSCFG clock enable */ 4295 #define RCC_APB2ENR_TIM9EN_Pos (2U) 4296 #define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00000004 */ 4297 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk /*!< TIM9 interface clock enable */ 4298 #define RCC_APB2ENR_TIM10EN_Pos (3U) 4299 #define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00000008 */ 4300 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk /*!< TIM10 interface clock enable */ 4301 #define RCC_APB2ENR_TIM11EN_Pos (4U) 4302 #define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00000010 */ 4303 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk /*!< TIM11 Timer clock enable */ 4304 #define RCC_APB2ENR_ADC1EN_Pos (9U) 4305 #define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */ 4306 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC1 clock enable */ 4307 #define RCC_APB2ENR_SPI1EN_Pos (12U) 4308 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ 4309 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */ 4310 #define RCC_APB2ENR_USART1EN_Pos (14U) 4311 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ 4312 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ 4313 4314 /***************** Bit definition for RCC_APB1ENR register ******************/ 4315 #define RCC_APB1ENR_TIM2EN_Pos (0U) 4316 #define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ 4317 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/ 4318 #define RCC_APB1ENR_TIM3EN_Pos (1U) 4319 #define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ 4320 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ 4321 #define RCC_APB1ENR_TIM4EN_Pos (2U) 4322 #define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */ 4323 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */ 4324 #define RCC_APB1ENR_TIM6EN_Pos (4U) 4325 #define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */ 4326 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */ 4327 #define RCC_APB1ENR_TIM7EN_Pos (5U) 4328 #define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */ 4329 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */ 4330 #define RCC_APB1ENR_LCDEN_Pos (9U) 4331 #define RCC_APB1ENR_LCDEN_Msk (0x1UL << RCC_APB1ENR_LCDEN_Pos) /*!< 0x00000200 */ 4332 #define RCC_APB1ENR_LCDEN RCC_APB1ENR_LCDEN_Msk /*!< LCD clock enable */ 4333 #define RCC_APB1ENR_WWDGEN_Pos (11U) 4334 #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ 4335 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ 4336 #define RCC_APB1ENR_SPI2EN_Pos (14U) 4337 #define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ 4338 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */ 4339 #define RCC_APB1ENR_USART2EN_Pos (17U) 4340 #define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ 4341 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */ 4342 #define RCC_APB1ENR_USART3EN_Pos (18U) 4343 #define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */ 4344 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */ 4345 #define RCC_APB1ENR_I2C1EN_Pos (21U) 4346 #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ 4347 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */ 4348 #define RCC_APB1ENR_I2C2EN_Pos (22U) 4349 #define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ 4350 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */ 4351 #define RCC_APB1ENR_USBEN_Pos (23U) 4352 #define RCC_APB1ENR_USBEN_Msk (0x1UL << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */ 4353 #define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB clock enable */ 4354 #define RCC_APB1ENR_PWREN_Pos (28U) 4355 #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ 4356 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */ 4357 #define RCC_APB1ENR_DACEN_Pos (29U) 4358 #define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */ 4359 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC interface clock enable */ 4360 #define RCC_APB1ENR_COMPEN_Pos (31U) 4361 #define RCC_APB1ENR_COMPEN_Msk (0x1UL << RCC_APB1ENR_COMPEN_Pos) /*!< 0x80000000 */ 4362 #define RCC_APB1ENR_COMPEN RCC_APB1ENR_COMPEN_Msk /*!< Comparator interface clock enable */ 4363 4364 /****************** Bit definition for RCC_AHBLPENR register ****************/ 4365 #define RCC_AHBLPENR_GPIOALPEN_Pos (0U) 4366 #define RCC_AHBLPENR_GPIOALPEN_Msk (0x1UL << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */ 4367 #define RCC_AHBLPENR_GPIOALPEN RCC_AHBLPENR_GPIOALPEN_Msk /*!< GPIO port A clock enabled in sleep mode */ 4368 #define RCC_AHBLPENR_GPIOBLPEN_Pos (1U) 4369 #define RCC_AHBLPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */ 4370 #define RCC_AHBLPENR_GPIOBLPEN RCC_AHBLPENR_GPIOBLPEN_Msk /*!< GPIO port B clock enabled in sleep mode */ 4371 #define RCC_AHBLPENR_GPIOCLPEN_Pos (2U) 4372 #define RCC_AHBLPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */ 4373 #define RCC_AHBLPENR_GPIOCLPEN RCC_AHBLPENR_GPIOCLPEN_Msk /*!< GPIO port C clock enabled in sleep mode */ 4374 #define RCC_AHBLPENR_GPIODLPEN_Pos (3U) 4375 #define RCC_AHBLPENR_GPIODLPEN_Msk (0x1UL << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */ 4376 #define RCC_AHBLPENR_GPIODLPEN RCC_AHBLPENR_GPIODLPEN_Msk /*!< GPIO port D clock enabled in sleep mode */ 4377 #define RCC_AHBLPENR_GPIOELPEN_Pos (4U) 4378 #define RCC_AHBLPENR_GPIOELPEN_Msk (0x1UL << RCC_AHBLPENR_GPIOELPEN_Pos) /*!< 0x00000010 */ 4379 #define RCC_AHBLPENR_GPIOELPEN RCC_AHBLPENR_GPIOELPEN_Msk /*!< GPIO port E clock enabled in sleep mode */ 4380 #define RCC_AHBLPENR_GPIOHLPEN_Pos (5U) 4381 #define RCC_AHBLPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */ 4382 #define RCC_AHBLPENR_GPIOHLPEN RCC_AHBLPENR_GPIOHLPEN_Msk /*!< GPIO port H clock enabled in sleep mode */ 4383 #define RCC_AHBLPENR_CRCLPEN_Pos (12U) 4384 #define RCC_AHBLPENR_CRCLPEN_Msk (0x1UL << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */ 4385 #define RCC_AHBLPENR_CRCLPEN RCC_AHBLPENR_CRCLPEN_Msk /*!< CRC clock enabled in sleep mode */ 4386 #define RCC_AHBLPENR_FLITFLPEN_Pos (15U) 4387 #define RCC_AHBLPENR_FLITFLPEN_Msk (0x1UL << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */ 4388 #define RCC_AHBLPENR_FLITFLPEN RCC_AHBLPENR_FLITFLPEN_Msk /*!< Flash Interface clock enabled in sleep mode 4389 (has effect only when the Flash memory is 4390 in power down mode) */ 4391 #define RCC_AHBLPENR_SRAMLPEN_Pos (16U) 4392 #define RCC_AHBLPENR_SRAMLPEN_Msk (0x1UL << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */ 4393 #define RCC_AHBLPENR_SRAMLPEN RCC_AHBLPENR_SRAMLPEN_Msk /*!< SRAM clock enabled in sleep mode */ 4394 #define RCC_AHBLPENR_DMA1LPEN_Pos (24U) 4395 #define RCC_AHBLPENR_DMA1LPEN_Msk (0x1UL << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */ 4396 #define RCC_AHBLPENR_DMA1LPEN RCC_AHBLPENR_DMA1LPEN_Msk /*!< DMA1 clock enabled in sleep mode */ 4397 4398 /****************** Bit definition for RCC_APB2LPENR register ***************/ 4399 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (0U) 4400 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */ 4401 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk /*!< System Configuration SYSCFG clock enabled in sleep mode */ 4402 #define RCC_APB2LPENR_TIM9LPEN_Pos (2U) 4403 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */ 4404 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk /*!< TIM9 interface clock enabled in sleep mode */ 4405 #define RCC_APB2LPENR_TIM10LPEN_Pos (3U) 4406 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */ 4407 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk /*!< TIM10 interface clock enabled in sleep mode */ 4408 #define RCC_APB2LPENR_TIM11LPEN_Pos (4U) 4409 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */ 4410 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk /*!< TIM11 Timer clock enabled in sleep mode */ 4411 #define RCC_APB2LPENR_ADC1LPEN_Pos (9U) 4412 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */ 4413 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk /*!< ADC1 clock enabled in sleep mode */ 4414 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U) 4415 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */ 4416 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk /*!< SPI1 clock enabled in sleep mode */ 4417 #define RCC_APB2LPENR_USART1LPEN_Pos (14U) 4418 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */ 4419 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk /*!< USART1 clock enabled in sleep mode */ 4420 4421 /***************** Bit definition for RCC_APB1LPENR register ****************/ 4422 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U) 4423 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */ 4424 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk /*!< Timer 2 clock enabled in sleep mode */ 4425 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U) 4426 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */ 4427 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk /*!< Timer 3 clock enabled in sleep mode */ 4428 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U) 4429 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */ 4430 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk /*!< Timer 4 clock enabled in sleep mode */ 4431 #define RCC_APB1LPENR_TIM6LPEN_Pos (4U) 4432 #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */ 4433 #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk /*!< Timer 6 clock enabled in sleep mode */ 4434 #define RCC_APB1LPENR_TIM7LPEN_Pos (5U) 4435 #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */ 4436 #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk /*!< Timer 7 clock enabled in sleep mode */ 4437 #define RCC_APB1LPENR_LCDLPEN_Pos (9U) 4438 #define RCC_APB1LPENR_LCDLPEN_Msk (0x1UL << RCC_APB1LPENR_LCDLPEN_Pos) /*!< 0x00000200 */ 4439 #define RCC_APB1LPENR_LCDLPEN RCC_APB1LPENR_LCDLPEN_Msk /*!< LCD clock enabled in sleep mode */ 4440 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U) 4441 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */ 4442 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk /*!< Window Watchdog clock enabled in sleep mode */ 4443 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U) 4444 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */ 4445 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk /*!< SPI 2 clock enabled in sleep mode */ 4446 #define RCC_APB1LPENR_USART2LPEN_Pos (17U) 4447 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */ 4448 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk /*!< USART 2 clock enabled in sleep mode */ 4449 #define RCC_APB1LPENR_USART3LPEN_Pos (18U) 4450 #define RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */ 4451 #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk /*!< USART 3 clock enabled in sleep mode */ 4452 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U) 4453 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */ 4454 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk /*!< I2C 1 clock enabled in sleep mode */ 4455 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U) 4456 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */ 4457 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk /*!< I2C 2 clock enabled in sleep mode */ 4458 #define RCC_APB1LPENR_USBLPEN_Pos (23U) 4459 #define RCC_APB1LPENR_USBLPEN_Msk (0x1UL << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */ 4460 #define RCC_APB1LPENR_USBLPEN RCC_APB1LPENR_USBLPEN_Msk /*!< USB clock enabled in sleep mode */ 4461 #define RCC_APB1LPENR_PWRLPEN_Pos (28U) 4462 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */ 4463 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk /*!< Power interface clock enabled in sleep mode */ 4464 #define RCC_APB1LPENR_DACLPEN_Pos (29U) 4465 #define RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */ 4466 #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk /*!< DAC interface clock enabled in sleep mode */ 4467 #define RCC_APB1LPENR_COMPLPEN_Pos (31U) 4468 #define RCC_APB1LPENR_COMPLPEN_Msk (0x1UL << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */ 4469 #define RCC_APB1LPENR_COMPLPEN RCC_APB1LPENR_COMPLPEN_Msk /*!< Comparator interface clock enabled in sleep mode*/ 4470 4471 /******************* Bit definition for RCC_CSR register ********************/ 4472 #define RCC_CSR_LSION_Pos (0U) 4473 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ 4474 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ 4475 #define RCC_CSR_LSIRDY_Pos (1U) 4476 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ 4477 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ 4478 4479 #define RCC_CSR_LSEON_Pos (8U) 4480 #define RCC_CSR_LSEON_Msk (0x1UL << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */ 4481 #define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */ 4482 #define RCC_CSR_LSERDY_Pos (9U) 4483 #define RCC_CSR_LSERDY_Msk (0x1UL << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */ 4484 #define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ 4485 #define RCC_CSR_LSEBYP_Pos (10U) 4486 #define RCC_CSR_LSEBYP_Msk (0x1UL << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */ 4487 #define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ 4488 4489 #define RCC_CSR_RTCSEL_Pos (16U) 4490 #define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ 4491 #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ 4492 #define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */ 4493 #define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */ 4494 4495 /*!< RTC congiguration */ 4496 #define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */ 4497 #define RCC_CSR_RTCSEL_LSE_Pos (16U) 4498 #define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */ 4499 #define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */ 4500 #define RCC_CSR_RTCSEL_LSI_Pos (17U) 4501 #define RCC_CSR_RTCSEL_LSI_Msk (0x1UL << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */ 4502 #define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */ 4503 #define RCC_CSR_RTCSEL_HSE_Pos (16U) 4504 #define RCC_CSR_RTCSEL_HSE_Msk (0x3UL << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */ 4505 #define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */ 4506 4507 #define RCC_CSR_RTCEN_Pos (22U) 4508 #define RCC_CSR_RTCEN_Msk (0x1UL << RCC_CSR_RTCEN_Pos) /*!< 0x00400000 */ 4509 #define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */ 4510 #define RCC_CSR_RTCRST_Pos (23U) 4511 #define RCC_CSR_RTCRST_Msk (0x1UL << RCC_CSR_RTCRST_Pos) /*!< 0x00800000 */ 4512 #define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC reset */ 4513 4514 #define RCC_CSR_RMVF_Pos (24U) 4515 #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ 4516 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ 4517 #define RCC_CSR_OBLRSTF_Pos (25U) 4518 #define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ 4519 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< Option Bytes Loader reset flag */ 4520 #define RCC_CSR_PINRSTF_Pos (26U) 4521 #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ 4522 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ 4523 #define RCC_CSR_PORRSTF_Pos (27U) 4524 #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ 4525 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ 4526 #define RCC_CSR_SFTRSTF_Pos (28U) 4527 #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ 4528 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ 4529 #define RCC_CSR_IWDGRSTF_Pos (29U) 4530 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ 4531 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ 4532 #define RCC_CSR_WWDGRSTF_Pos (30U) 4533 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ 4534 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ 4535 #define RCC_CSR_LPWRRSTF_Pos (31U) 4536 #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ 4537 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ 4538 4539 /******************************************************************************/ 4540 /* */ 4541 /* Real-Time Clock (RTC) */ 4542 /* */ 4543 /******************************************************************************/ 4544 /* 4545 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) 4546 */ 4547 #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */ 4548 #define RTC_BACKUP_SUPPORT /*!< BACKUP register feature support */ 4549 #define RTC_WAKEUP_SUPPORT /*!< WAKEUP feature support */ 4550 4551 /******************** Bits definition for RTC_TR register *******************/ 4552 #define RTC_TR_PM_Pos (22U) 4553 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ 4554 #define RTC_TR_PM RTC_TR_PM_Msk 4555 #define RTC_TR_HT_Pos (20U) 4556 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ 4557 #define RTC_TR_HT RTC_TR_HT_Msk 4558 #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ 4559 #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ 4560 #define RTC_TR_HU_Pos (16U) 4561 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ 4562 #define RTC_TR_HU RTC_TR_HU_Msk 4563 #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ 4564 #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ 4565 #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ 4566 #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ 4567 #define RTC_TR_MNT_Pos (12U) 4568 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ 4569 #define RTC_TR_MNT RTC_TR_MNT_Msk 4570 #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ 4571 #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ 4572 #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ 4573 #define RTC_TR_MNU_Pos (8U) 4574 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ 4575 #define RTC_TR_MNU RTC_TR_MNU_Msk 4576 #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ 4577 #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ 4578 #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ 4579 #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ 4580 #define RTC_TR_ST_Pos (4U) 4581 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ 4582 #define RTC_TR_ST RTC_TR_ST_Msk 4583 #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ 4584 #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ 4585 #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ 4586 #define RTC_TR_SU_Pos (0U) 4587 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ 4588 #define RTC_TR_SU RTC_TR_SU_Msk 4589 #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ 4590 #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ 4591 #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ 4592 #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ 4593 4594 /******************** Bits definition for RTC_DR register *******************/ 4595 #define RTC_DR_YT_Pos (20U) 4596 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ 4597 #define RTC_DR_YT RTC_DR_YT_Msk 4598 #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ 4599 #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ 4600 #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ 4601 #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ 4602 #define RTC_DR_YU_Pos (16U) 4603 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ 4604 #define RTC_DR_YU RTC_DR_YU_Msk 4605 #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ 4606 #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ 4607 #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ 4608 #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ 4609 #define RTC_DR_WDU_Pos (13U) 4610 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ 4611 #define RTC_DR_WDU RTC_DR_WDU_Msk 4612 #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ 4613 #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ 4614 #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ 4615 #define RTC_DR_MT_Pos (12U) 4616 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ 4617 #define RTC_DR_MT RTC_DR_MT_Msk 4618 #define RTC_DR_MU_Pos (8U) 4619 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ 4620 #define RTC_DR_MU RTC_DR_MU_Msk 4621 #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ 4622 #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ 4623 #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ 4624 #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ 4625 #define RTC_DR_DT_Pos (4U) 4626 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ 4627 #define RTC_DR_DT RTC_DR_DT_Msk 4628 #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ 4629 #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ 4630 #define RTC_DR_DU_Pos (0U) 4631 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ 4632 #define RTC_DR_DU RTC_DR_DU_Msk 4633 #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ 4634 #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ 4635 #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ 4636 #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ 4637 4638 /******************** Bits definition for RTC_CR register *******************/ 4639 #define RTC_CR_COE_Pos (23U) 4640 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ 4641 #define RTC_CR_COE RTC_CR_COE_Msk 4642 #define RTC_CR_OSEL_Pos (21U) 4643 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ 4644 #define RTC_CR_OSEL RTC_CR_OSEL_Msk 4645 #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ 4646 #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ 4647 #define RTC_CR_POL_Pos (20U) 4648 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ 4649 #define RTC_CR_POL RTC_CR_POL_Msk 4650 #define RTC_CR_BKP_Pos (18U) 4651 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ 4652 #define RTC_CR_BKP RTC_CR_BKP_Msk 4653 #define RTC_CR_SUB1H_Pos (17U) 4654 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ 4655 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk 4656 #define RTC_CR_ADD1H_Pos (16U) 4657 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ 4658 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk 4659 #define RTC_CR_TSIE_Pos (15U) 4660 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ 4661 #define RTC_CR_TSIE RTC_CR_TSIE_Msk 4662 #define RTC_CR_WUTIE_Pos (14U) 4663 #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ 4664 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk 4665 #define RTC_CR_ALRBIE_Pos (13U) 4666 #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ 4667 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk 4668 #define RTC_CR_ALRAIE_Pos (12U) 4669 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ 4670 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk 4671 #define RTC_CR_TSE_Pos (11U) 4672 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ 4673 #define RTC_CR_TSE RTC_CR_TSE_Msk 4674 #define RTC_CR_WUTE_Pos (10U) 4675 #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ 4676 #define RTC_CR_WUTE RTC_CR_WUTE_Msk 4677 #define RTC_CR_ALRBE_Pos (9U) 4678 #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ 4679 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk 4680 #define RTC_CR_ALRAE_Pos (8U) 4681 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ 4682 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk 4683 #define RTC_CR_DCE_Pos (7U) 4684 #define RTC_CR_DCE_Msk (0x1UL << RTC_CR_DCE_Pos) /*!< 0x00000080 */ 4685 #define RTC_CR_DCE RTC_CR_DCE_Msk 4686 #define RTC_CR_FMT_Pos (6U) 4687 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ 4688 #define RTC_CR_FMT RTC_CR_FMT_Msk 4689 #define RTC_CR_REFCKON_Pos (4U) 4690 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ 4691 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk 4692 #define RTC_CR_TSEDGE_Pos (3U) 4693 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ 4694 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk 4695 #define RTC_CR_WUCKSEL_Pos (0U) 4696 #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ 4697 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk 4698 #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ 4699 #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ 4700 #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ 4701 4702 /* Legacy defines */ 4703 #define RTC_CR_BCK_Pos RTC_CR_BKP_Pos 4704 #define RTC_CR_BCK_Msk RTC_CR_BKP_Msk 4705 #define RTC_CR_BCK RTC_CR_BKP 4706 4707 /******************** Bits definition for RTC_ISR register ******************/ 4708 #define RTC_ISR_TAMP1F_Pos (13U) 4709 #define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */ 4710 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk 4711 #define RTC_ISR_TSOVF_Pos (12U) 4712 #define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */ 4713 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk 4714 #define RTC_ISR_TSF_Pos (11U) 4715 #define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */ 4716 #define RTC_ISR_TSF RTC_ISR_TSF_Msk 4717 #define RTC_ISR_WUTF_Pos (10U) 4718 #define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */ 4719 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk 4720 #define RTC_ISR_ALRBF_Pos (9U) 4721 #define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */ 4722 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk 4723 #define RTC_ISR_ALRAF_Pos (8U) 4724 #define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */ 4725 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk 4726 #define RTC_ISR_INIT_Pos (7U) 4727 #define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ 4728 #define RTC_ISR_INIT RTC_ISR_INIT_Msk 4729 #define RTC_ISR_INITF_Pos (6U) 4730 #define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ 4731 #define RTC_ISR_INITF RTC_ISR_INITF_Msk 4732 #define RTC_ISR_RSF_Pos (5U) 4733 #define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ 4734 #define RTC_ISR_RSF RTC_ISR_RSF_Msk 4735 #define RTC_ISR_INITS_Pos (4U) 4736 #define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ 4737 #define RTC_ISR_INITS RTC_ISR_INITS_Msk 4738 #define RTC_ISR_WUTWF_Pos (2U) 4739 #define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ 4740 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk 4741 #define RTC_ISR_ALRBWF_Pos (1U) 4742 #define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ 4743 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk 4744 #define RTC_ISR_ALRAWF_Pos (0U) 4745 #define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ 4746 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk 4747 4748 /******************** Bits definition for RTC_PRER register *****************/ 4749 #define RTC_PRER_PREDIV_A_Pos (16U) 4750 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ 4751 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk 4752 #define RTC_PRER_PREDIV_S_Pos (0U) 4753 #define RTC_PRER_PREDIV_S_Msk (0x1FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00001FFF */ 4754 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk 4755 4756 /******************** Bits definition for RTC_WUTR register *****************/ 4757 #define RTC_WUTR_WUT_Pos (0U) 4758 #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ 4759 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk 4760 4761 /******************** Bits definition for RTC_CALIBR register ***************/ 4762 #define RTC_CALIBR_DCS_Pos (7U) 4763 #define RTC_CALIBR_DCS_Msk (0x1UL << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */ 4764 #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk 4765 #define RTC_CALIBR_DC_Pos (0U) 4766 #define RTC_CALIBR_DC_Msk (0x1FUL << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */ 4767 #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk 4768 4769 /******************** Bits definition for RTC_ALRMAR register ***************/ 4770 #define RTC_ALRMAR_MSK4_Pos (31U) 4771 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ 4772 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk 4773 #define RTC_ALRMAR_WDSEL_Pos (30U) 4774 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ 4775 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk 4776 #define RTC_ALRMAR_DT_Pos (28U) 4777 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ 4778 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk 4779 #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ 4780 #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ 4781 #define RTC_ALRMAR_DU_Pos (24U) 4782 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ 4783 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk 4784 #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ 4785 #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ 4786 #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ 4787 #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ 4788 #define RTC_ALRMAR_MSK3_Pos (23U) 4789 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ 4790 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk 4791 #define RTC_ALRMAR_PM_Pos (22U) 4792 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ 4793 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk 4794 #define RTC_ALRMAR_HT_Pos (20U) 4795 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ 4796 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk 4797 #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ 4798 #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ 4799 #define RTC_ALRMAR_HU_Pos (16U) 4800 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ 4801 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk 4802 #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ 4803 #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ 4804 #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ 4805 #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ 4806 #define RTC_ALRMAR_MSK2_Pos (15U) 4807 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ 4808 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk 4809 #define RTC_ALRMAR_MNT_Pos (12U) 4810 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ 4811 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk 4812 #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ 4813 #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ 4814 #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ 4815 #define RTC_ALRMAR_MNU_Pos (8U) 4816 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ 4817 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk 4818 #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ 4819 #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ 4820 #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ 4821 #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ 4822 #define RTC_ALRMAR_MSK1_Pos (7U) 4823 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ 4824 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk 4825 #define RTC_ALRMAR_ST_Pos (4U) 4826 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ 4827 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk 4828 #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ 4829 #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ 4830 #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ 4831 #define RTC_ALRMAR_SU_Pos (0U) 4832 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ 4833 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk 4834 #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ 4835 #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ 4836 #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ 4837 #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ 4838 4839 /******************** Bits definition for RTC_ALRMBR register ***************/ 4840 #define RTC_ALRMBR_MSK4_Pos (31U) 4841 #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ 4842 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk 4843 #define RTC_ALRMBR_WDSEL_Pos (30U) 4844 #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ 4845 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk 4846 #define RTC_ALRMBR_DT_Pos (28U) 4847 #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ 4848 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk 4849 #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ 4850 #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ 4851 #define RTC_ALRMBR_DU_Pos (24U) 4852 #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ 4853 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk 4854 #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ 4855 #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ 4856 #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ 4857 #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ 4858 #define RTC_ALRMBR_MSK3_Pos (23U) 4859 #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ 4860 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk 4861 #define RTC_ALRMBR_PM_Pos (22U) 4862 #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ 4863 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk 4864 #define RTC_ALRMBR_HT_Pos (20U) 4865 #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ 4866 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk 4867 #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ 4868 #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ 4869 #define RTC_ALRMBR_HU_Pos (16U) 4870 #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ 4871 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk 4872 #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ 4873 #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ 4874 #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ 4875 #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ 4876 #define RTC_ALRMBR_MSK2_Pos (15U) 4877 #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ 4878 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk 4879 #define RTC_ALRMBR_MNT_Pos (12U) 4880 #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ 4881 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk 4882 #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ 4883 #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ 4884 #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ 4885 #define RTC_ALRMBR_MNU_Pos (8U) 4886 #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ 4887 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk 4888 #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ 4889 #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ 4890 #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ 4891 #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ 4892 #define RTC_ALRMBR_MSK1_Pos (7U) 4893 #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ 4894 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk 4895 #define RTC_ALRMBR_ST_Pos (4U) 4896 #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ 4897 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk 4898 #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ 4899 #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ 4900 #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ 4901 #define RTC_ALRMBR_SU_Pos (0U) 4902 #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ 4903 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk 4904 #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ 4905 #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ 4906 #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ 4907 #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ 4908 4909 /******************** Bits definition for RTC_WPR register ******************/ 4910 #define RTC_WPR_KEY_Pos (0U) 4911 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ 4912 #define RTC_WPR_KEY RTC_WPR_KEY_Msk 4913 4914 /******************** Bits definition for RTC_TSTR register *****************/ 4915 #define RTC_TSTR_PM_Pos (22U) 4916 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ 4917 #define RTC_TSTR_PM RTC_TSTR_PM_Msk 4918 #define RTC_TSTR_HT_Pos (20U) 4919 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ 4920 #define RTC_TSTR_HT RTC_TSTR_HT_Msk 4921 #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ 4922 #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ 4923 #define RTC_TSTR_HU_Pos (16U) 4924 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ 4925 #define RTC_TSTR_HU RTC_TSTR_HU_Msk 4926 #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ 4927 #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ 4928 #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ 4929 #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ 4930 #define RTC_TSTR_MNT_Pos (12U) 4931 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ 4932 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk 4933 #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ 4934 #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ 4935 #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ 4936 #define RTC_TSTR_MNU_Pos (8U) 4937 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ 4938 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk 4939 #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ 4940 #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ 4941 #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ 4942 #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ 4943 #define RTC_TSTR_ST_Pos (4U) 4944 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ 4945 #define RTC_TSTR_ST RTC_TSTR_ST_Msk 4946 #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ 4947 #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ 4948 #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ 4949 #define RTC_TSTR_SU_Pos (0U) 4950 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ 4951 #define RTC_TSTR_SU RTC_TSTR_SU_Msk 4952 #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ 4953 #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ 4954 #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ 4955 #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ 4956 4957 /******************** Bits definition for RTC_TSDR register *****************/ 4958 #define RTC_TSDR_WDU_Pos (13U) 4959 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ 4960 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk 4961 #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ 4962 #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ 4963 #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ 4964 #define RTC_TSDR_MT_Pos (12U) 4965 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ 4966 #define RTC_TSDR_MT RTC_TSDR_MT_Msk 4967 #define RTC_TSDR_MU_Pos (8U) 4968 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ 4969 #define RTC_TSDR_MU RTC_TSDR_MU_Msk 4970 #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ 4971 #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ 4972 #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ 4973 #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ 4974 #define RTC_TSDR_DT_Pos (4U) 4975 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ 4976 #define RTC_TSDR_DT RTC_TSDR_DT_Msk 4977 #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ 4978 #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ 4979 #define RTC_TSDR_DU_Pos (0U) 4980 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ 4981 #define RTC_TSDR_DU RTC_TSDR_DU_Msk 4982 #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ 4983 #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ 4984 #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ 4985 #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ 4986 4987 /******************** Bits definition for RTC_TAFCR register ****************/ 4988 #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U) 4989 #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */ 4990 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk 4991 #define RTC_TAFCR_TAMPIE_Pos (2U) 4992 #define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */ 4993 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk 4994 #define RTC_TAFCR_TAMP1TRG_Pos (1U) 4995 #define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */ 4996 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk 4997 #define RTC_TAFCR_TAMP1E_Pos (0U) 4998 #define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */ 4999 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk 5000 5001 /******************** Bits definition for RTC_BKP0R register ****************/ 5002 #define RTC_BKP0R_Pos (0U) 5003 #define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */ 5004 #define RTC_BKP0R RTC_BKP0R_Msk 5005 5006 /******************** Bits definition for RTC_BKP1R register ****************/ 5007 #define RTC_BKP1R_Pos (0U) 5008 #define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */ 5009 #define RTC_BKP1R RTC_BKP1R_Msk 5010 5011 /******************** Bits definition for RTC_BKP2R register ****************/ 5012 #define RTC_BKP2R_Pos (0U) 5013 #define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */ 5014 #define RTC_BKP2R RTC_BKP2R_Msk 5015 5016 /******************** Bits definition for RTC_BKP3R register ****************/ 5017 #define RTC_BKP3R_Pos (0U) 5018 #define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */ 5019 #define RTC_BKP3R RTC_BKP3R_Msk 5020 5021 /******************** Bits definition for RTC_BKP4R register ****************/ 5022 #define RTC_BKP4R_Pos (0U) 5023 #define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */ 5024 #define RTC_BKP4R RTC_BKP4R_Msk 5025 5026 /******************** Bits definition for RTC_BKP5R register ****************/ 5027 #define RTC_BKP5R_Pos (0U) 5028 #define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */ 5029 #define RTC_BKP5R RTC_BKP5R_Msk 5030 5031 /******************** Bits definition for RTC_BKP6R register ****************/ 5032 #define RTC_BKP6R_Pos (0U) 5033 #define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */ 5034 #define RTC_BKP6R RTC_BKP6R_Msk 5035 5036 /******************** Bits definition for RTC_BKP7R register ****************/ 5037 #define RTC_BKP7R_Pos (0U) 5038 #define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */ 5039 #define RTC_BKP7R RTC_BKP7R_Msk 5040 5041 /******************** Bits definition for RTC_BKP8R register ****************/ 5042 #define RTC_BKP8R_Pos (0U) 5043 #define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */ 5044 #define RTC_BKP8R RTC_BKP8R_Msk 5045 5046 /******************** Bits definition for RTC_BKP9R register ****************/ 5047 #define RTC_BKP9R_Pos (0U) 5048 #define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */ 5049 #define RTC_BKP9R RTC_BKP9R_Msk 5050 5051 /******************** Bits definition for RTC_BKP10R register ***************/ 5052 #define RTC_BKP10R_Pos (0U) 5053 #define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */ 5054 #define RTC_BKP10R RTC_BKP10R_Msk 5055 5056 /******************** Bits definition for RTC_BKP11R register ***************/ 5057 #define RTC_BKP11R_Pos (0U) 5058 #define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */ 5059 #define RTC_BKP11R RTC_BKP11R_Msk 5060 5061 /******************** Bits definition for RTC_BKP12R register ***************/ 5062 #define RTC_BKP12R_Pos (0U) 5063 #define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */ 5064 #define RTC_BKP12R RTC_BKP12R_Msk 5065 5066 /******************** Bits definition for RTC_BKP13R register ***************/ 5067 #define RTC_BKP13R_Pos (0U) 5068 #define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */ 5069 #define RTC_BKP13R RTC_BKP13R_Msk 5070 5071 /******************** Bits definition for RTC_BKP14R register ***************/ 5072 #define RTC_BKP14R_Pos (0U) 5073 #define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */ 5074 #define RTC_BKP14R RTC_BKP14R_Msk 5075 5076 /******************** Bits definition for RTC_BKP15R register ***************/ 5077 #define RTC_BKP15R_Pos (0U) 5078 #define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */ 5079 #define RTC_BKP15R RTC_BKP15R_Msk 5080 5081 /******************** Bits definition for RTC_BKP16R register ***************/ 5082 #define RTC_BKP16R_Pos (0U) 5083 #define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */ 5084 #define RTC_BKP16R RTC_BKP16R_Msk 5085 5086 /******************** Bits definition for RTC_BKP17R register ***************/ 5087 #define RTC_BKP17R_Pos (0U) 5088 #define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */ 5089 #define RTC_BKP17R RTC_BKP17R_Msk 5090 5091 /******************** Bits definition for RTC_BKP18R register ***************/ 5092 #define RTC_BKP18R_Pos (0U) 5093 #define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */ 5094 #define RTC_BKP18R RTC_BKP18R_Msk 5095 5096 /******************** Bits definition for RTC_BKP19R register ***************/ 5097 #define RTC_BKP19R_Pos (0U) 5098 #define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */ 5099 #define RTC_BKP19R RTC_BKP19R_Msk 5100 5101 /******************** Number of backup registers ******************************/ 5102 #define RTC_BKP_NUMBER 20 5103 5104 /******************************************************************************/ 5105 /* */ 5106 /* Serial Peripheral Interface (SPI) */ 5107 /* */ 5108 /******************************************************************************/ 5109 5110 /* 5111 * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie) 5112 */ 5113 5114 /******************* Bit definition for SPI_CR1 register ********************/ 5115 #define SPI_CR1_CPHA_Pos (0U) 5116 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ 5117 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ 5118 #define SPI_CR1_CPOL_Pos (1U) 5119 #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ 5120 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */ 5121 #define SPI_CR1_MSTR_Pos (2U) 5122 #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ 5123 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */ 5124 5125 #define SPI_CR1_BR_Pos (3U) 5126 #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */ 5127 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */ 5128 #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */ 5129 #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */ 5130 #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */ 5131 5132 #define SPI_CR1_SPE_Pos (6U) 5133 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ 5134 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */ 5135 #define SPI_CR1_LSBFIRST_Pos (7U) 5136 #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ 5137 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */ 5138 #define SPI_CR1_SSI_Pos (8U) 5139 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ 5140 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */ 5141 #define SPI_CR1_SSM_Pos (9U) 5142 #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ 5143 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */ 5144 #define SPI_CR1_RXONLY_Pos (10U) 5145 #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ 5146 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */ 5147 #define SPI_CR1_DFF_Pos (11U) 5148 #define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */ 5149 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */ 5150 #define SPI_CR1_CRCNEXT_Pos (12U) 5151 #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ 5152 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */ 5153 #define SPI_CR1_CRCEN_Pos (13U) 5154 #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ 5155 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */ 5156 #define SPI_CR1_BIDIOE_Pos (14U) 5157 #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ 5158 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */ 5159 #define SPI_CR1_BIDIMODE_Pos (15U) 5160 #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ 5161 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */ 5162 5163 /******************* Bit definition for SPI_CR2 register ********************/ 5164 #define SPI_CR2_RXDMAEN_Pos (0U) 5165 #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ 5166 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ 5167 #define SPI_CR2_TXDMAEN_Pos (1U) 5168 #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ 5169 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ 5170 #define SPI_CR2_SSOE_Pos (2U) 5171 #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ 5172 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ 5173 #define SPI_CR2_ERRIE_Pos (5U) 5174 #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ 5175 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ 5176 #define SPI_CR2_RXNEIE_Pos (6U) 5177 #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ 5178 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ 5179 #define SPI_CR2_TXEIE_Pos (7U) 5180 #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ 5181 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ 5182 5183 /******************** Bit definition for SPI_SR register ********************/ 5184 #define SPI_SR_RXNE_Pos (0U) 5185 #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ 5186 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ 5187 #define SPI_SR_TXE_Pos (1U) 5188 #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */ 5189 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ 5190 #define SPI_SR_CHSIDE_Pos (2U) 5191 #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ 5192 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ 5193 #define SPI_SR_UDR_Pos (3U) 5194 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ 5195 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ 5196 #define SPI_SR_CRCERR_Pos (4U) 5197 #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ 5198 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ 5199 #define SPI_SR_MODF_Pos (5U) 5200 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */ 5201 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ 5202 #define SPI_SR_OVR_Pos (6U) 5203 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */ 5204 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ 5205 #define SPI_SR_BSY_Pos (7U) 5206 #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */ 5207 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ 5208 #define SPI_SR_FRE_Pos (8U) 5209 #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */ 5210 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */ 5211 5212 /******************** Bit definition for SPI_DR register ********************/ 5213 #define SPI_DR_DR_Pos (0U) 5214 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ 5215 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ 5216 5217 /******************* Bit definition for SPI_CRCPR register ******************/ 5218 #define SPI_CRCPR_CRCPOLY_Pos (0U) 5219 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ 5220 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */ 5221 5222 /****************** Bit definition for SPI_RXCRCR register ******************/ 5223 #define SPI_RXCRCR_RXCRC_Pos (0U) 5224 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ 5225 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */ 5226 5227 /****************** Bit definition for SPI_TXCRCR register ******************/ 5228 #define SPI_TXCRCR_TXCRC_Pos (0U) 5229 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ 5230 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ 5231 5232 /******************************************************************************/ 5233 /* */ 5234 /* System Configuration (SYSCFG) */ 5235 /* */ 5236 /******************************************************************************/ 5237 /***************** Bit definition for SYSCFG_MEMRMP register ****************/ 5238 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U) 5239 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */ 5240 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */ 5241 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */ 5242 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */ 5243 #define SYSCFG_MEMRMP_BOOT_MODE_Pos (8U) 5244 #define SYSCFG_MEMRMP_BOOT_MODE_Msk (0x3UL << SYSCFG_MEMRMP_BOOT_MODE_Pos) /*!< 0x00000300 */ 5245 #define SYSCFG_MEMRMP_BOOT_MODE SYSCFG_MEMRMP_BOOT_MODE_Msk /*!< Boot mode Config */ 5246 #define SYSCFG_MEMRMP_BOOT_MODE_0 (0x1UL << SYSCFG_MEMRMP_BOOT_MODE_Pos) /*!< 0x00000100 */ 5247 #define SYSCFG_MEMRMP_BOOT_MODE_1 (0x2UL << SYSCFG_MEMRMP_BOOT_MODE_Pos) /*!< 0x00000200 */ 5248 5249 /***************** Bit definition for SYSCFG_PMC register *******************/ 5250 #define SYSCFG_PMC_USB_PU_Pos (0U) 5251 #define SYSCFG_PMC_USB_PU_Msk (0x1UL << SYSCFG_PMC_USB_PU_Pos) /*!< 0x00000001 */ 5252 #define SYSCFG_PMC_USB_PU SYSCFG_PMC_USB_PU_Msk /*!< SYSCFG PMC */ 5253 #define SYSCFG_PMC_LCD_CAPA_Pos (1U) 5254 #define SYSCFG_PMC_LCD_CAPA_Msk (0x1FUL << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x0000003E */ 5255 #define SYSCFG_PMC_LCD_CAPA SYSCFG_PMC_LCD_CAPA_Msk /*!< LCD_CAPA decoupling capacitance connection */ 5256 #define SYSCFG_PMC_LCD_CAPA_0 (0x01UL << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000002 */ 5257 #define SYSCFG_PMC_LCD_CAPA_1 (0x02UL << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000004 */ 5258 #define SYSCFG_PMC_LCD_CAPA_2 (0x04UL << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000008 */ 5259 #define SYSCFG_PMC_LCD_CAPA_3 (0x08UL << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000010 */ 5260 #define SYSCFG_PMC_LCD_CAPA_4 (0x10UL << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000020 */ 5261 5262 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/ 5263 #define SYSCFG_EXTICR1_EXTI0_Pos (0U) 5264 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ 5265 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ 5266 #define SYSCFG_EXTICR1_EXTI1_Pos (4U) 5267 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ 5268 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ 5269 #define SYSCFG_EXTICR1_EXTI2_Pos (8U) 5270 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ 5271 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ 5272 #define SYSCFG_EXTICR1_EXTI3_Pos (12U) 5273 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ 5274 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ 5275 5276 /** 5277 * @brief EXTI0 configuration 5278 */ 5279 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */ 5280 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */ 5281 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */ 5282 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */ 5283 #define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */ 5284 #define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */ 5285 5286 /** 5287 * @brief EXTI1 configuration 5288 */ 5289 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */ 5290 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */ 5291 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */ 5292 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */ 5293 #define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */ 5294 #define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */ 5295 5296 /** 5297 * @brief EXTI2 configuration 5298 */ 5299 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */ 5300 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */ 5301 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */ 5302 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */ 5303 #define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */ 5304 #define SYSCFG_EXTICR1_EXTI2_PH (0x00000500U) /*!< PH[2] pin */ 5305 5306 /** 5307 * @brief EXTI3 configuration 5308 */ 5309 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */ 5310 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */ 5311 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */ 5312 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */ 5313 #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */ 5314 5315 /***************** Bit definition for SYSCFG_EXTICR2 register *****************/ 5316 #define SYSCFG_EXTICR2_EXTI4_Pos (0U) 5317 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ 5318 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ 5319 #define SYSCFG_EXTICR2_EXTI5_Pos (4U) 5320 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ 5321 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ 5322 #define SYSCFG_EXTICR2_EXTI6_Pos (8U) 5323 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ 5324 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ 5325 #define SYSCFG_EXTICR2_EXTI7_Pos (12U) 5326 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ 5327 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ 5328 5329 /** 5330 * @brief EXTI4 configuration 5331 */ 5332 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */ 5333 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */ 5334 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */ 5335 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */ 5336 #define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */ 5337 5338 /** 5339 * @brief EXTI5 configuration 5340 */ 5341 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */ 5342 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */ 5343 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */ 5344 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */ 5345 #define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */ 5346 5347 /** 5348 * @brief EXTI6 configuration 5349 */ 5350 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */ 5351 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */ 5352 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */ 5353 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */ 5354 #define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */ 5355 5356 /** 5357 * @brief EXTI7 configuration 5358 */ 5359 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */ 5360 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */ 5361 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */ 5362 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */ 5363 #define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */ 5364 5365 /***************** Bit definition for SYSCFG_EXTICR3 register *****************/ 5366 #define SYSCFG_EXTICR3_EXTI8_Pos (0U) 5367 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ 5368 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ 5369 #define SYSCFG_EXTICR3_EXTI9_Pos (4U) 5370 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ 5371 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ 5372 #define SYSCFG_EXTICR3_EXTI10_Pos (8U) 5373 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ 5374 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ 5375 #define SYSCFG_EXTICR3_EXTI11_Pos (12U) 5376 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ 5377 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ 5378 5379 /** 5380 * @brief EXTI8 configuration 5381 */ 5382 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */ 5383 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */ 5384 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */ 5385 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */ 5386 #define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */ 5387 5388 /** 5389 * @brief EXTI9 configuration 5390 */ 5391 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */ 5392 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */ 5393 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */ 5394 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */ 5395 #define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */ 5396 5397 /** 5398 * @brief EXTI10 configuration 5399 */ 5400 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */ 5401 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */ 5402 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */ 5403 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */ 5404 #define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */ 5405 5406 /** 5407 * @brief EXTI11 configuration 5408 */ 5409 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */ 5410 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */ 5411 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */ 5412 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */ 5413 #define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */ 5414 5415 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/ 5416 #define SYSCFG_EXTICR4_EXTI12_Pos (0U) 5417 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ 5418 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ 5419 #define SYSCFG_EXTICR4_EXTI13_Pos (4U) 5420 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ 5421 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ 5422 #define SYSCFG_EXTICR4_EXTI14_Pos (8U) 5423 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ 5424 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ 5425 #define SYSCFG_EXTICR4_EXTI15_Pos (12U) 5426 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ 5427 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ 5428 5429 /** 5430 * @brief EXTI12 configuration 5431 */ 5432 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */ 5433 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */ 5434 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */ 5435 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */ 5436 #define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */ 5437 5438 /** 5439 * @brief EXTI13 configuration 5440 */ 5441 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */ 5442 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */ 5443 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */ 5444 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */ 5445 #define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */ 5446 5447 /** 5448 * @brief EXTI14 configuration 5449 */ 5450 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */ 5451 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */ 5452 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */ 5453 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */ 5454 #define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */ 5455 5456 /** 5457 * @brief EXTI15 configuration 5458 */ 5459 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */ 5460 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */ 5461 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */ 5462 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */ 5463 #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */ 5464 5465 /******************************************************************************/ 5466 /* */ 5467 /* Routing Interface (RI) */ 5468 /* */ 5469 /******************************************************************************/ 5470 5471 /******************** Bit definition for RI_ICR register ********************/ 5472 #define RI_ICR_IC1OS_Pos (0U) 5473 #define RI_ICR_IC1OS_Msk (0xFUL << RI_ICR_IC1OS_Pos) /*!< 0x0000000F */ 5474 #define RI_ICR_IC1OS RI_ICR_IC1OS_Msk /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */ 5475 #define RI_ICR_IC1OS_0 (0x1UL << RI_ICR_IC1OS_Pos) /*!< 0x00000001 */ 5476 #define RI_ICR_IC1OS_1 (0x2UL << RI_ICR_IC1OS_Pos) /*!< 0x00000002 */ 5477 #define RI_ICR_IC1OS_2 (0x4UL << RI_ICR_IC1OS_Pos) /*!< 0x00000004 */ 5478 #define RI_ICR_IC1OS_3 (0x8UL << RI_ICR_IC1OS_Pos) /*!< 0x00000008 */ 5479 5480 #define RI_ICR_IC2OS_Pos (4U) 5481 #define RI_ICR_IC2OS_Msk (0xFUL << RI_ICR_IC2OS_Pos) /*!< 0x000000F0 */ 5482 #define RI_ICR_IC2OS RI_ICR_IC2OS_Msk /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */ 5483 #define RI_ICR_IC2OS_0 (0x1UL << RI_ICR_IC2OS_Pos) /*!< 0x00000010 */ 5484 #define RI_ICR_IC2OS_1 (0x2UL << RI_ICR_IC2OS_Pos) /*!< 0x00000020 */ 5485 #define RI_ICR_IC2OS_2 (0x4UL << RI_ICR_IC2OS_Pos) /*!< 0x00000040 */ 5486 #define RI_ICR_IC2OS_3 (0x8UL << RI_ICR_IC2OS_Pos) /*!< 0x00000080 */ 5487 5488 #define RI_ICR_IC3OS_Pos (8U) 5489 #define RI_ICR_IC3OS_Msk (0xFUL << RI_ICR_IC3OS_Pos) /*!< 0x00000F00 */ 5490 #define RI_ICR_IC3OS RI_ICR_IC3OS_Msk /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */ 5491 #define RI_ICR_IC3OS_0 (0x1UL << RI_ICR_IC3OS_Pos) /*!< 0x00000100 */ 5492 #define RI_ICR_IC3OS_1 (0x2UL << RI_ICR_IC3OS_Pos) /*!< 0x00000200 */ 5493 #define RI_ICR_IC3OS_2 (0x4UL << RI_ICR_IC3OS_Pos) /*!< 0x00000400 */ 5494 #define RI_ICR_IC3OS_3 (0x8UL << RI_ICR_IC3OS_Pos) /*!< 0x00000800 */ 5495 5496 #define RI_ICR_IC4OS_Pos (12U) 5497 #define RI_ICR_IC4OS_Msk (0xFUL << RI_ICR_IC4OS_Pos) /*!< 0x0000F000 */ 5498 #define RI_ICR_IC4OS RI_ICR_IC4OS_Msk /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */ 5499 #define RI_ICR_IC4OS_0 (0x1UL << RI_ICR_IC4OS_Pos) /*!< 0x00001000 */ 5500 #define RI_ICR_IC4OS_1 (0x2UL << RI_ICR_IC4OS_Pos) /*!< 0x00002000 */ 5501 #define RI_ICR_IC4OS_2 (0x4UL << RI_ICR_IC4OS_Pos) /*!< 0x00004000 */ 5502 #define RI_ICR_IC4OS_3 (0x8UL << RI_ICR_IC4OS_Pos) /*!< 0x00008000 */ 5503 5504 #define RI_ICR_TIM_Pos (16U) 5505 #define RI_ICR_TIM_Msk (0x3UL << RI_ICR_TIM_Pos) /*!< 0x00030000 */ 5506 #define RI_ICR_TIM RI_ICR_TIM_Msk /*!< TIM[3:0] bits (Timers select bits) */ 5507 #define RI_ICR_TIM_0 (0x1UL << RI_ICR_TIM_Pos) /*!< 0x00010000 */ 5508 #define RI_ICR_TIM_1 (0x2UL << RI_ICR_TIM_Pos) /*!< 0x00020000 */ 5509 5510 #define RI_ICR_IC1_Pos (18U) 5511 #define RI_ICR_IC1_Msk (0x1UL << RI_ICR_IC1_Pos) /*!< 0x00040000 */ 5512 #define RI_ICR_IC1 RI_ICR_IC1_Msk /*!< Input capture 1 */ 5513 #define RI_ICR_IC2_Pos (19U) 5514 #define RI_ICR_IC2_Msk (0x1UL << RI_ICR_IC2_Pos) /*!< 0x00080000 */ 5515 #define RI_ICR_IC2 RI_ICR_IC2_Msk /*!< Input capture 2 */ 5516 #define RI_ICR_IC3_Pos (20U) 5517 #define RI_ICR_IC3_Msk (0x1UL << RI_ICR_IC3_Pos) /*!< 0x00100000 */ 5518 #define RI_ICR_IC3 RI_ICR_IC3_Msk /*!< Input capture 3 */ 5519 #define RI_ICR_IC4_Pos (21U) 5520 #define RI_ICR_IC4_Msk (0x1UL << RI_ICR_IC4_Pos) /*!< 0x00200000 */ 5521 #define RI_ICR_IC4 RI_ICR_IC4_Msk /*!< Input capture 4 */ 5522 5523 /******************** Bit definition for RI_ASCR1 register ********************/ 5524 #define RI_ASCR1_CH_Pos (0U) 5525 #define RI_ASCR1_CH_Msk (0x3FCFFFFUL << RI_ASCR1_CH_Pos) /*!< 0x03FCFFFF */ 5526 #define RI_ASCR1_CH RI_ASCR1_CH_Msk /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */ 5527 #define RI_ASCR1_CH_0 (0x00000001U) /*!< Bit 0 */ 5528 #define RI_ASCR1_CH_1 (0x00000002U) /*!< Bit 1 */ 5529 #define RI_ASCR1_CH_2 (0x00000004U) /*!< Bit 2 */ 5530 #define RI_ASCR1_CH_3 (0x00000008U) /*!< Bit 3 */ 5531 #define RI_ASCR1_CH_4 (0x00000010U) /*!< Bit 4 */ 5532 #define RI_ASCR1_CH_5 (0x00000020U) /*!< Bit 5 */ 5533 #define RI_ASCR1_CH_6 (0x00000040U) /*!< Bit 6 */ 5534 #define RI_ASCR1_CH_7 (0x00000080U) /*!< Bit 7 */ 5535 #define RI_ASCR1_CH_8 (0x00000100U) /*!< Bit 8 */ 5536 #define RI_ASCR1_CH_9 (0x00000200U) /*!< Bit 9 */ 5537 #define RI_ASCR1_CH_10 (0x00000400U) /*!< Bit 10 */ 5538 #define RI_ASCR1_CH_11 (0x00000800U) /*!< Bit 11 */ 5539 #define RI_ASCR1_CH_12 (0x00001000U) /*!< Bit 12 */ 5540 #define RI_ASCR1_CH_13 (0x00002000U) /*!< Bit 13 */ 5541 #define RI_ASCR1_CH_14 (0x00004000U) /*!< Bit 14 */ 5542 #define RI_ASCR1_CH_15 (0x00008000U) /*!< Bit 15 */ 5543 #define RI_ASCR1_CH_18 (0x00040000U) /*!< Bit 18 */ 5544 #define RI_ASCR1_CH_19 (0x00080000U) /*!< Bit 19 */ 5545 #define RI_ASCR1_CH_20 (0x00100000U) /*!< Bit 20 */ 5546 #define RI_ASCR1_CH_21 (0x00200000U) /*!< Bit 21 */ 5547 #define RI_ASCR1_CH_22 (0x00400000U) /*!< Bit 22 */ 5548 #define RI_ASCR1_CH_23 (0x00800000U) /*!< Bit 23 */ 5549 #define RI_ASCR1_CH_24 (0x01000000U) /*!< Bit 24 */ 5550 #define RI_ASCR1_CH_25 (0x02000000U) /*!< Bit 25 */ 5551 #define RI_ASCR1_VCOMP_Pos (26U) 5552 #define RI_ASCR1_VCOMP_Msk (0x1UL << RI_ASCR1_VCOMP_Pos) /*!< 0x04000000 */ 5553 #define RI_ASCR1_VCOMP RI_ASCR1_VCOMP_Msk /*!< ADC analog switch selection for internal node to COMP1 */ 5554 #define RI_ASCR1_SCM_Pos (31U) 5555 #define RI_ASCR1_SCM_Msk (0x1UL << RI_ASCR1_SCM_Pos) /*!< 0x80000000 */ 5556 #define RI_ASCR1_SCM RI_ASCR1_SCM_Msk /*!< I/O Switch control mode */ 5557 5558 /******************** Bit definition for RI_ASCR2 register ********************/ 5559 #define RI_ASCR2_GR10_1 (0x00000001U) /*!< GR10-1 selection bit */ 5560 #define RI_ASCR2_GR10_2 (0x00000002U) /*!< GR10-2 selection bit */ 5561 #define RI_ASCR2_GR10_3 (0x00000004U) /*!< GR10-3 selection bit */ 5562 #define RI_ASCR2_GR10_4 (0x00000008U) /*!< GR10-4 selection bit */ 5563 #define RI_ASCR2_GR6_Pos (4U) 5564 #define RI_ASCR2_GR6_Msk (0x3UL << RI_ASCR2_GR6_Pos) /*!< 0x00000030 */ 5565 #define RI_ASCR2_GR6 RI_ASCR2_GR6_Msk /*!< GR6 selection bits */ 5566 #define RI_ASCR2_GR6_1 (0x1UL << RI_ASCR2_GR6_Pos) /*!< 0x00000010 */ 5567 #define RI_ASCR2_GR6_2 (0x2UL << RI_ASCR2_GR6_Pos) /*!< 0x00000020 */ 5568 #define RI_ASCR2_GR5_1 (0x00000040U) /*!< GR5-1 selection bit */ 5569 #define RI_ASCR2_GR5_2 (0x00000080U) /*!< GR5-2 selection bit */ 5570 #define RI_ASCR2_GR5_3 (0x00000100U) /*!< GR5-3 selection bit */ 5571 #define RI_ASCR2_GR4_1 (0x00000200U) /*!< GR4-1 selection bit */ 5572 #define RI_ASCR2_GR4_2 (0x00000400U) /*!< GR4-2 selection bit */ 5573 #define RI_ASCR2_GR4_3 (0x00000800U) /*!< GR4-3 selection bit */ 5574 #define RI_ASCR2_GR4_4 (0x00008000U) /*!< GR4-4 selection bit */ 5575 5576 /******************** Bit definition for RI_HYSCR1 register ********************/ 5577 #define RI_HYSCR1_PA_Pos (0U) 5578 #define RI_HYSCR1_PA_Msk (0xFFFFUL << RI_HYSCR1_PA_Pos) /*!< 0x0000FFFF */ 5579 #define RI_HYSCR1_PA RI_HYSCR1_PA_Msk /*!< PA[15:0] Port A Hysteresis selection */ 5580 #define RI_HYSCR1_PA_0 (0x0001UL << RI_HYSCR1_PA_Pos) /*!< 0x00000001 */ 5581 #define RI_HYSCR1_PA_1 (0x0002UL << RI_HYSCR1_PA_Pos) /*!< 0x00000002 */ 5582 #define RI_HYSCR1_PA_2 (0x0004UL << RI_HYSCR1_PA_Pos) /*!< 0x00000004 */ 5583 #define RI_HYSCR1_PA_3 (0x0008UL << RI_HYSCR1_PA_Pos) /*!< 0x00000008 */ 5584 #define RI_HYSCR1_PA_4 (0x0010UL << RI_HYSCR1_PA_Pos) /*!< 0x00000010 */ 5585 #define RI_HYSCR1_PA_5 (0x0020UL << RI_HYSCR1_PA_Pos) /*!< 0x00000020 */ 5586 #define RI_HYSCR1_PA_6 (0x0040UL << RI_HYSCR1_PA_Pos) /*!< 0x00000040 */ 5587 #define RI_HYSCR1_PA_7 (0x0080UL << RI_HYSCR1_PA_Pos) /*!< 0x00000080 */ 5588 #define RI_HYSCR1_PA_8 (0x0100UL << RI_HYSCR1_PA_Pos) /*!< 0x00000100 */ 5589 #define RI_HYSCR1_PA_9 (0x0200UL << RI_HYSCR1_PA_Pos) /*!< 0x00000200 */ 5590 #define RI_HYSCR1_PA_10 (0x0400UL << RI_HYSCR1_PA_Pos) /*!< 0x00000400 */ 5591 #define RI_HYSCR1_PA_11 (0x0800UL << RI_HYSCR1_PA_Pos) /*!< 0x00000800 */ 5592 #define RI_HYSCR1_PA_12 (0x1000UL << RI_HYSCR1_PA_Pos) /*!< 0x00001000 */ 5593 #define RI_HYSCR1_PA_13 (0x2000UL << RI_HYSCR1_PA_Pos) /*!< 0x00002000 */ 5594 #define RI_HYSCR1_PA_14 (0x4000UL << RI_HYSCR1_PA_Pos) /*!< 0x00004000 */ 5595 #define RI_HYSCR1_PA_15 (0x8000UL << RI_HYSCR1_PA_Pos) /*!< 0x00008000 */ 5596 5597 #define RI_HYSCR1_PB_Pos (16U) 5598 #define RI_HYSCR1_PB_Msk (0xFFFFUL << RI_HYSCR1_PB_Pos) /*!< 0xFFFF0000 */ 5599 #define RI_HYSCR1_PB RI_HYSCR1_PB_Msk /*!< PB[15:0] Port B Hysteresis selection */ 5600 #define RI_HYSCR1_PB_0 (0x0001UL << RI_HYSCR1_PB_Pos) /*!< 0x00010000 */ 5601 #define RI_HYSCR1_PB_1 (0x0002UL << RI_HYSCR1_PB_Pos) /*!< 0x00020000 */ 5602 #define RI_HYSCR1_PB_2 (0x0004UL << RI_HYSCR1_PB_Pos) /*!< 0x00040000 */ 5603 #define RI_HYSCR1_PB_3 (0x0008UL << RI_HYSCR1_PB_Pos) /*!< 0x00080000 */ 5604 #define RI_HYSCR1_PB_4 (0x0010UL << RI_HYSCR1_PB_Pos) /*!< 0x00100000 */ 5605 #define RI_HYSCR1_PB_5 (0x0020UL << RI_HYSCR1_PB_Pos) /*!< 0x00200000 */ 5606 #define RI_HYSCR1_PB_6 (0x0040UL << RI_HYSCR1_PB_Pos) /*!< 0x00400000 */ 5607 #define RI_HYSCR1_PB_7 (0x0080UL << RI_HYSCR1_PB_Pos) /*!< 0x00800000 */ 5608 #define RI_HYSCR1_PB_8 (0x0100UL << RI_HYSCR1_PB_Pos) /*!< 0x01000000 */ 5609 #define RI_HYSCR1_PB_9 (0x0200UL << RI_HYSCR1_PB_Pos) /*!< 0x02000000 */ 5610 #define RI_HYSCR1_PB_10 (0x0400UL << RI_HYSCR1_PB_Pos) /*!< 0x04000000 */ 5611 #define RI_HYSCR1_PB_11 (0x0800UL << RI_HYSCR1_PB_Pos) /*!< 0x08000000 */ 5612 #define RI_HYSCR1_PB_12 (0x1000UL << RI_HYSCR1_PB_Pos) /*!< 0x10000000 */ 5613 #define RI_HYSCR1_PB_13 (0x2000UL << RI_HYSCR1_PB_Pos) /*!< 0x20000000 */ 5614 #define RI_HYSCR1_PB_14 (0x4000UL << RI_HYSCR1_PB_Pos) /*!< 0x40000000 */ 5615 #define RI_HYSCR1_PB_15 (0x8000UL << RI_HYSCR1_PB_Pos) /*!< 0x80000000 */ 5616 5617 /******************** Bit definition for RI_HYSCR2 register ********************/ 5618 #define RI_HYSCR2_PC_Pos (0U) 5619 #define RI_HYSCR2_PC_Msk (0xFFFFUL << RI_HYSCR2_PC_Pos) /*!< 0x0000FFFF */ 5620 #define RI_HYSCR2_PC RI_HYSCR2_PC_Msk /*!< PC[15:0] Port C Hysteresis selection */ 5621 #define RI_HYSCR2_PC_0 (0x0001UL << RI_HYSCR2_PC_Pos) /*!< 0x00000001 */ 5622 #define RI_HYSCR2_PC_1 (0x0002UL << RI_HYSCR2_PC_Pos) /*!< 0x00000002 */ 5623 #define RI_HYSCR2_PC_2 (0x0004UL << RI_HYSCR2_PC_Pos) /*!< 0x00000004 */ 5624 #define RI_HYSCR2_PC_3 (0x0008UL << RI_HYSCR2_PC_Pos) /*!< 0x00000008 */ 5625 #define RI_HYSCR2_PC_4 (0x0010UL << RI_HYSCR2_PC_Pos) /*!< 0x00000010 */ 5626 #define RI_HYSCR2_PC_5 (0x0020UL << RI_HYSCR2_PC_Pos) /*!< 0x00000020 */ 5627 #define RI_HYSCR2_PC_6 (0x0040UL << RI_HYSCR2_PC_Pos) /*!< 0x00000040 */ 5628 #define RI_HYSCR2_PC_7 (0x0080UL << RI_HYSCR2_PC_Pos) /*!< 0x00000080 */ 5629 #define RI_HYSCR2_PC_8 (0x0100UL << RI_HYSCR2_PC_Pos) /*!< 0x00000100 */ 5630 #define RI_HYSCR2_PC_9 (0x0200UL << RI_HYSCR2_PC_Pos) /*!< 0x00000200 */ 5631 #define RI_HYSCR2_PC_10 (0x0400UL << RI_HYSCR2_PC_Pos) /*!< 0x00000400 */ 5632 #define RI_HYSCR2_PC_11 (0x0800UL << RI_HYSCR2_PC_Pos) /*!< 0x00000800 */ 5633 #define RI_HYSCR2_PC_12 (0x1000UL << RI_HYSCR2_PC_Pos) /*!< 0x00001000 */ 5634 #define RI_HYSCR2_PC_13 (0x2000UL << RI_HYSCR2_PC_Pos) /*!< 0x00002000 */ 5635 #define RI_HYSCR2_PC_14 (0x4000UL << RI_HYSCR2_PC_Pos) /*!< 0x00004000 */ 5636 #define RI_HYSCR2_PC_15 (0x8000UL << RI_HYSCR2_PC_Pos) /*!< 0x00008000 */ 5637 5638 #define RI_HYSCR2_PD_Pos (16U) 5639 #define RI_HYSCR2_PD_Msk (0xFFFFUL << RI_HYSCR2_PD_Pos) /*!< 0xFFFF0000 */ 5640 #define RI_HYSCR2_PD RI_HYSCR2_PD_Msk /*!< PD[15:0] Port D Hysteresis selection */ 5641 #define RI_HYSCR2_PD_0 (0x0001UL << RI_HYSCR2_PD_Pos) /*!< 0x00010000 */ 5642 #define RI_HYSCR2_PD_1 (0x0002UL << RI_HYSCR2_PD_Pos) /*!< 0x00020000 */ 5643 #define RI_HYSCR2_PD_2 (0x0004UL << RI_HYSCR2_PD_Pos) /*!< 0x00040000 */ 5644 #define RI_HYSCR2_PD_3 (0x0008UL << RI_HYSCR2_PD_Pos) /*!< 0x00080000 */ 5645 #define RI_HYSCR2_PD_4 (0x0010UL << RI_HYSCR2_PD_Pos) /*!< 0x00100000 */ 5646 #define RI_HYSCR2_PD_5 (0x0020UL << RI_HYSCR2_PD_Pos) /*!< 0x00200000 */ 5647 #define RI_HYSCR2_PD_6 (0x0040UL << RI_HYSCR2_PD_Pos) /*!< 0x00400000 */ 5648 #define RI_HYSCR2_PD_7 (0x0080UL << RI_HYSCR2_PD_Pos) /*!< 0x00800000 */ 5649 #define RI_HYSCR2_PD_8 (0x0100UL << RI_HYSCR2_PD_Pos) /*!< 0x01000000 */ 5650 #define RI_HYSCR2_PD_9 (0x0200UL << RI_HYSCR2_PD_Pos) /*!< 0x02000000 */ 5651 #define RI_HYSCR2_PD_10 (0x0400UL << RI_HYSCR2_PD_Pos) /*!< 0x04000000 */ 5652 #define RI_HYSCR2_PD_11 (0x0800UL << RI_HYSCR2_PD_Pos) /*!< 0x08000000 */ 5653 #define RI_HYSCR2_PD_12 (0x1000UL << RI_HYSCR2_PD_Pos) /*!< 0x10000000 */ 5654 #define RI_HYSCR2_PD_13 (0x2000UL << RI_HYSCR2_PD_Pos) /*!< 0x20000000 */ 5655 #define RI_HYSCR2_PD_14 (0x4000UL << RI_HYSCR2_PD_Pos) /*!< 0x40000000 */ 5656 #define RI_HYSCR2_PD_15 (0x8000UL << RI_HYSCR2_PD_Pos) /*!< 0x80000000 */ 5657 5658 /******************** Bit definition for RI_HYSCR3 register ********************/ 5659 #define RI_HYSCR3_PE_Pos (0U) 5660 #define RI_HYSCR3_PE_Msk (0xFFFFUL << RI_HYSCR3_PE_Pos) /*!< 0x0000FFFF */ 5661 #define RI_HYSCR3_PE RI_HYSCR3_PE_Msk /*!< PE[15:0] Port E Hysteresis selection */ 5662 #define RI_HYSCR3_PE_0 (0x0001UL << RI_HYSCR3_PE_Pos) /*!< 0x00000001 */ 5663 #define RI_HYSCR3_PE_1 (0x0002UL << RI_HYSCR3_PE_Pos) /*!< 0x00000002 */ 5664 #define RI_HYSCR3_PE_2 (0x0004UL << RI_HYSCR3_PE_Pos) /*!< 0x00000004 */ 5665 #define RI_HYSCR3_PE_3 (0x0008UL << RI_HYSCR3_PE_Pos) /*!< 0x00000008 */ 5666 #define RI_HYSCR3_PE_4 (0x0010UL << RI_HYSCR3_PE_Pos) /*!< 0x00000010 */ 5667 #define RI_HYSCR3_PE_5 (0x0020UL << RI_HYSCR3_PE_Pos) /*!< 0x00000020 */ 5668 #define RI_HYSCR3_PE_6 (0x0040UL << RI_HYSCR3_PE_Pos) /*!< 0x00000040 */ 5669 #define RI_HYSCR3_PE_7 (0x0080UL << RI_HYSCR3_PE_Pos) /*!< 0x00000080 */ 5670 #define RI_HYSCR3_PE_8 (0x0100UL << RI_HYSCR3_PE_Pos) /*!< 0x00000100 */ 5671 #define RI_HYSCR3_PE_9 (0x0200UL << RI_HYSCR3_PE_Pos) /*!< 0x00000200 */ 5672 #define RI_HYSCR3_PE_10 (0x0400UL << RI_HYSCR3_PE_Pos) /*!< 0x00000400 */ 5673 #define RI_HYSCR3_PE_11 (0x0800UL << RI_HYSCR3_PE_Pos) /*!< 0x00000800 */ 5674 #define RI_HYSCR3_PE_12 (0x1000UL << RI_HYSCR3_PE_Pos) /*!< 0x00001000 */ 5675 #define RI_HYSCR3_PE_13 (0x2000UL << RI_HYSCR3_PE_Pos) /*!< 0x00002000 */ 5676 #define RI_HYSCR3_PE_14 (0x4000UL << RI_HYSCR3_PE_Pos) /*!< 0x00004000 */ 5677 #define RI_HYSCR3_PE_15 (0x8000UL << RI_HYSCR3_PE_Pos) /*!< 0x00008000 */ 5678 5679 /******************************************************************************/ 5680 /* */ 5681 /* Timers (TIM) */ 5682 /* */ 5683 /******************************************************************************/ 5684 5685 /******************* Bit definition for TIM_CR1 register ********************/ 5686 #define TIM_CR1_CEN_Pos (0U) 5687 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ 5688 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ 5689 #define TIM_CR1_UDIS_Pos (1U) 5690 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ 5691 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ 5692 #define TIM_CR1_URS_Pos (2U) 5693 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */ 5694 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ 5695 #define TIM_CR1_OPM_Pos (3U) 5696 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ 5697 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ 5698 #define TIM_CR1_DIR_Pos (4U) 5699 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ 5700 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ 5701 5702 #define TIM_CR1_CMS_Pos (5U) 5703 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ 5704 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ 5705 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ 5706 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ 5707 5708 #define TIM_CR1_ARPE_Pos (7U) 5709 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ 5710 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ 5711 5712 #define TIM_CR1_CKD_Pos (8U) 5713 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ 5714 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ 5715 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ 5716 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ 5717 5718 /******************* Bit definition for TIM_CR2 register ********************/ 5719 #define TIM_CR2_CCDS_Pos (3U) 5720 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ 5721 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ 5722 5723 #define TIM_CR2_MMS_Pos (4U) 5724 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ 5725 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ 5726 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ 5727 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ 5728 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ 5729 5730 #define TIM_CR2_TI1S_Pos (7U) 5731 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ 5732 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ 5733 5734 /******************* Bit definition for TIM_SMCR register *******************/ 5735 #define TIM_SMCR_SMS_Pos (0U) 5736 #define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */ 5737 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ 5738 #define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */ 5739 #define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ 5740 #define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ 5741 5742 #define TIM_SMCR_OCCS_Pos (3U) 5743 #define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */ 5744 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */ 5745 5746 #define TIM_SMCR_TS_Pos (4U) 5747 #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ 5748 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ 5749 #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ 5750 #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ 5751 #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ 5752 5753 #define TIM_SMCR_MSM_Pos (7U) 5754 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ 5755 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ 5756 5757 #define TIM_SMCR_ETF_Pos (8U) 5758 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ 5759 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ 5760 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ 5761 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ 5762 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ 5763 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ 5764 5765 #define TIM_SMCR_ETPS_Pos (12U) 5766 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ 5767 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ 5768 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ 5769 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ 5770 5771 #define TIM_SMCR_ECE_Pos (14U) 5772 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ 5773 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ 5774 #define TIM_SMCR_ETP_Pos (15U) 5775 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ 5776 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ 5777 5778 /******************* Bit definition for TIM_DIER register *******************/ 5779 #define TIM_DIER_UIE_Pos (0U) 5780 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ 5781 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ 5782 #define TIM_DIER_CC1IE_Pos (1U) 5783 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ 5784 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ 5785 #define TIM_DIER_CC2IE_Pos (2U) 5786 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ 5787 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ 5788 #define TIM_DIER_CC3IE_Pos (3U) 5789 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ 5790 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ 5791 #define TIM_DIER_CC4IE_Pos (4U) 5792 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ 5793 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ 5794 #define TIM_DIER_TIE_Pos (6U) 5795 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ 5796 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ 5797 #define TIM_DIER_UDE_Pos (8U) 5798 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ 5799 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ 5800 #define TIM_DIER_CC1DE_Pos (9U) 5801 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ 5802 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ 5803 #define TIM_DIER_CC2DE_Pos (10U) 5804 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ 5805 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ 5806 #define TIM_DIER_CC3DE_Pos (11U) 5807 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ 5808 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ 5809 #define TIM_DIER_CC4DE_Pos (12U) 5810 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ 5811 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ 5812 #define TIM_DIER_COMDE ((uint16_t)0x2000U) /*!<COM DMA request enable */ 5813 #define TIM_DIER_TDE_Pos (14U) 5814 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ 5815 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ 5816 5817 /******************** Bit definition for TIM_SR register ********************/ 5818 #define TIM_SR_UIF_Pos (0U) 5819 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */ 5820 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ 5821 #define TIM_SR_CC1IF_Pos (1U) 5822 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ 5823 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ 5824 #define TIM_SR_CC2IF_Pos (2U) 5825 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ 5826 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ 5827 #define TIM_SR_CC3IF_Pos (3U) 5828 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ 5829 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ 5830 #define TIM_SR_CC4IF_Pos (4U) 5831 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ 5832 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ 5833 #define TIM_SR_TIF_Pos (6U) 5834 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */ 5835 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ 5836 #define TIM_SR_CC1OF_Pos (9U) 5837 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ 5838 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ 5839 #define TIM_SR_CC2OF_Pos (10U) 5840 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ 5841 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ 5842 #define TIM_SR_CC3OF_Pos (11U) 5843 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ 5844 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ 5845 #define TIM_SR_CC4OF_Pos (12U) 5846 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ 5847 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ 5848 5849 /******************* Bit definition for TIM_EGR register ********************/ 5850 #define TIM_EGR_UG_Pos (0U) 5851 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */ 5852 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ 5853 #define TIM_EGR_CC1G_Pos (1U) 5854 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ 5855 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ 5856 #define TIM_EGR_CC2G_Pos (2U) 5857 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ 5858 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ 5859 #define TIM_EGR_CC3G_Pos (3U) 5860 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ 5861 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ 5862 #define TIM_EGR_CC4G_Pos (4U) 5863 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ 5864 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ 5865 #define TIM_EGR_TG_Pos (6U) 5866 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */ 5867 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ 5868 5869 /****************** Bit definition for TIM_CCMR1 register *******************/ 5870 #define TIM_CCMR1_CC1S_Pos (0U) 5871 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ 5872 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ 5873 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ 5874 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ 5875 5876 #define TIM_CCMR1_OC1FE_Pos (2U) 5877 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ 5878 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ 5879 #define TIM_CCMR1_OC1PE_Pos (3U) 5880 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ 5881 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ 5882 5883 #define TIM_CCMR1_OC1M_Pos (4U) 5884 #define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */ 5885 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ 5886 #define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */ 5887 #define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */ 5888 #define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */ 5889 5890 #define TIM_CCMR1_OC1CE_Pos (7U) 5891 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ 5892 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */ 5893 5894 #define TIM_CCMR1_CC2S_Pos (8U) 5895 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ 5896 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ 5897 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ 5898 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ 5899 5900 #define TIM_CCMR1_OC2FE_Pos (10U) 5901 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ 5902 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ 5903 #define TIM_CCMR1_OC2PE_Pos (11U) 5904 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ 5905 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ 5906 5907 #define TIM_CCMR1_OC2M_Pos (12U) 5908 #define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */ 5909 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ 5910 #define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */ 5911 #define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */ 5912 #define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */ 5913 5914 #define TIM_CCMR1_OC2CE_Pos (15U) 5915 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ 5916 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ 5917 5918 /*----------------------------------------------------------------------------*/ 5919 5920 #define TIM_CCMR1_IC1PSC_Pos (2U) 5921 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ 5922 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ 5923 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ 5924 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ 5925 5926 #define TIM_CCMR1_IC1F_Pos (4U) 5927 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ 5928 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ 5929 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ 5930 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ 5931 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ 5932 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ 5933 5934 #define TIM_CCMR1_IC2PSC_Pos (10U) 5935 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ 5936 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ 5937 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ 5938 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ 5939 5940 #define TIM_CCMR1_IC2F_Pos (12U) 5941 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ 5942 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ 5943 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ 5944 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ 5945 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ 5946 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ 5947 5948 /****************** Bit definition for TIM_CCMR2 register *******************/ 5949 #define TIM_CCMR2_CC3S_Pos (0U) 5950 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ 5951 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ 5952 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ 5953 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ 5954 5955 #define TIM_CCMR2_OC3FE_Pos (2U) 5956 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ 5957 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ 5958 #define TIM_CCMR2_OC3PE_Pos (3U) 5959 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ 5960 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ 5961 5962 #define TIM_CCMR2_OC3M_Pos (4U) 5963 #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */ 5964 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ 5965 #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */ 5966 #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */ 5967 #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */ 5968 5969 #define TIM_CCMR2_OC3CE_Pos (7U) 5970 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ 5971 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ 5972 5973 #define TIM_CCMR2_CC4S_Pos (8U) 5974 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ 5975 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ 5976 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ 5977 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ 5978 5979 #define TIM_CCMR2_OC4FE_Pos (10U) 5980 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ 5981 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ 5982 #define TIM_CCMR2_OC4PE_Pos (11U) 5983 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ 5984 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ 5985 5986 #define TIM_CCMR2_OC4M_Pos (12U) 5987 #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */ 5988 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ 5989 #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */ 5990 #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */ 5991 #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */ 5992 5993 #define TIM_CCMR2_OC4CE_Pos (15U) 5994 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ 5995 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ 5996 5997 /*----------------------------------------------------------------------------*/ 5998 5999 #define TIM_CCMR2_IC3PSC_Pos (2U) 6000 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ 6001 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ 6002 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ 6003 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ 6004 6005 #define TIM_CCMR2_IC3F_Pos (4U) 6006 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ 6007 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ 6008 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ 6009 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ 6010 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ 6011 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ 6012 6013 #define TIM_CCMR2_IC4PSC_Pos (10U) 6014 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ 6015 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ 6016 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ 6017 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ 6018 6019 #define TIM_CCMR2_IC4F_Pos (12U) 6020 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ 6021 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ 6022 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ 6023 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ 6024 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ 6025 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ 6026 6027 /******************* Bit definition for TIM_CCER register *******************/ 6028 #define TIM_CCER_CC1E_Pos (0U) 6029 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ 6030 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ 6031 #define TIM_CCER_CC1P_Pos (1U) 6032 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ 6033 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ 6034 #define TIM_CCER_CC1NP_Pos (3U) 6035 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ 6036 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ 6037 #define TIM_CCER_CC2E_Pos (4U) 6038 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ 6039 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ 6040 #define TIM_CCER_CC2P_Pos (5U) 6041 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ 6042 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ 6043 #define TIM_CCER_CC2NP_Pos (7U) 6044 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ 6045 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ 6046 #define TIM_CCER_CC3E_Pos (8U) 6047 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ 6048 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ 6049 #define TIM_CCER_CC3P_Pos (9U) 6050 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ 6051 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ 6052 #define TIM_CCER_CC3NP_Pos (11U) 6053 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ 6054 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ 6055 #define TIM_CCER_CC4E_Pos (12U) 6056 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ 6057 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ 6058 #define TIM_CCER_CC4P_Pos (13U) 6059 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ 6060 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ 6061 #define TIM_CCER_CC4NP_Pos (15U) 6062 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */ 6063 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */ 6064 6065 /******************* Bit definition for TIM_CNT register ********************/ 6066 #define TIM_CNT_CNT_Pos (0U) 6067 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ 6068 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ 6069 6070 /******************* Bit definition for TIM_PSC register ********************/ 6071 #define TIM_PSC_PSC_Pos (0U) 6072 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ 6073 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ 6074 6075 /******************* Bit definition for TIM_ARR register ********************/ 6076 #define TIM_ARR_ARR_Pos (0U) 6077 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ 6078 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */ 6079 6080 /******************* Bit definition for TIM_CCR1 register *******************/ 6081 #define TIM_CCR1_CCR1_Pos (0U) 6082 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ 6083 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ 6084 6085 /******************* Bit definition for TIM_CCR2 register *******************/ 6086 #define TIM_CCR2_CCR2_Pos (0U) 6087 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ 6088 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ 6089 6090 /******************* Bit definition for TIM_CCR3 register *******************/ 6091 #define TIM_CCR3_CCR3_Pos (0U) 6092 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ 6093 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ 6094 6095 /******************* Bit definition for TIM_CCR4 register *******************/ 6096 #define TIM_CCR4_CCR4_Pos (0U) 6097 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ 6098 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ 6099 6100 /******************* Bit definition for TIM_DCR register ********************/ 6101 #define TIM_DCR_DBA_Pos (0U) 6102 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ 6103 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ 6104 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ 6105 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ 6106 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ 6107 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ 6108 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ 6109 6110 #define TIM_DCR_DBL_Pos (8U) 6111 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ 6112 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ 6113 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ 6114 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ 6115 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ 6116 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ 6117 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ 6118 6119 /******************* Bit definition for TIM_DMAR register *******************/ 6120 #define TIM_DMAR_DMAB_Pos (0U) 6121 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ 6122 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ 6123 6124 /******************* Bit definition for TIM_OR register *********************/ 6125 #define TIM_OR_TI1RMP_Pos (0U) 6126 #define TIM_OR_TI1RMP_Msk (0x3UL << TIM_OR_TI1RMP_Pos) /*!< 0x00000003 */ 6127 #define TIM_OR_TI1RMP TIM_OR_TI1RMP_Msk /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */ 6128 #define TIM_OR_TI1RMP_0 (0x1UL << TIM_OR_TI1RMP_Pos) /*!< 0x00000001 */ 6129 #define TIM_OR_TI1RMP_1 (0x2UL << TIM_OR_TI1RMP_Pos) /*!< 0x00000002 */ 6130 6131 #define TIM_OR_ETR_RMP_Pos (2U) 6132 #define TIM_OR_ETR_RMP_Msk (0x1UL << TIM_OR_ETR_RMP_Pos) /*!< 0x00000004 */ 6133 #define TIM_OR_ETR_RMP TIM_OR_ETR_RMP_Msk /*!<ETR_RMP bit (TIM10/11 ETR remap)*/ 6134 #define TIM_OR_TI1_RMP_RI_Pos (3U) 6135 #define TIM_OR_TI1_RMP_RI_Msk (0x1UL << TIM_OR_TI1_RMP_RI_Pos) /*!< 0x00000008 */ 6136 #define TIM_OR_TI1_RMP_RI TIM_OR_TI1_RMP_RI_Msk /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */ 6137 6138 6139 /******************************************************************************/ 6140 /* */ 6141 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ 6142 /* */ 6143 /******************************************************************************/ 6144 6145 /******************* Bit definition for USART_SR register *******************/ 6146 #define USART_SR_PE_Pos (0U) 6147 #define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos) /*!< 0x00000001 */ 6148 #define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */ 6149 #define USART_SR_FE_Pos (1U) 6150 #define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos) /*!< 0x00000002 */ 6151 #define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */ 6152 #define USART_SR_NE_Pos (2U) 6153 #define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos) /*!< 0x00000004 */ 6154 #define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */ 6155 #define USART_SR_ORE_Pos (3U) 6156 #define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos) /*!< 0x00000008 */ 6157 #define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */ 6158 #define USART_SR_IDLE_Pos (4U) 6159 #define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos) /*!< 0x00000010 */ 6160 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */ 6161 #define USART_SR_RXNE_Pos (5U) 6162 #define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos) /*!< 0x00000020 */ 6163 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */ 6164 #define USART_SR_TC_Pos (6U) 6165 #define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos) /*!< 0x00000040 */ 6166 #define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */ 6167 #define USART_SR_TXE_Pos (7U) 6168 #define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos) /*!< 0x00000080 */ 6169 #define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */ 6170 #define USART_SR_LBD_Pos (8U) 6171 #define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos) /*!< 0x00000100 */ 6172 #define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */ 6173 #define USART_SR_CTS_Pos (9U) 6174 #define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos) /*!< 0x00000200 */ 6175 #define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */ 6176 6177 /******************* Bit definition for USART_DR register *******************/ 6178 #define USART_DR_DR_Pos (0U) 6179 #define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos) /*!< 0x000001FF */ 6180 #define USART_DR_DR USART_DR_DR_Msk /*!< Data value */ 6181 6182 /****************** Bit definition for USART_BRR register *******************/ 6183 #define USART_BRR_DIV_FRACTION_Pos (0U) 6184 #define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */ 6185 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */ 6186 #define USART_BRR_DIV_MANTISSA_Pos (4U) 6187 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */ 6188 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */ 6189 6190 /****************** Bit definition for USART_CR1 register *******************/ 6191 #define USART_CR1_SBK_Pos (0U) 6192 #define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos) /*!< 0x00000001 */ 6193 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */ 6194 #define USART_CR1_RWU_Pos (1U) 6195 #define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos) /*!< 0x00000002 */ 6196 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */ 6197 #define USART_CR1_RE_Pos (2U) 6198 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */ 6199 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ 6200 #define USART_CR1_TE_Pos (3U) 6201 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */ 6202 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ 6203 #define USART_CR1_IDLEIE_Pos (4U) 6204 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ 6205 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ 6206 #define USART_CR1_RXNEIE_Pos (5U) 6207 #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ 6208 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */ 6209 #define USART_CR1_TCIE_Pos (6U) 6210 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ 6211 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ 6212 #define USART_CR1_TXEIE_Pos (7U) 6213 #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ 6214 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */ 6215 #define USART_CR1_PEIE_Pos (8U) 6216 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ 6217 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ 6218 #define USART_CR1_PS_Pos (9U) 6219 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */ 6220 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ 6221 #define USART_CR1_PCE_Pos (10U) 6222 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */ 6223 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ 6224 #define USART_CR1_WAKE_Pos (11U) 6225 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ 6226 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */ 6227 #define USART_CR1_M_Pos (12U) 6228 #define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos) /*!< 0x00001000 */ 6229 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */ 6230 #define USART_CR1_UE_Pos (13U) 6231 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00002000 */ 6232 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ 6233 #define USART_CR1_OVER8_Pos (15U) 6234 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ 6235 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit mode */ 6236 6237 /****************** Bit definition for USART_CR2 register *******************/ 6238 #define USART_CR2_ADD_Pos (0U) 6239 #define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos) /*!< 0x0000000F */ 6240 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ 6241 #define USART_CR2_LBDL_Pos (5U) 6242 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ 6243 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ 6244 #define USART_CR2_LBDIE_Pos (6U) 6245 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ 6246 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ 6247 #define USART_CR2_LBCL_Pos (8U) 6248 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ 6249 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ 6250 #define USART_CR2_CPHA_Pos (9U) 6251 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ 6252 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ 6253 #define USART_CR2_CPOL_Pos (10U) 6254 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ 6255 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ 6256 #define USART_CR2_CLKEN_Pos (11U) 6257 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ 6258 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ 6259 6260 #define USART_CR2_STOP_Pos (12U) 6261 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */ 6262 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ 6263 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */ 6264 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */ 6265 6266 #define USART_CR2_LINEN_Pos (14U) 6267 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ 6268 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ 6269 6270 /****************** Bit definition for USART_CR3 register *******************/ 6271 #define USART_CR3_EIE_Pos (0U) 6272 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */ 6273 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ 6274 #define USART_CR3_IREN_Pos (1U) 6275 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */ 6276 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ 6277 #define USART_CR3_IRLP_Pos (2U) 6278 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ 6279 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ 6280 #define USART_CR3_HDSEL_Pos (3U) 6281 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ 6282 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ 6283 #define USART_CR3_NACK_Pos (4U) 6284 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */ 6285 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */ 6286 #define USART_CR3_SCEN_Pos (5U) 6287 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ 6288 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */ 6289 #define USART_CR3_DMAR_Pos (6U) 6290 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ 6291 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ 6292 #define USART_CR3_DMAT_Pos (7U) 6293 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ 6294 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ 6295 #define USART_CR3_RTSE_Pos (8U) 6296 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ 6297 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ 6298 #define USART_CR3_CTSE_Pos (9U) 6299 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ 6300 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ 6301 #define USART_CR3_CTSIE_Pos (10U) 6302 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ 6303 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ 6304 #define USART_CR3_ONEBIT_Pos (11U) 6305 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ 6306 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */ 6307 6308 /****************** Bit definition for USART_GTPR register ******************/ 6309 #define USART_GTPR_PSC_Pos (0U) 6310 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ 6311 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ 6312 #define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos) /*!< 0x00000001 */ 6313 #define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos) /*!< 0x00000002 */ 6314 #define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos) /*!< 0x00000004 */ 6315 #define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos) /*!< 0x00000008 */ 6316 #define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos) /*!< 0x00000010 */ 6317 #define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos) /*!< 0x00000020 */ 6318 #define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos) /*!< 0x00000040 */ 6319 #define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos) /*!< 0x00000080 */ 6320 6321 #define USART_GTPR_GT_Pos (8U) 6322 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ 6323 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */ 6324 6325 /******************************************************************************/ 6326 /* */ 6327 /* Universal Serial Bus (USB) */ 6328 /* */ 6329 /******************************************************************************/ 6330 6331 /*!<Endpoint-specific registers */ 6332 6333 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */ 6334 #define USB_EP1R (USB_BASE + 0x00000004U) /*!< endpoint 1 register address */ 6335 #define USB_EP2R (USB_BASE + 0x00000008U) /*!< endpoint 2 register address */ 6336 #define USB_EP3R (USB_BASE + 0x0000000CU) /*!< endpoint 3 register address */ 6337 #define USB_EP4R (USB_BASE + 0x00000010U) /*!< endpoint 4 register address */ 6338 #define USB_EP5R (USB_BASE + 0x00000014U) /*!< endpoint 5 register address */ 6339 #define USB_EP6R (USB_BASE + 0x00000018U) /*!< endpoint 6 register address */ 6340 #define USB_EP7R (USB_BASE + 0x0000001CU) /*!< endpoint 7 register address */ 6341 6342 /* bit positions */ 6343 #define USB_EP_CTR_RX_Pos (15U) 6344 #define USB_EP_CTR_RX_Msk (0x1UL << USB_EP_CTR_RX_Pos) /*!< 0x00008000 */ 6345 #define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /*!< EndPoint Correct TRansfer RX */ 6346 #define USB_EP_DTOG_RX_Pos (14U) 6347 #define USB_EP_DTOG_RX_Msk (0x1UL << USB_EP_DTOG_RX_Pos) /*!< 0x00004000 */ 6348 #define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /*!< EndPoint Data TOGGLE RX */ 6349 #define USB_EPRX_STAT_Pos (12U) 6350 #define USB_EPRX_STAT_Msk (0x3UL << USB_EPRX_STAT_Pos) /*!< 0x00003000 */ 6351 #define USB_EPRX_STAT USB_EPRX_STAT_Msk /*!< EndPoint RX STATus bit field */ 6352 #define USB_EP_SETUP_Pos (11U) 6353 #define USB_EP_SETUP_Msk (0x1UL << USB_EP_SETUP_Pos) /*!< 0x00000800 */ 6354 #define USB_EP_SETUP USB_EP_SETUP_Msk /*!< EndPoint SETUP */ 6355 #define USB_EP_T_FIELD_Pos (9U) 6356 #define USB_EP_T_FIELD_Msk (0x3UL << USB_EP_T_FIELD_Pos) /*!< 0x00000600 */ 6357 #define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /*!< EndPoint TYPE */ 6358 #define USB_EP_KIND_Pos (8U) 6359 #define USB_EP_KIND_Msk (0x1UL << USB_EP_KIND_Pos) /*!< 0x00000100 */ 6360 #define USB_EP_KIND USB_EP_KIND_Msk /*!< EndPoint KIND */ 6361 #define USB_EP_CTR_TX_Pos (7U) 6362 #define USB_EP_CTR_TX_Msk (0x1UL << USB_EP_CTR_TX_Pos) /*!< 0x00000080 */ 6363 #define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /*!< EndPoint Correct TRansfer TX */ 6364 #define USB_EP_DTOG_TX_Pos (6U) 6365 #define USB_EP_DTOG_TX_Msk (0x1UL << USB_EP_DTOG_TX_Pos) /*!< 0x00000040 */ 6366 #define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /*!< EndPoint Data TOGGLE TX */ 6367 #define USB_EPTX_STAT_Pos (4U) 6368 #define USB_EPTX_STAT_Msk (0x3UL << USB_EPTX_STAT_Pos) /*!< 0x00000030 */ 6369 #define USB_EPTX_STAT USB_EPTX_STAT_Msk /*!< EndPoint TX STATus bit field */ 6370 #define USB_EPADDR_FIELD_Pos (0U) 6371 #define USB_EPADDR_FIELD_Msk (0xFUL << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */ 6372 #define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */ 6373 6374 /* EndPoint REGister MASK (no toggle fields) */ 6375 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD) 6376 /*!< EP_TYPE[1:0] EndPoint TYPE */ 6377 #define USB_EP_TYPE_MASK_Pos (9U) 6378 #define USB_EP_TYPE_MASK_Msk (0x3UL << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */ 6379 #define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */ 6380 #define USB_EP_BULK (0x00000000U) /*!< EndPoint BULK */ 6381 #define USB_EP_CONTROL (0x00000200U) /*!< EndPoint CONTROL */ 6382 #define USB_EP_ISOCHRONOUS (0x00000400U) /*!< EndPoint ISOCHRONOUS */ 6383 #define USB_EP_INTERRUPT (0x00000600U) /*!< EndPoint INTERRUPT */ 6384 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK) 6385 6386 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */ 6387 /*!< STAT_TX[1:0] STATus for TX transfer */ 6388 #define USB_EP_TX_DIS (0x00000000U) /*!< EndPoint TX DISabled */ 6389 #define USB_EP_TX_STALL (0x00000010U) /*!< EndPoint TX STALLed */ 6390 #define USB_EP_TX_NAK (0x00000020U) /*!< EndPoint TX NAKed */ 6391 #define USB_EP_TX_VALID (0x00000030U) /*!< EndPoint TX VALID */ 6392 #define USB_EPTX_DTOG1 (0x00000010U) /*!< EndPoint TX Data TOGgle bit1 */ 6393 #define USB_EPTX_DTOG2 (0x00000020U) /*!< EndPoint TX Data TOGgle bit2 */ 6394 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK) 6395 /*!< STAT_RX[1:0] STATus for RX transfer */ 6396 #define USB_EP_RX_DIS (0x00000000U) /*!< EndPoint RX DISabled */ 6397 #define USB_EP_RX_STALL (0x00001000U) /*!< EndPoint RX STALLed */ 6398 #define USB_EP_RX_NAK (0x00002000U) /*!< EndPoint RX NAKed */ 6399 #define USB_EP_RX_VALID (0x00003000U) /*!< EndPoint RX VALID */ 6400 #define USB_EPRX_DTOG1 (0x00001000U) /*!< EndPoint RX Data TOGgle bit1 */ 6401 #define USB_EPRX_DTOG2 (0x00002000U) /*!< EndPoint RX Data TOGgle bit1 */ 6402 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) 6403 6404 /******************* Bit definition for USB_EP0R register *******************/ 6405 #define USB_EP0R_EA_Pos (0U) 6406 #define USB_EP0R_EA_Msk (0xFUL << USB_EP0R_EA_Pos) /*!< 0x0000000F */ 6407 #define USB_EP0R_EA USB_EP0R_EA_Msk /*!<Endpoint Address */ 6408 6409 #define USB_EP0R_STAT_TX_Pos (4U) 6410 #define USB_EP0R_STAT_TX_Msk (0x3UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */ 6411 #define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 6412 #define USB_EP0R_STAT_TX_0 (0x1UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */ 6413 #define USB_EP0R_STAT_TX_1 (0x2UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */ 6414 6415 #define USB_EP0R_DTOG_TX_Pos (6U) 6416 #define USB_EP0R_DTOG_TX_Msk (0x1UL << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */ 6417 #define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ 6418 #define USB_EP0R_CTR_TX_Pos (7U) 6419 #define USB_EP0R_CTR_TX_Msk (0x1UL << USB_EP0R_CTR_TX_Pos) /*!< 0x00000080 */ 6420 #define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /*!<Correct Transfer for transmission */ 6421 #define USB_EP0R_EP_KIND_Pos (8U) 6422 #define USB_EP0R_EP_KIND_Msk (0x1UL << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */ 6423 #define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /*!<Endpoint Kind */ 6424 6425 #define USB_EP0R_EP_TYPE_Pos (9U) 6426 #define USB_EP0R_EP_TYPE_Msk (0x3UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */ 6427 #define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ 6428 #define USB_EP0R_EP_TYPE_0 (0x1UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */ 6429 #define USB_EP0R_EP_TYPE_1 (0x2UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */ 6430 6431 #define USB_EP0R_SETUP_Pos (11U) 6432 #define USB_EP0R_SETUP_Msk (0x1UL << USB_EP0R_SETUP_Pos) /*!< 0x00000800 */ 6433 #define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /*!<Setup transaction completed */ 6434 6435 #define USB_EP0R_STAT_RX_Pos (12U) 6436 #define USB_EP0R_STAT_RX_Msk (0x3UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */ 6437 #define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ 6438 #define USB_EP0R_STAT_RX_0 (0x1UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */ 6439 #define USB_EP0R_STAT_RX_1 (0x2UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */ 6440 6441 #define USB_EP0R_DTOG_RX_Pos (14U) 6442 #define USB_EP0R_DTOG_RX_Msk (0x1UL << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */ 6443 #define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ 6444 #define USB_EP0R_CTR_RX_Pos (15U) 6445 #define USB_EP0R_CTR_RX_Msk (0x1UL << USB_EP0R_CTR_RX_Pos) /*!< 0x00008000 */ 6446 #define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /*!<Correct Transfer for reception */ 6447 6448 /******************* Bit definition for USB_EP1R register *******************/ 6449 #define USB_EP1R_EA_Pos (0U) 6450 #define USB_EP1R_EA_Msk (0xFUL << USB_EP1R_EA_Pos) /*!< 0x0000000F */ 6451 #define USB_EP1R_EA USB_EP1R_EA_Msk /*!<Endpoint Address */ 6452 6453 #define USB_EP1R_STAT_TX_Pos (4U) 6454 #define USB_EP1R_STAT_TX_Msk (0x3UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */ 6455 #define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 6456 #define USB_EP1R_STAT_TX_0 (0x1UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */ 6457 #define USB_EP1R_STAT_TX_1 (0x2UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */ 6458 6459 #define USB_EP1R_DTOG_TX_Pos (6U) 6460 #define USB_EP1R_DTOG_TX_Msk (0x1UL << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */ 6461 #define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ 6462 #define USB_EP1R_CTR_TX_Pos (7U) 6463 #define USB_EP1R_CTR_TX_Msk (0x1UL << USB_EP1R_CTR_TX_Pos) /*!< 0x00000080 */ 6464 #define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /*!<Correct Transfer for transmission */ 6465 #define USB_EP1R_EP_KIND_Pos (8U) 6466 #define USB_EP1R_EP_KIND_Msk (0x1UL << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */ 6467 #define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /*!<Endpoint Kind */ 6468 6469 #define USB_EP1R_EP_TYPE_Pos (9U) 6470 #define USB_EP1R_EP_TYPE_Msk (0x3UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */ 6471 #define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ 6472 #define USB_EP1R_EP_TYPE_0 (0x1UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */ 6473 #define USB_EP1R_EP_TYPE_1 (0x2UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */ 6474 6475 #define USB_EP1R_SETUP_Pos (11U) 6476 #define USB_EP1R_SETUP_Msk (0x1UL << USB_EP1R_SETUP_Pos) /*!< 0x00000800 */ 6477 #define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /*!<Setup transaction completed */ 6478 6479 #define USB_EP1R_STAT_RX_Pos (12U) 6480 #define USB_EP1R_STAT_RX_Msk (0x3UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */ 6481 #define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ 6482 #define USB_EP1R_STAT_RX_0 (0x1UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */ 6483 #define USB_EP1R_STAT_RX_1 (0x2UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */ 6484 6485 #define USB_EP1R_DTOG_RX_Pos (14U) 6486 #define USB_EP1R_DTOG_RX_Msk (0x1UL << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */ 6487 #define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ 6488 #define USB_EP1R_CTR_RX_Pos (15U) 6489 #define USB_EP1R_CTR_RX_Msk (0x1UL << USB_EP1R_CTR_RX_Pos) /*!< 0x00008000 */ 6490 #define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /*!<Correct Transfer for reception */ 6491 6492 /******************* Bit definition for USB_EP2R register *******************/ 6493 #define USB_EP2R_EA_Pos (0U) 6494 #define USB_EP2R_EA_Msk (0xFUL << USB_EP2R_EA_Pos) /*!< 0x0000000F */ 6495 #define USB_EP2R_EA USB_EP2R_EA_Msk /*!<Endpoint Address */ 6496 6497 #define USB_EP2R_STAT_TX_Pos (4U) 6498 #define USB_EP2R_STAT_TX_Msk (0x3UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */ 6499 #define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 6500 #define USB_EP2R_STAT_TX_0 (0x1UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */ 6501 #define USB_EP2R_STAT_TX_1 (0x2UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */ 6502 6503 #define USB_EP2R_DTOG_TX_Pos (6U) 6504 #define USB_EP2R_DTOG_TX_Msk (0x1UL << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */ 6505 #define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ 6506 #define USB_EP2R_CTR_TX_Pos (7U) 6507 #define USB_EP2R_CTR_TX_Msk (0x1UL << USB_EP2R_CTR_TX_Pos) /*!< 0x00000080 */ 6508 #define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /*!<Correct Transfer for transmission */ 6509 #define USB_EP2R_EP_KIND_Pos (8U) 6510 #define USB_EP2R_EP_KIND_Msk (0x1UL << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */ 6511 #define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /*!<Endpoint Kind */ 6512 6513 #define USB_EP2R_EP_TYPE_Pos (9U) 6514 #define USB_EP2R_EP_TYPE_Msk (0x3UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */ 6515 #define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ 6516 #define USB_EP2R_EP_TYPE_0 (0x1UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */ 6517 #define USB_EP2R_EP_TYPE_1 (0x2UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */ 6518 6519 #define USB_EP2R_SETUP_Pos (11U) 6520 #define USB_EP2R_SETUP_Msk (0x1UL << USB_EP2R_SETUP_Pos) /*!< 0x00000800 */ 6521 #define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /*!<Setup transaction completed */ 6522 6523 #define USB_EP2R_STAT_RX_Pos (12U) 6524 #define USB_EP2R_STAT_RX_Msk (0x3UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */ 6525 #define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ 6526 #define USB_EP2R_STAT_RX_0 (0x1UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */ 6527 #define USB_EP2R_STAT_RX_1 (0x2UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */ 6528 6529 #define USB_EP2R_DTOG_RX_Pos (14U) 6530 #define USB_EP2R_DTOG_RX_Msk (0x1UL << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */ 6531 #define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ 6532 #define USB_EP2R_CTR_RX_Pos (15U) 6533 #define USB_EP2R_CTR_RX_Msk (0x1UL << USB_EP2R_CTR_RX_Pos) /*!< 0x00008000 */ 6534 #define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /*!<Correct Transfer for reception */ 6535 6536 /******************* Bit definition for USB_EP3R register *******************/ 6537 #define USB_EP3R_EA_Pos (0U) 6538 #define USB_EP3R_EA_Msk (0xFUL << USB_EP3R_EA_Pos) /*!< 0x0000000F */ 6539 #define USB_EP3R_EA USB_EP3R_EA_Msk /*!<Endpoint Address */ 6540 6541 #define USB_EP3R_STAT_TX_Pos (4U) 6542 #define USB_EP3R_STAT_TX_Msk (0x3UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */ 6543 #define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 6544 #define USB_EP3R_STAT_TX_0 (0x1UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */ 6545 #define USB_EP3R_STAT_TX_1 (0x2UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */ 6546 6547 #define USB_EP3R_DTOG_TX_Pos (6U) 6548 #define USB_EP3R_DTOG_TX_Msk (0x1UL << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */ 6549 #define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ 6550 #define USB_EP3R_CTR_TX_Pos (7U) 6551 #define USB_EP3R_CTR_TX_Msk (0x1UL << USB_EP3R_CTR_TX_Pos) /*!< 0x00000080 */ 6552 #define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /*!<Correct Transfer for transmission */ 6553 #define USB_EP3R_EP_KIND_Pos (8U) 6554 #define USB_EP3R_EP_KIND_Msk (0x1UL << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */ 6555 #define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /*!<Endpoint Kind */ 6556 6557 #define USB_EP3R_EP_TYPE_Pos (9U) 6558 #define USB_EP3R_EP_TYPE_Msk (0x3UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */ 6559 #define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ 6560 #define USB_EP3R_EP_TYPE_0 (0x1UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */ 6561 #define USB_EP3R_EP_TYPE_1 (0x2UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */ 6562 6563 #define USB_EP3R_SETUP_Pos (11U) 6564 #define USB_EP3R_SETUP_Msk (0x1UL << USB_EP3R_SETUP_Pos) /*!< 0x00000800 */ 6565 #define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /*!<Setup transaction completed */ 6566 6567 #define USB_EP3R_STAT_RX_Pos (12U) 6568 #define USB_EP3R_STAT_RX_Msk (0x3UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */ 6569 #define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ 6570 #define USB_EP3R_STAT_RX_0 (0x1UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */ 6571 #define USB_EP3R_STAT_RX_1 (0x2UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */ 6572 6573 #define USB_EP3R_DTOG_RX_Pos (14U) 6574 #define USB_EP3R_DTOG_RX_Msk (0x1UL << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */ 6575 #define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ 6576 #define USB_EP3R_CTR_RX_Pos (15U) 6577 #define USB_EP3R_CTR_RX_Msk (0x1UL << USB_EP3R_CTR_RX_Pos) /*!< 0x00008000 */ 6578 #define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /*!<Correct Transfer for reception */ 6579 6580 /******************* Bit definition for USB_EP4R register *******************/ 6581 #define USB_EP4R_EA_Pos (0U) 6582 #define USB_EP4R_EA_Msk (0xFUL << USB_EP4R_EA_Pos) /*!< 0x0000000F */ 6583 #define USB_EP4R_EA USB_EP4R_EA_Msk /*!<Endpoint Address */ 6584 6585 #define USB_EP4R_STAT_TX_Pos (4U) 6586 #define USB_EP4R_STAT_TX_Msk (0x3UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */ 6587 #define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 6588 #define USB_EP4R_STAT_TX_0 (0x1UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */ 6589 #define USB_EP4R_STAT_TX_1 (0x2UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */ 6590 6591 #define USB_EP4R_DTOG_TX_Pos (6U) 6592 #define USB_EP4R_DTOG_TX_Msk (0x1UL << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */ 6593 #define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ 6594 #define USB_EP4R_CTR_TX_Pos (7U) 6595 #define USB_EP4R_CTR_TX_Msk (0x1UL << USB_EP4R_CTR_TX_Pos) /*!< 0x00000080 */ 6596 #define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /*!<Correct Transfer for transmission */ 6597 #define USB_EP4R_EP_KIND_Pos (8U) 6598 #define USB_EP4R_EP_KIND_Msk (0x1UL << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */ 6599 #define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /*!<Endpoint Kind */ 6600 6601 #define USB_EP4R_EP_TYPE_Pos (9U) 6602 #define USB_EP4R_EP_TYPE_Msk (0x3UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */ 6603 #define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ 6604 #define USB_EP4R_EP_TYPE_0 (0x1UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */ 6605 #define USB_EP4R_EP_TYPE_1 (0x2UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */ 6606 6607 #define USB_EP4R_SETUP_Pos (11U) 6608 #define USB_EP4R_SETUP_Msk (0x1UL << USB_EP4R_SETUP_Pos) /*!< 0x00000800 */ 6609 #define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /*!<Setup transaction completed */ 6610 6611 #define USB_EP4R_STAT_RX_Pos (12U) 6612 #define USB_EP4R_STAT_RX_Msk (0x3UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */ 6613 #define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ 6614 #define USB_EP4R_STAT_RX_0 (0x1UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */ 6615 #define USB_EP4R_STAT_RX_1 (0x2UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */ 6616 6617 #define USB_EP4R_DTOG_RX_Pos (14U) 6618 #define USB_EP4R_DTOG_RX_Msk (0x1UL << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */ 6619 #define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ 6620 #define USB_EP4R_CTR_RX_Pos (15U) 6621 #define USB_EP4R_CTR_RX_Msk (0x1UL << USB_EP4R_CTR_RX_Pos) /*!< 0x00008000 */ 6622 #define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /*!<Correct Transfer for reception */ 6623 6624 /******************* Bit definition for USB_EP5R register *******************/ 6625 #define USB_EP5R_EA_Pos (0U) 6626 #define USB_EP5R_EA_Msk (0xFUL << USB_EP5R_EA_Pos) /*!< 0x0000000F */ 6627 #define USB_EP5R_EA USB_EP5R_EA_Msk /*!<Endpoint Address */ 6628 6629 #define USB_EP5R_STAT_TX_Pos (4U) 6630 #define USB_EP5R_STAT_TX_Msk (0x3UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */ 6631 #define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 6632 #define USB_EP5R_STAT_TX_0 (0x1UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */ 6633 #define USB_EP5R_STAT_TX_1 (0x2UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */ 6634 6635 #define USB_EP5R_DTOG_TX_Pos (6U) 6636 #define USB_EP5R_DTOG_TX_Msk (0x1UL << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */ 6637 #define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ 6638 #define USB_EP5R_CTR_TX_Pos (7U) 6639 #define USB_EP5R_CTR_TX_Msk (0x1UL << USB_EP5R_CTR_TX_Pos) /*!< 0x00000080 */ 6640 #define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /*!<Correct Transfer for transmission */ 6641 #define USB_EP5R_EP_KIND_Pos (8U) 6642 #define USB_EP5R_EP_KIND_Msk (0x1UL << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */ 6643 #define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /*!<Endpoint Kind */ 6644 6645 #define USB_EP5R_EP_TYPE_Pos (9U) 6646 #define USB_EP5R_EP_TYPE_Msk (0x3UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */ 6647 #define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ 6648 #define USB_EP5R_EP_TYPE_0 (0x1UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */ 6649 #define USB_EP5R_EP_TYPE_1 (0x2UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */ 6650 6651 #define USB_EP5R_SETUP_Pos (11U) 6652 #define USB_EP5R_SETUP_Msk (0x1UL << USB_EP5R_SETUP_Pos) /*!< 0x00000800 */ 6653 #define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /*!<Setup transaction completed */ 6654 6655 #define USB_EP5R_STAT_RX_Pos (12U) 6656 #define USB_EP5R_STAT_RX_Msk (0x3UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */ 6657 #define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ 6658 #define USB_EP5R_STAT_RX_0 (0x1UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */ 6659 #define USB_EP5R_STAT_RX_1 (0x2UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */ 6660 6661 #define USB_EP5R_DTOG_RX_Pos (14U) 6662 #define USB_EP5R_DTOG_RX_Msk (0x1UL << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */ 6663 #define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ 6664 #define USB_EP5R_CTR_RX_Pos (15U) 6665 #define USB_EP5R_CTR_RX_Msk (0x1UL << USB_EP5R_CTR_RX_Pos) /*!< 0x00008000 */ 6666 #define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /*!<Correct Transfer for reception */ 6667 6668 /******************* Bit definition for USB_EP6R register *******************/ 6669 #define USB_EP6R_EA_Pos (0U) 6670 #define USB_EP6R_EA_Msk (0xFUL << USB_EP6R_EA_Pos) /*!< 0x0000000F */ 6671 #define USB_EP6R_EA USB_EP6R_EA_Msk /*!<Endpoint Address */ 6672 6673 #define USB_EP6R_STAT_TX_Pos (4U) 6674 #define USB_EP6R_STAT_TX_Msk (0x3UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */ 6675 #define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 6676 #define USB_EP6R_STAT_TX_0 (0x1UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */ 6677 #define USB_EP6R_STAT_TX_1 (0x2UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */ 6678 6679 #define USB_EP6R_DTOG_TX_Pos (6U) 6680 #define USB_EP6R_DTOG_TX_Msk (0x1UL << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */ 6681 #define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ 6682 #define USB_EP6R_CTR_TX_Pos (7U) 6683 #define USB_EP6R_CTR_TX_Msk (0x1UL << USB_EP6R_CTR_TX_Pos) /*!< 0x00000080 */ 6684 #define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /*!<Correct Transfer for transmission */ 6685 #define USB_EP6R_EP_KIND_Pos (8U) 6686 #define USB_EP6R_EP_KIND_Msk (0x1UL << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */ 6687 #define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /*!<Endpoint Kind */ 6688 6689 #define USB_EP6R_EP_TYPE_Pos (9U) 6690 #define USB_EP6R_EP_TYPE_Msk (0x3UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */ 6691 #define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ 6692 #define USB_EP6R_EP_TYPE_0 (0x1UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */ 6693 #define USB_EP6R_EP_TYPE_1 (0x2UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */ 6694 6695 #define USB_EP6R_SETUP_Pos (11U) 6696 #define USB_EP6R_SETUP_Msk (0x1UL << USB_EP6R_SETUP_Pos) /*!< 0x00000800 */ 6697 #define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /*!<Setup transaction completed */ 6698 6699 #define USB_EP6R_STAT_RX_Pos (12U) 6700 #define USB_EP6R_STAT_RX_Msk (0x3UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */ 6701 #define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ 6702 #define USB_EP6R_STAT_RX_0 (0x1UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */ 6703 #define USB_EP6R_STAT_RX_1 (0x2UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */ 6704 6705 #define USB_EP6R_DTOG_RX_Pos (14U) 6706 #define USB_EP6R_DTOG_RX_Msk (0x1UL << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */ 6707 #define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ 6708 #define USB_EP6R_CTR_RX_Pos (15U) 6709 #define USB_EP6R_CTR_RX_Msk (0x1UL << USB_EP6R_CTR_RX_Pos) /*!< 0x00008000 */ 6710 #define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /*!<Correct Transfer for reception */ 6711 6712 /******************* Bit definition for USB_EP7R register *******************/ 6713 #define USB_EP7R_EA_Pos (0U) 6714 #define USB_EP7R_EA_Msk (0xFUL << USB_EP7R_EA_Pos) /*!< 0x0000000F */ 6715 #define USB_EP7R_EA USB_EP7R_EA_Msk /*!<Endpoint Address */ 6716 6717 #define USB_EP7R_STAT_TX_Pos (4U) 6718 #define USB_EP7R_STAT_TX_Msk (0x3UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */ 6719 #define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 6720 #define USB_EP7R_STAT_TX_0 (0x1UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */ 6721 #define USB_EP7R_STAT_TX_1 (0x2UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */ 6722 6723 #define USB_EP7R_DTOG_TX_Pos (6U) 6724 #define USB_EP7R_DTOG_TX_Msk (0x1UL << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */ 6725 #define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ 6726 #define USB_EP7R_CTR_TX_Pos (7U) 6727 #define USB_EP7R_CTR_TX_Msk (0x1UL << USB_EP7R_CTR_TX_Pos) /*!< 0x00000080 */ 6728 #define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /*!<Correct Transfer for transmission */ 6729 #define USB_EP7R_EP_KIND_Pos (8U) 6730 #define USB_EP7R_EP_KIND_Msk (0x1UL << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */ 6731 #define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /*!<Endpoint Kind */ 6732 6733 #define USB_EP7R_EP_TYPE_Pos (9U) 6734 #define USB_EP7R_EP_TYPE_Msk (0x3UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */ 6735 #define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ 6736 #define USB_EP7R_EP_TYPE_0 (0x1UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */ 6737 #define USB_EP7R_EP_TYPE_1 (0x2UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */ 6738 6739 #define USB_EP7R_SETUP_Pos (11U) 6740 #define USB_EP7R_SETUP_Msk (0x1UL << USB_EP7R_SETUP_Pos) /*!< 0x00000800 */ 6741 #define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /*!<Setup transaction completed */ 6742 6743 #define USB_EP7R_STAT_RX_Pos (12U) 6744 #define USB_EP7R_STAT_RX_Msk (0x3UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */ 6745 #define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ 6746 #define USB_EP7R_STAT_RX_0 (0x1UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */ 6747 #define USB_EP7R_STAT_RX_1 (0x2UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */ 6748 6749 #define USB_EP7R_DTOG_RX_Pos (14U) 6750 #define USB_EP7R_DTOG_RX_Msk (0x1UL << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */ 6751 #define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ 6752 #define USB_EP7R_CTR_RX_Pos (15U) 6753 #define USB_EP7R_CTR_RX_Msk (0x1UL << USB_EP7R_CTR_RX_Pos) /*!< 0x00008000 */ 6754 #define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /*!<Correct Transfer for reception */ 6755 6756 /*!<Common registers */ 6757 6758 #define USB_CNTR (USB_BASE + 0x00000040U) /*!< Control register */ 6759 #define USB_ISTR (USB_BASE + 0x00000044U) /*!< Interrupt status register */ 6760 #define USB_FNR (USB_BASE + 0x00000048U) /*!< Frame number register */ 6761 #define USB_DADDR (USB_BASE + 0x0000004CU) /*!< Device address register */ 6762 #define USB_BTABLE (USB_BASE + 0x00000050U) /*!< Buffer Table address register */ 6763 6764 6765 6766 /******************* Bit definition for USB_CNTR register *******************/ 6767 #define USB_CNTR_FRES_Pos (0U) 6768 #define USB_CNTR_FRES_Msk (0x1UL << USB_CNTR_FRES_Pos) /*!< 0x00000001 */ 6769 #define USB_CNTR_FRES USB_CNTR_FRES_Msk /*!<Force USB Reset */ 6770 #define USB_CNTR_PDWN_Pos (1U) 6771 #define USB_CNTR_PDWN_Msk (0x1UL << USB_CNTR_PDWN_Pos) /*!< 0x00000002 */ 6772 #define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /*!<Power down */ 6773 #define USB_CNTR_LPMODE_Pos (2U) 6774 #define USB_CNTR_LPMODE_Msk (0x1UL << USB_CNTR_LPMODE_Pos) /*!< 0x00000004 */ 6775 #define USB_CNTR_LPMODE USB_CNTR_LPMODE_Msk /*!<Low-power mode */ 6776 #define USB_CNTR_FSUSP_Pos (3U) 6777 #define USB_CNTR_FSUSP_Msk (0x1UL << USB_CNTR_FSUSP_Pos) /*!< 0x00000008 */ 6778 #define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /*!<Force suspend */ 6779 #define USB_CNTR_RESUME_Pos (4U) 6780 #define USB_CNTR_RESUME_Msk (0x1UL << USB_CNTR_RESUME_Pos) /*!< 0x00000010 */ 6781 #define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /*!<Resume request */ 6782 #define USB_CNTR_ESOFM_Pos (8U) 6783 #define USB_CNTR_ESOFM_Msk (0x1UL << USB_CNTR_ESOFM_Pos) /*!< 0x00000100 */ 6784 #define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /*!<Expected Start Of Frame Interrupt Mask */ 6785 #define USB_CNTR_SOFM_Pos (9U) 6786 #define USB_CNTR_SOFM_Msk (0x1UL << USB_CNTR_SOFM_Pos) /*!< 0x00000200 */ 6787 #define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /*!<Start Of Frame Interrupt Mask */ 6788 #define USB_CNTR_RESETM_Pos (10U) 6789 #define USB_CNTR_RESETM_Msk (0x1UL << USB_CNTR_RESETM_Pos) /*!< 0x00000400 */ 6790 #define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /*!<RESET Interrupt Mask */ 6791 #define USB_CNTR_SUSPM_Pos (11U) 6792 #define USB_CNTR_SUSPM_Msk (0x1UL << USB_CNTR_SUSPM_Pos) /*!< 0x00000800 */ 6793 #define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /*!<Suspend mode Interrupt Mask */ 6794 #define USB_CNTR_WKUPM_Pos (12U) 6795 #define USB_CNTR_WKUPM_Msk (0x1UL << USB_CNTR_WKUPM_Pos) /*!< 0x00001000 */ 6796 #define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /*!<Wakeup Interrupt Mask */ 6797 #define USB_CNTR_ERRM_Pos (13U) 6798 #define USB_CNTR_ERRM_Msk (0x1UL << USB_CNTR_ERRM_Pos) /*!< 0x00002000 */ 6799 #define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /*!<Error Interrupt Mask */ 6800 #define USB_CNTR_PMAOVRM_Pos (14U) 6801 #define USB_CNTR_PMAOVRM_Msk (0x1UL << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */ 6802 #define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /*!<Packet Memory Area Over / Underrun Interrupt Mask */ 6803 #define USB_CNTR_CTRM_Pos (15U) 6804 #define USB_CNTR_CTRM_Msk (0x1UL << USB_CNTR_CTRM_Pos) /*!< 0x00008000 */ 6805 #define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /*!<Correct Transfer Interrupt Mask */ 6806 6807 /******************* Bit definition for USB_ISTR register *******************/ 6808 #define USB_ISTR_EP_ID_Pos (0U) 6809 #define USB_ISTR_EP_ID_Msk (0xFUL << USB_ISTR_EP_ID_Pos) /*!< 0x0000000F */ 6810 #define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /*!<Endpoint Identifier */ 6811 #define USB_ISTR_DIR_Pos (4U) 6812 #define USB_ISTR_DIR_Msk (0x1UL << USB_ISTR_DIR_Pos) /*!< 0x00000010 */ 6813 #define USB_ISTR_DIR USB_ISTR_DIR_Msk /*!<Direction of transaction */ 6814 #define USB_ISTR_ESOF_Pos (8U) 6815 #define USB_ISTR_ESOF_Msk (0x1UL << USB_ISTR_ESOF_Pos) /*!< 0x00000100 */ 6816 #define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /*!<Expected Start Of Frame */ 6817 #define USB_ISTR_SOF_Pos (9U) 6818 #define USB_ISTR_SOF_Msk (0x1UL << USB_ISTR_SOF_Pos) /*!< 0x00000200 */ 6819 #define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!<Start Of Frame */ 6820 #define USB_ISTR_RESET_Pos (10U) 6821 #define USB_ISTR_RESET_Msk (0x1UL << USB_ISTR_RESET_Pos) /*!< 0x00000400 */ 6822 #define USB_ISTR_RESET USB_ISTR_RESET_Msk /*!<USB RESET request */ 6823 #define USB_ISTR_SUSP_Pos (11U) 6824 #define USB_ISTR_SUSP_Msk (0x1UL << USB_ISTR_SUSP_Pos) /*!< 0x00000800 */ 6825 #define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!<Suspend mode request */ 6826 #define USB_ISTR_WKUP_Pos (12U) 6827 #define USB_ISTR_WKUP_Msk (0x1UL << USB_ISTR_WKUP_Pos) /*!< 0x00001000 */ 6828 #define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!<Wake up */ 6829 #define USB_ISTR_ERR_Pos (13U) 6830 #define USB_ISTR_ERR_Msk (0x1UL << USB_ISTR_ERR_Pos) /*!< 0x00002000 */ 6831 #define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!<Error */ 6832 #define USB_ISTR_PMAOVR_Pos (14U) 6833 #define USB_ISTR_PMAOVR_Msk (0x1UL << USB_ISTR_PMAOVR_Pos) /*!< 0x00004000 */ 6834 #define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /*!<Packet Memory Area Over / Underrun */ 6835 #define USB_ISTR_CTR_Pos (15U) 6836 #define USB_ISTR_CTR_Msk (0x1UL << USB_ISTR_CTR_Pos) /*!< 0x00008000 */ 6837 #define USB_ISTR_CTR USB_ISTR_CTR_Msk /*!<Correct Transfer */ 6838 6839 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */ 6840 #define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/ 6841 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */ 6842 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */ 6843 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */ 6844 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */ 6845 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */ 6846 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */ 6847 6848 6849 /******************* Bit definition for USB_FNR register ********************/ 6850 #define USB_FNR_FN_Pos (0U) 6851 #define USB_FNR_FN_Msk (0x7FFUL << USB_FNR_FN_Pos) /*!< 0x000007FF */ 6852 #define USB_FNR_FN USB_FNR_FN_Msk /*!<Frame Number */ 6853 #define USB_FNR_LSOF_Pos (11U) 6854 #define USB_FNR_LSOF_Msk (0x3UL << USB_FNR_LSOF_Pos) /*!< 0x00001800 */ 6855 #define USB_FNR_LSOF USB_FNR_LSOF_Msk /*!<Lost SOF */ 6856 #define USB_FNR_LCK_Pos (13U) 6857 #define USB_FNR_LCK_Msk (0x1UL << USB_FNR_LCK_Pos) /*!< 0x00002000 */ 6858 #define USB_FNR_LCK USB_FNR_LCK_Msk /*!<Locked */ 6859 #define USB_FNR_RXDM_Pos (14U) 6860 #define USB_FNR_RXDM_Msk (0x1UL << USB_FNR_RXDM_Pos) /*!< 0x00004000 */ 6861 #define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!<Receive Data - Line Status */ 6862 #define USB_FNR_RXDP_Pos (15U) 6863 #define USB_FNR_RXDP_Msk (0x1UL << USB_FNR_RXDP_Pos) /*!< 0x00008000 */ 6864 #define USB_FNR_RXDP USB_FNR_RXDP_Msk /*!<Receive Data + Line Status */ 6865 6866 /****************** Bit definition for USB_DADDR register *******************/ 6867 #define USB_DADDR_ADD_Pos (0U) 6868 #define USB_DADDR_ADD_Msk (0x7FUL << USB_DADDR_ADD_Pos) /*!< 0x0000007F */ 6869 #define USB_DADDR_ADD USB_DADDR_ADD_Msk /*!<ADD[6:0] bits (Device Address) */ 6870 #define USB_DADDR_ADD0_Pos (0U) 6871 #define USB_DADDR_ADD0_Msk (0x1UL << USB_DADDR_ADD0_Pos) /*!< 0x00000001 */ 6872 #define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /*!<Bit 0 */ 6873 #define USB_DADDR_ADD1_Pos (1U) 6874 #define USB_DADDR_ADD1_Msk (0x1UL << USB_DADDR_ADD1_Pos) /*!< 0x00000002 */ 6875 #define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /*!<Bit 1 */ 6876 #define USB_DADDR_ADD2_Pos (2U) 6877 #define USB_DADDR_ADD2_Msk (0x1UL << USB_DADDR_ADD2_Pos) /*!< 0x00000004 */ 6878 #define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /*!<Bit 2 */ 6879 #define USB_DADDR_ADD3_Pos (3U) 6880 #define USB_DADDR_ADD3_Msk (0x1UL << USB_DADDR_ADD3_Pos) /*!< 0x00000008 */ 6881 #define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /*!<Bit 3 */ 6882 #define USB_DADDR_ADD4_Pos (4U) 6883 #define USB_DADDR_ADD4_Msk (0x1UL << USB_DADDR_ADD4_Pos) /*!< 0x00000010 */ 6884 #define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /*!<Bit 4 */ 6885 #define USB_DADDR_ADD5_Pos (5U) 6886 #define USB_DADDR_ADD5_Msk (0x1UL << USB_DADDR_ADD5_Pos) /*!< 0x00000020 */ 6887 #define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /*!<Bit 5 */ 6888 #define USB_DADDR_ADD6_Pos (6U) 6889 #define USB_DADDR_ADD6_Msk (0x1UL << USB_DADDR_ADD6_Pos) /*!< 0x00000040 */ 6890 #define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /*!<Bit 6 */ 6891 6892 #define USB_DADDR_EF_Pos (7U) 6893 #define USB_DADDR_EF_Msk (0x1UL << USB_DADDR_EF_Pos) /*!< 0x00000080 */ 6894 #define USB_DADDR_EF USB_DADDR_EF_Msk /*!<Enable Function */ 6895 6896 /****************** Bit definition for USB_BTABLE register ******************/ 6897 #define USB_BTABLE_BTABLE_Pos (3U) 6898 #define USB_BTABLE_BTABLE_Msk (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */ 6899 #define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /*!<Buffer Table */ 6900 6901 /*!< Buffer descriptor table */ 6902 /***************** Bit definition for USB_ADDR0_TX register *****************/ 6903 #define USB_ADDR0_TX_ADDR0_TX_Pos (1U) 6904 #define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */ 6905 #define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */ 6906 6907 /***************** Bit definition for USB_ADDR1_TX register *****************/ 6908 #define USB_ADDR1_TX_ADDR1_TX_Pos (1U) 6909 #define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */ 6910 #define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */ 6911 6912 /***************** Bit definition for USB_ADDR2_TX register *****************/ 6913 #define USB_ADDR2_TX_ADDR2_TX_Pos (1U) 6914 #define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */ 6915 #define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */ 6916 6917 /***************** Bit definition for USB_ADDR3_TX register *****************/ 6918 #define USB_ADDR3_TX_ADDR3_TX_Pos (1U) 6919 #define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */ 6920 #define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */ 6921 6922 /***************** Bit definition for USB_ADDR4_TX register *****************/ 6923 #define USB_ADDR4_TX_ADDR4_TX_Pos (1U) 6924 #define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */ 6925 #define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */ 6926 6927 /***************** Bit definition for USB_ADDR5_TX register *****************/ 6928 #define USB_ADDR5_TX_ADDR5_TX_Pos (1U) 6929 #define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */ 6930 #define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */ 6931 6932 /***************** Bit definition for USB_ADDR6_TX register *****************/ 6933 #define USB_ADDR6_TX_ADDR6_TX_Pos (1U) 6934 #define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */ 6935 #define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */ 6936 6937 /***************** Bit definition for USB_ADDR7_TX register *****************/ 6938 #define USB_ADDR7_TX_ADDR7_TX_Pos (1U) 6939 #define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */ 6940 #define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */ 6941 6942 /*----------------------------------------------------------------------------*/ 6943 6944 /***************** Bit definition for USB_COUNT0_TX register ****************/ 6945 #define USB_COUNT0_TX_COUNT0_TX_Pos (0U) 6946 #define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */ 6947 #define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */ 6948 6949 /***************** Bit definition for USB_COUNT1_TX register ****************/ 6950 #define USB_COUNT1_TX_COUNT1_TX_Pos (0U) 6951 #define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */ 6952 #define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */ 6953 6954 /***************** Bit definition for USB_COUNT2_TX register ****************/ 6955 #define USB_COUNT2_TX_COUNT2_TX_Pos (0U) 6956 #define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */ 6957 #define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */ 6958 6959 /***************** Bit definition for USB_COUNT3_TX register ****************/ 6960 #define USB_COUNT3_TX_COUNT3_TX_Pos (0U) 6961 #define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */ 6962 #define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */ 6963 6964 /***************** Bit definition for USB_COUNT4_TX register ****************/ 6965 #define USB_COUNT4_TX_COUNT4_TX_Pos (0U) 6966 #define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */ 6967 #define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */ 6968 6969 /***************** Bit definition for USB_COUNT5_TX register ****************/ 6970 #define USB_COUNT5_TX_COUNT5_TX_Pos (0U) 6971 #define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */ 6972 #define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */ 6973 6974 /***************** Bit definition for USB_COUNT6_TX register ****************/ 6975 #define USB_COUNT6_TX_COUNT6_TX_Pos (0U) 6976 #define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */ 6977 #define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */ 6978 6979 /***************** Bit definition for USB_COUNT7_TX register ****************/ 6980 #define USB_COUNT7_TX_COUNT7_TX_Pos (0U) 6981 #define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */ 6982 #define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */ 6983 6984 /*----------------------------------------------------------------------------*/ 6985 6986 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/ 6987 #define USB_COUNT0_TX_0_COUNT0_TX_0 (0x000003FFU) /*!< Transmission Byte Count 0 (low) */ 6988 6989 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/ 6990 #define USB_COUNT0_TX_1_COUNT0_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 0 (high) */ 6991 6992 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/ 6993 #define USB_COUNT1_TX_0_COUNT1_TX_0 (0x000003FFU) /*!< Transmission Byte Count 1 (low) */ 6994 6995 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/ 6996 #define USB_COUNT1_TX_1_COUNT1_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 1 (high) */ 6997 6998 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/ 6999 #define USB_COUNT2_TX_0_COUNT2_TX_0 (0x000003FFU) /*!< Transmission Byte Count 2 (low) */ 7000 7001 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/ 7002 #define USB_COUNT2_TX_1_COUNT2_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 2 (high) */ 7003 7004 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/ 7005 #define USB_COUNT3_TX_0_COUNT3_TX_0 (0x000003FFU) /*!< Transmission Byte Count 3 (low) */ 7006 7007 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/ 7008 #define USB_COUNT3_TX_1_COUNT3_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 3 (high) */ 7009 7010 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/ 7011 #define USB_COUNT4_TX_0_COUNT4_TX_0 (0x000003FFU) /*!< Transmission Byte Count 4 (low) */ 7012 7013 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/ 7014 #define USB_COUNT4_TX_1_COUNT4_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 4 (high) */ 7015 7016 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/ 7017 #define USB_COUNT5_TX_0_COUNT5_TX_0 (0x000003FFU) /*!< Transmission Byte Count 5 (low) */ 7018 7019 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/ 7020 #define USB_COUNT5_TX_1_COUNT5_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 5 (high) */ 7021 7022 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/ 7023 #define USB_COUNT6_TX_0_COUNT6_TX_0 (0x000003FFU) /*!< Transmission Byte Count 6 (low) */ 7024 7025 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/ 7026 #define USB_COUNT6_TX_1_COUNT6_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 6 (high) */ 7027 7028 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/ 7029 #define USB_COUNT7_TX_0_COUNT7_TX_0 (0x000003FFU) /*!< Transmission Byte Count 7 (low) */ 7030 7031 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/ 7032 #define USB_COUNT7_TX_1_COUNT7_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 7 (high) */ 7033 7034 /*----------------------------------------------------------------------------*/ 7035 7036 /***************** Bit definition for USB_ADDR0_RX register *****************/ 7037 #define USB_ADDR0_RX_ADDR0_RX_Pos (1U) 7038 #define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */ 7039 #define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */ 7040 7041 /***************** Bit definition for USB_ADDR1_RX register *****************/ 7042 #define USB_ADDR1_RX_ADDR1_RX_Pos (1U) 7043 #define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */ 7044 #define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */ 7045 7046 /***************** Bit definition for USB_ADDR2_RX register *****************/ 7047 #define USB_ADDR2_RX_ADDR2_RX_Pos (1U) 7048 #define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */ 7049 #define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */ 7050 7051 /***************** Bit definition for USB_ADDR3_RX register *****************/ 7052 #define USB_ADDR3_RX_ADDR3_RX_Pos (1U) 7053 #define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */ 7054 #define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */ 7055 7056 /***************** Bit definition for USB_ADDR4_RX register *****************/ 7057 #define USB_ADDR4_RX_ADDR4_RX_Pos (1U) 7058 #define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */ 7059 #define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */ 7060 7061 /***************** Bit definition for USB_ADDR5_RX register *****************/ 7062 #define USB_ADDR5_RX_ADDR5_RX_Pos (1U) 7063 #define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */ 7064 #define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */ 7065 7066 /***************** Bit definition for USB_ADDR6_RX register *****************/ 7067 #define USB_ADDR6_RX_ADDR6_RX_Pos (1U) 7068 #define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */ 7069 #define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */ 7070 7071 /***************** Bit definition for USB_ADDR7_RX register *****************/ 7072 #define USB_ADDR7_RX_ADDR7_RX_Pos (1U) 7073 #define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */ 7074 #define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */ 7075 7076 /*----------------------------------------------------------------------------*/ 7077 7078 /***************** Bit definition for USB_COUNT0_RX register ****************/ 7079 #define USB_COUNT0_RX_COUNT0_RX_Pos (0U) 7080 #define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */ 7081 #define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */ 7082 7083 #define USB_COUNT0_RX_NUM_BLOCK_Pos (10U) 7084 #define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 7085 #define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 7086 #define USB_COUNT0_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 7087 #define USB_COUNT0_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 7088 #define USB_COUNT0_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 7089 #define USB_COUNT0_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 7090 #define USB_COUNT0_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 7091 7092 #define USB_COUNT0_RX_BLSIZE_Pos (15U) 7093 #define USB_COUNT0_RX_BLSIZE_Msk (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */ 7094 #define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */ 7095 7096 /***************** Bit definition for USB_COUNT1_RX register ****************/ 7097 #define USB_COUNT1_RX_COUNT1_RX_Pos (0U) 7098 #define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */ 7099 #define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */ 7100 7101 #define USB_COUNT1_RX_NUM_BLOCK_Pos (10U) 7102 #define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 7103 #define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 7104 #define USB_COUNT1_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 7105 #define USB_COUNT1_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 7106 #define USB_COUNT1_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 7107 #define USB_COUNT1_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 7108 #define USB_COUNT1_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 7109 7110 #define USB_COUNT1_RX_BLSIZE_Pos (15U) 7111 #define USB_COUNT1_RX_BLSIZE_Msk (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */ 7112 #define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */ 7113 7114 /***************** Bit definition for USB_COUNT2_RX register ****************/ 7115 #define USB_COUNT2_RX_COUNT2_RX_Pos (0U) 7116 #define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */ 7117 #define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */ 7118 7119 #define USB_COUNT2_RX_NUM_BLOCK_Pos (10U) 7120 #define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 7121 #define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 7122 #define USB_COUNT2_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 7123 #define USB_COUNT2_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 7124 #define USB_COUNT2_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 7125 #define USB_COUNT2_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 7126 #define USB_COUNT2_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 7127 7128 #define USB_COUNT2_RX_BLSIZE_Pos (15U) 7129 #define USB_COUNT2_RX_BLSIZE_Msk (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */ 7130 #define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */ 7131 7132 /***************** Bit definition for USB_COUNT3_RX register ****************/ 7133 #define USB_COUNT3_RX_COUNT3_RX_Pos (0U) 7134 #define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */ 7135 #define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */ 7136 7137 #define USB_COUNT3_RX_NUM_BLOCK_Pos (10U) 7138 #define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 7139 #define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 7140 #define USB_COUNT3_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 7141 #define USB_COUNT3_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 7142 #define USB_COUNT3_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 7143 #define USB_COUNT3_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 7144 #define USB_COUNT3_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 7145 7146 #define USB_COUNT3_RX_BLSIZE_Pos (15U) 7147 #define USB_COUNT3_RX_BLSIZE_Msk (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */ 7148 #define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */ 7149 7150 /***************** Bit definition for USB_COUNT4_RX register ****************/ 7151 #define USB_COUNT4_RX_COUNT4_RX_Pos (0U) 7152 #define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */ 7153 #define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */ 7154 7155 #define USB_COUNT4_RX_NUM_BLOCK_Pos (10U) 7156 #define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 7157 #define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 7158 #define USB_COUNT4_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 7159 #define USB_COUNT4_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 7160 #define USB_COUNT4_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 7161 #define USB_COUNT4_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 7162 #define USB_COUNT4_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 7163 7164 #define USB_COUNT4_RX_BLSIZE_Pos (15U) 7165 #define USB_COUNT4_RX_BLSIZE_Msk (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */ 7166 #define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */ 7167 7168 /***************** Bit definition for USB_COUNT5_RX register ****************/ 7169 #define USB_COUNT5_RX_COUNT5_RX_Pos (0U) 7170 #define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */ 7171 #define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */ 7172 7173 #define USB_COUNT5_RX_NUM_BLOCK_Pos (10U) 7174 #define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 7175 #define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 7176 #define USB_COUNT5_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 7177 #define USB_COUNT5_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 7178 #define USB_COUNT5_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 7179 #define USB_COUNT5_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 7180 #define USB_COUNT5_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 7181 7182 #define USB_COUNT5_RX_BLSIZE_Pos (15U) 7183 #define USB_COUNT5_RX_BLSIZE_Msk (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */ 7184 #define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */ 7185 7186 /***************** Bit definition for USB_COUNT6_RX register ****************/ 7187 #define USB_COUNT6_RX_COUNT6_RX_Pos (0U) 7188 #define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */ 7189 #define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */ 7190 7191 #define USB_COUNT6_RX_NUM_BLOCK_Pos (10U) 7192 #define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 7193 #define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 7194 #define USB_COUNT6_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 7195 #define USB_COUNT6_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 7196 #define USB_COUNT6_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 7197 #define USB_COUNT6_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 7198 #define USB_COUNT6_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 7199 7200 #define USB_COUNT6_RX_BLSIZE_Pos (15U) 7201 #define USB_COUNT6_RX_BLSIZE_Msk (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */ 7202 #define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */ 7203 7204 /***************** Bit definition for USB_COUNT7_RX register ****************/ 7205 #define USB_COUNT7_RX_COUNT7_RX_Pos (0U) 7206 #define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */ 7207 #define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */ 7208 7209 #define USB_COUNT7_RX_NUM_BLOCK_Pos (10U) 7210 #define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 7211 #define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 7212 #define USB_COUNT7_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 7213 #define USB_COUNT7_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 7214 #define USB_COUNT7_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 7215 #define USB_COUNT7_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 7216 #define USB_COUNT7_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 7217 7218 #define USB_COUNT7_RX_BLSIZE_Pos (15U) 7219 #define USB_COUNT7_RX_BLSIZE_Msk (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */ 7220 #define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */ 7221 7222 /*----------------------------------------------------------------------------*/ 7223 7224 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/ 7225 #define USB_COUNT0_RX_0_COUNT0_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 7226 7227 #define USB_COUNT0_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 7228 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 7229 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 7230 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 7231 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 7232 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 7233 7234 #define USB_COUNT0_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 7235 7236 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/ 7237 #define USB_COUNT0_RX_1_COUNT0_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 7238 7239 #define USB_COUNT0_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 7240 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 1 */ 7241 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 7242 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 7243 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 7244 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 7245 7246 #define USB_COUNT0_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 7247 7248 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/ 7249 #define USB_COUNT1_RX_0_COUNT1_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 7250 7251 #define USB_COUNT1_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 7252 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 7253 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 7254 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 7255 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 7256 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 7257 7258 #define USB_COUNT1_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 7259 7260 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/ 7261 #define USB_COUNT1_RX_1_COUNT1_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 7262 7263 #define USB_COUNT1_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 7264 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 7265 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 7266 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 7267 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 7268 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 7269 7270 #define USB_COUNT1_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 7271 7272 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/ 7273 #define USB_COUNT2_RX_0_COUNT2_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 7274 7275 #define USB_COUNT2_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 7276 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 7277 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 7278 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 7279 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 7280 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 7281 7282 #define USB_COUNT2_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 7283 7284 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/ 7285 #define USB_COUNT2_RX_1_COUNT2_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 7286 7287 #define USB_COUNT2_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 7288 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 7289 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 7290 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 7291 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 7292 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 7293 7294 #define USB_COUNT2_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 7295 7296 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/ 7297 #define USB_COUNT3_RX_0_COUNT3_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 7298 7299 #define USB_COUNT3_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 7300 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 7301 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 7302 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 7303 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 7304 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 7305 7306 #define USB_COUNT3_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 7307 7308 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/ 7309 #define USB_COUNT3_RX_1_COUNT3_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 7310 7311 #define USB_COUNT3_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 7312 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 7313 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 7314 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 7315 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 7316 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 7317 7318 #define USB_COUNT3_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 7319 7320 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/ 7321 #define USB_COUNT4_RX_0_COUNT4_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 7322 7323 #define USB_COUNT4_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 7324 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 7325 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 7326 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 7327 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 7328 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 7329 7330 #define USB_COUNT4_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 7331 7332 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/ 7333 #define USB_COUNT4_RX_1_COUNT4_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 7334 7335 #define USB_COUNT4_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 7336 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 7337 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 7338 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 7339 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 7340 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 7341 7342 #define USB_COUNT4_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 7343 7344 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/ 7345 #define USB_COUNT5_RX_0_COUNT5_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 7346 7347 #define USB_COUNT5_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 7348 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 7349 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 7350 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 7351 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 7352 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 7353 7354 #define USB_COUNT5_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 7355 7356 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/ 7357 #define USB_COUNT5_RX_1_COUNT5_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 7358 7359 #define USB_COUNT5_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 7360 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 7361 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 7362 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 7363 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 7364 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 7365 7366 #define USB_COUNT5_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 7367 7368 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/ 7369 #define USB_COUNT6_RX_0_COUNT6_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 7370 7371 #define USB_COUNT6_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 7372 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 7373 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 7374 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 7375 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 7376 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 7377 7378 #define USB_COUNT6_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 7379 7380 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/ 7381 #define USB_COUNT6_RX_1_COUNT6_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 7382 7383 #define USB_COUNT6_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 7384 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 7385 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 7386 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 7387 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 7388 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 7389 7390 #define USB_COUNT6_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 7391 7392 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/ 7393 #define USB_COUNT7_RX_0_COUNT7_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 7394 7395 #define USB_COUNT7_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 7396 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 7397 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 7398 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 7399 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 7400 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 7401 7402 #define USB_COUNT7_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 7403 7404 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/ 7405 #define USB_COUNT7_RX_1_COUNT7_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 7406 7407 #define USB_COUNT7_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 7408 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 7409 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 7410 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 7411 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 7412 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 7413 7414 #define USB_COUNT7_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 7415 7416 /******************************************************************************/ 7417 /* */ 7418 /* Window WATCHDOG (WWDG) */ 7419 /* */ 7420 /******************************************************************************/ 7421 7422 /******************* Bit definition for WWDG_CR register ********************/ 7423 #define WWDG_CR_T_Pos (0U) 7424 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */ 7425 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ 7426 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */ 7427 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */ 7428 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */ 7429 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */ 7430 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */ 7431 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */ 7432 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */ 7433 7434 /* Legacy defines */ 7435 #define WWDG_CR_T0 WWDG_CR_T_0 7436 #define WWDG_CR_T1 WWDG_CR_T_1 7437 #define WWDG_CR_T2 WWDG_CR_T_2 7438 #define WWDG_CR_T3 WWDG_CR_T_3 7439 #define WWDG_CR_T4 WWDG_CR_T_4 7440 #define WWDG_CR_T5 WWDG_CR_T_5 7441 #define WWDG_CR_T6 WWDG_CR_T_6 7442 7443 #define WWDG_CR_WDGA_Pos (7U) 7444 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ 7445 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */ 7446 7447 /******************* Bit definition for WWDG_CFR register *******************/ 7448 #define WWDG_CFR_W_Pos (0U) 7449 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */ 7450 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */ 7451 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */ 7452 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */ 7453 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */ 7454 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */ 7455 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */ 7456 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */ 7457 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */ 7458 7459 /* Legacy defines */ 7460 #define WWDG_CFR_W0 WWDG_CFR_W_0 7461 #define WWDG_CFR_W1 WWDG_CFR_W_1 7462 #define WWDG_CFR_W2 WWDG_CFR_W_2 7463 #define WWDG_CFR_W3 WWDG_CFR_W_3 7464 #define WWDG_CFR_W4 WWDG_CFR_W_4 7465 #define WWDG_CFR_W5 WWDG_CFR_W_5 7466 #define WWDG_CFR_W6 WWDG_CFR_W_6 7467 7468 #define WWDG_CFR_WDGTB_Pos (7U) 7469 #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */ 7470 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */ 7471 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */ 7472 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */ 7473 7474 /* Legacy defines */ 7475 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 7476 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 7477 7478 #define WWDG_CFR_EWI_Pos (9U) 7479 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ 7480 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */ 7481 7482 /******************* Bit definition for WWDG_SR register ********************/ 7483 #define WWDG_SR_EWIF_Pos (0U) 7484 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ 7485 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ 7486 7487 /** 7488 * @} 7489 */ 7490 /** @addtogroup Exported_macro 7491 * @{ 7492 */ 7493 7494 /****************************** ADC Instances *********************************/ 7495 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) 7496 7497 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON) 7498 7499 /******************************** COMP Instances ******************************/ 7500 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \ 7501 ((INSTANCE) == COMP2)) 7502 7503 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON) 7504 7505 /****************************** CRC Instances *********************************/ 7506 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) 7507 7508 /****************************** DAC Instances *********************************/ 7509 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC) 7510 7511 /****************************** DMA Instances *********************************/ 7512 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ 7513 ((INSTANCE) == DMA1_Channel2) || \ 7514 ((INSTANCE) == DMA1_Channel3) || \ 7515 ((INSTANCE) == DMA1_Channel4) || \ 7516 ((INSTANCE) == DMA1_Channel5) || \ 7517 ((INSTANCE) == DMA1_Channel6) || \ 7518 ((INSTANCE) == DMA1_Channel7)) 7519 7520 /******************************* GPIO Instances *******************************/ 7521 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 7522 ((INSTANCE) == GPIOB) || \ 7523 ((INSTANCE) == GPIOC) || \ 7524 ((INSTANCE) == GPIOD) || \ 7525 ((INSTANCE) == GPIOE) || \ 7526 ((INSTANCE) == GPIOH)) 7527 7528 /**************************** GPIO Alternate Function Instances ***************/ 7529 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) 7530 7531 /**************************** GPIO Lock Instances *****************************/ 7532 /* On L1, all GPIO Bank support the Lock mechanism */ 7533 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) 7534 7535 /******************************** I2C Instances *******************************/ 7536 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ 7537 ((INSTANCE) == I2C2)) 7538 7539 /****************************** SMBUS Instances *******************************/ 7540 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) 7541 7542 /****************************** IWDG Instances ********************************/ 7543 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) 7544 7545 /****************************** RTC Instances *********************************/ 7546 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) 7547 7548 /******************************** SPI Instances *******************************/ 7549 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ 7550 ((INSTANCE) == SPI2)) 7551 7552 /****************************** TIM Instances *********************************/ 7553 7554 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 7555 ((INSTANCE) == TIM3) || \ 7556 ((INSTANCE) == TIM4) || \ 7557 ((INSTANCE) == TIM6) || \ 7558 ((INSTANCE) == TIM7) || \ 7559 ((INSTANCE) == TIM9) || \ 7560 ((INSTANCE) == TIM10) || \ 7561 ((INSTANCE) == TIM11)) 7562 7563 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 7564 ((INSTANCE) == TIM3) || \ 7565 ((INSTANCE) == TIM4) || \ 7566 ((INSTANCE) == TIM9) || \ 7567 ((INSTANCE) == TIM10) || \ 7568 ((INSTANCE) == TIM11)) 7569 7570 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 7571 ((INSTANCE) == TIM3) || \ 7572 ((INSTANCE) == TIM4) || \ 7573 ((INSTANCE) == TIM9)) 7574 7575 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 7576 ((INSTANCE) == TIM3) || \ 7577 ((INSTANCE) == TIM4)) 7578 7579 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 7580 ((INSTANCE) == TIM3) || \ 7581 ((INSTANCE) == TIM4)) 7582 7583 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 7584 ((INSTANCE) == TIM3) || \ 7585 ((INSTANCE) == TIM4) || \ 7586 ((INSTANCE) == TIM9)) 7587 7588 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 7589 ((INSTANCE) == TIM3) || \ 7590 ((INSTANCE) == TIM4) || \ 7591 ((INSTANCE) == TIM9) || \ 7592 ((INSTANCE) == TIM10) || \ 7593 ((INSTANCE) == TIM11)) 7594 7595 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 7596 ((INSTANCE) == TIM3) || \ 7597 ((INSTANCE) == TIM4) || \ 7598 ((INSTANCE) == TIM9)) 7599 7600 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 7601 ((INSTANCE) == TIM3) || \ 7602 ((INSTANCE) == TIM4) || \ 7603 ((INSTANCE) == TIM9)) 7604 7605 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 7606 ((INSTANCE) == TIM3) || \ 7607 ((INSTANCE) == TIM4)) 7608 7609 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 7610 ((INSTANCE) == TIM3) || \ 7611 ((INSTANCE) == TIM4)) 7612 7613 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 7614 ((INSTANCE) == TIM3) || \ 7615 ((INSTANCE) == TIM4) || \ 7616 ((INSTANCE) == TIM6) || \ 7617 ((INSTANCE) == TIM7) || \ 7618 ((INSTANCE) == TIM9)) 7619 7620 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 7621 ((INSTANCE) == TIM3) || \ 7622 ((INSTANCE) == TIM4) || \ 7623 ((INSTANCE) == TIM9)) 7624 7625 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (0) 7626 7627 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 7628 ((INSTANCE) == TIM3) || \ 7629 ((INSTANCE) == TIM4)) 7630 7631 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ 7632 ((((INSTANCE) == TIM2) && \ 7633 (((CHANNEL) == TIM_CHANNEL_1) || \ 7634 ((CHANNEL) == TIM_CHANNEL_2) || \ 7635 ((CHANNEL) == TIM_CHANNEL_3) || \ 7636 ((CHANNEL) == TIM_CHANNEL_4))) \ 7637 || \ 7638 (((INSTANCE) == TIM3) && \ 7639 (((CHANNEL) == TIM_CHANNEL_1) || \ 7640 ((CHANNEL) == TIM_CHANNEL_2) || \ 7641 ((CHANNEL) == TIM_CHANNEL_3) || \ 7642 ((CHANNEL) == TIM_CHANNEL_4))) \ 7643 || \ 7644 (((INSTANCE) == TIM4) && \ 7645 (((CHANNEL) == TIM_CHANNEL_1) || \ 7646 ((CHANNEL) == TIM_CHANNEL_2) || \ 7647 ((CHANNEL) == TIM_CHANNEL_3) || \ 7648 ((CHANNEL) == TIM_CHANNEL_4))) \ 7649 || \ 7650 (((INSTANCE) == TIM9) && \ 7651 (((CHANNEL) == TIM_CHANNEL_1) || \ 7652 ((CHANNEL) == TIM_CHANNEL_2))) \ 7653 || \ 7654 (((INSTANCE) == TIM10) && \ 7655 (((CHANNEL) == TIM_CHANNEL_1))) \ 7656 || \ 7657 (((INSTANCE) == TIM11) && \ 7658 (((CHANNEL) == TIM_CHANNEL_1)))) 7659 7660 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 7661 ((INSTANCE) == TIM3) || \ 7662 ((INSTANCE) == TIM4) || \ 7663 ((INSTANCE) == TIM9) || \ 7664 ((INSTANCE) == TIM10) || \ 7665 ((INSTANCE) == TIM11)) 7666 7667 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 7668 ((INSTANCE) == TIM3) || \ 7669 ((INSTANCE) == TIM4) || \ 7670 ((INSTANCE) == TIM6) || \ 7671 ((INSTANCE) == TIM7)) 7672 7673 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 7674 ((INSTANCE) == TIM3) || \ 7675 ((INSTANCE) == TIM4)) 7676 7677 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 7678 ((INSTANCE) == TIM3) || \ 7679 ((INSTANCE) == TIM4)) 7680 7681 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 7682 ((INSTANCE) == TIM3) || \ 7683 ((INSTANCE) == TIM4)) 7684 7685 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM9) || \ 7686 ((INSTANCE) == TIM10) || \ 7687 ((INSTANCE) == TIM11)) 7688 7689 /******************** USART Instances : Synchronous mode **********************/ 7690 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 7691 ((INSTANCE) == USART2) || \ 7692 ((INSTANCE) == USART3)) 7693 7694 /******************** UART Instances : Asynchronous mode **********************/ 7695 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 7696 ((INSTANCE) == USART2) || \ 7697 ((INSTANCE) == USART3)) 7698 7699 /******************** UART Instances : Half-Duplex mode **********************/ 7700 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 7701 ((INSTANCE) == USART2) || \ 7702 ((INSTANCE) == USART3)) 7703 7704 /******************** UART Instances : LIN mode **********************/ 7705 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 7706 ((INSTANCE) == USART2) || \ 7707 ((INSTANCE) == USART3)) 7708 7709 /****************** UART Instances : Hardware Flow control ********************/ 7710 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 7711 ((INSTANCE) == USART2) || \ 7712 ((INSTANCE) == USART3)) 7713 7714 /********************* UART Instances : Smard card mode ***********************/ 7715 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 7716 ((INSTANCE) == USART2) || \ 7717 ((INSTANCE) == USART3)) 7718 7719 /*********************** UART Instances : IRDA mode ***************************/ 7720 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 7721 ((INSTANCE) == USART2) || \ 7722 ((INSTANCE) == USART3)) 7723 7724 /***************** UART Instances : Multi-Processor mode **********************/ 7725 #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 7726 ((INSTANCE) == USART2) || \ 7727 ((INSTANCE) == USART3)) 7728 7729 /****************************** WWDG Instances ********************************/ 7730 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) 7731 7732 7733 /****************************** LCD Instances ********************************/ 7734 #define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD) 7735 7736 /****************************** USB Instances ********************************/ 7737 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) 7738 #define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE 7739 7740 /** 7741 * @} 7742 */ 7743 7744 /******************************************************************************/ 7745 /* For a painless codes migration between the STM32L1xx device product */ 7746 /* lines, the aliases defined below are put in place to overcome the */ 7747 /* differences in the interrupt handlers and IRQn definitions. */ 7748 /* No need to update developed interrupt code when moving across */ 7749 /* product lines within the same STM32L1 Family */ 7750 /******************************************************************************/ 7751 7752 /* Aliases for __IRQn */ 7753 7754 /* Aliases for __IRQHandler */ 7755 7756 /** 7757 * @} 7758 */ 7759 7760 /** 7761 * @} 7762 */ 7763 7764 #ifdef __cplusplus 7765 } 7766 #endif /* __cplusplus */ 7767 7768 #endif /* __STM32L152xB_H */ 7769 7770 7771 7772 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 7773
