1 /**
2 ******************************************************************************
3 * @file stm32l1xx_hal_cryp.c
4 * @author MCD Application Team
5 * @brief CRYP HAL module driver.
6 *
7 * This file provides firmware functions to manage the following
8 * functionalities of the Cryptography (CRYP) peripheral:
9 * + Initialization and de-initialization functions
10 * + Processing functions by algorithm using polling mode
11 * + Processing functions by algorithm using interrupt mode
12 * + Processing functions by algorithm using DMA mode
13 * + Peripheral State functions
14 *
15 @verbatim
16 ==============================================================================
17 ##### How to use this driver #####
18 ==============================================================================
19 [..]
20 The CRYP HAL driver can be used as follows:
21
22 (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
23 (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
24 (##) In case of using interrupts (e.g. HAL_CRYP_AESECB_Encrypt_IT())
25 (+) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
26 (+) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
27 (+) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
28 (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_AESECB_Encrypt_DMA())
29 (+) Enable the DMA2 interface clock using
30 (++) __HAL_RCC_DMA2_CLK_ENABLE()
31 (+) Configure and enable two DMA Channels one for managing data transfer from
32 memory to peripheral (input channel) and another channel for managing data
33 transfer from peripheral to memory (output channel)
34 (+) Associate the initialized DMA handle to the CRYP DMA handle
35 using __HAL_LINKDMA()
36 (+) Configure the priority and enable the NVIC for the transfer complete
37 interrupt on the two DMA Streams. The output stream should have higher
38 priority than the input stream.
39 (++) HAL_NVIC_SetPriority()
40 (++) HAL_NVIC_EnableIRQ()
41
42 (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:
43 (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit
44 (##) The encryption/decryption key.
45 (##) The initialization vector (counter). It is not used ECB mode.
46
47 (#)Three processing (encryption/decryption) functions are available:
48 (##) Polling mode: encryption and decryption APIs are blocking functions
49 i.e. they process the data and wait till the processing is finished
50 e.g. HAL_CRYP_AESCBC_Encrypt()
51 (##) Interrupt mode: encryption and decryption APIs are not blocking functions
52 i.e. they process the data under interrupt
53 e.g. HAL_CRYP_AESCBC_Encrypt_IT()
54 (##) DMA mode: encryption and decryption APIs are not blocking functions
55 i.e. the data transfer is ensured by DMA
56 e.g. HAL_CRYP_AESCBC_Encrypt_DMA()
57
58 (#)When the processing function is called for the first time after HAL_CRYP_Init()
59 the CRYP peripheral is initialized and processes the buffer in input.
60 At second call, the processing function performs an append of the already
61 processed buffer.
62 When a new data block is to be processed, call HAL_CRYP_Init() then the
63 processing function.
64
65 (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
66
67 @endverbatim
68 ******************************************************************************
69 * @attention
70 *
71 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
72 * All rights reserved.</center></h2>
73 *
74 * This software component is licensed by ST under BSD 3-Clause license,
75 * the "License"; You may not use this file except in compliance with the
76 * License. You may obtain a copy of the License at:
77 * opensource.org/licenses/BSD-3-Clause
78 *
79 ******************************************************************************
80 */
81
82 /* Includes ------------------------------------------------------------------*/
83 #include "stm32l1xx_hal.h"
84
85 #ifdef HAL_CRYP_MODULE_ENABLED
86
87 /** @addtogroup STM32L1xx_HAL_Driver
88 * @{
89 */
90
91 /** @defgroup CRYP CRYP
92 * @brief CRYP HAL module driver.
93 * @{
94 */
95
96 #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) || defined(STM32L162xDX)
97
98 /* Private typedef -----------------------------------------------------------*/
99 /* Private define ------------------------------------------------------------*/
100
101 /** @defgroup CRYP_Private_Defines CRYP Private Defines
102 * @{
103 */
104
105 #define CRYP_ALGO_CHAIN_MASK (AES_CR_MODE | AES_CR_CHMOD)
106
107 /**
108 * @}
109 */
110
111 /* Private macro -------------------------------------------------------------*/
112 /* Private variables ---------------------------------------------------------*/
113 /* Private function prototypes -----------------------------------------------*/
114
115 /** @defgroup CRYP_Private_Functions CRYP Private Functions
116 * @{
117 */
118
119 static HAL_StatusTypeDef CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef *hcryp);
120 static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector);
121 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key);
122 static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);
123 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
124 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
125 static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
126 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
127
128 /**
129 * @}
130 */
131
132 /* Private functions ---------------------------------------------------------*/
133
134 /** @defgroup CRYP_Exported_Functions CRYP Exported Functions
135 * @{
136 */
137
138 /** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
139 * @brief Initialization and Configuration functions.
140 *
141 @verbatim
142 ==============================================================================
143 ##### Initialization and de-initialization functions #####
144 ==============================================================================
145 [..] This section provides functions allowing to:
146 (+) Initialize the CRYP according to the specified parameters
147 in the CRYP_InitTypeDef and creates the associated handle
148 (+) DeInitialize the CRYP peripheral
149 (+) Initialize the CRYP MSP
150 (+) DeInitialize CRYP MSP
151
152 @endverbatim
153 * @{
154 */
155
156 /**
157 * @brief Initializes the CRYP according to the specified
158 * parameters in the CRYP_InitTypeDef and creates the associated handle.
159 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
160 * the configuration information for CRYP module
161 * @retval HAL status
162 */
HAL_CRYP_Init(CRYP_HandleTypeDef * hcryp)163 HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
164 {
165 /* Check the CRYP handle allocation */
166 if(hcryp == NULL)
167 {
168 return HAL_ERROR;
169 }
170
171 /* Check the parameters */
172 assert_param(IS_AES_ALL_INSTANCE(hcryp->Instance));
173 assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
174
175 if(hcryp->State == HAL_CRYP_STATE_RESET)
176 {
177 /* Allocate lock resource and initialize it */
178 hcryp->Lock = HAL_UNLOCKED;
179
180 /* Init the low level hardware */
181 HAL_CRYP_MspInit(hcryp);
182 }
183
184 /* Check if AES already enabled */
185 if (HAL_IS_BIT_CLR(hcryp->Instance->CR, AES_CR_EN))
186 {
187 /* Change the CRYP state */
188 hcryp->State = HAL_CRYP_STATE_BUSY;
189
190 /* Set the data type*/
191 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
192
193 /* Reset CrypInCount and CrypOutCount */
194 hcryp->CrypInCount = 0;
195 hcryp->CrypOutCount = 0;
196
197 /* Change the CRYP state */
198 hcryp->State = HAL_CRYP_STATE_READY;
199
200 /* Set the default CRYP phase */
201 hcryp->Phase = HAL_CRYP_PHASE_READY;
202
203 /* Return function status */
204 return HAL_OK;
205 }
206 else
207 {
208 /* The Datatype selection must be changed if the AES is disabled. Writing these bits while the AES is */
209 /* enabled is forbidden to avoid unpredictable AES behavior.*/
210
211 /* Return function status */
212 return HAL_ERROR;
213 }
214
215 }
216
217 /**
218 * @brief DeInitializes the CRYP peripheral.
219 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
220 * the configuration information for CRYP module
221 * @retval HAL status
222 */
HAL_CRYP_DeInit(CRYP_HandleTypeDef * hcryp)223 HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
224 {
225 /* Check the CRYP handle allocation */
226 if(hcryp == NULL)
227 {
228 return HAL_ERROR;
229 }
230
231 /* Change the CRYP state */
232 hcryp->State = HAL_CRYP_STATE_BUSY;
233
234 /* Set the default CRYP phase */
235 hcryp->Phase = HAL_CRYP_PHASE_READY;
236
237 /* Reset CrypInCount and CrypOutCount */
238 hcryp->CrypInCount = 0;
239 hcryp->CrypOutCount = 0;
240
241 /* Disable the CRYP Peripheral Clock */
242 __HAL_CRYP_DISABLE(hcryp);
243
244 /* DeInit the low level hardware: CLOCK, NVIC.*/
245 HAL_CRYP_MspDeInit(hcryp);
246
247 /* Change the CRYP state */
248 hcryp->State = HAL_CRYP_STATE_RESET;
249
250 /* Release Lock */
251 __HAL_UNLOCK(hcryp);
252
253 /* Return function status */
254 return HAL_OK;
255 }
256
257 /**
258 * @brief Initializes the CRYP MSP.
259 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
260 * the configuration information for CRYP module
261 * @retval None
262 */
HAL_CRYP_MspInit(CRYP_HandleTypeDef * hcryp)263 __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
264 {
265 /* Prevent unused argument(s) compilation warning */
266 UNUSED(hcryp);
267
268 /* NOTE : This function should not be modified; when the callback is needed,
269 the HAL_CRYP_MspInit can be implemented in the user file */
270 }
271
272 /**
273 * @brief DeInitializes CRYP MSP.
274 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
275 * the configuration information for CRYP module
276 * @retval None
277 */
HAL_CRYP_MspDeInit(CRYP_HandleTypeDef * hcryp)278 __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
279 {
280 /* Prevent unused argument(s) compilation warning */
281 UNUSED(hcryp);
282
283 /* NOTE : This function should not be modified; when the callback is needed,
284 the HAL_CRYP_MspDeInit can be implemented in the user file */
285 }
286
287 /**
288 * @}
289 */
290
291 /** @defgroup CRYP_Exported_Functions_Group2 AES processing functions
292 * @brief processing functions.
293 *
294 @verbatim
295 ==============================================================================
296 ##### AES processing functions #####
297 ==============================================================================
298 [..] This section provides functions allowing to:
299 (+) Encrypt plaintext using AES algorithm in different chaining modes
300 (+) Decrypt cyphertext using AES algorithm in different chaining modes
301 [..] Three processing functions are available:
302 (+) Polling mode
303 (+) Interrupt mode
304 (+) DMA mode
305
306 @endverbatim
307 * @{
308 */
309
310 /**
311 * @brief Initializes the CRYP peripheral in AES ECB encryption mode
312 * then encrypt pPlainData. The cypher data are available in pCypherData
313 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
314 * the configuration information for CRYP module
315 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
316 * @param Size Length of the plaintext buffer, must be a multiple of 16.
317 * @param pCypherData Pointer to the cyphertext buffer (aligned on u32)
318 * @param Timeout Specify Timeout value
319 * @retval HAL status
320 */
HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef * hcryp,uint8_t * pPlainData,uint16_t Size,uint8_t * pCypherData,uint32_t Timeout)321 HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
322 {
323 /* Process Locked */
324 __HAL_LOCK(hcryp);
325
326 /* Check that data aligned on u32 and Size multiple of 16*/
327 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
328 {
329 /* Process Locked */
330 __HAL_UNLOCK(hcryp);
331
332 /* Return function status */
333 return HAL_ERROR;
334 }
335
336 /* Check if HAL_CRYP_Init has been called */
337 if(hcryp->State != HAL_CRYP_STATE_RESET)
338 {
339 /* Change the CRYP state */
340 hcryp->State = HAL_CRYP_STATE_BUSY;
341
342 /* Check if initialization phase has already been performed */
343 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
344 {
345 /* Set the key */
346 CRYP_SetKey(hcryp, hcryp->Init.pKey);
347
348 /* Reset the CHMOD & MODE bits */
349 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
350
351 /* Set the CRYP peripheral in AES ECB mode */
352 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT);
353
354 /* Enable CRYP */
355 __HAL_CRYP_ENABLE(hcryp);
356
357 /* Set the phase */
358 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
359 }
360
361 /* Write Plain Data and Get Cypher Data */
362 if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
363 {
364 return HAL_TIMEOUT;
365 }
366
367 /* Change the CRYP state */
368 hcryp->State = HAL_CRYP_STATE_READY;
369
370 /* Process Unlocked */
371 __HAL_UNLOCK(hcryp);
372
373 /* Return function status */
374 return HAL_OK;
375 }
376 else
377 {
378 /* Process Locked */
379 __HAL_UNLOCK(hcryp);
380
381 /* Return function status */
382 return HAL_ERROR;
383 }
384 }
385
386 /**
387 * @brief Initializes the CRYP peripheral in AES CBC encryption mode
388 * then encrypt pPlainData. The cypher data are available in pCypherData
389 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
390 * the configuration information for CRYP module
391 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
392 * @param Size Length of the plaintext buffer, must be a multiple of 16.
393 * @param pCypherData Pointer to the cyphertext buffer (aligned on u32)
394 * @param Timeout Specify Timeout value
395 * @retval HAL status
396 */
HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef * hcryp,uint8_t * pPlainData,uint16_t Size,uint8_t * pCypherData,uint32_t Timeout)397 HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
398 {
399 /* Process Locked */
400 __HAL_LOCK(hcryp);
401
402 /* Check that data aligned on u32 */
403 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
404 {
405 /* Process Locked */
406 __HAL_UNLOCK(hcryp);
407
408 /* Return function status */
409 return HAL_ERROR;
410 }
411
412 /* Check if HAL_CRYP_Init has been called */
413 if(hcryp->State != HAL_CRYP_STATE_RESET)
414 {
415 /* Change the CRYP state */
416 hcryp->State = HAL_CRYP_STATE_BUSY;
417
418 /* Check if initialization phase has already been performed */
419 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
420 {
421 /* Set the key */
422 CRYP_SetKey(hcryp, hcryp->Init.pKey);
423
424 /* Reset the CHMOD & MODE bits */
425 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
426
427 /* Set the CRYP peripheral in AES CBC mode */
428 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT);
429
430 /* Set the Initialization Vector */
431 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
432
433 /* Enable CRYP */
434 __HAL_CRYP_ENABLE(hcryp);
435
436 /* Set the phase */
437 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
438 }
439
440 /* Write Plain Data and Get Cypher Data */
441 if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
442 {
443 return HAL_TIMEOUT;
444 }
445
446 /* Change the CRYP state */
447 hcryp->State = HAL_CRYP_STATE_READY;
448
449 /* Process Unlocked */
450 __HAL_UNLOCK(hcryp);
451
452 /* Return function status */
453 return HAL_OK;
454 }
455 else
456 {
457 /* Process Locked */
458 __HAL_UNLOCK(hcryp);
459
460 /* Return function status */
461 return HAL_ERROR;
462 }
463 }
464
465 /**
466 * @brief Initializes the CRYP peripheral in AES CTR encryption mode
467 * then encrypt pPlainData. The cypher data are available in pCypherData
468 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
469 * the configuration information for CRYP module
470 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
471 * @param Size Length of the plaintext buffer, must be a multiple of 16.
472 * @param pCypherData Pointer to the cyphertext buffer (aligned on u32)
473 * @param Timeout Specify Timeout value
474 * @retval HAL status
475 */
HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef * hcryp,uint8_t * pPlainData,uint16_t Size,uint8_t * pCypherData,uint32_t Timeout)476 HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
477 {
478 /* Process Locked */
479 __HAL_LOCK(hcryp);
480
481 /* Check that data aligned on u32 */
482 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
483 {
484 /* Process Locked */
485 __HAL_UNLOCK(hcryp);
486
487 /* Return function status */
488 return HAL_ERROR;
489 }
490
491 /* Check if HAL_CRYP_Init has been called */
492 if(hcryp->State != HAL_CRYP_STATE_RESET)
493 {
494 /* Change the CRYP state */
495 hcryp->State = HAL_CRYP_STATE_BUSY;
496
497 /* Check if initialization phase has already been performed */
498 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
499 {
500 /* Set the key */
501 CRYP_SetKey(hcryp, hcryp->Init.pKey);
502
503 /* Reset the CHMOD & MODE bits */
504 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
505
506 /* Set the CRYP peripheral in AES CTR mode */
507 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT);
508
509 /* Set the Initialization Vector */
510 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
511
512 /* Enable CRYP */
513 __HAL_CRYP_ENABLE(hcryp);
514
515 /* Set the phase */
516 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
517 }
518
519 /* Write Plain Data and Get Cypher Data */
520 if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
521 {
522 return HAL_TIMEOUT;
523 }
524
525 /* Change the CRYP state */
526 hcryp->State = HAL_CRYP_STATE_READY;
527
528 /* Process Unlocked */
529 __HAL_UNLOCK(hcryp);
530
531 /* Return function status */
532 return HAL_OK;
533 }
534 else
535 {
536 /* Release Lock */
537 __HAL_UNLOCK(hcryp);
538
539 /* Return function status */
540 return HAL_ERROR;
541 }
542 }
543
544 /**
545 * @brief Initializes the CRYP peripheral in AES ECB decryption mode
546 * then decrypted pCypherData. The cypher data are available in pPlainData
547 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
548 * the configuration information for CRYP module
549 * @param pCypherData Pointer to the cyphertext buffer (aligned on u32)
550 * @param Size Length of the plaintext buffer, must be a multiple of 16.
551 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
552 * @param Timeout Specify Timeout value
553 * @retval HAL status
554 */
HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef * hcryp,uint8_t * pCypherData,uint16_t Size,uint8_t * pPlainData,uint32_t Timeout)555 HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
556 {
557 /* Process Locked */
558 __HAL_LOCK(hcryp);
559
560 /* Check that data aligned on u32 */
561 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
562 {
563 /* Process Locked */
564 __HAL_UNLOCK(hcryp);
565
566 /* Return function status */
567 return HAL_ERROR;
568 }
569
570 /* Check if HAL_CRYP_Init has been called */
571 if(hcryp->State != HAL_CRYP_STATE_RESET)
572 {
573 /* Change the CRYP state */
574 hcryp->State = HAL_CRYP_STATE_BUSY;
575
576 /* Check if initialization phase has already been performed */
577 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
578 {
579 /* Set the key */
580 CRYP_SetKey(hcryp, hcryp->Init.pKey);
581
582 /* Reset the CHMOD & MODE bits */
583 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
584
585 /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */
586 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT);
587
588 /* Enable CRYP */
589 __HAL_CRYP_ENABLE(hcryp);
590
591 /* Set the phase */
592 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
593 }
594
595 /* Write Cypher Data and Get Plain Data */
596 if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
597 {
598 return HAL_TIMEOUT;
599 }
600
601 /* Change the CRYP state */
602 hcryp->State = HAL_CRYP_STATE_READY;
603
604 /* Process Unlocked */
605 __HAL_UNLOCK(hcryp);
606
607 /* Return function status */
608 return HAL_OK;
609 }
610 else
611 {
612 /* Release Lock */
613 __HAL_UNLOCK(hcryp);
614
615 /* Return function status */
616 return HAL_ERROR;
617 }
618 }
619
620 /**
621 * @brief Initializes the CRYP peripheral in AES ECB decryption mode
622 * then decrypted pCypherData. The cypher data are available in pPlainData
623 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
624 * the configuration information for CRYP module
625 * @param pCypherData Pointer to the cyphertext buffer (aligned on u32)
626 * @param Size Length of the plaintext buffer, must be a multiple of 16.
627 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
628 * @param Timeout Specify Timeout value
629 * @retval HAL status
630 */
HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef * hcryp,uint8_t * pCypherData,uint16_t Size,uint8_t * pPlainData,uint32_t Timeout)631 HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
632 {
633 /* Process Locked */
634 __HAL_LOCK(hcryp);
635
636 /* Check that data aligned on u32 */
637 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
638 {
639 /* Process Locked */
640 __HAL_UNLOCK(hcryp);
641
642 /* Return function status */
643 return HAL_ERROR;
644 }
645
646 /* Check if HAL_CRYP_Init has been called */
647 if(hcryp->State != HAL_CRYP_STATE_RESET)
648 {
649 /* Change the CRYP state */
650 hcryp->State = HAL_CRYP_STATE_BUSY;
651
652 /* Check if initialization phase has already been performed */
653 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
654 {
655 /* Set the key */
656 CRYP_SetKey(hcryp, hcryp->Init.pKey);
657
658 /* Reset the CHMOD & MODE bits */
659 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
660
661 /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */
662 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT);
663
664 /* Set the Initialization Vector */
665 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
666
667 /* Enable CRYP */
668 __HAL_CRYP_ENABLE(hcryp);
669
670 /* Set the phase */
671 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
672 }
673
674 /* Write Cypher Data and Get Plain Data */
675 if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
676 {
677 return HAL_TIMEOUT;
678 }
679
680 /* Change the CRYP state */
681 hcryp->State = HAL_CRYP_STATE_READY;
682
683 /* Process Unlocked */
684 __HAL_UNLOCK(hcryp);
685
686 /* Return function status */
687 return HAL_OK;
688 }
689 else
690 {
691 /* Release Lock */
692 __HAL_UNLOCK(hcryp);
693
694 /* Return function status */
695 return HAL_ERROR;
696 }
697 }
698
699 /**
700 * @brief Initializes the CRYP peripheral in AES CTR decryption mode
701 * then decrypted pCypherData. The cypher data are available in pPlainData
702 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
703 * the configuration information for CRYP module
704 * @param pCypherData Pointer to the cyphertext buffer (aligned on u32)
705 * @param Size Length of the plaintext buffer, must be a multiple of 16.
706 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
707 * @param Timeout Specify Timeout value
708 * @retval HAL status
709 */
HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef * hcryp,uint8_t * pCypherData,uint16_t Size,uint8_t * pPlainData,uint32_t Timeout)710 HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
711 {
712 /* Process Locked */
713 __HAL_LOCK(hcryp);
714
715 /* Check that data aligned on u32 */
716 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
717 {
718 /* Process Locked */
719 __HAL_UNLOCK(hcryp);
720
721 /* Return function status */
722 return HAL_ERROR;
723 }
724
725 /* Check if initialization phase has already been performed */
726 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->Phase == HAL_CRYP_PHASE_READY))
727 {
728 /* Change the CRYP state */
729 hcryp->State = HAL_CRYP_STATE_BUSY;
730
731 /* Set the key */
732 CRYP_SetKey(hcryp, hcryp->Init.pKey);
733
734 /* Reset the CHMOD & MODE bits */
735 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
736
737 /* Set the CRYP peripheral in AES CTR decryption mode */
738 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_DECRYPT);
739
740 /* Set the Initialization Vector */
741 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
742
743 /* Enable CRYP */
744 __HAL_CRYP_ENABLE(hcryp);
745
746 /* Set the phase */
747 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
748 }
749
750 /* Write Cypher Data and Get Plain Data */
751 if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
752 {
753 return HAL_TIMEOUT;
754 }
755
756 /* Change the CRYP state */
757 hcryp->State = HAL_CRYP_STATE_READY;
758
759 /* Process Unlocked */
760 __HAL_UNLOCK(hcryp);
761
762 /* Return function status */
763 return HAL_OK;
764 }
765
766 /**
767 * @brief Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt.
768 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
769 * the configuration information for CRYP module
770 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
771 * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes
772 * @param pCypherData Pointer to the cyphertext buffer (aligned on u32)
773 * @retval HAL status
774 */
HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef * hcryp,uint8_t * pPlainData,uint16_t Size,uint8_t * pCypherData)775 HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
776 {
777 uint32_t inputaddr = 0;
778
779 /* Check that data aligned on u32 */
780 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
781 {
782 /* Process Locked */
783 __HAL_UNLOCK(hcryp);
784
785 /* Return function status */
786 return HAL_ERROR;
787 }
788
789 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
790 {
791 /* Process Locked */
792 __HAL_LOCK(hcryp);
793
794 /* Get the buffer addresses and sizes */
795 hcryp->CrypInCount = Size;
796 hcryp->pCrypInBuffPtr = pPlainData;
797 hcryp->pCrypOutBuffPtr = pCypherData;
798 hcryp->CrypOutCount = Size;
799
800 /* Change the CRYP state */
801 hcryp->State = HAL_CRYP_STATE_BUSY;
802
803 /* Check if initialization phase has already been performed */
804 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
805 {
806 /* Set the key */
807 CRYP_SetKey(hcryp, hcryp->Init.pKey);
808
809 /* Reset the CHMOD & MODE bits */
810 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
811
812 /* Set the CRYP peripheral in AES ECB mode */
813 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT);
814
815 /* Set the phase */
816 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
817 }
818
819 /* Enable Interrupts */
820 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
821
822 /* Enable CRYP */
823 __HAL_CRYP_ENABLE(hcryp);
824
825 /* Get the last input data adress */
826 inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
827
828 /* Write the Input block in the Data Input register */
829 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
830 inputaddr+=4;
831 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
832 inputaddr+=4;
833 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
834 inputaddr+=4;
835 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
836 hcryp->pCrypInBuffPtr += 16;
837 hcryp->CrypInCount -= 16;
838
839 /* Return function status */
840 return HAL_OK;
841 }
842 else
843 {
844 /* Release Lock */
845 __HAL_UNLOCK(hcryp);
846
847 /* Return function status */
848 return HAL_ERROR;
849 }
850 }
851
852 /**
853 * @brief Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt.
854 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
855 * the configuration information for CRYP module
856 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
857 * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes
858 * @param pCypherData Pointer to the cyphertext buffer (aligned on u32)
859 * @retval HAL status
860 */
HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef * hcryp,uint8_t * pPlainData,uint16_t Size,uint8_t * pCypherData)861 HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
862 {
863 uint32_t inputaddr = 0;
864
865 /* Check that data aligned on u32 */
866 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
867 {
868 /* Process Locked */
869 __HAL_UNLOCK(hcryp);
870
871 /* Return function status */
872 return HAL_ERROR;
873 }
874
875 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
876 {
877 /* Process Locked */
878 __HAL_LOCK(hcryp);
879
880 /* Get the buffer addresses and sizes */
881 hcryp->CrypInCount = Size;
882 hcryp->pCrypInBuffPtr = pPlainData;
883 hcryp->pCrypOutBuffPtr = pCypherData;
884 hcryp->CrypOutCount = Size;
885
886 /* Change the CRYP state */
887 hcryp->State = HAL_CRYP_STATE_BUSY;
888
889 /* Check if initialization phase has already been performed */
890 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
891 {
892 /* Set the key */
893 CRYP_SetKey(hcryp, hcryp->Init.pKey);
894
895 /* Reset the CHMOD & MODE bits */
896 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
897
898 /* Set the CRYP peripheral in AES CBC mode */
899 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT);
900
901 /* Set the Initialization Vector */
902 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
903
904 /* Set the phase */
905 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
906 }
907
908 /* Enable Interrupts */
909 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
910
911 /* Enable CRYP */
912 __HAL_CRYP_ENABLE(hcryp);
913
914 /* Get the last input data adress */
915 inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
916
917 /* Write the Input block in the Data Input register */
918 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
919 inputaddr+=4;
920 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
921 inputaddr+=4;
922 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
923 inputaddr+=4;
924 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
925 hcryp->pCrypInBuffPtr += 16;
926 hcryp->CrypInCount -= 16;
927
928 /* Return function status */
929 return HAL_OK;
930 }
931 else
932 {
933 /* Release Lock */
934 __HAL_UNLOCK(hcryp);
935
936 /* Return function status */
937 return HAL_ERROR;
938 }
939 }
940
941 /**
942 * @brief Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt.
943 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
944 * the configuration information for CRYP module
945 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
946 * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes
947 * @param pCypherData Pointer to the cyphertext buffer (aligned on u32)
948 * @retval HAL status
949 */
HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef * hcryp,uint8_t * pPlainData,uint16_t Size,uint8_t * pCypherData)950 HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
951 {
952 uint32_t inputaddr = 0;
953
954 /* Check that data aligned on u32 */
955 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
956 {
957 /* Process Locked */
958 __HAL_UNLOCK(hcryp);
959
960 /* Return function status */
961 return HAL_ERROR;
962 }
963
964 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
965 {
966 /* Process Locked */
967 __HAL_LOCK(hcryp);
968
969 /* Get the buffer addresses and sizes */
970 hcryp->CrypInCount = Size;
971 hcryp->pCrypInBuffPtr = pPlainData;
972 hcryp->pCrypOutBuffPtr = pCypherData;
973 hcryp->CrypOutCount = Size;
974
975 /* Change the CRYP state */
976 hcryp->State = HAL_CRYP_STATE_BUSY;
977
978 /* Check if initialization phase has already been performed */
979 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
980 {
981 /* Set the key */
982 CRYP_SetKey(hcryp, hcryp->Init.pKey);
983
984 /* Reset the CHMOD & MODE bits */
985 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
986
987 /* Set the CRYP peripheral in AES CTR mode */
988 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT);
989
990 /* Set the Initialization Vector */
991 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
992
993 /* Set the phase */
994 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
995 }
996
997 /* Enable Interrupts */
998 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
999
1000 /* Enable CRYP */
1001 __HAL_CRYP_ENABLE(hcryp);
1002
1003 /* Get the last input data adress */
1004 inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
1005
1006 /* Write the Input block in the Data Input register */
1007 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1008 inputaddr+=4;
1009 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1010 inputaddr+=4;
1011 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1012 inputaddr+=4;
1013 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1014 hcryp->pCrypInBuffPtr += 16;
1015 hcryp->CrypInCount -= 16;
1016
1017 /* Return function status */
1018 return HAL_OK;
1019 }
1020 else
1021 {
1022 /* Release Lock */
1023 __HAL_UNLOCK(hcryp);
1024
1025 /* Return function status */
1026 return HAL_ERROR;
1027 }
1028 }
1029
1030 /**
1031 * @brief Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt.
1032 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1033 * the configuration information for CRYP module
1034 * @param pCypherData Pointer to the cyphertext buffer (aligned on u32)
1035 * @param Size Length of the plaintext buffer, must be a multiple of 16.
1036 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
1037 * @retval HAL status
1038 */
HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef * hcryp,uint8_t * pCypherData,uint16_t Size,uint8_t * pPlainData)1039 HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
1040 {
1041 uint32_t inputaddr = 0;
1042
1043 /* Check that data aligned on u32 */
1044 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
1045 {
1046 /* Process Locked */
1047 __HAL_UNLOCK(hcryp);
1048
1049 /* Return function status */
1050 return HAL_ERROR;
1051 }
1052
1053 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
1054 {
1055 /* Process Locked */
1056 __HAL_LOCK(hcryp);
1057
1058 /* Get the buffer addresses and sizes */
1059 hcryp->CrypInCount = Size;
1060 hcryp->pCrypInBuffPtr = pCypherData;
1061 hcryp->pCrypOutBuffPtr = pPlainData;
1062 hcryp->CrypOutCount = Size;
1063
1064 /* Change the CRYP state */
1065 hcryp->State = HAL_CRYP_STATE_BUSY;
1066
1067 /* Check if initialization phase has already been performed */
1068 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1069 {
1070 /* Set the key */
1071 CRYP_SetKey(hcryp, hcryp->Init.pKey);
1072
1073 /* Reset the CHMOD & MODE bits */
1074 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
1075
1076 /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */
1077 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT);
1078
1079 /* Set the phase */
1080 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1081 }
1082
1083 /* Enable Interrupts */
1084 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
1085
1086 /* Enable CRYP */
1087 __HAL_CRYP_ENABLE(hcryp);
1088
1089 /* Get the last input data adress */
1090 inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
1091
1092 /* Write the Input block in the Data Input register */
1093 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1094 inputaddr+=4;
1095 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1096 inputaddr+=4;
1097 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1098 inputaddr+=4;
1099 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1100 hcryp->pCrypInBuffPtr += 16;
1101 hcryp->CrypInCount -= 16;
1102
1103 /* Return function status */
1104 return HAL_OK;
1105 }
1106 else
1107 {
1108 /* Release Lock */
1109 __HAL_UNLOCK(hcryp);
1110
1111 /* Return function status */
1112 return HAL_ERROR;
1113 }
1114 }
1115
1116 /**
1117 * @brief Initializes the CRYP peripheral in AES CBC decryption mode using IT.
1118 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1119 * the configuration information for CRYP module
1120 * @param pCypherData Pointer to the cyphertext buffer (aligned on u32)
1121 * @param Size Length of the plaintext buffer, must be a multiple of 16
1122 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
1123 * @retval HAL status
1124 */
HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef * hcryp,uint8_t * pCypherData,uint16_t Size,uint8_t * pPlainData)1125 HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
1126 {
1127 uint32_t inputaddr = 0;
1128
1129 /* Check that data aligned on u32 */
1130 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
1131 {
1132 /* Process Locked */
1133 __HAL_UNLOCK(hcryp);
1134
1135 /* Return function status */
1136 return HAL_ERROR;
1137 }
1138
1139 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
1140 {
1141 /* Process Locked */
1142 __HAL_LOCK(hcryp);
1143
1144 /* Get the buffer addresses and sizes */
1145 hcryp->CrypInCount = Size;
1146 hcryp->pCrypInBuffPtr = pCypherData;
1147 hcryp->pCrypOutBuffPtr = pPlainData;
1148 hcryp->CrypOutCount = Size;
1149
1150 /* Change the CRYP state */
1151 hcryp->State = HAL_CRYP_STATE_BUSY;
1152
1153 /* Check if initialization phase has already been performed */
1154 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1155 {
1156 /* Set the key */
1157 CRYP_SetKey(hcryp, hcryp->Init.pKey);
1158
1159 /* Reset the CHMOD & MODE bits */
1160 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
1161
1162 /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */
1163 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT);
1164
1165 /* Set the Initialization Vector */
1166 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
1167
1168 /* Set the phase */
1169 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1170 }
1171
1172 /* Enable Interrupts */
1173 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
1174
1175 /* Enable CRYP */
1176 __HAL_CRYP_ENABLE(hcryp);
1177
1178 /* Get the last input data adress */
1179 inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
1180
1181 /* Write the Input block in the Data Input register */
1182 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1183 inputaddr+=4;
1184 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1185 inputaddr+=4;
1186 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1187 inputaddr+=4;
1188 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1189 hcryp->pCrypInBuffPtr += 16;
1190 hcryp->CrypInCount -= 16;
1191
1192 /* Return function status */
1193 return HAL_OK;
1194 }
1195 else
1196 {
1197 /* Release Lock */
1198 __HAL_UNLOCK(hcryp);
1199
1200 /* Return function status */
1201 return HAL_ERROR;
1202 }
1203 }
1204
1205 /**
1206 * @brief Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt.
1207 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1208 * the configuration information for CRYP module
1209 * @param pCypherData Pointer to the cyphertext buffer (aligned on u32)
1210 * @param Size Length of the plaintext buffer, must be a multiple of 16
1211 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
1212 * @retval HAL status
1213 */
HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef * hcryp,uint8_t * pCypherData,uint16_t Size,uint8_t * pPlainData)1214 HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
1215 {
1216 uint32_t inputaddr = 0;
1217
1218 /* Check that data aligned on u32 */
1219 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
1220 {
1221 /* Process Locked */
1222 __HAL_UNLOCK(hcryp);
1223
1224 /* Return function status */
1225 return HAL_ERROR;
1226 }
1227
1228 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
1229 {
1230 /* Process Locked */
1231 __HAL_LOCK(hcryp);
1232
1233 /* Get the buffer addresses and sizes */
1234 hcryp->CrypInCount = Size;
1235 hcryp->pCrypInBuffPtr = pCypherData;
1236 hcryp->pCrypOutBuffPtr = pPlainData;
1237 hcryp->CrypOutCount = Size;
1238
1239 /* Change the CRYP state */
1240 hcryp->State = HAL_CRYP_STATE_BUSY;
1241
1242 /* Check if initialization phase has already been performed */
1243 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1244 {
1245 /* Set the key */
1246 CRYP_SetKey(hcryp, hcryp->Init.pKey);
1247
1248 /* Reset the CHMOD & MODE bits */
1249 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
1250
1251 /* Set the CRYP peripheral in AES CTR decryption mode */
1252 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_DECRYPT);
1253
1254 /* Set the Initialization Vector */
1255 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
1256
1257 /* Set the phase */
1258 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1259 }
1260
1261 /* Enable Interrupts */
1262 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
1263
1264 /* Enable CRYP */
1265 __HAL_CRYP_ENABLE(hcryp);
1266
1267 /* Get the last input data adress */
1268 inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
1269
1270 /* Write the Input block in the Data Input register */
1271 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1272 inputaddr+=4;
1273 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1274 inputaddr+=4;
1275 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1276 inputaddr+=4;
1277 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1278 hcryp->pCrypInBuffPtr += 16;
1279 hcryp->CrypInCount -= 16;
1280
1281 /* Return function status */
1282 return HAL_OK;
1283 }
1284 else
1285 {
1286 /* Release Lock */
1287 __HAL_UNLOCK(hcryp);
1288
1289 /* Return function status */
1290 return HAL_ERROR;
1291 }
1292 }
1293
1294 /**
1295 * @brief Initializes the CRYP peripheral in AES ECB encryption mode using DMA.
1296 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1297 * the configuration information for CRYP module
1298 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
1299 * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes
1300 * @param pCypherData Pointer to the cyphertext buffer (aligned on u32)
1301 * @retval HAL status
1302 */
HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef * hcryp,uint8_t * pPlainData,uint16_t Size,uint8_t * pCypherData)1303 HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
1304 {
1305 uint32_t inputaddr = 0, outputaddr = 0;
1306
1307 /* Check that data aligned on u32 */
1308 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
1309 {
1310 /* Process Locked */
1311 __HAL_UNLOCK(hcryp);
1312
1313 /* Return function status */
1314 return HAL_ERROR;
1315 }
1316
1317 /* Check if HAL_CRYP_Init has been called */
1318 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
1319 {
1320 /* Process Locked */
1321 __HAL_LOCK(hcryp);
1322
1323 inputaddr = (uint32_t)pPlainData;
1324 outputaddr = (uint32_t)pCypherData;
1325
1326 /* Change the CRYP state */
1327 hcryp->State = HAL_CRYP_STATE_BUSY;
1328
1329 /* Check if initialization phase has already been performed */
1330 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1331 {
1332 /* Set the key */
1333 CRYP_SetKey(hcryp, hcryp->Init.pKey);
1334
1335 /* Set the CRYP peripheral in AES ECB mode */
1336 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT);
1337
1338 /* Set the phase */
1339 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1340 }
1341 /* Set the input and output addresses and start DMA transfer */
1342 CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
1343
1344 /* Process Unlocked */
1345 __HAL_UNLOCK(hcryp);
1346
1347 /* Return function status */
1348 return HAL_OK;
1349 }
1350 else
1351 {
1352 /* Release Lock */
1353 __HAL_UNLOCK(hcryp);
1354
1355 return HAL_ERROR;
1356 }
1357 }
1358
1359 /**
1360 * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
1361 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1362 * the configuration information for CRYP module
1363 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
1364 * @param Size Length of the plaintext buffer, must be a multiple of 16.
1365 * @param pCypherData Pointer to the cyphertext buffer (aligned on u32)
1366 * @retval HAL status
1367 */
HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef * hcryp,uint8_t * pPlainData,uint16_t Size,uint8_t * pCypherData)1368 HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
1369 {
1370 uint32_t inputaddr = 0, outputaddr = 0;
1371
1372 /* Check that data aligned on u32 */
1373 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
1374 {
1375 /* Process Locked */
1376 __HAL_UNLOCK(hcryp);
1377
1378 /* Return function status */
1379 return HAL_ERROR;
1380 }
1381
1382 /* Check if HAL_CRYP_Init has been called */
1383 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
1384 {
1385 /* Process Locked */
1386 __HAL_LOCK(hcryp);
1387
1388 inputaddr = (uint32_t)pPlainData;
1389 outputaddr = (uint32_t)pCypherData;
1390
1391 /* Change the CRYP state */
1392 hcryp->State = HAL_CRYP_STATE_BUSY;
1393
1394 /* Check if initialization phase has already been performed */
1395 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1396 {
1397 /* Set the key */
1398 CRYP_SetKey(hcryp, hcryp->Init.pKey);
1399
1400 /* Set the CRYP peripheral in AES CBC mode */
1401 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT);
1402
1403 /* Set the Initialization Vector */
1404 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
1405
1406 /* Set the phase */
1407 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1408 }
1409 /* Set the input and output addresses and start DMA transfer */
1410 CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
1411
1412 /* Process Unlocked */
1413 __HAL_UNLOCK(hcryp);
1414
1415 /* Return function status */
1416 return HAL_OK;
1417 }
1418 else
1419 {
1420 /* Release Lock */
1421 __HAL_UNLOCK(hcryp);
1422
1423 return HAL_ERROR;
1424 }
1425 }
1426
1427 /**
1428 * @brief Initializes the CRYP peripheral in AES CTR encryption mode using DMA.
1429 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1430 * the configuration information for CRYP module
1431 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
1432 * @param Size Length of the plaintext buffer, must be a multiple of 16.
1433 * @param pCypherData Pointer to the cyphertext buffer (aligned on u32)
1434 * @retval HAL status
1435 */
HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef * hcryp,uint8_t * pPlainData,uint16_t Size,uint8_t * pCypherData)1436 HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
1437 {
1438 uint32_t inputaddr = 0, outputaddr = 0;
1439
1440 /* Check that data aligned on u32 */
1441 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
1442 {
1443 /* Process Locked */
1444 __HAL_UNLOCK(hcryp);
1445
1446 /* Return function status */
1447 return HAL_ERROR;
1448 }
1449
1450 /* Check if HAL_CRYP_Init has been called */
1451 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
1452 {
1453 /* Process Locked */
1454 __HAL_LOCK(hcryp);
1455
1456 inputaddr = (uint32_t)pPlainData;
1457 outputaddr = (uint32_t)pCypherData;
1458
1459 /* Change the CRYP state */
1460 hcryp->State = HAL_CRYP_STATE_BUSY;
1461
1462 /* Check if initialization phase has already been performed */
1463 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1464 {
1465 /* Set the key */
1466 CRYP_SetKey(hcryp, hcryp->Init.pKey);
1467
1468 /* Set the CRYP peripheral in AES CTR mode */
1469 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT);
1470
1471 /* Set the Initialization Vector */
1472 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
1473
1474 /* Set the phase */
1475 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1476 }
1477
1478 /* Set the input and output addresses and start DMA transfer */
1479 CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
1480
1481 /* Process Unlocked */
1482 __HAL_UNLOCK(hcryp);
1483
1484 /* Return function status */
1485 return HAL_OK;
1486 }
1487 else
1488 {
1489 /* Release Lock */
1490 __HAL_UNLOCK(hcryp);
1491
1492 return HAL_ERROR;
1493 }
1494 }
1495
1496 /**
1497 * @brief Initializes the CRYP peripheral in AES ECB decryption mode using DMA.
1498 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1499 * the configuration information for CRYP module
1500 * @param pCypherData Pointer to the cyphertext buffer (aligned on u32)
1501 * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes
1502 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
1503 * @retval HAL status
1504 */
HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef * hcryp,uint8_t * pCypherData,uint16_t Size,uint8_t * pPlainData)1505 HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
1506 {
1507 uint32_t inputaddr = 0, outputaddr = 0;
1508
1509 /* Check that data aligned on u32 */
1510 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
1511 {
1512 /* Process Locked */
1513 __HAL_UNLOCK(hcryp);
1514
1515 /* Return function status */
1516 return HAL_ERROR;
1517 }
1518
1519 /* Check if HAL_CRYP_Init has been called */
1520 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
1521 {
1522 /* Process Locked */
1523 __HAL_LOCK(hcryp);
1524
1525 inputaddr = (uint32_t)pCypherData;
1526 outputaddr = (uint32_t)pPlainData;
1527
1528 /* Change the CRYP state */
1529 hcryp->State = HAL_CRYP_STATE_BUSY;
1530
1531 /* Check if initialization phase has already been performed */
1532 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1533 {
1534 /* Set the key */
1535 CRYP_SetKey(hcryp, hcryp->Init.pKey);
1536
1537 /* Reset the CHMOD & MODE bits */
1538 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
1539
1540 /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */
1541 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT);
1542
1543 /* Set the phase */
1544 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1545 }
1546
1547 /* Set the input and output addresses and start DMA transfer */
1548 CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
1549
1550 /* Process Unlocked */
1551 __HAL_UNLOCK(hcryp);
1552
1553 /* Return function status */
1554 return HAL_OK;
1555 }
1556 else
1557 {
1558 /* Release Lock */
1559 __HAL_UNLOCK(hcryp);
1560
1561 return HAL_ERROR;
1562 }
1563 }
1564
1565 /**
1566 * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
1567 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1568 * the configuration information for CRYP module
1569 * @param pCypherData Pointer to the cyphertext buffer (aligned on u32)
1570 * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes
1571 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
1572 * @retval HAL status
1573 */
HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef * hcryp,uint8_t * pCypherData,uint16_t Size,uint8_t * pPlainData)1574 HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
1575 {
1576 uint32_t inputaddr = 0, outputaddr = 0;
1577
1578 /* Check that data aligned on u32 */
1579 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
1580 {
1581 /* Process Locked */
1582 __HAL_UNLOCK(hcryp);
1583
1584 /* Return function status */
1585 return HAL_ERROR;
1586 }
1587
1588 /* Check if HAL_CRYP_Init has been called */
1589 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
1590 {
1591 /* Process Locked */
1592 __HAL_LOCK(hcryp);
1593
1594 inputaddr = (uint32_t)pCypherData;
1595 outputaddr = (uint32_t)pPlainData;
1596
1597 /* Change the CRYP state */
1598 hcryp->State = HAL_CRYP_STATE_BUSY;
1599
1600 /* Check if initialization phase has already been performed */
1601 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1602 {
1603 /* Set the key */
1604 CRYP_SetKey(hcryp, hcryp->Init.pKey);
1605
1606 /* Reset the CHMOD & MODE bits */
1607 CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
1608
1609 /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */
1610 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT);
1611
1612 /* Set the Initialization Vector */
1613 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
1614
1615 /* Set the phase */
1616 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1617 }
1618
1619 /* Set the input and output addresses and start DMA transfer */
1620 CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
1621
1622 /* Process Unlocked */
1623 __HAL_UNLOCK(hcryp);
1624
1625 /* Return function status */
1626 return HAL_OK;
1627 }
1628 else
1629 {
1630 /* Release Lock */
1631 __HAL_UNLOCK(hcryp);
1632
1633 return HAL_ERROR;
1634 }
1635 }
1636
1637 /**
1638 * @brief Initializes the CRYP peripheral in AES CTR decryption mode using DMA.
1639 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1640 * the configuration information for CRYP module
1641 * @param pCypherData Pointer to the cyphertext buffer (aligned on u32)
1642 * @param Size Length of the plaintext buffer, must be a multiple of 16
1643 * @param pPlainData Pointer to the plaintext buffer (aligned on u32)
1644 * @retval HAL status
1645 */
HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef * hcryp,uint8_t * pCypherData,uint16_t Size,uint8_t * pPlainData)1646 HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
1647 {
1648 uint32_t inputaddr = 0, outputaddr = 0;
1649
1650 /* Check that data aligned on u32 */
1651 if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
1652 {
1653 /* Process Locked */
1654 __HAL_UNLOCK(hcryp);
1655
1656 /* Return function status */
1657 return HAL_ERROR;
1658 }
1659
1660 /* Check if HAL_CRYP_Init has been called */
1661 if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
1662 {
1663 /* Process Locked */
1664 __HAL_LOCK(hcryp);
1665
1666 inputaddr = (uint32_t)pCypherData;
1667 outputaddr = (uint32_t)pPlainData;
1668
1669 /* Change the CRYP state */
1670 hcryp->State = HAL_CRYP_STATE_BUSY;
1671
1672 /* Check if initialization phase has already been performed */
1673 if(hcryp->Phase == HAL_CRYP_PHASE_READY)
1674 {
1675 /* Set the key */
1676 CRYP_SetKey(hcryp, hcryp->Init.pKey);
1677
1678 /* Set the CRYP peripheral in AES CTR mode */
1679 __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_DECRYPT);
1680
1681 /* Set the Initialization Vector */
1682 CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
1683
1684 /* Set the phase */
1685 hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
1686 }
1687
1688 /* Set the input and output addresses and start DMA transfer */
1689 CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
1690
1691 /* Process Unlocked */
1692 __HAL_UNLOCK(hcryp);
1693
1694 /* Return function status */
1695 return HAL_OK;
1696 }
1697 else
1698 {
1699 /* Release Lock */
1700 __HAL_UNLOCK(hcryp);
1701
1702 return HAL_ERROR;
1703 }
1704 }
1705
1706 /**
1707 * @}
1708 */
1709
1710 /** @defgroup CRYP_Exported_Functions_Group3 DMA callback functions
1711 * @brief DMA callback functions.
1712 *
1713 @verbatim
1714 ==============================================================================
1715 ##### DMA callback functions #####
1716 ==============================================================================
1717 [..] This section provides DMA callback functions:
1718 (+) DMA Input data transfer complete
1719 (+) DMA Output data transfer complete
1720 (+) DMA error
1721
1722 @endverbatim
1723 * @{
1724 */
1725
1726 /**
1727 * @brief CRYP error callback.
1728 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1729 * the configuration information for CRYP module
1730 * @retval None
1731 */
HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef * hcryp)1732 __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
1733 {
1734 /* Prevent unused argument(s) compilation warning */
1735 UNUSED(hcryp);
1736
1737 /* NOTE : This function should not be modified; when the callback is needed,
1738 the HAL_CRYP_ErrorCallback can be implemented in the user file
1739 */
1740 }
1741
1742 /**
1743 * @brief Input transfer completed callback.
1744 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1745 * the configuration information for CRYP module
1746 * @retval None
1747 */
HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef * hcryp)1748 __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
1749 {
1750 /* Prevent unused argument(s) compilation warning */
1751 UNUSED(hcryp);
1752
1753 /* NOTE : This function should not be modified; when the callback is needed,
1754 the HAL_CRYP_InCpltCallback can be implemented in the user file
1755 */
1756 }
1757
1758 /**
1759 * @brief Output transfer completed callback.
1760 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1761 * the configuration information for CRYP module
1762 * @retval None
1763 */
HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef * hcryp)1764 __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
1765 {
1766 /* Prevent unused argument(s) compilation warning */
1767 UNUSED(hcryp);
1768
1769 /* NOTE : This function should not be modified; when the callback is needed,
1770 the HAL_CRYP_OutCpltCallback can be implemented in the user file
1771 */
1772 }
1773
1774 /**
1775 * @}
1776 */
1777
1778 /** @defgroup CRYP_Exported_Functions_Group4 CRYP IRQ handler
1779 * @brief CRYP IRQ handler.
1780 *
1781 @verbatim
1782 ==============================================================================
1783 ##### CRYP IRQ handler management #####
1784 ==============================================================================
1785 [..] This section provides CRYP IRQ handler function.
1786
1787 @endverbatim
1788 * @{
1789 */
1790
1791 /**
1792 * @brief This function handles CRYP interrupt request.
1793 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1794 * the configuration information for CRYP module
1795 * @retval None
1796 */
HAL_CRYP_IRQHandler(CRYP_HandleTypeDef * hcryp)1797 void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
1798 {
1799 /* Check if error occurred*/
1800 if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_ERR) != RESET)
1801 {
1802 if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_FLAG_RDERR) != RESET)
1803 {
1804 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_RDERR);
1805 }
1806
1807 if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_FLAG_WRERR) != RESET)
1808 {
1809 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_WRERR);
1810 }
1811
1812 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_CCF) != RESET)
1813 {
1814 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_CCF);
1815 }
1816
1817 hcryp->State= HAL_CRYP_STATE_ERROR;
1818 /* Disable Computation Complete Interrupt */
1819 __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_CC);
1820 __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_ERR);
1821
1822 HAL_CRYP_ErrorCallback(hcryp);
1823
1824 /* Process Unlocked */
1825 __HAL_UNLOCK(hcryp);
1826
1827 return;
1828 }
1829
1830 /* Check if computation complete interrupt was enabled*/
1831 if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CC) != RESET)
1832 {
1833 /* Clear CCF Flag */
1834 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_CCF);
1835
1836 CRYP_EncryptDecrypt_IT(hcryp);
1837 }
1838 }
1839
1840 /**
1841 * @}
1842 */
1843
1844 /** @defgroup CRYP_Exported_Functions_Group5 Peripheral State functions
1845 * @brief Peripheral State functions.
1846 *
1847 @verbatim
1848 ==============================================================================
1849 ##### Peripheral State functions #####
1850 ==============================================================================
1851 [..]
1852 This subsection permits to get in run-time the status of the peripheral.
1853
1854 @endverbatim
1855 * @{
1856 */
1857
1858 /**
1859 * @brief Returns the CRYP state.
1860 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1861 * the configuration information for CRYP module
1862 * @retval HAL state
1863 */
HAL_CRYP_GetState(CRYP_HandleTypeDef * hcryp)1864 HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
1865 {
1866 return hcryp->State;
1867 }
1868
1869 /**
1870 * @}
1871 */
1872
1873 /**
1874 * @}
1875 */
1876
1877 /** @addtogroup CRYP_Private_Functions
1878 * @{
1879 */
1880
1881 /**
1882 * @brief IT function called under interruption context to continue encryption or decryption
1883 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1884 * the configuration information for CRYP module
1885 * @retval HAL status
1886 */
CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef * hcryp)1887 static HAL_StatusTypeDef CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef *hcryp)
1888 {
1889 uint32_t inputaddr = 0, outputaddr = 0;
1890
1891 /* Get the last Output data adress */
1892 outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
1893
1894 /* Read the Output block from the Output Register */
1895 *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
1896 outputaddr+=4;
1897 *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
1898 outputaddr+=4;
1899 *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
1900 outputaddr+=4;
1901 *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
1902
1903 hcryp->pCrypOutBuffPtr += 16;
1904 hcryp->CrypOutCount -= 16;
1905
1906 /* Check if all input text is encrypted or decrypted */
1907 if(hcryp->CrypOutCount == 0)
1908 {
1909 /* Disable Computation Complete Interrupt */
1910 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CC);
1911 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_ERR);
1912
1913 /* Process Unlocked */
1914 __HAL_UNLOCK(hcryp);
1915
1916 /* Change the CRYP state */
1917 hcryp->State = HAL_CRYP_STATE_READY;
1918
1919 /* Call computation complete callback */
1920 HAL_CRYPEx_ComputationCpltCallback(hcryp);
1921 }
1922 else /* Process the rest of input text */
1923 {
1924 /* Get the last Intput data adress */
1925 inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
1926
1927 /* Write the Input block in the Data Input register */
1928 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1929 inputaddr+=4;
1930 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1931 inputaddr+=4;
1932 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1933 inputaddr+=4;
1934 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
1935 hcryp->pCrypInBuffPtr += 16;
1936 hcryp->CrypInCount -= 16;
1937 }
1938 return HAL_OK;
1939 }
1940 /**
1941 * @brief DMA CRYP Input Data process complete callback.
1942 * @param hdma DMA handle
1943 * @retval None
1944 */
CRYP_DMAInCplt(DMA_HandleTypeDef * hdma)1945 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
1946 {
1947 CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
1948
1949 /* Disable the DMA transfer for input request */
1950 CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
1951
1952 /* Call input data transfer complete callback */
1953 HAL_CRYP_InCpltCallback(hcryp);
1954 }
1955
1956 /**
1957 * @brief DMA CRYP Output Data process complete callback.
1958 * @param hdma DMA handle
1959 * @retval None
1960 */
CRYP_DMAOutCplt(DMA_HandleTypeDef * hdma)1961 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
1962 {
1963 CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
1964
1965 /* Disable the DMA transfer for output request by resetting the DMAOUTEN bit
1966 in the DMACR register */
1967 CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
1968
1969 /* Clear CCF Flag */
1970 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_CCF);
1971
1972 /* Disable CRYP */
1973 __HAL_CRYP_DISABLE(hcryp);
1974
1975 /* Change the CRYP state to ready */
1976 hcryp->State = HAL_CRYP_STATE_READY;
1977
1978 /* Call output data transfer complete callback */
1979 HAL_CRYP_OutCpltCallback(hcryp);
1980 }
1981
1982 /**
1983 * @brief DMA CRYP communication error callback.
1984 * @param hdma DMA handle
1985 * @retval None
1986 */
CRYP_DMAError(DMA_HandleTypeDef * hdma)1987 static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
1988 {
1989 CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
1990 hcryp->State= HAL_CRYP_STATE_ERROR;
1991 HAL_CRYP_ErrorCallback(hcryp);
1992 }
1993
1994 /**
1995 * @brief Writes the Key in Key registers.
1996 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1997 * the configuration information for CRYP module
1998 * @param Key Pointer to Key buffer
1999 * @note Key must be written as little endian.
2000 * If Key pointer points at address n,
2001 * n[15:0] contains key[96:127],
2002 * (n+4)[15:0] contains key[64:95],
2003 * (n+8)[15:0] contains key[32:63] and
2004 * (n+12)[15:0] contains key[0:31]
2005 * @retval None
2006 */
CRYP_SetKey(CRYP_HandleTypeDef * hcryp,uint8_t * Key)2007 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key)
2008 {
2009 uint32_t keyaddr = (uint32_t)Key;
2010
2011 hcryp->Instance->KEYR3 = __REV(*(uint32_t*)(keyaddr));
2012 keyaddr+=4;
2013 hcryp->Instance->KEYR2 = __REV(*(uint32_t*)(keyaddr));
2014 keyaddr+=4;
2015 hcryp->Instance->KEYR1 = __REV(*(uint32_t*)(keyaddr));
2016 keyaddr+=4;
2017 hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr));
2018 }
2019
2020 /**
2021 * @brief Writes the InitVector/InitCounter in IV registers.
2022 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
2023 * the configuration information for CRYP module
2024 * @param InitVector Pointer to InitVector/InitCounter buffer
2025 * @note Init Vector must be written as little endian.
2026 * If Init Vector pointer points at address n,
2027 * n[15:0] contains Vector[96:127],
2028 * (n+4)[15:0] contains Vector[64:95],
2029 * (n+8)[15:0] contains Vector[32:63] and
2030 * (n+12)[15:0] contains Vector[0:31]
2031 * @retval None
2032 */
CRYP_SetInitVector(CRYP_HandleTypeDef * hcryp,uint8_t * InitVector)2033 static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector)
2034 {
2035 uint32_t ivaddr = (uint32_t)InitVector;
2036
2037 hcryp->Instance->IVR3 = __REV(*(uint32_t*)(ivaddr));
2038 ivaddr+=4;
2039 hcryp->Instance->IVR2 = __REV(*(uint32_t*)(ivaddr));
2040 ivaddr+=4;
2041 hcryp->Instance->IVR1 = __REV(*(uint32_t*)(ivaddr));
2042 ivaddr+=4;
2043 hcryp->Instance->IVR0 = __REV(*(uint32_t*)(ivaddr));
2044 }
2045
2046 /**
2047 * @brief Process Data: Writes Input data in polling mode and reads the output data
2048 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
2049 * the configuration information for CRYP module
2050 * @param Input Pointer to the Input buffer
2051 * @param Ilength Length of the Input buffer, must be a multiple of 16.
2052 * @param Output Pointer to the returned buffer
2053 * @param Timeout Specify Timeout value
2054 * @retval None
2055 */
CRYP_ProcessData(CRYP_HandleTypeDef * hcryp,uint8_t * Input,uint16_t Ilength,uint8_t * Output,uint32_t Timeout)2056 static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
2057 {
2058 uint32_t tickstart = 0;
2059
2060 uint32_t index = 0;
2061 uint32_t inputaddr = (uint32_t)Input;
2062 uint32_t outputaddr = (uint32_t)Output;
2063
2064 for(index=0; (index < Ilength); index += 16)
2065 {
2066 /* Write the Input block in the Data Input register */
2067 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
2068 inputaddr+=4;
2069 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
2070 inputaddr+=4;
2071 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
2072 inputaddr+=4;
2073 hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
2074 inputaddr+=4;
2075
2076 /* Get timeout */
2077 tickstart = HAL_GetTick();
2078
2079 while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
2080 {
2081 /* Check for the Timeout */
2082 if(Timeout != HAL_MAX_DELAY)
2083 {
2084 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
2085 {
2086 /* Change state */
2087 hcryp->State = HAL_CRYP_STATE_TIMEOUT;
2088
2089 /* Process Unlocked */
2090 __HAL_UNLOCK(hcryp);
2091
2092 return HAL_TIMEOUT;
2093 }
2094 }
2095 }
2096 /* Clear CCF Flag */
2097 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_CCF);
2098
2099 /* Read the Output block from the Data Output Register */
2100 *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
2101 outputaddr+=4;
2102 *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
2103 outputaddr+=4;
2104 *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
2105 outputaddr+=4;
2106 *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
2107 outputaddr+=4;
2108 }
2109 /* Return function status */
2110 return HAL_OK;
2111 }
2112
2113 /**
2114 * @brief Set the DMA configuration and start the DMA transfer
2115 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
2116 * the configuration information for CRYP module
2117 * @param inputaddr address of the Input buffer
2118 * @param Size Size of the Input buffer, must be a multiple of 16.
2119 * @param outputaddr address of the Output buffer
2120 * @retval None
2121 */
CRYP_SetDMAConfig(CRYP_HandleTypeDef * hcryp,uint32_t inputaddr,uint16_t Size,uint32_t outputaddr)2122 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
2123 {
2124 /* Set the CRYP DMA transfer complete callback */
2125 hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
2126 /* Set the DMA error callback */
2127 hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
2128
2129 /* Set the CRYP DMA transfer complete callback */
2130 hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
2131 /* Set the DMA error callback */
2132 hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
2133
2134 /* Enable the DMA In DMA Stream */
2135 HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size/4);
2136
2137 /* Enable the DMA Out DMA Stream */
2138 HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size/4);
2139
2140 /* Enable In and Out DMA requests */
2141 SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN));
2142
2143 /* Enable CRYP */
2144 __HAL_CRYP_ENABLE(hcryp);
2145 }
2146
2147 /**
2148 * @}
2149 */
2150
2151 #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX*/
2152
2153 /**
2154 * @}
2155 */
2156
2157 /**
2158 * @}
2159 */
2160
2161 #endif /* HAL_CRYP_MODULE_ENABLED */
2162
2163 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2164
