1 /**
2 ******************************************************************************
3 * @file stm32l1xx_ll_i2c.h
4 * @author MCD Application Team
5 * @brief Header file of I2C LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32L1xx_LL_I2C_H
22 #define __STM32L1xx_LL_I2C_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l1xx.h"
30
31 /** @addtogroup STM32L1xx_LL_Driver
32 * @{
33 */
34
35 #if defined (I2C1) || defined (I2C2)
36
37 /** @defgroup I2C_LL I2C
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45 /** @defgroup I2C_LL_Private_Constants I2C Private Constants
46 * @{
47 */
48
49 /* Defines used to perform compute and check in the macros */
50 #define LL_I2C_MAX_SPEED_STANDARD 100000U
51 #define LL_I2C_MAX_SPEED_FAST 400000U
52 /**
53 * @}
54 */
55
56 /* Private macros ------------------------------------------------------------*/
57 #if defined(USE_FULL_LL_DRIVER)
58 /** @defgroup I2C_LL_Private_Macros I2C Private Macros
59 * @{
60 */
61 /**
62 * @}
63 */
64 #endif /*USE_FULL_LL_DRIVER*/
65
66 /* Exported types ------------------------------------------------------------*/
67 #if defined(USE_FULL_LL_DRIVER)
68 /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
69 * @{
70 */
71 typedef struct
72 {
73 uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
74 This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
75
76 This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
77
78 uint32_t ClockSpeed; /*!< Specifies the clock frequency.
79 This parameter must be set to a value lower than 400kHz (in Hz)
80
81 This feature can be modified afterwards using unitary function @ref LL_I2C_SetClockPeriod()
82 or @ref LL_I2C_SetDutyCycle() or @ref LL_I2C_SetClockSpeedMode() or @ref LL_I2C_ConfigSpeed(). */
83
84 uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
85 This parameter can be a value of @ref I2C_LL_EC_DUTYCYCLE
86
87 This feature can be modified afterwards using unitary function @ref LL_I2C_SetDutyCycle(). */
88
89 uint32_t OwnAddress1; /*!< Specifies the device own address 1.
90 This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
91
92 This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
93
94 uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
95 This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
96
97 This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
98
99 uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
100 This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
101
102 This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
103 } LL_I2C_InitTypeDef;
104 /**
105 * @}
106 */
107 #endif /*USE_FULL_LL_DRIVER*/
108
109 /* Exported constants --------------------------------------------------------*/
110 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
111 * @{
112 */
113
114 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
115 * @brief Flags defines which can be used with LL_I2C_ReadReg function
116 * @{
117 */
118 #define LL_I2C_SR1_SB I2C_SR1_SB /*!< Start Bit (master mode) */
119 #define LL_I2C_SR1_ADDR I2C_SR1_ADDR /*!< Address sent (master mode) or
120 Address matched flag (slave mode) */
121 #define LL_I2C_SR1_BTF I2C_SR1_BTF /*!< Byte Transfer Finished flag */
122 #define LL_I2C_SR1_ADD10 I2C_SR1_ADD10 /*!< 10-bit header sent (master mode) */
123 #define LL_I2C_SR1_STOPF I2C_SR1_STOPF /*!< Stop detection flag (slave mode) */
124 #define LL_I2C_SR1_RXNE I2C_SR1_RXNE /*!< Data register not empty (receivers) */
125 #define LL_I2C_SR1_TXE I2C_SR1_TXE /*!< Data register empty (transmitters) */
126 #define LL_I2C_SR1_BERR I2C_SR1_BERR /*!< Bus error */
127 #define LL_I2C_SR1_ARLO I2C_SR1_ARLO /*!< Arbitration lost */
128 #define LL_I2C_SR1_AF I2C_SR1_AF /*!< Acknowledge failure flag */
129 #define LL_I2C_SR1_OVR I2C_SR1_OVR /*!< Overrun/Underrun */
130 #define LL_I2C_SR1_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
131 #define LL_I2C_SR1_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
132 #define LL_I2C_SR1_SMALERT I2C_ISR_SMALERT /*!< SMBus alert (SMBus mode) */
133 #define LL_I2C_SR2_MSL I2C_SR2_MSL /*!< Master/Slave flag */
134 #define LL_I2C_SR2_BUSY I2C_SR2_BUSY /*!< Bus busy flag */
135 #define LL_I2C_SR2_TRA I2C_SR2_TRA /*!< Transmitter/receiver direction */
136 #define LL_I2C_SR2_GENCALL I2C_SR2_GENCALL /*!< General call address (Slave mode) */
137 #define LL_I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT /*!< SMBus Device default address (Slave mode) */
138 #define LL_I2C_SR2_SMBHOST I2C_SR2_SMBHOST /*!< SMBus Host address (Slave mode) */
139 #define LL_I2C_SR2_DUALF I2C_SR2_DUALF /*!< Dual flag (Slave mode) */
140 /**
141 * @}
142 */
143
144 /** @defgroup I2C_LL_EC_IT IT Defines
145 * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
146 * @{
147 */
148 #define LL_I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN /*!< Events interrupts enable */
149 #define LL_I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN /*!< Buffer interrupts enable */
150 #define LL_I2C_CR2_ITERREN I2C_CR2_ITERREN /*!< Error interrupts enable */
151 /**
152 * @}
153 */
154
155 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
156 * @{
157 */
158 #define LL_I2C_OWNADDRESS1_7BIT 0x00004000U /*!< Own address 1 is a 7-bit address. */
159 #define LL_I2C_OWNADDRESS1_10BIT (uint32_t)(I2C_OAR1_ADDMODE | 0x00004000U) /*!< Own address 1 is a 10-bit address. */
160 /**
161 * @}
162 */
163
164 /** @defgroup I2C_LL_EC_DUTYCYCLE Fast Mode Duty Cycle
165 * @{
166 */
167 #define LL_I2C_DUTYCYCLE_2 0x00000000U /*!< I2C fast mode Tlow/Thigh = 2 */
168 #define LL_I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY /*!< I2C fast mode Tlow/Thigh = 16/9 */
169 /**
170 * @}
171 */
172
173 /** @defgroup I2C_LL_EC_CLOCK_SPEED_MODE Master Clock Speed Mode
174 * @{
175 */
176 #define LL_I2C_CLOCK_SPEED_STANDARD_MODE 0x00000000U /*!< Master clock speed range is standard mode */
177 #define LL_I2C_CLOCK_SPEED_FAST_MODE I2C_CCR_FS /*!< Master clock speed range is fast mode */
178 /**
179 * @}
180 */
181
182 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
183 * @{
184 */
185 #define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
186 #define LL_I2C_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP) /*!< SMBus Host address acknowledge */
187 #define LL_I2C_MODE_SMBUS_DEVICE I2C_CR1_SMBUS /*!< SMBus Device default mode (Default address not acknowledge) */
188 #define LL_I2C_MODE_SMBUS_DEVICE_ARP (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_ENARP) /*!< SMBus Device Default address acknowledge */
189 /**
190 * @}
191 */
192
193 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
194 * @{
195 */
196 #define LL_I2C_ACK I2C_CR1_ACK /*!< ACK is sent after current received byte. */
197 #define LL_I2C_NACK 0x00000000U /*!< NACK is sent after current received byte.*/
198 /**
199 * @}
200 */
201
202 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
203 * @{
204 */
205 #define LL_I2C_DIRECTION_WRITE I2C_SR2_TRA /*!< Bus is in write transfer */
206 #define LL_I2C_DIRECTION_READ 0x00000000U /*!< Bus is in read transfer */
207 /**
208 * @}
209 */
210
211 /**
212 * @}
213 */
214
215 /* Exported macro ------------------------------------------------------------*/
216 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
217 * @{
218 */
219
220 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
221 * @{
222 */
223
224 /**
225 * @brief Write a value in I2C register
226 * @param __INSTANCE__ I2C Instance
227 * @param __REG__ Register to be written
228 * @param __VALUE__ Value to be written in the register
229 * @retval None
230 */
231 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
232
233 /**
234 * @brief Read a value in I2C register
235 * @param __INSTANCE__ I2C Instance
236 * @param __REG__ Register to be read
237 * @retval Register value
238 */
239 #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
240 /**
241 * @}
242 */
243
244 /** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
245 * @{
246 */
247
248 /**
249 * @brief Convert Peripheral Clock Frequency in Mhz.
250 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
251 * @retval Value of peripheral clock (in Mhz)
252 */
253 #define __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__) (uint32_t)((__PCLK__)/1000000U)
254
255 /**
256 * @brief Convert Peripheral Clock Frequency in Hz.
257 * @param __PCLK__ This parameter must be a value of peripheral clock (in Mhz).
258 * @retval Value of peripheral clock (in Hz)
259 */
260 #define __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__) (uint32_t)((__PCLK__)*1000000U)
261
262 /**
263 * @brief Compute I2C Clock rising time.
264 * @param __FREQRANGE__ This parameter must be a value of peripheral clock (in Mhz).
265 * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
266 * @retval Value between Min_Data=0x02 and Max_Data=0x3F
267 */
268 #define __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
269
270 /**
271 * @brief Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value.
272 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
273 * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
274 * @param __DUTYCYCLE__ This parameter can be one of the following values:
275 * @arg @ref LL_I2C_DUTYCYCLE_2
276 * @arg @ref LL_I2C_DUTYCYCLE_16_9
277 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
278 */
279 #define __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \
280 (__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \
281 (__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__))))
282
283 /**
284 * @brief Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value.
285 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
286 * @param __SPEED__ This parameter must be a value lower than 100kHz (in Hz).
287 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF.
288 */
289 #define __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__) (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
290
291 /**
292 * @brief Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value.
293 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
294 * @param __SPEED__ This parameter must be a value between Min_Data=100Khz and Max_Data=400Khz (in Hz).
295 * @param __DUTYCYCLE__ This parameter can be one of the following values:
296 * @arg @ref LL_I2C_DUTYCYCLE_2
297 * @arg @ref LL_I2C_DUTYCYCLE_16_9
298 * @retval Value between Min_Data=0x001 and Max_Data=0xFFF
299 */
300 #define __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \
301 (((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \
302 (((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U))))
303
304 /**
305 * @brief Get the Least significant bits of a 10-Bits address.
306 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
307 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
308 */
309 #define __LL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
310
311 /**
312 * @brief Convert a 10-Bits address to a 10-Bits header with Write direction.
313 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
314 * @retval Value between Min_Data=0xF0 and Max_Data=0xF6
315 */
316 #define __LL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
317
318 /**
319 * @brief Convert a 10-Bits address to a 10-Bits header with Read direction.
320 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
321 * @retval Value between Min_Data=0xF1 and Max_Data=0xF7
322 */
323 #define __LL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
324
325 /**
326 * @}
327 */
328
329 /**
330 * @}
331 */
332
333 /* Exported functions --------------------------------------------------------*/
334
335 /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
336 * @{
337 */
338
339 /** @defgroup I2C_LL_EF_Configuration Configuration
340 * @{
341 */
342
343 /**
344 * @brief Enable I2C peripheral (PE = 1).
345 * @rmtoll CR1 PE LL_I2C_Enable
346 * @param I2Cx I2C Instance.
347 * @retval None
348 */
LL_I2C_Enable(I2C_TypeDef * I2Cx)349 __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
350 {
351 SET_BIT(I2Cx->CR1, I2C_CR1_PE);
352 }
353
354 /**
355 * @brief Disable I2C peripheral (PE = 0).
356 * @rmtoll CR1 PE LL_I2C_Disable
357 * @param I2Cx I2C Instance.
358 * @retval None
359 */
LL_I2C_Disable(I2C_TypeDef * I2Cx)360 __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
361 {
362 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
363 }
364
365 /**
366 * @brief Check if the I2C peripheral is enabled or disabled.
367 * @rmtoll CR1 PE LL_I2C_IsEnabled
368 * @param I2Cx I2C Instance.
369 * @retval State of bit (1 or 0).
370 */
LL_I2C_IsEnabled(I2C_TypeDef * I2Cx)371 __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
372 {
373 return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
374 }
375
376
377 /**
378 * @brief Enable DMA transmission requests.
379 * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_TX
380 * @param I2Cx I2C Instance.
381 * @retval None
382 */
LL_I2C_EnableDMAReq_TX(I2C_TypeDef * I2Cx)383 __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
384 {
385 SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
386 }
387
388 /**
389 * @brief Disable DMA transmission requests.
390 * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_TX
391 * @param I2Cx I2C Instance.
392 * @retval None
393 */
LL_I2C_DisableDMAReq_TX(I2C_TypeDef * I2Cx)394 __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
395 {
396 CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
397 }
398
399 /**
400 * @brief Check if DMA transmission requests are enabled or disabled.
401 * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_TX
402 * @param I2Cx I2C Instance.
403 * @retval State of bit (1 or 0).
404 */
LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef * I2Cx)405 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
406 {
407 return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
408 }
409
410 /**
411 * @brief Enable DMA reception requests.
412 * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_RX
413 * @param I2Cx I2C Instance.
414 * @retval None
415 */
LL_I2C_EnableDMAReq_RX(I2C_TypeDef * I2Cx)416 __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
417 {
418 SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
419 }
420
421 /**
422 * @brief Disable DMA reception requests.
423 * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_RX
424 * @param I2Cx I2C Instance.
425 * @retval None
426 */
LL_I2C_DisableDMAReq_RX(I2C_TypeDef * I2Cx)427 __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
428 {
429 CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
430 }
431
432 /**
433 * @brief Check if DMA reception requests are enabled or disabled.
434 * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_RX
435 * @param I2Cx I2C Instance.
436 * @retval State of bit (1 or 0).
437 */
LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef * I2Cx)438 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
439 {
440 return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
441 }
442
443 /**
444 * @brief Get the data register address used for DMA transfer.
445 * @rmtoll DR DR LL_I2C_DMA_GetRegAddr
446 * @param I2Cx I2C Instance.
447 * @retval Address of data register
448 */
LL_I2C_DMA_GetRegAddr(I2C_TypeDef * I2Cx)449 __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx)
450 {
451 return (uint32_t) & (I2Cx->DR);
452 }
453
454 /**
455 * @brief Enable Clock stretching.
456 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
457 * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
458 * @param I2Cx I2C Instance.
459 * @retval None
460 */
LL_I2C_EnableClockStretching(I2C_TypeDef * I2Cx)461 __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
462 {
463 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
464 }
465
466 /**
467 * @brief Disable Clock stretching.
468 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
469 * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
470 * @param I2Cx I2C Instance.
471 * @retval None
472 */
LL_I2C_DisableClockStretching(I2C_TypeDef * I2Cx)473 __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
474 {
475 SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
476 }
477
478 /**
479 * @brief Check if Clock stretching is enabled or disabled.
480 * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
481 * @param I2Cx I2C Instance.
482 * @retval State of bit (1 or 0).
483 */
LL_I2C_IsEnabledClockStretching(I2C_TypeDef * I2Cx)484 __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
485 {
486 return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
487 }
488
489 /**
490 * @brief Enable General Call.
491 * @note When enabled the Address 0x00 is ACKed.
492 * @rmtoll CR1 ENGC LL_I2C_EnableGeneralCall
493 * @param I2Cx I2C Instance.
494 * @retval None
495 */
LL_I2C_EnableGeneralCall(I2C_TypeDef * I2Cx)496 __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
497 {
498 SET_BIT(I2Cx->CR1, I2C_CR1_ENGC);
499 }
500
501 /**
502 * @brief Disable General Call.
503 * @note When disabled the Address 0x00 is NACKed.
504 * @rmtoll CR1 ENGC LL_I2C_DisableGeneralCall
505 * @param I2Cx I2C Instance.
506 * @retval None
507 */
LL_I2C_DisableGeneralCall(I2C_TypeDef * I2Cx)508 __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
509 {
510 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENGC);
511 }
512
513 /**
514 * @brief Check if General Call is enabled or disabled.
515 * @rmtoll CR1 ENGC LL_I2C_IsEnabledGeneralCall
516 * @param I2Cx I2C Instance.
517 * @retval State of bit (1 or 0).
518 */
LL_I2C_IsEnabledGeneralCall(I2C_TypeDef * I2Cx)519 __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
520 {
521 return (READ_BIT(I2Cx->CR1, I2C_CR1_ENGC) == (I2C_CR1_ENGC));
522 }
523
524 /**
525 * @brief Set the Own Address1.
526 * @rmtoll OAR1 ADD0 LL_I2C_SetOwnAddress1\n
527 * OAR1 ADD1_7 LL_I2C_SetOwnAddress1\n
528 * OAR1 ADD8_9 LL_I2C_SetOwnAddress1\n
529 * OAR1 ADDMODE LL_I2C_SetOwnAddress1
530 * @param I2Cx I2C Instance.
531 * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
532 * @param OwnAddrSize This parameter can be one of the following values:
533 * @arg @ref LL_I2C_OWNADDRESS1_7BIT
534 * @arg @ref LL_I2C_OWNADDRESS1_10BIT
535 * @retval None
536 */
LL_I2C_SetOwnAddress1(I2C_TypeDef * I2Cx,uint32_t OwnAddress1,uint32_t OwnAddrSize)537 __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
538 {
539 MODIFY_REG(I2Cx->OAR1, I2C_OAR1_ADD0 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD8_9 | I2C_OAR1_ADDMODE, OwnAddress1 | OwnAddrSize);
540 }
541
542 /**
543 * @brief Set the 7bits Own Address2.
544 * @note This action has no effect if own address2 is enabled.
545 * @rmtoll OAR2 ADD2 LL_I2C_SetOwnAddress2
546 * @param I2Cx I2C Instance.
547 * @param OwnAddress2 This parameter must be a value between Min_Data=0 and Max_Data=0x7F.
548 * @retval None
549 */
LL_I2C_SetOwnAddress2(I2C_TypeDef * I2Cx,uint32_t OwnAddress2)550 __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2)
551 {
552 MODIFY_REG(I2Cx->OAR2, I2C_OAR2_ADD2, OwnAddress2);
553 }
554
555 /**
556 * @brief Enable acknowledge on Own Address2 match address.
557 * @rmtoll OAR2 ENDUAL LL_I2C_EnableOwnAddress2
558 * @param I2Cx I2C Instance.
559 * @retval None
560 */
LL_I2C_EnableOwnAddress2(I2C_TypeDef * I2Cx)561 __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
562 {
563 SET_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
564 }
565
566 /**
567 * @brief Disable acknowledge on Own Address2 match address.
568 * @rmtoll OAR2 ENDUAL LL_I2C_DisableOwnAddress2
569 * @param I2Cx I2C Instance.
570 * @retval None
571 */
LL_I2C_DisableOwnAddress2(I2C_TypeDef * I2Cx)572 __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
573 {
574 CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
575 }
576
577 /**
578 * @brief Check if Own Address1 acknowledge is enabled or disabled.
579 * @rmtoll OAR2 ENDUAL LL_I2C_IsEnabledOwnAddress2
580 * @param I2Cx I2C Instance.
581 * @retval State of bit (1 or 0).
582 */
LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef * I2Cx)583 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
584 {
585 return (READ_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL) == (I2C_OAR2_ENDUAL));
586 }
587
588 /**
589 * @brief Configure the Peripheral clock frequency.
590 * @rmtoll CR2 FREQ LL_I2C_SetPeriphClock
591 * @param I2Cx I2C Instance.
592 * @param PeriphClock Peripheral Clock (in Hz)
593 * @retval None
594 */
LL_I2C_SetPeriphClock(I2C_TypeDef * I2Cx,uint32_t PeriphClock)595 __STATIC_INLINE void LL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock)
596 {
597 MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock));
598 }
599
600 /**
601 * @brief Get the Peripheral clock frequency.
602 * @rmtoll CR2 FREQ LL_I2C_GetPeriphClock
603 * @param I2Cx I2C Instance.
604 * @retval Value of Peripheral Clock (in Hz)
605 */
LL_I2C_GetPeriphClock(I2C_TypeDef * I2Cx)606 __STATIC_INLINE uint32_t LL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx)
607 {
608 return (uint32_t)(__LL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CR2, I2C_CR2_FREQ)));
609 }
610
611 /**
612 * @brief Configure the Duty cycle (Fast mode only).
613 * @rmtoll CCR DUTY LL_I2C_SetDutyCycle
614 * @param I2Cx I2C Instance.
615 * @param DutyCycle This parameter can be one of the following values:
616 * @arg @ref LL_I2C_DUTYCYCLE_2
617 * @arg @ref LL_I2C_DUTYCYCLE_16_9
618 * @retval None
619 */
LL_I2C_SetDutyCycle(I2C_TypeDef * I2Cx,uint32_t DutyCycle)620 __STATIC_INLINE void LL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle)
621 {
622 MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle);
623 }
624
625 /**
626 * @brief Get the Duty cycle (Fast mode only).
627 * @rmtoll CCR DUTY LL_I2C_GetDutyCycle
628 * @param I2Cx I2C Instance.
629 * @retval Returned value can be one of the following values:
630 * @arg @ref LL_I2C_DUTYCYCLE_2
631 * @arg @ref LL_I2C_DUTYCYCLE_16_9
632 */
LL_I2C_GetDutyCycle(I2C_TypeDef * I2Cx)633 __STATIC_INLINE uint32_t LL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx)
634 {
635 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY));
636 }
637
638 /**
639 * @brief Configure the I2C master clock speed mode.
640 * @rmtoll CCR FS LL_I2C_SetClockSpeedMode
641 * @param I2Cx I2C Instance.
642 * @param ClockSpeedMode This parameter can be one of the following values:
643 * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
644 * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
645 * @retval None
646 */
LL_I2C_SetClockSpeedMode(I2C_TypeDef * I2Cx,uint32_t ClockSpeedMode)647 __STATIC_INLINE void LL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode)
648 {
649 MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode);
650 }
651
652 /**
653 * @brief Get the the I2C master speed mode.
654 * @rmtoll CCR FS LL_I2C_GetClockSpeedMode
655 * @param I2Cx I2C Instance.
656 * @retval Returned value can be one of the following values:
657 * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
658 * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
659 */
LL_I2C_GetClockSpeedMode(I2C_TypeDef * I2Cx)660 __STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx)
661 {
662 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS));
663 }
664
665 /**
666 * @brief Configure the SCL, SDA rising time.
667 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
668 * @rmtoll TRISE TRISE LL_I2C_SetRiseTime
669 * @param I2Cx I2C Instance.
670 * @param RiseTime This parameter must be a value between Min_Data=0x02 and Max_Data=0x3F.
671 * @retval None
672 */
LL_I2C_SetRiseTime(I2C_TypeDef * I2Cx,uint32_t RiseTime)673 __STATIC_INLINE void LL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime)
674 {
675 MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, RiseTime);
676 }
677
678 /**
679 * @brief Get the SCL, SDA rising time.
680 * @rmtoll TRISE TRISE LL_I2C_GetRiseTime
681 * @param I2Cx I2C Instance.
682 * @retval Value between Min_Data=0x02 and Max_Data=0x3F
683 */
LL_I2C_GetRiseTime(I2C_TypeDef * I2Cx)684 __STATIC_INLINE uint32_t LL_I2C_GetRiseTime(I2C_TypeDef *I2Cx)
685 {
686 return (uint32_t)(READ_BIT(I2Cx->TRISE, I2C_TRISE_TRISE));
687 }
688
689 /**
690 * @brief Configure the SCL high and low period.
691 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
692 * @rmtoll CCR CCR LL_I2C_SetClockPeriod
693 * @param I2Cx I2C Instance.
694 * @param ClockPeriod This parameter must be a value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
695 * @retval None
696 */
LL_I2C_SetClockPeriod(I2C_TypeDef * I2Cx,uint32_t ClockPeriod)697 __STATIC_INLINE void LL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod)
698 {
699 MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod);
700 }
701
702 /**
703 * @brief Get the SCL high and low period.
704 * @rmtoll CCR CCR LL_I2C_GetClockPeriod
705 * @param I2Cx I2C Instance.
706 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
707 */
LL_I2C_GetClockPeriod(I2C_TypeDef * I2Cx)708 __STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx)
709 {
710 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR));
711 }
712
713 /**
714 * @brief Configure the SCL speed.
715 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
716 * @rmtoll CR2 FREQ LL_I2C_ConfigSpeed\n
717 * TRISE TRISE LL_I2C_ConfigSpeed\n
718 * CCR FS LL_I2C_ConfigSpeed\n
719 * CCR DUTY LL_I2C_ConfigSpeed\n
720 * CCR CCR LL_I2C_ConfigSpeed
721 * @param I2Cx I2C Instance.
722 * @param PeriphClock Peripheral Clock (in Hz)
723 * @param ClockSpeed This parameter must be a value lower than 400kHz (in Hz).
724 * @param DutyCycle This parameter can be one of the following values:
725 * @arg @ref LL_I2C_DUTYCYCLE_2
726 * @arg @ref LL_I2C_DUTYCYCLE_16_9
727 * @retval None
728 */
LL_I2C_ConfigSpeed(I2C_TypeDef * I2Cx,uint32_t PeriphClock,uint32_t ClockSpeed,uint32_t DutyCycle)729 __STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed,
730 uint32_t DutyCycle)
731 {
732 uint32_t freqrange = 0x0U;
733 uint32_t clockconfig = 0x0U;
734
735 /* Compute frequency range */
736 freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock);
737
738 /* Configure I2Cx: Frequency range register */
739 MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, freqrange);
740
741 /* Configure I2Cx: Rise Time register */
742 MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, __LL_I2C_RISE_TIME(freqrange, ClockSpeed));
743
744 /* Configure Speed mode, Duty Cycle and Clock control register value */
745 if (ClockSpeed > LL_I2C_MAX_SPEED_STANDARD)
746 {
747 /* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */
748 clockconfig = LL_I2C_CLOCK_SPEED_FAST_MODE | \
749 __LL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle) | \
750 DutyCycle;
751 }
752 else
753 {
754 /* Set Speed mode at standard for Clock Speed request in standard clock range */
755 clockconfig = LL_I2C_CLOCK_SPEED_STANDARD_MODE | \
756 __LL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed);
757 }
758
759 /* Configure I2Cx: Clock control register */
760 MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), clockconfig);
761 }
762
763 /**
764 * @brief Configure peripheral mode.
765 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
766 * SMBus feature is supported by the I2Cx Instance.
767 * @rmtoll CR1 SMBUS LL_I2C_SetMode\n
768 * CR1 SMBTYPE LL_I2C_SetMode\n
769 * CR1 ENARP LL_I2C_SetMode
770 * @param I2Cx I2C Instance.
771 * @param PeripheralMode This parameter can be one of the following values:
772 * @arg @ref LL_I2C_MODE_I2C
773 * @arg @ref LL_I2C_MODE_SMBUS_HOST
774 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
775 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
776 * @retval None
777 */
LL_I2C_SetMode(I2C_TypeDef * I2Cx,uint32_t PeripheralMode)778 __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
779 {
780 MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP, PeripheralMode);
781 }
782
783 /**
784 * @brief Get peripheral mode.
785 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
786 * SMBus feature is supported by the I2Cx Instance.
787 * @rmtoll CR1 SMBUS LL_I2C_GetMode\n
788 * CR1 SMBTYPE LL_I2C_GetMode\n
789 * CR1 ENARP LL_I2C_GetMode
790 * @param I2Cx I2C Instance.
791 * @retval Returned value can be one of the following values:
792 * @arg @ref LL_I2C_MODE_I2C
793 * @arg @ref LL_I2C_MODE_SMBUS_HOST
794 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
795 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
796 */
LL_I2C_GetMode(I2C_TypeDef * I2Cx)797 __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
798 {
799 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP));
800 }
801
802 /**
803 * @brief Enable SMBus alert (Host or Device mode)
804 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
805 * SMBus feature is supported by the I2Cx Instance.
806 * @note SMBus Device mode:
807 * - SMBus Alert pin is drived low and
808 * Alert Response Address Header acknowledge is enabled.
809 * SMBus Host mode:
810 * - SMBus Alert pin management is supported.
811 * @rmtoll CR1 ALERT LL_I2C_EnableSMBusAlert
812 * @param I2Cx I2C Instance.
813 * @retval None
814 */
LL_I2C_EnableSMBusAlert(I2C_TypeDef * I2Cx)815 __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
816 {
817 SET_BIT(I2Cx->CR1, I2C_CR1_ALERT);
818 }
819
820 /**
821 * @brief Disable SMBus alert (Host or Device mode)
822 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
823 * SMBus feature is supported by the I2Cx Instance.
824 * @note SMBus Device mode:
825 * - SMBus Alert pin is not drived (can be used as a standard GPIO) and
826 * Alert Response Address Header acknowledge is disabled.
827 * SMBus Host mode:
828 * - SMBus Alert pin management is not supported.
829 * @rmtoll CR1 ALERT LL_I2C_DisableSMBusAlert
830 * @param I2Cx I2C Instance.
831 * @retval None
832 */
LL_I2C_DisableSMBusAlert(I2C_TypeDef * I2Cx)833 __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
834 {
835 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERT);
836 }
837
838 /**
839 * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
840 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
841 * SMBus feature is supported by the I2Cx Instance.
842 * @rmtoll CR1 ALERT LL_I2C_IsEnabledSMBusAlert
843 * @param I2Cx I2C Instance.
844 * @retval State of bit (1 or 0).
845 */
LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef * I2Cx)846 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
847 {
848 return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERT) == (I2C_CR1_ALERT));
849 }
850
851 /**
852 * @brief Enable SMBus Packet Error Calculation (PEC).
853 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
854 * SMBus feature is supported by the I2Cx Instance.
855 * @rmtoll CR1 ENPEC LL_I2C_EnableSMBusPEC
856 * @param I2Cx I2C Instance.
857 * @retval None
858 */
LL_I2C_EnableSMBusPEC(I2C_TypeDef * I2Cx)859 __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
860 {
861 SET_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
862 }
863
864 /**
865 * @brief Disable SMBus Packet Error Calculation (PEC).
866 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
867 * SMBus feature is supported by the I2Cx Instance.
868 * @rmtoll CR1 ENPEC LL_I2C_DisableSMBusPEC
869 * @param I2Cx I2C Instance.
870 * @retval None
871 */
LL_I2C_DisableSMBusPEC(I2C_TypeDef * I2Cx)872 __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
873 {
874 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
875 }
876
877 /**
878 * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
879 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
880 * SMBus feature is supported by the I2Cx Instance.
881 * @rmtoll CR1 ENPEC LL_I2C_IsEnabledSMBusPEC
882 * @param I2Cx I2C Instance.
883 * @retval State of bit (1 or 0).
884 */
LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef * I2Cx)885 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
886 {
887 return (READ_BIT(I2Cx->CR1, I2C_CR1_ENPEC) == (I2C_CR1_ENPEC));
888 }
889
890 /**
891 * @}
892 */
893
894 /** @defgroup I2C_LL_EF_IT_Management IT_Management
895 * @{
896 */
897
898 /**
899 * @brief Enable TXE interrupt.
900 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_TX\n
901 * CR2 ITBUFEN LL_I2C_EnableIT_TX
902 * @param I2Cx I2C Instance.
903 * @retval None
904 */
LL_I2C_EnableIT_TX(I2C_TypeDef * I2Cx)905 __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
906 {
907 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
908 }
909
910 /**
911 * @brief Disable TXE interrupt.
912 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_TX\n
913 * CR2 ITBUFEN LL_I2C_DisableIT_TX
914 * @param I2Cx I2C Instance.
915 * @retval None
916 */
LL_I2C_DisableIT_TX(I2C_TypeDef * I2Cx)917 __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
918 {
919 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
920 }
921
922 /**
923 * @brief Check if the TXE Interrupt is enabled or disabled.
924 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_TX\n
925 * CR2 ITBUFEN LL_I2C_IsEnabledIT_TX
926 * @param I2Cx I2C Instance.
927 * @retval State of bit (1 or 0).
928 */
LL_I2C_IsEnabledIT_TX(I2C_TypeDef * I2Cx)929 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
930 {
931 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
932 }
933
934 /**
935 * @brief Enable RXNE interrupt.
936 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_RX\n
937 * CR2 ITBUFEN LL_I2C_EnableIT_RX
938 * @param I2Cx I2C Instance.
939 * @retval None
940 */
LL_I2C_EnableIT_RX(I2C_TypeDef * I2Cx)941 __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
942 {
943 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
944 }
945
946 /**
947 * @brief Disable RXNE interrupt.
948 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_RX\n
949 * CR2 ITBUFEN LL_I2C_DisableIT_RX
950 * @param I2Cx I2C Instance.
951 * @retval None
952 */
LL_I2C_DisableIT_RX(I2C_TypeDef * I2Cx)953 __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
954 {
955 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
956 }
957
958 /**
959 * @brief Check if the RXNE Interrupt is enabled or disabled.
960 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_RX\n
961 * CR2 ITBUFEN LL_I2C_IsEnabledIT_RX
962 * @param I2Cx I2C Instance.
963 * @retval State of bit (1 or 0).
964 */
LL_I2C_IsEnabledIT_RX(I2C_TypeDef * I2Cx)965 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
966 {
967 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
968 }
969
970 /**
971 * @brief Enable Events interrupts.
972 * @note Any of these events will generate interrupt :
973 * Start Bit (SB)
974 * Address sent, Address matched (ADDR)
975 * 10-bit header sent (ADD10)
976 * Stop detection (STOPF)
977 * Byte transfer finished (BTF)
978 *
979 * @note Any of these events will generate interrupt if Buffer interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_BUF()) :
980 * Receive buffer not empty (RXNE)
981 * Transmit buffer empty (TXE)
982 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_EVT
983 * @param I2Cx I2C Instance.
984 * @retval None
985 */
LL_I2C_EnableIT_EVT(I2C_TypeDef * I2Cx)986 __STATIC_INLINE void LL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx)
987 {
988 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
989 }
990
991 /**
992 * @brief Disable Events interrupts.
993 * @note Any of these events will generate interrupt :
994 * Start Bit (SB)
995 * Address sent, Address matched (ADDR)
996 * 10-bit header sent (ADD10)
997 * Stop detection (STOPF)
998 * Byte transfer finished (BTF)
999 * Receive buffer not empty (RXNE)
1000 * Transmit buffer empty (TXE)
1001 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_EVT
1002 * @param I2Cx I2C Instance.
1003 * @retval None
1004 */
LL_I2C_DisableIT_EVT(I2C_TypeDef * I2Cx)1005 __STATIC_INLINE void LL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx)
1006 {
1007 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
1008 }
1009
1010 /**
1011 * @brief Check if Events interrupts are enabled or disabled.
1012 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_EVT
1013 * @param I2Cx I2C Instance.
1014 * @retval State of bit (1 or 0).
1015 */
LL_I2C_IsEnabledIT_EVT(I2C_TypeDef * I2Cx)1016 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx)
1017 {
1018 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN) == (I2C_CR2_ITEVTEN));
1019 }
1020
1021 /**
1022 * @brief Enable Buffer interrupts.
1023 * @note Any of these Buffer events will generate interrupt if Events interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_EVT()) :
1024 * Receive buffer not empty (RXNE)
1025 * Transmit buffer empty (TXE)
1026 * @rmtoll CR2 ITBUFEN LL_I2C_EnableIT_BUF
1027 * @param I2Cx I2C Instance.
1028 * @retval None
1029 */
LL_I2C_EnableIT_BUF(I2C_TypeDef * I2Cx)1030 __STATIC_INLINE void LL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx)
1031 {
1032 SET_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
1033 }
1034
1035 /**
1036 * @brief Disable Buffer interrupts.
1037 * @note Any of these Buffer events will generate interrupt :
1038 * Receive buffer not empty (RXNE)
1039 * Transmit buffer empty (TXE)
1040 * @rmtoll CR2 ITBUFEN LL_I2C_DisableIT_BUF
1041 * @param I2Cx I2C Instance.
1042 * @retval None
1043 */
LL_I2C_DisableIT_BUF(I2C_TypeDef * I2Cx)1044 __STATIC_INLINE void LL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx)
1045 {
1046 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
1047 }
1048
1049 /**
1050 * @brief Check if Buffer interrupts are enabled or disabled.
1051 * @rmtoll CR2 ITBUFEN LL_I2C_IsEnabledIT_BUF
1052 * @param I2Cx I2C Instance.
1053 * @retval State of bit (1 or 0).
1054 */
LL_I2C_IsEnabledIT_BUF(I2C_TypeDef * I2Cx)1055 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx)
1056 {
1057 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN) == (I2C_CR2_ITBUFEN));
1058 }
1059
1060 /**
1061 * @brief Enable Error interrupts.
1062 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1063 * SMBus feature is supported by the I2Cx Instance.
1064 * @note Any of these errors will generate interrupt :
1065 * Bus Error detection (BERR)
1066 * Arbitration Loss (ARLO)
1067 * Acknowledge Failure(AF)
1068 * Overrun/Underrun (OVR)
1069 * SMBus Timeout detection (TIMEOUT)
1070 * SMBus PEC error detection (PECERR)
1071 * SMBus Alert pin event detection (SMBALERT)
1072 * @rmtoll CR2 ITERREN LL_I2C_EnableIT_ERR
1073 * @param I2Cx I2C Instance.
1074 * @retval None
1075 */
LL_I2C_EnableIT_ERR(I2C_TypeDef * I2Cx)1076 __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
1077 {
1078 SET_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
1079 }
1080
1081 /**
1082 * @brief Disable Error interrupts.
1083 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1084 * SMBus feature is supported by the I2Cx Instance.
1085 * @note Any of these errors will generate interrupt :
1086 * Bus Error detection (BERR)
1087 * Arbitration Loss (ARLO)
1088 * Acknowledge Failure(AF)
1089 * Overrun/Underrun (OVR)
1090 * SMBus Timeout detection (TIMEOUT)
1091 * SMBus PEC error detection (PECERR)
1092 * SMBus Alert pin event detection (SMBALERT)
1093 * @rmtoll CR2 ITERREN LL_I2C_DisableIT_ERR
1094 * @param I2Cx I2C Instance.
1095 * @retval None
1096 */
LL_I2C_DisableIT_ERR(I2C_TypeDef * I2Cx)1097 __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
1098 {
1099 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
1100 }
1101
1102 /**
1103 * @brief Check if Error interrupts are enabled or disabled.
1104 * @rmtoll CR2 ITERREN LL_I2C_IsEnabledIT_ERR
1105 * @param I2Cx I2C Instance.
1106 * @retval State of bit (1 or 0).
1107 */
LL_I2C_IsEnabledIT_ERR(I2C_TypeDef * I2Cx)1108 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
1109 {
1110 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITERREN) == (I2C_CR2_ITERREN));
1111 }
1112
1113 /**
1114 * @}
1115 */
1116
1117 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
1118 * @{
1119 */
1120
1121 /**
1122 * @brief Indicate the status of Transmit data register empty flag.
1123 * @note RESET: When next data is written in Transmit data register.
1124 * SET: When Transmit data register is empty.
1125 * @rmtoll SR1 TXE LL_I2C_IsActiveFlag_TXE
1126 * @param I2Cx I2C Instance.
1127 * @retval State of bit (1 or 0).
1128 */
LL_I2C_IsActiveFlag_TXE(I2C_TypeDef * I2Cx)1129 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
1130 {
1131 return (READ_BIT(I2Cx->SR1, I2C_SR1_TXE) == (I2C_SR1_TXE));
1132 }
1133
1134 /**
1135 * @brief Indicate the status of Byte Transfer Finished flag.
1136 * RESET: When Data byte transfer not done.
1137 * SET: When Data byte transfer succeeded.
1138 * @rmtoll SR1 BTF LL_I2C_IsActiveFlag_BTF
1139 * @param I2Cx I2C Instance.
1140 * @retval State of bit (1 or 0).
1141 */
LL_I2C_IsActiveFlag_BTF(I2C_TypeDef * I2Cx)1142 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx)
1143 {
1144 return (READ_BIT(I2Cx->SR1, I2C_SR1_BTF) == (I2C_SR1_BTF));
1145 }
1146
1147 /**
1148 * @brief Indicate the status of Receive data register not empty flag.
1149 * @note RESET: When Receive data register is read.
1150 * SET: When the received data is copied in Receive data register.
1151 * @rmtoll SR1 RXNE LL_I2C_IsActiveFlag_RXNE
1152 * @param I2Cx I2C Instance.
1153 * @retval State of bit (1 or 0).
1154 */
LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef * I2Cx)1155 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
1156 {
1157 return (READ_BIT(I2Cx->SR1, I2C_SR1_RXNE) == (I2C_SR1_RXNE));
1158 }
1159
1160 /**
1161 * @brief Indicate the status of Start Bit (master mode).
1162 * @note RESET: When No Start condition.
1163 * SET: When Start condition is generated.
1164 * @rmtoll SR1 SB LL_I2C_IsActiveFlag_SB
1165 * @param I2Cx I2C Instance.
1166 * @retval State of bit (1 or 0).
1167 */
LL_I2C_IsActiveFlag_SB(I2C_TypeDef * I2Cx)1168 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB(I2C_TypeDef *I2Cx)
1169 {
1170 return (READ_BIT(I2Cx->SR1, I2C_SR1_SB) == (I2C_SR1_SB));
1171 }
1172
1173 /**
1174 * @brief Indicate the status of Address sent (master mode) or Address matched flag (slave mode).
1175 * @note RESET: Clear default value.
1176 * SET: When the address is fully sent (master mode) or when the received slave address matched with one of the enabled slave address (slave mode).
1177 * @rmtoll SR1 ADDR LL_I2C_IsActiveFlag_ADDR
1178 * @param I2Cx I2C Instance.
1179 * @retval State of bit (1 or 0).
1180 */
LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef * I2Cx)1181 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
1182 {
1183 return (READ_BIT(I2Cx->SR1, I2C_SR1_ADDR) == (I2C_SR1_ADDR));
1184 }
1185
1186 /**
1187 * @brief Indicate the status of 10-bit header sent (master mode).
1188 * @note RESET: When no ADD10 event occurred.
1189 * SET: When the master has sent the first address byte (header).
1190 * @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10
1191 * @param I2Cx I2C Instance.
1192 * @retval State of bit (1 or 0).
1193 */
LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef * I2Cx)1194 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef *I2Cx)
1195 {
1196 return (READ_BIT(I2Cx->SR1, I2C_SR1_ADD10) == (I2C_SR1_ADD10));
1197 }
1198
1199 /**
1200 * @brief Indicate the status of Acknowledge failure flag.
1201 * @note RESET: No acknowledge failure.
1202 * SET: When an acknowledge failure is received after a byte transmission.
1203 * @rmtoll SR1 AF LL_I2C_IsActiveFlag_AF
1204 * @param I2Cx I2C Instance.
1205 * @retval State of bit (1 or 0).
1206 */
LL_I2C_IsActiveFlag_AF(I2C_TypeDef * I2Cx)1207 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx)
1208 {
1209 return (READ_BIT(I2Cx->SR1, I2C_SR1_AF) == (I2C_SR1_AF));
1210 }
1211
1212 /**
1213 * @brief Indicate the status of Stop detection flag (slave mode).
1214 * @note RESET: Clear default value.
1215 * SET: When a Stop condition is detected.
1216 * @rmtoll SR1 STOPF LL_I2C_IsActiveFlag_STOP
1217 * @param I2Cx I2C Instance.
1218 * @retval State of bit (1 or 0).
1219 */
LL_I2C_IsActiveFlag_STOP(I2C_TypeDef * I2Cx)1220 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
1221 {
1222 return (READ_BIT(I2Cx->SR1, I2C_SR1_STOPF) == (I2C_SR1_STOPF));
1223 }
1224
1225 /**
1226 * @brief Indicate the status of Bus error flag.
1227 * @note RESET: Clear default value.
1228 * SET: When a misplaced Start or Stop condition is detected.
1229 * @rmtoll SR1 BERR LL_I2C_IsActiveFlag_BERR
1230 * @param I2Cx I2C Instance.
1231 * @retval State of bit (1 or 0).
1232 */
LL_I2C_IsActiveFlag_BERR(I2C_TypeDef * I2Cx)1233 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
1234 {
1235 return (READ_BIT(I2Cx->SR1, I2C_SR1_BERR) == (I2C_SR1_BERR));
1236 }
1237
1238 /**
1239 * @brief Indicate the status of Arbitration lost flag.
1240 * @note RESET: Clear default value.
1241 * SET: When arbitration lost.
1242 * @rmtoll SR1 ARLO LL_I2C_IsActiveFlag_ARLO
1243 * @param I2Cx I2C Instance.
1244 * @retval State of bit (1 or 0).
1245 */
LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef * I2Cx)1246 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
1247 {
1248 return (READ_BIT(I2Cx->SR1, I2C_SR1_ARLO) == (I2C_SR1_ARLO));
1249 }
1250
1251 /**
1252 * @brief Indicate the status of Overrun/Underrun flag.
1253 * @note RESET: Clear default value.
1254 * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
1255 * @rmtoll SR1 OVR LL_I2C_IsActiveFlag_OVR
1256 * @param I2Cx I2C Instance.
1257 * @retval State of bit (1 or 0).
1258 */
LL_I2C_IsActiveFlag_OVR(I2C_TypeDef * I2Cx)1259 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
1260 {
1261 return (READ_BIT(I2Cx->SR1, I2C_SR1_OVR) == (I2C_SR1_OVR));
1262 }
1263
1264 /**
1265 * @brief Indicate the status of SMBus PEC error flag in reception.
1266 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1267 * SMBus feature is supported by the I2Cx Instance.
1268 * @rmtoll SR1 PECERR LL_I2C_IsActiveSMBusFlag_PECERR
1269 * @param I2Cx I2C Instance.
1270 * @retval State of bit (1 or 0).
1271 */
LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef * I2Cx)1272 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
1273 {
1274 return (READ_BIT(I2Cx->SR1, I2C_SR1_PECERR) == (I2C_SR1_PECERR));
1275 }
1276
1277 /**
1278 * @brief Indicate the status of SMBus Timeout detection flag.
1279 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1280 * SMBus feature is supported by the I2Cx Instance.
1281 * @rmtoll SR1 TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
1282 * @param I2Cx I2C Instance.
1283 * @retval State of bit (1 or 0).
1284 */
LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef * I2Cx)1285 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
1286 {
1287 return (READ_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT) == (I2C_SR1_TIMEOUT));
1288 }
1289
1290 /**
1291 * @brief Indicate the status of SMBus alert flag.
1292 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1293 * SMBus feature is supported by the I2Cx Instance.
1294 * @rmtoll SR1 SMBALERT LL_I2C_IsActiveSMBusFlag_ALERT
1295 * @param I2Cx I2C Instance.
1296 * @retval State of bit (1 or 0).
1297 */
LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef * I2Cx)1298 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
1299 {
1300 return (READ_BIT(I2Cx->SR1, I2C_SR1_SMBALERT) == (I2C_SR1_SMBALERT));
1301 }
1302
1303 /**
1304 * @brief Indicate the status of Bus Busy flag.
1305 * @note RESET: Clear default value.
1306 * SET: When a Start condition is detected.
1307 * @rmtoll SR2 BUSY LL_I2C_IsActiveFlag_BUSY
1308 * @param I2Cx I2C Instance.
1309 * @retval State of bit (1 or 0).
1310 */
LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef * I2Cx)1311 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
1312 {
1313 return (READ_BIT(I2Cx->SR2, I2C_SR2_BUSY) == (I2C_SR2_BUSY));
1314 }
1315
1316 /**
1317 * @brief Indicate the status of Dual flag.
1318 * @note RESET: Received address matched with OAR1.
1319 * SET: Received address matched with OAR2.
1320 * @rmtoll SR2 DUALF LL_I2C_IsActiveFlag_DUAL
1321 * @param I2Cx I2C Instance.
1322 * @retval State of bit (1 or 0).
1323 */
LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef * I2Cx)1324 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx)
1325 {
1326 return (READ_BIT(I2Cx->SR2, I2C_SR2_DUALF) == (I2C_SR2_DUALF));
1327 }
1328
1329 /**
1330 * @brief Indicate the status of SMBus Host address reception (Slave mode).
1331 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1332 * SMBus feature is supported by the I2Cx Instance.
1333 * @note RESET: No SMBus Host address
1334 * SET: SMBus Host address received.
1335 * @note This status is cleared by hardware after a STOP condition or repeated START condition.
1336 * @rmtoll SR2 SMBHOST LL_I2C_IsActiveSMBusFlag_SMBHOST
1337 * @param I2Cx I2C Instance.
1338 * @retval State of bit (1 or 0).
1339 */
LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef * I2Cx)1340 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx)
1341 {
1342 return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBHOST) == (I2C_SR2_SMBHOST));
1343 }
1344
1345 /**
1346 * @brief Indicate the status of SMBus Device default address reception (Slave mode).
1347 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1348 * SMBus feature is supported by the I2Cx Instance.
1349 * @note RESET: No SMBus Device default address
1350 * SET: SMBus Device default address received.
1351 * @note This status is cleared by hardware after a STOP condition or repeated START condition.
1352 * @rmtoll SR2 SMBDEFAULT LL_I2C_IsActiveSMBusFlag_SMBDEFAULT
1353 * @param I2Cx I2C Instance.
1354 * @retval State of bit (1 or 0).
1355 */
LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef * I2Cx)1356 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx)
1357 {
1358 return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBDEFAULT) == (I2C_SR2_SMBDEFAULT));
1359 }
1360
1361 /**
1362 * @brief Indicate the status of General call address reception (Slave mode).
1363 * @note RESET: No General call address
1364 * SET: General call address received.
1365 * @note This status is cleared by hardware after a STOP condition or repeated START condition.
1366 * @rmtoll SR2 GENCALL LL_I2C_IsActiveFlag_GENCALL
1367 * @param I2Cx I2C Instance.
1368 * @retval State of bit (1 or 0).
1369 */
LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef * I2Cx)1370 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx)
1371 {
1372 return (READ_BIT(I2Cx->SR2, I2C_SR2_GENCALL) == (I2C_SR2_GENCALL));
1373 }
1374
1375 /**
1376 * @brief Indicate the status of Master/Slave flag.
1377 * @note RESET: Slave Mode.
1378 * SET: Master Mode.
1379 * @rmtoll SR2 MSL LL_I2C_IsActiveFlag_MSL
1380 * @param I2Cx I2C Instance.
1381 * @retval State of bit (1 or 0).
1382 */
LL_I2C_IsActiveFlag_MSL(I2C_TypeDef * I2Cx)1383 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx)
1384 {
1385 return (READ_BIT(I2Cx->SR2, I2C_SR2_MSL) == (I2C_SR2_MSL));
1386 }
1387
1388 /**
1389 * @brief Clear Address Matched flag.
1390 * @note Clearing this flag is done by a read access to the I2Cx_SR1
1391 * register followed by a read access to the I2Cx_SR2 register.
1392 * @rmtoll SR1 ADDR LL_I2C_ClearFlag_ADDR
1393 * @param I2Cx I2C Instance.
1394 * @retval None
1395 */
LL_I2C_ClearFlag_ADDR(I2C_TypeDef * I2Cx)1396 __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
1397 {
1398 __IO uint32_t tmpreg;
1399 tmpreg = I2Cx->SR1;
1400 (void) tmpreg;
1401 tmpreg = I2Cx->SR2;
1402 (void) tmpreg;
1403 }
1404
1405 /**
1406 * @brief Clear Acknowledge failure flag.
1407 * @rmtoll SR1 AF LL_I2C_ClearFlag_AF
1408 * @param I2Cx I2C Instance.
1409 * @retval None
1410 */
LL_I2C_ClearFlag_AF(I2C_TypeDef * I2Cx)1411 __STATIC_INLINE void LL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx)
1412 {
1413 CLEAR_BIT(I2Cx->SR1, I2C_SR1_AF);
1414 }
1415
1416 /**
1417 * @brief Clear Stop detection flag.
1418 * @note Clearing this flag is done by a read access to the I2Cx_SR1
1419 * register followed by a write access to I2Cx_CR1 register.
1420 * @rmtoll SR1 STOPF LL_I2C_ClearFlag_STOP\n
1421 * CR1 PE LL_I2C_ClearFlag_STOP
1422 * @param I2Cx I2C Instance.
1423 * @retval None
1424 */
LL_I2C_ClearFlag_STOP(I2C_TypeDef * I2Cx)1425 __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
1426 {
1427 __IO uint32_t tmpreg;
1428 tmpreg = I2Cx->SR1;
1429 (void) tmpreg;
1430 SET_BIT(I2Cx->CR1, I2C_CR1_PE);
1431 }
1432
1433 /**
1434 * @brief Clear Bus error flag.
1435 * @rmtoll SR1 BERR LL_I2C_ClearFlag_BERR
1436 * @param I2Cx I2C Instance.
1437 * @retval None
1438 */
LL_I2C_ClearFlag_BERR(I2C_TypeDef * I2Cx)1439 __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
1440 {
1441 CLEAR_BIT(I2Cx->SR1, I2C_SR1_BERR);
1442 }
1443
1444 /**
1445 * @brief Clear Arbitration lost flag.
1446 * @rmtoll SR1 ARLO LL_I2C_ClearFlag_ARLO
1447 * @param I2Cx I2C Instance.
1448 * @retval None
1449 */
LL_I2C_ClearFlag_ARLO(I2C_TypeDef * I2Cx)1450 __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
1451 {
1452 CLEAR_BIT(I2Cx->SR1, I2C_SR1_ARLO);
1453 }
1454
1455 /**
1456 * @brief Clear Overrun/Underrun flag.
1457 * @rmtoll SR1 OVR LL_I2C_ClearFlag_OVR
1458 * @param I2Cx I2C Instance.
1459 * @retval None
1460 */
LL_I2C_ClearFlag_OVR(I2C_TypeDef * I2Cx)1461 __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
1462 {
1463 CLEAR_BIT(I2Cx->SR1, I2C_SR1_OVR);
1464 }
1465
1466 /**
1467 * @brief Clear SMBus PEC error flag.
1468 * @rmtoll SR1 PECERR LL_I2C_ClearSMBusFlag_PECERR
1469 * @param I2Cx I2C Instance.
1470 * @retval None
1471 */
LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef * I2Cx)1472 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
1473 {
1474 CLEAR_BIT(I2Cx->SR1, I2C_SR1_PECERR);
1475 }
1476
1477 /**
1478 * @brief Clear SMBus Timeout detection flag.
1479 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1480 * SMBus feature is supported by the I2Cx Instance.
1481 * @rmtoll SR1 TIMEOUT LL_I2C_ClearSMBusFlag_TIMEOUT
1482 * @param I2Cx I2C Instance.
1483 * @retval None
1484 */
LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef * I2Cx)1485 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
1486 {
1487 CLEAR_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT);
1488 }
1489
1490 /**
1491 * @brief Clear SMBus Alert flag.
1492 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1493 * SMBus feature is supported by the I2Cx Instance.
1494 * @rmtoll SR1 SMBALERT LL_I2C_ClearSMBusFlag_ALERT
1495 * @param I2Cx I2C Instance.
1496 * @retval None
1497 */
LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef * I2Cx)1498 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
1499 {
1500 CLEAR_BIT(I2Cx->SR1, I2C_SR1_SMBALERT);
1501 }
1502
1503 /**
1504 * @}
1505 */
1506
1507 /** @defgroup I2C_LL_EF_Data_Management Data_Management
1508 * @{
1509 */
1510
1511 /**
1512 * @brief Enable Reset of I2C peripheral.
1513 * @rmtoll CR1 SWRST LL_I2C_EnableReset
1514 * @param I2Cx I2C Instance.
1515 * @retval None
1516 */
LL_I2C_EnableReset(I2C_TypeDef * I2Cx)1517 __STATIC_INLINE void LL_I2C_EnableReset(I2C_TypeDef *I2Cx)
1518 {
1519 SET_BIT(I2Cx->CR1, I2C_CR1_SWRST);
1520 }
1521
1522 /**
1523 * @brief Disable Reset of I2C peripheral.
1524 * @rmtoll CR1 SWRST LL_I2C_DisableReset
1525 * @param I2Cx I2C Instance.
1526 * @retval None
1527 */
LL_I2C_DisableReset(I2C_TypeDef * I2Cx)1528 __STATIC_INLINE void LL_I2C_DisableReset(I2C_TypeDef *I2Cx)
1529 {
1530 CLEAR_BIT(I2Cx->CR1, I2C_CR1_SWRST);
1531 }
1532
1533 /**
1534 * @brief Check if the I2C peripheral is under reset state or not.
1535 * @rmtoll CR1 SWRST LL_I2C_IsResetEnabled
1536 * @param I2Cx I2C Instance.
1537 * @retval State of bit (1 or 0).
1538 */
LL_I2C_IsResetEnabled(I2C_TypeDef * I2Cx)1539 __STATIC_INLINE uint32_t LL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx)
1540 {
1541 return (READ_BIT(I2Cx->CR1, I2C_CR1_SWRST) == (I2C_CR1_SWRST));
1542 }
1543
1544 /**
1545 * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
1546 * @note Usage in Slave or Master mode.
1547 * @rmtoll CR1 ACK LL_I2C_AcknowledgeNextData
1548 * @param I2Cx I2C Instance.
1549 * @param TypeAcknowledge This parameter can be one of the following values:
1550 * @arg @ref LL_I2C_ACK
1551 * @arg @ref LL_I2C_NACK
1552 * @retval None
1553 */
LL_I2C_AcknowledgeNextData(I2C_TypeDef * I2Cx,uint32_t TypeAcknowledge)1554 __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
1555 {
1556 MODIFY_REG(I2Cx->CR1, I2C_CR1_ACK, TypeAcknowledge);
1557 }
1558
1559 /**
1560 * @brief Generate a START or RESTART condition
1561 * @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
1562 * This action has no effect when RELOAD is set.
1563 * @rmtoll CR1 START LL_I2C_GenerateStartCondition
1564 * @param I2Cx I2C Instance.
1565 * @retval None
1566 */
LL_I2C_GenerateStartCondition(I2C_TypeDef * I2Cx)1567 __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
1568 {
1569 SET_BIT(I2Cx->CR1, I2C_CR1_START);
1570 }
1571
1572 /**
1573 * @brief Generate a STOP condition after the current byte transfer (master mode).
1574 * @rmtoll CR1 STOP LL_I2C_GenerateStopCondition
1575 * @param I2Cx I2C Instance.
1576 * @retval None
1577 */
LL_I2C_GenerateStopCondition(I2C_TypeDef * I2Cx)1578 __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
1579 {
1580 SET_BIT(I2Cx->CR1, I2C_CR1_STOP);
1581 }
1582
1583 /**
1584 * @brief Enable bit POS (master/host mode).
1585 * @note In that case, the ACK bit controls the (N)ACK of the next byte received or the PEC bit indicates that the next byte in shift register is a PEC.
1586 * @rmtoll CR1 POS LL_I2C_EnableBitPOS
1587 * @param I2Cx I2C Instance.
1588 * @retval None
1589 */
LL_I2C_EnableBitPOS(I2C_TypeDef * I2Cx)1590 __STATIC_INLINE void LL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx)
1591 {
1592 SET_BIT(I2Cx->CR1, I2C_CR1_POS);
1593 }
1594
1595 /**
1596 * @brief Disable bit POS (master/host mode).
1597 * @note In that case, the ACK bit controls the (N)ACK of the current byte received or the PEC bit indicates that the current byte in shift register is a PEC.
1598 * @rmtoll CR1 POS LL_I2C_DisableBitPOS
1599 * @param I2Cx I2C Instance.
1600 * @retval None
1601 */
LL_I2C_DisableBitPOS(I2C_TypeDef * I2Cx)1602 __STATIC_INLINE void LL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx)
1603 {
1604 CLEAR_BIT(I2Cx->CR1, I2C_CR1_POS);
1605 }
1606
1607 /**
1608 * @brief Check if bit POS is enabled or disabled.
1609 * @rmtoll CR1 POS LL_I2C_IsEnabledBitPOS
1610 * @param I2Cx I2C Instance.
1611 * @retval State of bit (1 or 0).
1612 */
LL_I2C_IsEnabledBitPOS(I2C_TypeDef * I2Cx)1613 __STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx)
1614 {
1615 return (READ_BIT(I2Cx->CR1, I2C_CR1_POS) == (I2C_CR1_POS));
1616 }
1617
1618 /**
1619 * @brief Indicate the value of transfer direction.
1620 * @note RESET: Bus is in read transfer (peripheral point of view).
1621 * SET: Bus is in write transfer (peripheral point of view).
1622 * @rmtoll SR2 TRA LL_I2C_GetTransferDirection
1623 * @param I2Cx I2C Instance.
1624 * @retval Returned value can be one of the following values:
1625 * @arg @ref LL_I2C_DIRECTION_WRITE
1626 * @arg @ref LL_I2C_DIRECTION_READ
1627 */
LL_I2C_GetTransferDirection(I2C_TypeDef * I2Cx)1628 __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
1629 {
1630 return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_TRA));
1631 }
1632
1633 /**
1634 * @brief Enable DMA last transfer.
1635 * @note This action mean that next DMA EOT is the last transfer.
1636 * @rmtoll CR2 LAST LL_I2C_EnableLastDMA
1637 * @param I2Cx I2C Instance.
1638 * @retval None
1639 */
LL_I2C_EnableLastDMA(I2C_TypeDef * I2Cx)1640 __STATIC_INLINE void LL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx)
1641 {
1642 SET_BIT(I2Cx->CR2, I2C_CR2_LAST);
1643 }
1644
1645 /**
1646 * @brief Disable DMA last transfer.
1647 * @note This action mean that next DMA EOT is not the last transfer.
1648 * @rmtoll CR2 LAST LL_I2C_DisableLastDMA
1649 * @param I2Cx I2C Instance.
1650 * @retval None
1651 */
LL_I2C_DisableLastDMA(I2C_TypeDef * I2Cx)1652 __STATIC_INLINE void LL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx)
1653 {
1654 CLEAR_BIT(I2Cx->CR2, I2C_CR2_LAST);
1655 }
1656
1657 /**
1658 * @brief Check if DMA last transfer is enabled or disabled.
1659 * @rmtoll CR2 LAST LL_I2C_IsEnabledLastDMA
1660 * @param I2Cx I2C Instance.
1661 * @retval State of bit (1 or 0).
1662 */
LL_I2C_IsEnabledLastDMA(I2C_TypeDef * I2Cx)1663 __STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx)
1664 {
1665 return (READ_BIT(I2Cx->CR2, I2C_CR2_LAST) == (I2C_CR2_LAST));
1666 }
1667
1668 /**
1669 * @brief Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
1670 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1671 * SMBus feature is supported by the I2Cx Instance.
1672 * @note This feature is cleared by hardware when the PEC byte is transferred or compared,
1673 * or by a START or STOP condition, it is also cleared by software.
1674 * @rmtoll CR1 PEC LL_I2C_EnableSMBusPECCompare
1675 * @param I2Cx I2C Instance.
1676 * @retval None
1677 */
LL_I2C_EnableSMBusPECCompare(I2C_TypeDef * I2Cx)1678 __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
1679 {
1680 SET_BIT(I2Cx->CR1, I2C_CR1_PEC);
1681 }
1682
1683 /**
1684 * @brief Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
1685 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1686 * SMBus feature is supported by the I2Cx Instance.
1687 * @rmtoll CR1 PEC LL_I2C_DisableSMBusPECCompare
1688 * @param I2Cx I2C Instance.
1689 * @retval None
1690 */
LL_I2C_DisableSMBusPECCompare(I2C_TypeDef * I2Cx)1691 __STATIC_INLINE void LL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx)
1692 {
1693 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PEC);
1694 }
1695
1696 /**
1697 * @brief Check if the SMBus Packet Error byte transfer or internal comparison is requested or not.
1698 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1699 * SMBus feature is supported by the I2Cx Instance.
1700 * @rmtoll CR1 PEC LL_I2C_IsEnabledSMBusPECCompare
1701 * @param I2Cx I2C Instance.
1702 * @retval State of bit (1 or 0).
1703 */
LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef * I2Cx)1704 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
1705 {
1706 return (READ_BIT(I2Cx->CR1, I2C_CR1_PEC) == (I2C_CR1_PEC));
1707 }
1708
1709 /**
1710 * @brief Get the SMBus Packet Error byte calculated.
1711 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1712 * SMBus feature is supported by the I2Cx Instance.
1713 * @rmtoll SR2 PEC LL_I2C_GetSMBusPEC
1714 * @param I2Cx I2C Instance.
1715 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1716 */
LL_I2C_GetSMBusPEC(I2C_TypeDef * I2Cx)1717 __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
1718 {
1719 return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_PEC) >> I2C_SR2_PEC_Pos);
1720 }
1721
1722 /**
1723 * @brief Read Receive Data register.
1724 * @rmtoll DR DR LL_I2C_ReceiveData8
1725 * @param I2Cx I2C Instance.
1726 * @retval Value between Min_Data=0x0 and Max_Data=0xFF
1727 */
LL_I2C_ReceiveData8(I2C_TypeDef * I2Cx)1728 __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
1729 {
1730 return (uint8_t)(READ_BIT(I2Cx->DR, I2C_DR_DR));
1731 }
1732
1733 /**
1734 * @brief Write in Transmit Data Register .
1735 * @rmtoll DR DR LL_I2C_TransmitData8
1736 * @param I2Cx I2C Instance.
1737 * @param Data Value between Min_Data=0x0 and Max_Data=0xFF
1738 * @retval None
1739 */
LL_I2C_TransmitData8(I2C_TypeDef * I2Cx,uint8_t Data)1740 __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
1741 {
1742 MODIFY_REG(I2Cx->DR, I2C_DR_DR, Data);
1743 }
1744
1745 /**
1746 * @}
1747 */
1748
1749 #if defined(USE_FULL_LL_DRIVER)
1750 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
1751 * @{
1752 */
1753
1754 uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
1755 uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
1756 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
1757
1758
1759 /**
1760 * @}
1761 */
1762 #endif /* USE_FULL_LL_DRIVER */
1763
1764 /**
1765 * @}
1766 */
1767
1768 /**
1769 * @}
1770 */
1771
1772 #endif /* I2C1 || I2C2 */
1773
1774 /**
1775 * @}
1776 */
1777
1778 #ifdef __cplusplus
1779 }
1780 #endif
1781
1782 #endif /* __STM32L1xx_LL_I2C_H */
1783
1784 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1785
