1 /**
2 ******************************************************************************
3 * @file stm32l0xx_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32L0xx_LL_PWR_H
21 #define __STM32L0xx_LL_PWR_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32l0xx.h"
29
30 /** @addtogroup STM32L0xx_LL_Driver
31 * @{
32 */
33
34 #if defined(PWR)
35
36 /** @defgroup PWR_LL PWR
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /* Exported types ------------------------------------------------------------*/
45 /* Exported constants --------------------------------------------------------*/
46 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
47 * @{
48 */
49
50 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
51 * @brief Flags defines which can be used with LL_PWR_WriteReg function
52 * @{
53 */
54 #define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
55 #define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
56 /**
57 * @}
58 */
59
60 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
61 * @brief Flags defines which can be used with LL_PWR_ReadReg function
62 * @{
63 */
64 #define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
65 #define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
66 #if defined(PWR_PVD_SUPPORT)
67 #define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
68 #endif /* PWR_PVD_SUPPORT */
69 #if defined(PWR_CSR_VREFINTRDYF)
70 #define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF /*!< VREFINT ready flag */
71 #endif /* PWR_CSR_VREFINTRDYF */
72 #define LL_PWR_CSR_VOS PWR_CSR_VOSF /*!< Voltage scaling select flag */
73 #define LL_PWR_CSR_REGLPF PWR_CSR_REGLPF /*!< Regulator low power flag */
74 #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */
75 #define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */
76 #if defined(PWR_CSR_EWUP3)
77 #define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */
78 #endif /* PWR_CSR_EWUP3 */
79 /**
80 * @}
81 */
82
83 /** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage
84 * @{
85 */
86 #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS_0) /*!< 1.8V (range 1) */
87 #define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR_VOS_1) /*!< 1.5V (range 2) */
88 #define LL_PWR_REGU_VOLTAGE_SCALE3 (PWR_CR_VOS_0 | PWR_CR_VOS_1) /*!< 1.2V (range 3) */
89 /**
90 * @}
91 */
92
93 /** @defgroup PWR_LL_EC_MODE_PWR Mode Power
94 * @{
95 */
96 #define LL_PWR_MODE_STOP 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */
97 #define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
98 /**
99 * @}
100 */
101
102 /** @defgroup PWR_LL_EC_REGU_MODE_LP_MODES Regulator Mode In Low Power Modes
103 * @{
104 */
105 #define LL_PWR_REGU_LPMODES_MAIN 0x00000000U /*!< Voltage regulator in main mode during deepsleep/sleep/low-power run mode */
106 #define LL_PWR_REGU_LPMODES_LOW_POWER (PWR_CR_LPSDSR) /*!< Voltage regulator in low-power mode during deepsleep/sleep/low-power run mode */
107 /**
108 * @}
109 */
110 #if defined(PWR_CR_LPDS)
111 /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
112 * @{
113 */
114 #define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage regulator in main mode during deepsleep mode when PWR_CR_LPSDSR = 0 */
115 #define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage regulator in low-power mode during deepsleep mode when PWR_CR_LPSDSR = 0 */
116 /**
117 * @}
118 */
119 #endif /* PWR_CR_LPDS */
120
121 #if defined(PWR_PVD_SUPPORT)
122 /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
123 * @{
124 */
125 #define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 1.9 V */
126 #define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.1 V */
127 #define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.3 V */
128 #define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */
129 #define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.7 V */
130 #define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.9 V */
131 #define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 3.1 V */
132 #define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< External input analog voltage (Compare internally to VREFINT) */
133 /**
134 * @}
135 */
136 #endif /* PWR_PVD_SUPPORT */
137 /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
138 * @{
139 */
140 #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */
141 #define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC13 */
142 #if defined(PWR_CSR_EWUP3)
143 #define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PE6 or PA2 according to device */
144 #endif /* PWR_CSR_EWUP3 */
145 /**
146 * @}
147 */
148
149 /**
150 * @}
151 */
152
153
154 /* Exported macro ------------------------------------------------------------*/
155 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
156 * @{
157 */
158
159 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
160 * @{
161 */
162
163 /**
164 * @brief Write a value in PWR register
165 * @param __REG__ Register to be written
166 * @param __VALUE__ Value to be written in the register
167 * @retval None
168 */
169 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
170
171 /**
172 * @brief Read a value in PWR register
173 * @param __REG__ Register to be read
174 * @retval Register value
175 */
176 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
177 /**
178 * @}
179 */
180
181 /**
182 * @}
183 */
184
185 /* Exported functions --------------------------------------------------------*/
186 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
187 * @{
188 */
189
190 /** @defgroup PWR_LL_EF_Configuration Configuration
191 * @{
192 */
193 /**
194 * @brief Switch the regulator from main mode to low-power mode
195 * @rmtoll CR LPRUN LL_PWR_EnableLowPowerRunMode
196 * @note Remind to set the regulator to low power before enabling
197 * LowPower run mode (bit @ref LL_PWR_REGU_LPMODES_LOW_POWER).
198 * @retval None
199 */
LL_PWR_EnableLowPowerRunMode(void)200 __STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void)
201 {
202 SET_BIT(PWR->CR, PWR_CR_LPRUN);
203 }
204
205 /**
206 * @brief Switch the regulator from low-power mode to main mode
207 * @rmtoll CR LPRUN LL_PWR_DisableLowPowerRunMode
208 * @retval None
209 */
LL_PWR_DisableLowPowerRunMode(void)210 __STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void)
211 {
212 CLEAR_BIT(PWR->CR, PWR_CR_LPRUN);
213 }
214
215 /**
216 * @brief Check if the regulator is in low-power mode
217 * @rmtoll CR LPRUN LL_PWR_IsEnabledLowPowerRunMode
218 * @retval State of bit (1 or 0).
219 */
LL_PWR_IsEnabledLowPowerRunMode(void)220 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void)
221 {
222 return (READ_BIT(PWR->CR, PWR_CR_LPRUN) == (PWR_CR_LPRUN));
223 }
224
225 /**
226 * @brief Set voltage regulator to low-power and switch from
227 * run main mode to run low-power mode.
228 * @rmtoll CR LPSDSR LL_PWR_EnterLowPowerRunMode\n
229 * CR LPRUN LL_PWR_EnterLowPowerRunMode
230 * @note This "high level" function is introduced to provide functional
231 * compatibility with other families. Notice that the two registers
232 * have to be written sequentially, so this function is not atomic.
233 * To assure atomicity you can call separately the following functions:
234 * - @ref LL_PWR_SetRegulModeLP(@ref LL_PWR_REGU_LPMODES_LOW_POWER);
235 * - @ref LL_PWR_EnableLowPowerRunMode();
236 * @retval None
237 */
LL_PWR_EnterLowPowerRunMode(void)238 __STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void)
239 {
240 SET_BIT(PWR->CR, PWR_CR_LPSDSR); /* => LL_PWR_SetRegulModeLP(LL_PWR_REGU_LPMODES_LOW_POWER) */
241 SET_BIT(PWR->CR, PWR_CR_LPRUN); /* => LL_PWR_EnableLowPowerRunMode() */
242 }
243
244 /**
245 * @brief Set voltage regulator to main and switch from
246 * run main mode to low-power mode.
247 * @rmtoll CR LPSDSR LL_PWR_ExitLowPowerRunMode\n
248 * CR LPRUN LL_PWR_ExitLowPowerRunMode
249 * @note This "high level" function is introduced to provide functional
250 * compatibility with other families. Notice that the two registers
251 * have to be written sequentially, so this function is not atomic.
252 * To assure atomicity you can call separately the following functions:
253 * - @ref LL_PWR_DisableLowPowerRunMode();
254 * - @ref LL_PWR_SetRegulModeLP(@ref LL_PWR_REGU_LPMODES_MAIN);
255 * @retval None
256 */
LL_PWR_ExitLowPowerRunMode(void)257 __STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void)
258 {
259 CLEAR_BIT(PWR->CR, PWR_CR_LPRUN); /* => LL_PWR_DisableLowPowerRunMode() */
260 CLEAR_BIT(PWR->CR, PWR_CR_LPSDSR); /* => LL_PWR_SetRegulModeLP(LL_PWR_REGU_LPMODES_MAIN) */
261 }
262 /**
263 * @brief Set the main internal regulator output voltage
264 * @rmtoll CR VOS LL_PWR_SetRegulVoltageScaling
265 * @param VoltageScaling This parameter can be one of the following values:
266 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
267 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
268 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
269 * @retval None
270 */
LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)271 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
272 {
273 MODIFY_REG(PWR->CR, PWR_CR_VOS, VoltageScaling);
274 }
275
276 /**
277 * @brief Get the main internal regulator output voltage
278 * @rmtoll CR VOS LL_PWR_GetRegulVoltageScaling
279 * @retval Returned value can be one of the following values:
280 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
281 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
282 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
283 */
LL_PWR_GetRegulVoltageScaling(void)284 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
285 {
286 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_VOS));
287 }
288
289 /**
290 * @brief Enable access to the backup domain
291 * @rmtoll CR DBP LL_PWR_EnableBkUpAccess
292 * @retval None
293 */
LL_PWR_EnableBkUpAccess(void)294 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
295 {
296 SET_BIT(PWR->CR, PWR_CR_DBP);
297 }
298
299 /**
300 * @brief Disable access to the backup domain
301 * @rmtoll CR DBP LL_PWR_DisableBkUpAccess
302 * @retval None
303 */
LL_PWR_DisableBkUpAccess(void)304 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
305 {
306 CLEAR_BIT(PWR->CR, PWR_CR_DBP);
307 }
308
309 /**
310 * @brief Check if the backup domain is enabled
311 * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
312 * @retval State of bit (1 or 0).
313 */
LL_PWR_IsEnabledBkUpAccess(void)314 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
315 {
316 return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
317 }
318
319 /**
320 * @brief Set voltage regulator mode during low power modes
321 * @rmtoll CR LPSDSR LL_PWR_SetRegulModeLP
322 * @param RegulMode This parameter can be one of the following values:
323 * @arg @ref LL_PWR_REGU_LPMODES_MAIN
324 * @arg @ref LL_PWR_REGU_LPMODES_LOW_POWER
325 * @retval None
326 */
LL_PWR_SetRegulModeLP(uint32_t RegulMode)327 __STATIC_INLINE void LL_PWR_SetRegulModeLP(uint32_t RegulMode)
328 {
329 MODIFY_REG(PWR->CR, PWR_CR_LPSDSR, RegulMode);
330 }
331
332 /**
333 * @brief Get voltage regulator mode during low power modes
334 * @rmtoll CR LPSDSR LL_PWR_GetRegulModeLP
335 * @retval Returned value can be one of the following values:
336 * @arg @ref LL_PWR_REGU_LPMODES_MAIN
337 * @arg @ref LL_PWR_REGU_LPMODES_LOW_POWER
338 */
LL_PWR_GetRegulModeLP(void)339 __STATIC_INLINE uint32_t LL_PWR_GetRegulModeLP(void)
340 {
341 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPSDSR));
342 }
343
344 #if defined(PWR_CR_LPDS)
345 /**
346 * @brief Set voltage regulator mode during deep sleep mode
347 * @rmtoll CR LPDS LL_PWR_SetRegulModeDS
348 * @param RegulMode This parameter can be one of the following values:
349 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
350 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
351 * @retval None
352 */
LL_PWR_SetRegulModeDS(uint32_t RegulMode)353 __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
354 {
355 MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
356 }
357
358 /**
359 * @brief Get voltage regulator mode during deep sleep mode
360 * @rmtoll CR LPDS LL_PWR_GetRegulModeDS
361 * @retval Returned value can be one of the following values:
362 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
363 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
364 */
LL_PWR_GetRegulModeDS(void)365 __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
366 {
367 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
368 }
369 #endif /* PWR_CR_LPDS */
370
371 /**
372 * @brief Set power down mode when CPU enters deepsleep
373 * @rmtoll CR PDDS LL_PWR_SetPowerMode
374 * @param PDMode This parameter can be one of the following values:
375 * @arg @ref LL_PWR_MODE_STOP
376 * @arg @ref LL_PWR_MODE_STANDBY
377 * @note Set the regulator to low power (bit @ref LL_PWR_REGU_LPMODES_LOW_POWER)
378 * before setting MODE_STOP. If the regulator remains in "main mode",
379 * it consumes more power without providing any additional feature.
380 * In MODE_STANDBY the regulator is automatically off.
381 * @note It is forbidden to configure both EN_VREFINT=1 and ULP=1 if the device is
382 * in Stop mode or in Sleep/Low-power sleep mode. If the device is not in
383 * low-power mode, VREFINT is always enabled whatever the state of EN_VREFINT and ULP
384 * @retval None
385 */
LL_PWR_SetPowerMode(uint32_t PDMode)386 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
387 {
388 MODIFY_REG(PWR->CR, PWR_CR_PDDS, PDMode);
389 }
390
391 /**
392 * @brief Get power down mode when CPU enters deepsleep
393 * @rmtoll CR PDDS LL_PWR_GetPowerMode
394 * @retval Returned value can be one of the following values:
395 * @arg @ref LL_PWR_MODE_STOP
396 * @arg @ref LL_PWR_MODE_STANDBY
397 */
LL_PWR_GetPowerMode(void)398 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
399 {
400 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PDDS));
401 }
402
403 #if defined(PWR_PVD_SUPPORT)
404 /**
405 * @brief Configure the voltage threshold detected by the Power Voltage Detector
406 * @rmtoll CR PLS LL_PWR_SetPVDLevel
407 * @param PVDLevel This parameter can be one of the following values:
408 * @arg @ref LL_PWR_PVDLEVEL_0
409 * @arg @ref LL_PWR_PVDLEVEL_1
410 * @arg @ref LL_PWR_PVDLEVEL_2
411 * @arg @ref LL_PWR_PVDLEVEL_3
412 * @arg @ref LL_PWR_PVDLEVEL_4
413 * @arg @ref LL_PWR_PVDLEVEL_5
414 * @arg @ref LL_PWR_PVDLEVEL_6
415 * @arg @ref LL_PWR_PVDLEVEL_7
416 * @retval None
417 */
LL_PWR_SetPVDLevel(uint32_t PVDLevel)418 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
419 {
420 MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
421 }
422
423 /**
424 * @brief Get the voltage threshold detection
425 * @rmtoll CR PLS LL_PWR_GetPVDLevel
426 * @retval Returned value can be one of the following values:
427 * @arg @ref LL_PWR_PVDLEVEL_0
428 * @arg @ref LL_PWR_PVDLEVEL_1
429 * @arg @ref LL_PWR_PVDLEVEL_2
430 * @arg @ref LL_PWR_PVDLEVEL_3
431 * @arg @ref LL_PWR_PVDLEVEL_4
432 * @arg @ref LL_PWR_PVDLEVEL_5
433 * @arg @ref LL_PWR_PVDLEVEL_6
434 * @arg @ref LL_PWR_PVDLEVEL_7
435 */
LL_PWR_GetPVDLevel(void)436 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
437 {
438 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
439 }
440
441 /**
442 * @brief Enable Power Voltage Detector
443 * @rmtoll CR PVDE LL_PWR_EnablePVD
444 * @retval None
445 */
LL_PWR_EnablePVD(void)446 __STATIC_INLINE void LL_PWR_EnablePVD(void)
447 {
448 SET_BIT(PWR->CR, PWR_CR_PVDE);
449 }
450
451 /**
452 * @brief Disable Power Voltage Detector
453 * @rmtoll CR PVDE LL_PWR_DisablePVD
454 * @retval None
455 */
LL_PWR_DisablePVD(void)456 __STATIC_INLINE void LL_PWR_DisablePVD(void)
457 {
458 CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
459 }
460
461 /**
462 * @brief Check if Power Voltage Detector is enabled
463 * @rmtoll CR PVDE LL_PWR_IsEnabledPVD
464 * @retval State of bit (1 or 0).
465 */
LL_PWR_IsEnabledPVD(void)466 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
467 {
468 return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
469 }
470 #endif /* PWR_PVD_SUPPORT */
471
472 /**
473 * @brief Enable the WakeUp PINx functionality
474 * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n
475 * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n
476 * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin
477 * @param WakeUpPin This parameter can be one of the following values:
478 * @arg @ref LL_PWR_WAKEUP_PIN1
479 * @arg @ref LL_PWR_WAKEUP_PIN2
480 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
481 *
482 * (*) not available on all devices
483 * @retval None
484 */
LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)485 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
486 {
487 SET_BIT(PWR->CSR, WakeUpPin);
488 }
489
490 /**
491 * @brief Disable the WakeUp PINx functionality
492 * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n
493 * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n
494 * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin
495 * @param WakeUpPin This parameter can be one of the following values:
496 * @arg @ref LL_PWR_WAKEUP_PIN1
497 * @arg @ref LL_PWR_WAKEUP_PIN2
498 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
499 *
500 * (*) not available on all devices
501 * @retval None
502 */
LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)503 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
504 {
505 CLEAR_BIT(PWR->CSR, WakeUpPin);
506 }
507
508 /**
509 * @brief Check if the WakeUp PINx functionality is enabled
510 * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n
511 * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n
512 * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin
513 * @param WakeUpPin This parameter can be one of the following values:
514 * @arg @ref LL_PWR_WAKEUP_PIN1
515 * @arg @ref LL_PWR_WAKEUP_PIN2
516 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
517 *
518 * (*) not available on all devices
519 * @retval State of bit (1 or 0).
520 */
LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)521 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
522 {
523 return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
524 }
525
526 /**
527 * @brief Enable ultra low-power mode by enabling VREFINT switch off in low-power modes
528 * @rmtoll CR ULP LL_PWR_EnableUltraLowPower
529 * @retval None
530 */
LL_PWR_EnableUltraLowPower(void)531 __STATIC_INLINE void LL_PWR_EnableUltraLowPower(void)
532 {
533 SET_BIT(PWR->CR, PWR_CR_ULP);
534 }
535
536 /**
537 * @brief Disable ultra low-power mode by disabling VREFINT switch off in low-power modes
538 * @rmtoll CR ULP LL_PWR_DisableUltraLowPower
539 * @retval None
540 */
LL_PWR_DisableUltraLowPower(void)541 __STATIC_INLINE void LL_PWR_DisableUltraLowPower(void)
542 {
543 CLEAR_BIT(PWR->CR, PWR_CR_ULP);
544 }
545
546 /**
547 * @brief Check if ultra low-power mode is enabled by checking if VREFINT switch off in low-power modes is enabled
548 * @rmtoll CR ULP LL_PWR_IsEnabledUltraLowPower
549 * @retval State of bit (1 or 0).
550 */
LL_PWR_IsEnabledUltraLowPower(void)551 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUltraLowPower(void)
552 {
553 return (READ_BIT(PWR->CR, PWR_CR_ULP) == (PWR_CR_ULP));
554 }
555
556 /**
557 * @brief Enable fast wakeup by ignoring VREFINT startup time when exiting from low-power mode
558 * @rmtoll CR FWU LL_PWR_EnableFastWakeUp
559 * @note Works in conjunction with ultra low power mode.
560 * @retval None
561 */
LL_PWR_EnableFastWakeUp(void)562 __STATIC_INLINE void LL_PWR_EnableFastWakeUp(void)
563 {
564 SET_BIT(PWR->CR, PWR_CR_FWU);
565 }
566
567 /**
568 * @brief Disable fast wakeup by waiting VREFINT startup time when exiting from low-power mode
569 * @rmtoll CR FWU LL_PWR_DisableFastWakeUp
570 * @note Works in conjunction with ultra low power mode.
571 * @retval None
572 */
LL_PWR_DisableFastWakeUp(void)573 __STATIC_INLINE void LL_PWR_DisableFastWakeUp(void)
574 {
575 CLEAR_BIT(PWR->CR, PWR_CR_FWU);
576 }
577
578 /**
579 * @brief Check if fast wakeup is enabled by checking if VREFINT startup time when exiting from low-power mode is ignored
580 * @rmtoll CR FWU LL_PWR_IsEnabledFastWakeUp
581 * @retval State of bit (1 or 0).
582 */
LL_PWR_IsEnabledFastWakeUp(void)583 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFastWakeUp(void)
584 {
585 return (READ_BIT(PWR->CR, PWR_CR_FWU) == (PWR_CR_FWU));
586 }
587
588 /**
589 * @brief Enable non-volatile memory (Flash and EEPROM) keeping off feature when exiting from low-power mode
590 * @rmtoll CR DS_EE_KOFF LL_PWR_EnableNVMKeptOff
591 * @note When enabled, after entering low-power mode (Stop or Standby only), if RUN_PD of FLASH_ACR register
592 * is also set, the Flash memory will not be woken up when exiting from deepsleep mode.
593 * When enabled, the EEPROM will not be woken up when exiting from low-power mode (if the bit RUN_PD is set)
594 * @retval None
595 */
LL_PWR_EnableNVMKeptOff(void)596 __STATIC_INLINE void LL_PWR_EnableNVMKeptOff(void)
597 {
598 SET_BIT(PWR->CR, PWR_CR_DSEEKOFF);
599 }
600
601 /**
602 * @brief Disable non-volatile memory (Flash and EEPROM) keeping off feature when exiting from low-power mode
603 * @rmtoll CR DS_EE_KOFF LL_PWR_DisableNVMKeptOff
604 * @note When disabled, Flash memory is woken up when exiting from deepsleep mode even if the bit RUN_PD is set
605 * @retval None
606 */
LL_PWR_DisableNVMKeptOff(void)607 __STATIC_INLINE void LL_PWR_DisableNVMKeptOff(void)
608 {
609 CLEAR_BIT(PWR->CR, PWR_CR_DSEEKOFF);
610 }
611
612 /**
613 * @brief Check if non-volatile memory (Flash and EEPROM) keeping off feature when exiting from low-power mode is enabled
614 * @rmtoll CR DS_EE_KOFF LL_PWR_IsEnabledNVMKeptOff
615 * @retval State of bit (1 or 0).
616 */
LL_PWR_IsEnabledNVMKeptOff(void)617 __STATIC_INLINE uint32_t LL_PWR_IsEnabledNVMKeptOff(void)
618 {
619 return (READ_BIT(PWR->CR, PWR_CR_DSEEKOFF) == (PWR_CR_DSEEKOFF));
620 }
621
622 /**
623 * @}
624 */
625
626 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
627 * @{
628 */
629
630 /**
631 * @brief Get Wake-up Flag
632 * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
633 * @retval State of bit (1 or 0).
634 */
LL_PWR_IsActiveFlag_WU(void)635 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
636 {
637 return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
638 }
639
640 /**
641 * @brief Get Standby Flag
642 * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
643 * @retval State of bit (1 or 0).
644 */
LL_PWR_IsActiveFlag_SB(void)645 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
646 {
647 return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
648 }
649
650 #if defined(PWR_PVD_SUPPORT)
651 /**
652 * @brief Indicate whether VDD voltage is below the selected PVD threshold
653 * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
654 * @retval State of bit (1 or 0).
655 */
LL_PWR_IsActiveFlag_PVDO(void)656 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
657 {
658 return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
659 }
660 #endif /* PWR_PVD_SUPPORT */
661
662 #if defined(PWR_CSR_VREFINTRDYF)
663 /**
664 * @brief Get Internal Reference VrefInt Flag
665 * @rmtoll CSR VREFINTRDYF LL_PWR_IsActiveFlag_VREFINTRDY
666 * @retval State of bit (1 or 0).
667 */
LL_PWR_IsActiveFlag_VREFINTRDY(void)668 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void)
669 {
670 return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF));
671 }
672 #endif /* PWR_CSR_VREFINTRDYF */
673 /**
674 * @brief Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
675 * @rmtoll CSR VOSF LL_PWR_IsActiveFlag_VOS
676 * @retval State of bit (1 or 0).
677 */
LL_PWR_IsActiveFlag_VOS(void)678 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
679 {
680 return (READ_BIT(PWR->CSR, LL_PWR_CSR_VOS) == (LL_PWR_CSR_VOS));
681 }
682 /**
683 * @brief Indicate whether the regulator is ready in main mode or is in low-power mode
684 * @rmtoll CSR REGLPF LL_PWR_IsActiveFlag_REGLPF
685 * @note Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing.
686 * @retval State of bit (1 or 0).
687 */
LL_PWR_IsActiveFlag_REGLPF(void)688 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void)
689 {
690 return (READ_BIT(PWR->CSR, PWR_CSR_REGLPF) == (PWR_CSR_REGLPF));
691 }
692 /**
693 * @brief Clear Standby Flag
694 * @rmtoll CR CSBF LL_PWR_ClearFlag_SB
695 * @retval None
696 */
LL_PWR_ClearFlag_SB(void)697 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
698 {
699 SET_BIT(PWR->CR, PWR_CR_CSBF);
700 }
701
702 /**
703 * @brief Clear Wake-up Flags
704 * @rmtoll CR CWUF LL_PWR_ClearFlag_WU
705 * @retval None
706 */
LL_PWR_ClearFlag_WU(void)707 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
708 {
709 SET_BIT(PWR->CR, PWR_CR_CWUF);
710 }
711 #if defined(USE_FULL_LL_DRIVER)
712 /** @defgroup PWR_LL_EF_Init De-initialization function
713 * @{
714 */
715 ErrorStatus LL_PWR_DeInit(void);
716 /**
717 * @}
718 */
719 #endif /* USE_FULL_LL_DRIVER */
720
721 /**
722 * @}
723 */
724
725 /**
726 * @}
727 */
728
729 /**
730 * @}
731 */
732
733 #endif /* defined(PWR) */
734
735 /**
736 * @}
737 */
738
739 #ifdef __cplusplus
740 }
741 #endif
742
743 #endif /* __STM32L0xx_LL_PWR_H */
744
