1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_spi.c
4 * @author MCD Application Team
5 * @brief SPI LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32h7xx_ll_spi.h"
22 #include "stm32h7xx_ll_bus.h"
23 #include "stm32h7xx_ll_rcc.h"
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32H7xx_LL_Driver
31 * @{
32 */
33
34 #if defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6)
35
36 /** @addtogroup SPI_LL
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /** @addtogroup SPI_LL_Private_Macros
45 * @{
46 */
47
48 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) || \
49 ((__VALUE__) == LL_SPI_MODE_SLAVE))
50
51 #define IS_LL_SPI_SS_IDLENESS(__VALUE__) (((__VALUE__) == LL_SPI_SS_IDLENESS_00CYCLE) || \
52 ((__VALUE__) == LL_SPI_SS_IDLENESS_01CYCLE) || \
53 ((__VALUE__) == LL_SPI_SS_IDLENESS_02CYCLE) || \
54 ((__VALUE__) == LL_SPI_SS_IDLENESS_03CYCLE) || \
55 ((__VALUE__) == LL_SPI_SS_IDLENESS_04CYCLE) || \
56 ((__VALUE__) == LL_SPI_SS_IDLENESS_05CYCLE) || \
57 ((__VALUE__) == LL_SPI_SS_IDLENESS_06CYCLE) || \
58 ((__VALUE__) == LL_SPI_SS_IDLENESS_07CYCLE) || \
59 ((__VALUE__) == LL_SPI_SS_IDLENESS_08CYCLE) || \
60 ((__VALUE__) == LL_SPI_SS_IDLENESS_09CYCLE) || \
61 ((__VALUE__) == LL_SPI_SS_IDLENESS_10CYCLE) || \
62 ((__VALUE__) == LL_SPI_SS_IDLENESS_11CYCLE) || \
63 ((__VALUE__) == LL_SPI_SS_IDLENESS_12CYCLE) || \
64 ((__VALUE__) == LL_SPI_SS_IDLENESS_13CYCLE) || \
65 ((__VALUE__) == LL_SPI_SS_IDLENESS_14CYCLE) || \
66 ((__VALUE__) == LL_SPI_SS_IDLENESS_15CYCLE))
67
68 #define IS_LL_SPI_ID_IDLENESS(__VALUE__) (((__VALUE__) == LL_SPI_ID_IDLENESS_00CYCLE) || \
69 ((__VALUE__) == LL_SPI_ID_IDLENESS_01CYCLE) || \
70 ((__VALUE__) == LL_SPI_ID_IDLENESS_02CYCLE) || \
71 ((__VALUE__) == LL_SPI_ID_IDLENESS_03CYCLE) || \
72 ((__VALUE__) == LL_SPI_ID_IDLENESS_04CYCLE) || \
73 ((__VALUE__) == LL_SPI_ID_IDLENESS_05CYCLE) || \
74 ((__VALUE__) == LL_SPI_ID_IDLENESS_06CYCLE) || \
75 ((__VALUE__) == LL_SPI_ID_IDLENESS_07CYCLE) || \
76 ((__VALUE__) == LL_SPI_ID_IDLENESS_08CYCLE) || \
77 ((__VALUE__) == LL_SPI_ID_IDLENESS_09CYCLE) || \
78 ((__VALUE__) == LL_SPI_ID_IDLENESS_10CYCLE) || \
79 ((__VALUE__) == LL_SPI_ID_IDLENESS_11CYCLE) || \
80 ((__VALUE__) == LL_SPI_ID_IDLENESS_12CYCLE) || \
81 ((__VALUE__) == LL_SPI_ID_IDLENESS_13CYCLE) || \
82 ((__VALUE__) == LL_SPI_ID_IDLENESS_14CYCLE) || \
83 ((__VALUE__) == LL_SPI_ID_IDLENESS_15CYCLE))
84
85 #define IS_LL_SPI_TXCRCINIT_PATTERN(__VALUE__) (((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN) || \
86 ((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ONES_PATTERN))
87
88 #define IS_LL_SPI_RXCRCINIT_PATTERN(__VALUE__) (((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN) || \
89 ((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ONES_PATTERN))
90
91 #define IS_LL_SPI_UDR_CONFIG_REGISTER(__VALUE__) (((__VALUE__) == LL_SPI_UDR_CONFIG_REGISTER_PATTERN) || \
92 ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_RECEIVED) || \
93 ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_TRANSMITTED))
94
95 #define IS_LL_SPI_UDR_DETECT_BEGIN_DATA(__VALUE__) (((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME) || \
96 ((__VALUE__) == LL_SPI_UDR_DETECT_END_DATA_FRAME) || \
97 ((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS))
98
99 #define IS_LL_SPI_PROTOCOL(__VALUE__) (((__VALUE__) == LL_SPI_PROTOCOL_MOTOROLA) || \
100 ((__VALUE__) == LL_SPI_PROTOCOL_TI))
101
102 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) || \
103 ((__VALUE__) == LL_SPI_PHASE_2EDGE))
104
105 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) || \
106 ((__VALUE__) == LL_SPI_POLARITY_HIGH))
107
108 #define IS_LL_SPI_BAUDRATEPRESCALER(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) || \
109 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) || \
110 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) || \
111 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) || \
112 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) || \
113 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) || \
114 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) || \
115 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
116
117 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) || \
118 ((__VALUE__) == LL_SPI_MSB_FIRST))
119
120 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) || \
121 ((__VALUE__) == LL_SPI_SIMPLEX_TX) || \
122 ((__VALUE__) == LL_SPI_SIMPLEX_RX) || \
123 ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) || \
124 ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
125
126 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) || \
127 ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) || \
128 ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) || \
129 ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) || \
130 ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) || \
131 ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) || \
132 ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) || \
133 ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) || \
134 ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) || \
135 ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) || \
136 ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) || \
137 ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) || \
138 ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT) || \
139 ((__VALUE__) == LL_SPI_DATAWIDTH_17BIT) || \
140 ((__VALUE__) == LL_SPI_DATAWIDTH_18BIT) || \
141 ((__VALUE__) == LL_SPI_DATAWIDTH_19BIT) || \
142 ((__VALUE__) == LL_SPI_DATAWIDTH_20BIT) || \
143 ((__VALUE__) == LL_SPI_DATAWIDTH_21BIT) || \
144 ((__VALUE__) == LL_SPI_DATAWIDTH_22BIT) || \
145 ((__VALUE__) == LL_SPI_DATAWIDTH_23BIT) || \
146 ((__VALUE__) == LL_SPI_DATAWIDTH_24BIT) || \
147 ((__VALUE__) == LL_SPI_DATAWIDTH_25BIT) || \
148 ((__VALUE__) == LL_SPI_DATAWIDTH_26BIT) || \
149 ((__VALUE__) == LL_SPI_DATAWIDTH_27BIT) || \
150 ((__VALUE__) == LL_SPI_DATAWIDTH_28BIT) || \
151 ((__VALUE__) == LL_SPI_DATAWIDTH_29BIT) || \
152 ((__VALUE__) == LL_SPI_DATAWIDTH_30BIT) || \
153 ((__VALUE__) == LL_SPI_DATAWIDTH_31BIT) || \
154 ((__VALUE__) == LL_SPI_DATAWIDTH_32BIT))
155
156 #define IS_LL_SPI_FIFO_TH(__VALUE__) (((__VALUE__) == LL_SPI_FIFO_TH_01DATA) || \
157 ((__VALUE__) == LL_SPI_FIFO_TH_02DATA) || \
158 ((__VALUE__) == LL_SPI_FIFO_TH_03DATA) || \
159 ((__VALUE__) == LL_SPI_FIFO_TH_04DATA) || \
160 ((__VALUE__) == LL_SPI_FIFO_TH_05DATA) || \
161 ((__VALUE__) == LL_SPI_FIFO_TH_06DATA) || \
162 ((__VALUE__) == LL_SPI_FIFO_TH_07DATA) || \
163 ((__VALUE__) == LL_SPI_FIFO_TH_08DATA) || \
164 ((__VALUE__) == LL_SPI_FIFO_TH_09DATA) || \
165 ((__VALUE__) == LL_SPI_FIFO_TH_10DATA) || \
166 ((__VALUE__) == LL_SPI_FIFO_TH_11DATA) || \
167 ((__VALUE__) == LL_SPI_FIFO_TH_12DATA) || \
168 ((__VALUE__) == LL_SPI_FIFO_TH_13DATA) || \
169 ((__VALUE__) == LL_SPI_FIFO_TH_14DATA) || \
170 ((__VALUE__) == LL_SPI_FIFO_TH_15DATA) || \
171 ((__VALUE__) == LL_SPI_FIFO_TH_16DATA))
172
173 #define IS_LL_SPI_CRC(__VALUE__) (((__VALUE__) == LL_SPI_CRC_4BIT) || \
174 ((__VALUE__) == LL_SPI_CRC_5BIT) || \
175 ((__VALUE__) == LL_SPI_CRC_6BIT) || \
176 ((__VALUE__) == LL_SPI_CRC_7BIT) || \
177 ((__VALUE__) == LL_SPI_CRC_8BIT) || \
178 ((__VALUE__) == LL_SPI_CRC_9BIT) || \
179 ((__VALUE__) == LL_SPI_CRC_10BIT) || \
180 ((__VALUE__) == LL_SPI_CRC_11BIT) || \
181 ((__VALUE__) == LL_SPI_CRC_12BIT) || \
182 ((__VALUE__) == LL_SPI_CRC_13BIT) || \
183 ((__VALUE__) == LL_SPI_CRC_14BIT) || \
184 ((__VALUE__) == LL_SPI_CRC_15BIT) || \
185 ((__VALUE__) == LL_SPI_CRC_16BIT) || \
186 ((__VALUE__) == LL_SPI_CRC_17BIT) || \
187 ((__VALUE__) == LL_SPI_CRC_18BIT) || \
188 ((__VALUE__) == LL_SPI_CRC_19BIT) || \
189 ((__VALUE__) == LL_SPI_CRC_20BIT) || \
190 ((__VALUE__) == LL_SPI_CRC_21BIT) || \
191 ((__VALUE__) == LL_SPI_CRC_22BIT) || \
192 ((__VALUE__) == LL_SPI_CRC_23BIT) || \
193 ((__VALUE__) == LL_SPI_CRC_24BIT) || \
194 ((__VALUE__) == LL_SPI_CRC_25BIT) || \
195 ((__VALUE__) == LL_SPI_CRC_26BIT) || \
196 ((__VALUE__) == LL_SPI_CRC_27BIT) || \
197 ((__VALUE__) == LL_SPI_CRC_28BIT) || \
198 ((__VALUE__) == LL_SPI_CRC_29BIT) || \
199 ((__VALUE__) == LL_SPI_CRC_30BIT) || \
200 ((__VALUE__) == LL_SPI_CRC_31BIT) || \
201 ((__VALUE__) == LL_SPI_CRC_32BIT))
202
203 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) || \
204 ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) || \
205 ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
206
207 #define IS_LL_SPI_RX_FIFO(__VALUE__) (((__VALUE__) == LL_SPI_RX_FIFO_0PACKET) || \
208 ((__VALUE__) == LL_SPI_RX_FIFO_1PACKET) || \
209 ((__VALUE__) == LL_SPI_RX_FIFO_2PACKET) || \
210 ((__VALUE__) == LL_SPI_RX_FIFO_3PACKET))
211
212 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) || \
213 ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
214
215 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1UL)
216
217 /**
218 * @}
219 */
220
221 /* Private function prototypes -----------------------------------------------*/
222
223 /* Exported functions --------------------------------------------------------*/
224 /** @addtogroup SPI_LL_Exported_Functions
225 * @{
226 */
227
228 /** @addtogroup SPI_LL_EF_Init
229 * @{
230 */
231
232 /**
233 * @brief De-initialize the SPI registers to their default reset values.
234 * @param SPIx SPI Instance
235 * @retval An ErrorStatus enumeration value:
236 * - SUCCESS: SPI registers are de-initialized
237 * - ERROR: SPI registers are not de-initialized
238 */
LL_SPI_DeInit(SPI_TypeDef * SPIx)239 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
240 {
241 ErrorStatus status = ERROR;
242
243 /* Check the parameters */
244 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
245
246 #if defined(SPI1)
247 if (SPIx == SPI1)
248 {
249 /* Force reset of SPI clock */
250 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
251
252 /* Release reset of SPI clock */
253 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
254
255 /* Update the return status */
256 status = SUCCESS;
257 }
258 #endif /* SPI1 */
259 #if defined(SPI2)
260 if (SPIx == SPI2)
261 {
262 /* Force reset of SPI clock */
263 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
264
265 /* Release reset of SPI clock */
266 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
267
268 /* Update the return status */
269 status = SUCCESS;
270 }
271 #endif /* SPI2 */
272 #if defined(SPI3)
273 if (SPIx == SPI3)
274 {
275 /* Force reset of SPI clock */
276 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
277
278 /* Release reset of SPI clock */
279 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
280
281 /* Update the return status */
282 status = SUCCESS;
283 }
284 #endif /* SPI3 */
285 #if defined(SPI4)
286 if (SPIx == SPI4)
287 {
288 /* Force reset of SPI clock */
289 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4);
290
291 /* Release reset of SPI clock */
292 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
293
294 /* Update the return status */
295 status = SUCCESS;
296 }
297 #endif /* SPI4 */
298 #if defined(SPI5)
299 if (SPIx == SPI5)
300 {
301 /* Force reset of SPI clock */
302 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5);
303
304 /* Release reset of SPI clock */
305 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5);
306
307 /* Update the return status */
308 status = SUCCESS;
309 }
310 #endif /* SPI5 */
311 #if defined(SPI6)
312 if (SPIx == SPI6)
313 {
314 /* Force reset of SPI clock */
315 LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_SPI6);
316
317 /* Release reset of SPI clock */
318 LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_SPI6);
319
320 /* Update the return status */
321 status = SUCCESS;
322 }
323 #endif /* SPI6 */
324
325 return status;
326 }
327
328 /**
329 * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
330 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled
331 * (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function.
332 * Otherwise, ERROR result will be returned.
333 * @param SPIx SPI Instance
334 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
335 * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
336 */
LL_SPI_Init(SPI_TypeDef * SPIx,LL_SPI_InitTypeDef * SPI_InitStruct)337 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
338 {
339 ErrorStatus status = ERROR;
340 uint32_t tmp_nss;
341 uint32_t tmp_mode;
342 uint32_t tmp_nss_polarity;
343
344 /* Check the SPI Instance SPIx*/
345 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
346
347 /* Check the SPI parameters from SPI_InitStruct*/
348 assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
349 assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
350 assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
351 assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
352 assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
353 assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
354 assert_param(IS_LL_SPI_BAUDRATEPRESCALER(SPI_InitStruct->BaudRate));
355 assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
356 assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
357
358 /* Check the SPI instance is not enabled */
359 if (LL_SPI_IsEnabled(SPIx) == 0x00000000UL)
360 {
361 /*---------------------------- SPIx CFG1 Configuration ------------------------
362 * Configure SPIx CFG1 with parameters:
363 * - Master Baud Rate : SPI_CFG1_MBR[2:0] bits
364 * - CRC Computation Enable : SPI_CFG1_CRCEN bit
365 * - Length of data frame : SPI_CFG1_DSIZE[4:0] bits
366 */
367 MODIFY_REG(SPIx->CFG1, SPI_CFG1_MBR | SPI_CFG1_CRCEN | SPI_CFG1_DSIZE,
368 SPI_InitStruct->BaudRate | SPI_InitStruct->CRCCalculation | SPI_InitStruct->DataWidth);
369
370 tmp_nss = SPI_InitStruct->NSS;
371 tmp_mode = SPI_InitStruct->Mode;
372 tmp_nss_polarity = LL_SPI_GetNSSPolarity(SPIx);
373
374 /* Checks to setup Internal SS signal level and avoid a MODF Error */
375 if ((tmp_nss == LL_SPI_NSS_SOFT) && (((tmp_nss_polarity == LL_SPI_NSS_POLARITY_LOW) && \
376 (tmp_mode == LL_SPI_MODE_MASTER)) || \
377 ((tmp_nss_polarity == LL_SPI_NSS_POLARITY_HIGH) && \
378 (tmp_mode == LL_SPI_MODE_SLAVE))))
379 {
380 LL_SPI_SetInternalSSLevel(SPIx, LL_SPI_SS_LEVEL_HIGH);
381 }
382
383 /*---------------------------- SPIx CFG2 Configuration ------------------------
384 * Configure SPIx CFG2 with parameters:
385 * - NSS management : SPI_CFG2_SSM, SPI_CFG2_SSOE bits
386 * - ClockPolarity : SPI_CFG2_CPOL bit
387 * - ClockPhase : SPI_CFG2_CPHA bit
388 * - BitOrder : SPI_CFG2_LSBFRST bit
389 * - Master/Slave Mode : SPI_CFG2_MASTER bit
390 * - SPI Mode : SPI_CFG2_COMM[1:0] bits
391 */
392 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE |
393 SPI_CFG2_CPOL | SPI_CFG2_CPHA |
394 SPI_CFG2_LSBFRST | SPI_CFG2_MASTER | SPI_CFG2_COMM,
395 SPI_InitStruct->NSS | SPI_InitStruct->ClockPolarity |
396 SPI_InitStruct->ClockPhase | SPI_InitStruct->BitOrder |
397 SPI_InitStruct->Mode | (SPI_InitStruct->TransferDirection & SPI_CFG2_COMM));
398
399 /*---------------------------- SPIx CR1 Configuration ------------------------
400 * Configure SPIx CR1 with parameter:
401 * - Half Duplex Direction : SPI_CR1_HDDIR bit
402 */
403 MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, SPI_InitStruct->TransferDirection & SPI_CR1_HDDIR);
404
405 /*---------------------------- SPIx CRCPOLY Configuration ----------------------
406 * Configure SPIx CRCPOLY with parameter:
407 * - CRCPoly : CRCPOLY[31:0] bits
408 */
409 if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
410 {
411 assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
412 LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
413 }
414
415 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
416 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
417
418 status = SUCCESS;
419 }
420
421 return status;
422 }
423
424 /**
425 * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
426 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
427 * whose fields will be set to default values.
428 * @retval None
429 */
LL_SPI_StructInit(LL_SPI_InitTypeDef * SPI_InitStruct)430 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
431 {
432 /* Set SPI_InitStruct fields to default values */
433 SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
434 SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
435 SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
436 SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
437 SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
438 SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
439 SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
440 SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
441 SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
442 SPI_InitStruct->CRCPoly = 7UL;
443 }
444
445 /**
446 * @}
447 */
448
449 /**
450 * @}
451 */
452
453 /**
454 * @}
455 */
456 /** @addtogroup I2S_LL
457 * @{
458 */
459
460 /* Private types -------------------------------------------------------------*/
461 /* Private variables ---------------------------------------------------------*/
462 /* Private constants ---------------------------------------------------------*/
463 /** @defgroup I2S_LL_Private_Constants I2S Private Constants
464 * @{
465 */
466 /* I2S registers Masks */
467 #define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
468 SPI_I2SCFGR_DATFMT | SPI_I2SCFGR_CKPOL | \
469 SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_MCKOE | \
470 SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
471
472 /**
473 * @}
474 */
475 /* Private macros ------------------------------------------------------------*/
476 /** @defgroup I2S_LL_Private_Macros I2S Private Macros
477 * @{
478 */
479
480 #define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) || \
481 ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) || \
482 ((__VALUE__) == LL_I2S_DATAFORMAT_24B) || \
483 ((__VALUE__) == LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED) || \
484 ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
485
486 #define IS_LL_I2S_CHANNEL_LENGTH_TYPE (__VALUE__) (((__VALUE__) == LL_I2S_SLAVE_VARIABLE_CH_LENGTH) || \
487 ((__VALUE__) == LL_I2S_SLAVE_FIXED_CH_LENGTH))
488
489 #define IS_LL_I2S_CKPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) || \
490 ((__VALUE__) == LL_I2S_POLARITY_HIGH))
491
492 #define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) || \
493 ((__VALUE__) == LL_I2S_STANDARD_MSB) || \
494 ((__VALUE__) == LL_I2S_STANDARD_LSB) || \
495 ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) || \
496 ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
497
498 #define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) || \
499 ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) || \
500 ((__VALUE__) == LL_I2S_MODE_SLAVE_FULL_DUPLEX) || \
501 ((__VALUE__) == LL_I2S_MODE_MASTER_TX) || \
502 ((__VALUE__) == LL_I2S_MODE_MASTER_RX) || \
503 ((__VALUE__) == LL_I2S_MODE_MASTER_FULL_DUPLEX))
504
505 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) || \
506 ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
507
508 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) && \
509 ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) || \
510 ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
511
512 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) <= 0xFFUL)
513
514 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) || \
515 ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
516
517 #define IS_LL_I2S_FIFO_TH (__VALUE__) (((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_01DATA) || \
518 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_02DATA) || \
519 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_03DATA) || \
520 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_04DATA) || \
521 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_05DATA) || \
522 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_06DATA) || \
523 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_07DATA) || \
524 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_08DATA))
525
526 #define IS_LL_I2S_BIT_ORDER(__VALUE__) (((__VALUE__) == LL_I2S_LSB_FIRST) || \
527 ((__VALUE__) == LL_I2S_MSB_FIRST))
528 /**
529 * @}
530 */
531
532 /* Private function prototypes -----------------------------------------------*/
533
534 /* Exported functions --------------------------------------------------------*/
535 /** @addtogroup I2S_LL_Exported_Functions
536 * @{
537 */
538
539 /** @addtogroup I2S_LL_EF_Init
540 * @{
541 */
542
543 /**
544 * @brief De-initialize the SPI/I2S registers to their default reset values.
545 * @param SPIx SPI Instance
546 * @retval An ErrorStatus enumeration value:
547 * - SUCCESS: SPI registers are de-initialized
548 * - ERROR: SPI registers are not de-initialized
549 */
LL_I2S_DeInit(SPI_TypeDef * SPIx)550 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
551 {
552 return LL_SPI_DeInit(SPIx);
553 }
554
555 /**
556 * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
557 * @note As some bits in I2S configuration registers can only be written when the SPI is disabled
558 * (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function.
559 * Otherwise, ERROR result will be returned.
560 * @note I2S (SPI) source clock must be ready before calling this function. Otherwise will results
561 * in wrong programming.
562 * @param SPIx SPI Instance
563 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
564 * @retval An ErrorStatus enumeration value:
565 * - SUCCESS: SPI registers are Initialized
566 * - ERROR: SPI registers are not Initialized
567 */
LL_I2S_Init(SPI_TypeDef * SPIx,LL_I2S_InitTypeDef * I2S_InitStruct)568 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
569 {
570 uint32_t i2sdiv = 0UL;
571 uint32_t i2sodd = 0UL;
572 uint32_t packetlength = 1UL;
573 uint32_t ispcm = 0UL;
574 uint32_t tmp;
575 uint32_t sourceclock;
576
577 ErrorStatus status = ERROR;
578
579 /* Check the I2S parameters */
580 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
581 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
582 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
583 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
584 assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
585 assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
586 assert_param(IS_LL_I2S_CKPOL(I2S_InitStruct->ClockPolarity));
587
588 /* Check that SPE bit is set to 0 in order to be sure that SPI/I2S block is disabled.
589 * In this case, it is useless to check if the I2SMOD bit is set to 0 because
590 * this bit I2SMOD only serves to select the desired mode.
591 */
592 if (LL_SPI_IsEnabled(SPIx) == 0x00000000UL)
593 {
594 /*---------------------------- SPIx I2SCFGR Configuration --------------------
595 * Configure SPIx I2SCFGR with parameters:
596 * - Mode : SPI_I2SCFGR_I2SCFG[2:0] bits
597 * - Standard : SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
598 * - DataFormat : SPI_I2SCFGR_CHLEN, SPI_I2SCFGR_DATFMT and SPI_I2SCFGR_DATLEN[1:0] bits
599 * - ClockPolarity : SPI_I2SCFGR_CKPOL bit
600 * - MCLKOutput : SPI_I2SPR_MCKOE bit
601 * - I2S mode : SPI_I2SCFGR_I2SMOD bit
602 */
603
604 /* Write to SPIx I2SCFGR */
605 MODIFY_REG(SPIx->I2SCFGR,
606 I2S_I2SCFGR_CLEAR_MASK,
607 I2S_InitStruct->Mode | I2S_InitStruct->Standard |
608 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
609 I2S_InitStruct->MCLKOutput | SPI_I2SCFGR_I2SMOD);
610
611 /*---------------------------- SPIx I2SCFGR Configuration ----------------------
612 * Configure SPIx I2SCFGR with parameters:
613 * - AudioFreq : SPI_I2SCFGR_I2SDIV[7:0] and SPI_I2SCFGR_ODD bits
614 */
615
616 /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
617 * else, default values are used: i2sodd = 0U, i2sdiv = 0U.
618 */
619 if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
620 {
621 /* Check the frame length (For the Prescaler computing)
622 * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
623 */
624 if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
625 {
626 /* Packet length is 32 bits */
627 packetlength = 2UL;
628 }
629
630 /* Check if PCM standard is used */
631 if ((I2S_InitStruct->Standard == LL_I2S_STANDARD_PCM_SHORT) ||
632 (I2S_InitStruct->Standard == LL_I2S_STANDARD_PCM_LONG))
633 {
634 ispcm = 1UL;
635 }
636
637 /* Get the I2S (SPI) source clock value */
638 #if defined (SPI_SPI6I2S_SUPPORT)
639 if (SPIx == SPI6)
640 {
641 sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI6_CLKSOURCE);
642 }
643 else
644 {
645 sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI123_CLKSOURCE);
646 }
647 #else
648 sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI123_CLKSOURCE);
649 #endif /* SPI_SPI6I2S_SUPPORT */
650
651 /* Compute the Real divider depending on the MCLK output state with a fixed point */
652 if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
653 {
654 /* MCLK output is enabled */
655 tmp = (((sourceclock / (256UL >> ispcm)) * 16UL) / I2S_InitStruct->AudioFreq) + 8UL;
656 }
657 else
658 {
659 /* MCLK output is disabled */
660 tmp = (((sourceclock / ((32UL >> ispcm) * packetlength)) * 16UL) / I2S_InitStruct->AudioFreq) + 8UL;
661 }
662
663 /* Remove the fixed point */
664 tmp = tmp / 16UL;
665
666 /* Check the parity of the divider */
667 i2sodd = tmp & 0x1UL;
668
669 /* Compute the i2sdiv prescaler */
670 i2sdiv = tmp / 2UL;
671 }
672
673 /* Test if the obtain values are forbidden or out of range */
674 if (((i2sodd == 1UL) && (i2sdiv == 1UL)) || (i2sdiv > 0xFFUL))
675 {
676 /* Set the default values */
677 i2sdiv = 0UL;
678 i2sodd = 0UL;
679 }
680
681 /* Write to SPIx I2SCFGR register the computed value */
682 MODIFY_REG(SPIx->I2SCFGR,
683 SPI_I2SCFGR_ODD | SPI_I2SCFGR_I2SDIV,
684 (i2sodd << SPI_I2SCFGR_ODD_Pos) | (i2sdiv << SPI_I2SCFGR_I2SDIV_Pos));
685
686 status = SUCCESS;
687 }
688
689 return status;
690 }
691
692 /**
693 * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
694 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
695 * whose fields will be set to default values.
696 * @retval None
697 */
LL_I2S_StructInit(LL_I2S_InitTypeDef * I2S_InitStruct)698 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
699 {
700 /*--------------- Reset I2S init structure parameters values -----------------*/
701 I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
702 I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
703 I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
704 I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
705 I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
706 I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
707 }
708
709 /**
710 * @brief Set linear and parity prescaler.
711 * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
712 * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
713 * @param SPIx SPI Instance
714 * @param PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF
715 * @note PrescalerLinear '1' is not authorized with parity LL_I2S_PRESCALER_PARITY_ODD
716 * @param PrescalerParity This parameter can be one of the following values:
717 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
718 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
719 * @retval None
720 */
LL_I2S_ConfigPrescaler(SPI_TypeDef * SPIx,uint32_t PrescalerLinear,uint32_t PrescalerParity)721 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
722 {
723 /* Check the I2S parameters */
724 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
725 assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
726 assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
727
728 /* Write to SPIx I2SPR */
729 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV | SPI_I2SCFGR_ODD, (PrescalerLinear << SPI_I2SCFGR_I2SDIV_Pos) |
730 (PrescalerParity << SPI_I2SCFGR_ODD_Pos));
731 }
732
733 /**
734 * @}
735 */
736
737 /**
738 * @}
739 */
740
741 /**
742 * @}
743 */
744
745 #endif /* defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) */
746
747 /**
748 * @}
749 */
750 #endif /* USE_FULL_LL_DRIVER */
751
