1 /** 2 ****************************************************************************** 3 * @file stm32h7xx_hal_pssi.h 4 * @author MCD Application Team 5 * @brief Header file of PSSI HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32H7xx_HAL_PSSI_H 21 #define STM32H7xx_HAL_PSSI_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h7xx_hal_def.h" 29 30 /** @addtogroup STM32H7xx_HAL_Driver 31 * @{ 32 */ 33 #if defined(PSSI) 34 /** @addtogroup PSSI PSSI 35 * @brief PSSI HAL module driver 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup PSSI_Exported_Types PSSI Exported Types 41 * @{ 42 */ 43 44 45 /** 46 * @brief PSSI Init structure definition 47 */ 48 typedef struct 49 { 50 uint32_t DataWidth; /* !< Configures the parallel bus width 8 lines or 16 lines */ 51 uint32_t BusWidth; /* !< Configures the parallel bus width 8 lines or 16 lines */ 52 uint32_t ControlSignal; /* !< Configures Data enable and Data ready */ 53 uint32_t ClockPolarity; /* !< Configures the PSSI Input Clock polarity */ 54 uint32_t DataEnablePolarity; /* !< Configures the PSSI Data Enable polarity */ 55 uint32_t ReadyPolarity; /* !< Configures the PSSI Ready polarity */ 56 57 } PSSI_InitTypeDef; 58 59 60 /** 61 * @brief HAL PSSI State structures definition 62 */ 63 typedef enum 64 { 65 HAL_PSSI_STATE_RESET = 0x00U, /* !< PSSI not yet initialized or disabled */ 66 HAL_PSSI_STATE_READY = 0x01U, /* !< Peripheral initialized and ready for use */ 67 HAL_PSSI_STATE_BUSY = 0x02U, /* !< An internal process is ongoing */ 68 HAL_PSSI_STATE_BUSY_TX = 0x03U, /* !< Transmit process is ongoing */ 69 HAL_PSSI_STATE_BUSY_RX = 0x04U, /* !< Receive process is ongoing */ 70 HAL_PSSI_STATE_TIMEOUT = 0x05U, /* !< Timeout state */ 71 HAL_PSSI_STATE_ERROR = 0x06U, /* !< PSSI state error */ 72 HAL_PSSI_STATE_ABORT = 0x07U, /* !< PSSI process is aborted */ 73 74 } HAL_PSSI_StateTypeDef; 75 76 /** 77 * @brief PSSI handle Structure definition 78 */ 79 typedef struct __PSSI_HandleTypeDef 80 { 81 PSSI_TypeDef *Instance; /*!< PSSI register base address. */ 82 PSSI_InitTypeDef Init; /*!< PSSI Initialization Structure. */ 83 uint32_t *pBuffPtr; /*!< PSSI Data buffer. */ 84 uint32_t XferCount; /*!< PSSI transfer count */ 85 uint32_t XferSize; /*!< PSSI transfer size */ 86 DMA_HandleTypeDef *hdmatx; /*!< PSSI Tx DMA Handle parameters */ 87 DMA_HandleTypeDef *hdmarx; /*!< PSSI Rx DMA Handle parameters */ 88 89 void (* TxCpltCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI transfer complete callback. */ 90 void (* RxCpltCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI transfer complete callback. */ 91 void (* ErrorCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI transfer complete callback. */ 92 void (* AbortCpltCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI transfer error callback. */ 93 94 void (* MspInitCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI Msp Init callback. */ 95 void (* MspDeInitCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI Msp DeInit callback. */ 96 97 HAL_LockTypeDef Lock; /*!< PSSI lock. */ 98 __IO HAL_PSSI_StateTypeDef State; /*!< PSSI transfer state. */ 99 __IO uint32_t ErrorCode; /*!< PSSI error code. */ 100 101 } PSSI_HandleTypeDef; 102 103 104 /** 105 * @brief HAL PSSI Callback pointer definition 106 */ 107 typedef void (*pPSSI_CallbackTypeDef)(PSSI_HandleTypeDef *hpssi); /*!< Pointer to a PSSI common callback function */ 108 109 /** 110 * @brief HAL PSSI Callback ID enumeration definition 111 */ 112 typedef enum 113 { 114 HAL_PSSI_TX_COMPLETE_CB_ID = 0x00U, /*!< PSSI Tx Transfer completed callback ID */ 115 HAL_PSSI_RX_COMPLETE_CB_ID = 0x01U, /*!< PSSI Rx Transfer completed callback ID */ 116 HAL_PSSI_ERROR_CB_ID = 0x03U, /*!< PSSI Error callback ID */ 117 HAL_PSSI_ABORT_CB_ID = 0x04U, /*!< PSSI Abort callback ID */ 118 119 HAL_PSSI_MSPINIT_CB_ID = 0x05U, /*!< PSSI Msp Init callback ID */ 120 HAL_PSSI_MSPDEINIT_CB_ID = 0x06U /*!< PSSI Msp DeInit callback ID */ 121 122 } HAL_PSSI_CallbackIDTypeDef; 123 124 125 /** 126 * @} 127 */ 128 129 /* Exported constants --------------------------------------------------------*/ 130 /** @defgroup PSSI_Exported_Constants PSSI Exported Constants 131 * @{ 132 */ 133 134 /** @defgroup PSSI_Error_Code PSSI Error Code 135 * @{ 136 */ 137 #define HAL_PSSI_ERROR_NONE 0x00000000U /*!< No error */ 138 #define HAL_PSSI_ERROR_NOT_SUPPORTED 0x00000001U /*!< Not supported operation */ 139 #define HAL_PSSI_ERROR_UNDER_RUN 0x00000002U /*!< FIFO Under-run error */ 140 #define HAL_PSSI_ERROR_OVER_RUN 0x00000004U /*!< FIFO Over-run error */ 141 #define HAL_PSSI_ERROR_DMA 0x00000008U /*!< Dma error */ 142 #define HAL_PSSI_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */ 143 #define HAL_PSSI_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid callback error */ 144 145 146 /** 147 * @} 148 */ 149 150 /** @defgroup PSSI_DATA_WIDTH PSSI Data Width 151 * @{ 152 */ 153 154 #define HAL_PSSI_8BITS 0x00000000U /*!< 8 Bits */ 155 #define HAL_PSSI_16BITS 0x00000001U /*!< 16 Bits */ 156 #define HAL_PSSI_32BITS 0x00000002U /*!< 32 Bits */ 157 /** 158 * @} 159 */ 160 161 /** @defgroup PSSI_BUS_WIDTH PSSI Bus Width 162 * @{ 163 */ 164 165 #define HAL_PSSI_8LINES 0x00000000U /*!< 8 data lines */ 166 #define HAL_PSSI_16LINES PSSI_CR_EDM /*!< 16 data lines */ 167 /** 168 * @} 169 */ 170 /** @defgroup PSSI_MODE PSSI mode 171 * @{ 172 */ 173 #define HAL_PSSI_UNIDIRECTIONAL 0x00000000U /*!< Uni-directional mode */ 174 #define HAL_PSSI_BIDIRECTIONAL 0x00000001U /*!< Bi-directional mode */ 175 /** 176 * @} 177 */ 178 179 /** @defgroup ControlSignal_Configuration ControlSignal Configuration 180 * @{ 181 */ 182 #define HAL_PSSI_DE_RDY_DISABLE (0x0U << PSSI_CR_DERDYCFG_Pos) /*!< Neither DE nor RDY are enabled */ 183 #define HAL_PSSI_RDY_ENABLE (0x1U << PSSI_CR_DERDYCFG_Pos) /*!< Only RDY enabled */ 184 #define HAL_PSSI_DE_ENABLE (0x2U << PSSI_CR_DERDYCFG_Pos) /*!< Only DE enabled */ 185 #define HAL_PSSI_DE_RDY_ALT_ENABLE (0x3U << PSSI_CR_DERDYCFG_Pos) /*!< Both RDY and DE alternate functions enabled */ 186 #define HAL_PSSI_MAP_RDY_BIDIR_ENABLE (0x4U << PSSI_CR_DERDYCFG_Pos) /*!< Bi-directional on RDY pin */ 187 #define HAL_PSSI_RDY_MAP_ENABLE (0x5U << PSSI_CR_DERDYCFG_Pos) /*!< Only RDY enabled, mapped to DE pin */ 188 #define HAL_PSSI_DE_MAP_ENABLE (0x6U << PSSI_CR_DERDYCFG_Pos) /*!< Only DE enabled, mapped to RDY pin */ 189 #define HAL_PSSI_MAP_DE_BIDIR_ENABLE (0x7U << PSSI_CR_DERDYCFG_Pos) /*!< Bi-directional on DE pin */ 190 191 /** 192 * @} 193 */ 194 195 196 /** @defgroup Data_Enable_Polarity Data Enable Polarity 197 * @{ 198 */ 199 #define HAL_PSSI_DEPOL_ACTIVE_LOW 0x0U /*!< Active Low */ 200 #define HAL_PSSI_DEPOL_ACTIVE_HIGH PSSI_CR_DEPOL /*!< Active High */ 201 /** 202 * @} 203 */ 204 /** @defgroup Reday_Polarity Reday Polarity 205 * @{ 206 */ 207 #define HAL_PSSI_RDYPOL_ACTIVE_LOW 0x0U /*!< Active Low */ 208 #define HAL_PSSI_RDYPOL_ACTIVE_HIGH PSSI_CR_RDYPOL /*!< Active High */ 209 /** 210 * @} 211 */ 212 213 /** @defgroup Clock_Polarity Clock Polarity 214 * @{ 215 */ 216 #define HAL_PSSI_FALLING_EDGE 0x0U /*!< Fallling Edge */ 217 #define HAL_PSSI_RISING_EDGE 0x1U /*!< Rising Edge */ 218 219 220 /** 221 * @} 222 */ 223 224 225 /** @defgroup PSSI_DEFINITION PSSI definitions 226 * @{ 227 */ 228 229 #define PSSI_MAX_NBYTE_SIZE 0x10000U /* 64 KB */ 230 #define PSSI_TIMEOUT_TRANSMIT 0x0000FFFFU /*!< Timeout Value */ 231 232 #define PSSI_CR_OUTEN_INPUT 0x00000000U /*!< Input Mode */ 233 #define PSSI_CR_OUTEN_OUTPUT PSSI_CR_OUTEN /*!< Output Mode */ 234 235 #define PSSI_CR_DMA_ENABLE PSSI_CR_DMAEN /*!< DMA Mode Enable */ 236 #define PSSI_CR_DMA_DISABLE (~PSSI_CR_DMAEN) /*!< DMA Mode Disable*/ 237 238 #define PSSI_CR_16BITS PSSI_CR_EDM /*!< 16 Lines Mode */ 239 #define PSSI_CR_8BITS (~PSSI_CR_EDM) /*!< 8 Lines Mode */ 240 241 #define PSSI_FLAG_RTT1B PSSI_SR_RTT1B /*!< 1 Byte Fifo Flag*/ 242 #define PSSI_FLAG_RTT4B PSSI_SR_RTT4B /*!< 4 Bytes Fifo Flag*/ 243 244 245 246 /** 247 * @} 248 */ 249 250 /** @defgroup PSSI_Interrupts PSSI Interrupts 251 * @{ 252 */ 253 254 #define PSSI_FLAG_OVR_RIS PSSI_RIS_OVR_RIS /*!< Overrun, Underrun errors flag */ 255 #define PSSI_FLAG_MASK PSSI_RIS_OVR_RIS_Msk /*!< Overrun, Underrun errors Mask */ 256 #define PSSI_FLAG_OVR_MIS PSSI_MIS_OVR_MIS /*!< Overrun, Underrun masked errors flag */ 257 /** 258 * @} 259 */ 260 261 262 263 /** 264 * @} 265 */ 266 /* Exported macros ------------------------------------------------------------*/ 267 /** @defgroup PSSI_Exported_Macros PSSI Exported Macros 268 * @{ 269 */ 270 271 /** @brief Reset PSSI handle state 272 * @param __HANDLE__ specifies the PSSI handle. 273 * @retval None 274 */ 275 276 #define HAL_PSSI_RESET_HANDLE_STATE(__HANDLE__) do{ \ 277 (__HANDLE__)->State = HAL_PSSI_STATE_RESET;\ 278 (__HANDLE__)->MspInitCallback = NULL; \ 279 (__HANDLE__)->MspDeInitCallback = NULL; \ 280 }while(0) 281 282 283 /** 284 * @brief Enable the PSSI. 285 * @param __HANDLE__ PSSI handle 286 * @retval None. 287 */ 288 #define HAL_PSSI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= PSSI_CR_ENABLE) 289 /** 290 * @brief Disable the PSSI. 291 * @param __HANDLE__ PSSI handle 292 * @retval None. 293 */ 294 #define HAL_PSSI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~PSSI_CR_ENABLE)) 295 296 /* PSSI pripheral STATUS */ 297 /** 298 * @brief Get the PSSI pending flags. 299 * @param __HANDLE__ PSSI handle 300 * @param __FLAG__ flag to check. 301 * This parameter can be any combination of the following values: 302 * @arg PSSI_FLAG_RTT1B: FIFO is ready to transfer one byte 303 * @arg PSSI_FLAG_RTT4B: FIFO is ready to transfer four bytes 304 * @retval The state of FLAG. 305 */ 306 307 #define HAL_PSSI_GET_STATUS(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR & (__FLAG__)) 308 309 310 311 /* Interrupt & Flag management */ 312 /** 313 * @brief Get the PSSI pending flags. 314 * @param __HANDLE__ PSSI handle 315 * @param __FLAG__ flag to check. 316 * This parameter can be any combination of the following values: 317 * @arg PSSI_FLAG_OVR_RIS: Data Buffer overrun/underrun error flag 318 * @retval The state of FLAG. 319 */ 320 #define HAL_PSSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->RIS & (__FLAG__)) 321 322 /** 323 * @brief Clear the PSSI pending flags. 324 * @param __HANDLE__ PSSI handle 325 * @param __FLAG__ specifies the flag to clear. 326 * This parameter can be any combination of the following values: 327 * @arg PSSI_FLAG_OVR_RIS: Data Buffer overrun/underrun error flag 328 * @retval None 329 */ 330 #define HAL_PSSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) 331 332 /** 333 * @brief Enable the specified PSSI interrupts. 334 * @param __HANDLE__ PSSI handle 335 * @param __INTERRUPT__ specifies the PSSI interrupt sources to be enabled. 336 * This parameter can be any combination of the following values: 337 * @arg PSSI_FLAG_OVR_RIS: Configuration error mask 338 * @retval None 339 */ 340 #define HAL_PSSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) 341 342 /** 343 * @brief Disable the specified PSSI interrupts. 344 * @param __HANDLE__ PSSI handle 345 * @param __INTERRUPT__ specifies the PSSI interrupt sources to be disabled. 346 * This parameter can be any combination of the following values: 347 * @arg PSSI_IT_OVR_IE: Configuration error mask 348 * @retval None 349 */ 350 #define HAL_PSSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__)) 351 352 /** 353 * @brief Check whether the specified PSSI interrupt source is enabled or not. 354 * @param __HANDLE__ PSSI handle 355 * @param __INTERRUPT__ specifies the PSSI interrupt source to check. 356 * This parameter can be one of the following values: 357 * @arg PSSI_IT_OVR_IE: Data Buffer overrun/underrun error interrupt mask 358 * @retval The state of INTERRUPT source. 359 */ 360 #define HAL_PSSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) 361 362 363 /** 364 * @brief Check whether the PSSI Control signal is valid. 365 * @param __CONTROL__ Control signals configuration 366 * @retval Valid or not. 367 */ 368 369 #define IS_PSSI_CONTROL_SIGNAL(__CONTROL__) (((__CONTROL__) == HAL_PSSI_DE_RDY_DISABLE ) || \ 370 ((__CONTROL__) == HAL_PSSI_RDY_ENABLE ) || \ 371 ((__CONTROL__) == HAL_PSSI_DE_ENABLE ) || \ 372 ((__CONTROL__) == HAL_PSSI_DE_RDY_ALT_ENABLE ) || \ 373 ((__CONTROL__) == HAL_PSSI_MAP_RDY_BIDIR_ENABLE ) || \ 374 ((__CONTROL__) == HAL_PSSI_RDY_MAP_ENABLE ) || \ 375 ((__CONTROL__) == HAL_PSSI_DE_MAP_ENABLE ) || \ 376 ((__CONTROL__) == HAL_PSSI_MAP_DE_BIDIR_ENABLE )) 377 378 379 380 /** 381 * @brief Check whether the PSSI Bus Width is valid. 382 * @param __BUSWIDTH__ PSSI Bush width 383 * @retval Valid or not. 384 */ 385 386 #define IS_PSSI_BUSWIDTH(__BUSWIDTH__) (((__BUSWIDTH__) == HAL_PSSI_8LINES ) || \ 387 ((__BUSWIDTH__) == HAL_PSSI_16LINES )) 388 389 /** 390 391 * @brief Check whether the PSSI Clock Polarity is valid. 392 * @param __CLOCKPOL__ PSSI Clock Polarity 393 * @retval Valid or not. 394 */ 395 396 #define IS_PSSI_CLOCK_POLARITY(__CLOCKPOL__) (((__CLOCKPOL__) == HAL_PSSI_FALLING_EDGE ) || \ 397 ((__CLOCKPOL__) == HAL_PSSI_RISING_EDGE )) 398 399 400 /** 401 * @brief Check whether the PSSI Data Enable Polarity is valid. 402 * @param __DEPOL__ PSSI DE Polarity 403 * @retval Valid or not. 404 */ 405 406 #define IS_PSSI_DE_POLARITY(__DEPOL__) (((__DEPOL__) == HAL_PSSI_DEPOL_ACTIVE_LOW ) || \ 407 ((__DEPOL__) == HAL_PSSI_DEPOL_ACTIVE_HIGH )) 408 409 /** 410 * @brief Check whether the PSSI Ready Polarity is valid. 411 * @param __RDYPOL__ PSSI RDY Polarity 412 * @retval Valid or not. 413 */ 414 415 #define IS_PSSI_RDY_POLARITY(__RDYPOL__) (((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_LOW ) || \ 416 ((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_HIGH )) 417 /** 418 * @} 419 */ 420 421 422 /* Exported functions --------------------------------------------------------*/ 423 /** @addtogroup PSSI_Exported_Functions PSSI Exported Functions 424 * @{ 425 */ 426 427 /** @addtogroup PSSI_Exported_Functions_Group1 Initialization and de-initialization functions 428 * @{ 429 */ 430 431 /* Initialization and de-initialization functions *******************************/ 432 HAL_StatusTypeDef HAL_PSSI_Init(PSSI_HandleTypeDef *hpssi); 433 HAL_StatusTypeDef HAL_PSSI_DeInit(PSSI_HandleTypeDef *hpssi); 434 void HAL_PSSI_MspInit(PSSI_HandleTypeDef *hpssi); 435 void HAL_PSSI_MspDeInit(PSSI_HandleTypeDef *hpssi); 436 /* Callbacks Register/UnRegister functions ***********************************/ 437 438 HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID, 439 pPSSI_CallbackTypeDef pCallback); 440 HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID); 441 442 443 /** 444 * @} 445 */ 446 447 448 /** @addtogroup PSSI_Exported_Functions_Group2 Input and Output operation functions 449 * @{ 450 */ 451 452 /* IO operation functions *******************************************************/ 453 HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout); 454 HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout); 455 HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size); 456 HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size); 457 HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi); 458 459 /** 460 * @} 461 */ 462 463 /** @addtogroup PSSI_Exported_Functions_Group3 Peripheral State and Error functions 464 * @{ 465 */ 466 467 /* Peripheral State functions ***************************************************/ 468 HAL_PSSI_StateTypeDef HAL_PSSI_GetState(PSSI_HandleTypeDef *hpssi); 469 uint32_t HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi); 470 471 /** 472 * @} 473 */ 474 475 /** @addtogroup PSSI_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks 476 * @{ 477 */ 478 479 void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi); 480 void HAL_PSSI_TxCpltCallback(PSSI_HandleTypeDef *hpssi); 481 void HAL_PSSI_RxCpltCallback(PSSI_HandleTypeDef *hpssi); 482 void HAL_PSSI_ErrorCallback(PSSI_HandleTypeDef *hpssi); 483 void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi); 484 485 486 /** 487 * @} 488 */ 489 490 491 492 /** 493 * @} 494 */ 495 496 /* Private constants ---------------------------------------------------------*/ 497 498 499 /* Private macros ------------------------------------------------------------*/ 500 501 502 /** 503 * @} 504 */ 505 #endif /* PSSI */ 506 507 /** 508 * @} 509 */ 510 511 512 #ifdef __cplusplus 513 } 514 #endif 515 516 #endif /* STM32H7xx_HAL_PSSI_H */ 517
