1 /** 2 ****************************************************************************** 3 * @file stm32h7xx_hal_dma2d.h 4 * @author MCD Application Team 5 * @brief Header file of DMA2D HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32H7xx_HAL_DMA2D_H 21 #define STM32H7xx_HAL_DMA2D_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h7xx_hal_def.h" 29 30 /** @addtogroup STM32H7xx_HAL_Driver 31 * @{ 32 */ 33 34 #if defined (DMA2D) 35 36 /** @addtogroup DMA2D DMA2D 37 * @brief DMA2D HAL module driver 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup DMA2D_Exported_Types DMA2D Exported Types 43 * @{ 44 */ 45 #define MAX_DMA2D_LAYER 2U /*!< DMA2D maximum number of layers */ 46 47 /** 48 * @brief DMA2D CLUT Structure definition 49 */ 50 typedef struct 51 { 52 uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/ 53 54 uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode. 55 This parameter can be one value of @ref DMA2D_CLUT_CM. */ 56 57 uint32_t Size; /*!< Configures the DMA2D CLUT size. 58 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/ 59 } DMA2D_CLUTCfgTypeDef; 60 61 /** 62 * @brief DMA2D Init structure definition 63 */ 64 typedef struct 65 { 66 uint32_t Mode; /*!< Configures the DMA2D transfer mode. 67 This parameter can be one value of @ref DMA2D_Mode. */ 68 69 uint32_t ColorMode; /*!< Configures the color format of the output image. 70 This parameter can be one value of @ref DMA2D_Output_Color_Mode. */ 71 72 uint32_t OutputOffset; /*!< Specifies the Offset value. 73 This parameter must be a number between 74 Min_Data = 0x0000 and Max_Data = 0x3FFF. */ 75 uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter. 76 This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ 77 78 uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR) 79 for the output pixel format converter. 80 This parameter can be one value of @ref DMA2D_RB_Swap. */ 81 82 83 uint32_t BytesSwap; /*!< Select byte regular mode or bytes swap mode (two by two). 84 This parameter can be one value of @ref DMA2D_Bytes_Swap. */ 85 86 uint32_t LineOffsetMode; /*!< Configures how is expressed the line offset for the foreground, background and output. 87 This parameter can be one value of @ref DMA2D_Line_Offset_Mode. */ 88 89 } DMA2D_InitTypeDef; 90 91 92 /** 93 * @brief DMA2D Layer structure definition 94 */ 95 typedef struct 96 { 97 uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset. 98 This parameter must be a number between 99 Min_Data = 0x0000 and Max_Data = 0x3FFF. */ 100 101 uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode. 102 This parameter can be one value of @ref DMA2D_Input_Color_Mode. */ 103 104 uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode. 105 This parameter can be one value of @ref DMA2D_Alpha_Mode. */ 106 107 uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value 108 in case of A8 or A4 color mode. 109 This parameter must be a number between Min_Data = 0x00 110 and Max_Data = 0xFF except for the color modes detailed below. 111 @note In case of A8 or A4 color mode (ARGB), 112 this parameter must be a number between 113 Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where 114 - InputAlpha[24:31] is the alpha value ALPHA[0:7] 115 - InputAlpha[16:23] is the red value RED[0:7] 116 - InputAlpha[8:15] is the green value GREEN[0:7] 117 - InputAlpha[0:7] is the blue value BLUE[0:7]. */ 118 uint32_t AlphaInverted; /*!< Select regular or inverted alpha value. 119 This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ 120 121 uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR). 122 This parameter can be one value of @ref DMA2D_RB_Swap. */ 123 124 uint32_t ChromaSubSampling; /*!< Configure the chroma sub-sampling mode for the YCbCr color mode 125 This parameter can be one value of @ref DMA2D_Chroma_Sub_Sampling */ 126 127 } DMA2D_LayerCfgTypeDef; 128 129 /** 130 * @brief HAL DMA2D State structures definition 131 */ 132 typedef enum 133 { 134 HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */ 135 HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 136 HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 137 HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 138 HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */ 139 HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */ 140 } HAL_DMA2D_StateTypeDef; 141 142 /** 143 * @brief DMA2D handle Structure definition 144 */ 145 typedef struct __DMA2D_HandleTypeDef 146 { 147 DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */ 148 149 DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */ 150 151 void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer complete callback. */ 152 153 void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer error callback. */ 154 155 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 156 void (* LineEventCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D line event callback. */ 157 158 void (* CLUTLoadingCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D CLUT loading completion callback */ 159 160 void (* MspInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp Init callback. */ 161 162 void (* MspDeInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp DeInit callback. */ 163 164 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ 165 166 DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ 167 168 HAL_LockTypeDef Lock; /*!< DMA2D lock. */ 169 170 __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */ 171 172 __IO uint32_t ErrorCode; /*!< DMA2D error code. */ 173 } DMA2D_HandleTypeDef; 174 175 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 176 /** 177 * @brief HAL DMA2D Callback pointer definition 178 */ 179 typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointer to a DMA2D common callback function */ 180 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 181 /** 182 * @} 183 */ 184 185 /* Exported constants --------------------------------------------------------*/ 186 /** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants 187 * @{ 188 */ 189 190 /** @defgroup DMA2D_Error_Code DMA2D Error Code 191 * @{ 192 */ 193 #define HAL_DMA2D_ERROR_NONE 0x00000000U /*!< No error */ 194 #define HAL_DMA2D_ERROR_TE 0x00000001U /*!< Transfer error */ 195 #define HAL_DMA2D_ERROR_CE 0x00000002U /*!< Configuration error */ 196 #define HAL_DMA2D_ERROR_CAE 0x00000004U /*!< CLUT access error */ 197 #define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 198 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 199 #define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid callback error */ 200 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ 201 202 /** 203 * @} 204 */ 205 206 /** @defgroup DMA2D_Mode DMA2D Mode 207 * @{ 208 */ 209 #define DMA2D_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */ 210 #define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ 211 #define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ 212 #define DMA2D_R2M (DMA2D_CR_MODE_1 | DMA2D_CR_MODE_0) /*!< DMA2D register to memory transfer mode */ 213 #define DMA2D_M2M_BLEND_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color FG */ 214 #define DMA2D_M2M_BLEND_BG (DMA2D_CR_MODE_2 | DMA2D_CR_MODE_0) /*!< DMA2D memory to memory with blending transfer mode and fixed color BG */ 215 /** 216 * @} 217 */ 218 219 /** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode 220 * @{ 221 */ 222 #define DMA2D_OUTPUT_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D color mode */ 223 #define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */ 224 #define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */ 225 #define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */ 226 #define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */ 227 /** 228 * @} 229 */ 230 231 /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode 232 * @{ 233 */ 234 #define DMA2D_INPUT_ARGB8888 0x00000000U /*!< ARGB8888 color mode */ 235 #define DMA2D_INPUT_RGB888 0x00000001U /*!< RGB888 color mode */ 236 #define DMA2D_INPUT_RGB565 0x00000002U /*!< RGB565 color mode */ 237 #define DMA2D_INPUT_ARGB1555 0x00000003U /*!< ARGB1555 color mode */ 238 #define DMA2D_INPUT_ARGB4444 0x00000004U /*!< ARGB4444 color mode */ 239 #define DMA2D_INPUT_L8 0x00000005U /*!< L8 color mode */ 240 #define DMA2D_INPUT_AL44 0x00000006U /*!< AL44 color mode */ 241 #define DMA2D_INPUT_AL88 0x00000007U /*!< AL88 color mode */ 242 #define DMA2D_INPUT_L4 0x00000008U /*!< L4 color mode */ 243 #define DMA2D_INPUT_A8 0x00000009U /*!< A8 color mode */ 244 #define DMA2D_INPUT_A4 0x0000000AU /*!< A4 color mode */ 245 #define DMA2D_INPUT_YCBCR 0x0000000BU /*!< YCbCr color mode */ 246 /** 247 * @} 248 */ 249 250 /** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode 251 * @{ 252 */ 253 #define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ 254 #define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */ 255 #define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value 256 with original alpha channel value */ 257 /** 258 * @} 259 */ 260 261 /** @defgroup DMA2D_Alpha_Inverted DMA2D Alpha Inversion 262 * @{ 263 */ 264 #define DMA2D_REGULAR_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ 265 #define DMA2D_INVERTED_ALPHA 0x00000001U /*!< Invert the alpha channel value */ 266 /** 267 * @} 268 */ 269 270 /** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap 271 * @{ 272 */ 273 #define DMA2D_RB_REGULAR 0x00000000U /*!< Select regular mode (RGB or ARGB) */ 274 #define DMA2D_RB_SWAP 0x00000001U /*!< Select swap mode (BGR or ABGR) */ 275 /** 276 * @} 277 */ 278 279 280 281 /** @defgroup DMA2D_Line_Offset_Mode DMA2D Line Offset Mode 282 * @{ 283 */ 284 #define DMA2D_LOM_PIXELS 0x00000000U /*!< Line offsets expressed in pixels */ 285 #define DMA2D_LOM_BYTES DMA2D_CR_LOM /*!< Line offsets expressed in bytes */ 286 /** 287 * @} 288 */ 289 290 /** @defgroup DMA2D_Bytes_Swap DMA2D Bytes Swap 291 * @{ 292 */ 293 #define DMA2D_BYTES_REGULAR 0x00000000U /*!< Bytes in regular order in output FIFO */ 294 #define DMA2D_BYTES_SWAP DMA2D_OPFCCR_SB /*!< Bytes are swapped two by two in output FIFO */ 295 /** 296 * @} 297 */ 298 299 /** @defgroup DMA2D_Chroma_Sub_Sampling DMA2D Chroma Sub Sampling 300 * @{ 301 */ 302 #define DMA2D_NO_CSS 0x00000000U /*!< No chroma sub-sampling 4:4:4 */ 303 #define DMA2D_CSS_422 0x00000001U /*!< chroma sub-sampling 4:2:2 */ 304 #define DMA2D_CSS_420 0x00000002U /*!< chroma sub-sampling 4:2:0 */ 305 /** 306 * @} 307 */ 308 309 /** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode 310 * @{ 311 */ 312 #define DMA2D_CCM_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D CLUT color mode */ 313 #define DMA2D_CCM_RGB888 0x00000001U /*!< RGB888 DMA2D CLUT color mode */ 314 /** 315 * @} 316 */ 317 318 /** @defgroup DMA2D_Interrupts DMA2D Interrupts 319 * @{ 320 */ 321 #define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ 322 #define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */ 323 #define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */ 324 #define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ 325 #define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ 326 #define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ 327 /** 328 * @} 329 */ 330 331 /** @defgroup DMA2D_Flags DMA2D Flags 332 * @{ 333 */ 334 #define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ 335 #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */ 336 #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */ 337 #define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */ 338 #define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */ 339 #define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */ 340 /** 341 * @} 342 */ 343 344 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 345 /** 346 * @brief HAL DMA2D common Callback ID enumeration definition 347 */ 348 typedef enum 349 { 350 HAL_DMA2D_MSPINIT_CB_ID = 0x00U, /*!< DMA2D MspInit callback ID */ 351 HAL_DMA2D_MSPDEINIT_CB_ID = 0x01U, /*!< DMA2D MspDeInit callback ID */ 352 HAL_DMA2D_TRANSFERCOMPLETE_CB_ID = 0x02U, /*!< DMA2D transfer complete callback ID */ 353 HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */ 354 HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */ 355 HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */ 356 } HAL_DMA2D_CallbackIDTypeDef; 357 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 358 359 360 /** 361 * @} 362 */ 363 /* Exported macros ------------------------------------------------------------*/ 364 /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros 365 * @{ 366 */ 367 368 /** @brief Reset DMA2D handle state 369 * @param __HANDLE__ specifies the DMA2D handle. 370 * @retval None 371 */ 372 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 373 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \ 374 (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\ 375 (__HANDLE__)->MspInitCallback = NULL; \ 376 (__HANDLE__)->MspDeInitCallback = NULL; \ 377 }while(0) 378 #else 379 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) 380 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 381 382 383 /** 384 * @brief Enable the DMA2D. 385 * @param __HANDLE__ DMA2D handle 386 * @retval None. 387 */ 388 #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) 389 390 391 /* Interrupt & Flag management */ 392 /** 393 * @brief Get the DMA2D pending flags. 394 * @param __HANDLE__ DMA2D handle 395 * @param __FLAG__ flag to check. 396 * This parameter can be any combination of the following values: 397 * @arg DMA2D_FLAG_CE: Configuration error flag 398 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag 399 * @arg DMA2D_FLAG_CAE: CLUT access error flag 400 * @arg DMA2D_FLAG_TW: Transfer Watermark flag 401 * @arg DMA2D_FLAG_TC: Transfer complete flag 402 * @arg DMA2D_FLAG_TE: Transfer error flag 403 * @retval The state of FLAG. 404 */ 405 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) 406 407 /** 408 * @brief Clear the DMA2D pending flags. 409 * @param __HANDLE__ DMA2D handle 410 * @param __FLAG__ specifies the flag to clear. 411 * This parameter can be any combination of the following values: 412 * @arg DMA2D_FLAG_CE: Configuration error flag 413 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag 414 * @arg DMA2D_FLAG_CAE: CLUT access error flag 415 * @arg DMA2D_FLAG_TW: Transfer Watermark flag 416 * @arg DMA2D_FLAG_TC: Transfer complete flag 417 * @arg DMA2D_FLAG_TE: Transfer error flag 418 * @retval None 419 */ 420 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__)) 421 422 /** 423 * @brief Enable the specified DMA2D interrupts. 424 * @param __HANDLE__ DMA2D handle 425 * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled. 426 * This parameter can be any combination of the following values: 427 * @arg DMA2D_IT_CE: Configuration error interrupt mask 428 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 429 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 430 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 431 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 432 * @arg DMA2D_IT_TE: Transfer error interrupt mask 433 * @retval None 434 */ 435 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) 436 437 /** 438 * @brief Disable the specified DMA2D interrupts. 439 * @param __HANDLE__ DMA2D handle 440 * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled. 441 * This parameter can be any combination of the following values: 442 * @arg DMA2D_IT_CE: Configuration error interrupt mask 443 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 444 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 445 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 446 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 447 * @arg DMA2D_IT_TE: Transfer error interrupt mask 448 * @retval None 449 */ 450 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) 451 452 /** 453 * @brief Check whether the specified DMA2D interrupt source is enabled or not. 454 * @param __HANDLE__ DMA2D handle 455 * @param __INTERRUPT__ specifies the DMA2D interrupt source to check. 456 * This parameter can be one of the following values: 457 * @arg DMA2D_IT_CE: Configuration error interrupt mask 458 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 459 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 460 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 461 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 462 * @arg DMA2D_IT_TE: Transfer error interrupt mask 463 * @retval The state of INTERRUPT source. 464 */ 465 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) 466 467 /** 468 * @} 469 */ 470 471 /* Exported functions --------------------------------------------------------*/ 472 /** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions 473 * @{ 474 */ 475 476 /** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions 477 * @{ 478 */ 479 480 /* Initialization and de-initialization functions *******************************/ 481 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); 482 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d); 483 void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d); 484 void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d); 485 /* Callbacks Register/UnRegister functions ***********************************/ 486 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 487 HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, 488 pDMA2D_CallbackTypeDef pCallback); 489 HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID); 490 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 491 492 /** 493 * @} 494 */ 495 496 497 /** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions 498 * @{ 499 */ 500 501 /* IO operation functions *******************************************************/ 502 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, 503 uint32_t Height); 504 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, 505 uint32_t DstAddress, uint32_t Width, uint32_t Height); 506 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, 507 uint32_t Height); 508 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, 509 uint32_t DstAddress, uint32_t Width, uint32_t Height); 510 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); 511 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); 512 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); 513 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 514 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, 515 uint32_t LayerIdx); 516 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, 517 uint32_t LayerIdx); 518 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 519 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 520 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 521 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 522 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 523 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout); 524 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d); 525 void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d); 526 void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d); 527 528 /** 529 * @} 530 */ 531 532 /** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions 533 * @{ 534 */ 535 536 /* Peripheral Control functions *************************************************/ 537 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 538 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 539 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line); 540 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d); 541 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d); 542 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime); 543 544 /** 545 * @} 546 */ 547 548 /** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions 549 * @{ 550 */ 551 552 /* Peripheral State functions ***************************************************/ 553 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d); 554 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); 555 556 /** 557 * @} 558 */ 559 560 /** 561 * @} 562 */ 563 564 /* Private constants ---------------------------------------------------------*/ 565 566 /** @addtogroup DMA2D_Private_Constants DMA2D Private Constants 567 * @{ 568 */ 569 570 /** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark 571 * @{ 572 */ 573 #define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */ 574 /** 575 * @} 576 */ 577 578 /** @defgroup DMA2D_Color_Value DMA2D Color Value 579 * @{ 580 */ 581 #define DMA2D_COLOR_VALUE 0x000000FFU /*!< Color value mask */ 582 /** 583 * @} 584 */ 585 586 /** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers 587 * @{ 588 */ 589 #define DMA2D_MAX_LAYER 2U /*!< DMA2D maximum number of layers */ 590 /** 591 * @} 592 */ 593 594 /** @defgroup DMA2D_Layers DMA2D Layers 595 * @{ 596 */ 597 #define DMA2D_BACKGROUND_LAYER 0x00000000U /*!< DMA2D Background Layer (layer 0) */ 598 #define DMA2D_FOREGROUND_LAYER 0x00000001U /*!< DMA2D Foreground Layer (layer 1) */ 599 /** 600 * @} 601 */ 602 603 /** @defgroup DMA2D_Offset DMA2D Offset 604 * @{ 605 */ 606 #define DMA2D_OFFSET DMA2D_FGOR_LO /*!< maximum Line Offset */ 607 /** 608 * @} 609 */ 610 611 /** @defgroup DMA2D_Size DMA2D Size 612 * @{ 613 */ 614 #define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D maximum number of pixels per line */ 615 #define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D maximum number of lines */ 616 /** 617 * @} 618 */ 619 620 /** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size 621 * @{ 622 */ 623 #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U) /*!< DMA2D maximum CLUT size */ 624 /** 625 * @} 626 */ 627 628 /** 629 * @} 630 */ 631 632 633 /* Private macros ------------------------------------------------------------*/ 634 /** @defgroup DMA2D_Private_Macros DMA2D Private Macros 635 * @{ 636 */ 637 #define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER)\ 638 || ((LAYER) == DMA2D_FOREGROUND_LAYER)) 639 640 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ 641 ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M) || \ 642 ((MODE) == DMA2D_M2M_BLEND_FG) || ((MODE) == DMA2D_M2M_BLEND_BG)) 643 644 #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || \ 645 ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ 646 ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || \ 647 ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ 648 ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444)) 649 650 #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE) 651 #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE) 652 #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) 653 #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) 654 655 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \ 656 ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ 657 ((INPUT_CM) == DMA2D_INPUT_RGB565) || \ 658 ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ 659 ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || \ 660 ((INPUT_CM) == DMA2D_INPUT_L8) || \ 661 ((INPUT_CM) == DMA2D_INPUT_AL44) || \ 662 ((INPUT_CM) == DMA2D_INPUT_AL88) || \ 663 ((INPUT_CM) == DMA2D_INPUT_L4) || \ 664 ((INPUT_CM) == DMA2D_INPUT_A8) || \ 665 ((INPUT_CM) == DMA2D_INPUT_A4) || \ 666 ((INPUT_CM) == DMA2D_INPUT_YCBCR)) 667 668 #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \ 669 ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \ 670 ((AlphaMode) == DMA2D_COMBINE_ALPHA)) 671 672 #define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \ 673 ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA)) 674 675 #define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \ 676 ((RB_Swap) == DMA2D_RB_SWAP)) 677 678 #define IS_DMA2D_LOM_MODE(LOM) (((LOM) == DMA2D_LOM_PIXELS) || \ 679 ((LOM) == DMA2D_LOM_BYTES)) 680 681 #define IS_DMA2D_BYTES_SWAP(BYTES_SWAP) (((BYTES_SWAP) == DMA2D_BYTES_REGULAR) || \ 682 ((BYTES_SWAP) == DMA2D_BYTES_SWAP)) 683 684 #define IS_DMA2D_CHROMA_SUB_SAMPLING(CSS) (((CSS) == DMA2D_NO_CSS) || \ 685 ((CSS) == DMA2D_CSS_422) || \ 686 ((CSS) == DMA2D_CSS_420)) 687 688 #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888)) 689 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) 690 #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX) 691 #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \ 692 ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ 693 ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) 694 #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \ 695 ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ 696 ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) 697 /** 698 * @} 699 */ 700 701 /** 702 * @} 703 */ 704 705 #endif /* defined (DMA2D) */ 706 707 /** 708 * @} 709 */ 710 711 #ifdef __cplusplus 712 } 713 #endif 714 715 #endif /* STM32H7xx_HAL_DMA2D_H */ 716
