1 /**
2   ******************************************************************************
3   * @file    stm32g473xx.h
4   * @author  MCD Application Team
5   * @brief   CMSIS STM32G473xx Device Peripheral Access Layer Header File.
6   *
7   *          This file contains:
8   *           - Data structures and the address mapping for all peripherals
9   *           - Peripheral's registers declarations and bits definition
10   *           - Macros to access peripheral's registers hardware
11   *
12   ******************************************************************************
13   * @attention
14   *
15   * Copyright (c) 2019 STMicroelectronics.
16   * All rights reserved.
17   *
18   * This software is licensed under terms that can be found in the LICENSE file
19   * in the root directory of this software component.
20   * If no LICENSE file comes with this software, it is provided AS-IS.
21   *
22   ******************************************************************************
23   */
24 
25 /** @addtogroup CMSIS_Device
26   * @{
27   */
28 
29 /** @addtogroup stm32g473xx
30   * @{
31   */
32 
33 #ifndef __STM32G473xx_H
34 #define __STM32G473xx_H
35 
36 #ifdef __cplusplus
37  extern "C" {
38 #endif /* __cplusplus */
39 
40 /** @addtogroup Configuration_section_for_CMSIS
41   * @{
42   */
43 
44 /**
45   * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
46    */
47 #define __CM4_REV                 0x0001U  /*!< Cortex-M4 revision r0p1                       */
48 #define __MPU_PRESENT             1U       /*!< STM32G4XX provides an MPU                     */
49 #define __NVIC_PRIO_BITS          4U       /*!< STM32G4XX uses 4 Bits for the Priority Levels */
50 #define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
51 #define __FPU_PRESENT             1U       /*!< FPU present                                   */
52 
53 /**
54   * @}
55   */
56 
57 /** @addtogroup Peripheral_interrupt_number_definition
58   * @{
59   */
60 
61 /**
62  * @brief STM32G4XX Interrupt Number Definition, according to the selected device
63  *        in @ref Library_configuration_section
64  */
65 typedef enum
66 {
67 /******  Cortex-M4 Processor Exceptions Numbers *********************************************************************************/
68   NonMaskableInt_IRQn         = -14,    /*!< 2 Cortex-M4 Non Maskable Interrupt                                                 */
69   HardFault_IRQn              = -13,    /*!< 3 Cortex-M4 Hard Fault Interrupt                                                   */
70   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                                            */
71   BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                                    */
72   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                                  */
73   SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                                     */
74   DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                                               */
75   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                                     */
76   SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                                 */
77 /******  STM32 specific Interrupt Numbers ***************************************************************************************/
78   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                                          */
79   PVD_PVM_IRQn                = 1,      /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts                     */
80   RTC_TAMP_LSECSS_IRQn        = 2,      /*!< RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI               */
81   RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                                         */
82   FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                                             */
83   RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                                               */
84   EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                                               */
85   EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                                               */
86   EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                                               */
87   EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                                               */
88   EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                                               */
89   DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                                                    */
90   DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                                                    */
91   DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                                                    */
92   DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                                                    */
93   DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                                                    */
94   DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                                                    */
95   DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                                                    */
96   ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                                                     */
97   USB_HP_IRQn                 = 19,     /*!< USB HP Interrupt                                                                   */
98   USB_LP_IRQn                 = 20,     /*!< USB LP  Interrupt                                                                  */
99   FDCAN1_IT0_IRQn             = 21,     /*!< FDCAN1 IT0 Interrupt                                                               */
100   FDCAN1_IT1_IRQn             = 22,     /*!< FDCAN1 IT1 Interrupt                                                               */
101   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                                      */
102   TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break, Transition error, Index error and TIM15 global interrupt               */
103   TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM16 global interrupt                                   */
104   TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */
105   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                                     */
106   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                                              */
107   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                                              */
108   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                                              */
109   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                                               */
110   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                                               */
111   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                                               */
112   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                                               */
113   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                                              */
114   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                                              */
115   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                                            */
116   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                                            */
117   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                                            */
118   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                                    */
119   RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                                    */
120   USBWakeUp_IRQn              = 42,     /*!< USB Wakeup through EXTI line Interrupt                                             */
121   TIM8_BRK_IRQn               = 43,     /*!< TIM8 Break, Transition error and Index error Interrupt                             */
122   TIM8_UP_IRQn                = 44,     /*!< TIM8 Update Interrupt                                                              */
123   TIM8_TRG_COM_IRQn           = 45,     /*!< TIM8 Trigger, Commutation, Direction change and Index Interrupt                    */
124   TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                                     */
125   ADC3_IRQn                   = 47,     /*!< ADC3 global  Interrupt                                                             */
126   FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                                               */
127   LPTIM1_IRQn                 = 49,     /*!< LP TIM1 Interrupt                                                                  */
128   TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                                              */
129   SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                                              */
130   UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                                             */
131   UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                                             */
132   TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&3 underrun error  interrupts                                  */
133   TIM7_DAC_IRQn               = 55,     /*!< TIM7 global and DAC2&4 underrun error  interrupts                                  */
134   DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                                                    */
135   DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                                                    */
136   DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                                                    */
137   DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                                                    */
138   DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                                                    */
139   ADC4_IRQn                   = 61,     /*!< ADC4 global Interrupt                                                              */
140   ADC5_IRQn                   = 62,     /*!< ADC5 global Interrupt                                                              */
141   UCPD1_IRQn                  = 63,     /*!< UCPD global Interrupt                                                              */
142   COMP1_2_3_IRQn              = 64,     /*!< COMP1, COMP2 and COMP3 Interrupts                                                  */
143   COMP4_5_6_IRQn              = 65,     /*!< COMP4, COMP5 and COMP6                                                             */
144   COMP7_IRQn                  = 66,     /*!< COMP7 Interrupt                                                                    */
145   CRS_IRQn                    = 75,     /*!< CRS global interrupt                                                               */
146   SAI1_IRQn                   = 76,     /*!< Serial Audio Interface global interrupt                                            */
147   TIM20_BRK_IRQn              = 77,     /*!< TIM20 Break, Transition error and Index error Interrupt                            */
148   TIM20_UP_IRQn               = 78,     /*!< TIM20 Update interrupt                                                             */
149   TIM20_TRG_COM_IRQn          = 79,     /*!< TIM20 Trigger, Commutation, Direction change and Index Interrupt                   */
150   TIM20_CC_IRQn               = 80,     /*!< TIM20 Capture Compare interrupt                                                    */
151   FPU_IRQn                    = 81,     /*!< FPU global interrupt                                                               */
152   I2C4_EV_IRQn                = 82,     /*!< I2C4 Event interrupt                                                               */
153   I2C4_ER_IRQn                = 83,     /*!< I2C4 Error interrupt                                                               */
154   SPI4_IRQn                   = 84,     /*!< SPI4 Event interrupt                                                               */
155   FDCAN2_IT0_IRQn             = 86,     /*!< FDCAN2 interrupt line 0 interrupt                                                  */
156   FDCAN2_IT1_IRQn             = 87,     /*!< FDCAN2 interrupt line 1 interrupt                                                  */
157   FDCAN3_IT0_IRQn             = 88,     /*!< FDCAN3 interrupt line 0 interrupt                                                  */
158   FDCAN3_IT1_IRQn             = 89,     /*!< FDCAN3 interrupt line 1 interrupt                                                  */
159   RNG_IRQn                    = 90,     /*!< RNG global interrupt                                                               */
160   LPUART1_IRQn                = 91,     /*!< LP UART 1 Interrupt                                                                */
161   I2C3_EV_IRQn                = 92,     /*!< I2C3 Event Interrupt                                                               */
162   I2C3_ER_IRQn                = 93,     /*!< I2C3 Error interrupt                                                               */
163   DMAMUX_OVR_IRQn             = 94,     /*!< DMAMUX overrun global interrupt                                                    */
164   QUADSPI_IRQn                = 95,     /*!< QUADSPI interrupt                                                                  */
165   DMA1_Channel8_IRQn          = 96,     /*!< DMA1 Channel 8 interrupt                                                           */
166   DMA2_Channel6_IRQn          = 97,     /*!< DMA2 Channel 6 interrupt                                                           */
167   DMA2_Channel7_IRQn          = 98,     /*!< DMA2 Channel 7 interrupt                                                           */
168   DMA2_Channel8_IRQn          = 99,     /*!< DMA2 Channel 8 interrupt                                                           */
169   CORDIC_IRQn                 = 100,    /*!< CORDIC global Interrupt                                                            */
170   FMAC_IRQn                   = 101     /*!< FMAC global Interrupt                                                              */
171 } IRQn_Type;
172 
173 /**
174   * @}
175   */
176 
177 #include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
178 #include "system_stm32g4xx.h"
179 #include <stdint.h>
180 
181 /** @addtogroup Peripheral_registers_structures
182   * @{
183   */
184 
185 /**
186   * @brief Analog to Digital Converter
187   */
188 
189 typedef struct
190 {
191   __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
192   __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
193   __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
194   __IO uint32_t CFGR;         /*!< ADC configuration register 1,                  Address offset: 0x0C */
195   __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
196   __IO uint32_t SMPR1;        /*!< ADC sampling time register 1,                  Address offset: 0x14 */
197   __IO uint32_t SMPR2;        /*!< ADC sampling time register 2,                  Address offset: 0x18 */
198        uint32_t RESERVED1;    /*!< Reserved,                                                      0x1C */
199   __IO uint32_t TR1;          /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
200   __IO uint32_t TR2;          /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */
201   __IO uint32_t TR3;          /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x28 */
202        uint32_t RESERVED2;    /*!< Reserved,                                                      0x2C */
203   __IO uint32_t SQR1;         /*!< ADC group regular sequencer register 1,        Address offset: 0x30 */
204   __IO uint32_t SQR2;         /*!< ADC group regular sequencer register 2,        Address offset: 0x34 */
205   __IO uint32_t SQR3;         /*!< ADC group regular sequencer register 3,        Address offset: 0x38 */
206   __IO uint32_t SQR4;         /*!< ADC group regular sequencer register 4,        Address offset: 0x3C */
207   __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
208        uint32_t RESERVED3;    /*!< Reserved,                                                      0x44 */
209        uint32_t RESERVED4;    /*!< Reserved,                                                      0x48 */
210   __IO uint32_t JSQR;         /*!< ADC group injected sequencer register,         Address offset: 0x4C */
211        uint32_t RESERVED5[4]; /*!< Reserved,                                               0x50 - 0x5C */
212   __IO uint32_t OFR1;         /*!< ADC offset register 1,                         Address offset: 0x60 */
213   __IO uint32_t OFR2;         /*!< ADC offset register 2,                         Address offset: 0x64 */
214   __IO uint32_t OFR3;         /*!< ADC offset register 3,                         Address offset: 0x68 */
215   __IO uint32_t OFR4;         /*!< ADC offset register 4,                         Address offset: 0x6C */
216        uint32_t RESERVED6[4]; /*!< Reserved,                                               0x70 - 0x7C */
217   __IO uint32_t JDR1;         /*!< ADC group injected rank 1 data register,       Address offset: 0x80 */
218   __IO uint32_t JDR2;         /*!< ADC group injected rank 2 data register,       Address offset: 0x84 */
219   __IO uint32_t JDR3;         /*!< ADC group injected rank 3 data register,       Address offset: 0x88 */
220   __IO uint32_t JDR4;         /*!< ADC group injected rank 4 data register,       Address offset: 0x8C */
221        uint32_t RESERVED7[4]; /*!< Reserved,                                             0x090 - 0x09C */
222   __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 2 configuration register,  Address offset: 0xA0 */
223   __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 Configuration Register,  Address offset: 0xA4 */
224        uint32_t RESERVED8;    /*!< Reserved,                                                     0x0A8 */
225        uint32_t RESERVED9;    /*!< Reserved,                                                     0x0AC */
226   __IO uint32_t DIFSEL;       /*!< ADC differential mode selection register,      Address offset: 0xB0 */
227   __IO uint32_t CALFACT;      /*!< ADC calibration factors,                       Address offset: 0xB4 */
228        uint32_t RESERVED10[2];/*!< Reserved,                                             0x0B8 - 0x0BC */
229   __IO uint32_t GCOMP;        /*!< ADC calibration factors,                       Address offset: 0xC0 */
230 } ADC_TypeDef;
231 
232 typedef struct
233 {
234   __IO uint32_t CSR;          /*!< ADC common status register,            Address offset: 0x300 + 0x00 */
235   uint32_t      RESERVED1;    /*!< Reserved,                              Address offset: 0x300 + 0x04 */
236   __IO uint32_t CCR;          /*!< ADC common configuration register,     Address offset: 0x300 + 0x08 */
237   __IO uint32_t CDR;          /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */
238 } ADC_Common_TypeDef;
239 
240 /**
241   * @brief FD Controller Area Network
242   */
243 
244 typedef struct
245 {
246   __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */
247   __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */
248        uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */
249   __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */
250   __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */
251   __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */
252   __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */
253   __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */
254   __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */
255   __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */
256   __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */
257   __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */
258        uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */
259   __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */
260   __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */
261   __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */
262        uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */
263   __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */
264   __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */
265   __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */
266   __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */
267        uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */
268   __IO uint32_t RXGFC;        /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */
269   __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x084 */
270   __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x088 */
271        uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */
272   __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x090 */
273   __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x094 */
274   __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x098 */
275   __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x09C */
276        uint32_t RESERVED6[8]; /*!< Reserved,                                                                0x0A0 - 0x0BC */
277   __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */
278   __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */
279   __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0C8 */
280   __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0CC */
281   __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D0 */
282   __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D4 */
283   __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0D8 */
284   __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0DC */
285   __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */
286   __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0E4 */
287   __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0E8 */
288 } FDCAN_GlobalTypeDef;
289 
290 /**
291   * @brief FD Controller Area Network Configuration
292   */
293 
294 typedef struct
295 {
296   __IO uint32_t CKDIV;        /*!< FDCAN clock divider register,                            Address offset: 0x100 + 0x000 */
297 } FDCAN_Config_TypeDef;
298 
299 /**
300   * @brief Comparator
301   */
302 
303 typedef struct
304 {
305   __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
306 } COMP_TypeDef;
307 
308 /**
309   * @brief CRC calculation unit
310   */
311 
312 typedef struct
313 {
314   __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
315   __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
316   __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
317   uint32_t      RESERVED0;   /*!< Reserved,                                                    0x0C */
318   __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
319   __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
320 } CRC_TypeDef;
321 
322 /**
323   * @brief Clock Recovery System
324   */
325 typedef struct
326 {
327   __IO uint32_t CR;          /*!< CRS ccontrol register,              Address offset: 0x00 */
328   __IO uint32_t CFGR;        /*!< CRS configuration register,         Address offset: 0x04 */
329   __IO uint32_t ISR;         /*!< CRS interrupt and status register,  Address offset: 0x08 */
330   __IO uint32_t ICR;         /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
331 } CRS_TypeDef;
332 
333 /**
334   * @brief Digital to Analog Converter
335   */
336 
337 typedef struct
338 {
339   __IO uint32_t CR;          /*!< DAC control register,                                    Address offset: 0x00 */
340   __IO uint32_t SWTRIGR;     /*!< DAC software trigger register,                           Address offset: 0x04 */
341   __IO uint32_t DHR12R1;     /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
342   __IO uint32_t DHR12L1;     /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
343   __IO uint32_t DHR8R1;      /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
344   __IO uint32_t DHR12R2;     /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
345   __IO uint32_t DHR12L2;     /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
346   __IO uint32_t DHR8R2;      /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
347   __IO uint32_t DHR12RD;     /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
348   __IO uint32_t DHR12LD;     /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
349   __IO uint32_t DHR8RD;      /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
350   __IO uint32_t DOR1;        /*!< DAC channel1 data output register,                       Address offset: 0x2C */
351   __IO uint32_t DOR2;        /*!< DAC channel2 data output register,                       Address offset: 0x30 */
352   __IO uint32_t SR;          /*!< DAC status register,                                     Address offset: 0x34 */
353   __IO uint32_t CCR;         /*!< DAC calibration control register,                        Address offset: 0x38 */
354   __IO uint32_t MCR;         /*!< DAC mode control register,                               Address offset: 0x3C */
355   __IO uint32_t SHSR1;       /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
356   __IO uint32_t SHSR2;       /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */
357   __IO uint32_t SHHR;        /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
358   __IO uint32_t SHRR;        /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
359   __IO uint32_t RESERVED[2];
360   __IO uint32_t STR1;        /*!< DAC Sawtooth register,                                   Address offset: 0x58 */
361   __IO uint32_t STR2;        /*!< DAC Sawtooth register,                                   Address offset: 0x5C */
362   __IO uint32_t STMODR;      /*!< DAC Sawtooth Mode register,                              Address offset: 0x60 */
363 } DAC_TypeDef;
364 
365 /**
366   * @brief Debug MCU
367   */
368 
369 typedef struct
370 {
371   __IO uint32_t IDCODE;      /*!< MCU device ID code,                 Address offset: 0x00 */
372   __IO uint32_t CR;          /*!< Debug MCU configuration register,   Address offset: 0x04 */
373   __IO uint32_t APB1FZR1;    /*!< Debug MCU APB1 freeze register 1,   Address offset: 0x08 */
374   __IO uint32_t APB1FZR2;    /*!< Debug MCU APB1 freeze register 2,   Address offset: 0x0C */
375   __IO uint32_t APB2FZ;      /*!< Debug MCU APB2 freeze register,     Address offset: 0x10 */
376 } DBGMCU_TypeDef;
377 
378 /**
379   * @brief DMA Controller
380   */
381 
382 typedef struct
383 {
384   __IO uint32_t CCR;         /*!< DMA channel x configuration register        */
385   __IO uint32_t CNDTR;       /*!< DMA channel x number of data register       */
386   __IO uint32_t CPAR;        /*!< DMA channel x peripheral address register   */
387   __IO uint32_t CMAR;        /*!< DMA channel x memory address register       */
388 } DMA_Channel_TypeDef;
389 
390 typedef struct
391 {
392   __IO uint32_t ISR;         /*!< DMA interrupt status register,                 Address offset: 0x00 */
393   __IO uint32_t IFCR;        /*!< DMA interrupt flag clear register,             Address offset: 0x04 */
394 } DMA_TypeDef;
395 
396 /**
397   * @brief DMA Multiplexer
398   */
399 
400 typedef struct
401 {
402   __IO uint32_t   CCR;       /*!< DMA Multiplexer Channel x Control Register    Address offset: 0x0004 * (channel x) */
403 }DMAMUX_Channel_TypeDef;
404 
405 typedef struct
406 {
407   __IO uint32_t   CSR;      /*!< DMA Channel Status Register                    Address offset: 0x0080   */
408   __IO uint32_t   CFR;      /*!< DMA Channel Clear Flag Register                Address offset: 0x0084   */
409 }DMAMUX_ChannelStatus_TypeDef;
410 
411 typedef struct
412 {
413   __IO uint32_t   RGCR;        /*!< DMA Request Generator x Control Register     Address offset: 0x0100 + 0x0004 * (Req Gen x) */
414 }DMAMUX_RequestGen_TypeDef;
415 
416 typedef struct
417 {
418   __IO uint32_t   RGSR;        /*!< DMA Request Generator Status Register        Address offset: 0x0140   */
419   __IO uint32_t   RGCFR;        /*!< DMA Request Generator Clear Flag Register    Address offset: 0x0144   */
420 }DMAMUX_RequestGenStatus_TypeDef;
421 
422 /**
423   * @brief External Interrupt/Event Controller
424   */
425 
426 typedef struct
427 {
428   __IO uint32_t IMR1;        /*!< EXTI Interrupt mask register 1,             Address offset: 0x00 */
429   __IO uint32_t EMR1;        /*!< EXTI Event mask register 1,                 Address offset: 0x04 */
430   __IO uint32_t RTSR1;       /*!< EXTI Rising trigger selection register 1,   Address offset: 0x08 */
431   __IO uint32_t FTSR1;       /*!< EXTI Falling trigger selection register 1,  Address offset: 0x0C */
432   __IO uint32_t SWIER1;      /*!< EXTI Software interrupt event register 1,   Address offset: 0x10 */
433   __IO uint32_t PR1;         /*!< EXTI Pending register 1,                    Address offset: 0x14 */
434   uint32_t      RESERVED1;   /*!< Reserved, 0x18                                                   */
435   uint32_t      RESERVED2;   /*!< Reserved, 0x1C                                                   */
436   __IO uint32_t IMR2;        /*!< EXTI Interrupt mask register 2,             Address offset: 0x20 */
437   __IO uint32_t EMR2;        /*!< EXTI Event mask register 2,                 Address offset: 0x24 */
438   __IO uint32_t RTSR2;       /*!< EXTI Rising trigger selection register 2,   Address offset: 0x28 */
439   __IO uint32_t FTSR2;       /*!< EXTI Falling trigger selection register 2,  Address offset: 0x2C */
440   __IO uint32_t SWIER2;      /*!< EXTI Software interrupt event register 2,   Address offset: 0x30 */
441   __IO uint32_t PR2;         /*!< EXTI Pending register 2,                    Address offset: 0x34 */
442 } EXTI_TypeDef;
443 
444 /**
445   * @brief FLASH Registers
446   */
447 
448 typedef struct
449 {
450   __IO uint32_t ACR;              /*!< FLASH access control register,            Address offset: 0x00 */
451   __IO uint32_t PDKEYR;           /*!< FLASH power down key register,            Address offset: 0x04 */
452   __IO uint32_t KEYR;             /*!< FLASH key register,                       Address offset: 0x08 */
453   __IO uint32_t OPTKEYR;          /*!< FLASH option key register,                Address offset: 0x0C */
454   __IO uint32_t SR;               /*!< FLASH status register,                    Address offset: 0x10 */
455   __IO uint32_t CR;               /*!< FLASH control register,                   Address offset: 0x14 */
456   __IO uint32_t ECCR;             /*!< FLASH ECC register,                       Address offset: 0x18 */
457        uint32_t RESERVED1;        /*!< Reserved1,                                Address offset: 0x1C */
458   __IO uint32_t OPTR;             /*!< FLASH option register,                    Address offset: 0x20 */
459   __IO uint32_t PCROP1SR;         /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
460   __IO uint32_t PCROP1ER;         /*!< FLASH bank1 PCROP end address register,   Address offset: 0x28 */
461   __IO uint32_t WRP1AR;           /*!< FLASH bank1 WRP area A address register,  Address offset: 0x2C */
462   __IO uint32_t WRP1BR;           /*!< FLASH bank1 WRP area B address register,  Address offset: 0x30 */
463        uint32_t RESERVED2[4];     /*!< Reserved2,                                Address offset: 0x34 */
464   __IO uint32_t PCROP2SR;         /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
465   __IO uint32_t PCROP2ER;         /*!< FLASH bank2 PCROP end address register,   Address offset: 0x48 */
466   __IO uint32_t WRP2AR;           /*!< FLASH bank2 WRP area A address register,  Address offset: 0x4C */
467   __IO uint32_t WRP2BR;           /*!< FLASH bank2 WRP area B address register,  Address offset: 0x50 */
468        uint32_t RESERVED3[7];     /*!< Reserved3,                                Address offset: 0x54 */
469   __IO uint32_t SEC1R;            /*!< FLASH Securable memory register bank1,    Address offset: 0x70 */
470   __IO uint32_t SEC2R;            /*!< FLASH Securable memory register bank2,    Address offset: 0x74 */
471 } FLASH_TypeDef;
472 
473 /**
474   * @brief FMAC
475   */
476 typedef struct
477 {
478   __IO uint32_t X1BUFCFG;        /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00          */
479   __IO uint32_t X2BUFCFG;        /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04          */
480   __IO uint32_t YBUFCFG;         /*!< FMAC Y Buffer Configuration register,  Address offset: 0x08          */
481   __IO uint32_t PARAM;           /*!< FMAC Parameter register,               Address offset: 0x0C          */
482   __IO uint32_t CR;              /*!< FMAC Control register,                 Address offset: 0x10          */
483   __IO uint32_t SR;              /*!< FMAC Status register,                  Address offset: 0x14          */
484   __IO uint32_t WDATA;           /*!< FMAC Write Data register,              Address offset: 0x18          */
485   __IO uint32_t RDATA;           /*!< FMAC Read Data register,               Address offset: 0x1C          */
486 } FMAC_TypeDef;
487 
488 /**
489   * @brief Flexible Memory Controller
490   */
491 
492 typedef struct
493 {
494   __IO uint32_t BTCR[8];     /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
495   __IO uint32_t PCSCNTR;     /*!< PSRAM chip-select counter register,                                               Address offset:    0x20 */
496 } FMC_Bank1_TypeDef;
497 
498 /**
499   * @brief Flexible Memory Controller Bank1E
500   */
501 
502 typedef struct
503 {
504   __IO uint32_t BWTR[7];     /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
505 } FMC_Bank1E_TypeDef;
506 
507 /**
508   * @brief Flexible Memory Controller Bank3
509   */
510 
511 typedef struct
512 {
513   __IO uint32_t PCR;        /*!< NAND Flash control register,                       Address offset: 0x80 */
514   __IO uint32_t SR;         /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */
515   __IO uint32_t PMEM;       /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */
516   __IO uint32_t PATT;       /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
517   uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                            */
518   __IO uint32_t ECCR;       /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */
519 } FMC_Bank3_TypeDef;
520 
521 /**
522   * @brief General Purpose I/O
523   */
524 
525 typedef struct
526 {
527   __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */
528   __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */
529   __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */
530   __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
531   __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */
532   __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */
533   __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
534   __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */
535   __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
536   __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */
537 } GPIO_TypeDef;
538 
539 /**
540   * @brief Inter-integrated Circuit Interface
541   */
542 
543 typedef struct
544 {
545   __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
546   __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
547   __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
548   __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
549   __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
550   __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
551   __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
552   __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
553   __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
554   __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
555   __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
556 } I2C_TypeDef;
557 
558 /**
559   * @brief Independent WATCHDOG
560   */
561 
562 typedef struct
563 {
564   __IO uint32_t KR;          /*!< IWDG Key register,       Address offset: 0x00 */
565   __IO uint32_t PR;          /*!< IWDG Prescaler register, Address offset: 0x04 */
566   __IO uint32_t RLR;         /*!< IWDG Reload register,    Address offset: 0x08 */
567   __IO uint32_t SR;          /*!< IWDG Status register,    Address offset: 0x0C */
568   __IO uint32_t WINR;        /*!< IWDG Window register,    Address offset: 0x10 */
569 } IWDG_TypeDef;
570 
571 /**
572   * @brief LPTIMER
573   */
574 
575 typedef struct
576 {
577   __IO uint32_t ISR;              /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
578   __IO uint32_t ICR;              /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
579   __IO uint32_t IER;              /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
580   __IO uint32_t CFGR;             /*!< LPTIM Configuration register,                       Address offset: 0x0C */
581   __IO uint32_t CR;               /*!< LPTIM Control register,                             Address offset: 0x10 */
582   __IO uint32_t CMP;              /*!< LPTIM Compare register,                             Address offset: 0x14 */
583   __IO uint32_t ARR;              /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
584   __IO uint32_t CNT;              /*!< LPTIM Counter register,                             Address offset: 0x1C */
585   __IO uint32_t OR;               /*!< LPTIM Option register,                              Address offset: 0x20 */
586 } LPTIM_TypeDef;
587 
588 /**
589   * @brief Operational Amplifier (OPAMP)
590   */
591 
592 typedef struct
593 {
594   __IO uint32_t CSR;           /*!< OPAMP control/status register,                     Address offset: 0x00 */
595   __IO uint32_t RESERVED[5];   /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */
596   __IO uint32_t TCMR;          /*!< OPAMP timer controlled mux mode register,          Address offset: 0x18 */
597 } OPAMP_TypeDef;
598 
599 /**
600   * @brief Power Control
601   */
602 
603 typedef struct
604 {
605   __IO uint32_t CR1;      /*!< PWR power control register 1,        Address offset: 0x00 */
606   __IO uint32_t CR2;      /*!< PWR power control register 2,        Address offset: 0x04 */
607   __IO uint32_t CR3;      /*!< PWR power control register 3,        Address offset: 0x08 */
608   __IO uint32_t CR4;      /*!< PWR power control register 4,        Address offset: 0x0C */
609   __IO uint32_t SR1;      /*!< PWR power status register 1,         Address offset: 0x10 */
610   __IO uint32_t SR2;      /*!< PWR power status register 2,         Address offset: 0x14 */
611   __IO uint32_t SCR;      /*!< PWR power status reset register,     Address offset: 0x18 */
612   uint32_t RESERVED;      /*!< Reserved,                            Address offset: 0x1C */
613   __IO uint32_t PUCRA;    /*!< Pull_up control register of portA,   Address offset: 0x20 */
614   __IO uint32_t PDCRA;    /*!< Pull_Down control register of portA, Address offset: 0x24 */
615   __IO uint32_t PUCRB;    /*!< Pull_up control register of portB,   Address offset: 0x28 */
616   __IO uint32_t PDCRB;    /*!< Pull_Down control register of portB, Address offset: 0x2C */
617   __IO uint32_t PUCRC;    /*!< Pull_up control register of portC,   Address offset: 0x30 */
618   __IO uint32_t PDCRC;    /*!< Pull_Down control register of portC, Address offset: 0x34 */
619   __IO uint32_t PUCRD;    /*!< Pull_up control register of portD,   Address offset: 0x38 */
620   __IO uint32_t PDCRD;    /*!< Pull_Down control register of portD, Address offset: 0x3C */
621   __IO uint32_t PUCRE;    /*!< Pull_up control register of portE,   Address offset: 0x40 */
622   __IO uint32_t PDCRE;    /*!< Pull_Down control register of portE, Address offset: 0x44 */
623   __IO uint32_t PUCRF;    /*!< Pull_up control register of portF,   Address offset: 0x48 */
624   __IO uint32_t PDCRF;    /*!< Pull_Down control register of portF, Address offset: 0x4C */
625   __IO uint32_t PUCRG;    /*!< Pull_up control register of portG,   Address offset: 0x50 */
626   __IO uint32_t PDCRG;    /*!< Pull_Down control register of portG, Address offset: 0x54 */
627   uint32_t RESERVED1[10]; /*!< Reserved                             Address offset: 0x58 - 0x7C */
628   __IO uint32_t CR5;      /*!< PWR power control register 5,        Address offset: 0x80 */
629 } PWR_TypeDef;
630 
631 /**
632   * @brief QUAD Serial Peripheral Interface
633   */
634 
635 typedef struct
636 {
637   __IO uint32_t CR;          /*!< QUADSPI Control register,                           Address offset: 0x00 */
638   __IO uint32_t DCR;         /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
639   __IO uint32_t SR;          /*!< QUADSPI Status register,                            Address offset: 0x08 */
640   __IO uint32_t FCR;         /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
641   __IO uint32_t DLR;         /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
642   __IO uint32_t CCR;         /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
643   __IO uint32_t AR;          /*!< QUADSPI Address register,                           Address offset: 0x18 */
644   __IO uint32_t ABR;         /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
645   __IO uint32_t DR;          /*!< QUADSPI Data register,                              Address offset: 0x20 */
646   __IO uint32_t PSMKR;       /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
647   __IO uint32_t PSMAR;       /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */
648   __IO uint32_t PIR;         /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
649   __IO uint32_t LPTR;        /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */
650 } QUADSPI_TypeDef;
651 
652 /**
653   * @brief Reset and Clock Control
654   */
655 
656 typedef struct
657 {
658   __IO uint32_t CR;          /*!< RCC clock control register,                                              Address offset: 0x00 */
659   __IO uint32_t ICSCR;       /*!< RCC internal clock sources calibration register,                         Address offset: 0x04 */
660   __IO uint32_t CFGR;        /*!< RCC clock configuration register,                                        Address offset: 0x08 */
661   __IO uint32_t PLLCFGR;     /*!< RCC system PLL configuration register,                                   Address offset: 0x0C */
662   uint32_t      RESERVED0;   /*!< Reserved,                                                                Address offset: 0x10 */
663   uint32_t      RESERVED1;   /*!< Reserved,                                                                Address offset: 0x14 */
664   __IO uint32_t CIER;        /*!< RCC clock interrupt enable register,                                     Address offset: 0x18 */
665   __IO uint32_t CIFR;        /*!< RCC clock interrupt flag register,                                       Address offset: 0x1C */
666   __IO uint32_t CICR;        /*!< RCC clock interrupt clear register,                                      Address offset: 0x20 */
667   uint32_t      RESERVED2;   /*!< Reserved,                                                                Address offset: 0x24 */
668   __IO uint32_t AHB1RSTR;    /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x28 */
669   __IO uint32_t AHB2RSTR;    /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x2C */
670   __IO uint32_t AHB3RSTR;    /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x30 */
671   uint32_t      RESERVED3;   /*!< Reserved,                                                                Address offset: 0x34 */
672   __IO uint32_t APB1RSTR1;   /*!< RCC APB1 peripheral reset register 1,                                    Address offset: 0x38 */
673   __IO uint32_t APB1RSTR2;   /*!< RCC APB1 peripheral reset register 2,                                    Address offset: 0x3C */
674   __IO uint32_t APB2RSTR;    /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x40 */
675   uint32_t      RESERVED4;   /*!< Reserved,                                                                Address offset: 0x44 */
676   __IO uint32_t AHB1ENR;     /*!< RCC AHB1 peripheral clocks enable register,                              Address offset: 0x48 */
677   __IO uint32_t AHB2ENR;     /*!< RCC AHB2 peripheral clocks enable register,                              Address offset: 0x4C */
678   __IO uint32_t AHB3ENR;     /*!< RCC AHB3 peripheral clocks enable register,                              Address offset: 0x50 */
679   uint32_t      RESERVED5;   /*!< Reserved,                                                                Address offset: 0x54 */
680   __IO uint32_t APB1ENR1;    /*!< RCC APB1 peripheral clocks enable register 1,                            Address offset: 0x58 */
681   __IO uint32_t APB1ENR2;    /*!< RCC APB1 peripheral clocks enable register 2,                            Address offset: 0x5C */
682   __IO uint32_t APB2ENR;     /*!< RCC APB2 peripheral clocks enable register,                              Address offset: 0x60 */
683   uint32_t      RESERVED6;   /*!< Reserved,                                                                Address offset: 0x64 */
684   __IO uint32_t AHB1SMENR;   /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x68 */
685   __IO uint32_t AHB2SMENR;   /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x6C */
686   __IO uint32_t AHB3SMENR;   /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x70 */
687   uint32_t      RESERVED7;   /*!< Reserved,                                                                Address offset: 0x74 */
688   __IO uint32_t APB1SMENR1;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
689   __IO uint32_t APB1SMENR2;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
690   __IO uint32_t APB2SMENR;   /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
691   uint32_t      RESERVED8;   /*!< Reserved,                                                                Address offset: 0x84 */
692   __IO uint32_t CCIPR;       /*!< RCC peripherals independent clock configuration register,                Address offset: 0x88 */
693   uint32_t      RESERVED9;   /*!< Reserved,                                                                Address offset: 0x8C */
694   __IO uint32_t BDCR;        /*!< RCC backup domain control register,                                      Address offset: 0x90 */
695   __IO uint32_t CSR;         /*!< RCC clock control & status register,                                     Address offset: 0x94 */
696   __IO uint32_t CRRCR;       /*!< RCC clock recovery RC register,                                          Address offset: 0x98 */
697   __IO uint32_t CCIPR2;      /*!< RCC peripherals independent clock configuration register 2,              Address offset: 0x9C */
698 } RCC_TypeDef;
699 
700 /**
701   * @brief Real-Time Clock
702   */
703 /*
704 * @brief Specific device feature definitions
705 */
706 #define RTC_TAMP_INT_6_SUPPORT
707 #define RTC_TAMP_INT_NB        4u
708 
709 #define RTC_TAMP_NB            3u
710 #define RTC_BACKUP_NB          32u
711 
712 
713 typedef struct
714 {
715   __IO uint32_t TR;          /*!< RTC time register,                                         Address offset: 0x00 */
716   __IO uint32_t DR;          /*!< RTC date register,                                         Address offset: 0x04 */
717   __IO uint32_t SSR;         /*!< RTC sub second register,                                   Address offset: 0x08 */
718   __IO uint32_t ICSR;        /*!< RTC initialization control and status register,            Address offset: 0x0C */
719   __IO uint32_t PRER;        /*!< RTC prescaler register,                                    Address offset: 0x10 */
720   __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
721   __IO uint32_t CR;          /*!< RTC control register,                                      Address offset: 0x18 */
722        uint32_t RESERVED0;   /*!< Reserved                                                   Address offset: 0x1C */
723        uint32_t RESERVED1;   /*!< Reserved                                                   Address offset: 0x20 */
724   __IO uint32_t WPR;         /*!< RTC write protection register,                             Address offset: 0x24 */
725   __IO uint32_t CALR;        /*!< RTC calibration register,                                  Address offset: 0x28 */
726   __IO uint32_t SHIFTR;      /*!< RTC shift control register,                                Address offset: 0x2C */
727   __IO uint32_t TSTR;        /*!< RTC time stamp time register,                              Address offset: 0x30 */
728   __IO uint32_t TSDR;        /*!< RTC time stamp date register,                              Address offset: 0x34 */
729   __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
730        uint32_t RESERVED2;   /*!< Reserved                                                   Address offset: 0x3C */
731   __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                                      Address offset: 0x40 */
732   __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
733   __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                                      Address offset: 0x48 */
734   __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                           Address offset: 0x4C */
735   __IO uint32_t SR;          /*!< RTC Status register,                                       Address offset: 0x50 */
736   __IO uint32_t MISR;        /*!< RTC Masked Interrupt Status register,                      Address offset: 0x54 */
737        uint32_t RESERVED3;   /*!< Reserved                                                   Address offset: 0x58 */
738   __IO uint32_t SCR;         /*!< RTC Status Clear register,                                 Address offset: 0x5C */
739 } RTC_TypeDef;
740 
741 /**
742   * @brief Tamper and backup registers
743   */
744 
745 typedef struct
746 {
747   __IO uint32_t CR1;                     /*!< TAMP configuration register 1,          Address offset: 0x00 */
748   __IO uint32_t CR2;                     /*!< TAMP configuration register 2,          Address offset: 0x04 */
749        uint32_t RESERVED0;               /*!< no configuration register 3,            Address offset: 0x08 */
750   __IO uint32_t FLTCR;                   /*!< TAMP filter control register,           Address offset: 0x0C */
751        uint32_t RESERVED1[6];            /*!< Reserved                                Address offset: 0x10 - 0x24 */
752        uint32_t RESERVED2;               /*!< Reserved                                Address offset: 0x28 */
753   __IO uint32_t IER;                     /*!< TAMP Interrupt enable register,         Address offset: 0x2C */
754   __IO uint32_t SR;                      /*!< TAMP Status register,                   Address offset: 0x30 */
755   __IO uint32_t MISR;                    /*!< TAMP Masked Interrupt Status register   Address offset: 0x34 */
756        uint32_t RESERVED3;               /*!< Reserved                                Address offset: 0x38 */
757   __IO uint32_t SCR;                     /*!< TAMP Status clear register,             Address offset: 0x3C */
758        uint32_t RESERVED4[48];           /*!< Reserved                                Address offset: 0x040 - 0xFC */
759   __IO uint32_t BKP0R;                   /*!< TAMP backup register 0,                 Address offset: 0x100 */
760   __IO uint32_t BKP1R;                   /*!< TAMP backup register 1,                 Address offset: 0x104 */
761   __IO uint32_t BKP2R;                   /*!< TAMP backup register 2,                 Address offset: 0x108 */
762   __IO uint32_t BKP3R;                   /*!< TAMP backup register 3,                 Address offset: 0x10C */
763   __IO uint32_t BKP4R;                   /*!< TAMP backup register 4,                 Address offset: 0x110 */
764   __IO uint32_t BKP5R;                   /*!< TAMP backup register 5,                 Address offset: 0x114 */
765   __IO uint32_t BKP6R;                   /*!< TAMP backup register 6,                 Address offset: 0x118 */
766   __IO uint32_t BKP7R;                   /*!< TAMP backup register 7,                 Address offset: 0x11C */
767   __IO uint32_t BKP8R;                   /*!< TAMP backup register 8,                 Address offset: 0x120 */
768   __IO uint32_t BKP9R;                   /*!< TAMP backup register 9,                 Address offset: 0x124 */
769   __IO uint32_t BKP10R;                  /*!< TAMP backup register 10,                Address offset: 0x128 */
770   __IO uint32_t BKP11R;                  /*!< TAMP backup register 11,                Address offset: 0x12C */
771   __IO uint32_t BKP12R;                  /*!< TAMP backup register 12,                Address offset: 0x130 */
772   __IO uint32_t BKP13R;                  /*!< TAMP backup register 13,                Address offset: 0x134 */
773   __IO uint32_t BKP14R;                  /*!< TAMP backup register 14,                Address offset: 0x138 */
774   __IO uint32_t BKP15R;                  /*!< TAMP backup register 15,                Address offset: 0x13C */
775   __IO uint32_t BKP16R;                  /*!< TAMP backup register 16,                Address offset: 0x140 */
776   __IO uint32_t BKP17R;                  /*!< TAMP backup register 17,                Address offset: 0x144 */
777   __IO uint32_t BKP18R;                  /*!< TAMP backup register 18,                Address offset: 0x148 */
778   __IO uint32_t BKP19R;                  /*!< TAMP backup register 19,                Address offset: 0x14C */
779   __IO uint32_t BKP20R;                  /*!< TAMP backup register 20,                Address offset: 0x150 */
780   __IO uint32_t BKP21R;                  /*!< TAMP backup register 21,                Address offset: 0x154 */
781   __IO uint32_t BKP22R;                  /*!< TAMP backup register 22,                Address offset: 0x158 */
782   __IO uint32_t BKP23R;                  /*!< TAMP backup register 23,                Address offset: 0x15C */
783   __IO uint32_t BKP24R;                  /*!< TAMP backup register 24,                Address offset: 0x160 */
784   __IO uint32_t BKP25R;                  /*!< TAMP backup register 25,                Address offset: 0x164 */
785   __IO uint32_t BKP26R;                  /*!< TAMP backup register 26,                Address offset: 0x168 */
786   __IO uint32_t BKP27R;                  /*!< TAMP backup register 27,                Address offset: 0x16C */
787   __IO uint32_t BKP28R;                  /*!< TAMP backup register 28,                Address offset: 0x170 */
788   __IO uint32_t BKP29R;                  /*!< TAMP backup register 29,                Address offset: 0x174 */
789   __IO uint32_t BKP30R;                  /*!< TAMP backup register 30,                Address offset: 0x178 */
790   __IO uint32_t BKP31R;                  /*!< TAMP backup register 31,                Address offset: 0x17C */
791 } TAMP_TypeDef;
792 
793 /**
794   * @brief Serial Audio Interface
795   */
796 
797 typedef struct
798 {
799   __IO uint32_t GCR;          /*!< SAI global configuration register,        Address offset: 0x00 */
800   uint32_t      RESERVED[16]; /*!< Reserved,                         Address offset: 0x04 to 0x40 */
801   __IO uint32_t PDMCR;        /*!< SAI PDM control register,                 Address offset: 0x44 */
802   __IO uint32_t PDMDLY;       /*!< SAI PDM delay register,                   Address offset: 0x48 */
803 } SAI_TypeDef;
804 
805 typedef struct
806 {
807   __IO uint32_t CR1;         /*!< SAI block x configuration register 1,     Address offset: 0x04 */
808   __IO uint32_t CR2;         /*!< SAI block x configuration register 2,     Address offset: 0x08 */
809   __IO uint32_t FRCR;        /*!< SAI block x frame configuration register, Address offset: 0x0C */
810   __IO uint32_t SLOTR;       /*!< SAI block x slot register,                Address offset: 0x10 */
811   __IO uint32_t IMR;         /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
812   __IO uint32_t SR;          /*!< SAI block x status register,              Address offset: 0x18 */
813   __IO uint32_t CLRFR;       /*!< SAI block x clear flag register,          Address offset: 0x1C */
814   __IO uint32_t DR;          /*!< SAI block x data register,                Address offset: 0x20 */
815 } SAI_Block_TypeDef;
816 
817 /**
818   * @brief Serial Peripheral Interface
819   */
820 
821 typedef struct
822 {
823   __IO uint32_t CR1;         /*!< SPI Control register 1,                              Address offset: 0x00 */
824   __IO uint32_t CR2;         /*!< SPI Control register 2,                              Address offset: 0x04 */
825   __IO uint32_t SR;          /*!< SPI Status register,                                 Address offset: 0x08 */
826   __IO uint32_t DR;          /*!< SPI data register,                                  Address offset: 0x0C */
827   __IO uint32_t CRCPR;       /*!< SPI CRC polynomial register,                         Address offset: 0x10 */
828   __IO uint32_t RXCRCR;      /*!< SPI Rx CRC register,                                 Address offset: 0x14 */
829   __IO uint32_t TXCRCR;      /*!< SPI Tx CRC register,                                 Address offset: 0x18 */
830   __IO uint32_t I2SCFGR;     /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
831   __IO uint32_t I2SPR;       /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
832 } SPI_TypeDef;
833 
834 /**
835   * @brief System configuration controller
836   */
837 
838 typedef struct
839 {
840   __IO uint32_t MEMRMP;      /*!< SYSCFG memory remap register,                        Address offset: 0x00      */
841   __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                     Address offset: 0x04      */
842   __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration registers,   Address offset: 0x08-0x14 */
843   __IO uint32_t SCSR;        /*!< SYSCFG CCMSRAM control and status register,          Address offset: 0x18      */
844   __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                     Address offset: 0x1C      */
845   __IO uint32_t SWPR;        /*!< SYSCFG CCMSRAM write protection register,            Address offset: 0x20      */
846   __IO uint32_t SKR;         /*!< SYSCFG CCMSRAM Key Register,                         Address offset: 0x24      */
847 } SYSCFG_TypeDef;
848 
849 /**
850   * @brief TIM
851   */
852 
853 typedef struct
854 {
855   __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
856   __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
857   __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
858   __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
859   __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
860   __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
861   __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
862   __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
863   __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
864   __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
865   __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */
866   __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
867   __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
868   __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
869   __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
870   __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
871   __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
872   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
873   __IO uint32_t CCR5;        /*!< TIM capture/compare register 5,           Address offset: 0x48 */
874   __IO uint32_t CCR6;        /*!< TIM capture/compare register 6,           Address offset: 0x4C */
875   __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x50 */
876   __IO uint32_t DTR2;        /*!< TIM deadtime register 2,                  Address offset: 0x54 */
877   __IO uint32_t ECR;         /*!< TIM encoder control register,             Address offset: 0x58 */
878   __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x5C */
879   __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */
880   __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */
881   __IO uint32_t OR ;         /*!< TIM option register,                      Address offset: 0x68 */
882        uint32_t RESERVED0[220];/*!< Reserved,                               Address offset: 0x6C */
883   __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x3DC */
884   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x3E0 */
885 } TIM_TypeDef;
886 
887 /**
888   * @brief Universal Synchronous Asynchronous Receiver Transmitter
889   */
890 typedef struct
891 {
892   __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00  */
893   __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04  */
894   __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08  */
895   __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C  */
896   __IO uint32_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10  */
897   __IO uint32_t RTOR;        /*!< USART Receiver Timeout register,          Address offset: 0x14  */
898   __IO uint32_t RQR;         /*!< USART Request register,                   Address offset: 0x18  */
899   __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C  */
900   __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20  */
901   __IO uint32_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24  */
902   __IO uint32_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28  */
903   __IO uint32_t PRESC;       /*!< USART Prescaler register,                 Address offset: 0x2C  */
904 } USART_TypeDef;
905 
906 /**
907   * @brief Universal Serial Bus Full Speed Device
908   */
909 
910 typedef struct
911 {
912   __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */
913   __IO uint16_t RESERVED0;       /*!< Reserved */
914   __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
915   __IO uint16_t RESERVED1;       /*!< Reserved */
916   __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
917   __IO uint16_t RESERVED2;       /*!< Reserved */
918   __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */
919   __IO uint16_t RESERVED3;       /*!< Reserved */
920   __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
921   __IO uint16_t RESERVED4;       /*!< Reserved */
922   __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
923   __IO uint16_t RESERVED5;       /*!< Reserved */
924   __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
925   __IO uint16_t RESERVED6;       /*!< Reserved */
926   __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
927   __IO uint16_t RESERVED7[17];   /*!< Reserved */
928   __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
929   __IO uint16_t RESERVED8;       /*!< Reserved */
930   __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
931   __IO uint16_t RESERVED9;       /*!< Reserved */
932   __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
933   __IO uint16_t RESERVEDA;       /*!< Reserved */
934   __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
935   __IO uint16_t RESERVEDB;       /*!< Reserved */
936   __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
937   __IO uint16_t RESERVEDC;       /*!< Reserved */
938   __IO uint16_t LPMCSR;          /*!< LPM Control and Status register,        Address offset: 0x54 */
939   __IO uint16_t RESERVEDD;       /*!< Reserved */
940   __IO uint16_t BCDR;            /*!< Battery Charging detector register,     Address offset: 0x58 */
941   __IO uint16_t RESERVEDE;       /*!< Reserved */
942 } USB_TypeDef;
943 
944 /**
945   * @brief VREFBUF
946   */
947 
948 typedef struct
949 {
950   __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
951   __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
952 } VREFBUF_TypeDef;
953 
954 /**
955   * @brief Window WATCHDOG
956   */
957 
958 typedef struct
959 {
960   __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */
961   __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */
962   __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */
963 } WWDG_TypeDef;
964 
965 
966 /**
967   * @brief RNG
968   */
969 typedef struct
970 {
971   __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
972   __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
973   __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
974 } RNG_TypeDef;
975 
976 /**
977   * @brief CORDIC
978   */
979 
980 typedef struct
981 {
982   __IO uint32_t CSR;          /*!< CORDIC control and status register,        Address offset: 0x00 */
983   __IO uint32_t WDATA;        /*!< CORDIC argument register,                  Address offset: 0x04 */
984   __IO uint32_t RDATA;        /*!< CORDIC result register,                    Address offset: 0x08 */
985 } CORDIC_TypeDef;
986 
987 /**
988   * @brief UCPD
989   */
990 
991 typedef struct
992 {
993   __IO uint32_t CFG1;          /*!< UCPD configuration register 1,             Address offset: 0x00 */
994   __IO uint32_t CFG2;          /*!< UCPD configuration register 2,             Address offset: 0x04 */
995   __IO uint32_t RESERVED0;     /*!< UCPD reserved register,                    Address offset: 0x08 */
996   __IO uint32_t CR;            /*!< UCPD control register,                     Address offset: 0x0C */
997   __IO uint32_t IMR;           /*!< UCPD interrupt mask register,              Address offset: 0x10 */
998   __IO uint32_t SR;            /*!< UCPD status register,                      Address offset: 0x14 */
999   __IO uint32_t ICR;           /*!< UCPD interrupt flag clear register         Address offset: 0x18 */
1000   __IO uint32_t TX_ORDSET;     /*!< UCPD Tx ordered set type register,         Address offset: 0x1C */
1001   __IO uint32_t TX_PAYSZ;      /*!< UCPD Tx payload size register,             Address offset: 0x20 */
1002   __IO uint32_t TXDR;          /*!< UCPD Tx data register,                     Address offset: 0x24 */
1003   __IO uint32_t RX_ORDSET;     /*!< UCPD Rx ordered set type register,         Address offset: 0x28 */
1004   __IO uint32_t RX_PAYSZ;      /*!< UCPD Rx payload size register,             Address offset: 0x2C */
1005   __IO uint32_t RXDR;          /*!< UCPD Rx data register,                     Address offset: 0x30 */
1006   __IO uint32_t RX_ORDEXT1;    /*!< UCPD Rx ordered set extension 1 register,  Address offset: 0x34 */
1007   __IO uint32_t RX_ORDEXT2;    /*!< UCPD Rx ordered set extension 2 register,  Address offset: 0x38 */
1008 } UCPD_TypeDef;
1009 
1010 
1011 /**
1012   * @}
1013   */
1014 
1015 /** @addtogroup Peripheral_memory_map
1016   * @{
1017   */
1018 
1019 #define FLASH_BASE            (0x08000000UL) /*!< FLASH (up to 512 kB) base address */
1020 #define SRAM1_BASE            (0x20000000UL) /*!< SRAM1(up to 80 KB) base address */
1021 #define SRAM2_BASE            (0x20014000UL) /*!< SRAM2(16 KB) base address */
1022 #define CCMSRAM_BASE          (0x10000000UL) /*!< CCMSRAM(32 KB) base address */
1023 #define PERIPH_BASE           (0x40000000UL) /*!< Peripheral base address */
1024 #define FMC_BASE              (0x60000000UL) /*!< FMC base address */
1025 #define QSPI_BASE             (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */
1026 
1027 #define FMC_R_BASE            (0xA0000000UL) /*!< FMC  control registers base address */
1028 #define QSPI_R_BASE           (0xA0001000UL) /*!< QUADSPI control registers base address */
1029 #define SRAM1_BB_BASE         (0x22000000UL) /*!< SRAM1(80 KB) base address in the bit-band region */
1030 #define SRAM2_BB_BASE         (0x22280000UL) /*!< SRAM2(16 KB) base address in the bit-band region */
1031 #define CCMSRAM_BB_BASE       (0x22300000UL) /*!< CCMSRAM(32 KB) base address in the bit-band region */
1032 #define PERIPH_BB_BASE        (0x42000000UL) /*!< Peripheral base address in the bit-band region */
1033 /* Legacy defines */
1034 #define SRAM_BASE             SRAM1_BASE
1035 #define SRAM_BB_BASE          SRAM1_BB_BASE
1036 
1037 #define SRAM1_SIZE_MAX        (0x00014000UL) /*!< maximum SRAM1 size (up to 80 KBytes) */
1038 #define SRAM2_SIZE            (0x00004000UL) /*!< SRAM2 size (16 KBytes) */
1039 #define CCMSRAM_SIZE          (0x00008000UL) /*!< CCMSRAM size (32 KBytes) */
1040 
1041 /*!< Peripheral memory map */
1042 #define APB1PERIPH_BASE        PERIPH_BASE
1043 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
1044 #define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
1045 #define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)
1046 
1047 #define FMC_BANK1             FMC_BASE
1048 #define FMC_BANK1_1           FMC_BANK1
1049 #define FMC_BANK1_2           (FMC_BANK1 + 0x04000000UL)
1050 #define FMC_BANK1_3           (FMC_BANK1 + 0x08000000UL)
1051 #define FMC_BANK1_4           (FMC_BANK1 + 0x0C000000UL)
1052 #define FMC_BANK3             (FMC_BASE  + 0x20000000UL)
1053 
1054 /*!< APB1 peripherals */
1055 #define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)
1056 #define TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)
1057 #define TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)
1058 #define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)
1059 #define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)
1060 #define TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)
1061 #define CRS_BASE              (APB1PERIPH_BASE + 0x2000UL)
1062 #define TAMP_BASE             (APB1PERIPH_BASE + 0x2400UL)
1063 #define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)
1064 #define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)
1065 #define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)
1066 #define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)
1067 #define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)
1068 #define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)
1069 #define USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)
1070 #define UART4_BASE            (APB1PERIPH_BASE + 0x4C00UL)
1071 #define UART5_BASE            (APB1PERIPH_BASE + 0x5000UL)
1072 #define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)
1073 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)
1074 #define USB_BASE              (APB1PERIPH_BASE + 0x5C00UL)  /*!< USB_IP Peripheral Registers base address */
1075 #define USB_PMAADDR           (APB1PERIPH_BASE + 0x6000UL)  /*!< USB_IP Packet Memory Area base address */
1076 #define FDCAN1_BASE           (APB1PERIPH_BASE + 0x6400UL)
1077 #define FDCAN_CONFIG_BASE     (APB1PERIPH_BASE + 0x6500UL)  /*!< FDCAN configuration registers base address */
1078 #define FDCAN2_BASE           (APB1PERIPH_BASE + 0x6800UL)
1079 #define FDCAN3_BASE           (APB1PERIPH_BASE + 0x6C00UL)
1080 #define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)
1081 #define I2C3_BASE             (APB1PERIPH_BASE + 0x7800UL)
1082 #define LPTIM1_BASE           (APB1PERIPH_BASE + 0x7C00UL)
1083 #define LPUART1_BASE          (APB1PERIPH_BASE + 0x8000UL)
1084 #define I2C4_BASE             (APB1PERIPH_BASE + 0x8400UL)
1085 #define UCPD1_BASE            (APB1PERIPH_BASE + 0xA000UL)
1086 #define SRAMCAN_BASE          (APB1PERIPH_BASE + 0xA400UL)
1087 
1088 /*!< APB2 peripherals */
1089 #define SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000UL)
1090 #define VREFBUF_BASE          (APB2PERIPH_BASE + 0x0030UL)
1091 #define COMP1_BASE            (APB2PERIPH_BASE + 0x0200UL)
1092 #define COMP2_BASE            (APB2PERIPH_BASE + 0x0204UL)
1093 #define COMP3_BASE            (APB2PERIPH_BASE + 0x0208UL)
1094 #define COMP4_BASE            (APB2PERIPH_BASE + 0x020CUL)
1095 #define COMP5_BASE            (APB2PERIPH_BASE + 0x0210UL)
1096 #define COMP6_BASE            (APB2PERIPH_BASE + 0x0214UL)
1097 #define COMP7_BASE            (APB2PERIPH_BASE + 0x0218UL)
1098 #define OPAMP_BASE            (APB2PERIPH_BASE + 0x0300UL)
1099 #define OPAMP1_BASE           (APB2PERIPH_BASE + 0x0300UL)
1100 #define OPAMP2_BASE           (APB2PERIPH_BASE + 0x0304UL)
1101 #define OPAMP3_BASE           (APB2PERIPH_BASE + 0x0308UL)
1102 #define OPAMP4_BASE           (APB2PERIPH_BASE + 0x030CUL)
1103 #define OPAMP5_BASE           (APB2PERIPH_BASE + 0x0310UL)
1104 #define OPAMP6_BASE           (APB2PERIPH_BASE + 0x0314UL)
1105 
1106 #define EXTI_BASE             (APB2PERIPH_BASE + 0x0400UL)
1107 #define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00UL)
1108 #define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)
1109 #define TIM8_BASE             (APB2PERIPH_BASE + 0x3400UL)
1110 #define USART1_BASE           (APB2PERIPH_BASE + 0x3800UL)
1111 #define SPI4_BASE             (APB2PERIPH_BASE + 0x3C00UL)
1112 #define TIM15_BASE            (APB2PERIPH_BASE + 0x4000UL)
1113 #define TIM16_BASE            (APB2PERIPH_BASE + 0x4400UL)
1114 #define TIM17_BASE            (APB2PERIPH_BASE + 0x4800UL)
1115 #define TIM20_BASE            (APB2PERIPH_BASE + 0x5000UL)
1116 #define SAI1_BASE             (APB2PERIPH_BASE + 0x5400UL)
1117 #define SAI1_Block_A_BASE     (SAI1_BASE + 0x0004UL)
1118 #define SAI1_Block_B_BASE     (SAI1_BASE + 0x0024UL)
1119 
1120 /*!< AHB1 peripherals */
1121 #define DMA1_BASE             (AHB1PERIPH_BASE)
1122 #define DMA2_BASE             (AHB1PERIPH_BASE + 0x0400UL)
1123 #define DMAMUX1_BASE          (AHB1PERIPH_BASE + 0x0800UL)
1124 #define CORDIC_BASE           (AHB1PERIPH_BASE + 0x0C00UL)
1125 #define RCC_BASE              (AHB1PERIPH_BASE + 0x1000UL)
1126 #define FMAC_BASE             (AHB1PERIPH_BASE + 0x1400UL)
1127 #define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x2000UL)
1128 #define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)
1129 
1130 #define DMA1_Channel1_BASE    (DMA1_BASE + 0x0008UL)
1131 #define DMA1_Channel2_BASE    (DMA1_BASE + 0x001CUL)
1132 #define DMA1_Channel3_BASE    (DMA1_BASE + 0x0030UL)
1133 #define DMA1_Channel4_BASE    (DMA1_BASE + 0x0044UL)
1134 #define DMA1_Channel5_BASE    (DMA1_BASE + 0x0058UL)
1135 #define DMA1_Channel6_BASE    (DMA1_BASE + 0x006CUL)
1136 #define DMA1_Channel7_BASE    (DMA1_BASE + 0x0080UL)
1137 #define DMA1_Channel8_BASE    (DMA1_BASE + 0x0094UL)
1138 
1139 #define DMA2_Channel1_BASE    (DMA2_BASE + 0x0008UL)
1140 #define DMA2_Channel2_BASE    (DMA2_BASE + 0x001CUL)
1141 #define DMA2_Channel3_BASE    (DMA2_BASE + 0x0030UL)
1142 #define DMA2_Channel4_BASE    (DMA2_BASE + 0x0044UL)
1143 #define DMA2_Channel5_BASE    (DMA2_BASE + 0x0058UL)
1144 #define DMA2_Channel6_BASE    (DMA2_BASE + 0x006CUL)
1145 #define DMA2_Channel7_BASE    (DMA2_BASE + 0x0080UL)
1146 #define DMA2_Channel8_BASE    (DMA2_BASE + 0x0094UL)
1147 
1148 #define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)
1149 #define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004UL)
1150 #define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008UL)
1151 #define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000CUL)
1152 #define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010UL)
1153 #define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014UL)
1154 #define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0018UL)
1155 #define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x001CUL)
1156 #define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x0020UL)
1157 #define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x0024UL)
1158 #define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)
1159 #define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)
1160 #define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)
1161 #define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)
1162 #define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)
1163 #define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)
1164 #define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100UL)
1165 #define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104UL)
1166 #define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108UL)
1167 #define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010CUL)
1168 
1169 #define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080UL)
1170 #define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)
1171 
1172 /*!< AHB2 peripherals */
1173 #define GPIOA_BASE            (AHB2PERIPH_BASE + 0x0000UL)
1174 #define GPIOB_BASE            (AHB2PERIPH_BASE + 0x0400UL)
1175 #define GPIOC_BASE            (AHB2PERIPH_BASE + 0x0800UL)
1176 #define GPIOD_BASE            (AHB2PERIPH_BASE + 0x0C00UL)
1177 #define GPIOE_BASE            (AHB2PERIPH_BASE + 0x1000UL)
1178 #define GPIOF_BASE            (AHB2PERIPH_BASE + 0x1400UL)
1179 #define GPIOG_BASE            (AHB2PERIPH_BASE + 0x1800UL)
1180 
1181 #define ADC1_BASE             (AHB2PERIPH_BASE + 0x08000000UL)
1182 #define ADC2_BASE             (AHB2PERIPH_BASE + 0x08000100UL)
1183 #define ADC12_COMMON_BASE     (AHB2PERIPH_BASE + 0x08000300UL)
1184 #define ADC3_BASE             (AHB2PERIPH_BASE + 0x08000400UL)
1185 #define ADC4_BASE             (AHB2PERIPH_BASE + 0x08000500UL)
1186 #define ADC5_BASE             (AHB2PERIPH_BASE + 0x08000600UL)
1187 #define ADC345_COMMON_BASE    (AHB2PERIPH_BASE + 0x08000700UL)
1188 
1189 #define DAC_BASE              (AHB2PERIPH_BASE + 0x08000800UL)
1190 #define DAC1_BASE             (AHB2PERIPH_BASE + 0x08000800UL)
1191 #define DAC2_BASE             (AHB2PERIPH_BASE + 0x08000C00UL)
1192 #define DAC3_BASE             (AHB2PERIPH_BASE + 0x08001000UL)
1193 #define DAC4_BASE             (AHB2PERIPH_BASE + 0x08001400UL)
1194 
1195 /*!< FMC Banks registers base  address */
1196 #define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)
1197 #define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)
1198 #define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)
1199 #define RNG_BASE              (AHB2PERIPH_BASE + 0x08060800UL)
1200 /* Debug MCU registers base address */
1201 #define DBGMCU_BASE           (0xE0042000UL)
1202 
1203 #define PACKAGE_BASE          (0x1FFF7500UL)        /*!< Package data register base address     */
1204 #define UID_BASE              (0x1FFF7590UL)        /*!< Unique device ID register base address */
1205 #define FLASHSIZE_BASE        (0x1FFF75E0UL)        /*!< Flash size data register base address  */
1206 /**
1207   * @}
1208   */
1209 
1210 /** @addtogroup Peripheral_declaration
1211   * @{
1212   */
1213 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
1214 #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
1215 #define TIM4                ((TIM_TypeDef *) TIM4_BASE)
1216 #define TIM5                ((TIM_TypeDef *) TIM5_BASE)
1217 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
1218 #define TIM7                ((TIM_TypeDef *) TIM7_BASE)
1219 #define CRS                 ((CRS_TypeDef *) CRS_BASE)
1220 #define TAMP                ((TAMP_TypeDef *) TAMP_BASE)
1221 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
1222 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
1223 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
1224 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
1225 #define SPI3                ((SPI_TypeDef *) SPI3_BASE)
1226 #define USART2              ((USART_TypeDef *) USART2_BASE)
1227 #define USART3              ((USART_TypeDef *) USART3_BASE)
1228 #define UART4               ((USART_TypeDef *) UART4_BASE)
1229 #define UART5               ((USART_TypeDef *) UART5_BASE)
1230 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
1231 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
1232 #define USB                 ((USB_TypeDef *) USB_BASE)
1233 #define FDCAN1              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
1234 #define FDCAN_CONFIG        ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE)
1235 #define FDCAN2              ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
1236 #define FDCAN3              ((FDCAN_GlobalTypeDef *) FDCAN3_BASE)
1237 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
1238 #define I2C3                ((I2C_TypeDef *) I2C3_BASE)
1239 #define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
1240 #define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
1241 #define I2C4                ((I2C_TypeDef *) I2C4_BASE)
1242 #define UCPD1              ((UCPD_TypeDef *) UCPD1_BASE)
1243 
1244 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
1245 #define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)
1246 #define COMP1               ((COMP_TypeDef *) COMP1_BASE)
1247 #define COMP2               ((COMP_TypeDef *) COMP2_BASE)
1248 #define COMP3               ((COMP_TypeDef *) COMP3_BASE)
1249 #define COMP4               ((COMP_TypeDef *) COMP4_BASE)
1250 #define COMP5               ((COMP_TypeDef *) COMP5_BASE)
1251 #define COMP6               ((COMP_TypeDef *) COMP6_BASE)
1252 #define COMP7               ((COMP_TypeDef *) COMP7_BASE)
1253 
1254 #define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
1255 #define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)
1256 #define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)
1257 #define OPAMP3              ((OPAMP_TypeDef *) OPAMP3_BASE)
1258 #define OPAMP4              ((OPAMP_TypeDef *) OPAMP4_BASE)
1259 #define OPAMP5              ((OPAMP_TypeDef *) OPAMP5_BASE)
1260 #define OPAMP6              ((OPAMP_TypeDef *) OPAMP6_BASE)
1261 
1262 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
1263 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
1264 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
1265 #define TIM8                ((TIM_TypeDef *) TIM8_BASE)
1266 #define USART1              ((USART_TypeDef *) USART1_BASE)
1267 #define SPI4                ((SPI_TypeDef *) SPI4_BASE)
1268 #define TIM15               ((TIM_TypeDef *) TIM15_BASE)
1269 #define TIM16               ((TIM_TypeDef *) TIM16_BASE)
1270 #define TIM17               ((TIM_TypeDef *) TIM17_BASE)
1271 #define TIM20               ((TIM_TypeDef *) TIM20_BASE)
1272 #define SAI1                ((SAI_TypeDef *) SAI1_BASE)
1273 #define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1274 #define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1275 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
1276 #define DMA2                ((DMA_TypeDef *) DMA2_BASE)
1277 #define DMAMUX1             ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
1278 #define CORDIC              ((CORDIC_TypeDef *) CORDIC_BASE)
1279 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
1280 #define FMAC                ((FMAC_TypeDef *) FMAC_BASE)
1281 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
1282 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
1283 
1284 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
1285 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
1286 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
1287 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
1288 #define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
1289 #define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
1290 #define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
1291 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
1292 #define ADC2                ((ADC_TypeDef *) ADC2_BASE)
1293 #define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
1294 #define ADC3                ((ADC_TypeDef *) ADC3_BASE)
1295 #define ADC4                ((ADC_TypeDef *) ADC4_BASE)
1296 #define ADC5                ((ADC_TypeDef *) ADC5_BASE)
1297 #define ADC345_COMMON       ((ADC_Common_TypeDef *) ADC345_COMMON_BASE)
1298 #define DAC                 ((DAC_TypeDef *) DAC_BASE)
1299 #define DAC1                ((DAC_TypeDef *) DAC1_BASE)
1300 #define DAC2                ((DAC_TypeDef *) DAC2_BASE)
1301 #define DAC3                ((DAC_TypeDef *) DAC3_BASE)
1302 #define DAC4                ((DAC_TypeDef *) DAC4_BASE)
1303 #define RNG                 ((RNG_TypeDef *) RNG_BASE)
1304 
1305 #define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
1306 #define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
1307 #define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
1308 #define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
1309 #define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
1310 #define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
1311 #define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
1312 #define DMA1_Channel8       ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE)
1313 
1314 #define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
1315 #define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
1316 #define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
1317 #define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
1318 #define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
1319 #define DMA2_Channel6       ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
1320 #define DMA2_Channel7       ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
1321 #define DMA2_Channel8       ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE)
1322 
1323 #define DMAMUX1_Channel0    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
1324 #define DMAMUX1_Channel1    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
1325 #define DMAMUX1_Channel2    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
1326 #define DMAMUX1_Channel3    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
1327 #define DMAMUX1_Channel4    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
1328 #define DMAMUX1_Channel5    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
1329 #define DMAMUX1_Channel6    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
1330 #define DMAMUX1_Channel7    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
1331 #define DMAMUX1_Channel8    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
1332 #define DMAMUX1_Channel9    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
1333 #define DMAMUX1_Channel10   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
1334 #define DMAMUX1_Channel11   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
1335 #define DMAMUX1_Channel12   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
1336 #define DMAMUX1_Channel13   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
1337 #define DMAMUX1_Channel14   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
1338 #define DMAMUX1_Channel15   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
1339 
1340 #define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
1341 #define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
1342 #define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
1343 #define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
1344 
1345 #define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
1346 #define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
1347 
1348 #define FMC_Bank1_R         ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1349 #define FMC_Bank1E_R        ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1350 #define FMC_Bank3_R         ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1351 
1352 #define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
1353 
1354 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
1355 
1356 /**
1357   * @}
1358   */
1359 
1360 /** @addtogroup Exported_constants
1361   * @{
1362   */
1363 
1364   /** @addtogroup Hardware_Constant_Definition
1365     * @{
1366     */
1367 #define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
1368 
1369   /**
1370     * @}
1371     */
1372 
1373 /** @addtogroup Peripheral_Registers_Bits_Definition
1374   * @{
1375   */
1376 
1377 /******************************************************************************/
1378 /*                         Peripheral Registers_Bits_Definition               */
1379 /******************************************************************************/
1380 
1381 /******************************************************************************/
1382 /*                                                                            */
1383 /*                        Analog to Digital Converter                         */
1384 /*                                                                            */
1385 /******************************************************************************/
1386 
1387 /*
1388  * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
1389  */
1390 #define ADC_MULTIMODE_SUPPORT                          /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
1391 
1392 /********************  Bit definition for ADC_ISR register  *******************/
1393 #define ADC_ISR_ADRDY_Pos              (0U)
1394 #define ADC_ISR_ADRDY_Msk              (0x1UL << ADC_ISR_ADRDY_Pos)            /*!< 0x00000001 */
1395 #define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
1396 #define ADC_ISR_EOSMP_Pos              (1U)
1397 #define ADC_ISR_EOSMP_Msk              (0x1UL << ADC_ISR_EOSMP_Pos)            /*!< 0x00000002 */
1398 #define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
1399 #define ADC_ISR_EOC_Pos                (2U)
1400 #define ADC_ISR_EOC_Msk                (0x1UL << ADC_ISR_EOC_Pos)              /*!< 0x00000004 */
1401 #define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
1402 #define ADC_ISR_EOS_Pos                (3U)
1403 #define ADC_ISR_EOS_Msk                (0x1UL << ADC_ISR_EOS_Pos)              /*!< 0x00000008 */
1404 #define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
1405 #define ADC_ISR_OVR_Pos                (4U)
1406 #define ADC_ISR_OVR_Msk                (0x1UL << ADC_ISR_OVR_Pos)              /*!< 0x00000010 */
1407 #define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
1408 #define ADC_ISR_JEOC_Pos               (5U)
1409 #define ADC_ISR_JEOC_Msk               (0x1UL << ADC_ISR_JEOC_Pos)             /*!< 0x00000020 */
1410 #define ADC_ISR_JEOC                   ADC_ISR_JEOC_Msk                        /*!< ADC group injected end of unitary conversion flag */
1411 #define ADC_ISR_JEOS_Pos               (6U)
1412 #define ADC_ISR_JEOS_Msk               (0x1UL << ADC_ISR_JEOS_Pos)             /*!< 0x00000040 */
1413 #define ADC_ISR_JEOS                   ADC_ISR_JEOS_Msk                        /*!< ADC group injected end of sequence conversions flag */
1414 #define ADC_ISR_AWD1_Pos               (7U)
1415 #define ADC_ISR_AWD1_Msk               (0x1UL << ADC_ISR_AWD1_Pos)             /*!< 0x00000080 */
1416 #define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
1417 #define ADC_ISR_AWD2_Pos               (8U)
1418 #define ADC_ISR_AWD2_Msk               (0x1UL << ADC_ISR_AWD2_Pos)             /*!< 0x00000100 */
1419 #define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
1420 #define ADC_ISR_AWD3_Pos               (9U)
1421 #define ADC_ISR_AWD3_Msk               (0x1UL << ADC_ISR_AWD3_Pos)             /*!< 0x00000200 */
1422 #define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
1423 #define ADC_ISR_JQOVF_Pos              (10U)
1424 #define ADC_ISR_JQOVF_Msk              (0x1UL << ADC_ISR_JQOVF_Pos)            /*!< 0x00000400 */
1425 #define ADC_ISR_JQOVF                  ADC_ISR_JQOVF_Msk                       /*!< ADC group injected contexts queue overflow flag */
1426 
1427 /********************  Bit definition for ADC_IER register  *******************/
1428 #define ADC_IER_ADRDYIE_Pos            (0U)
1429 #define ADC_IER_ADRDYIE_Msk            (0x1UL << ADC_IER_ADRDYIE_Pos)          /*!< 0x00000001 */
1430 #define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
1431 #define ADC_IER_EOSMPIE_Pos            (1U)
1432 #define ADC_IER_EOSMPIE_Msk            (0x1UL << ADC_IER_EOSMPIE_Pos)          /*!< 0x00000002 */
1433 #define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
1434 #define ADC_IER_EOCIE_Pos              (2U)
1435 #define ADC_IER_EOCIE_Msk              (0x1UL << ADC_IER_EOCIE_Pos)            /*!< 0x00000004 */
1436 #define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
1437 #define ADC_IER_EOSIE_Pos              (3U)
1438 #define ADC_IER_EOSIE_Msk              (0x1UL << ADC_IER_EOSIE_Pos)            /*!< 0x00000008 */
1439 #define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
1440 #define ADC_IER_OVRIE_Pos              (4U)
1441 #define ADC_IER_OVRIE_Msk              (0x1UL << ADC_IER_OVRIE_Pos)            /*!< 0x00000010 */
1442 #define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
1443 #define ADC_IER_JEOCIE_Pos             (5U)
1444 #define ADC_IER_JEOCIE_Msk             (0x1UL << ADC_IER_JEOCIE_Pos)           /*!< 0x00000020 */
1445 #define ADC_IER_JEOCIE                 ADC_IER_JEOCIE_Msk                      /*!< ADC group injected end of unitary conversion interrupt */
1446 #define ADC_IER_JEOSIE_Pos             (6U)
1447 #define ADC_IER_JEOSIE_Msk             (0x1UL << ADC_IER_JEOSIE_Pos)           /*!< 0x00000040 */
1448 #define ADC_IER_JEOSIE                 ADC_IER_JEOSIE_Msk                      /*!< ADC group injected end of sequence conversions interrupt */
1449 #define ADC_IER_AWD1IE_Pos             (7U)
1450 #define ADC_IER_AWD1IE_Msk             (0x1UL << ADC_IER_AWD1IE_Pos)           /*!< 0x00000080 */
1451 #define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
1452 #define ADC_IER_AWD2IE_Pos             (8U)
1453 #define ADC_IER_AWD2IE_Msk             (0x1UL << ADC_IER_AWD2IE_Pos)           /*!< 0x00000100 */
1454 #define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
1455 #define ADC_IER_AWD3IE_Pos             (9U)
1456 #define ADC_IER_AWD3IE_Msk             (0x1UL << ADC_IER_AWD3IE_Pos)           /*!< 0x00000200 */
1457 #define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
1458 #define ADC_IER_JQOVFIE_Pos            (10U)
1459 #define ADC_IER_JQOVFIE_Msk            (0x1UL << ADC_IER_JQOVFIE_Pos)          /*!< 0x00000400 */
1460 #define ADC_IER_JQOVFIE                ADC_IER_JQOVFIE_Msk                     /*!< ADC group injected contexts queue overflow interrupt */
1461 
1462 /********************  Bit definition for ADC_CR register  ********************/
1463 #define ADC_CR_ADEN_Pos                (0U)
1464 #define ADC_CR_ADEN_Msk                (0x1UL << ADC_CR_ADEN_Pos)              /*!< 0x00000001 */
1465 #define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
1466 #define ADC_CR_ADDIS_Pos               (1U)
1467 #define ADC_CR_ADDIS_Msk               (0x1UL << ADC_CR_ADDIS_Pos)             /*!< 0x00000002 */
1468 #define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
1469 #define ADC_CR_ADSTART_Pos             (2U)
1470 #define ADC_CR_ADSTART_Msk             (0x1UL << ADC_CR_ADSTART_Pos)           /*!< 0x00000004 */
1471 #define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
1472 #define ADC_CR_JADSTART_Pos            (3U)
1473 #define ADC_CR_JADSTART_Msk            (0x1UL << ADC_CR_JADSTART_Pos)          /*!< 0x00000008 */
1474 #define ADC_CR_JADSTART                ADC_CR_JADSTART_Msk                     /*!< ADC group injected conversion start */
1475 #define ADC_CR_ADSTP_Pos               (4U)
1476 #define ADC_CR_ADSTP_Msk               (0x1UL << ADC_CR_ADSTP_Pos)             /*!< 0x00000010 */
1477 #define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
1478 #define ADC_CR_JADSTP_Pos              (5U)
1479 #define ADC_CR_JADSTP_Msk              (0x1UL << ADC_CR_JADSTP_Pos)            /*!< 0x00000020 */
1480 #define ADC_CR_JADSTP                  ADC_CR_JADSTP_Msk                       /*!< ADC group injected conversion stop */
1481 #define ADC_CR_ADVREGEN_Pos            (28U)
1482 #define ADC_CR_ADVREGEN_Msk            (0x1UL << ADC_CR_ADVREGEN_Pos)          /*!< 0x10000000 */
1483 #define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */
1484 #define ADC_CR_DEEPPWD_Pos             (29U)
1485 #define ADC_CR_DEEPPWD_Msk             (0x1UL << ADC_CR_DEEPPWD_Pos)           /*!< 0x20000000 */
1486 #define ADC_CR_DEEPPWD                 ADC_CR_DEEPPWD_Msk                      /*!< ADC deep power down enable */
1487 #define ADC_CR_ADCALDIF_Pos            (30U)
1488 #define ADC_CR_ADCALDIF_Msk            (0x1UL << ADC_CR_ADCALDIF_Pos)          /*!< 0x40000000 */
1489 #define ADC_CR_ADCALDIF                ADC_CR_ADCALDIF_Msk                     /*!< ADC differential mode for calibration */
1490 #define ADC_CR_ADCAL_Pos               (31U)
1491 #define ADC_CR_ADCAL_Msk               (0x1UL << ADC_CR_ADCAL_Pos)             /*!< 0x80000000 */
1492 #define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
1493 
1494 /********************  Bit definition for ADC_CFGR register  ******************/
1495 #define ADC_CFGR_DMAEN_Pos             (0U)
1496 #define ADC_CFGR_DMAEN_Msk             (0x1UL << ADC_CFGR_DMAEN_Pos)           /*!< 0x00000001 */
1497 #define ADC_CFGR_DMAEN                 ADC_CFGR_DMAEN_Msk                      /*!< ADC DMA transfer enable */
1498 #define ADC_CFGR_DMACFG_Pos            (1U)
1499 #define ADC_CFGR_DMACFG_Msk            (0x1UL << ADC_CFGR_DMACFG_Pos)          /*!< 0x00000002 */
1500 #define ADC_CFGR_DMACFG                ADC_CFGR_DMACFG_Msk                     /*!< ADC DMA transfer configuration */
1501 
1502 #define ADC_CFGR_RES_Pos               (3U)
1503 #define ADC_CFGR_RES_Msk               (0x3UL << ADC_CFGR_RES_Pos)             /*!< 0x00000018 */
1504 #define ADC_CFGR_RES                   ADC_CFGR_RES_Msk                        /*!< ADC data resolution */
1505 #define ADC_CFGR_RES_0                 (0x1UL << ADC_CFGR_RES_Pos)             /*!< 0x00000008 */
1506 #define ADC_CFGR_RES_1                 (0x2UL << ADC_CFGR_RES_Pos)             /*!< 0x00000010 */
1507 
1508 #define ADC_CFGR_EXTSEL_Pos            (5U)
1509 #define ADC_CFGR_EXTSEL_Msk            (0x1FUL << ADC_CFGR_EXTSEL_Pos)         /*!< 0x000003E0 */
1510 #define ADC_CFGR_EXTSEL                ADC_CFGR_EXTSEL_Msk                     /*!< ADC group regular external trigger source */
1511 #define ADC_CFGR_EXTSEL_0              (0x1UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000020 */
1512 #define ADC_CFGR_EXTSEL_1              (0x2UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000040 */
1513 #define ADC_CFGR_EXTSEL_2              (0x4UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000080 */
1514 #define ADC_CFGR_EXTSEL_3              (0x8UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000100 */
1515 #define ADC_CFGR_EXTSEL_4              (0x10UL << ADC_CFGR_EXTSEL_Pos)         /*!< 0x00000200 */
1516 
1517 #define ADC_CFGR_EXTEN_Pos             (10U)
1518 #define ADC_CFGR_EXTEN_Msk             (0x3UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000C00 */
1519 #define ADC_CFGR_EXTEN                 ADC_CFGR_EXTEN_Msk                      /*!< ADC group regular external trigger polarity */
1520 #define ADC_CFGR_EXTEN_0               (0x1UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000400 */
1521 #define ADC_CFGR_EXTEN_1               (0x2UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000800 */
1522 
1523 #define ADC_CFGR_OVRMOD_Pos            (12U)
1524 #define ADC_CFGR_OVRMOD_Msk            (0x1UL << ADC_CFGR_OVRMOD_Pos)          /*!< 0x00001000 */
1525 #define ADC_CFGR_OVRMOD                ADC_CFGR_OVRMOD_Msk                     /*!< ADC group regular overrun configuration */
1526 #define ADC_CFGR_CONT_Pos              (13U)
1527 #define ADC_CFGR_CONT_Msk              (0x1UL << ADC_CFGR_CONT_Pos)            /*!< 0x00002000 */
1528 #define ADC_CFGR_CONT                  ADC_CFGR_CONT_Msk                       /*!< ADC group regular continuous conversion mode */
1529 #define ADC_CFGR_AUTDLY_Pos            (14U)
1530 #define ADC_CFGR_AUTDLY_Msk            (0x1UL << ADC_CFGR_AUTDLY_Pos)          /*!< 0x00004000 */
1531 #define ADC_CFGR_AUTDLY                ADC_CFGR_AUTDLY_Msk                     /*!< ADC low power auto wait */
1532 #define ADC_CFGR_ALIGN_Pos             (15U)
1533 #define ADC_CFGR_ALIGN_Msk             (0x1UL << ADC_CFGR_ALIGN_Pos)           /*!< 0x00008000 */
1534 #define ADC_CFGR_ALIGN                 ADC_CFGR_ALIGN_Msk                      /*!< ADC data alignement */
1535 #define ADC_CFGR_DISCEN_Pos            (16U)
1536 #define ADC_CFGR_DISCEN_Msk            (0x1UL << ADC_CFGR_DISCEN_Pos)          /*!< 0x00010000 */
1537 #define ADC_CFGR_DISCEN                ADC_CFGR_DISCEN_Msk                     /*!< ADC group regular sequencer discontinuous mode */
1538 
1539 #define ADC_CFGR_DISCNUM_Pos           (17U)
1540 #define ADC_CFGR_DISCNUM_Msk           (0x7UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x000E0000 */
1541 #define ADC_CFGR_DISCNUM               ADC_CFGR_DISCNUM_Msk                    /*!< ADC group regular sequencer discontinuous number of ranks */
1542 #define ADC_CFGR_DISCNUM_0             (0x1UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00020000 */
1543 #define ADC_CFGR_DISCNUM_1             (0x2UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00040000 */
1544 #define ADC_CFGR_DISCNUM_2             (0x4UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00080000 */
1545 
1546 #define ADC_CFGR_JDISCEN_Pos           (20U)
1547 #define ADC_CFGR_JDISCEN_Msk           (0x1UL << ADC_CFGR_JDISCEN_Pos)         /*!< 0x00100000 */
1548 #define ADC_CFGR_JDISCEN               ADC_CFGR_JDISCEN_Msk                    /*!< ADC group injected sequencer discontinuous mode */
1549 #define ADC_CFGR_JQM_Pos               (21U)
1550 #define ADC_CFGR_JQM_Msk               (0x1UL << ADC_CFGR_JQM_Pos)             /*!< 0x00200000 */
1551 #define ADC_CFGR_JQM                   ADC_CFGR_JQM_Msk                        /*!< ADC group injected contexts queue mode */
1552 #define ADC_CFGR_AWD1SGL_Pos           (22U)
1553 #define ADC_CFGR_AWD1SGL_Msk           (0x1UL << ADC_CFGR_AWD1SGL_Pos)         /*!< 0x00400000 */
1554 #define ADC_CFGR_AWD1SGL               ADC_CFGR_AWD1SGL_Msk                    /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
1555 #define ADC_CFGR_AWD1EN_Pos            (23U)
1556 #define ADC_CFGR_AWD1EN_Msk            (0x1UL << ADC_CFGR_AWD1EN_Pos)          /*!< 0x00800000 */
1557 #define ADC_CFGR_AWD1EN                ADC_CFGR_AWD1EN_Msk                     /*!< ADC analog watchdog 1 enable on scope ADC group regular */
1558 #define ADC_CFGR_JAWD1EN_Pos           (24U)
1559 #define ADC_CFGR_JAWD1EN_Msk           (0x1UL << ADC_CFGR_JAWD1EN_Pos)         /*!< 0x01000000 */
1560 #define ADC_CFGR_JAWD1EN               ADC_CFGR_JAWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group injected */
1561 #define ADC_CFGR_JAUTO_Pos             (25U)
1562 #define ADC_CFGR_JAUTO_Msk             (0x1UL << ADC_CFGR_JAUTO_Pos)           /*!< 0x02000000 */
1563 #define ADC_CFGR_JAUTO                 ADC_CFGR_JAUTO_Msk                      /*!< ADC group injected automatic trigger mode */
1564 
1565 #define ADC_CFGR_AWD1CH_Pos            (26U)
1566 #define ADC_CFGR_AWD1CH_Msk            (0x1FUL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x7C000000 */
1567 #define ADC_CFGR_AWD1CH                ADC_CFGR_AWD1CH_Msk                     /*!< ADC analog watchdog 1 monitored channel selection */
1568 #define ADC_CFGR_AWD1CH_0              (0x01UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x04000000 */
1569 #define ADC_CFGR_AWD1CH_1              (0x02UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x08000000 */
1570 #define ADC_CFGR_AWD1CH_2              (0x04UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x10000000 */
1571 #define ADC_CFGR_AWD1CH_3              (0x08UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x20000000 */
1572 #define ADC_CFGR_AWD1CH_4              (0x10UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x40000000 */
1573 
1574 #define ADC_CFGR_JQDIS_Pos             (31U)
1575 #define ADC_CFGR_JQDIS_Msk             (0x1UL << ADC_CFGR_JQDIS_Pos)           /*!< 0x80000000 */
1576 #define ADC_CFGR_JQDIS                 ADC_CFGR_JQDIS_Msk                      /*!< ADC group injected contexts queue disable */
1577 
1578 /********************  Bit definition for ADC_CFGR2 register  *****************/
1579 #define ADC_CFGR2_ROVSE_Pos            (0U)
1580 #define ADC_CFGR2_ROVSE_Msk            (0x1UL << ADC_CFGR2_ROVSE_Pos)          /*!< 0x00000001 */
1581 #define ADC_CFGR2_ROVSE                ADC_CFGR2_ROVSE_Msk                     /*!< ADC oversampler enable on scope ADC group regular */
1582 #define ADC_CFGR2_JOVSE_Pos            (1U)
1583 #define ADC_CFGR2_JOVSE_Msk            (0x1UL << ADC_CFGR2_JOVSE_Pos)          /*!< 0x00000002 */
1584 #define ADC_CFGR2_JOVSE                ADC_CFGR2_JOVSE_Msk                     /*!< ADC oversampler enable on scope ADC group injected */
1585 
1586 #define ADC_CFGR2_OVSR_Pos             (2U)
1587 #define ADC_CFGR2_OVSR_Msk             (0x7UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x0000001C */
1588 #define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */
1589 #define ADC_CFGR2_OVSR_0               (0x1UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000004 */
1590 #define ADC_CFGR2_OVSR_1               (0x2UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000008 */
1591 #define ADC_CFGR2_OVSR_2               (0x4UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000010 */
1592 
1593 #define ADC_CFGR2_OVSS_Pos             (5U)
1594 #define ADC_CFGR2_OVSS_Msk             (0xFUL << ADC_CFGR2_OVSS_Pos)           /*!< 0x000001E0 */
1595 #define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
1596 #define ADC_CFGR2_OVSS_0               (0x1UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000020 */
1597 #define ADC_CFGR2_OVSS_1               (0x2UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000040 */
1598 #define ADC_CFGR2_OVSS_2               (0x4UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000080 */
1599 #define ADC_CFGR2_OVSS_3               (0x8UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000100 */
1600 
1601 #define ADC_CFGR2_TROVS_Pos            (9U)
1602 #define ADC_CFGR2_TROVS_Msk            (0x1UL << ADC_CFGR2_TROVS_Pos)          /*!< 0x00000200 */
1603 #define ADC_CFGR2_TROVS                ADC_CFGR2_TROVS_Msk                     /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
1604 #define ADC_CFGR2_ROVSM_Pos            (10U)
1605 #define ADC_CFGR2_ROVSM_Msk            (0x1UL << ADC_CFGR2_ROVSM_Pos)          /*!< 0x00000400 */
1606 #define ADC_CFGR2_ROVSM                ADC_CFGR2_ROVSM_Msk                     /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
1607 
1608 #define ADC_CFGR2_GCOMP_Pos            (16U)
1609 #define ADC_CFGR2_GCOMP_Msk            (0x1UL << ADC_CFGR2_GCOMP_Pos)          /*!< 0x00010000 */
1610 #define ADC_CFGR2_GCOMP                ADC_CFGR2_GCOMP_Msk                     /*!< ADC Gain Compensation mode */
1611 
1612 #define ADC_CFGR2_SWTRIG_Pos           (25U)
1613 #define ADC_CFGR2_SWTRIG_Msk           (0x1UL << ADC_CFGR2_SWTRIG_Pos)         /*!< 0x02000000 */
1614 #define ADC_CFGR2_SWTRIG               ADC_CFGR2_SWTRIG_Msk                    /*!< ADC Software Trigger Bit for Sample time control trigger mode */
1615 #define ADC_CFGR2_BULB_Pos             (26U)
1616 #define ADC_CFGR2_BULB_Msk             (0x1UL << ADC_CFGR2_BULB_Pos)           /*!< 0x04000000 */
1617 #define ADC_CFGR2_BULB                 ADC_CFGR2_BULB_Msk                      /*!< ADC Bulb sampling mode */
1618 #define ADC_CFGR2_SMPTRIG_Pos          (27U)
1619 #define ADC_CFGR2_SMPTRIG_Msk          (0x1UL << ADC_CFGR2_SMPTRIG_Pos)        /*!< 0x08000000 */
1620 #define ADC_CFGR2_SMPTRIG              ADC_CFGR2_SMPTRIG_Msk                   /*!< ADC Sample Time Control Trigger mode */
1621 
1622 /********************  Bit definition for ADC_SMPR1 register  *****************/
1623 #define ADC_SMPR1_SMP0_Pos             (0U)
1624 #define ADC_SMPR1_SMP0_Msk             (0x7UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000007 */
1625 #define ADC_SMPR1_SMP0                 ADC_SMPR1_SMP0_Msk                      /*!< ADC channel 0 sampling time selection  */
1626 #define ADC_SMPR1_SMP0_0               (0x1UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000001 */
1627 #define ADC_SMPR1_SMP0_1               (0x2UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000002 */
1628 #define ADC_SMPR1_SMP0_2               (0x4UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000004 */
1629 
1630 #define ADC_SMPR1_SMP1_Pos             (3U)
1631 #define ADC_SMPR1_SMP1_Msk             (0x7UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000038 */
1632 #define ADC_SMPR1_SMP1                 ADC_SMPR1_SMP1_Msk                      /*!< ADC channel 1 sampling time selection  */
1633 #define ADC_SMPR1_SMP1_0               (0x1UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000008 */
1634 #define ADC_SMPR1_SMP1_1               (0x2UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000010 */
1635 #define ADC_SMPR1_SMP1_2               (0x4UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000020 */
1636 
1637 #define ADC_SMPR1_SMP2_Pos             (6U)
1638 #define ADC_SMPR1_SMP2_Msk             (0x7UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x000001C0 */
1639 #define ADC_SMPR1_SMP2                 ADC_SMPR1_SMP2_Msk                      /*!< ADC channel 2 sampling time selection  */
1640 #define ADC_SMPR1_SMP2_0               (0x1UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000040 */
1641 #define ADC_SMPR1_SMP2_1               (0x2UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000080 */
1642 #define ADC_SMPR1_SMP2_2               (0x4UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000100 */
1643 
1644 #define ADC_SMPR1_SMP3_Pos             (9U)
1645 #define ADC_SMPR1_SMP3_Msk             (0x7UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000E00 */
1646 #define ADC_SMPR1_SMP3                 ADC_SMPR1_SMP3_Msk                      /*!< ADC channel 3 sampling time selection  */
1647 #define ADC_SMPR1_SMP3_0               (0x1UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000200 */
1648 #define ADC_SMPR1_SMP3_1               (0x2UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000400 */
1649 #define ADC_SMPR1_SMP3_2               (0x4UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000800 */
1650 
1651 #define ADC_SMPR1_SMP4_Pos             (12U)
1652 #define ADC_SMPR1_SMP4_Msk             (0x7UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00007000 */
1653 #define ADC_SMPR1_SMP4                 ADC_SMPR1_SMP4_Msk                      /*!< ADC channel 4 sampling time selection  */
1654 #define ADC_SMPR1_SMP4_0               (0x1UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00001000 */
1655 #define ADC_SMPR1_SMP4_1               (0x2UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00002000 */
1656 #define ADC_SMPR1_SMP4_2               (0x4UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00004000 */
1657 
1658 #define ADC_SMPR1_SMP5_Pos             (15U)
1659 #define ADC_SMPR1_SMP5_Msk             (0x7UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00038000 */
1660 #define ADC_SMPR1_SMP5                 ADC_SMPR1_SMP5_Msk                      /*!< ADC channel 5 sampling time selection  */
1661 #define ADC_SMPR1_SMP5_0               (0x1UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00008000 */
1662 #define ADC_SMPR1_SMP5_1               (0x2UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00010000 */
1663 #define ADC_SMPR1_SMP5_2               (0x4UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00020000 */
1664 
1665 #define ADC_SMPR1_SMP6_Pos             (18U)
1666 #define ADC_SMPR1_SMP6_Msk             (0x7UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x001C0000 */
1667 #define ADC_SMPR1_SMP6                 ADC_SMPR1_SMP6_Msk                      /*!< ADC channel 6 sampling time selection  */
1668 #define ADC_SMPR1_SMP6_0               (0x1UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00040000 */
1669 #define ADC_SMPR1_SMP6_1               (0x2UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00080000 */
1670 #define ADC_SMPR1_SMP6_2               (0x4UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00100000 */
1671 
1672 #define ADC_SMPR1_SMP7_Pos             (21U)
1673 #define ADC_SMPR1_SMP7_Msk             (0x7UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00E00000 */
1674 #define ADC_SMPR1_SMP7                 ADC_SMPR1_SMP7_Msk                      /*!< ADC channel 7 sampling time selection  */
1675 #define ADC_SMPR1_SMP7_0               (0x1UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00200000 */
1676 #define ADC_SMPR1_SMP7_1               (0x2UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00400000 */
1677 #define ADC_SMPR1_SMP7_2               (0x4UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00800000 */
1678 
1679 #define ADC_SMPR1_SMP8_Pos             (24U)
1680 #define ADC_SMPR1_SMP8_Msk             (0x7UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x07000000 */
1681 #define ADC_SMPR1_SMP8                 ADC_SMPR1_SMP8_Msk                      /*!< ADC channel 8 sampling time selection  */
1682 #define ADC_SMPR1_SMP8_0               (0x1UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x01000000 */
1683 #define ADC_SMPR1_SMP8_1               (0x2UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x02000000 */
1684 #define ADC_SMPR1_SMP8_2               (0x4UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x04000000 */
1685 
1686 #define ADC_SMPR1_SMP9_Pos             (27U)
1687 #define ADC_SMPR1_SMP9_Msk             (0x7UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x38000000 */
1688 #define ADC_SMPR1_SMP9                 ADC_SMPR1_SMP9_Msk                      /*!< ADC channel 9 sampling time selection  */
1689 #define ADC_SMPR1_SMP9_0               (0x1UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x08000000 */
1690 #define ADC_SMPR1_SMP9_1               (0x2UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x10000000 */
1691 #define ADC_SMPR1_SMP9_2               (0x4UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x20000000 */
1692 
1693 #define ADC_SMPR1_SMPPLUS_Pos          (31U)
1694 #define ADC_SMPR1_SMPPLUS_Msk          (0x1UL << ADC_SMPR1_SMPPLUS_Pos)        /*!< 0x80000000 */
1695 #define ADC_SMPR1_SMPPLUS              ADC_SMPR1_SMPPLUS_Msk                   /*!< ADC channels sampling time additional setting */
1696 
1697 /********************  Bit definition for ADC_SMPR2 register  *****************/
1698 #define ADC_SMPR2_SMP10_Pos            (0U)
1699 #define ADC_SMPR2_SMP10_Msk            (0x7UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000007 */
1700 #define ADC_SMPR2_SMP10                ADC_SMPR2_SMP10_Msk                     /*!< ADC channel 10 sampling time selection  */
1701 #define ADC_SMPR2_SMP10_0              (0x1UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000001 */
1702 #define ADC_SMPR2_SMP10_1              (0x2UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000002 */
1703 #define ADC_SMPR2_SMP10_2              (0x4UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000004 */
1704 
1705 #define ADC_SMPR2_SMP11_Pos            (3U)
1706 #define ADC_SMPR2_SMP11_Msk            (0x7UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000038 */
1707 #define ADC_SMPR2_SMP11                ADC_SMPR2_SMP11_Msk                     /*!< ADC channel 11 sampling time selection  */
1708 #define ADC_SMPR2_SMP11_0              (0x1UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000008 */
1709 #define ADC_SMPR2_SMP11_1              (0x2UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000010 */
1710 #define ADC_SMPR2_SMP11_2              (0x4UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000020 */
1711 
1712 #define ADC_SMPR2_SMP12_Pos            (6U)
1713 #define ADC_SMPR2_SMP12_Msk            (0x7UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x000001C0 */
1714 #define ADC_SMPR2_SMP12                ADC_SMPR2_SMP12_Msk                     /*!< ADC channel 12 sampling time selection  */
1715 #define ADC_SMPR2_SMP12_0              (0x1UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000040 */
1716 #define ADC_SMPR2_SMP12_1              (0x2UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000080 */
1717 #define ADC_SMPR2_SMP12_2              (0x4UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000100 */
1718 
1719 #define ADC_SMPR2_SMP13_Pos            (9U)
1720 #define ADC_SMPR2_SMP13_Msk            (0x7UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000E00 */
1721 #define ADC_SMPR2_SMP13                ADC_SMPR2_SMP13_Msk                     /*!< ADC channel 13 sampling time selection  */
1722 #define ADC_SMPR2_SMP13_0              (0x1UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000200 */
1723 #define ADC_SMPR2_SMP13_1              (0x2UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000400 */
1724 #define ADC_SMPR2_SMP13_2              (0x4UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000800 */
1725 
1726 #define ADC_SMPR2_SMP14_Pos            (12U)
1727 #define ADC_SMPR2_SMP14_Msk            (0x7UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00007000 */
1728 #define ADC_SMPR2_SMP14                ADC_SMPR2_SMP14_Msk                     /*!< ADC channel 14 sampling time selection  */
1729 #define ADC_SMPR2_SMP14_0              (0x1UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00001000 */
1730 #define ADC_SMPR2_SMP14_1              (0x2UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00002000 */
1731 #define ADC_SMPR2_SMP14_2              (0x4UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00004000 */
1732 
1733 #define ADC_SMPR2_SMP15_Pos            (15U)
1734 #define ADC_SMPR2_SMP15_Msk            (0x7UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00038000 */
1735 #define ADC_SMPR2_SMP15                ADC_SMPR2_SMP15_Msk                     /*!< ADC channel 15 sampling time selection  */
1736 #define ADC_SMPR2_SMP15_0              (0x1UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00008000 */
1737 #define ADC_SMPR2_SMP15_1              (0x2UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00010000 */
1738 #define ADC_SMPR2_SMP15_2              (0x4UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00020000 */
1739 
1740 #define ADC_SMPR2_SMP16_Pos            (18U)
1741 #define ADC_SMPR2_SMP16_Msk            (0x7UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x001C0000 */
1742 #define ADC_SMPR2_SMP16                ADC_SMPR2_SMP16_Msk                     /*!< ADC channel 16 sampling time selection  */
1743 #define ADC_SMPR2_SMP16_0              (0x1UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00040000 */
1744 #define ADC_SMPR2_SMP16_1              (0x2UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00080000 */
1745 #define ADC_SMPR2_SMP16_2              (0x4UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00100000 */
1746 
1747 #define ADC_SMPR2_SMP17_Pos            (21U)
1748 #define ADC_SMPR2_SMP17_Msk            (0x7UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00E00000 */
1749 #define ADC_SMPR2_SMP17                ADC_SMPR2_SMP17_Msk                     /*!< ADC channel 17 sampling time selection  */
1750 #define ADC_SMPR2_SMP17_0              (0x1UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00200000 */
1751 #define ADC_SMPR2_SMP17_1              (0x2UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00400000 */
1752 #define ADC_SMPR2_SMP17_2              (0x4UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00800000 */
1753 
1754 #define ADC_SMPR2_SMP18_Pos            (24U)
1755 #define ADC_SMPR2_SMP18_Msk            (0x7UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x07000000 */
1756 #define ADC_SMPR2_SMP18                ADC_SMPR2_SMP18_Msk                     /*!< ADC channel 18 sampling time selection  */
1757 #define ADC_SMPR2_SMP18_0              (0x1UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x01000000 */
1758 #define ADC_SMPR2_SMP18_1              (0x2UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x02000000 */
1759 #define ADC_SMPR2_SMP18_2              (0x4UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x04000000 */
1760 
1761 /********************  Bit definition for ADC_TR1 register  *******************/
1762 #define ADC_TR1_LT1_Pos                (0U)
1763 #define ADC_TR1_LT1_Msk                (0xFFFUL << ADC_TR1_LT1_Pos)            /*!< 0x00000FFF */
1764 #define ADC_TR1_LT1                    ADC_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */
1765 
1766 #define ADC_TR1_AWDFILT_Pos            (12U)
1767 #define ADC_TR1_AWDFILT_Msk            (0x7UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00007000 */
1768 #define ADC_TR1_AWDFILT                ADC_TR1_AWDFILT_Msk                     /*!< ADC analog watchdog filtering parameter  */
1769 #define ADC_TR1_AWDFILT_0              (0x1UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00001000 */
1770 #define ADC_TR1_AWDFILT_1              (0x2UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00002000 */
1771 #define ADC_TR1_AWDFILT_2              (0x4UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00004000 */
1772 
1773 #define ADC_TR1_HT1_Pos                (16U)
1774 #define ADC_TR1_HT1_Msk                (0xFFFUL << ADC_TR1_HT1_Pos)            /*!< 0x0FFF0000 */
1775 #define ADC_TR1_HT1                    ADC_TR1_HT1_Msk                         /*!< ADC analog watchdog 1 threshold high */
1776 
1777 /********************  Bit definition for ADC_TR2 register  *******************/
1778 #define ADC_TR2_LT2_Pos                (0U)
1779 #define ADC_TR2_LT2_Msk                (0xFFUL << ADC_TR2_LT2_Pos)             /*!< 0x000000FF */
1780 #define ADC_TR2_LT2                    ADC_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */
1781 
1782 #define ADC_TR2_HT2_Pos                (16U)
1783 #define ADC_TR2_HT2_Msk                (0xFFUL << ADC_TR2_HT2_Pos)             /*!< 0x00FF0000 */
1784 #define ADC_TR2_HT2                    ADC_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */
1785 
1786 /********************  Bit definition for ADC_TR3 register  *******************/
1787 #define ADC_TR3_LT3_Pos                (0U)
1788 #define ADC_TR3_LT3_Msk                (0xFFUL << ADC_TR3_LT3_Pos)             /*!< 0x000000FF */
1789 #define ADC_TR3_LT3                    ADC_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */
1790 
1791 #define ADC_TR3_HT3_Pos                (16U)
1792 #define ADC_TR3_HT3_Msk                (0xFFUL << ADC_TR3_HT3_Pos)             /*!< 0x00FF0000 */
1793 #define ADC_TR3_HT3                    ADC_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */
1794 
1795 /********************  Bit definition for ADC_SQR1 register  ******************/
1796 #define ADC_SQR1_L_Pos                 (0U)
1797 #define ADC_SQR1_L_Msk                 (0xFUL << ADC_SQR1_L_Pos)               /*!< 0x0000000F */
1798 #define ADC_SQR1_L                     ADC_SQR1_L_Msk                          /*!< ADC group regular sequencer scan length */
1799 #define ADC_SQR1_L_0                   (0x1UL << ADC_SQR1_L_Pos)               /*!< 0x00000001 */
1800 #define ADC_SQR1_L_1                   (0x2UL << ADC_SQR1_L_Pos)               /*!< 0x00000002 */
1801 #define ADC_SQR1_L_2                   (0x4UL << ADC_SQR1_L_Pos)               /*!< 0x00000004 */
1802 #define ADC_SQR1_L_3                   (0x8UL << ADC_SQR1_L_Pos)               /*!< 0x00000008 */
1803 
1804 #define ADC_SQR1_SQ1_Pos               (6U)
1805 #define ADC_SQR1_SQ1_Msk               (0x1FUL << ADC_SQR1_SQ1_Pos)            /*!< 0x000007C0 */
1806 #define ADC_SQR1_SQ1                   ADC_SQR1_SQ1_Msk                        /*!< ADC group regular sequencer rank 1 */
1807 #define ADC_SQR1_SQ1_0                 (0x01UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000040 */
1808 #define ADC_SQR1_SQ1_1                 (0x02UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000080 */
1809 #define ADC_SQR1_SQ1_2                 (0x04UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000100 */
1810 #define ADC_SQR1_SQ1_3                 (0x08UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000200 */
1811 #define ADC_SQR1_SQ1_4                 (0x10UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000400 */
1812 
1813 #define ADC_SQR1_SQ2_Pos               (12U)
1814 #define ADC_SQR1_SQ2_Msk               (0x1FUL << ADC_SQR1_SQ2_Pos)            /*!< 0x0001F000 */
1815 #define ADC_SQR1_SQ2                   ADC_SQR1_SQ2_Msk                        /*!< ADC group regular sequencer rank 2 */
1816 #define ADC_SQR1_SQ2_0                 (0x01UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00001000 */
1817 #define ADC_SQR1_SQ2_1                 (0x02UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00002000 */
1818 #define ADC_SQR1_SQ2_2                 (0x04UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00004000 */
1819 #define ADC_SQR1_SQ2_3                 (0x08UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00008000 */
1820 #define ADC_SQR1_SQ2_4                 (0x10UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00010000 */
1821 
1822 #define ADC_SQR1_SQ3_Pos               (18U)
1823 #define ADC_SQR1_SQ3_Msk               (0x1FUL << ADC_SQR1_SQ3_Pos)            /*!< 0x007C0000 */
1824 #define ADC_SQR1_SQ3                   ADC_SQR1_SQ3_Msk                        /*!< ADC group regular sequencer rank 3 */
1825 #define ADC_SQR1_SQ3_0                 (0x01UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00040000 */
1826 #define ADC_SQR1_SQ3_1                 (0x02UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00080000 */
1827 #define ADC_SQR1_SQ3_2                 (0x04UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00100000 */
1828 #define ADC_SQR1_SQ3_3                 (0x08UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00200000 */
1829 #define ADC_SQR1_SQ3_4                 (0x10UL<< ADC_SQR1_SQ3_Pos)             /*!< 0x00400000 */
1830 
1831 #define ADC_SQR1_SQ4_Pos               (24U)
1832 #define ADC_SQR1_SQ4_Msk               (0x1FUL << ADC_SQR1_SQ4_Pos)            /*!< 0x1F000000 */
1833 #define ADC_SQR1_SQ4                   ADC_SQR1_SQ4_Msk                        /*!< ADC group regular sequencer rank 4 */
1834 #define ADC_SQR1_SQ4_0                 (0x01UL << ADC_SQR1_SQ4_Pos)            /*!< 0x01000000 */
1835 #define ADC_SQR1_SQ4_1                 (0x02UL << ADC_SQR1_SQ4_Pos)            /*!< 0x02000000 */
1836 #define ADC_SQR1_SQ4_2                 (0x04UL << ADC_SQR1_SQ4_Pos)            /*!< 0x04000000 */
1837 #define ADC_SQR1_SQ4_3                 (0x08UL << ADC_SQR1_SQ4_Pos)            /*!< 0x08000000 */
1838 #define ADC_SQR1_SQ4_4                 (0x10UL << ADC_SQR1_SQ4_Pos)            /*!< 0x10000000 */
1839 
1840 /********************  Bit definition for ADC_SQR2 register  ******************/
1841 #define ADC_SQR2_SQ5_Pos               (0U)
1842 #define ADC_SQR2_SQ5_Msk               (0x1FUL << ADC_SQR2_SQ5_Pos)            /*!< 0x0000001F */
1843 #define ADC_SQR2_SQ5                   ADC_SQR2_SQ5_Msk                        /*!< ADC group regular sequencer rank 5 */
1844 #define ADC_SQR2_SQ5_0                 (0x01UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000001 */
1845 #define ADC_SQR2_SQ5_1                 (0x02UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000002 */
1846 #define ADC_SQR2_SQ5_2                 (0x04UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000004 */
1847 #define ADC_SQR2_SQ5_3                 (0x08UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000008 */
1848 #define ADC_SQR2_SQ5_4                 (0x10UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000010 */
1849 
1850 #define ADC_SQR2_SQ6_Pos               (6U)
1851 #define ADC_SQR2_SQ6_Msk               (0x1FUL << ADC_SQR2_SQ6_Pos)            /*!< 0x000007C0 */
1852 #define ADC_SQR2_SQ6                   ADC_SQR2_SQ6_Msk                        /*!< ADC group regular sequencer rank 6 */
1853 #define ADC_SQR2_SQ6_0                 (0x01UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000040 */
1854 #define ADC_SQR2_SQ6_1                 (0x02UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000080 */
1855 #define ADC_SQR2_SQ6_2                 (0x04UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000100 */
1856 #define ADC_SQR2_SQ6_3                 (0x08UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000200 */
1857 #define ADC_SQR2_SQ6_4                 (0x10UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000400 */
1858 
1859 #define ADC_SQR2_SQ7_Pos               (12U)
1860 #define ADC_SQR2_SQ7_Msk               (0x1FUL << ADC_SQR2_SQ7_Pos)            /*!< 0x0001F000 */
1861 #define ADC_SQR2_SQ7                   ADC_SQR2_SQ7_Msk                        /*!< ADC group regular sequencer rank 7 */
1862 #define ADC_SQR2_SQ7_0                 (0x01UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00001000 */
1863 #define ADC_SQR2_SQ7_1                 (0x02UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00002000 */
1864 #define ADC_SQR2_SQ7_2                 (0x04UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00004000 */
1865 #define ADC_SQR2_SQ7_3                 (0x08UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00008000 */
1866 #define ADC_SQR2_SQ7_4                 (0x10UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00010000 */
1867 
1868 #define ADC_SQR2_SQ8_Pos               (18U)
1869 #define ADC_SQR2_SQ8_Msk               (0x1FUL << ADC_SQR2_SQ8_Pos)            /*!< 0x007C0000 */
1870 #define ADC_SQR2_SQ8                   ADC_SQR2_SQ8_Msk                        /*!< ADC group regular sequencer rank 8 */
1871 #define ADC_SQR2_SQ8_0                 (0x01UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00040000 */
1872 #define ADC_SQR2_SQ8_1                 (0x02UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00080000 */
1873 #define ADC_SQR2_SQ8_2                 (0x04UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00100000 */
1874 #define ADC_SQR2_SQ8_3                 (0x08UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00200000 */
1875 #define ADC_SQR2_SQ8_4                 (0x10UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00400000 */
1876 
1877 #define ADC_SQR2_SQ9_Pos               (24U)
1878 #define ADC_SQR2_SQ9_Msk               (0x1FUL << ADC_SQR2_SQ9_Pos)            /*!< 0x1F000000 */
1879 #define ADC_SQR2_SQ9                   ADC_SQR2_SQ9_Msk                        /*!< ADC group regular sequencer rank 9 */
1880 #define ADC_SQR2_SQ9_0                 (0x01UL << ADC_SQR2_SQ9_Pos)            /*!< 0x01000000 */
1881 #define ADC_SQR2_SQ9_1                 (0x02UL << ADC_SQR2_SQ9_Pos)            /*!< 0x02000000 */
1882 #define ADC_SQR2_SQ9_2                 (0x04UL << ADC_SQR2_SQ9_Pos)            /*!< 0x04000000 */
1883 #define ADC_SQR2_SQ9_3                 (0x08UL << ADC_SQR2_SQ9_Pos)            /*!< 0x08000000 */
1884 #define ADC_SQR2_SQ9_4                 (0x10UL << ADC_SQR2_SQ9_Pos)            /*!< 0x10000000 */
1885 
1886 /********************  Bit definition for ADC_SQR3 register  ******************/
1887 #define ADC_SQR3_SQ10_Pos              (0U)
1888 #define ADC_SQR3_SQ10_Msk              (0x1FUL << ADC_SQR3_SQ10_Pos)           /*!< 0x0000001F */
1889 #define ADC_SQR3_SQ10                  ADC_SQR3_SQ10_Msk                       /*!< ADC group regular sequencer rank 10 */
1890 #define ADC_SQR3_SQ10_0                (0x01UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000001 */
1891 #define ADC_SQR3_SQ10_1                (0x02UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000002 */
1892 #define ADC_SQR3_SQ10_2                (0x04UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000004 */
1893 #define ADC_SQR3_SQ10_3                (0x08UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000008 */
1894 #define ADC_SQR3_SQ10_4                (0x10UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000010 */
1895 
1896 #define ADC_SQR3_SQ11_Pos              (6U)
1897 #define ADC_SQR3_SQ11_Msk              (0x1FUL << ADC_SQR3_SQ11_Pos)           /*!< 0x000007C0 */
1898 #define ADC_SQR3_SQ11                  ADC_SQR3_SQ11_Msk                       /*!< ADC group regular sequencer rank 11 */
1899 #define ADC_SQR3_SQ11_0                (0x01UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000040 */
1900 #define ADC_SQR3_SQ11_1                (0x02UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000080 */
1901 #define ADC_SQR3_SQ11_2                (0x04UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000100 */
1902 #define ADC_SQR3_SQ11_3                (0x08UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000200 */
1903 #define ADC_SQR3_SQ11_4                (0x10UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000400 */
1904 
1905 #define ADC_SQR3_SQ12_Pos              (12U)
1906 #define ADC_SQR3_SQ12_Msk              (0x1FUL << ADC_SQR3_SQ12_Pos)           /*!< 0x0001F000 */
1907 #define ADC_SQR3_SQ12                  ADC_SQR3_SQ12_Msk                       /*!< ADC group regular sequencer rank 12 */
1908 #define ADC_SQR3_SQ12_0                (0x01UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00001000 */
1909 #define ADC_SQR3_SQ12_1                (0x02UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00002000 */
1910 #define ADC_SQR3_SQ12_2                (0x04UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00004000 */
1911 #define ADC_SQR3_SQ12_3                (0x08UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00008000 */
1912 #define ADC_SQR3_SQ12_4                (0x10UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00010000 */
1913 
1914 #define ADC_SQR3_SQ13_Pos              (18U)
1915 #define ADC_SQR3_SQ13_Msk              (0x1FUL << ADC_SQR3_SQ13_Pos)           /*!< 0x007C0000 */
1916 #define ADC_SQR3_SQ13                  ADC_SQR3_SQ13_Msk                       /*!< ADC group regular sequencer rank 13 */
1917 #define ADC_SQR3_SQ13_0                (0x01UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00040000 */
1918 #define ADC_SQR3_SQ13_1                (0x02UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00080000 */
1919 #define ADC_SQR3_SQ13_2                (0x04UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00100000 */
1920 #define ADC_SQR3_SQ13_3                (0x08UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00200000 */
1921 #define ADC_SQR3_SQ13_4                (0x10UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00400000 */
1922 
1923 #define ADC_SQR3_SQ14_Pos              (24U)
1924 #define ADC_SQR3_SQ14_Msk              (0x1FUL << ADC_SQR3_SQ14_Pos)           /*!< 0x1F000000 */
1925 #define ADC_SQR3_SQ14                  ADC_SQR3_SQ14_Msk                       /*!< ADC group regular sequencer rank 14 */
1926 #define ADC_SQR3_SQ14_0                (0x01UL << ADC_SQR3_SQ14_Pos)           /*!< 0x01000000 */
1927 #define ADC_SQR3_SQ14_1                (0x02UL << ADC_SQR3_SQ14_Pos)           /*!< 0x02000000 */
1928 #define ADC_SQR3_SQ14_2                (0x04UL << ADC_SQR3_SQ14_Pos)           /*!< 0x04000000 */
1929 #define ADC_SQR3_SQ14_3                (0x08UL << ADC_SQR3_SQ14_Pos)           /*!< 0x08000000 */
1930 #define ADC_SQR3_SQ14_4                (0x10UL << ADC_SQR3_SQ14_Pos)           /*!< 0x10000000 */
1931 
1932 /********************  Bit definition for ADC_SQR4 register  ******************/
1933 #define ADC_SQR4_SQ15_Pos              (0U)
1934 #define ADC_SQR4_SQ15_Msk              (0x1FUL << ADC_SQR4_SQ15_Pos)           /*!< 0x0000001F */
1935 #define ADC_SQR4_SQ15                  ADC_SQR4_SQ15_Msk                       /*!< ADC group regular sequencer rank 15 */
1936 #define ADC_SQR4_SQ15_0                (0x01UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000001 */
1937 #define ADC_SQR4_SQ15_1                (0x02UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000002 */
1938 #define ADC_SQR4_SQ15_2                (0x04UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000004 */
1939 #define ADC_SQR4_SQ15_3                (0x08UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000008 */
1940 #define ADC_SQR4_SQ15_4                (0x10UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000010 */
1941 
1942 #define ADC_SQR4_SQ16_Pos              (6U)
1943 #define ADC_SQR4_SQ16_Msk              (0x1FUL << ADC_SQR4_SQ16_Pos)           /*!< 0x000007C0 */
1944 #define ADC_SQR4_SQ16                  ADC_SQR4_SQ16_Msk                       /*!< ADC group regular sequencer rank 16 */
1945 #define ADC_SQR4_SQ16_0                (0x01UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000040 */
1946 #define ADC_SQR4_SQ16_1                (0x02UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000080 */
1947 #define ADC_SQR4_SQ16_2                (0x04UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000100 */
1948 #define ADC_SQR4_SQ16_3                (0x08UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000200 */
1949 #define ADC_SQR4_SQ16_4                (0x10UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000400 */
1950 
1951 /********************  Bit definition for ADC_DR register  ********************/
1952 #define ADC_DR_RDATA_Pos               (0U)
1953 #define ADC_DR_RDATA_Msk               (0xFFFFUL << ADC_DR_RDATA_Pos)          /*!< 0x0000FFFF */
1954 #define ADC_DR_RDATA                   ADC_DR_RDATA_Msk                        /*!< ADC group regular conversion data */
1955 
1956 /********************  Bit definition for ADC_JSQR register  ******************/
1957 #define ADC_JSQR_JL_Pos                (0U)
1958 #define ADC_JSQR_JL_Msk                (0x3UL << ADC_JSQR_JL_Pos)              /*!< 0x00000003 */
1959 #define ADC_JSQR_JL                    ADC_JSQR_JL_Msk                         /*!< ADC group injected sequencer scan length */
1960 #define ADC_JSQR_JL_0                  (0x1UL << ADC_JSQR_JL_Pos)              /*!< 0x00000001 */
1961 #define ADC_JSQR_JL_1                  (0x2UL << ADC_JSQR_JL_Pos)              /*!< 0x00000002 */
1962 
1963 #define ADC_JSQR_JEXTSEL_Pos           (2U)
1964 #define ADC_JSQR_JEXTSEL_Msk           (0x1FUL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x0000007C */
1965 #define ADC_JSQR_JEXTSEL               ADC_JSQR_JEXTSEL_Msk                    /*!< ADC group injected external trigger source */
1966 #define ADC_JSQR_JEXTSEL_0             (0x1UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000004 */
1967 #define ADC_JSQR_JEXTSEL_1             (0x2UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000008 */
1968 #define ADC_JSQR_JEXTSEL_2             (0x4UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000010 */
1969 #define ADC_JSQR_JEXTSEL_3             (0x8UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000020 */
1970 #define ADC_JSQR_JEXTSEL_4             (0x10UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000040 */
1971 
1972 #define ADC_JSQR_JEXTEN_Pos            (7U)
1973 #define ADC_JSQR_JEXTEN_Msk            (0x3UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000180 */
1974 #define ADC_JSQR_JEXTEN                ADC_JSQR_JEXTEN_Msk                     /*!< ADC group injected external trigger polarity */
1975 #define ADC_JSQR_JEXTEN_0              (0x1UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000080 */
1976 #define ADC_JSQR_JEXTEN_1              (0x2UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000100 */
1977 
1978 #define ADC_JSQR_JSQ1_Pos              (9U)
1979 #define ADC_JSQR_JSQ1_Msk              (0x1FUL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00003E00 */
1980 #define ADC_JSQR_JSQ1                  ADC_JSQR_JSQ1_Msk                       /*!< ADC group injected sequencer rank 1 */
1981 #define ADC_JSQR_JSQ1_0                (0x01UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000200 */
1982 #define ADC_JSQR_JSQ1_1                (0x02UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000400 */
1983 #define ADC_JSQR_JSQ1_2                (0x04UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000800 */
1984 #define ADC_JSQR_JSQ1_3                (0x08UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00001000 */
1985 #define ADC_JSQR_JSQ1_4                (0x10UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00002000 */
1986 
1987 #define ADC_JSQR_JSQ2_Pos              (15U)
1988 #define ADC_JSQR_JSQ2_Msk              (0x1FUL << ADC_JSQR_JSQ2_Pos)           /*!< 0x0007C000 */
1989 #define ADC_JSQR_JSQ2                  ADC_JSQR_JSQ2_Msk                       /*!< ADC group injected sequencer rank 2 */
1990 #define ADC_JSQR_JSQ2_0                (0x01UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00004000 */
1991 #define ADC_JSQR_JSQ2_1                (0x02UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00008000 */
1992 #define ADC_JSQR_JSQ2_2                (0x04UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00010000 */
1993 #define ADC_JSQR_JSQ2_3                (0x08UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00020000 */
1994 #define ADC_JSQR_JSQ2_4                (0x10UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00040000 */
1995 
1996 #define ADC_JSQR_JSQ3_Pos              (21U)
1997 #define ADC_JSQR_JSQ3_Msk              (0x1FUL << ADC_JSQR_JSQ3_Pos)           /*!< 0x03E00000 */
1998 #define ADC_JSQR_JSQ3                  ADC_JSQR_JSQ3_Msk                       /*!< ADC group injected sequencer rank 3 */
1999 #define ADC_JSQR_JSQ3_0                (0x01UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00200000 */
2000 #define ADC_JSQR_JSQ3_1                (0x02UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00400000 */
2001 #define ADC_JSQR_JSQ3_2                (0x04UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00800000 */
2002 #define ADC_JSQR_JSQ3_3                (0x08UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x01000000 */
2003 #define ADC_JSQR_JSQ3_4                (0x10UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x02000000 */
2004 
2005 #define ADC_JSQR_JSQ4_Pos              (27U)
2006 #define ADC_JSQR_JSQ4_Msk              (0x1FUL << ADC_JSQR_JSQ4_Pos)           /*!< 0xF8000000 */
2007 #define ADC_JSQR_JSQ4                  ADC_JSQR_JSQ4_Msk                       /*!< ADC group injected sequencer rank 4 */
2008 #define ADC_JSQR_JSQ4_0                (0x01UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x08000000 */
2009 #define ADC_JSQR_JSQ4_1                (0x02UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x10000000 */
2010 #define ADC_JSQR_JSQ4_2                (0x04UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x20000000 */
2011 #define ADC_JSQR_JSQ4_3                (0x08UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x40000000 */
2012 #define ADC_JSQR_JSQ4_4                (0x10UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x80000000 */
2013 
2014 /********************  Bit definition for ADC_OFR1 register  ******************/
2015 #define ADC_OFR1_OFFSET1_Pos           (0U)
2016 #define ADC_OFR1_OFFSET1_Msk           (0xFFFUL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000FFF */
2017 #define ADC_OFR1_OFFSET1               ADC_OFR1_OFFSET1_Msk                    /*!< ADC offset number 1 offset level */
2018 
2019 #define ADC_OFR1_OFFSETPOS_Pos         (24U)
2020 #define ADC_OFR1_OFFSETPOS_Msk         (0x1UL << ADC_OFR1_OFFSETPOS_Pos)       /*!< 0x01000000 */
2021 #define ADC_OFR1_OFFSETPOS             ADC_OFR1_OFFSETPOS_Msk                  /*!< ADC offset number 1 positive */
2022 #define ADC_OFR1_SATEN_Pos             (25U)
2023 #define ADC_OFR1_SATEN_Msk             (0x1UL << ADC_OFR1_SATEN_Pos)           /*!< 0x02000000 */
2024 #define ADC_OFR1_SATEN                 ADC_OFR1_SATEN_Msk                      /*!< ADC offset number 1 saturation enable */
2025 
2026 #define ADC_OFR1_OFFSET1_CH_Pos        (26U)
2027 #define ADC_OFR1_OFFSET1_CH_Msk        (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x7C000000 */
2028 #define ADC_OFR1_OFFSET1_CH            ADC_OFR1_OFFSET1_CH_Msk                 /*!< ADC offset number 1 channel selection */
2029 #define ADC_OFR1_OFFSET1_CH_0          (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x04000000 */
2030 #define ADC_OFR1_OFFSET1_CH_1          (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x08000000 */
2031 #define ADC_OFR1_OFFSET1_CH_2          (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x10000000 */
2032 #define ADC_OFR1_OFFSET1_CH_3          (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x20000000 */
2033 #define ADC_OFR1_OFFSET1_CH_4          (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x40000000 */
2034 
2035 #define ADC_OFR1_OFFSET1_EN_Pos        (31U)
2036 #define ADC_OFR1_OFFSET1_EN_Msk        (0x1UL << ADC_OFR1_OFFSET1_EN_Pos)      /*!< 0x80000000 */
2037 #define ADC_OFR1_OFFSET1_EN            ADC_OFR1_OFFSET1_EN_Msk                 /*!< ADC offset number 1 enable */
2038 
2039 /********************  Bit definition for ADC_OFR2 register  ******************/
2040 #define ADC_OFR2_OFFSET2_Pos           (0U)
2041 #define ADC_OFR2_OFFSET2_Msk           (0xFFFUL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000FFF */
2042 #define ADC_OFR2_OFFSET2               ADC_OFR2_OFFSET2_Msk                    /*!< ADC offset number 2 offset level */
2043 
2044 #define ADC_OFR2_OFFSETPOS_Pos         (24U)
2045 #define ADC_OFR2_OFFSETPOS_Msk         (0x1UL << ADC_OFR2_OFFSETPOS_Pos)       /*!< 0x01000000 */
2046 #define ADC_OFR2_OFFSETPOS             ADC_OFR2_OFFSETPOS_Msk                  /*!< ADC offset number 2 positive */
2047 #define ADC_OFR2_SATEN_Pos             (25U)
2048 #define ADC_OFR2_SATEN_Msk             (0x1UL << ADC_OFR2_SATEN_Pos)           /*!< 0x02000000 */
2049 #define ADC_OFR2_SATEN                 ADC_OFR2_SATEN_Msk                      /*!< ADC offset number 2 saturation enable */
2050 
2051 #define ADC_OFR2_OFFSET2_CH_Pos        (26U)
2052 #define ADC_OFR2_OFFSET2_CH_Msk        (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x7C000000 */
2053 #define ADC_OFR2_OFFSET2_CH            ADC_OFR2_OFFSET2_CH_Msk                 /*!< ADC offset number 2 channel selection */
2054 #define ADC_OFR2_OFFSET2_CH_0          (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x04000000 */
2055 #define ADC_OFR2_OFFSET2_CH_1          (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x08000000 */
2056 #define ADC_OFR2_OFFSET2_CH_2          (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x10000000 */
2057 #define ADC_OFR2_OFFSET2_CH_3          (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x20000000 */
2058 #define ADC_OFR2_OFFSET2_CH_4          (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x40000000 */
2059 
2060 #define ADC_OFR2_OFFSET2_EN_Pos        (31U)
2061 #define ADC_OFR2_OFFSET2_EN_Msk        (0x1UL << ADC_OFR2_OFFSET2_EN_Pos)      /*!< 0x80000000 */
2062 #define ADC_OFR2_OFFSET2_EN            ADC_OFR2_OFFSET2_EN_Msk                 /*!< ADC offset number 2 enable */
2063 
2064 /********************  Bit definition for ADC_OFR3 register  ******************/
2065 #define ADC_OFR3_OFFSET3_Pos           (0U)
2066 #define ADC_OFR3_OFFSET3_Msk           (0xFFFUL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000FFF */
2067 #define ADC_OFR3_OFFSET3               ADC_OFR3_OFFSET3_Msk                    /*!< ADC offset number 3 offset level */
2068 
2069 #define ADC_OFR3_OFFSETPOS_Pos         (24U)
2070 #define ADC_OFR3_OFFSETPOS_Msk         (0x1UL << ADC_OFR3_OFFSETPOS_Pos)       /*!< 0x01000000 */
2071 #define ADC_OFR3_OFFSETPOS             ADC_OFR3_OFFSETPOS_Msk                  /*!< ADC offset number 3 positive */
2072 #define ADC_OFR3_SATEN_Pos             (25U)
2073 #define ADC_OFR3_SATEN_Msk             (0x1UL << ADC_OFR3_SATEN_Pos)           /*!< 0x02000000 */
2074 #define ADC_OFR3_SATEN                 ADC_OFR3_SATEN_Msk                      /*!< ADC offset number 3 saturation enable */
2075 
2076 #define ADC_OFR3_OFFSET3_CH_Pos        (26U)
2077 #define ADC_OFR3_OFFSET3_CH_Msk        (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x7C000000 */
2078 #define ADC_OFR3_OFFSET3_CH            ADC_OFR3_OFFSET3_CH_Msk                 /*!< ADC offset number 3 channel selection */
2079 #define ADC_OFR3_OFFSET3_CH_0          (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x04000000 */
2080 #define ADC_OFR3_OFFSET3_CH_1          (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x08000000 */
2081 #define ADC_OFR3_OFFSET3_CH_2          (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x10000000 */
2082 #define ADC_OFR3_OFFSET3_CH_3          (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x20000000 */
2083 #define ADC_OFR3_OFFSET3_CH_4          (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x40000000 */
2084 
2085 #define ADC_OFR3_OFFSET3_EN_Pos        (31U)
2086 #define ADC_OFR3_OFFSET3_EN_Msk        (0x1UL << ADC_OFR3_OFFSET3_EN_Pos)      /*!< 0x80000000 */
2087 #define ADC_OFR3_OFFSET3_EN            ADC_OFR3_OFFSET3_EN_Msk                 /*!< ADC offset number 3 enable */
2088 
2089 /********************  Bit definition for ADC_OFR4 register  ******************/
2090 #define ADC_OFR4_OFFSET4_Pos           (0U)
2091 #define ADC_OFR4_OFFSET4_Msk           (0xFFFUL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000FFF */
2092 #define ADC_OFR4_OFFSET4               ADC_OFR4_OFFSET4_Msk                    /*!< ADC offset number 4 offset level */
2093 
2094 #define ADC_OFR4_OFFSETPOS_Pos         (24U)
2095 #define ADC_OFR4_OFFSETPOS_Msk         (0x1UL << ADC_OFR4_OFFSETPOS_Pos)       /*!< 0x01000000 */
2096 #define ADC_OFR4_OFFSETPOS             ADC_OFR4_OFFSETPOS_Msk                  /*!< ADC offset number 4 positive */
2097 #define ADC_OFR4_SATEN_Pos             (25U)
2098 #define ADC_OFR4_SATEN_Msk             (0x1UL << ADC_OFR4_SATEN_Pos)           /*!< 0x02000000 */
2099 #define ADC_OFR4_SATEN                 ADC_OFR4_SATEN_Msk                      /*!< ADC offset number 4 saturation enable */
2100 
2101 #define ADC_OFR4_OFFSET4_CH_Pos        (26U)
2102 #define ADC_OFR4_OFFSET4_CH_Msk        (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x7C000000 */
2103 #define ADC_OFR4_OFFSET4_CH            ADC_OFR4_OFFSET4_CH_Msk                 /*!< ADC offset number 4 channel selection */
2104 #define ADC_OFR4_OFFSET4_CH_0          (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x04000000 */
2105 #define ADC_OFR4_OFFSET4_CH_1          (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x08000000 */
2106 #define ADC_OFR4_OFFSET4_CH_2          (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x10000000 */
2107 #define ADC_OFR4_OFFSET4_CH_3          (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x20000000 */
2108 #define ADC_OFR4_OFFSET4_CH_4          (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x40000000 */
2109 
2110 #define ADC_OFR4_OFFSET4_EN_Pos        (31U)
2111 #define ADC_OFR4_OFFSET4_EN_Msk        (0x1UL << ADC_OFR4_OFFSET4_EN_Pos)      /*!< 0x80000000 */
2112 #define ADC_OFR4_OFFSET4_EN            ADC_OFR4_OFFSET4_EN_Msk                 /*!< ADC offset number 4 enable */
2113 
2114 /********************  Bit definition for ADC_JDR1 register  ******************/
2115 #define ADC_JDR1_JDATA_Pos             (0U)
2116 #define ADC_JDR1_JDATA_Msk             (0xFFFFUL << ADC_JDR1_JDATA_Pos)        /*!< 0x0000FFFF */
2117 #define ADC_JDR1_JDATA                 ADC_JDR1_JDATA_Msk                      /*!< ADC group injected sequencer rank 1 conversion data */
2118 
2119 /********************  Bit definition for ADC_JDR2 register  ******************/
2120 #define ADC_JDR2_JDATA_Pos             (0U)
2121 #define ADC_JDR2_JDATA_Msk             (0xFFFFUL << ADC_JDR2_JDATA_Pos)        /*!< 0x0000FFFF */
2122 #define ADC_JDR2_JDATA                 ADC_JDR2_JDATA_Msk                      /*!< ADC group injected sequencer rank 2 conversion data */
2123 
2124 /********************  Bit definition for ADC_JDR3 register  ******************/
2125 #define ADC_JDR3_JDATA_Pos             (0U)
2126 #define ADC_JDR3_JDATA_Msk             (0xFFFFUL << ADC_JDR3_JDATA_Pos)        /*!< 0x0000FFFF */
2127 #define ADC_JDR3_JDATA                 ADC_JDR3_JDATA_Msk                      /*!< ADC group injected sequencer rank 3 conversion data */
2128 
2129 /********************  Bit definition for ADC_JDR4 register  ******************/
2130 #define ADC_JDR4_JDATA_Pos             (0U)
2131 #define ADC_JDR4_JDATA_Msk             (0xFFFFUL << ADC_JDR4_JDATA_Pos)        /*!< 0x0000FFFF */
2132 #define ADC_JDR4_JDATA                 ADC_JDR4_JDATA_Msk                      /*!< ADC group injected sequencer rank 4 conversion data */
2133 
2134 /********************  Bit definition for ADC_AWD2CR register  ****************/
2135 #define ADC_AWD2CR_AWD2CH_Pos          (0U)
2136 #define ADC_AWD2CR_AWD2CH_Msk          (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x0007FFFF */
2137 #define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
2138 #define ADC_AWD2CR_AWD2CH_0            (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000001 */
2139 #define ADC_AWD2CR_AWD2CH_1            (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000002 */
2140 #define ADC_AWD2CR_AWD2CH_2            (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000004 */
2141 #define ADC_AWD2CR_AWD2CH_3            (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000008 */
2142 #define ADC_AWD2CR_AWD2CH_4            (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000010 */
2143 #define ADC_AWD2CR_AWD2CH_5            (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000020 */
2144 #define ADC_AWD2CR_AWD2CH_6            (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000040 */
2145 #define ADC_AWD2CR_AWD2CH_7            (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000080 */
2146 #define ADC_AWD2CR_AWD2CH_8            (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000100 */
2147 #define ADC_AWD2CR_AWD2CH_9            (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000200 */
2148 #define ADC_AWD2CR_AWD2CH_10           (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000400 */
2149 #define ADC_AWD2CR_AWD2CH_11           (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000800 */
2150 #define ADC_AWD2CR_AWD2CH_12           (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00001000 */
2151 #define ADC_AWD2CR_AWD2CH_13           (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00002000 */
2152 #define ADC_AWD2CR_AWD2CH_14           (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00004000 */
2153 #define ADC_AWD2CR_AWD2CH_15           (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00008000 */
2154 #define ADC_AWD2CR_AWD2CH_16           (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00010000 */
2155 #define ADC_AWD2CR_AWD2CH_17           (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00020000 */
2156 #define ADC_AWD2CR_AWD2CH_18           (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00040000 */
2157 
2158 /********************  Bit definition for ADC_AWD3CR register  ****************/
2159 #define ADC_AWD3CR_AWD3CH_Pos          (0U)
2160 #define ADC_AWD3CR_AWD3CH_Msk          (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x0007FFFF */
2161 #define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
2162 #define ADC_AWD3CR_AWD3CH_0            (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000001 */
2163 #define ADC_AWD3CR_AWD3CH_1            (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000002 */
2164 #define ADC_AWD3CR_AWD3CH_2            (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000004 */
2165 #define ADC_AWD3CR_AWD3CH_3            (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000008 */
2166 #define ADC_AWD3CR_AWD3CH_4            (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000010 */
2167 #define ADC_AWD3CR_AWD3CH_5            (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000020 */
2168 #define ADC_AWD3CR_AWD3CH_6            (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000040 */
2169 #define ADC_AWD3CR_AWD3CH_7            (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000080 */
2170 #define ADC_AWD3CR_AWD3CH_8            (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000100 */
2171 #define ADC_AWD3CR_AWD3CH_9            (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000200 */
2172 #define ADC_AWD3CR_AWD3CH_10           (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000400 */
2173 #define ADC_AWD3CR_AWD3CH_11           (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000800 */
2174 #define ADC_AWD3CR_AWD3CH_12           (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00001000 */
2175 #define ADC_AWD3CR_AWD3CH_13           (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00002000 */
2176 #define ADC_AWD3CR_AWD3CH_14           (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00004000 */
2177 #define ADC_AWD3CR_AWD3CH_15           (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00008000 */
2178 #define ADC_AWD3CR_AWD3CH_16           (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00010000 */
2179 #define ADC_AWD3CR_AWD3CH_17           (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00020000 */
2180 #define ADC_AWD3CR_AWD3CH_18           (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00040000 */
2181 
2182 /********************  Bit definition for ADC_DIFSEL register  ****************/
2183 #define ADC_DIFSEL_DIFSEL_Pos          (0U)
2184 #define ADC_DIFSEL_DIFSEL_Msk          (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x0007FFFF */
2185 #define ADC_DIFSEL_DIFSEL              ADC_DIFSEL_DIFSEL_Msk                   /*!< ADC channel differential or single-ended mode */
2186 #define ADC_DIFSEL_DIFSEL_0            (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000001 */
2187 #define ADC_DIFSEL_DIFSEL_1            (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000002 */
2188 #define ADC_DIFSEL_DIFSEL_2            (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000004 */
2189 #define ADC_DIFSEL_DIFSEL_3            (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000008 */
2190 #define ADC_DIFSEL_DIFSEL_4            (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000010 */
2191 #define ADC_DIFSEL_DIFSEL_5            (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000020 */
2192 #define ADC_DIFSEL_DIFSEL_6            (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000040 */
2193 #define ADC_DIFSEL_DIFSEL_7            (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000080 */
2194 #define ADC_DIFSEL_DIFSEL_8            (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000100 */
2195 #define ADC_DIFSEL_DIFSEL_9            (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000200 */
2196 #define ADC_DIFSEL_DIFSEL_10           (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000400 */
2197 #define ADC_DIFSEL_DIFSEL_11           (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000800 */
2198 #define ADC_DIFSEL_DIFSEL_12           (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00001000 */
2199 #define ADC_DIFSEL_DIFSEL_13           (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00002000 */
2200 #define ADC_DIFSEL_DIFSEL_14           (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00004000 */
2201 #define ADC_DIFSEL_DIFSEL_15           (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00008000 */
2202 #define ADC_DIFSEL_DIFSEL_16           (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00010000 */
2203 #define ADC_DIFSEL_DIFSEL_17           (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00020000 */
2204 #define ADC_DIFSEL_DIFSEL_18           (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00040000 */
2205 
2206 /********************  Bit definition for ADC_CALFACT register  ***************/
2207 #define ADC_CALFACT_CALFACT_S_Pos      (0U)
2208 #define ADC_CALFACT_CALFACT_S_Msk      (0x7FUL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x0000007F */
2209 #define ADC_CALFACT_CALFACT_S          ADC_CALFACT_CALFACT_S_Msk               /*!< ADC calibration factor in single-ended mode */
2210 #define ADC_CALFACT_CALFACT_S_0        (0x01UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000001 */
2211 #define ADC_CALFACT_CALFACT_S_1        (0x02UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000002 */
2212 #define ADC_CALFACT_CALFACT_S_2        (0x04UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000004 */
2213 #define ADC_CALFACT_CALFACT_S_3        (0x08UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000008 */
2214 #define ADC_CALFACT_CALFACT_S_4        (0x10UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000010 */
2215 #define ADC_CALFACT_CALFACT_S_5        (0x20UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000020 */
2216 #define ADC_CALFACT_CALFACT_S_6        (0x40UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000030 */
2217 
2218 #define ADC_CALFACT_CALFACT_D_Pos      (16U)
2219 #define ADC_CALFACT_CALFACT_D_Msk      (0x7FUL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x007F0000 */
2220 #define ADC_CALFACT_CALFACT_D          ADC_CALFACT_CALFACT_D_Msk               /*!< ADC calibration factor in differential mode */
2221 #define ADC_CALFACT_CALFACT_D_0        (0x01UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00010000 */
2222 #define ADC_CALFACT_CALFACT_D_1        (0x02UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00020000 */
2223 #define ADC_CALFACT_CALFACT_D_2        (0x04UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00040000 */
2224 #define ADC_CALFACT_CALFACT_D_3        (0x08UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00080000 */
2225 #define ADC_CALFACT_CALFACT_D_4        (0x10UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00100000 */
2226 #define ADC_CALFACT_CALFACT_D_5        (0x20UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00200000 */
2227 #define ADC_CALFACT_CALFACT_D_6        (0x40UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00300000 */
2228 
2229 /********************  Bit definition for ADC_GCOMP register  *****************/
2230 #define ADC_GCOMP_GCOMPCOEFF_Pos       (0U)
2231 #define ADC_GCOMP_GCOMPCOEFF_Msk       (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)  /*!< 0x00003FFF */
2232 #define ADC_GCOMP_GCOMPCOEFF           ADC_GCOMP_GCOMPCOEFF_Msk                /*!< ADC Gain Compensation Coefficient */
2233 
2234 /*************************  ADC Common registers  *****************************/
2235 /********************  Bit definition for ADC_CSR register  *******************/
2236 #define ADC_CSR_ADRDY_MST_Pos          (0U)
2237 #define ADC_CSR_ADRDY_MST_Msk          (0x1UL << ADC_CSR_ADRDY_MST_Pos)        /*!< 0x00000001 */
2238 #define ADC_CSR_ADRDY_MST              ADC_CSR_ADRDY_MST_Msk                   /*!< ADC multimode master ready flag */
2239 #define ADC_CSR_EOSMP_MST_Pos          (1U)
2240 #define ADC_CSR_EOSMP_MST_Msk          (0x1UL << ADC_CSR_EOSMP_MST_Pos)        /*!< 0x00000002 */
2241 #define ADC_CSR_EOSMP_MST              ADC_CSR_EOSMP_MST_Msk                   /*!< ADC multimode master group regular end of sampling flag */
2242 #define ADC_CSR_EOC_MST_Pos            (2U)
2243 #define ADC_CSR_EOC_MST_Msk            (0x1UL << ADC_CSR_EOC_MST_Pos)          /*!< 0x00000004 */
2244 #define ADC_CSR_EOC_MST                ADC_CSR_EOC_MST_Msk                     /*!< ADC multimode master group regular end of unitary conversion flag */
2245 #define ADC_CSR_EOS_MST_Pos            (3U)
2246 #define ADC_CSR_EOS_MST_Msk            (0x1UL << ADC_CSR_EOS_MST_Pos)          /*!< 0x00000008 */
2247 #define ADC_CSR_EOS_MST                ADC_CSR_EOS_MST_Msk                     /*!< ADC multimode master group regular end of sequence conversions flag */
2248 #define ADC_CSR_OVR_MST_Pos            (4U)
2249 #define ADC_CSR_OVR_MST_Msk            (0x1UL << ADC_CSR_OVR_MST_Pos)          /*!< 0x00000010 */
2250 #define ADC_CSR_OVR_MST                ADC_CSR_OVR_MST_Msk                     /*!< ADC multimode master group regular overrun flag */
2251 #define ADC_CSR_JEOC_MST_Pos           (5U)
2252 #define ADC_CSR_JEOC_MST_Msk           (0x1UL << ADC_CSR_JEOC_MST_Pos)         /*!< 0x00000020 */
2253 #define ADC_CSR_JEOC_MST               ADC_CSR_JEOC_MST_Msk                    /*!< ADC multimode master group injected end of unitary conversion flag */
2254 #define ADC_CSR_JEOS_MST_Pos           (6U)
2255 #define ADC_CSR_JEOS_MST_Msk           (0x1UL << ADC_CSR_JEOS_MST_Pos)         /*!< 0x00000040 */
2256 #define ADC_CSR_JEOS_MST               ADC_CSR_JEOS_MST_Msk                    /*!< ADC multimode master group injected end of sequence conversions flag */
2257 #define ADC_CSR_AWD1_MST_Pos           (7U)
2258 #define ADC_CSR_AWD1_MST_Msk           (0x1UL << ADC_CSR_AWD1_MST_Pos)         /*!< 0x00000080 */
2259 #define ADC_CSR_AWD1_MST               ADC_CSR_AWD1_MST_Msk                    /*!< ADC multimode master analog watchdog 1 flag */
2260 #define ADC_CSR_AWD2_MST_Pos           (8U)
2261 #define ADC_CSR_AWD2_MST_Msk           (0x1UL << ADC_CSR_AWD2_MST_Pos)         /*!< 0x00000100 */
2262 #define ADC_CSR_AWD2_MST               ADC_CSR_AWD2_MST_Msk                    /*!< ADC multimode master analog watchdog 2 flag */
2263 #define ADC_CSR_AWD3_MST_Pos           (9U)
2264 #define ADC_CSR_AWD3_MST_Msk           (0x1UL << ADC_CSR_AWD3_MST_Pos)         /*!< 0x00000200 */
2265 #define ADC_CSR_AWD3_MST               ADC_CSR_AWD3_MST_Msk                    /*!< ADC multimode master analog watchdog 3 flag */
2266 #define ADC_CSR_JQOVF_MST_Pos          (10U)
2267 #define ADC_CSR_JQOVF_MST_Msk          (0x1UL << ADC_CSR_JQOVF_MST_Pos)        /*!< 0x00000400 */
2268 #define ADC_CSR_JQOVF_MST              ADC_CSR_JQOVF_MST_Msk                   /*!< ADC multimode master group injected contexts queue overflow flag */
2269 
2270 #define ADC_CSR_ADRDY_SLV_Pos          (16U)
2271 #define ADC_CSR_ADRDY_SLV_Msk          (0x1UL << ADC_CSR_ADRDY_SLV_Pos)        /*!< 0x00010000 */
2272 #define ADC_CSR_ADRDY_SLV              ADC_CSR_ADRDY_SLV_Msk                   /*!< ADC multimode slave ready flag */
2273 #define ADC_CSR_EOSMP_SLV_Pos          (17U)
2274 #define ADC_CSR_EOSMP_SLV_Msk          (0x1UL << ADC_CSR_EOSMP_SLV_Pos)        /*!< 0x00020000 */
2275 #define ADC_CSR_EOSMP_SLV              ADC_CSR_EOSMP_SLV_Msk                   /*!< ADC multimode slave group regular end of sampling flag */
2276 #define ADC_CSR_EOC_SLV_Pos            (18U)
2277 #define ADC_CSR_EOC_SLV_Msk            (0x1UL << ADC_CSR_EOC_SLV_Pos)          /*!< 0x00040000 */
2278 #define ADC_CSR_EOC_SLV                ADC_CSR_EOC_SLV_Msk                     /*!< ADC multimode slave group regular end of unitary conversion flag */
2279 #define ADC_CSR_EOS_SLV_Pos            (19U)
2280 #define ADC_CSR_EOS_SLV_Msk            (0x1UL << ADC_CSR_EOS_SLV_Pos)          /*!< 0x00080000 */
2281 #define ADC_CSR_EOS_SLV                ADC_CSR_EOS_SLV_Msk                     /*!< ADC multimode slave group regular end of sequence conversions flag */
2282 #define ADC_CSR_OVR_SLV_Pos            (20U)
2283 #define ADC_CSR_OVR_SLV_Msk            (0x1UL << ADC_CSR_OVR_SLV_Pos)          /*!< 0x00100000 */
2284 #define ADC_CSR_OVR_SLV                ADC_CSR_OVR_SLV_Msk                     /*!< ADC multimode slave group regular overrun flag */
2285 #define ADC_CSR_JEOC_SLV_Pos           (21U)
2286 #define ADC_CSR_JEOC_SLV_Msk           (0x1UL << ADC_CSR_JEOC_SLV_Pos)         /*!< 0x00200000 */
2287 #define ADC_CSR_JEOC_SLV               ADC_CSR_JEOC_SLV_Msk                    /*!< ADC multimode slave group injected end of unitary conversion flag */
2288 #define ADC_CSR_JEOS_SLV_Pos           (22U)
2289 #define ADC_CSR_JEOS_SLV_Msk           (0x1UL << ADC_CSR_JEOS_SLV_Pos)         /*!< 0x00400000 */
2290 #define ADC_CSR_JEOS_SLV               ADC_CSR_JEOS_SLV_Msk                    /*!< ADC multimode slave group injected end of sequence conversions flag */
2291 #define ADC_CSR_AWD1_SLV_Pos           (23U)
2292 #define ADC_CSR_AWD1_SLV_Msk           (0x1UL << ADC_CSR_AWD1_SLV_Pos)         /*!< 0x00800000 */
2293 #define ADC_CSR_AWD1_SLV               ADC_CSR_AWD1_SLV_Msk                    /*!< ADC multimode slave analog watchdog 1 flag */
2294 #define ADC_CSR_AWD2_SLV_Pos           (24U)
2295 #define ADC_CSR_AWD2_SLV_Msk           (0x1UL << ADC_CSR_AWD2_SLV_Pos)         /*!< 0x01000000 */
2296 #define ADC_CSR_AWD2_SLV               ADC_CSR_AWD2_SLV_Msk                    /*!< ADC multimode slave analog watchdog 2 flag */
2297 #define ADC_CSR_AWD3_SLV_Pos           (25U)
2298 #define ADC_CSR_AWD3_SLV_Msk           (0x1UL << ADC_CSR_AWD3_SLV_Pos)         /*!< 0x02000000 */
2299 #define ADC_CSR_AWD3_SLV               ADC_CSR_AWD3_SLV_Msk                    /*!< ADC multimode slave analog watchdog 3 flag */
2300 #define ADC_CSR_JQOVF_SLV_Pos          (26U)
2301 #define ADC_CSR_JQOVF_SLV_Msk          (0x1UL << ADC_CSR_JQOVF_SLV_Pos)        /*!< 0x04000000 */
2302 #define ADC_CSR_JQOVF_SLV              ADC_CSR_JQOVF_SLV_Msk                   /*!< ADC multimode slave group injected contexts queue overflow flag */
2303 
2304 /********************  Bit definition for ADC_CCR register  *******************/
2305 #define ADC_CCR_DUAL_Pos               (0U)
2306 #define ADC_CCR_DUAL_Msk               (0x1FUL << ADC_CCR_DUAL_Pos)            /*!< 0x0000001F */
2307 #define ADC_CCR_DUAL                   ADC_CCR_DUAL_Msk                        /*!< ADC multimode mode selection */
2308 #define ADC_CCR_DUAL_0                 (0x01UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000001 */
2309 #define ADC_CCR_DUAL_1                 (0x02UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000002 */
2310 #define ADC_CCR_DUAL_2                 (0x04UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000004 */
2311 #define ADC_CCR_DUAL_3                 (0x08UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000008 */
2312 #define ADC_CCR_DUAL_4                 (0x10UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000010 */
2313 
2314 #define ADC_CCR_DELAY_Pos              (8U)
2315 #define ADC_CCR_DELAY_Msk              (0xFUL << ADC_CCR_DELAY_Pos)            /*!< 0x00000F00 */
2316 #define ADC_CCR_DELAY                  ADC_CCR_DELAY_Msk                       /*!< ADC multimode delay between 2 sampling phases */
2317 #define ADC_CCR_DELAY_0                (0x1UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000100 */
2318 #define ADC_CCR_DELAY_1                (0x2UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000200 */
2319 #define ADC_CCR_DELAY_2                (0x4UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000400 */
2320 #define ADC_CCR_DELAY_3                (0x8UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000800 */
2321 
2322 #define ADC_CCR_DMACFG_Pos             (13U)
2323 #define ADC_CCR_DMACFG_Msk             (0x1UL << ADC_CCR_DMACFG_Pos)           /*!< 0x00002000 */
2324 #define ADC_CCR_DMACFG                 ADC_CCR_DMACFG_Msk                      /*!< ADC multimode DMA transfer configuration */
2325 
2326 #define ADC_CCR_MDMA_Pos               (14U)
2327 #define ADC_CCR_MDMA_Msk               (0x3UL << ADC_CCR_MDMA_Pos)             /*!< 0x0000C000 */
2328 #define ADC_CCR_MDMA                   ADC_CCR_MDMA_Msk                        /*!< ADC multimode DMA transfer enable */
2329 #define ADC_CCR_MDMA_0                 (0x1UL << ADC_CCR_MDMA_Pos)             /*!< 0x00004000 */
2330 #define ADC_CCR_MDMA_1                 (0x2UL << ADC_CCR_MDMA_Pos)             /*!< 0x00008000 */
2331 
2332 #define ADC_CCR_CKMODE_Pos             (16U)
2333 #define ADC_CCR_CKMODE_Msk             (0x3UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00030000 */
2334 #define ADC_CCR_CKMODE                 ADC_CCR_CKMODE_Msk                      /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
2335 #define ADC_CCR_CKMODE_0               (0x1UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00010000 */
2336 #define ADC_CCR_CKMODE_1               (0x2UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00020000 */
2337 
2338 #define ADC_CCR_PRESC_Pos              (18U)
2339 #define ADC_CCR_PRESC_Msk              (0xFUL << ADC_CCR_PRESC_Pos)            /*!< 0x003C0000 */
2340 #define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */
2341 #define ADC_CCR_PRESC_0                (0x1UL << ADC_CCR_PRESC_Pos)            /*!< 0x00040000 */
2342 #define ADC_CCR_PRESC_1                (0x2UL << ADC_CCR_PRESC_Pos)            /*!< 0x00080000 */
2343 #define ADC_CCR_PRESC_2                (0x4UL << ADC_CCR_PRESC_Pos)            /*!< 0x00100000 */
2344 #define ADC_CCR_PRESC_3                (0x8UL << ADC_CCR_PRESC_Pos)            /*!< 0x00200000 */
2345 
2346 #define ADC_CCR_VREFEN_Pos             (22U)
2347 #define ADC_CCR_VREFEN_Msk             (0x1UL << ADC_CCR_VREFEN_Pos)           /*!< 0x00400000 */
2348 #define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
2349 #define ADC_CCR_VSENSESEL_Pos          (23U)
2350 #define ADC_CCR_VSENSESEL_Msk          (0x1UL << ADC_CCR_VSENSESEL_Pos)        /*!< 0x00800000 */
2351 #define ADC_CCR_VSENSESEL              ADC_CCR_VSENSESEL_Msk                   /*!< ADC internal path to temperature sensor enable */
2352 #define ADC_CCR_VBATSEL_Pos            (24U)
2353 #define ADC_CCR_VBATSEL_Msk            (0x1UL << ADC_CCR_VBATSEL_Pos)          /*!< 0x01000000 */
2354 #define ADC_CCR_VBATSEL                ADC_CCR_VBATSEL_Msk                     /*!< ADC internal path to battery voltage enable */
2355 
2356 /********************  Bit definition for ADC_CDR register  *******************/
2357 #define ADC_CDR_RDATA_MST_Pos          (0U)
2358 #define ADC_CDR_RDATA_MST_Msk          (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x0000FFFF */
2359 #define ADC_CDR_RDATA_MST              ADC_CDR_RDATA_MST_Msk                   /*!< ADC multimode master group regular conversion data */
2360 
2361 #define ADC_CDR_RDATA_SLV_Pos          (16U)
2362 #define ADC_CDR_RDATA_SLV_Msk          (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0xFFFF0000 */
2363 #define ADC_CDR_RDATA_SLV              ADC_CDR_RDATA_SLV_Msk                   /*!< ADC multimode slave group regular conversion data */
2364 
2365 
2366 /******************************************************************************/
2367 /*                                                                            */
2368 /*                      Analog Comparators (COMP)                             */
2369 /*                                                                            */
2370 /******************************************************************************/
2371 /**********************  Bit definition for COMP_CSR register  ****************/
2372 #define COMP_CSR_EN_Pos            (0U)
2373 #define COMP_CSR_EN_Msk            (0x1UL << COMP_CSR_EN_Pos)                  /*!< 0x00000001 */
2374 #define COMP_CSR_EN                COMP_CSR_EN_Msk                             /*!< Comparator enable */
2375 
2376 #define COMP_CSR_INMSEL_Pos        (4U)
2377 #define COMP_CSR_INMSEL_Msk        (0xFUL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000070 */
2378 #define COMP_CSR_INMSEL            COMP_CSR_INMSEL_Msk                         /*!< Comparator input minus selection */
2379 #define COMP_CSR_INMSEL_0          (0x1UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000010 */
2380 #define COMP_CSR_INMSEL_1          (0x2UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000020 */
2381 #define COMP_CSR_INMSEL_2          (0x4UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000040 */
2382 #define COMP_CSR_INMSEL_3          (0x8UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000080 */
2383 
2384 #define COMP_CSR_INPSEL_Pos        (8U)
2385 #define COMP_CSR_INPSEL_Msk        (0x1UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000100 */
2386 #define COMP_CSR_INPSEL            COMP_CSR_INPSEL_Msk                         /*!< Comparator input plus selection */
2387 
2388 #define COMP_CSR_POLARITY_Pos      (15U)
2389 #define COMP_CSR_POLARITY_Msk      (0x1UL << COMP_CSR_POLARITY_Pos)            /*!< 0x00008000 */
2390 #define COMP_CSR_POLARITY          COMP_CSR_POLARITY_Msk                       /*!< Comparator output polarity */
2391 
2392 #define COMP_CSR_HYST_Pos          (16U)
2393 #define COMP_CSR_HYST_Msk          (0x7UL << COMP_CSR_HYST_Pos)                /*!< 0x00070000 */
2394 #define COMP_CSR_HYST              COMP_CSR_HYST_Msk                           /*!< Comparator hysteresis */
2395 #define COMP_CSR_HYST_0            (0x1UL << COMP_CSR_HYST_Pos)                /*!< 0x00010000 */
2396 #define COMP_CSR_HYST_1            (0x2UL << COMP_CSR_HYST_Pos)                /*!< 0x00020000 */
2397 #define COMP_CSR_HYST_2            (0x4UL << COMP_CSR_HYST_Pos)                /*!< 0x00040000 */
2398 
2399 #define COMP_CSR_BLANKING_Pos      (19U)
2400 #define COMP_CSR_BLANKING_Msk      (0x7UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00380000 */
2401 #define COMP_CSR_BLANKING          COMP_CSR_BLANKING_Msk                       /*!< Comparator blanking source */
2402 #define COMP_CSR_BLANKING_0        (0x1UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00080000 */
2403 #define COMP_CSR_BLANKING_1        (0x2UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00100000 */
2404 #define COMP_CSR_BLANKING_2        (0x4UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00200000 */
2405 
2406 #define COMP_CSR_BRGEN_Pos         (22U)
2407 #define COMP_CSR_BRGEN_Msk         (0x1UL << COMP_CSR_BRGEN_Pos)               /*!< 0x00400000 */
2408 #define COMP_CSR_BRGEN             COMP_CSR_BRGEN_Msk                          /*!< Comparator scaler bridge enable */
2409 
2410 #define COMP_CSR_SCALEN_Pos        (23U)
2411 #define COMP_CSR_SCALEN_Msk        (0x1UL << COMP_CSR_SCALEN_Pos)              /*!< 0x00800000 */
2412 #define COMP_CSR_SCALEN            COMP_CSR_SCALEN_Msk                         /*!< Comparator voltage scaler enable */
2413 
2414 #define COMP_CSR_VALUE_Pos         (30U)
2415 #define COMP_CSR_VALUE_Msk         (0x1UL << COMP_CSR_VALUE_Pos)               /*!< 0x40000000 */
2416 #define COMP_CSR_VALUE             COMP_CSR_VALUE_Msk                          /*!< Comparator output level */
2417 
2418 #define COMP_CSR_LOCK_Pos          (31U)
2419 #define COMP_CSR_LOCK_Msk          (0x1UL << COMP_CSR_LOCK_Pos)                /*!< 0x80000000 */
2420 #define COMP_CSR_LOCK              COMP_CSR_LOCK_Msk                           /*!< Comparator lock */
2421 
2422 /******************************************************************************/
2423 /*                                                                            */
2424 /*                          CORDIC calculation unit                           */
2425 /*                                                                            */
2426 /******************************************************************************/
2427 /*******************  Bit definition for CORDIC_CSR register  *****************/
2428 #define CORDIC_CSR_FUNC_Pos      (0U)
2429 #define CORDIC_CSR_FUNC_Msk      (0xFUL << CORDIC_CSR_FUNC_Pos)                /*!< 0x0000000F */
2430 #define CORDIC_CSR_FUNC          CORDIC_CSR_FUNC_Msk                           /*!< Function */
2431 #define CORDIC_CSR_FUNC_0        (0x1UL << CORDIC_CSR_FUNC_Pos)                /*!< 0x00000001 */
2432 #define CORDIC_CSR_FUNC_1        (0x2UL << CORDIC_CSR_FUNC_Pos)                /*!< 0x00000002 */
2433 #define CORDIC_CSR_FUNC_2        (0x4UL << CORDIC_CSR_FUNC_Pos)                /*!< 0x00000004 */
2434 #define CORDIC_CSR_FUNC_3        (0x8UL << CORDIC_CSR_FUNC_Pos)                /*!< 0x00000008 */
2435 #define CORDIC_CSR_PRECISION_Pos (4U)
2436 #define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x000000F0 */
2437 #define CORDIC_CSR_PRECISION     CORDIC_CSR_PRECISION_Msk                      /*!< Precision */
2438 #define CORDIC_CSR_PRECISION_0   (0x1UL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x00000010 */
2439 #define CORDIC_CSR_PRECISION_1   (0x2UL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x00000020 */
2440 #define CORDIC_CSR_PRECISION_2   (0x4UL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x00000040 */
2441 #define CORDIC_CSR_PRECISION_3   (0x8UL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x00000080 */
2442 #define CORDIC_CSR_SCALE_Pos     (8U)
2443 #define CORDIC_CSR_SCALE_Msk     (0x7UL << CORDIC_CSR_SCALE_Pos)               /*!< 0x00000700 */
2444 #define CORDIC_CSR_SCALE         CORDIC_CSR_SCALE_Msk                          /*!< Scaling factor */
2445 #define CORDIC_CSR_SCALE_0       (0x1UL << CORDIC_CSR_SCALE_Pos)               /*!< 0x00000100 */
2446 #define CORDIC_CSR_SCALE_1       (0x2UL << CORDIC_CSR_SCALE_Pos)               /*!< 0x00000200 */
2447 #define CORDIC_CSR_SCALE_2       (0x4UL << CORDIC_CSR_SCALE_Pos)               /*!< 0x00000400 */
2448 #define CORDIC_CSR_IEN_Pos       (16U)
2449 #define CORDIC_CSR_IEN_Msk       (0x1UL << CORDIC_CSR_IEN_Pos)                 /*!< 0x00010000 */
2450 #define CORDIC_CSR_IEN           CORDIC_CSR_IEN_Msk                            /*!< Interrupt Enable */
2451 #define CORDIC_CSR_DMAREN_Pos    (17U)
2452 #define CORDIC_CSR_DMAREN_Msk    (0x1UL << CORDIC_CSR_DMAREN_Pos)              /*!< 0x00020000 */
2453 #define CORDIC_CSR_DMAREN        CORDIC_CSR_DMAREN_Msk                         /*!< DMA Read channel Enable */
2454 #define CORDIC_CSR_DMAWEN_Pos    (18U)
2455 #define CORDIC_CSR_DMAWEN_Msk    (0x1UL << CORDIC_CSR_DMAWEN_Pos)              /*!< 0x00040000 */
2456 #define CORDIC_CSR_DMAWEN        CORDIC_CSR_DMAWEN_Msk                         /*!< DMA Write channel Enable */
2457 #define CORDIC_CSR_NRES_Pos      (19U)
2458 #define CORDIC_CSR_NRES_Msk      (0x1UL << CORDIC_CSR_NRES_Pos)                /*!< 0x00080000 */
2459 #define CORDIC_CSR_NRES          CORDIC_CSR_NRES_Msk                           /*!< Number of results in WDATA register */
2460 #define CORDIC_CSR_NARGS_Pos     (20U)
2461 #define CORDIC_CSR_NARGS_Msk     (0x1UL << CORDIC_CSR_NARGS_Pos)               /*!< 0x00100000 */
2462 #define CORDIC_CSR_NARGS         CORDIC_CSR_NARGS_Msk                          /*!< Number of arguments in RDATA register */
2463 #define CORDIC_CSR_RESSIZE_Pos   (21U)
2464 #define CORDIC_CSR_RESSIZE_Msk   (0x1UL << CORDIC_CSR_RESSIZE_Pos)             /*!< 0x00200000 */
2465 #define CORDIC_CSR_RESSIZE       CORDIC_CSR_RESSIZE_Msk                        /*!< Width of output data */
2466 #define CORDIC_CSR_ARGSIZE_Pos   (22U)
2467 #define CORDIC_CSR_ARGSIZE_Msk   (0x1UL << CORDIC_CSR_ARGSIZE_Pos)             /*!< 0x00400000 */
2468 #define CORDIC_CSR_ARGSIZE       CORDIC_CSR_ARGSIZE_Msk                        /*!< Width of input data */
2469 #define CORDIC_CSR_RRDY_Pos      (31U)
2470 #define CORDIC_CSR_RRDY_Msk      (0x1UL << CORDIC_CSR_RRDY_Pos)                /*!< 0x80000000 */
2471 #define CORDIC_CSR_RRDY          CORDIC_CSR_RRDY_Msk                           /*!< Result Ready Flag */
2472 
2473 /*******************  Bit definition for CORDIC_WDATA register  ***************/
2474 #define CORDIC_WDATA_ARG_Pos     (0U)
2475 #define CORDIC_WDATA_ARG_Msk     (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos)        /*!< 0xFFFFFFFF */
2476 #define CORDIC_WDATA_ARG         CORDIC_WDATA_ARG_Msk                          /*!< Input Argument */
2477 
2478 /*******************  Bit definition for CORDIC_RDATA register  ***************/
2479 #define CORDIC_RDATA_RES_Pos     (0U)
2480 #define CORDIC_RDATA_RES_Msk     (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos)        /*!< 0xFFFFFFFF */
2481 #define CORDIC_RDATA_RES         CORDIC_RDATA_RES_Msk                          /*!< Output Result */
2482 
2483 /******************************************************************************/
2484 /*                                                                            */
2485 /*                          CRC calculation unit                              */
2486 /*                                                                            */
2487 /******************************************************************************/
2488 /*******************  Bit definition for CRC_DR register  *********************/
2489 #define CRC_DR_DR_Pos            (0U)
2490 #define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */
2491 #define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
2492 
2493 /*******************  Bit definition for CRC_IDR register  ********************/
2494 #define CRC_IDR_IDR_Pos          (0U)
2495 #define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)             /*!< 0xFFFFFFFF */
2496 #define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */
2497 
2498 /********************  Bit definition for CRC_CR register  ********************/
2499 #define CRC_CR_RESET_Pos         (0U)
2500 #define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */
2501 #define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
2502 #define CRC_CR_POLYSIZE_Pos      (3U)
2503 #define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */
2504 #define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
2505 #define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000008 */
2506 #define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000010 */
2507 #define CRC_CR_REV_IN_Pos        (5U)
2508 #define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */
2509 #define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
2510 #define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000020 */
2511 #define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000040 */
2512 #define CRC_CR_REV_OUT_Pos       (7U)
2513 #define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */
2514 #define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
2515 
2516 /*******************  Bit definition for CRC_INIT register  *******************/
2517 #define CRC_INIT_INIT_Pos        (0U)
2518 #define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */
2519 #define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
2520 
2521 /*******************  Bit definition for CRC_POL register  ********************/
2522 #define CRC_POL_POL_Pos          (0U)
2523 #define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */
2524 #define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
2525 
2526 /******************************************************************************/
2527 /*                                                                            */
2528 /*                          CRS Clock Recovery System                         */
2529 /******************************************************************************/
2530 
2531 /*******************  Bit definition for CRS_CR register  *********************/
2532 #define CRS_CR_SYNCOKIE_Pos       (0U)
2533 #define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */
2534 #define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */
2535 #define CRS_CR_SYNCWARNIE_Pos     (1U)
2536 #define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */
2537 #define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */
2538 #define CRS_CR_ERRIE_Pos          (2U)
2539 #define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */
2540 #define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */
2541 #define CRS_CR_ESYNCIE_Pos        (3U)
2542 #define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */
2543 #define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */
2544 #define CRS_CR_CEN_Pos            (5U)
2545 #define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */
2546 #define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */
2547 #define CRS_CR_AUTOTRIMEN_Pos     (6U)
2548 #define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */
2549 #define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */
2550 #define CRS_CR_SWSYNC_Pos         (7U)
2551 #define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */
2552 #define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */
2553 #define CRS_CR_TRIM_Pos           (8U)
2554 #define CRS_CR_TRIM_Msk           (0x7FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00007F00 */
2555 #define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */
2556 
2557 /*******************  Bit definition for CRS_CFGR register  *********************/
2558 #define CRS_CFGR_RELOAD_Pos       (0U)
2559 #define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */
2560 #define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */
2561 #define CRS_CFGR_FELIM_Pos        (16U)
2562 #define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */
2563 #define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */
2564 
2565 #define CRS_CFGR_SYNCDIV_Pos      (24U)
2566 #define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */
2567 #define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */
2568 #define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x01000000 */
2569 #define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x02000000 */
2570 #define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x04000000 */
2571 
2572 #define CRS_CFGR_SYNCSRC_Pos      (28U)
2573 #define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */
2574 #define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */
2575 #define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x10000000 */
2576 #define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x20000000 */
2577 
2578 #define CRS_CFGR_SYNCPOL_Pos      (31U)
2579 #define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */
2580 #define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */
2581 
2582 /*******************  Bit definition for CRS_ISR register  *********************/
2583 #define CRS_ISR_SYNCOKF_Pos       (0U)
2584 #define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */
2585 #define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */
2586 #define CRS_ISR_SYNCWARNF_Pos     (1U)
2587 #define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */
2588 #define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */
2589 #define CRS_ISR_ERRF_Pos          (2U)
2590 #define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */
2591 #define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */
2592 #define CRS_ISR_ESYNCF_Pos        (3U)
2593 #define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */
2594 #define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */
2595 #define CRS_ISR_SYNCERR_Pos       (8U)
2596 #define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */
2597 #define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */
2598 #define CRS_ISR_SYNCMISS_Pos      (9U)
2599 #define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */
2600 #define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */
2601 #define CRS_ISR_TRIMOVF_Pos       (10U)
2602 #define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */
2603 #define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */
2604 #define CRS_ISR_FEDIR_Pos         (15U)
2605 #define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */
2606 #define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */
2607 #define CRS_ISR_FECAP_Pos         (16U)
2608 #define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */
2609 #define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */
2610 
2611 /*******************  Bit definition for CRS_ICR register  *********************/
2612 #define CRS_ICR_SYNCOKC_Pos       (0U)
2613 #define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */
2614 #define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */
2615 #define CRS_ICR_SYNCWARNC_Pos     (1U)
2616 #define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */
2617 #define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */
2618 #define CRS_ICR_ERRC_Pos          (2U)
2619 #define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */
2620 #define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */
2621 #define CRS_ICR_ESYNCC_Pos        (3U)
2622 #define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */
2623 #define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */
2624 
2625 /******************************************************************************/
2626 /*                                                                            */
2627 /*                      Digital to Analog Converter                           */
2628 /*                                                                            */
2629 /******************************************************************************/
2630 /*
2631  * @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
2632  */
2633 #define DAC_CHANNEL2_SUPPORT                           /*!< DAC feature available only on specific devices: DAC channel 2 available */
2634 
2635 /********************  Bit definition for DAC_CR register  ********************/
2636 #define DAC_CR_EN1_Pos              (0U)
2637 #define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */
2638 #define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
2639 #define DAC_CR_TEN1_Pos             (1U)
2640 #define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */
2641 #define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
2642 
2643 #define DAC_CR_TSEL1_Pos            (2U)
2644 #define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */
2645 #define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
2646 #define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000004 */
2647 #define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000008 */
2648 #define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000010 */
2649 #define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000020 */
2650 
2651 #define DAC_CR_WAVE1_Pos            (6U)
2652 #define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */
2653 #define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
2654 #define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                /*!< 0x00000040 */
2655 #define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                /*!< 0x00000080 */
2656 
2657 #define DAC_CR_MAMP1_Pos            (8U)
2658 #define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */
2659 #define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
2660 #define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000100 */
2661 #define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000200 */
2662 #define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000400 */
2663 #define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000800 */
2664 
2665 #define DAC_CR_DMAEN1_Pos           (12U)
2666 #define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */
2667 #define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
2668 #define DAC_CR_DMAUDRIE1_Pos        (13U)
2669 #define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */
2670 #define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/
2671 #define DAC_CR_CEN1_Pos             (14U)
2672 #define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */
2673 #define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/
2674 
2675 #define DAC_CR_HFSEL_Pos            (15U)
2676 #define DAC_CR_HFSEL_Msk            (0x1UL << DAC_CR_HFSEL_Pos)                /*!< 0x00008000 */
2677 #define DAC_CR_HFSEL                DAC_CR_HFSEL_Msk                           /*!<DAC channel 1 and 2 high frequency mode enable >*/
2678 
2679 #define DAC_CR_EN2_Pos              (16U)
2680 #define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */
2681 #define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
2682 #define DAC_CR_TEN2_Pos             (17U)
2683 #define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */
2684 #define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
2685 
2686 #define DAC_CR_TSEL2_Pos            (18U)
2687 #define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */
2688 #define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[3:0] (DAC channel2 Trigger selection) */
2689 #define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                /*!< 0x00040000 */
2690 #define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                /*!< 0x00080000 */
2691 #define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                /*!< 0x00100000 */
2692 #define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                /*!< 0x00200000 */
2693 
2694 #define DAC_CR_WAVE2_Pos            (22U)
2695 #define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */
2696 #define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
2697 #define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                /*!< 0x00400000 */
2698 #define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                /*!< 0x00800000 */
2699 
2700 #define DAC_CR_MAMP2_Pos            (24U)
2701 #define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */
2702 #define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
2703 #define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                /*!< 0x01000000 */
2704 #define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                /*!< 0x02000000 */
2705 #define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                /*!< 0x04000000 */
2706 #define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                /*!< 0x08000000 */
2707 
2708 #define DAC_CR_DMAEN2_Pos           (28U)
2709 #define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */
2710 #define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
2711 #define DAC_CR_DMAUDRIE2_Pos        (29U)
2712 #define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */
2713 #define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/
2714 #define DAC_CR_CEN2_Pos             (30U)
2715 #define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */
2716 #define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/
2717 
2718 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
2719 #define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
2720 #define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */
2721 #define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
2722 #define DAC_SWTRIGR_SWTRIG2_Pos     (1U)
2723 #define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */
2724 #define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
2725 #define DAC_SWTRIGR_SWTRIGB1_Pos    (16U)
2726 #define DAC_SWTRIGR_SWTRIGB1_Msk    (0x1UL << DAC_SWTRIGR_SWTRIGB1_Pos)        /*!< 0x00010000 */
2727 #define DAC_SWTRIGR_SWTRIGB1        DAC_SWTRIGR_SWTRIGB1_Msk                   /*!<DAC channel1 software trigger B */
2728 #define DAC_SWTRIGR_SWTRIGB2_Pos    (17U)
2729 #define DAC_SWTRIGR_SWTRIGB2_Msk    (0x1UL << DAC_SWTRIGR_SWTRIGB2_Pos)        /*!< 0x00020000 */
2730 #define DAC_SWTRIGR_SWTRIGB2        DAC_SWTRIGR_SWTRIGB2_Msk                   /*!<DAC channel2 software trigger B */
2731 
2732 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
2733 #define DAC_DHR12R1_DACC1DHR_Pos    (0U)
2734 #define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */
2735 #define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
2736 #define DAC_DHR12R1_DACC1DHRB_Pos   (16U)
2737 #define DAC_DHR12R1_DACC1DHRB_Msk   (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos)     /*!< 0x0FFF0000 */
2738 #define DAC_DHR12R1_DACC1DHRB       DAC_DHR12R1_DACC1DHRB_Msk                  /*!<DAC channel1 12-bit Right-aligned data B */
2739 
2740 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
2741 #define DAC_DHR12L1_DACC1DHR_Pos    (4U)
2742 #define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
2743 #define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
2744 #define DAC_DHR12L1_DACC1DHRB_Pos   (20U)
2745 #define DAC_DHR12L1_DACC1DHRB_Msk   (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos)     /*!< 0xFFF00000 */
2746 #define DAC_DHR12L1_DACC1DHRB       DAC_DHR12L1_DACC1DHRB_Msk                  /*!<DAC channel1 12-bit Left aligned data B */
2747 
2748 /******************  Bit definition for DAC_DHR8R1 register  ******************/
2749 #define DAC_DHR8R1_DACC1DHR_Pos     (0U)
2750 #define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */
2751 #define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
2752 #define DAC_DHR8R1_DACC1DHRB_Pos    (8U)
2753 #define DAC_DHR8R1_DACC1DHRB_Msk    (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos)       /*!< 0x0000FF00 */
2754 #define DAC_DHR8R1_DACC1DHRB        DAC_DHR8R1_DACC1DHRB_Msk                   /*!<DAC channel1 8-bit Right aligned data B */
2755 
2756 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
2757 #define DAC_DHR12R2_DACC2DHR_Pos    (0U)
2758 #define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */
2759 #define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
2760 #define DAC_DHR12R2_DACC2DHRB_Pos   (16U)
2761 #define DAC_DHR12R2_DACC2DHRB_Msk   (0xFFFUL << DAC_DHR12R2_DACC2DHRB_Pos)     /*!< 0x0FFF0000 */
2762 #define DAC_DHR12R2_DACC2DHRB       DAC_DHR12R2_DACC2DHRB_Msk                  /*!<DAC channel2 12-bit Right-aligned data B */
2763 
2764 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
2765 #define DAC_DHR12L2_DACC2DHR_Pos    (4U)
2766 #define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */
2767 #define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
2768 #define DAC_DHR12L2_DACC2DHRB_Pos   (20U)
2769 #define DAC_DHR12L2_DACC2DHRB_Msk   (0xFFFUL << DAC_DHR12L2_DACC2DHRB_Pos)     /*!< 0xFFF00000 */
2770 #define DAC_DHR12L2_DACC2DHRB       DAC_DHR12L2_DACC2DHRB_Msk                  /*!<DAC channel2 12-bit Left aligned data B */
2771 
2772 /******************  Bit definition for DAC_DHR8R2 register  ******************/
2773 #define DAC_DHR8R2_DACC2DHR_Pos     (0U)
2774 #define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */
2775 #define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
2776 #define DAC_DHR8R2_DACC2DHRB_Pos    (8U)
2777 #define DAC_DHR8R2_DACC2DHRB_Msk    (0xFFUL << DAC_DHR8R2_DACC2DHRB_Pos)       /*!< 0x0000FF00 */
2778 #define DAC_DHR8R2_DACC2DHRB        DAC_DHR8R2_DACC2DHRB_Msk                   /*!<DAC channel2 8-bit Right aligned data B */
2779 
2780 /*****************  Bit definition for DAC_DHR12RD register  ******************/
2781 #define DAC_DHR12RD_DACC1DHR_Pos    (0U)
2782 #define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */
2783 #define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
2784 #define DAC_DHR12RD_DACC2DHR_Pos    (16U)
2785 #define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */
2786 #define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
2787 
2788 /*****************  Bit definition for DAC_DHR12LD register  ******************/
2789 #define DAC_DHR12LD_DACC1DHR_Pos    (4U)
2790 #define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
2791 #define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
2792 #define DAC_DHR12LD_DACC2DHR_Pos    (20U)
2793 #define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */
2794 #define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
2795 
2796 /******************  Bit definition for DAC_DHR8RD register  ******************/
2797 #define DAC_DHR8RD_DACC1DHR_Pos     (0U)
2798 #define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */
2799 #define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
2800 #define DAC_DHR8RD_DACC2DHR_Pos     (8U)
2801 #define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */
2802 #define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
2803 
2804 /*******************  Bit definition for DAC_DOR1 register  *******************/
2805 #define DAC_DOR1_DACC1DOR_Pos       (0U)
2806 #define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */
2807 #define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
2808 #define DAC_DOR1_DACC1DORB_Pos      (16U)
2809 #define DAC_DOR1_DACC1DORB_Msk      (0xFFFUL << DAC_DOR1_DACC1DORB_Pos)        /*!< 0x0FFF0000 */
2810 #define DAC_DOR1_DACC1DORB          DAC_DOR1_DACC1DORB_Msk                     /*!<DAC channel1 data output B */
2811 
2812 /*******************  Bit definition for DAC_DOR2 register  *******************/
2813 #define DAC_DOR2_DACC2DOR_Pos       (0U)
2814 #define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */
2815 #define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
2816 #define DAC_DOR2_DACC2DORB_Pos      (16U)
2817 #define DAC_DOR2_DACC2DORB_Msk      (0xFFFUL << DAC_DOR2_DACC2DORB_Pos)        /*!< 0x0FFF0000 */
2818 #define DAC_DOR2_DACC2DORB          DAC_DOR2_DACC2DORB_Msk                     /*!<DAC channel2 data output B */
2819 
2820 /********************  Bit definition for DAC_SR register  ********************/
2821 #define DAC_SR_DAC1RDY_Pos          (11U)
2822 #define DAC_SR_DAC1RDY_Msk          (0x1UL << DAC_SR_DAC1RDY_Pos)              /*!< 0x00000800 */
2823 #define DAC_SR_DAC1RDY              DAC_SR_DAC1RDY_Msk                         /*!<DAC channel 1 ready status bit */
2824 #define DAC_SR_DORSTAT1_Pos         (12U)
2825 #define DAC_SR_DORSTAT1_Msk         (0x1UL << DAC_SR_DORSTAT1_Pos)             /*!< 0x00001000 */
2826 #define DAC_SR_DORSTAT1             DAC_SR_DORSTAT1_Msk                        /*!<DAC channel 1 output register status bit */
2827 #define DAC_SR_DMAUDR1_Pos          (13U)
2828 #define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */
2829 #define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
2830 #define DAC_SR_CAL_FLAG1_Pos        (14U)
2831 #define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */
2832 #define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */
2833 #define DAC_SR_BWST1_Pos            (15U)
2834 #define DAC_SR_BWST1_Msk            (0x1UL << DAC_SR_BWST1_Pos)                /*!< 0x00008000 */
2835 #define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */
2836 
2837 #define DAC_SR_DAC2RDY_Pos          (27U)
2838 #define DAC_SR_DAC2RDY_Msk          (0x1UL << DAC_SR_DAC2RDY_Pos)              /*!< 0x08000000 */
2839 #define DAC_SR_DAC2RDY              DAC_SR_DAC2RDY_Msk                         /*!<DAC channel 2 ready status bit */
2840 #define DAC_SR_DORSTAT2_Pos         (28U)
2841 #define DAC_SR_DORSTAT2_Msk         (0x1UL << DAC_SR_DORSTAT2_Pos)             /*!< 0x10000000 */
2842 #define DAC_SR_DORSTAT2             DAC_SR_DORSTAT2_Msk                        /*!<DAC channel 2 output register status bit */
2843 #define DAC_SR_DMAUDR2_Pos          (29U)
2844 #define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */
2845 #define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
2846 #define DAC_SR_CAL_FLAG2_Pos        (30U)
2847 #define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */
2848 #define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */
2849 #define DAC_SR_BWST2_Pos            (31U)
2850 #define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */
2851 #define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */
2852 
2853 /*******************  Bit definition for DAC_CCR register  ********************/
2854 #define DAC_CCR_OTRIM1_Pos          (0U)
2855 #define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */
2856 #define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */
2857 #define DAC_CCR_OTRIM2_Pos          (16U)
2858 #define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */
2859 #define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */
2860 
2861 /*******************  Bit definition for DAC_MCR register  *******************/
2862 #define DAC_MCR_MODE1_Pos           (0U)
2863 #define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */
2864 #define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */
2865 #define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000001 */
2866 #define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000002 */
2867 #define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000004 */
2868 
2869 #define DAC_MCR_DMADOUBLE1_Pos      (8U)
2870 #define DAC_MCR_DMADOUBLE1_Msk      (0x1UL << DAC_MCR_DMADOUBLE1_Pos)          /*!< 0x00000100 */
2871 #define DAC_MCR_DMADOUBLE1          DAC_MCR_DMADOUBLE1_Msk                     /*!<DAC Channel 1 DMA double data mode */
2872 
2873 #define DAC_MCR_SINFORMAT1_Pos      (9U)
2874 #define DAC_MCR_SINFORMAT1_Msk      (0x1UL << DAC_MCR_SINFORMAT1_Pos)          /*!< 0x00000200 */
2875 #define DAC_MCR_SINFORMAT1          DAC_MCR_SINFORMAT1_Msk                     /*!<DAC Channel 1 enable signed format */
2876 
2877 #define DAC_MCR_HFSEL_Pos           (14U)
2878 #define DAC_MCR_HFSEL_Msk           (0x3UL << DAC_MCR_HFSEL_Pos)               /*!< 0x0000C000 */
2879 #define DAC_MCR_HFSEL               DAC_MCR_HFSEL_Msk                          /*!<HFSEL[1:0] (High Frequency interface mode selection) */
2880 #define DAC_MCR_HFSEL_0             (0x1UL << DAC_MCR_HFSEL_Pos)               /*!< 0x00004000 */
2881 #define DAC_MCR_HFSEL_1             (0x2UL << DAC_MCR_HFSEL_Pos)               /*!< 0x00008000 */
2882 
2883 #define DAC_MCR_MODE2_Pos           (16U)
2884 #define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */
2885 #define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */
2886 #define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)               /*!< 0x00010000 */
2887 #define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)               /*!< 0x00020000 */
2888 #define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)               /*!< 0x00040000 */
2889 
2890 #define DAC_MCR_DMADOUBLE2_Pos      (24U)
2891 #define DAC_MCR_DMADOUBLE2_Msk      (0x1UL << DAC_MCR_DMADOUBLE2_Pos)          /*!< 0x01000000 */
2892 #define DAC_MCR_DMADOUBLE2          DAC_MCR_DMADOUBLE2_Msk                     /*!<DAC Channel 2 DMA double data mode */
2893 
2894 #define DAC_MCR_SINFORMAT2_Pos      (25U)
2895 #define DAC_MCR_SINFORMAT2_Msk      (0x1UL << DAC_MCR_SINFORMAT2_Pos)          /*!< 0x02000000 */
2896 #define DAC_MCR_SINFORMAT2          DAC_MCR_SINFORMAT2_Msk                     /*!<DAC Channel 2 enable signed format */
2897 
2898 /******************  Bit definition for DAC_SHSR1 register  ******************/
2899 #define DAC_SHSR1_TSAMPLE1_Pos      (0U)
2900 #define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */
2901 #define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */
2902 
2903 /******************  Bit definition for DAC_SHSR2 register  ******************/
2904 #define DAC_SHSR2_TSAMPLE2_Pos      (0U)
2905 #define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */
2906 #define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */
2907 
2908 /******************  Bit definition for DAC_SHHR register  ******************/
2909 #define DAC_SHHR_THOLD1_Pos         (0U)
2910 #define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */
2911 #define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */
2912 #define DAC_SHHR_THOLD2_Pos         (16U)
2913 #define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */
2914 #define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */
2915 
2916 /******************  Bit definition for DAC_SHRR register  ******************/
2917 #define DAC_SHRR_TREFRESH1_Pos      (0U)
2918 #define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */
2919 #define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */
2920 #define DAC_SHRR_TREFRESH2_Pos      (16U)
2921 #define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */
2922 #define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */
2923 
2924 /******************  Bit definition for DAC_STR1 register  ******************/
2925 #define DAC_STR1_STRSTDATA1_Pos     (0U)
2926 #define DAC_STR1_STRSTDATA1_Msk     (0xFFFUL << DAC_STR1_STRSTDATA1_Pos)       /*!< 0x00000FFF */
2927 #define DAC_STR1_STRSTDATA1         DAC_STR1_STRSTDATA1_Msk                    /*!<DAC Channel 1 Sawtooth starting value */
2928 #define DAC_STR1_STDIR1_Pos         (12U)
2929 #define DAC_STR1_STDIR1_Msk         (0x1UL << DAC_STR1_STDIR1_Pos)             /*!< 0x00001000 */
2930 #define DAC_STR1_STDIR1             DAC_STR1_STDIR1_Msk                        /*!<DAC Channel 1 Sawtooth direction setting */
2931 
2932 #define DAC_STR1_STINCDATA1_Pos     (16U)
2933 #define DAC_STR1_STINCDATA1_Msk     (0xFFFFUL << DAC_STR1_STINCDATA1_Pos)      /*!< 0xFFFF0000 */
2934 #define DAC_STR1_STINCDATA1         DAC_STR1_STINCDATA1_Msk                    /*!<DAC Channel 1 Sawtooth increment value (12.4 bit format) */
2935 
2936 /******************  Bit definition for DAC_STR2 register  ******************/
2937 #define DAC_STR2_STRSTDATA2_Pos     (0U)
2938 #define DAC_STR2_STRSTDATA2_Msk     (0xFFFUL << DAC_STR2_STRSTDATA2_Pos)       /*!< 0x00000FFF */
2939 #define DAC_STR2_STRSTDATA2         DAC_STR2_STRSTDATA2_Msk                    /*!<DAC Channel 2 Sawtooth starting value */
2940 #define DAC_STR2_STDIR2_Pos         (12U)
2941 #define DAC_STR2_STDIR2_Msk         (0x1UL << DAC_STR2_STDIR2_Pos)             /*!< 0x00001000 */
2942 #define DAC_STR2_STDIR2             DAC_STR2_STDIR2_Msk                        /*!<DAC Channel 2 Sawtooth direction setting */
2943 
2944 #define DAC_STR2_STINCDATA2_Pos     (16U)
2945 #define DAC_STR2_STINCDATA2_Msk     (0xFFFFUL << DAC_STR2_STINCDATA2_Pos)      /*!< 0xFFFF0000 */
2946 #define DAC_STR2_STINCDATA2         DAC_STR2_STINCDATA2_Msk                    /*!<DAC Channel 2 Sawtooth increment value (12.4 bit format) */
2947 
2948 /******************  Bit definition for DAC_STMODR register  ****************/
2949 #define DAC_STMODR_STRSTTRIGSEL1_Pos (0U)
2950 #define DAC_STMODR_STRSTTRIGSEL1_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL1_Pos)   /*!< 0x0000000F */
2951 #define DAC_STMODR_STRSTTRIGSEL1     DAC_STMODR_STRSTTRIGSEL1_Msk              /*!<STRSTTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */
2952 #define DAC_STMODR_STRSTTRIGSEL1_0   (0x1UL << DAC_STMODR_STRSTTRIGSEL1_Pos)   /*!< 0x00000001 */
2953 #define DAC_STMODR_STRSTTRIGSEL1_1   (0x2UL << DAC_STMODR_STRSTTRIGSEL1_Pos)   /*!< 0x00000002 */
2954 #define DAC_STMODR_STRSTTRIGSEL1_2   (0x4UL << DAC_STMODR_STRSTTRIGSEL1_Pos)   /*!< 0x00000004 */
2955 #define DAC_STMODR_STRSTTRIGSEL1_3   (0x8UL << DAC_STMODR_STRSTTRIGSEL1_Pos)   /*!< 0x00000008 */
2956 
2957 #define DAC_STMODR_STINCTRIGSEL1_Pos (8U)
2958 #define DAC_STMODR_STINCTRIGSEL1_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL1_Pos)   /*!< 0x0000000F */
2959 #define DAC_STMODR_STINCTRIGSEL1     DAC_STMODR_STINCTRIGSEL1_Msk              /*!<STINCTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */
2960 #define DAC_STMODR_STINCTRIGSEL1_0   (0x1UL << DAC_STMODR_STINCTRIGSEL1_Pos)   /*!< 0x00000001 */
2961 #define DAC_STMODR_STINCTRIGSEL1_1   (0x2UL << DAC_STMODR_STINCTRIGSEL1_Pos)   /*!< 0x00000002 */
2962 #define DAC_STMODR_STINCTRIGSEL1_2   (0x4UL << DAC_STMODR_STINCTRIGSEL1_Pos)   /*!< 0x00000004 */
2963 #define DAC_STMODR_STINCTRIGSEL1_3   (0x8UL << DAC_STMODR_STINCTRIGSEL1_Pos)   /*!< 0x00000008 */
2964 
2965 #define DAC_STMODR_STRSTTRIGSEL2_Pos (16U)
2966 #define DAC_STMODR_STRSTTRIGSEL2_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL2_Pos)   /*!< 0x0000000F */
2967 #define DAC_STMODR_STRSTTRIGSEL2     DAC_STMODR_STRSTTRIGSEL2_Msk              /*!<STRSTTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */
2968 #define DAC_STMODR_STRSTTRIGSEL2_0   (0x1UL << DAC_STMODR_STRSTTRIGSEL2_Pos)   /*!< 0x00000001 */
2969 #define DAC_STMODR_STRSTTRIGSEL2_1   (0x2UL << DAC_STMODR_STRSTTRIGSEL2_Pos)   /*!< 0x00000002 */
2970 #define DAC_STMODR_STRSTTRIGSEL2_2   (0x4UL << DAC_STMODR_STRSTTRIGSEL2_Pos)   /*!< 0x00000004 */
2971 #define DAC_STMODR_STRSTTRIGSEL2_3   (0x8UL << DAC_STMODR_STRSTTRIGSEL2_Pos)   /*!< 0x00000008 */
2972 
2973 #define DAC_STMODR_STINCTRIGSEL2_Pos (24U)
2974 #define DAC_STMODR_STINCTRIGSEL2_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL2_Pos)   /*!< 0x0000000F */
2975 #define DAC_STMODR_STINCTRIGSEL2     DAC_STMODR_STINCTRIGSEL2_Msk              /*!<STINCTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */
2976 #define DAC_STMODR_STINCTRIGSEL2_0   (0x1UL << DAC_STMODR_STINCTRIGSEL2_Pos)   /*!< 0x00000001 */
2977 #define DAC_STMODR_STINCTRIGSEL2_1   (0x2UL << DAC_STMODR_STINCTRIGSEL2_Pos)   /*!< 0x00000002 */
2978 #define DAC_STMODR_STINCTRIGSEL2_2   (0x4UL << DAC_STMODR_STINCTRIGSEL2_Pos)   /*!< 0x00000004 */
2979 #define DAC_STMODR_STINCTRIGSEL2_3   (0x8UL << DAC_STMODR_STINCTRIGSEL2_Pos)   /*!< 0x00000008 */
2980 
2981 /******************************************************************************/
2982 /*                                                                            */
2983 /*                                 Debug MCU                                  */
2984 /*                                                                            */
2985 /******************************************************************************/
2986 /********************  Bit definition for DBGMCU_IDCODE register  *************/
2987 #define DBGMCU_IDCODE_DEV_ID_Pos               (0U)
2988 #define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)/*!< 0x00000FFF */
2989 #define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk
2990 #define DBGMCU_IDCODE_REV_ID_Pos               (16U)
2991 #define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)/*!< 0xFFFF0000 */
2992 #define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk
2993 
2994 /********************  Bit definition for DBGMCU_CR register  *****************/
2995 #define DBGMCU_CR_DBG_SLEEP_Pos                (0U)
2996 #define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)/*!< 0x00000001 */
2997 #define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk
2998 #define DBGMCU_CR_DBG_STOP_Pos                 (1U)
2999 #define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos)/*!< 0x00000002 */
3000 #define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk
3001 #define DBGMCU_CR_DBG_STANDBY_Pos              (2U)
3002 #define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)/*!< 0x00000004 */
3003 #define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk
3004 #define DBGMCU_CR_TRACE_IOEN_Pos               (5U)
3005 #define DBGMCU_CR_TRACE_IOEN_Msk               (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)/*!< 0x00000020 */
3006 #define DBGMCU_CR_TRACE_IOEN                   DBGMCU_CR_TRACE_IOEN_Msk
3007 
3008 #define DBGMCU_CR_TRACE_MODE_Pos               (6U)
3009 #define DBGMCU_CR_TRACE_MODE_Msk               (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x000000C0 */
3010 #define DBGMCU_CR_TRACE_MODE                   DBGMCU_CR_TRACE_MODE_Msk
3011 #define DBGMCU_CR_TRACE_MODE_0                 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000040 */
3012 #define DBGMCU_CR_TRACE_MODE_1                 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000080 */
3013 
3014 /********************  Bit definition for DBGMCU_APB1FZR1 register  ***********/
3015 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos      (0U)
3016 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)/*!< 0x00000001 */
3017 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP          DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
3018 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos      (1U)
3019 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos)/*!< 0x00000002 */
3020 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP          DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
3021 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos      (2U)
3022 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos)/*!< 0x00000004 */
3023 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP          DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
3024 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos      (3U)
3025 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos)/*!< 0x00000008 */
3026 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP          DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk
3027 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos      (4U)
3028 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)/*!< 0x00000010 */
3029 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP          DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
3030 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos      (5U)
3031 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos)/*!< 0x00000020 */
3032 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP          DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
3033 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos       (10U)
3034 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk       (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos)/*!< 0x00000400 */
3035 #define DBGMCU_APB1FZR1_DBG_RTC_STOP           DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
3036 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos      (11U)
3037 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)/*!< 0x00000800 */
3038 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP          DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
3039 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos      (12U)
3040 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)/*!< 0x00001000 */
3041 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP          DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
3042 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos      (21U)
3043 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)/*!< 0x00200000 */
3044 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP          DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
3045 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos      (22U)
3046 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)/*!< 0x00400000 */
3047 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP          DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
3048 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos      (30U)
3049 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos)/*!< 0x40000000 */
3050 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP          DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
3051 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos    (31U)
3052 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk    (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)/*!< 0x80000000 */
3053 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP        DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
3054 
3055 /********************  Bit definition for DBGMCU_APB1FZR2 register  **********/
3056 #define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos      (1U)
3057 #define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk      (0x1UL << DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos)/*!< 0x00000002 */
3058 #define DBGMCU_APB1FZR2_DBG_I2C4_STOP          DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk
3059 
3060 /********************  Bit definition for DBGMCU_APB2FZ register  ************/
3061 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos        (11U)
3062 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk        (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos)/*!< 0x00000800 */
3063 #define DBGMCU_APB2FZ_DBG_TIM1_STOP            DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
3064 #define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos        (13U)
3065 #define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk        (0x1UL << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos)/*!< 0x00002000 */
3066 #define DBGMCU_APB2FZ_DBG_TIM8_STOP            DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk
3067 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos       (16U)
3068 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos)/*!< 0x00010000 */
3069 #define DBGMCU_APB2FZ_DBG_TIM15_STOP           DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
3070 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos       (17U)
3071 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */
3072 #define DBGMCU_APB2FZ_DBG_TIM16_STOP           DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
3073 #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos       (18U)
3074 #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */
3075 #define DBGMCU_APB2FZ_DBG_TIM17_STOP           DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
3076 #define DBGMCU_APB2FZ_DBG_TIM20_STOP_Pos       (20U)
3077 #define DBGMCU_APB2FZ_DBG_TIM20_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM20_STOP_Pos)/*!< 0x00100000 */
3078 #define DBGMCU_APB2FZ_DBG_TIM20_STOP           DBGMCU_APB2FZ_DBG_TIM20_STOP_Msk
3079 
3080 /******************************************************************************/
3081 /*                                                                            */
3082 /*                           DMA Controller (DMA)                             */
3083 /*                                                                            */
3084 /******************************************************************************/
3085 
3086 /*******************  Bit definition for DMA_ISR register  ********************/
3087 #define DMA_ISR_GIF1_Pos       (0U)
3088 #define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                     /*!< 0x00000001 */
3089 #define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag */
3090 #define DMA_ISR_TCIF1_Pos      (1U)
3091 #define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                    /*!< 0x00000002 */
3092 #define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag */
3093 #define DMA_ISR_HTIF1_Pos      (2U)
3094 #define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                    /*!< 0x00000004 */
3095 #define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag */
3096 #define DMA_ISR_TEIF1_Pos      (3U)
3097 #define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                    /*!< 0x00000008 */
3098 #define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag */
3099 #define DMA_ISR_GIF2_Pos       (4U)
3100 #define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                     /*!< 0x00000010 */
3101 #define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag */
3102 #define DMA_ISR_TCIF2_Pos      (5U)
3103 #define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                    /*!< 0x00000020 */
3104 #define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag */
3105 #define DMA_ISR_HTIF2_Pos      (6U)
3106 #define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                    /*!< 0x00000040 */
3107 #define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag */
3108 #define DMA_ISR_TEIF2_Pos      (7U)
3109 #define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                    /*!< 0x00000080 */
3110 #define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag */
3111 #define DMA_ISR_GIF3_Pos       (8U)
3112 #define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                     /*!< 0x00000100 */
3113 #define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag */
3114 #define DMA_ISR_TCIF3_Pos      (9U)
3115 #define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                    /*!< 0x00000200 */
3116 #define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag */
3117 #define DMA_ISR_HTIF3_Pos      (10U)
3118 #define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                    /*!< 0x00000400 */
3119 #define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag */
3120 #define DMA_ISR_TEIF3_Pos      (11U)
3121 #define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                    /*!< 0x00000800 */
3122 #define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag */
3123 #define DMA_ISR_GIF4_Pos       (12U)
3124 #define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                     /*!< 0x00001000 */
3125 #define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag */
3126 #define DMA_ISR_TCIF4_Pos      (13U)
3127 #define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                    /*!< 0x00002000 */
3128 #define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag */
3129 #define DMA_ISR_HTIF4_Pos      (14U)
3130 #define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                    /*!< 0x00004000 */
3131 #define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag */
3132 #define DMA_ISR_TEIF4_Pos      (15U)
3133 #define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                    /*!< 0x00008000 */
3134 #define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag */
3135 #define DMA_ISR_GIF5_Pos       (16U)
3136 #define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                     /*!< 0x00010000 */
3137 #define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag */
3138 #define DMA_ISR_TCIF5_Pos      (17U)
3139 #define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                    /*!< 0x00020000 */
3140 #define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag */
3141 #define DMA_ISR_HTIF5_Pos      (18U)
3142 #define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                    /*!< 0x00040000 */
3143 #define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag */
3144 #define DMA_ISR_TEIF5_Pos      (19U)
3145 #define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                    /*!< 0x00080000 */
3146 #define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag */
3147 #define DMA_ISR_GIF6_Pos       (20U)
3148 #define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                     /*!< 0x00100000 */
3149 #define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
3150 #define DMA_ISR_TCIF6_Pos      (21U)
3151 #define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                    /*!< 0x00200000 */
3152 #define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
3153 #define DMA_ISR_HTIF6_Pos      (22U)
3154 #define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                    /*!< 0x00400000 */
3155 #define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
3156 #define DMA_ISR_TEIF6_Pos      (23U)
3157 #define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                    /*!< 0x00800000 */
3158 #define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
3159 #define DMA_ISR_GIF7_Pos       (24U)
3160 #define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                     /*!< 0x01000000 */
3161 #define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
3162 #define DMA_ISR_TCIF7_Pos      (25U)
3163 #define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                    /*!< 0x02000000 */
3164 #define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
3165 #define DMA_ISR_HTIF7_Pos      (26U)
3166 #define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                    /*!< 0x04000000 */
3167 #define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
3168 #define DMA_ISR_TEIF7_Pos      (27U)
3169 #define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                    /*!< 0x08000000 */
3170 #define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
3171 #define DMA_ISR_GIF8_Pos       (28U)
3172 #define DMA_ISR_GIF8_Msk       (0x1UL << DMA_ISR_GIF8_Pos)                     /*!< 0x10000000 */
3173 #define DMA_ISR_GIF8           DMA_ISR_GIF8_Msk                                /*!< Channel 8 Global interrupt flag */
3174 #define DMA_ISR_TCIF8_Pos      (29U)
3175 #define DMA_ISR_TCIF8_Msk      (0x1UL << DMA_ISR_TCIF8_Pos)                    /*!< 0x20000000 */
3176 #define DMA_ISR_TCIF8          DMA_ISR_TCIF8_Msk                               /*!< Channel 8 Transfer Complete flag */
3177 #define DMA_ISR_HTIF8_Pos      (30U)
3178 #define DMA_ISR_HTIF8_Msk      (0x1UL << DMA_ISR_HTIF8_Pos)                    /*!< 0x40000000 */
3179 #define DMA_ISR_HTIF8          DMA_ISR_HTIF8_Msk                               /*!< Channel 8 Half Transfer flag */
3180 #define DMA_ISR_TEIF8_Pos      (31U)
3181 #define DMA_ISR_TEIF8_Msk      (0x1UL << DMA_ISR_TEIF8_Pos)                    /*!< 0x80000000 */
3182 #define DMA_ISR_TEIF8          DMA_ISR_TEIF8_Msk                               /*!< Channel 8 Transfer Error flag */
3183 
3184 /*******************  Bit definition for DMA_IFCR register  *******************/
3185 #define DMA_IFCR_CGIF1_Pos     (0U)
3186 #define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                   /*!< 0x00000001 */
3187 #define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clearr */
3188 #define DMA_IFCR_CTCIF1_Pos    (1U)
3189 #define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                  /*!< 0x00000002 */
3190 #define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear */
3191 #define DMA_IFCR_CHTIF1_Pos    (2U)
3192 #define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                  /*!< 0x00000004 */
3193 #define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear */
3194 #define DMA_IFCR_CTEIF1_Pos    (3U)
3195 #define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                  /*!< 0x00000008 */
3196 #define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear */
3197 #define DMA_IFCR_CGIF2_Pos     (4U)
3198 #define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                   /*!< 0x00000010 */
3199 #define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear */
3200 #define DMA_IFCR_CTCIF2_Pos    (5U)
3201 #define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                  /*!< 0x00000020 */
3202 #define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear */
3203 #define DMA_IFCR_CHTIF2_Pos    (6U)
3204 #define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                  /*!< 0x00000040 */
3205 #define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear */
3206 #define DMA_IFCR_CTEIF2_Pos    (7U)
3207 #define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                  /*!< 0x00000080 */
3208 #define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear */
3209 #define DMA_IFCR_CGIF3_Pos     (8U)
3210 #define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                   /*!< 0x00000100 */
3211 #define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear */
3212 #define DMA_IFCR_CTCIF3_Pos    (9U)
3213 #define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                  /*!< 0x00000200 */
3214 #define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear */
3215 #define DMA_IFCR_CHTIF3_Pos    (10U)
3216 #define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                  /*!< 0x00000400 */
3217 #define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear */
3218 #define DMA_IFCR_CTEIF3_Pos    (11U)
3219 #define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                  /*!< 0x00000800 */
3220 #define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear */
3221 #define DMA_IFCR_CGIF4_Pos     (12U)
3222 #define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                   /*!< 0x00001000 */
3223 #define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear */
3224 #define DMA_IFCR_CTCIF4_Pos    (13U)
3225 #define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                  /*!< 0x00002000 */
3226 #define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear */
3227 #define DMA_IFCR_CHTIF4_Pos    (14U)
3228 #define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                  /*!< 0x00004000 */
3229 #define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear */
3230 #define DMA_IFCR_CTEIF4_Pos    (15U)
3231 #define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                  /*!< 0x00008000 */
3232 #define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear */
3233 #define DMA_IFCR_CGIF5_Pos     (16U)
3234 #define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                   /*!< 0x00010000 */
3235 #define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear */
3236 #define DMA_IFCR_CTCIF5_Pos    (17U)
3237 #define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                  /*!< 0x00020000 */
3238 #define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear */
3239 #define DMA_IFCR_CHTIF5_Pos    (18U)
3240 #define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                  /*!< 0x00040000 */
3241 #define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear */
3242 #define DMA_IFCR_CTEIF5_Pos    (19U)
3243 #define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                  /*!< 0x00080000 */
3244 #define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear */
3245 #define DMA_IFCR_CGIF6_Pos     (20U)
3246 #define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                   /*!< 0x00100000 */
3247 #define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
3248 #define DMA_IFCR_CTCIF6_Pos    (21U)
3249 #define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                  /*!< 0x00200000 */
3250 #define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
3251 #define DMA_IFCR_CHTIF6_Pos    (22U)
3252 #define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                  /*!< 0x00400000 */
3253 #define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
3254 #define DMA_IFCR_CTEIF6_Pos    (23U)
3255 #define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                  /*!< 0x00800000 */
3256 #define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
3257 #define DMA_IFCR_CGIF7_Pos     (24U)
3258 #define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                   /*!< 0x01000000 */
3259 #define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
3260 #define DMA_IFCR_CTCIF7_Pos    (25U)
3261 #define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                  /*!< 0x02000000 */
3262 #define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
3263 #define DMA_IFCR_CHTIF7_Pos    (26U)
3264 #define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                  /*!< 0x04000000 */
3265 #define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
3266 #define DMA_IFCR_CTEIF7_Pos    (27U)
3267 #define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                  /*!< 0x08000000 */
3268 #define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
3269 #define DMA_IFCR_CGIF8_Pos     (28U)
3270 #define DMA_IFCR_CGIF8_Msk     (0x1UL << DMA_IFCR_CGIF8_Pos)                   /*!< 0x10000000 */
3271 #define DMA_IFCR_CGIF8         DMA_IFCR_CGIF8_Msk                              /*!< Channel 8 Global interrupt clear */
3272 #define DMA_IFCR_CTCIF8_Pos    (29U)
3273 #define DMA_IFCR_CTCIF8_Msk    (0x1UL << DMA_IFCR_CTCIF8_Pos)                  /*!< 0x20000000 */
3274 #define DMA_IFCR_CTCIF8        DMA_IFCR_CTCIF8_Msk                             /*!< Channel 8 Transfer Complete clear */
3275 #define DMA_IFCR_CHTIF8_Pos    (30U)
3276 #define DMA_IFCR_CHTIF8_Msk    (0x1UL << DMA_IFCR_CHTIF8_Pos)                  /*!< 0x40000000 */
3277 #define DMA_IFCR_CHTIF8        DMA_IFCR_CHTIF8_Msk                             /*!< Channel 8 Half Transfer clear */
3278 #define DMA_IFCR_CTEIF8_Pos    (31U)
3279 #define DMA_IFCR_CTEIF8_Msk    (0x1UL << DMA_IFCR_CTEIF8_Pos)                  /*!< 0x80000000 */
3280 #define DMA_IFCR_CTEIF8        DMA_IFCR_CTEIF8_Msk                             /*!< Channel 8 Transfer Error clear */
3281 
3282 /*******************  Bit definition for DMA_CCR register  ********************/
3283 #define DMA_CCR_EN_Pos         (0U)
3284 #define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                       /*!< 0x00000001 */
3285 #define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
3286 #define DMA_CCR_TCIE_Pos       (1U)
3287 #define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                     /*!< 0x00000002 */
3288 #define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
3289 #define DMA_CCR_HTIE_Pos       (2U)
3290 #define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                     /*!< 0x00000004 */
3291 #define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
3292 #define DMA_CCR_TEIE_Pos       (3U)
3293 #define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                     /*!< 0x00000008 */
3294 #define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
3295 #define DMA_CCR_DIR_Pos        (4U)
3296 #define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                      /*!< 0x00000010 */
3297 #define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
3298 #define DMA_CCR_CIRC_Pos       (5U)
3299 #define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                     /*!< 0x00000020 */
3300 #define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
3301 #define DMA_CCR_PINC_Pos       (6U)
3302 #define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                     /*!< 0x00000040 */
3303 #define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
3304 #define DMA_CCR_MINC_Pos       (7U)
3305 #define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                     /*!< 0x00000080 */
3306 #define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
3307 
3308 #define DMA_CCR_PSIZE_Pos      (8U)
3309 #define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000300 */
3310 #define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
3311 #define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000100 */
3312 #define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000200 */
3313 
3314 #define DMA_CCR_MSIZE_Pos      (10U)
3315 #define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000C00 */
3316 #define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
3317 #define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000400 */
3318 #define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000800 */
3319 
3320 #define DMA_CCR_PL_Pos         (12U)
3321 #define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                       /*!< 0x00003000 */
3322 #define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
3323 #define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                       /*!< 0x00001000 */
3324 #define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                       /*!< 0x00002000 */
3325 
3326 #define DMA_CCR_MEM2MEM_Pos    (14U)
3327 #define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                  /*!< 0x00004000 */
3328 #define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
3329 
3330 /******************  Bit definition for DMA_CNDTR register  *******************/
3331 #define DMA_CNDTR_NDT_Pos      (0U)
3332 #define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                 /*!< 0x0000FFFF */
3333 #define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
3334 
3335 /******************  Bit definition for DMA_CPAR register  ********************/
3336 #define DMA_CPAR_PA_Pos        (0U)
3337 #define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)               /*!< 0xFFFFFFFF */
3338 #define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
3339 
3340 /******************  Bit definition for DMA_CMAR register  ********************/
3341 #define DMA_CMAR_MA_Pos        (0U)
3342 #define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)               /*!< 0xFFFFFFFF */
3343 #define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
3344 
3345 /******************************************************************************/
3346 /*                                                                            */
3347 /*                             DMAMUX Controller                              */
3348 /*                                                                            */
3349 /******************************************************************************/
3350 
3351 /********************  Bits definition for DMAMUX_CxCR register  **************/
3352 #define DMAMUX_CxCR_DMAREQ_ID_Pos                    (0U)
3353 #define DMAMUX_CxCR_DMAREQ_ID_Msk                    (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x000000FF */
3354 #define DMAMUX_CxCR_DMAREQ_ID                        DMAMUX_CxCR_DMAREQ_ID_Msk
3355 #define DMAMUX_CxCR_DMAREQ_ID_0                      (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000001 */
3356 #define DMAMUX_CxCR_DMAREQ_ID_1                      (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000002 */
3357 #define DMAMUX_CxCR_DMAREQ_ID_2                      (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000004 */
3358 #define DMAMUX_CxCR_DMAREQ_ID_3                      (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000008 */
3359 #define DMAMUX_CxCR_DMAREQ_ID_4                      (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000010 */
3360 #define DMAMUX_CxCR_DMAREQ_ID_5                      (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000020 */
3361 #define DMAMUX_CxCR_DMAREQ_ID_6                      (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000040 */
3362 #define DMAMUX_CxCR_DMAREQ_ID_7                      (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000080 */
3363 
3364 #define DMAMUX_CxCR_SOIE_Pos                         (8U)
3365 #define DMAMUX_CxCR_SOIE_Msk                         (0x1UL << DMAMUX_CxCR_SOIE_Pos)/*!< 0x00000100 */
3366 #define DMAMUX_CxCR_SOIE                             DMAMUX_CxCR_SOIE_Msk
3367 
3368 #define DMAMUX_CxCR_EGE_Pos                          (9U)
3369 #define DMAMUX_CxCR_EGE_Msk                          (0x1UL << DMAMUX_CxCR_EGE_Pos)/*!< 0x00000200 */
3370 #define DMAMUX_CxCR_EGE                              DMAMUX_CxCR_EGE_Msk
3371 
3372 #define DMAMUX_CxCR_SE_Pos                           (16U)
3373 #define DMAMUX_CxCR_SE_Msk                           (0x1UL << DMAMUX_CxCR_SE_Pos)/*!< 0x00010000 */
3374 #define DMAMUX_CxCR_SE                               DMAMUX_CxCR_SE_Msk
3375 
3376 #define DMAMUX_CxCR_SPOL_Pos                         (17U)
3377 #define DMAMUX_CxCR_SPOL_Msk                         (0x3UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00060000 */
3378 #define DMAMUX_CxCR_SPOL                             DMAMUX_CxCR_SPOL_Msk
3379 #define DMAMUX_CxCR_SPOL_0                           (0x1UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00020000 */
3380 #define DMAMUX_CxCR_SPOL_1                           (0x2UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00040000 */
3381 
3382 #define DMAMUX_CxCR_NBREQ_Pos                        (19U)
3383 #define DMAMUX_CxCR_NBREQ_Msk                        (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00F80000 */
3384 #define DMAMUX_CxCR_NBREQ                            DMAMUX_CxCR_NBREQ_Msk
3385 #define DMAMUX_CxCR_NBREQ_0                          (0x01UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00080000 */
3386 #define DMAMUX_CxCR_NBREQ_1                          (0x02UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00100000 */
3387 #define DMAMUX_CxCR_NBREQ_2                          (0x04UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00200000 */
3388 #define DMAMUX_CxCR_NBREQ_3                          (0x08UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00400000 */
3389 #define DMAMUX_CxCR_NBREQ_4                          (0x10UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00800000 */
3390 
3391 #define DMAMUX_CxCR_SYNC_ID_Pos                      (24U)
3392 #define DMAMUX_CxCR_SYNC_ID_Msk                      (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x1F000000 */
3393 #define DMAMUX_CxCR_SYNC_ID                          DMAMUX_CxCR_SYNC_ID_Msk
3394 #define DMAMUX_CxCR_SYNC_ID_0                        (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x01000000 */
3395 #define DMAMUX_CxCR_SYNC_ID_1                        (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x02000000 */
3396 #define DMAMUX_CxCR_SYNC_ID_2                        (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x04000000 */
3397 #define DMAMUX_CxCR_SYNC_ID_3                        (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x08000000 */
3398 #define DMAMUX_CxCR_SYNC_ID_4                        (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x10000000 */
3399 
3400 /********************  Bits definition for DMAMUX_CSR register  ****************/
3401 #define DMAMUX_CSR_SOF0_Pos                          (0U)
3402 #define DMAMUX_CSR_SOF0_Msk                          (0x1UL << DMAMUX_CSR_SOF0_Pos)/*!< 0x00000001 */
3403 #define DMAMUX_CSR_SOF0                              DMAMUX_CSR_SOF0_Msk
3404 #define DMAMUX_CSR_SOF1_Pos                          (1U)
3405 #define DMAMUX_CSR_SOF1_Msk                          (0x1UL << DMAMUX_CSR_SOF1_Pos)/*!< 0x00000002 */
3406 #define DMAMUX_CSR_SOF1                              DMAMUX_CSR_SOF1_Msk
3407 #define DMAMUX_CSR_SOF2_Pos                          (2U)
3408 #define DMAMUX_CSR_SOF2_Msk                          (0x1UL << DMAMUX_CSR_SOF2_Pos)/*!< 0x00000004 */
3409 #define DMAMUX_CSR_SOF2                              DMAMUX_CSR_SOF2_Msk
3410 #define DMAMUX_CSR_SOF3_Pos                          (3U)
3411 #define DMAMUX_CSR_SOF3_Msk                          (0x1UL << DMAMUX_CSR_SOF3_Pos)/*!< 0x00000008 */
3412 #define DMAMUX_CSR_SOF3                              DMAMUX_CSR_SOF3_Msk
3413 #define DMAMUX_CSR_SOF4_Pos                          (4U)
3414 #define DMAMUX_CSR_SOF4_Msk                          (0x1UL << DMAMUX_CSR_SOF4_Pos)/*!< 0x00000010 */
3415 #define DMAMUX_CSR_SOF4                              DMAMUX_CSR_SOF4_Msk
3416 #define DMAMUX_CSR_SOF5_Pos                          (5U)
3417 #define DMAMUX_CSR_SOF5_Msk                          (0x1UL << DMAMUX_CSR_SOF5_Pos)/*!< 0x00000020 */
3418 #define DMAMUX_CSR_SOF5                              DMAMUX_CSR_SOF5_Msk
3419 #define DMAMUX_CSR_SOF6_Pos                          (6U)
3420 #define DMAMUX_CSR_SOF6_Msk                          (0x1UL << DMAMUX_CSR_SOF6_Pos)/*!< 0x00000040 */
3421 #define DMAMUX_CSR_SOF6                              DMAMUX_CSR_SOF6_Msk
3422 #define DMAMUX_CSR_SOF7_Pos                          (7U)
3423 #define DMAMUX_CSR_SOF7_Msk                          (0x1UL << DMAMUX_CSR_SOF7_Pos)/*!< 0x00000080 */
3424 #define DMAMUX_CSR_SOF7                              DMAMUX_CSR_SOF7_Msk
3425 #define DMAMUX_CSR_SOF8_Pos                          (8U)
3426 #define DMAMUX_CSR_SOF8_Msk                          (0x1UL << DMAMUX_CSR_SOF8_Pos)/*!< 0x00000100 */
3427 #define DMAMUX_CSR_SOF8                              DMAMUX_CSR_SOF8_Msk
3428 #define DMAMUX_CSR_SOF9_Pos                          (9U)
3429 #define DMAMUX_CSR_SOF9_Msk                          (0x1UL << DMAMUX_CSR_SOF9_Pos)/*!< 0x00000200 */
3430 #define DMAMUX_CSR_SOF9                              DMAMUX_CSR_SOF9_Msk
3431 #define DMAMUX_CSR_SOF10_Pos                         (10U)
3432 #define DMAMUX_CSR_SOF10_Msk                         (0x1UL << DMAMUX_CSR_SOF10_Pos)/*!< 0x00000400 */
3433 #define DMAMUX_CSR_SOF10                             DMAMUX_CSR_SOF10_Msk
3434 #define DMAMUX_CSR_SOF11_Pos                         (11U)
3435 #define DMAMUX_CSR_SOF11_Msk                         (0x1UL << DMAMUX_CSR_SOF11_Pos)/*!< 0x00000800 */
3436 #define DMAMUX_CSR_SOF11                              DMAMUX_CSR_SOF11_Msk
3437 #define DMAMUX_CSR_SOF12_Pos                         (12U)
3438 #define DMAMUX_CSR_SOF12_Msk                         (0x1UL << DMAMUX_CSR_SOF12_Pos)/*!< 0x00001000 */
3439 #define DMAMUX_CSR_SOF12                             DMAMUX_CSR_SOF12_Msk
3440 #define DMAMUX_CSR_SOF13_Pos                         (13U)
3441 #define DMAMUX_CSR_SOF13_Msk                         (0x1UL << DMAMUX_CSR_SOF13_Pos)/*!< 0x00002000 */
3442 #define DMAMUX_CSR_SOF13                             DMAMUX_CSR_SOF13_Msk
3443 #define DMAMUX_CSR_SOF14_Pos                         (14U)
3444 #define DMAMUX_CSR_SOF14_Msk                         (0x1UL << DMAMUX_CSR_SOF14_Pos)/*!< 0x00004000 */
3445 #define DMAMUX_CSR_SOF14                             DMAMUX_CSR_SOF14_Msk
3446 #define DMAMUX_CSR_SOF15_Pos                         (15U)
3447 #define DMAMUX_CSR_SOF15_Msk                         (0x1UL << DMAMUX_CSR_SOF15_Pos)/*!< 0x00008000 */
3448 #define DMAMUX_CSR_SOF15                             DMAMUX_CSR_SOF15_Msk
3449 
3450 /********************  Bits definition for DMAMUX_CFR register  ****************/
3451 #define DMAMUX_CFR_CSOF0_Pos                         (0U)
3452 #define DMAMUX_CFR_CSOF0_Msk                         (0x1UL << DMAMUX_CFR_CSOF0_Pos)/*!< 0x00000001 */
3453 #define DMAMUX_CFR_CSOF0                             DMAMUX_CFR_CSOF0_Msk
3454 #define DMAMUX_CFR_CSOF1_Pos                         (1U)
3455 #define DMAMUX_CFR_CSOF1_Msk                         (0x1UL << DMAMUX_CFR_CSOF1_Pos)/*!< 0x00000002 */
3456 #define DMAMUX_CFR_CSOF1                             DMAMUX_CFR_CSOF1_Msk
3457 #define DMAMUX_CFR_CSOF2_Pos                         (2U)
3458 #define DMAMUX_CFR_CSOF2_Msk                         (0x1UL << DMAMUX_CFR_CSOF2_Pos)/*!< 0x00000004 */
3459 #define DMAMUX_CFR_CSOF2                             DMAMUX_CFR_CSOF2_Msk
3460 #define DMAMUX_CFR_CSOF3_Pos                         (3U)
3461 #define DMAMUX_CFR_CSOF3_Msk                         (0x1UL << DMAMUX_CFR_CSOF3_Pos)/*!< 0x00000008 */
3462 #define DMAMUX_CFR_CSOF3                             DMAMUX_CFR_CSOF3_Msk
3463 #define DMAMUX_CFR_CSOF4_Pos                         (4U)
3464 #define DMAMUX_CFR_CSOF4_Msk                         (0x1UL << DMAMUX_CFR_CSOF4_Pos)/*!< 0x00000010 */
3465 #define DMAMUX_CFR_CSOF4                             DMAMUX_CFR_CSOF4_Msk
3466 #define DMAMUX_CFR_CSOF5_Pos                         (5U)
3467 #define DMAMUX_CFR_CSOF5_Msk                         (0x1UL << DMAMUX_CFR_CSOF5_Pos)/*!< 0x00000020 */
3468 #define DMAMUX_CFR_CSOF5                             DMAMUX_CFR_CSOF5_Msk
3469 #define DMAMUX_CFR_CSOF6_Pos                         (6U)
3470 #define DMAMUX_CFR_CSOF6_Msk                         (0x1UL << DMAMUX_CFR_CSOF6_Pos)/*!< 0x00000040 */
3471 #define DMAMUX_CFR_CSOF6                             DMAMUX_CFR_CSOF6_Msk
3472 #define DMAMUX_CFR_CSOF7_Pos                         (7U)
3473 #define DMAMUX_CFR_CSOF7_Msk                         (0x1UL << DMAMUX_CFR_CSOF7_Pos)/*!< 0x00000080 */
3474 #define DMAMUX_CFR_CSOF7                             DMAMUX_CFR_CSOF7_Msk
3475 #define DMAMUX_CFR_CSOF8_Pos                         (8U)
3476 #define DMAMUX_CFR_CSOF8_Msk                         (0x1UL << DMAMUX_CFR_CSOF8_Pos)/*!< 0x00000100 */
3477 #define DMAMUX_CFR_CSOF8                             DMAMUX_CFR_CSOF8_Msk
3478 #define DMAMUX_CFR_CSOF9_Pos                         (9U)
3479 #define DMAMUX_CFR_CSOF9_Msk                         (0x1UL << DMAMUX_CFR_CSOF9_Pos)/*!< 0x00000200 */
3480 #define DMAMUX_CFR_CSOF9                             DMAMUX_CFR_CSOF9_Msk
3481 #define DMAMUX_CFR_CSOF10_Pos                        (10U)
3482 #define DMAMUX_CFR_CSOF10_Msk                        (0x1UL << DMAMUX_CFR_CSOF10_Pos)/*!< 0x00000400 */
3483 #define DMAMUX_CFR_CSOF10                            DMAMUX_CFR_CSOF10_Msk
3484 #define DMAMUX_CFR_CSOF11_Pos                        (11U)
3485 #define DMAMUX_CFR_CSOF11_Msk                        (0x1UL << DMAMUX_CFR_CSOF11_Pos)/*!< 0x00000800 */
3486 #define DMAMUX_CFR_CSOF11                            DMAMUX_CFR_CSOF11_Msk
3487 #define DMAMUX_CFR_CSOF12_Pos                        (12U)
3488 #define DMAMUX_CFR_CSOF12_Msk                        (0x1UL << DMAMUX_CFR_CSOF12_Pos)/*!< 0x00001000 */
3489 #define DMAMUX_CFR_CSOF12                            DMAMUX_CFR_CSOF12_Msk
3490 #define DMAMUX_CFR_CSOF13_Pos                        (13U)
3491 #define DMAMUX_CFR_CSOF13_Msk                        (0x1UL << DMAMUX_CFR_CSOF13_Pos)/*!< 0x00002000 */
3492 #define DMAMUX_CFR_CSOF13                            DMAMUX_CFR_CSOF13_Msk
3493 #define DMAMUX_CFR_CSOF14_Pos                        (14U)
3494 #define DMAMUX_CFR_CSOF14_Msk                        (0x1UL << DMAMUX_CFR_CSOF14_Pos)/*!< 0x00004000 */
3495 #define DMAMUX_CFR_CSOF14                            DMAMUX_CFR_CSOF14_Msk
3496 #define DMAMUX_CFR_CSOF15_Pos                        (15U)
3497 #define DMAMUX_CFR_CSOF15_Msk                        (0x1UL << DMAMUX_CFR_CSOF15_Pos)/*!< 0x00008000 */
3498 #define DMAMUX_CFR_CSOF15                            DMAMUX_CFR_CSOF15_Msk
3499 
3500 /********************  Bits definition for DMAMUX_RGxCR register  ************/
3501 #define DMAMUX_RGxCR_SIG_ID_Pos                      (0U)
3502 #define DMAMUX_RGxCR_SIG_ID_Msk                      (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x0000001F */
3503 #define DMAMUX_RGxCR_SIG_ID                          DMAMUX_RGxCR_SIG_ID_Msk
3504 #define DMAMUX_RGxCR_SIG_ID_0                        (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000001 */
3505 #define DMAMUX_RGxCR_SIG_ID_1                        (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000002 */
3506 #define DMAMUX_RGxCR_SIG_ID_2                        (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000004 */
3507 #define DMAMUX_RGxCR_SIG_ID_3                        (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000008 */
3508 #define DMAMUX_RGxCR_SIG_ID_4                        (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000010 */
3509 
3510 #define DMAMUX_RGxCR_OIE_Pos                         (8U)
3511 #define DMAMUX_RGxCR_OIE_Msk                         (0x1UL << DMAMUX_RGxCR_OIE_Pos)/*!< 0x00000100 */
3512 #define DMAMUX_RGxCR_OIE                             DMAMUX_RGxCR_OIE_Msk
3513 
3514 #define DMAMUX_RGxCR_GE_Pos                          (16U)
3515 #define DMAMUX_RGxCR_GE_Msk                          (0x1UL << DMAMUX_RGxCR_GE_Pos)/*!< 0x00010000 */
3516 #define DMAMUX_RGxCR_GE                              DMAMUX_RGxCR_GE_Msk
3517 
3518 #define DMAMUX_RGxCR_GPOL_Pos                        (17U)
3519 #define DMAMUX_RGxCR_GPOL_Msk                        (0x3UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00060000 */
3520 #define DMAMUX_RGxCR_GPOL                            DMAMUX_RGxCR_GPOL_Msk
3521 #define DMAMUX_RGxCR_GPOL_0                          (0x1UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00020000 */
3522 #define DMAMUX_RGxCR_GPOL_1                          (0x2UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00040000 */
3523 
3524 #define DMAMUX_RGxCR_GNBREQ_Pos                      (19U)
3525 #define DMAMUX_RGxCR_GNBREQ_Msk                      (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00F80000 */
3526 #define DMAMUX_RGxCR_GNBREQ                          DMAMUX_RGxCR_GNBREQ_Msk
3527 #define DMAMUX_RGxCR_GNBREQ_0                        (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00080000 */
3528 #define DMAMUX_RGxCR_GNBREQ_1                        (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00100000 */
3529 #define DMAMUX_RGxCR_GNBREQ_2                        (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00200000 */
3530 #define DMAMUX_RGxCR_GNBREQ_3                        (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00400000 */
3531 #define DMAMUX_RGxCR_GNBREQ_4                        (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00800000 */
3532 
3533 /********************  Bits definition for DMAMUX_RGSR register  **************/
3534 #define DMAMUX_RGSR_OF0_Pos                          (0U)
3535 #define DMAMUX_RGSR_OF0_Msk                          (0x1UL << DMAMUX_RGSR_OF0_Pos)/*!< 0x00000001 */
3536 #define DMAMUX_RGSR_OF0                              DMAMUX_RGSR_OF0_Msk
3537 #define DMAMUX_RGSR_OF1_Pos                          (1U)
3538 #define DMAMUX_RGSR_OF1_Msk                          (0x1UL << DMAMUX_RGSR_OF1_Pos)/*!< 0x00000002 */
3539 #define DMAMUX_RGSR_OF1                              DMAMUX_RGSR_OF1_Msk
3540 #define DMAMUX_RGSR_OF2_Pos                          (2U)
3541 #define DMAMUX_RGSR_OF2_Msk                          (0x1UL << DMAMUX_RGSR_OF2_Pos)/*!< 0x00000004 */
3542 #define DMAMUX_RGSR_OF2                              DMAMUX_RGSR_OF2_Msk
3543 #define DMAMUX_RGSR_OF3_Pos                          (3U)
3544 #define DMAMUX_RGSR_OF3_Msk                          (0x1UL << DMAMUX_RGSR_OF3_Pos)/*!< 0x00000008 */
3545 #define DMAMUX_RGSR_OF3                              DMAMUX_RGSR_OF3_Msk
3546 
3547 /********************  Bits definition for DMAMUX_RGCFR register  ************/
3548 #define DMAMUX_RGCFR_COF0_Pos                        (0U)
3549 #define DMAMUX_RGCFR_COF0_Msk                        (0x1UL << DMAMUX_RGCFR_COF0_Pos)/*!< 0x00000001 */
3550 #define DMAMUX_RGCFR_COF0                            DMAMUX_RGCFR_COF0_Msk
3551 #define DMAMUX_RGCFR_COF1_Pos                        (1U)
3552 #define DMAMUX_RGCFR_COF1_Msk                        (0x1UL << DMAMUX_RGCFR_COF1_Pos)/*!< 0x00000002 */
3553 #define DMAMUX_RGCFR_COF1                            DMAMUX_RGCFR_COF1_Msk
3554 #define DMAMUX_RGCFR_COF2_Pos                        (2U)
3555 #define DMAMUX_RGCFR_COF2_Msk                        (0x1UL << DMAMUX_RGCFR_COF2_Pos)/*!< 0x00000004 */
3556 #define DMAMUX_RGCFR_COF2                            DMAMUX_RGCFR_COF2_Msk
3557 #define DMAMUX_RGCFR_COF3_Pos                        (3U)
3558 #define DMAMUX_RGCFR_COF3_Msk                        (0x1UL << DMAMUX_RGCFR_COF3_Pos)/*!< 0x00000008 */
3559 #define DMAMUX_RGCFR_COF3                            DMAMUX_RGCFR_COF3_Msk
3560 
3561 /******************** Bits definition for DMAMUX_IPHW_CFGR2  ******************/
3562 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos       (0U)
3563 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos)/*!< 0x00000001 */
3564 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk
3565 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos       (1U)
3566 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos)/*!< 0x00000002 */
3567 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk
3568 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos       (2U)
3569 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos)/*!< 0x00000004 */
3570 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk
3571 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos       (3U)
3572 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos)/*!< 0x00000008 */
3573 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk
3574 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos       (4U)
3575 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos)/*!< 0x00000010 */
3576 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk
3577 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos       (5U)
3578 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos)/*!< 0x00000020 */
3579 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk
3580 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos       (6U)
3581 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos)/*!< 0x00000040 */
3582 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk
3583 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos       (7U)
3584 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos)/*!< 0x00000080 */
3585 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk
3586 
3587 /******************** Bits definition for DMAMUX_IPHW_CFGR1  ******************/
3588 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos       (0U)
3589 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos)/*!< 0x00000001 */
3590 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk
3591 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos       (1U)
3592 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos)/*!< 0x00000002 */
3593 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk
3594 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos       (2U)
3595 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos)/*!< 0x00000004 */
3596 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk
3597 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos       (3U)
3598 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos)/*!< 0x00000008 */
3599 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk
3600 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos       (4U)
3601 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos)/*!< 0x00000010 */
3602 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk
3603 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos       (5U)
3604 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos)/*!< 0x00000020 */
3605 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk
3606 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos       (6U)
3607 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos)/*!< 0x00000040 */
3608 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk
3609 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos       (7U)
3610 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos)/*!< 0x00000080 */
3611 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk
3612 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos    (8U)
3613 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos)/*!< 0x00000100 */
3614 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk
3615 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos    (9U)
3616 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos)/*!< 0x00000200 */
3617 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk
3618 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos    (10U)
3619 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos)/*!< 0x00000400 */
3620 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk
3621 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos    (11U)
3622 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos)/*!< 0x00000800 */
3623 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk
3624 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos    (12U)
3625 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos)/*!< 0x00001000 */
3626 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk
3627 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos    (13U)
3628 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos)/*!< 0x00002000 */
3629 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk
3630 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos    (14U)
3631 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos)/*!< 0x00004000 */
3632 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk
3633 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos    (15U)
3634 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos)/*!< 0x00008000 */
3635 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk
3636 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos          (16U)
3637 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos)/*!< 0x00010000 */
3638 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk
3639 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos          (17U)
3640 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos)/*!< 0x00020000 */
3641 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk
3642 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos          (18U)
3643 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos)/*!< 0x00040000 */
3644 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk
3645 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos          (19U)
3646 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos)/*!< 0x00080000 */
3647 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk
3648 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos          (20U)
3649 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos)/*!< 0x00100000 */
3650 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk
3651 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos          (21U)
3652 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos)/*!< 0x00200000 */
3653 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk
3654 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos          (22U)
3655 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos)/*!< 0x00400000 */
3656 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk
3657 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos          (23U)
3658 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos)/*!< 0x00800000 */
3659 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk
3660 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos        (24U)
3661 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos)/*!< 0x01000000 */
3662 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk
3663 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos        (25U)
3664 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos)/*!< 0x02000000 */
3665 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk
3666 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos        (26U)
3667 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos)/*!< 0x04000000 */
3668 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk
3669 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos        (27U)
3670 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos)/*!< 0x08000000 */
3671 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk
3672 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos        (28U)
3673 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos)/*!< 0x10000000 */
3674 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk
3675 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos        (29U)
3676 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos)/*!< 0x20000000 */
3677 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk
3678 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos        (30U)
3679 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos)/*!< 0x40000000 */
3680 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk
3681 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos        (31U)
3682 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos)/*!< 0x80000000 */
3683 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk
3684 
3685 
3686 /******************************************************************************/
3687 /*                                                                            */
3688 /*                    External Interrupt/Event Controller                     */
3689 /*                                                                            */
3690 /******************************************************************************/
3691 /*******************  Bit definition for EXTI_IMR1 register  ******************/
3692 #define EXTI_IMR1_IM0_Pos        (0U)
3693 #define EXTI_IMR1_IM0_Msk        (0x1UL << EXTI_IMR1_IM0_Pos)                  /*!< 0x00000001 */
3694 #define EXTI_IMR1_IM0            EXTI_IMR1_IM0_Msk                             /*!< Interrupt Mask on line 0 */
3695 #define EXTI_IMR1_IM1_Pos        (1U)
3696 #define EXTI_IMR1_IM1_Msk        (0x1UL << EXTI_IMR1_IM1_Pos)                  /*!< 0x00000002 */
3697 #define EXTI_IMR1_IM1            EXTI_IMR1_IM1_Msk                             /*!< Interrupt Mask on line 1 */
3698 #define EXTI_IMR1_IM2_Pos        (2U)
3699 #define EXTI_IMR1_IM2_Msk        (0x1UL << EXTI_IMR1_IM2_Pos)                  /*!< 0x00000004 */
3700 #define EXTI_IMR1_IM2            EXTI_IMR1_IM2_Msk                             /*!< Interrupt Mask on line 2 */
3701 #define EXTI_IMR1_IM3_Pos        (3U)
3702 #define EXTI_IMR1_IM3_Msk        (0x1UL << EXTI_IMR1_IM3_Pos)                  /*!< 0x00000008 */
3703 #define EXTI_IMR1_IM3            EXTI_IMR1_IM3_Msk                             /*!< Interrupt Mask on line 3 */
3704 #define EXTI_IMR1_IM4_Pos        (4U)
3705 #define EXTI_IMR1_IM4_Msk        (0x1UL << EXTI_IMR1_IM4_Pos)                  /*!< 0x00000010 */
3706 #define EXTI_IMR1_IM4            EXTI_IMR1_IM4_Msk                             /*!< Interrupt Mask on line 4 */
3707 #define EXTI_IMR1_IM5_Pos        (5U)
3708 #define EXTI_IMR1_IM5_Msk        (0x1UL << EXTI_IMR1_IM5_Pos)                  /*!< 0x00000020 */
3709 #define EXTI_IMR1_IM5            EXTI_IMR1_IM5_Msk                             /*!< Interrupt Mask on line 5 */
3710 #define EXTI_IMR1_IM6_Pos        (6U)
3711 #define EXTI_IMR1_IM6_Msk        (0x1UL << EXTI_IMR1_IM6_Pos)                  /*!< 0x00000040 */
3712 #define EXTI_IMR1_IM6            EXTI_IMR1_IM6_Msk                             /*!< Interrupt Mask on line 6 */
3713 #define EXTI_IMR1_IM7_Pos        (7U)
3714 #define EXTI_IMR1_IM7_Msk        (0x1UL << EXTI_IMR1_IM7_Pos)                  /*!< 0x00000080 */
3715 #define EXTI_IMR1_IM7            EXTI_IMR1_IM7_Msk                             /*!< Interrupt Mask on line 7 */
3716 #define EXTI_IMR1_IM8_Pos        (8U)
3717 #define EXTI_IMR1_IM8_Msk        (0x1UL << EXTI_IMR1_IM8_Pos)                  /*!< 0x00000100 */
3718 #define EXTI_IMR1_IM8            EXTI_IMR1_IM8_Msk                             /*!< Interrupt Mask on line 8 */
3719 #define EXTI_IMR1_IM9_Pos        (9U)
3720 #define EXTI_IMR1_IM9_Msk        (0x1UL << EXTI_IMR1_IM9_Pos)                  /*!< 0x00000200 */
3721 #define EXTI_IMR1_IM9            EXTI_IMR1_IM9_Msk                             /*!< Interrupt Mask on line 9 */
3722 #define EXTI_IMR1_IM10_Pos       (10U)
3723 #define EXTI_IMR1_IM10_Msk       (0x1UL << EXTI_IMR1_IM10_Pos)                 /*!< 0x00000400 */
3724 #define EXTI_IMR1_IM10           EXTI_IMR1_IM10_Msk                            /*!< Interrupt Mask on line 10 */
3725 #define EXTI_IMR1_IM11_Pos       (11U)
3726 #define EXTI_IMR1_IM11_Msk       (0x1UL << EXTI_IMR1_IM11_Pos)                 /*!< 0x00000800 */
3727 #define EXTI_IMR1_IM11           EXTI_IMR1_IM11_Msk                            /*!< Interrupt Mask on line 11 */
3728 #define EXTI_IMR1_IM12_Pos       (12U)
3729 #define EXTI_IMR1_IM12_Msk       (0x1UL << EXTI_IMR1_IM12_Pos)                 /*!< 0x00001000 */
3730 #define EXTI_IMR1_IM12           EXTI_IMR1_IM12_Msk                            /*!< Interrupt Mask on line 12 */
3731 #define EXTI_IMR1_IM13_Pos       (13U)
3732 #define EXTI_IMR1_IM13_Msk       (0x1UL << EXTI_IMR1_IM13_Pos)                 /*!< 0x00002000 */
3733 #define EXTI_IMR1_IM13           EXTI_IMR1_IM13_Msk                            /*!< Interrupt Mask on line 13 */
3734 #define EXTI_IMR1_IM14_Pos       (14U)
3735 #define EXTI_IMR1_IM14_Msk       (0x1UL << EXTI_IMR1_IM14_Pos)                 /*!< 0x00004000 */
3736 #define EXTI_IMR1_IM14           EXTI_IMR1_IM14_Msk                            /*!< Interrupt Mask on line 14 */
3737 #define EXTI_IMR1_IM15_Pos       (15U)
3738 #define EXTI_IMR1_IM15_Msk       (0x1UL << EXTI_IMR1_IM15_Pos)                 /*!< 0x00008000 */
3739 #define EXTI_IMR1_IM15           EXTI_IMR1_IM15_Msk                            /*!< Interrupt Mask on line 15 */
3740 #define EXTI_IMR1_IM16_Pos       (16U)
3741 #define EXTI_IMR1_IM16_Msk       (0x1UL << EXTI_IMR1_IM16_Pos)                 /*!< 0x00010000 */
3742 #define EXTI_IMR1_IM16           EXTI_IMR1_IM16_Msk                            /*!< Interrupt Mask on line 16 */
3743 #define EXTI_IMR1_IM17_Pos       (17U)
3744 #define EXTI_IMR1_IM17_Msk       (0x1UL << EXTI_IMR1_IM17_Pos)                 /*!< 0x00020000 */
3745 #define EXTI_IMR1_IM17           EXTI_IMR1_IM17_Msk                            /*!< Interrupt Mask on line 17 */
3746 #define EXTI_IMR1_IM18_Pos       (18U)
3747 #define EXTI_IMR1_IM18_Msk       (0x1UL << EXTI_IMR1_IM18_Pos)                 /*!< 0x00040000 */
3748 #define EXTI_IMR1_IM18           EXTI_IMR1_IM18_Msk                            /*!< Interrupt Mask on line 18 */
3749 #define EXTI_IMR1_IM19_Pos       (19U)
3750 #define EXTI_IMR1_IM19_Msk       (0x1UL << EXTI_IMR1_IM19_Pos)                 /*!< 0x00080000 */
3751 #define EXTI_IMR1_IM19           EXTI_IMR1_IM19_Msk                            /*!< Interrupt Mask on line 19 */
3752 #define EXTI_IMR1_IM20_Pos       (20U)
3753 #define EXTI_IMR1_IM20_Msk       (0x1UL << EXTI_IMR1_IM20_Pos)                 /*!< 0x00100000 */
3754 #define EXTI_IMR1_IM20           EXTI_IMR1_IM20_Msk                            /*!< Interrupt Mask on line 20 */
3755 #define EXTI_IMR1_IM21_Pos       (21U)
3756 #define EXTI_IMR1_IM21_Msk       (0x1UL << EXTI_IMR1_IM21_Pos)                 /*!< 0x00200000 */
3757 #define EXTI_IMR1_IM21           EXTI_IMR1_IM21_Msk                            /*!< Interrupt Mask on line 21 */
3758 #define EXTI_IMR1_IM22_Pos       (22U)
3759 #define EXTI_IMR1_IM22_Msk       (0x1UL << EXTI_IMR1_IM22_Pos)                 /*!< 0x00400000 */
3760 #define EXTI_IMR1_IM22           EXTI_IMR1_IM22_Msk                            /*!< Interrupt Mask on line 22 */
3761 #define EXTI_IMR1_IM23_Pos       (23U)
3762 #define EXTI_IMR1_IM23_Msk       (0x1UL << EXTI_IMR1_IM23_Pos)                 /*!< 0x00800000 */
3763 #define EXTI_IMR1_IM23           EXTI_IMR1_IM23_Msk                            /*!< Interrupt Mask on line 23 */
3764 #define EXTI_IMR1_IM24_Pos       (24U)
3765 #define EXTI_IMR1_IM24_Msk       (0x1UL << EXTI_IMR1_IM24_Pos)                 /*!< 0x01000000 */
3766 #define EXTI_IMR1_IM24           EXTI_IMR1_IM24_Msk                            /*!< Interrupt Mask on line 24 */
3767 #define EXTI_IMR1_IM25_Pos       (25U)
3768 #define EXTI_IMR1_IM25_Msk       (0x1UL << EXTI_IMR1_IM25_Pos)                 /*!< 0x02000000 */
3769 #define EXTI_IMR1_IM25           EXTI_IMR1_IM25_Msk                            /*!< Interrupt Mask on line 25 */
3770 #define EXTI_IMR1_IM26_Pos       (26U)
3771 #define EXTI_IMR1_IM26_Msk       (0x1UL << EXTI_IMR1_IM26_Pos)                 /*!< 0x04000000 */
3772 #define EXTI_IMR1_IM26           EXTI_IMR1_IM26_Msk                            /*!< Interrupt Mask on line 26 */
3773 #define EXTI_IMR1_IM27_Pos       (27U)
3774 #define EXTI_IMR1_IM27_Msk       (0x1UL << EXTI_IMR1_IM27_Pos)                 /*!< 0x08000000 */
3775 #define EXTI_IMR1_IM27           EXTI_IMR1_IM27_Msk                            /*!< Interrupt Mask on line 27 */
3776 #define EXTI_IMR1_IM28_Pos       (28U)
3777 #define EXTI_IMR1_IM28_Msk       (0x1UL << EXTI_IMR1_IM28_Pos)                 /*!< 0x10000000 */
3778 #define EXTI_IMR1_IM28           EXTI_IMR1_IM28_Msk                            /*!< Interrupt Mask on line 28 */
3779 #define EXTI_IMR1_IM29_Pos       (29U)
3780 #define EXTI_IMR1_IM29_Msk       (0x1UL << EXTI_IMR1_IM29_Pos)                 /*!< 0x20000000 */
3781 #define EXTI_IMR1_IM29           EXTI_IMR1_IM29_Msk                            /*!< Interrupt Mask on line 29 */
3782 #define EXTI_IMR1_IM30_Pos       (30U)
3783 #define EXTI_IMR1_IM30_Msk       (0x1UL << EXTI_IMR1_IM30_Pos)                 /*!< 0x40000000 */
3784 #define EXTI_IMR1_IM30           EXTI_IMR1_IM30_Msk                            /*!< Interrupt Mask on line 30 */
3785 #define EXTI_IMR1_IM31_Pos       (31U)
3786 #define EXTI_IMR1_IM31_Msk       (0x1UL << EXTI_IMR1_IM31_Pos)                 /*!< 0x80000000 */
3787 #define EXTI_IMR1_IM31           EXTI_IMR1_IM31_Msk                            /*!< Interrupt Mask on line 31 */
3788 #define EXTI_IMR1_IM_Pos         (0U)
3789 #define EXTI_IMR1_IM_Msk         (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)            /*!< 0xFFFFFFFF */
3790 #define EXTI_IMR1_IM             EXTI_IMR1_IM_Msk                              /*!< Interrupt Mask All */
3791 
3792 /*******************  Bit definition for EXTI_EMR1 register  ******************/
3793 #define EXTI_EMR1_EM0_Pos        (0U)
3794 #define EXTI_EMR1_EM0_Msk        (0x1UL << EXTI_EMR1_EM0_Pos)                  /*!< 0x00000001 */
3795 #define EXTI_EMR1_EM0            EXTI_EMR1_EM0_Msk                             /*!< Event Mask on line 0 */
3796 #define EXTI_EMR1_EM1_Pos        (1U)
3797 #define EXTI_EMR1_EM1_Msk        (0x1UL << EXTI_EMR1_EM1_Pos)                  /*!< 0x00000002 */
3798 #define EXTI_EMR1_EM1            EXTI_EMR1_EM1_Msk                             /*!< Event Mask on line 1 */
3799 #define EXTI_EMR1_EM2_Pos        (2U)
3800 #define EXTI_EMR1_EM2_Msk        (0x1UL << EXTI_EMR1_EM2_Pos)                  /*!< 0x00000004 */
3801 #define EXTI_EMR1_EM2            EXTI_EMR1_EM2_Msk                             /*!< Event Mask on line 2 */
3802 #define EXTI_EMR1_EM3_Pos        (3U)
3803 #define EXTI_EMR1_EM3_Msk        (0x1UL << EXTI_EMR1_EM3_Pos)                  /*!< 0x00000008 */
3804 #define EXTI_EMR1_EM3            EXTI_EMR1_EM3_Msk                             /*!< Event Mask on line 3 */
3805 #define EXTI_EMR1_EM4_Pos        (4U)
3806 #define EXTI_EMR1_EM4_Msk        (0x1UL << EXTI_EMR1_EM4_Pos)                  /*!< 0x00000010 */
3807 #define EXTI_EMR1_EM4            EXTI_EMR1_EM4_Msk                             /*!< Event Mask on line 4 */
3808 #define EXTI_EMR1_EM5_Pos        (5U)
3809 #define EXTI_EMR1_EM5_Msk        (0x1UL << EXTI_EMR1_EM5_Pos)                  /*!< 0x00000020 */
3810 #define EXTI_EMR1_EM5            EXTI_EMR1_EM5_Msk                             /*!< Event Mask on line 5 */
3811 #define EXTI_EMR1_EM6_Pos        (6U)
3812 #define EXTI_EMR1_EM6_Msk        (0x1UL << EXTI_EMR1_EM6_Pos)                  /*!< 0x00000040 */
3813 #define EXTI_EMR1_EM6            EXTI_EMR1_EM6_Msk                             /*!< Event Mask on line 6 */
3814 #define EXTI_EMR1_EM7_Pos        (7U)
3815 #define EXTI_EMR1_EM7_Msk        (0x1UL << EXTI_EMR1_EM7_Pos)                  /*!< 0x00000080 */
3816 #define EXTI_EMR1_EM7            EXTI_EMR1_EM7_Msk                             /*!< Event Mask on line 7 */
3817 #define EXTI_EMR1_EM8_Pos        (8U)
3818 #define EXTI_EMR1_EM8_Msk        (0x1UL << EXTI_EMR1_EM8_Pos)                  /*!< 0x00000100 */
3819 #define EXTI_EMR1_EM8            EXTI_EMR1_EM8_Msk                             /*!< Event Mask on line 8 */
3820 #define EXTI_EMR1_EM9_Pos        (9U)
3821 #define EXTI_EMR1_EM9_Msk        (0x1UL << EXTI_EMR1_EM9_Pos)                  /*!< 0x00000200 */
3822 #define EXTI_EMR1_EM9            EXTI_EMR1_EM9_Msk                             /*!< Event Mask on line 9 */
3823 #define EXTI_EMR1_EM10_Pos       (10U)
3824 #define EXTI_EMR1_EM10_Msk       (0x1UL << EXTI_EMR1_EM10_Pos)                 /*!< 0x00000400 */
3825 #define EXTI_EMR1_EM10           EXTI_EMR1_EM10_Msk                            /*!< Event Mask on line 10 */
3826 #define EXTI_EMR1_EM11_Pos       (11U)
3827 #define EXTI_EMR1_EM11_Msk       (0x1UL << EXTI_EMR1_EM11_Pos)                 /*!< 0x00000800 */
3828 #define EXTI_EMR1_EM11           EXTI_EMR1_EM11_Msk                            /*!< Event Mask on line 11 */
3829 #define EXTI_EMR1_EM12_Pos       (12U)
3830 #define EXTI_EMR1_EM12_Msk       (0x1UL << EXTI_EMR1_EM12_Pos)                 /*!< 0x00001000 */
3831 #define EXTI_EMR1_EM12           EXTI_EMR1_EM12_Msk                            /*!< Event Mask on line 12 */
3832 #define EXTI_EMR1_EM13_Pos       (13U)
3833 #define EXTI_EMR1_EM13_Msk       (0x1UL << EXTI_EMR1_EM13_Pos)                 /*!< 0x00002000 */
3834 #define EXTI_EMR1_EM13           EXTI_EMR1_EM13_Msk                            /*!< Event Mask on line 13 */
3835 #define EXTI_EMR1_EM14_Pos       (14U)
3836 #define EXTI_EMR1_EM14_Msk       (0x1UL << EXTI_EMR1_EM14_Pos)                 /*!< 0x00004000 */
3837 #define EXTI_EMR1_EM14           EXTI_EMR1_EM14_Msk                            /*!< Event Mask on line 14 */
3838 #define EXTI_EMR1_EM15_Pos       (15U)
3839 #define EXTI_EMR1_EM15_Msk       (0x1UL << EXTI_EMR1_EM15_Pos)                 /*!< 0x00008000 */
3840 #define EXTI_EMR1_EM15           EXTI_EMR1_EM15_Msk                            /*!< Event Mask on line 15 */
3841 #define EXTI_EMR1_EM16_Pos       (16U)
3842 #define EXTI_EMR1_EM16_Msk       (0x1UL << EXTI_EMR1_EM16_Pos)                 /*!< 0x00010000 */
3843 #define EXTI_EMR1_EM16           EXTI_EMR1_EM16_Msk                            /*!< Event Mask on line 16 */
3844 #define EXTI_EMR1_EM17_Pos       (17U)
3845 #define EXTI_EMR1_EM17_Msk       (0x1UL << EXTI_EMR1_EM17_Pos)                 /*!< 0x00020000 */
3846 #define EXTI_EMR1_EM17           EXTI_EMR1_EM17_Msk                            /*!< Event Mask on line 17 */
3847 #define EXTI_EMR1_EM18_Pos       (18U)
3848 #define EXTI_EMR1_EM18_Msk       (0x1UL << EXTI_EMR1_EM18_Pos)                 /*!< 0x00040000 */
3849 #define EXTI_EMR1_EM18           EXTI_EMR1_EM18_Msk                            /*!< Event Mask on line 18 */
3850 #define EXTI_EMR1_EM19_Pos       (19U)
3851 #define EXTI_EMR1_EM19_Msk       (0x1UL << EXTI_EMR1_EM19_Pos)                 /*!< 0x00080000 */
3852 #define EXTI_EMR1_EM19           EXTI_EMR1_EM19_Msk                            /*!< Event Mask on line 19 */
3853 #define EXTI_EMR1_EM20_Pos       (20U)
3854 #define EXTI_EMR1_EM20_Msk       (0x1UL << EXTI_EMR1_EM20_Pos)                 /*!< 0x00100000 */
3855 #define EXTI_EMR1_EM20           EXTI_EMR1_EM20_Msk                            /*!< Event Mask on line 20 */
3856 #define EXTI_EMR1_EM21_Pos       (21U)
3857 #define EXTI_EMR1_EM21_Msk       (0x1UL << EXTI_EMR1_EM21_Pos)                 /*!< 0x00200000 */
3858 #define EXTI_EMR1_EM21           EXTI_EMR1_EM21_Msk                            /*!< Event Mask on line 21 */
3859 #define EXTI_EMR1_EM22_Pos       (22U)
3860 #define EXTI_EMR1_EM22_Msk       (0x1UL << EXTI_EMR1_EM22_Pos)                 /*!< 0x00400000 */
3861 #define EXTI_EMR1_EM22           EXTI_EMR1_EM22_Msk                            /*!< Event Mask on line 22 */
3862 #define EXTI_EMR1_EM23_Pos       (23U)
3863 #define EXTI_EMR1_EM23_Msk       (0x1UL << EXTI_EMR1_EM23_Pos)                 /*!< 0x00800000 */
3864 #define EXTI_EMR1_EM23           EXTI_EMR1_EM23_Msk                            /*!< Event Mask on line 23 */
3865 #define EXTI_EMR1_EM24_Pos       (24U)
3866 #define EXTI_EMR1_EM24_Msk       (0x1UL << EXTI_EMR1_EM24_Pos)                 /*!< 0x01000000 */
3867 #define EXTI_EMR1_EM24           EXTI_EMR1_EM24_Msk                            /*!< Event Mask on line 24 */
3868 #define EXTI_EMR1_EM25_Pos       (25U)
3869 #define EXTI_EMR1_EM25_Msk       (0x1UL << EXTI_EMR1_EM25_Pos)                 /*!< 0x02000000 */
3870 #define EXTI_EMR1_EM25           EXTI_EMR1_EM25_Msk                            /*!< Event Mask on line 25 */
3871 #define EXTI_EMR1_EM26_Pos       (26U)
3872 #define EXTI_EMR1_EM26_Msk       (0x1UL << EXTI_EMR1_EM26_Pos)                 /*!< 0x04000000 */
3873 #define EXTI_EMR1_EM26           EXTI_EMR1_EM26_Msk                            /*!< Event Mask on line 26 */
3874 #define EXTI_EMR1_EM27_Pos       (27U)
3875 #define EXTI_EMR1_EM27_Msk       (0x1UL << EXTI_EMR1_EM27_Pos)                 /*!< 0x08000000 */
3876 #define EXTI_EMR1_EM27           EXTI_EMR1_EM27_Msk                            /*!< Event Mask on line 27 */
3877 #define EXTI_EMR1_EM28_Pos       (28U)
3878 #define EXTI_EMR1_EM28_Msk       (0x1UL << EXTI_EMR1_EM28_Pos)                 /*!< 0x10000000 */
3879 #define EXTI_EMR1_EM28           EXTI_EMR1_EM28_Msk                            /*!< Event Mask on line 28 */
3880 #define EXTI_EMR1_EM29_Pos       (29U)
3881 #define EXTI_EMR1_EM29_Msk       (0x1UL << EXTI_EMR1_EM29_Pos)                 /*!< 0x20000000 */
3882 #define EXTI_EMR1_EM29           EXTI_EMR1_EM29_Msk                            /*!< Event Mask on line 29 */
3883 #define EXTI_EMR1_EM30_Pos       (30U)
3884 #define EXTI_EMR1_EM30_Msk       (0x1UL << EXTI_EMR1_EM30_Pos)                 /*!< 0x40000000 */
3885 #define EXTI_EMR1_EM30           EXTI_EMR1_EM30_Msk                            /*!< Event Mask on line 30 */
3886 #define EXTI_EMR1_EM31_Pos       (31U)
3887 #define EXTI_EMR1_EM31_Msk       (0x1UL << EXTI_EMR1_EM31_Pos)                 /*!< 0x80000000 */
3888 #define EXTI_EMR1_EM31           EXTI_EMR1_EM31_Msk                            /*!< Event Mask on line 31 */
3889 
3890 /******************  Bit definition for EXTI_RTSR1 register  ******************/
3891 #define EXTI_RTSR1_RT0_Pos       (0U)
3892 #define EXTI_RTSR1_RT0_Msk       (0x1UL << EXTI_RTSR1_RT0_Pos)                 /*!< 0x00000001 */
3893 #define EXTI_RTSR1_RT0           EXTI_RTSR1_RT0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
3894 #define EXTI_RTSR1_RT1_Pos       (1U)
3895 #define EXTI_RTSR1_RT1_Msk       (0x1UL << EXTI_RTSR1_RT1_Pos)                 /*!< 0x00000002 */
3896 #define EXTI_RTSR1_RT1           EXTI_RTSR1_RT1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
3897 #define EXTI_RTSR1_RT2_Pos       (2U)
3898 #define EXTI_RTSR1_RT2_Msk       (0x1UL << EXTI_RTSR1_RT2_Pos)                 /*!< 0x00000004 */
3899 #define EXTI_RTSR1_RT2           EXTI_RTSR1_RT2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
3900 #define EXTI_RTSR1_RT3_Pos       (3U)
3901 #define EXTI_RTSR1_RT3_Msk       (0x1UL << EXTI_RTSR1_RT3_Pos)                 /*!< 0x00000008 */
3902 #define EXTI_RTSR1_RT3           EXTI_RTSR1_RT3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
3903 #define EXTI_RTSR1_RT4_Pos       (4U)
3904 #define EXTI_RTSR1_RT4_Msk       (0x1UL << EXTI_RTSR1_RT4_Pos)                 /*!< 0x00000010 */
3905 #define EXTI_RTSR1_RT4           EXTI_RTSR1_RT4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
3906 #define EXTI_RTSR1_RT5_Pos       (5U)
3907 #define EXTI_RTSR1_RT5_Msk       (0x1UL << EXTI_RTSR1_RT5_Pos)                 /*!< 0x00000020 */
3908 #define EXTI_RTSR1_RT5           EXTI_RTSR1_RT5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
3909 #define EXTI_RTSR1_RT6_Pos       (6U)
3910 #define EXTI_RTSR1_RT6_Msk       (0x1UL << EXTI_RTSR1_RT6_Pos)                 /*!< 0x00000040 */
3911 #define EXTI_RTSR1_RT6           EXTI_RTSR1_RT6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
3912 #define EXTI_RTSR1_RT7_Pos       (7U)
3913 #define EXTI_RTSR1_RT7_Msk       (0x1UL << EXTI_RTSR1_RT7_Pos)                 /*!< 0x00000080 */
3914 #define EXTI_RTSR1_RT7           EXTI_RTSR1_RT7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
3915 #define EXTI_RTSR1_RT8_Pos       (8U)
3916 #define EXTI_RTSR1_RT8_Msk       (0x1UL << EXTI_RTSR1_RT8_Pos)                 /*!< 0x00000100 */
3917 #define EXTI_RTSR1_RT8           EXTI_RTSR1_RT8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
3918 #define EXTI_RTSR1_RT9_Pos       (9U)
3919 #define EXTI_RTSR1_RT9_Msk       (0x1UL << EXTI_RTSR1_RT9_Pos)                 /*!< 0x00000200 */
3920 #define EXTI_RTSR1_RT9           EXTI_RTSR1_RT9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
3921 #define EXTI_RTSR1_RT10_Pos      (10U)
3922 #define EXTI_RTSR1_RT10_Msk      (0x1UL << EXTI_RTSR1_RT10_Pos)                /*!< 0x00000400 */
3923 #define EXTI_RTSR1_RT10          EXTI_RTSR1_RT10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
3924 #define EXTI_RTSR1_RT11_Pos      (11U)
3925 #define EXTI_RTSR1_RT11_Msk      (0x1UL << EXTI_RTSR1_RT11_Pos)                /*!< 0x00000800 */
3926 #define EXTI_RTSR1_RT11          EXTI_RTSR1_RT11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
3927 #define EXTI_RTSR1_RT12_Pos      (12U)
3928 #define EXTI_RTSR1_RT12_Msk      (0x1UL << EXTI_RTSR1_RT12_Pos)                /*!< 0x00001000 */
3929 #define EXTI_RTSR1_RT12          EXTI_RTSR1_RT12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
3930 #define EXTI_RTSR1_RT13_Pos      (13U)
3931 #define EXTI_RTSR1_RT13_Msk      (0x1UL << EXTI_RTSR1_RT13_Pos)                /*!< 0x00002000 */
3932 #define EXTI_RTSR1_RT13          EXTI_RTSR1_RT13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
3933 #define EXTI_RTSR1_RT14_Pos      (14U)
3934 #define EXTI_RTSR1_RT14_Msk      (0x1UL << EXTI_RTSR1_RT14_Pos)                /*!< 0x00004000 */
3935 #define EXTI_RTSR1_RT14          EXTI_RTSR1_RT14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
3936 #define EXTI_RTSR1_RT15_Pos      (15U)
3937 #define EXTI_RTSR1_RT15_Msk      (0x1UL << EXTI_RTSR1_RT15_Pos)                /*!< 0x00008000 */
3938 #define EXTI_RTSR1_RT15          EXTI_RTSR1_RT15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
3939 #define EXTI_RTSR1_RT16_Pos      (16U)
3940 #define EXTI_RTSR1_RT16_Msk      (0x1UL << EXTI_RTSR1_RT16_Pos)                /*!< 0x00010000 */
3941 #define EXTI_RTSR1_RT16          EXTI_RTSR1_RT16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
3942 #define EXTI_RTSR1_RT17_Pos      (17U)
3943 #define EXTI_RTSR1_RT17_Msk      (0x1UL << EXTI_RTSR1_RT17_Pos)                /*!< 0x00020000 */
3944 #define EXTI_RTSR1_RT17          EXTI_RTSR1_RT17_Msk                           /*!< Rising trigger event configuration bit of line 17 */
3945 #define EXTI_RTSR1_RT19_Pos      (19U)
3946 #define EXTI_RTSR1_RT19_Msk      (0x1UL << EXTI_RTSR1_RT19_Pos)                /*!< 0x00080000 */
3947 #define EXTI_RTSR1_RT19          EXTI_RTSR1_RT19_Msk                           /*!< Rising trigger event configuration bit of line 19 */
3948 #define EXTI_RTSR1_RT20_Pos      (20U)
3949 #define EXTI_RTSR1_RT20_Msk      (0x1UL << EXTI_RTSR1_RT20_Pos)                /*!< 0x00100000 */
3950 #define EXTI_RTSR1_RT20          EXTI_RTSR1_RT20_Msk                           /*!< Rising trigger event configuration bit of line 20 */
3951 #define EXTI_RTSR1_RT21_Pos      (21U)
3952 #define EXTI_RTSR1_RT21_Msk      (0x1UL << EXTI_RTSR1_RT21_Pos)                /*!< 0x00200000 */
3953 #define EXTI_RTSR1_RT21          EXTI_RTSR1_RT21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
3954 #define EXTI_RTSR1_RT22_Pos      (22U)
3955 #define EXTI_RTSR1_RT22_Msk      (0x1UL << EXTI_RTSR1_RT22_Pos)                /*!< 0x00400000 */
3956 #define EXTI_RTSR1_RT22          EXTI_RTSR1_RT22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
3957 #define EXTI_RTSR1_RT29_Pos      (29U)
3958 #define EXTI_RTSR1_RT29_Msk      (0x1UL << EXTI_RTSR1_RT29_Pos)                /*!< 0x20000000 */
3959 #define EXTI_RTSR1_RT29          EXTI_RTSR1_RT29_Msk                           /*!< Rising trigger event configuration bit of line 29 */
3960 #define EXTI_RTSR1_RT30_Pos      (30U)
3961 #define EXTI_RTSR1_RT30_Msk      (0x1UL << EXTI_RTSR1_RT30_Pos)                /*!< 0x40000000 */
3962 #define EXTI_RTSR1_RT30          EXTI_RTSR1_RT30_Msk                           /*!< Rising trigger event configuration bit of line 30 */
3963 #define EXTI_RTSR1_RT31_Pos      (31U)
3964 #define EXTI_RTSR1_RT31_Msk      (0x1UL << EXTI_RTSR1_RT31_Pos)                /*!< 0x80000000 */
3965 #define EXTI_RTSR1_RT31          EXTI_RTSR1_RT31_Msk                           /*!< Rising trigger event configuration bit of line 31 */
3966 
3967 /******************  Bit definition for EXTI_FTSR1 register  ******************/
3968 #define EXTI_FTSR1_FT0_Pos       (0U)
3969 #define EXTI_FTSR1_FT0_Msk       (0x1UL << EXTI_FTSR1_FT0_Pos)                 /*!< 0x00000001 */
3970 #define EXTI_FTSR1_FT0           EXTI_FTSR1_FT0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
3971 #define EXTI_FTSR1_FT1_Pos       (1U)
3972 #define EXTI_FTSR1_FT1_Msk       (0x1UL << EXTI_FTSR1_FT1_Pos)                 /*!< 0x00000002 */
3973 #define EXTI_FTSR1_FT1           EXTI_FTSR1_FT1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
3974 #define EXTI_FTSR1_FT2_Pos       (2U)
3975 #define EXTI_FTSR1_FT2_Msk       (0x1UL << EXTI_FTSR1_FT2_Pos)                 /*!< 0x00000004 */
3976 #define EXTI_FTSR1_FT2           EXTI_FTSR1_FT2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
3977 #define EXTI_FTSR1_FT3_Pos       (3U)
3978 #define EXTI_FTSR1_FT3_Msk       (0x1UL << EXTI_FTSR1_FT3_Pos)                 /*!< 0x00000008 */
3979 #define EXTI_FTSR1_FT3           EXTI_FTSR1_FT3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
3980 #define EXTI_FTSR1_FT4_Pos       (4U)
3981 #define EXTI_FTSR1_FT4_Msk       (0x1UL << EXTI_FTSR1_FT4_Pos)                 /*!< 0x00000010 */
3982 #define EXTI_FTSR1_FT4           EXTI_FTSR1_FT4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
3983 #define EXTI_FTSR1_FT5_Pos       (5U)
3984 #define EXTI_FTSR1_FT5_Msk       (0x1UL << EXTI_FTSR1_FT5_Pos)                 /*!< 0x00000020 */
3985 #define EXTI_FTSR1_FT5           EXTI_FTSR1_FT5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
3986 #define EXTI_FTSR1_FT6_Pos       (6U)
3987 #define EXTI_FTSR1_FT6_Msk       (0x1UL << EXTI_FTSR1_FT6_Pos)                 /*!< 0x00000040 */
3988 #define EXTI_FTSR1_FT6           EXTI_FTSR1_FT6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
3989 #define EXTI_FTSR1_FT7_Pos       (7U)
3990 #define EXTI_FTSR1_FT7_Msk       (0x1UL << EXTI_FTSR1_FT7_Pos)                 /*!< 0x00000080 */
3991 #define EXTI_FTSR1_FT7           EXTI_FTSR1_FT7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
3992 #define EXTI_FTSR1_FT8_Pos       (8U)
3993 #define EXTI_FTSR1_FT8_Msk       (0x1UL << EXTI_FTSR1_FT8_Pos)                 /*!< 0x00000100 */
3994 #define EXTI_FTSR1_FT8           EXTI_FTSR1_FT8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
3995 #define EXTI_FTSR1_FT9_Pos       (9U)
3996 #define EXTI_FTSR1_FT9_Msk       (0x1UL << EXTI_FTSR1_FT9_Pos)                 /*!< 0x00000200 */
3997 #define EXTI_FTSR1_FT9           EXTI_FTSR1_FT9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
3998 #define EXTI_FTSR1_FT10_Pos      (10U)
3999 #define EXTI_FTSR1_FT10_Msk      (0x1UL << EXTI_FTSR1_FT10_Pos)                /*!< 0x00000400 */
4000 #define EXTI_FTSR1_FT10          EXTI_FTSR1_FT10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
4001 #define EXTI_FTSR1_FT11_Pos      (11U)
4002 #define EXTI_FTSR1_FT11_Msk      (0x1UL << EXTI_FTSR1_FT11_Pos)                /*!< 0x00000800 */
4003 #define EXTI_FTSR1_FT11          EXTI_FTSR1_FT11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
4004 #define EXTI_FTSR1_FT12_Pos      (12U)
4005 #define EXTI_FTSR1_FT12_Msk      (0x1UL << EXTI_FTSR1_FT12_Pos)                /*!< 0x00001000 */
4006 #define EXTI_FTSR1_FT12          EXTI_FTSR1_FT12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
4007 #define EXTI_FTSR1_FT13_Pos      (13U)
4008 #define EXTI_FTSR1_FT13_Msk      (0x1UL << EXTI_FTSR1_FT13_Pos)                /*!< 0x00002000 */
4009 #define EXTI_FTSR1_FT13          EXTI_FTSR1_FT13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
4010 #define EXTI_FTSR1_FT14_Pos      (14U)
4011 #define EXTI_FTSR1_FT14_Msk      (0x1UL << EXTI_FTSR1_FT14_Pos)                /*!< 0x00004000 */
4012 #define EXTI_FTSR1_FT14          EXTI_FTSR1_FT14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
4013 #define EXTI_FTSR1_FT15_Pos      (15U)
4014 #define EXTI_FTSR1_FT15_Msk      (0x1UL << EXTI_FTSR1_FT15_Pos)                /*!< 0x00008000 */
4015 #define EXTI_FTSR1_FT15          EXTI_FTSR1_FT15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
4016 #define EXTI_FTSR1_FT16_Pos      (16U)
4017 #define EXTI_FTSR1_FT16_Msk      (0x1UL << EXTI_FTSR1_FT16_Pos)                /*!< 0x00010000 */
4018 #define EXTI_FTSR1_FT16          EXTI_FTSR1_FT16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
4019 #define EXTI_FTSR1_FT17_Pos      (17U)
4020 #define EXTI_FTSR1_FT17_Msk      (0x1UL << EXTI_FTSR1_FT17_Pos)                /*!< 0x00020000 */
4021 #define EXTI_FTSR1_FT17          EXTI_FTSR1_FT17_Msk                           /*!< Falling trigger event configuration bit of line 17 */
4022 #define EXTI_FTSR1_FT19_Pos      (19U)
4023 #define EXTI_FTSR1_FT19_Msk      (0x1UL << EXTI_FTSR1_FT19_Pos)                /*!< 0x00080000 */
4024 #define EXTI_FTSR1_FT19          EXTI_FTSR1_FT19_Msk                           /*!< Falling trigger event configuration bit of line 19 */
4025 #define EXTI_FTSR1_FT20_Pos      (20U)
4026 #define EXTI_FTSR1_FT20_Msk      (0x1UL << EXTI_FTSR1_FT20_Pos)                /*!< 0x00100000 */
4027 #define EXTI_FTSR1_FT20          EXTI_FTSR1_FT20_Msk                           /*!< Falling trigger event configuration bit of line 20 */
4028 #define EXTI_FTSR1_FT21_Pos      (21U)
4029 #define EXTI_FTSR1_FT21_Msk      (0x1UL << EXTI_FTSR1_FT21_Pos)                /*!< 0x00200000 */
4030 #define EXTI_FTSR1_FT21          EXTI_FTSR1_FT21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
4031 #define EXTI_FTSR1_FT22_Pos      (22U)
4032 #define EXTI_FTSR1_FT22_Msk      (0x1UL << EXTI_FTSR1_FT22_Pos)                /*!< 0x00400000 */
4033 #define EXTI_FTSR1_FT22          EXTI_FTSR1_FT22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
4034 #define EXTI_FTSR1_FT29_Pos      (29U)
4035 #define EXTI_FTSR1_FT29_Msk      (0x1UL << EXTI_FTSR1_FT29_Pos)                /*!< 0x20000000 */
4036 #define EXTI_FTSR1_FT29          EXTI_FTSR1_FT29_Msk                           /*!< Falling trigger event configuration bit of line 29 */
4037 #define EXTI_FTSR1_FT30_Pos      (30U)
4038 #define EXTI_FTSR1_FT30_Msk      (0x1UL << EXTI_FTSR1_FT30_Pos)                /*!< 0x40000000 */
4039 #define EXTI_FTSR1_FT30          EXTI_FTSR1_FT30_Msk                           /*!< Falling trigger event configuration bit of line 30 */
4040 #define EXTI_FTSR1_FT31_Pos      (31U)
4041 #define EXTI_FTSR1_FT31_Msk      (0x1UL << EXTI_FTSR1_FT31_Pos)                /*!< 0x80000000 */
4042 #define EXTI_FTSR1_FT31          EXTI_FTSR1_FT31_Msk                           /*!< Falling trigger event configuration bit of line 31 */
4043 
4044 /******************  Bit definition for EXTI_SWIER1 register  *****************/
4045 #define EXTI_SWIER1_SWI0_Pos     (0U)
4046 #define EXTI_SWIER1_SWI0_Msk     (0x1UL << EXTI_SWIER1_SWI0_Pos)               /*!< 0x00000001 */
4047 #define EXTI_SWIER1_SWI0         EXTI_SWIER1_SWI0_Msk                          /*!< Software Interrupt on line 0 */
4048 #define EXTI_SWIER1_SWI1_Pos     (1U)
4049 #define EXTI_SWIER1_SWI1_Msk     (0x1UL << EXTI_SWIER1_SWI1_Pos)               /*!< 0x00000002 */
4050 #define EXTI_SWIER1_SWI1         EXTI_SWIER1_SWI1_Msk                          /*!< Software Interrupt on line 1 */
4051 #define EXTI_SWIER1_SWI2_Pos     (2U)
4052 #define EXTI_SWIER1_SWI2_Msk     (0x1UL << EXTI_SWIER1_SWI2_Pos)               /*!< 0x00000004 */
4053 #define EXTI_SWIER1_SWI2         EXTI_SWIER1_SWI2_Msk                          /*!< Software Interrupt on line 2 */
4054 #define EXTI_SWIER1_SWI3_Pos     (3U)
4055 #define EXTI_SWIER1_SWI3_Msk     (0x1UL << EXTI_SWIER1_SWI3_Pos)               /*!< 0x00000008 */
4056 #define EXTI_SWIER1_SWI3         EXTI_SWIER1_SWI3_Msk                          /*!< Software Interrupt on line 3 */
4057 #define EXTI_SWIER1_SWI4_Pos     (4U)
4058 #define EXTI_SWIER1_SWI4_Msk     (0x1UL << EXTI_SWIER1_SWI4_Pos)               /*!< 0x00000010 */
4059 #define EXTI_SWIER1_SWI4         EXTI_SWIER1_SWI4_Msk                          /*!< Software Interrupt on line 4 */
4060 #define EXTI_SWIER1_SWI5_Pos     (5U)
4061 #define EXTI_SWIER1_SWI5_Msk     (0x1UL << EXTI_SWIER1_SWI5_Pos)               /*!< 0x00000020 */
4062 #define EXTI_SWIER1_SWI5         EXTI_SWIER1_SWI5_Msk                          /*!< Software Interrupt on line 5 */
4063 #define EXTI_SWIER1_SWI6_Pos     (6U)
4064 #define EXTI_SWIER1_SWI6_Msk     (0x1UL << EXTI_SWIER1_SWI6_Pos)               /*!< 0x00000040 */
4065 #define EXTI_SWIER1_SWI6         EXTI_SWIER1_SWI6_Msk                          /*!< Software Interrupt on line 6 */
4066 #define EXTI_SWIER1_SWI7_Pos     (7U)
4067 #define EXTI_SWIER1_SWI7_Msk     (0x1UL << EXTI_SWIER1_SWI7_Pos)               /*!< 0x00000080 */
4068 #define EXTI_SWIER1_SWI7         EXTI_SWIER1_SWI7_Msk                          /*!< Software Interrupt on line 7 */
4069 #define EXTI_SWIER1_SWI8_Pos     (8U)
4070 #define EXTI_SWIER1_SWI8_Msk     (0x1UL << EXTI_SWIER1_SWI8_Pos)               /*!< 0x00000100 */
4071 #define EXTI_SWIER1_SWI8         EXTI_SWIER1_SWI8_Msk                          /*!< Software Interrupt on line 8 */
4072 #define EXTI_SWIER1_SWI9_Pos     (9U)
4073 #define EXTI_SWIER1_SWI9_Msk     (0x1UL << EXTI_SWIER1_SWI9_Pos)               /*!< 0x00000200 */
4074 #define EXTI_SWIER1_SWI9         EXTI_SWIER1_SWI9_Msk                          /*!< Software Interrupt on line 9 */
4075 #define EXTI_SWIER1_SWI10_Pos    (10U)
4076 #define EXTI_SWIER1_SWI10_Msk    (0x1UL << EXTI_SWIER1_SWI10_Pos)              /*!< 0x00000400 */
4077 #define EXTI_SWIER1_SWI10        EXTI_SWIER1_SWI10_Msk                         /*!< Software Interrupt on line 10 */
4078 #define EXTI_SWIER1_SWI11_Pos    (11U)
4079 #define EXTI_SWIER1_SWI11_Msk    (0x1UL << EXTI_SWIER1_SWI11_Pos)              /*!< 0x00000800 */
4080 #define EXTI_SWIER1_SWI11        EXTI_SWIER1_SWI11_Msk                         /*!< Software Interrupt on line 11 */
4081 #define EXTI_SWIER1_SWI12_Pos    (12U)
4082 #define EXTI_SWIER1_SWI12_Msk    (0x1UL << EXTI_SWIER1_SWI12_Pos)              /*!< 0x00001000 */
4083 #define EXTI_SWIER1_SWI12        EXTI_SWIER1_SWI12_Msk                         /*!< Software Interrupt on line 12 */
4084 #define EXTI_SWIER1_SWI13_Pos    (13U)
4085 #define EXTI_SWIER1_SWI13_Msk    (0x1UL << EXTI_SWIER1_SWI13_Pos)              /*!< 0x00002000 */
4086 #define EXTI_SWIER1_SWI13        EXTI_SWIER1_SWI13_Msk                         /*!< Software Interrupt on line 13 */
4087 #define EXTI_SWIER1_SWI14_Pos    (14U)
4088 #define EXTI_SWIER1_SWI14_Msk    (0x1UL << EXTI_SWIER1_SWI14_Pos)              /*!< 0x00004000 */
4089 #define EXTI_SWIER1_SWI14        EXTI_SWIER1_SWI14_Msk                         /*!< Software Interrupt on line 14 */
4090 #define EXTI_SWIER1_SWI15_Pos    (15U)
4091 #define EXTI_SWIER1_SWI15_Msk    (0x1UL << EXTI_SWIER1_SWI15_Pos)              /*!< 0x00008000 */
4092 #define EXTI_SWIER1_SWI15        EXTI_SWIER1_SWI15_Msk                         /*!< Software Interrupt on line 15 */
4093 #define EXTI_SWIER1_SWI16_Pos    (16U)
4094 #define EXTI_SWIER1_SWI16_Msk    (0x1UL << EXTI_SWIER1_SWI16_Pos)              /*!< 0x00010000 */
4095 #define EXTI_SWIER1_SWI16        EXTI_SWIER1_SWI16_Msk                         /*!< Software Interrupt on line 16 */
4096 #define EXTI_SWIER1_SWI17_Pos    (17U)
4097 #define EXTI_SWIER1_SWI17_Msk    (0x1UL << EXTI_SWIER1_SWI17_Pos)              /*!< 0x00020000 */
4098 #define EXTI_SWIER1_SWI17        EXTI_SWIER1_SWI17_Msk                         /*!< Software Interrupt on line 17 */
4099 #define EXTI_SWIER1_SWI19_Pos    (19U)
4100 #define EXTI_SWIER1_SWI19_Msk    (0x1UL << EXTI_SWIER1_SWI19_Pos)              /*!< 0x00080000 */
4101 #define EXTI_SWIER1_SWI19        EXTI_SWIER1_SWI19_Msk                         /*!< Software Interrupt on line 19 */
4102 #define EXTI_SWIER1_SWI20_Pos    (20U)
4103 #define EXTI_SWIER1_SWI20_Msk    (0x1UL << EXTI_SWIER1_SWI20_Pos)              /*!< 0x00100000 */
4104 #define EXTI_SWIER1_SWI20        EXTI_SWIER1_SWI20_Msk                         /*!< Software Interrupt on line 20 */
4105 #define EXTI_SWIER1_SWI21_Pos    (21U)
4106 #define EXTI_SWIER1_SWI21_Msk    (0x1UL << EXTI_SWIER1_SWI21_Pos)              /*!< 0x00200000 */
4107 #define EXTI_SWIER1_SWI21        EXTI_SWIER1_SWI21_Msk                         /*!< Software Interrupt on line 21 */
4108 #define EXTI_SWIER1_SWI22_Pos    (22U)
4109 #define EXTI_SWIER1_SWI22_Msk    (0x1UL << EXTI_SWIER1_SWI22_Pos)              /*!< 0x00400000 */
4110 #define EXTI_SWIER1_SWI22        EXTI_SWIER1_SWI22_Msk                         /*!< Software Interrupt on line 22 */
4111 #define EXTI_SWIER1_SWI29_Pos    (29U)
4112 #define EXTI_SWIER1_SWI29_Msk    (0x1UL << EXTI_SWIER1_SWI29_Pos)              /*!< 0x20000000 */
4113 #define EXTI_SWIER1_SWI29        EXTI_SWIER1_SWI29_Msk                         /*!< Software Interrupt on line 29 */
4114 #define EXTI_SWIER1_SWI30_Pos    (30U)
4115 #define EXTI_SWIER1_SWI30_Msk    (0x1UL << EXTI_SWIER1_SWI30_Pos)              /*!< 0x40000000 */
4116 #define EXTI_SWIER1_SWI30        EXTI_SWIER1_SWI30_Msk                         /*!< Software Interrupt on line 30 */
4117 #define EXTI_SWIER1_SWI31_Pos    (31U)
4118 #define EXTI_SWIER1_SWI31_Msk    (0x1UL << EXTI_SWIER1_SWI31_Pos)              /*!< 0x80000000 */
4119 #define EXTI_SWIER1_SWI31        EXTI_SWIER1_SWI31_Msk                         /*!< Software Interrupt on line 31 */
4120 
4121 /*******************  Bit definition for EXTI_PR1 register  *******************/
4122 #define EXTI_PR1_PIF0_Pos        (0U)
4123 #define EXTI_PR1_PIF0_Msk        (0x1UL << EXTI_PR1_PIF0_Pos)                  /*!< 0x00000001 */
4124 #define EXTI_PR1_PIF0            EXTI_PR1_PIF0_Msk                             /*!< Pending bit for line 0 */
4125 #define EXTI_PR1_PIF1_Pos        (1U)
4126 #define EXTI_PR1_PIF1_Msk        (0x1UL << EXTI_PR1_PIF1_Pos)                  /*!< 0x00000002 */
4127 #define EXTI_PR1_PIF1            EXTI_PR1_PIF1_Msk                             /*!< Pending bit for line 1 */
4128 #define EXTI_PR1_PIF2_Pos        (2U)
4129 #define EXTI_PR1_PIF2_Msk        (0x1UL << EXTI_PR1_PIF2_Pos)                  /*!< 0x00000004 */
4130 #define EXTI_PR1_PIF2            EXTI_PR1_PIF2_Msk                             /*!< Pending bit for line 2 */
4131 #define EXTI_PR1_PIF3_Pos        (3U)
4132 #define EXTI_PR1_PIF3_Msk        (0x1UL << EXTI_PR1_PIF3_Pos)                  /*!< 0x00000008 */
4133 #define EXTI_PR1_PIF3            EXTI_PR1_PIF3_Msk                             /*!< Pending bit for line 3 */
4134 #define EXTI_PR1_PIF4_Pos        (4U)
4135 #define EXTI_PR1_PIF4_Msk        (0x1UL << EXTI_PR1_PIF4_Pos)                  /*!< 0x00000010 */
4136 #define EXTI_PR1_PIF4            EXTI_PR1_PIF4_Msk                             /*!< Pending bit for line 4 */
4137 #define EXTI_PR1_PIF5_Pos        (5U)
4138 #define EXTI_PR1_PIF5_Msk        (0x1UL << EXTI_PR1_PIF5_Pos)                  /*!< 0x00000020 */
4139 #define EXTI_PR1_PIF5            EXTI_PR1_PIF5_Msk                             /*!< Pending bit for line 5 */
4140 #define EXTI_PR1_PIF6_Pos        (6U)
4141 #define EXTI_PR1_PIF6_Msk        (0x1UL << EXTI_PR1_PIF6_Pos)                  /*!< 0x00000040 */
4142 #define EXTI_PR1_PIF6            EXTI_PR1_PIF6_Msk                             /*!< Pending bit for line 6 */
4143 #define EXTI_PR1_PIF7_Pos        (7U)
4144 #define EXTI_PR1_PIF7_Msk        (0x1UL << EXTI_PR1_PIF7_Pos)                  /*!< 0x00000080 */
4145 #define EXTI_PR1_PIF7            EXTI_PR1_PIF7_Msk                             /*!< Pending bit for line 7 */
4146 #define EXTI_PR1_PIF8_Pos        (8U)
4147 #define EXTI_PR1_PIF8_Msk        (0x1UL << EXTI_PR1_PIF8_Pos)                  /*!< 0x00000100 */
4148 #define EXTI_PR1_PIF8            EXTI_PR1_PIF8_Msk                             /*!< Pending bit for line 8 */
4149 #define EXTI_PR1_PIF9_Pos        (9U)
4150 #define EXTI_PR1_PIF9_Msk        (0x1UL << EXTI_PR1_PIF9_Pos)                  /*!< 0x00000200 */
4151 #define EXTI_PR1_PIF9            EXTI_PR1_PIF9_Msk                             /*!< Pending bit for line 9 */
4152 #define EXTI_PR1_PIF10_Pos       (10U)
4153 #define EXTI_PR1_PIF10_Msk       (0x1UL << EXTI_PR1_PIF10_Pos)                 /*!< 0x00000400 */
4154 #define EXTI_PR1_PIF10           EXTI_PR1_PIF10_Msk                            /*!< Pending bit for line 10 */
4155 #define EXTI_PR1_PIF11_Pos       (11U)
4156 #define EXTI_PR1_PIF11_Msk       (0x1UL << EXTI_PR1_PIF11_Pos)                 /*!< 0x00000800 */
4157 #define EXTI_PR1_PIF11           EXTI_PR1_PIF11_Msk                            /*!< Pending bit for line 11 */
4158 #define EXTI_PR1_PIF12_Pos       (12U)
4159 #define EXTI_PR1_PIF12_Msk       (0x1UL << EXTI_PR1_PIF12_Pos)                 /*!< 0x00001000 */
4160 #define EXTI_PR1_PIF12           EXTI_PR1_PIF12_Msk                            /*!< Pending bit for line 12 */
4161 #define EXTI_PR1_PIF13_Pos       (13U)
4162 #define EXTI_PR1_PIF13_Msk       (0x1UL << EXTI_PR1_PIF13_Pos)                 /*!< 0x00002000 */
4163 #define EXTI_PR1_PIF13           EXTI_PR1_PIF13_Msk                            /*!< Pending bit for line 13 */
4164 #define EXTI_PR1_PIF14_Pos       (14U)
4165 #define EXTI_PR1_PIF14_Msk       (0x1UL << EXTI_PR1_PIF14_Pos)                 /*!< 0x00004000 */
4166 #define EXTI_PR1_PIF14           EXTI_PR1_PIF14_Msk                            /*!< Pending bit for line 14 */
4167 #define EXTI_PR1_PIF15_Pos       (15U)
4168 #define EXTI_PR1_PIF15_Msk       (0x1UL << EXTI_PR1_PIF15_Pos)                 /*!< 0x00008000 */
4169 #define EXTI_PR1_PIF15           EXTI_PR1_PIF15_Msk                            /*!< Pending bit for line 15 */
4170 #define EXTI_PR1_PIF16_Pos       (16U)
4171 #define EXTI_PR1_PIF16_Msk       (0x1UL << EXTI_PR1_PIF16_Pos)                 /*!< 0x00010000 */
4172 #define EXTI_PR1_PIF16           EXTI_PR1_PIF16_Msk                            /*!< Pending bit for line 16 */
4173 #define EXTI_PR1_PIF17_Pos       (17U)
4174 #define EXTI_PR1_PIF17_Msk       (0x1UL << EXTI_PR1_PIF17_Pos)                 /*!< 0x00020000 */
4175 #define EXTI_PR1_PIF17           EXTI_PR1_PIF17_Msk                            /*!< Pending bit for line 17 */
4176 #define EXTI_PR1_PIF19_Pos       (19U)
4177 #define EXTI_PR1_PIF19_Msk       (0x1UL << EXTI_PR1_PIF19_Pos)                 /*!< 0x00080000 */
4178 #define EXTI_PR1_PIF19           EXTI_PR1_PIF19_Msk                            /*!< Pending bit for line 19 */
4179 #define EXTI_PR1_PIF20_Pos       (20U)
4180 #define EXTI_PR1_PIF20_Msk       (0x1UL << EXTI_PR1_PIF20_Pos)                 /*!< 0x00100000 */
4181 #define EXTI_PR1_PIF20           EXTI_PR1_PIF20_Msk                            /*!< Pending bit for line 20 */
4182 #define EXTI_PR1_PIF21_Pos       (21U)
4183 #define EXTI_PR1_PIF21_Msk       (0x1UL << EXTI_PR1_PIF21_Pos)                 /*!< 0x00200000 */
4184 #define EXTI_PR1_PIF21           EXTI_PR1_PIF21_Msk                            /*!< Pending bit for line 21 */
4185 #define EXTI_PR1_PIF22_Pos       (22U)
4186 #define EXTI_PR1_PIF22_Msk       (0x1UL << EXTI_PR1_PIF22_Pos)                 /*!< 0x00400000 */
4187 #define EXTI_PR1_PIF22           EXTI_PR1_PIF22_Msk                            /*!< Pending bit for line 22 */
4188 #define EXTI_PR1_PIF29_Pos       (29U)
4189 #define EXTI_PR1_PIF29_Msk       (0x1UL << EXTI_PR1_PIF29_Pos)                 /*!< 0x20000000 */
4190 #define EXTI_PR1_PIF29           EXTI_PR1_PIF29_Msk                            /*!< Pending bit for line 29 */
4191 #define EXTI_PR1_PIF30_Pos       (30U)
4192 #define EXTI_PR1_PIF30_Msk       (0x1UL << EXTI_PR1_PIF30_Pos)                 /*!< 0x40000000 */
4193 #define EXTI_PR1_PIF30           EXTI_PR1_PIF30_Msk                            /*!< Pending bit for line 30 */
4194 #define EXTI_PR1_PIF31_Pos       (31U)
4195 #define EXTI_PR1_PIF31_Msk       (0x1UL << EXTI_PR1_PIF31_Pos)                 /*!< 0x80000000 */
4196 #define EXTI_PR1_PIF31           EXTI_PR1_PIF31_Msk                            /*!< Pending bit for line 31 */
4197 
4198 /*******************  Bit definition for EXTI_IMR2 register  ******************/
4199 #define EXTI_IMR2_IM32_Pos       (0U)
4200 #define EXTI_IMR2_IM32_Msk       (0x1UL << EXTI_IMR2_IM32_Pos)                 /*!< 0x00000001 */
4201 #define EXTI_IMR2_IM32           EXTI_IMR2_IM32_Msk                            /*!< Interrupt Mask on line 32 */
4202 #define EXTI_IMR2_IM33_Pos       (1U)
4203 #define EXTI_IMR2_IM33_Msk       (0x1UL << EXTI_IMR2_IM33_Pos)                 /*!< 0x00000002 */
4204 #define EXTI_IMR2_IM33           EXTI_IMR2_IM33_Msk                            /*!< Interrupt Mask on line 33 */
4205 #define EXTI_IMR2_IM34_Pos       (2U)
4206 #define EXTI_IMR2_IM34_Msk       (0x1UL << EXTI_IMR2_IM34_Pos)                 /*!< 0x00000004 */
4207 #define EXTI_IMR2_IM34           EXTI_IMR2_IM34_Msk                            /*!< Interrupt Mask on line 34 */
4208 #define EXTI_IMR2_IM35_Pos       (3U)
4209 #define EXTI_IMR2_IM35_Msk       (0x1UL << EXTI_IMR2_IM35_Pos)                 /*!< 0x00000008 */
4210 #define EXTI_IMR2_IM35           EXTI_IMR2_IM35_Msk                            /*!< Interrupt Mask on line 35 */
4211 #define EXTI_IMR2_IM36_Pos       (4U)
4212 #define EXTI_IMR2_IM36_Msk       (0x1UL << EXTI_IMR2_IM36_Pos)                 /*!< 0x00000010 */
4213 #define EXTI_IMR2_IM36           EXTI_IMR2_IM36_Msk                            /*!< Interrupt Mask on line 36 */
4214 #define EXTI_IMR2_IM37_Pos       (5U)
4215 #define EXTI_IMR2_IM37_Msk       (0x1UL << EXTI_IMR2_IM37_Pos)                 /*!< 0x00000020 */
4216 #define EXTI_IMR2_IM37           EXTI_IMR2_IM37_Msk                            /*!< Interrupt Mask on line 37 */
4217 #define EXTI_IMR2_IM38_Pos       (6U)
4218 #define EXTI_IMR2_IM38_Msk       (0x1UL << EXTI_IMR2_IM38_Pos)                 /*!< 0x00000040 */
4219 #define EXTI_IMR2_IM38           EXTI_IMR2_IM38_Msk                            /*!< Interrupt Mask on line 38 */
4220 #define EXTI_IMR2_IM39_Pos       (7U)
4221 #define EXTI_IMR2_IM39_Msk       (0x1UL << EXTI_IMR2_IM39_Pos)                 /*!< 0x00000080 */
4222 #define EXTI_IMR2_IM39           EXTI_IMR2_IM39_Msk                            /*!< Interrupt Mask on line 39 */
4223 #define EXTI_IMR2_IM40_Pos       (8U)
4224 #define EXTI_IMR2_IM40_Msk       (0x1UL << EXTI_IMR2_IM40_Pos)                 /*!< 0x00000100 */
4225 #define EXTI_IMR2_IM40           EXTI_IMR2_IM40_Msk                            /*!< Interrupt Mask on line 40 */
4226 #define EXTI_IMR2_IM41_Pos       (9U)
4227 #define EXTI_IMR2_IM41_Msk       (0x1UL << EXTI_IMR2_IM41_Pos)                 /*!< 0x00000200 */
4228 #define EXTI_IMR2_IM41           EXTI_IMR2_IM41_Msk                            /*!< Interrupt Mask on line 41 */
4229 #define EXTI_IMR2_IM42_Pos       (10U)
4230 #define EXTI_IMR2_IM42_Msk       (0x1UL << EXTI_IMR2_IM42_Pos)                 /*!< 0x00000400 */
4231 #define EXTI_IMR2_IM42           EXTI_IMR2_IM42_Msk                            /*!< Interrupt Mask on line 42 */
4232 #define EXTI_IMR2_IM_Pos         (0U)
4233 #define EXTI_IMR2_IM_Msk         (0x7FFUL << EXTI_IMR2_IM_Pos)                 /*!< 0x000007FF */
4234 #define EXTI_IMR2_IM             EXTI_IMR2_IM_Msk                              /*!< Interrupt Mask all        */
4235 
4236 /*******************  Bit definition for EXTI_EMR2 register  ******************/
4237 #define EXTI_EMR2_EM32_Pos       (0U)
4238 #define EXTI_EMR2_EM32_Msk       (0x1UL << EXTI_EMR2_EM32_Pos)                 /*!< 0x00000001 */
4239 #define EXTI_EMR2_EM32           EXTI_EMR2_EM32_Msk                            /*!< Event Mask on line 32 */
4240 #define EXTI_EMR2_EM33_Pos       (1U)
4241 #define EXTI_EMR2_EM33_Msk       (0x1UL << EXTI_EMR2_EM33_Pos)                 /*!< 0x00000002 */
4242 #define EXTI_EMR2_EM33           EXTI_EMR2_EM33_Msk                            /*!< Event Mask on line 33 */
4243 #define EXTI_EMR2_EM34_Pos       (2U)
4244 #define EXTI_EMR2_EM34_Msk       (0x1UL << EXTI_EMR2_EM34_Pos)                 /*!< 0x00000004 */
4245 #define EXTI_EMR2_EM34           EXTI_EMR2_EM34_Msk                            /*!< Event Mask on line 34 */
4246 #define EXTI_EMR2_EM35_Pos       (3U)
4247 #define EXTI_EMR2_EM35_Msk       (0x1UL << EXTI_EMR2_EM35_Pos)                 /*!< 0x00000008 */
4248 #define EXTI_EMR2_EM35           EXTI_EMR2_EM35_Msk                            /*!< Event Mask on line 35 */
4249 #define EXTI_EMR2_EM36_Pos       (4U)
4250 #define EXTI_EMR2_EM36_Msk       (0x1UL << EXTI_EMR2_EM36_Pos)                 /*!< 0x00000010 */
4251 #define EXTI_EMR2_EM36           EXTI_EMR2_EM36_Msk                            /*!< Event Mask on line 36 */
4252 #define EXTI_EMR2_EM37_Pos       (5U)
4253 #define EXTI_EMR2_EM37_Msk       (0x1UL << EXTI_EMR2_EM37_Pos)                 /*!< 0x00000020 */
4254 #define EXTI_EMR2_EM37           EXTI_EMR2_EM37_Msk                            /*!< Event Mask on line 37 */
4255 #define EXTI_EMR2_EM38_Pos       (6U)
4256 #define EXTI_EMR2_EM38_Msk       (0x1UL << EXTI_EMR2_EM38_Pos)                 /*!< 0x00000040 */
4257 #define EXTI_EMR2_EM38           EXTI_EMR2_EM38_Msk                            /*!< Event Mask on line 38 */
4258 #define EXTI_EMR2_EM39_Pos       (7U)
4259 #define EXTI_EMR2_EM39_Msk       (0x1UL << EXTI_EMR2_EM39_Pos)                 /*!< 0x00000080 */
4260 #define EXTI_EMR2_EM39           EXTI_EMR2_EM39_Msk                            /*!< Event Mask on line 39 */
4261 #define EXTI_EMR2_EM40_Pos       (8U)
4262 #define EXTI_EMR2_EM40_Msk       (0x1UL << EXTI_EMR2_EM40_Pos)                 /*!< 0x00000100 */
4263 #define EXTI_EMR2_EM40           EXTI_EMR2_EM40_Msk                            /*!< Event Mask on line 40 */
4264 #define EXTI_EMR2_EM41_Pos       (9U)
4265 #define EXTI_EMR2_EM41_Msk       (0x1UL << EXTI_EMR2_EM41_Pos)                 /*!< 0x00000200 */
4266 #define EXTI_EMR2_EM41           EXTI_EMR2_EM41_Msk                            /*!< Event Mask on line 41 */
4267 #define EXTI_EMR2_EM42_Pos       (10U)
4268 #define EXTI_EMR2_EM42_Msk       (0x1UL << EXTI_EMR2_EM42_Pos)                 /*!< 0x00000400 */
4269 #define EXTI_EMR2_EM42           EXTI_EMR2_EM42_Msk                            /*!< Event Mask on line 42 */
4270 #define EXTI_EMR2_EM_Pos         (0U)
4271 #define EXTI_EMR2_EM_Msk         (0x7FFUL << EXTI_EMR2_EM_Pos)                 /*!< 0x000007FF */
4272 #define EXTI_EMR2_EM             EXTI_EMR2_EM_Msk                              /*!< Interrupt Mask all        */
4273 
4274 /******************  Bit definition for EXTI_RTSR2 register  ******************/
4275 #define EXTI_RTSR2_RT32_Pos      (0U)
4276 #define EXTI_RTSR2_RT32_Msk      (0x1UL << EXTI_RTSR2_RT32_Pos)                /*!< 0x00000001 */
4277 #define EXTI_RTSR2_RT32          EXTI_RTSR2_RT32_Msk                           /*!< Rising trigger event configuration bit of line 32 */
4278 #define EXTI_RTSR2_RT33_Pos      (1U)
4279 #define EXTI_RTSR2_RT33_Msk      (0x1UL << EXTI_RTSR2_RT33_Pos)                /*!< 0x00000002 */
4280 #define EXTI_RTSR2_RT33          EXTI_RTSR2_RT33_Msk                           /*!< Rising trigger event configuration bit of line 33 */
4281 #define EXTI_RTSR2_RT38_Pos      (6U)
4282 #define EXTI_RTSR2_RT38_Msk      (0x1UL << EXTI_RTSR2_RT38_Pos)                /*!< 0x00000040 */
4283 #define EXTI_RTSR2_RT38          EXTI_RTSR2_RT38_Msk                           /*!< Rising trigger event configuration bit of line 38 */
4284 #define EXTI_RTSR2_RT39_Pos      (7U)
4285 #define EXTI_RTSR2_RT39_Msk      (0x1UL << EXTI_RTSR2_RT39_Pos)                /*!< 0x00000080 */
4286 #define EXTI_RTSR2_RT39          EXTI_RTSR2_RT39_Msk                           /*!< Rising trigger event configuration bit of line 39 */
4287 #define EXTI_RTSR2_RT40_Pos      (8U)
4288 #define EXTI_RTSR2_RT40_Msk      (0x1UL << EXTI_RTSR2_RT40_Pos)                /*!< 0x00000100 */
4289 #define EXTI_RTSR2_RT40          EXTI_RTSR2_RT40_Msk                           /*!< Rising trigger event configuration bit of line 40 */
4290 #define EXTI_RTSR2_RT41_Pos      (9U)
4291 #define EXTI_RTSR2_RT41_Msk      (0x1UL << EXTI_RTSR2_RT41_Pos)                /*!< 0x00000200 */
4292 #define EXTI_RTSR2_RT41          EXTI_RTSR2_RT41_Msk                           /*!< Rising trigger event configuration bit of line 41 */
4293 
4294 /******************  Bit definition for EXTI_FTSR2 register  ******************/
4295 #define EXTI_FTSR2_FT32_Pos      (0U)
4296 #define EXTI_FTSR2_FT32_Msk      (0x1UL << EXTI_FTSR2_FT32_Pos)                /*!< 0x00000001 */
4297 #define EXTI_FTSR2_FT32          EXTI_FTSR2_FT32_Msk                           /*!< Falling trigger event configuration bit of line 32 */
4298 #define EXTI_FTSR2_FT33_Pos      (1U)
4299 #define EXTI_FTSR2_FT33_Msk      (0x1UL << EXTI_FTSR2_FT33_Pos)                /*!< 0x00000002 */
4300 #define EXTI_FTSR2_FT33          EXTI_FTSR2_FT33_Msk                           /*!< Falling trigger event configuration bit of line 33 */
4301 #define EXTI_FTSR2_FT38_Pos      (6U)
4302 #define EXTI_FTSR2_FT38_Msk      (0x1UL << EXTI_FTSR2_FT38_Pos)                /*!< 0x00000040 */
4303 #define EXTI_FTSR2_FT38          EXTI_FTSR2_FT38_Msk                           /*!< Falling trigger event configuration bit of line 37 */
4304 #define EXTI_FTSR2_FT39_Pos      (7U)
4305 #define EXTI_FTSR2_FT39_Msk      (0x1UL << EXTI_FTSR2_FT39_Pos)                /*!< 0x00000080 */
4306 #define EXTI_FTSR2_FT39          EXTI_FTSR2_FT39_Msk                           /*!< Falling trigger event configuration bit of line 39 */
4307 #define EXTI_FTSR2_FT40_Pos      (8U)
4308 #define EXTI_FTSR2_FT40_Msk      (0x1UL << EXTI_FTSR2_FT40_Pos)                /*!< 0x00000100 */
4309 #define EXTI_FTSR2_FT40          EXTI_FTSR2_FT40_Msk                           /*!< Falling trigger event configuration bit of line 40 */
4310 #define EXTI_FTSR2_FT41_Pos      (9U)
4311 #define EXTI_FTSR2_FT41_Msk      (0x1UL << EXTI_FTSR2_FT41_Pos)                /*!< 0x00000200 */
4312 #define EXTI_FTSR2_FT41          EXTI_FTSR2_FT41_Msk                           /*!< Falling trigger event configuration bit of line 41 */
4313 
4314 /******************  Bit definition for EXTI_SWIER2 register  *****************/
4315 #define EXTI_SWIER2_SWI32_Pos    (0U)
4316 #define EXTI_SWIER2_SWI32_Msk    (0x1UL << EXTI_SWIER2_SWI32_Pos)              /*!< 0x00000001 */
4317 #define EXTI_SWIER2_SWI32        EXTI_SWIER2_SWI32_Msk                         /*!< Software Interrupt on line 32 */
4318 #define EXTI_SWIER2_SWI33_Pos    (1U)
4319 #define EXTI_SWIER2_SWI33_Msk    (0x1UL << EXTI_SWIER2_SWI33_Pos)              /*!< 0x00000002 */
4320 #define EXTI_SWIER2_SWI33        EXTI_SWIER2_SWI33_Msk                         /*!< Software Interrupt on line 33 */
4321 #define EXTI_SWIER2_SWI38_Pos    (6U)
4322 #define EXTI_SWIER2_SWI38_Msk    (0x1UL << EXTI_SWIER2_SWI38_Pos)              /*!< 0x00000040 */
4323 #define EXTI_SWIER2_SWI38        EXTI_SWIER2_SWI38_Msk                         /*!< Software Interrupt on line 38 */
4324 #define EXTI_SWIER2_SWI39_Pos    (7U)
4325 #define EXTI_SWIER2_SWI39_Msk    (0x1UL << EXTI_SWIER2_SWI39_Pos)              /*!< 0x00000080 */
4326 #define EXTI_SWIER2_SWI39        EXTI_SWIER2_SWI39_Msk                         /*!< Software Interrupt on line 39 */
4327 #define EXTI_SWIER2_SWI40_Pos    (8U)
4328 #define EXTI_SWIER2_SWI40_Msk    (0x1UL << EXTI_SWIER2_SWI40_Pos)              /*!< 0x00000100 */
4329 #define EXTI_SWIER2_SWI40        EXTI_SWIER2_SWI40_Msk                         /*!< Software Interrupt on line 40 */
4330 #define EXTI_SWIER2_SWI41_Pos    (9U)
4331 #define EXTI_SWIER2_SWI41_Msk    (0x1UL << EXTI_SWIER2_SWI41_Pos)              /*!< 0x00000200 */
4332 #define EXTI_SWIER2_SWI41        EXTI_SWIER2_SWI41_Msk                         /*!< Software Interrupt on line 41 */
4333 
4334 /*******************  Bit definition for EXTI_PR2 register  *******************/
4335 #define EXTI_PR2_PIF32_Pos       (0U)
4336 #define EXTI_PR2_PIF32_Msk       (0x1UL << EXTI_PR2_PIF32_Pos)                 /*!< 0x00000001 */
4337 #define EXTI_PR2_PIF32           EXTI_PR2_PIF32_Msk                            /*!< Pending bit for line 32 */
4338 #define EXTI_PR2_PIF33_Pos       (1U)
4339 #define EXTI_PR2_PIF33_Msk       (0x1UL << EXTI_PR2_PIF33_Pos)                 /*!< 0x00000002 */
4340 #define EXTI_PR2_PIF33           EXTI_PR2_PIF33_Msk                            /*!< Pending bit for line 33 */
4341 #define EXTI_PR2_PIF38_Pos       (6U)
4342 #define EXTI_PR2_PIF38_Msk       (0x1UL << EXTI_PR2_PIF38_Pos)                 /*!< 0x00000040 */
4343 #define EXTI_PR2_PIF38           EXTI_PR2_PIF38_Msk                            /*!< Pending bit for line 38 */
4344 #define EXTI_PR2_PIF39_Pos       (7U)
4345 #define EXTI_PR2_PIF39_Msk       (0x1UL << EXTI_PR2_PIF39_Pos)                 /*!< 0x00000080 */
4346 #define EXTI_PR2_PIF39           EXTI_PR2_PIF39_Msk                            /*!< Pending bit for line 39 */
4347 #define EXTI_PR2_PIF40_Pos       (8U)
4348 #define EXTI_PR2_PIF40_Msk       (0x1UL << EXTI_PR2_PIF40_Pos)                 /*!< 0x00000100 */
4349 #define EXTI_PR2_PIF40           EXTI_PR2_PIF40_Msk                            /*!< Pending bit for line 40 */
4350 #define EXTI_PR2_PIF41_Pos       (9U)
4351 #define EXTI_PR2_PIF41_Msk       (0x1UL << EXTI_PR2_PIF41_Pos)                 /*!< 0x00000200 */
4352 #define EXTI_PR2_PIF41           EXTI_PR2_PIF41_Msk                            /*!< Pending bit for line 41 */
4353 
4354 /******************************************************************************/
4355 /*                                                                            */
4356 /*                 Flexible Datarate Controller Area Network                  */
4357 /*                                                                            */
4358 /******************************************************************************/
4359 /*!<FDCAN control and status registers */
4360 /*****************  Bit definition for FDCAN_CREL register  *******************/
4361 #define FDCAN_CREL_DAY_Pos        (0U)
4362 #define FDCAN_CREL_DAY_Msk        (0xFFUL << FDCAN_CREL_DAY_Pos)               /*!< 0x000000FF */
4363 #define FDCAN_CREL_DAY            FDCAN_CREL_DAY_Msk                           /*!<Timestamp Day                           */
4364 #define FDCAN_CREL_MON_Pos        (8U)
4365 #define FDCAN_CREL_MON_Msk        (0xFFUL << FDCAN_CREL_MON_Pos)               /*!< 0x0000FF00 */
4366 #define FDCAN_CREL_MON            FDCAN_CREL_MON_Msk                           /*!<Timestamp Month                         */
4367 #define FDCAN_CREL_YEAR_Pos       (16U)
4368 #define FDCAN_CREL_YEAR_Msk       (0xFUL << FDCAN_CREL_YEAR_Pos)               /*!< 0x000F0000 */
4369 #define FDCAN_CREL_YEAR           FDCAN_CREL_YEAR_Msk                          /*!<Timestamp Year                          */
4370 #define FDCAN_CREL_SUBSTEP_Pos    (20U)
4371 #define FDCAN_CREL_SUBSTEP_Msk    (0xFUL << FDCAN_CREL_SUBSTEP_Pos)            /*!< 0x00F00000 */
4372 #define FDCAN_CREL_SUBSTEP        FDCAN_CREL_SUBSTEP_Msk                       /*!<Sub-step of Core release                */
4373 #define FDCAN_CREL_STEP_Pos       (24U)
4374 #define FDCAN_CREL_STEP_Msk       (0xFUL << FDCAN_CREL_STEP_Pos)               /*!< 0x0F000000 */
4375 #define FDCAN_CREL_STEP           FDCAN_CREL_STEP_Msk                          /*!<Step of Core release                    */
4376 #define FDCAN_CREL_REL_Pos        (28U)
4377 #define FDCAN_CREL_REL_Msk        (0xFUL << FDCAN_CREL_REL_Pos)                /*!< 0xF0000000 */
4378 #define FDCAN_CREL_REL            FDCAN_CREL_REL_Msk                           /*!<Core release                            */
4379 
4380 /*****************  Bit definition for FDCAN_ENDN register  *******************/
4381 #define FDCAN_ENDN_ETV_Pos        (0U)
4382 #define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)         /*!< 0xFFFFFFFF */
4383 #define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endiannes Test Value                    */
4384 
4385 /*****************  Bit definition for FDCAN_DBTP register  *******************/
4386 #define FDCAN_DBTP_DSJW_Pos       (0U)
4387 #define FDCAN_DBTP_DSJW_Msk       (0xFUL << FDCAN_DBTP_DSJW_Pos)               /*!< 0x0000000F */
4388 #define FDCAN_DBTP_DSJW           FDCAN_DBTP_DSJW_Msk                          /*!<Synchronization Jump Width              */
4389 #define FDCAN_DBTP_DTSEG2_Pos     (4U)
4390 #define FDCAN_DBTP_DTSEG2_Msk     (0xFUL << FDCAN_DBTP_DTSEG2_Pos)             /*!< 0x000000F0 */
4391 #define FDCAN_DBTP_DTSEG2         FDCAN_DBTP_DTSEG2_Msk                        /*!<Data time segment after sample point    */
4392 #define FDCAN_DBTP_DTSEG1_Pos     (8U)
4393 #define FDCAN_DBTP_DTSEG1_Msk     (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)            /*!< 0x00001F00 */
4394 #define FDCAN_DBTP_DTSEG1         FDCAN_DBTP_DTSEG1_Msk                        /*!<Data time segment before sample point   */
4395 #define FDCAN_DBTP_DBRP_Pos       (16U)
4396 #define FDCAN_DBTP_DBRP_Msk       (0x1FUL << FDCAN_DBTP_DBRP_Pos)              /*!< 0x001F0000 */
4397 #define FDCAN_DBTP_DBRP           FDCAN_DBTP_DBRP_Msk                          /*!<Data BIt Rate Prescaler                 */
4398 #define FDCAN_DBTP_TDC_Pos        (23U)
4399 #define FDCAN_DBTP_TDC_Msk        (0x1UL << FDCAN_DBTP_TDC_Pos)                /*!< 0x00800000 */
4400 #define FDCAN_DBTP_TDC            FDCAN_DBTP_TDC_Msk                           /*!<Transceiver Delay Compensation          */
4401 
4402 /*****************  Bit definition for FDCAN_TEST register  *******************/
4403 #define FDCAN_TEST_LBCK_Pos       (4U)
4404 #define FDCAN_TEST_LBCK_Msk       (0x1UL << FDCAN_TEST_LBCK_Pos)               /*!< 0x00000010 */
4405 #define FDCAN_TEST_LBCK           FDCAN_TEST_LBCK_Msk                          /*!<Loop Back mode                           */
4406 #define FDCAN_TEST_TX_Pos         (5U)
4407 #define FDCAN_TEST_TX_Msk         (0x3UL << FDCAN_TEST_TX_Pos)                 /*!< 0x00000060 */
4408 #define FDCAN_TEST_TX             FDCAN_TEST_TX_Msk                            /*!<Control of Transmit Pin                  */
4409 #define FDCAN_TEST_RX_Pos         (7U)
4410 #define FDCAN_TEST_RX_Msk         (0x1UL << FDCAN_TEST_RX_Pos)                 /*!< 0x00000080 */
4411 #define FDCAN_TEST_RX             FDCAN_TEST_RX_Msk                            /*!<Receive Pin                              */
4412 
4413 /*****************  Bit definition for FDCAN_RWD register  ********************/
4414 #define FDCAN_RWD_WDC_Pos         (0U)
4415 #define FDCAN_RWD_WDC_Msk         (0xFFUL << FDCAN_RWD_WDC_Pos)                /*!< 0x000000FF */
4416 #define FDCAN_RWD_WDC             FDCAN_RWD_WDC_Msk                            /*!<Watchdog configuration                   */
4417 #define FDCAN_RWD_WDV_Pos         (8U)
4418 #define FDCAN_RWD_WDV_Msk         (0xFFUL << FDCAN_RWD_WDV_Pos)                /*!< 0x0000FF00 */
4419 #define FDCAN_RWD_WDV             FDCAN_RWD_WDV_Msk                            /*!<Watchdog value                           */
4420 
4421 /*****************  Bit definition for FDCAN_CCCR register  ********************/
4422 #define FDCAN_CCCR_INIT_Pos       (0U)
4423 #define FDCAN_CCCR_INIT_Msk       (0x1UL << FDCAN_CCCR_INIT_Pos)               /*!< 0x00000001 */
4424 #define FDCAN_CCCR_INIT           FDCAN_CCCR_INIT_Msk                          /*!<Initialization                           */
4425 #define FDCAN_CCCR_CCE_Pos        (1U)
4426 #define FDCAN_CCCR_CCE_Msk        (0x1UL << FDCAN_CCCR_CCE_Pos)                /*!< 0x00000002 */
4427 #define FDCAN_CCCR_CCE            FDCAN_CCCR_CCE_Msk                           /*!<Configuration Change Enable              */
4428 #define FDCAN_CCCR_ASM_Pos        (2U)
4429 #define FDCAN_CCCR_ASM_Msk        (0x1UL << FDCAN_CCCR_ASM_Pos)                /*!< 0x00000004 */
4430 #define FDCAN_CCCR_ASM            FDCAN_CCCR_ASM_Msk                           /*!<ASM Restricted Operation Mode            */
4431 #define FDCAN_CCCR_CSA_Pos        (3U)
4432 #define FDCAN_CCCR_CSA_Msk        (0x1UL << FDCAN_CCCR_CSA_Pos)                /*!< 0x00000008 */
4433 #define FDCAN_CCCR_CSA            FDCAN_CCCR_CSA_Msk                           /*!<Clock Stop Acknowledge                   */
4434 #define FDCAN_CCCR_CSR_Pos        (4U)
4435 #define FDCAN_CCCR_CSR_Msk        (0x1UL << FDCAN_CCCR_CSR_Pos)                /*!< 0x00000010 */
4436 #define FDCAN_CCCR_CSR            FDCAN_CCCR_CSR_Msk                           /*!<Clock Stop Request                       */
4437 #define FDCAN_CCCR_MON_Pos        (5U)
4438 #define FDCAN_CCCR_MON_Msk        (0x1UL << FDCAN_CCCR_MON_Pos)                /*!< 0x00000020 */
4439 #define FDCAN_CCCR_MON            FDCAN_CCCR_MON_Msk                           /*!<Bus Monitoring Mode                      */
4440 #define FDCAN_CCCR_DAR_Pos        (6U)
4441 #define FDCAN_CCCR_DAR_Msk        (0x1UL << FDCAN_CCCR_DAR_Pos)                /*!< 0x00000040 */
4442 #define FDCAN_CCCR_DAR            FDCAN_CCCR_DAR_Msk                           /*!<Disable Automatic Retransmission         */
4443 #define FDCAN_CCCR_TEST_Pos       (7U)
4444 #define FDCAN_CCCR_TEST_Msk       (0x1UL << FDCAN_CCCR_TEST_Pos)               /*!< 0x00000080 */
4445 #define FDCAN_CCCR_TEST           FDCAN_CCCR_TEST_Msk                          /*!<Test Mode Enable                         */
4446 #define FDCAN_CCCR_FDOE_Pos       (8U)
4447 #define FDCAN_CCCR_FDOE_Msk       (0x1UL << FDCAN_CCCR_FDOE_Pos)               /*!< 0x00000100 */
4448 #define FDCAN_CCCR_FDOE           FDCAN_CCCR_FDOE_Msk                          /*!<FD Operation Enable                      */
4449 #define FDCAN_CCCR_BRSE_Pos       (9U)
4450 #define FDCAN_CCCR_BRSE_Msk       (0x1UL << FDCAN_CCCR_BRSE_Pos)               /*!< 0x00000200 */
4451 #define FDCAN_CCCR_BRSE           FDCAN_CCCR_BRSE_Msk                          /*!<FDCAN Bit Rate Switching                 */
4452 #define FDCAN_CCCR_PXHD_Pos       (12U)
4453 #define FDCAN_CCCR_PXHD_Msk       (0x1UL << FDCAN_CCCR_PXHD_Pos)               /*!< 0x00001000 */
4454 #define FDCAN_CCCR_PXHD           FDCAN_CCCR_PXHD_Msk                          /*!<Protocol Exception Handling Disable      */
4455 #define FDCAN_CCCR_EFBI_Pos       (13U)
4456 #define FDCAN_CCCR_EFBI_Msk       (0x1UL << FDCAN_CCCR_EFBI_Pos)               /*!< 0x00002000 */
4457 #define FDCAN_CCCR_EFBI           FDCAN_CCCR_EFBI_Msk                          /*!<Edge Filtering during Bus Integration    */
4458 #define FDCAN_CCCR_TXP_Pos        (14U)
4459 #define FDCAN_CCCR_TXP_Msk        (0x1UL << FDCAN_CCCR_TXP_Pos)                /*!< 0x00004000 */
4460 #define FDCAN_CCCR_TXP            FDCAN_CCCR_TXP_Msk                           /*!<Two CAN bit times Pause                  */
4461 #define FDCAN_CCCR_NISO_Pos       (15U)
4462 #define FDCAN_CCCR_NISO_Msk       (0x1UL << FDCAN_CCCR_NISO_Pos)               /*!< 0x00008000 */
4463 #define FDCAN_CCCR_NISO           FDCAN_CCCR_NISO_Msk                          /*!<Non ISO Operation                        */
4464 
4465 /*****************  Bit definition for FDCAN_NBTP register  ********************/
4466 #define FDCAN_NBTP_NTSEG2_Pos     (0U)
4467 #define FDCAN_NBTP_NTSEG2_Msk     (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)            /*!< 0x0000007F */
4468 #define FDCAN_NBTP_NTSEG2         FDCAN_NBTP_NTSEG2_Msk                        /*!<Nominal Time segment after sample point  */
4469 #define FDCAN_NBTP_NTSEG1_Pos     (8U)
4470 #define FDCAN_NBTP_NTSEG1_Msk     (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)            /*!< 0x0000FF00 */
4471 #define FDCAN_NBTP_NTSEG1         FDCAN_NBTP_NTSEG1_Msk                        /*!<Nominal Time segment before sample point */
4472 #define FDCAN_NBTP_NBRP_Pos       (16U)
4473 #define FDCAN_NBTP_NBRP_Msk       (0x1FFUL << FDCAN_NBTP_NBRP_Pos)             /*!< 0x01FF0000 */
4474 #define FDCAN_NBTP_NBRP           FDCAN_NBTP_NBRP_Msk                          /*!<Bit Rate Prescaler                       */
4475 #define FDCAN_NBTP_NSJW_Pos       (25U)
4476 #define FDCAN_NBTP_NSJW_Msk       (0x7FUL << FDCAN_NBTP_NSJW_Pos)              /*!< 0xFE000000 */
4477 #define FDCAN_NBTP_NSJW           FDCAN_NBTP_NSJW_Msk                          /*!<Nominal (Re)Synchronization Jump Width   */
4478 
4479 /*****************  Bit definition for FDCAN_TSCC register  ********************/
4480 #define FDCAN_TSCC_TSS_Pos        (0U)
4481 #define FDCAN_TSCC_TSS_Msk        (0x3UL << FDCAN_TSCC_TSS_Pos)                /*!< 0x00000003 */
4482 #define FDCAN_TSCC_TSS            FDCAN_TSCC_TSS_Msk                           /*!<Timestamp Select                         */
4483 #define FDCAN_TSCC_TCP_Pos        (16U)
4484 #define FDCAN_TSCC_TCP_Msk        (0xFUL << FDCAN_TSCC_TCP_Pos)                /*!< 0x000F0000 */
4485 #define FDCAN_TSCC_TCP            FDCAN_TSCC_TCP_Msk                           /*!<Timestamp Counter Prescaler              */
4486 
4487 /*****************  Bit definition for FDCAN_TSCV register  ********************/
4488 #define FDCAN_TSCV_TSC_Pos        (0U)
4489 #define FDCAN_TSCV_TSC_Msk        (0xFFFFUL << FDCAN_TSCV_TSC_Pos)             /*!< 0x0000FFFF */
4490 #define FDCAN_TSCV_TSC            FDCAN_TSCV_TSC_Msk                           /*!<Timestamp Counter                        */
4491 
4492 /*****************  Bit definition for FDCAN_TOCC register  ********************/
4493 #define FDCAN_TOCC_ETOC_Pos       (0U)
4494 #define FDCAN_TOCC_ETOC_Msk       (0x1UL << FDCAN_TOCC_ETOC_Pos)               /*!< 0x00000001 */
4495 #define FDCAN_TOCC_ETOC           FDCAN_TOCC_ETOC_Msk                          /*!<Enable Timeout Counter                   */
4496 #define FDCAN_TOCC_TOS_Pos        (1U)
4497 #define FDCAN_TOCC_TOS_Msk        (0x3UL << FDCAN_TOCC_TOS_Pos)                /*!< 0x00000006 */
4498 #define FDCAN_TOCC_TOS            FDCAN_TOCC_TOS_Msk                           /*!<Timeout Select                           */
4499 #define FDCAN_TOCC_TOP_Pos        (16U)
4500 #define FDCAN_TOCC_TOP_Msk        (0xFFFFUL << FDCAN_TOCC_TOP_Pos)             /*!< 0xFFFF0000 */
4501 #define FDCAN_TOCC_TOP            FDCAN_TOCC_TOP_Msk                           /*!<Timeout Period                           */
4502 
4503 /*****************  Bit definition for FDCAN_TOCV register  ********************/
4504 #define FDCAN_TOCV_TOC_Pos        (0U)
4505 #define FDCAN_TOCV_TOC_Msk        (0xFFFFUL << FDCAN_TOCV_TOC_Pos)             /*!< 0x0000FFFF */
4506 #define FDCAN_TOCV_TOC            FDCAN_TOCV_TOC_Msk                           /*!<Timeout Counter                          */
4507 
4508 /*****************  Bit definition for FDCAN_ECR register  *********************/
4509 #define FDCAN_ECR_TEC_Pos         (0U)
4510 #define FDCAN_ECR_TEC_Msk         (0xFFUL << FDCAN_ECR_TEC_Pos)                /*!< 0x000000FF */
4511 #define FDCAN_ECR_TEC             FDCAN_ECR_TEC_Msk                            /*!<Transmit Error Counter                   */
4512 #define FDCAN_ECR_REC_Pos         (8U)
4513 #define FDCAN_ECR_REC_Msk         (0x7FUL << FDCAN_ECR_REC_Pos)                /*!< 0x00007F00 */
4514 #define FDCAN_ECR_REC             FDCAN_ECR_REC_Msk                            /*!<Receive Error Counter                    */
4515 #define FDCAN_ECR_RP_Pos          (15U)
4516 #define FDCAN_ECR_RP_Msk          (0x1UL << FDCAN_ECR_RP_Pos)                  /*!< 0x00008000 */
4517 #define FDCAN_ECR_RP              FDCAN_ECR_RP_Msk                             /*!<Receive Error Passive                    */
4518 #define FDCAN_ECR_CEL_Pos         (16U)
4519 #define FDCAN_ECR_CEL_Msk         (0xFFUL << FDCAN_ECR_CEL_Pos)                /*!< 0x00FF0000 */
4520 #define FDCAN_ECR_CEL             FDCAN_ECR_CEL_Msk                            /*!<CAN Error Logging                        */
4521 
4522 /*****************  Bit definition for FDCAN_PSR register  *********************/
4523 #define FDCAN_PSR_LEC_Pos         (0U)
4524 #define FDCAN_PSR_LEC_Msk         (0x7UL << FDCAN_PSR_LEC_Pos)                 /*!< 0x00000007 */
4525 #define FDCAN_PSR_LEC             FDCAN_PSR_LEC_Msk                            /*!<Last Error Code                          */
4526 #define FDCAN_PSR_ACT_Pos         (3U)
4527 #define FDCAN_PSR_ACT_Msk         (0x3UL << FDCAN_PSR_ACT_Pos)                 /*!< 0x00000018 */
4528 #define FDCAN_PSR_ACT             FDCAN_PSR_ACT_Msk                            /*!<Activity                                 */
4529 #define FDCAN_PSR_EP_Pos          (5U)
4530 #define FDCAN_PSR_EP_Msk          (0x1UL << FDCAN_PSR_EP_Pos)                  /*!< 0x00000020 */
4531 #define FDCAN_PSR_EP              FDCAN_PSR_EP_Msk                             /*!<Error Passive                            */
4532 #define FDCAN_PSR_EW_Pos          (6U)
4533 #define FDCAN_PSR_EW_Msk          (0x1UL << FDCAN_PSR_EW_Pos)                  /*!< 0x00000040 */
4534 #define FDCAN_PSR_EW              FDCAN_PSR_EW_Msk                             /*!<Warning Status                           */
4535 #define FDCAN_PSR_BO_Pos          (7U)
4536 #define FDCAN_PSR_BO_Msk          (0x1UL << FDCAN_PSR_BO_Pos)                  /*!< 0x00000080 */
4537 #define FDCAN_PSR_BO              FDCAN_PSR_BO_Msk                             /*!<Bus_Off Status                           */
4538 #define FDCAN_PSR_DLEC_Pos        (8U)
4539 #define FDCAN_PSR_DLEC_Msk        (0x7UL << FDCAN_PSR_DLEC_Pos)                /*!< 0x00000700 */
4540 #define FDCAN_PSR_DLEC            FDCAN_PSR_DLEC_Msk                           /*!<Data Last Error Code                     */
4541 #define FDCAN_PSR_RESI_Pos        (11U)
4542 #define FDCAN_PSR_RESI_Msk        (0x1UL << FDCAN_PSR_RESI_Pos)                /*!< 0x00000800 */
4543 #define FDCAN_PSR_RESI            FDCAN_PSR_RESI_Msk                           /*!<ESI flag of last received FDCAN Message  */
4544 #define FDCAN_PSR_RBRS_Pos        (12U)
4545 #define FDCAN_PSR_RBRS_Msk        (0x1UL << FDCAN_PSR_RBRS_Pos)                /*!< 0x00001000 */
4546 #define FDCAN_PSR_RBRS            FDCAN_PSR_RBRS_Msk                           /*!<BRS flag of last received FDCAN Message  */
4547 #define FDCAN_PSR_REDL_Pos        (13U)
4548 #define FDCAN_PSR_REDL_Msk        (0x1UL << FDCAN_PSR_REDL_Pos)                /*!< 0x00002000 */
4549 #define FDCAN_PSR_REDL            FDCAN_PSR_REDL_Msk                           /*!<Received FDCAN Message                   */
4550 #define FDCAN_PSR_PXE_Pos         (14U)
4551 #define FDCAN_PSR_PXE_Msk         (0x1UL << FDCAN_PSR_PXE_Pos)                 /*!< 0x00004000 */
4552 #define FDCAN_PSR_PXE             FDCAN_PSR_PXE_Msk                            /*!<Protocol Exception Event                 */
4553 #define FDCAN_PSR_TDCV_Pos        (16U)
4554 #define FDCAN_PSR_TDCV_Msk        (0x7FUL << FDCAN_PSR_TDCV_Pos)               /*!< 0x007F0000 */
4555 #define FDCAN_PSR_TDCV            FDCAN_PSR_TDCV_Msk                           /*!<Transmitter Delay Compensation Value     */
4556 
4557 /*****************  Bit definition for FDCAN_TDCR register  ********************/
4558 #define FDCAN_TDCR_TDCF_Pos       (0U)
4559 #define FDCAN_TDCR_TDCF_Msk       (0x7FUL << FDCAN_TDCR_TDCF_Pos)              /*!< 0x0000007F */
4560 #define FDCAN_TDCR_TDCF           FDCAN_TDCR_TDCF_Msk                          /*!<Transmitter Delay Compensation Filter    */
4561 #define FDCAN_TDCR_TDCO_Pos       (8U)
4562 #define FDCAN_TDCR_TDCO_Msk       (0x7FUL << FDCAN_TDCR_TDCO_Pos)              /*!< 0x00007F00 */
4563 #define FDCAN_TDCR_TDCO           FDCAN_TDCR_TDCO_Msk                          /*!<Transmitter Delay Compensation Offset    */
4564 
4565 /*****************  Bit definition for FDCAN_IR register  **********************/
4566 #define FDCAN_IR_RF0N_Pos         (0U)
4567 #define FDCAN_IR_RF0N_Msk         (0x1UL << FDCAN_IR_RF0N_Pos)                 /*!< 0x00000001 */
4568 #define FDCAN_IR_RF0N             FDCAN_IR_RF0N_Msk                            /*!<Rx FIFO 0 New Message                    */
4569 #define FDCAN_IR_RF0F_Pos         (1U)
4570 #define FDCAN_IR_RF0F_Msk         (0x1UL << FDCAN_IR_RF0F_Pos)                 /*!< 0x00000002 */
4571 #define FDCAN_IR_RF0F             FDCAN_IR_RF0F_Msk                            /*!<Rx FIFO 0 Full                           */
4572 #define FDCAN_IR_RF0L_Pos         (2U)
4573 #define FDCAN_IR_RF0L_Msk         (0x1UL << FDCAN_IR_RF0L_Pos)                 /*!< 0x00000004 */
4574 #define FDCAN_IR_RF0L             FDCAN_IR_RF0L_Msk                            /*!<Rx FIFO 0 Message Lost                   */
4575 #define FDCAN_IR_RF1N_Pos         (3U)
4576 #define FDCAN_IR_RF1N_Msk         (0x1UL << FDCAN_IR_RF1N_Pos)                 /*!< 0x00000008 */
4577 #define FDCAN_IR_RF1N             FDCAN_IR_RF1N_Msk                            /*!<Rx FIFO 1 New Message                    */
4578 #define FDCAN_IR_RF1F_Pos         (4U)
4579 #define FDCAN_IR_RF1F_Msk         (0x1UL << FDCAN_IR_RF1F_Pos)                 /*!< 0x00000010 */
4580 #define FDCAN_IR_RF1F             FDCAN_IR_RF1F_Msk                            /*!<Rx FIFO 1 Full                           */
4581 #define FDCAN_IR_RF1L_Pos         (5U)
4582 #define FDCAN_IR_RF1L_Msk         (0x1UL << FDCAN_IR_RF1L_Pos)                 /*!< 0x00000020 */
4583 #define FDCAN_IR_RF1L             FDCAN_IR_RF1L_Msk                            /*!<Rx FIFO 1 Message Lost                   */
4584 #define FDCAN_IR_HPM_Pos          (6U)
4585 #define FDCAN_IR_HPM_Msk          (0x1UL << FDCAN_IR_HPM_Pos)                  /*!< 0x00000040 */
4586 #define FDCAN_IR_HPM              FDCAN_IR_HPM_Msk                             /*!<High Priority Message                    */
4587 #define FDCAN_IR_TC_Pos           (7U)
4588 #define FDCAN_IR_TC_Msk           (0x1UL << FDCAN_IR_TC_Pos)                   /*!< 0x00000080 */
4589 #define FDCAN_IR_TC               FDCAN_IR_TC_Msk                              /*!<Transmission Completed                   */
4590 #define FDCAN_IR_TCF_Pos          (8U)
4591 #define FDCAN_IR_TCF_Msk          (0x1UL << FDCAN_IR_TCF_Pos)                  /*!< 0x00000100 */
4592 #define FDCAN_IR_TCF              FDCAN_IR_TCF_Msk                             /*!<Transmission Cancellation Finished       */
4593 #define FDCAN_IR_TFE_Pos          (9U)
4594 #define FDCAN_IR_TFE_Msk          (0x1UL << FDCAN_IR_TFE_Pos)                  /*!< 0x00000200 */
4595 #define FDCAN_IR_TFE              FDCAN_IR_TFE_Msk                             /*!<Tx FIFO Empty                            */
4596 #define FDCAN_IR_TEFN_Pos         (10U)
4597 #define FDCAN_IR_TEFN_Msk         (0x1UL << FDCAN_IR_TEFN_Pos)                 /*!< 0x00000400 */
4598 #define FDCAN_IR_TEFN             FDCAN_IR_TEFN_Msk                            /*!<Tx Event FIFO New Entry                  */
4599 #define FDCAN_IR_TEFF_Pos         (11U)
4600 #define FDCAN_IR_TEFF_Msk         (0x1UL << FDCAN_IR_TEFF_Pos)                 /*!< 0x00000800 */
4601 #define FDCAN_IR_TEFF             FDCAN_IR_TEFF_Msk                            /*!<Tx Event FIFO Full                       */
4602 #define FDCAN_IR_TEFL_Pos         (12U)
4603 #define FDCAN_IR_TEFL_Msk         (0x1UL << FDCAN_IR_TEFL_Pos)                 /*!< 0x00001000 */
4604 #define FDCAN_IR_TEFL             FDCAN_IR_TEFL_Msk                            /*!<Tx Event FIFO Element Lost               */
4605 #define FDCAN_IR_TSW_Pos          (13U)
4606 #define FDCAN_IR_TSW_Msk          (0x1UL << FDCAN_IR_TSW_Pos)                  /*!< 0x00002000 */
4607 #define FDCAN_IR_TSW              FDCAN_IR_TSW_Msk                             /*!<Timestamp Wraparound                     */
4608 #define FDCAN_IR_MRAF_Pos         (14U)
4609 #define FDCAN_IR_MRAF_Msk         (0x1UL << FDCAN_IR_MRAF_Pos)                 /*!< 0x00004000 */
4610 #define FDCAN_IR_MRAF             FDCAN_IR_MRAF_Msk                            /*!<Message RAM Access Failure               */
4611 #define FDCAN_IR_TOO_Pos          (15U)
4612 #define FDCAN_IR_TOO_Msk          (0x1UL << FDCAN_IR_TOO_Pos)                  /*!< 0x00008000 */
4613 #define FDCAN_IR_TOO              FDCAN_IR_TOO_Msk                             /*!<Timeout Occurred                         */
4614 #define FDCAN_IR_ELO_Pos          (16U)
4615 #define FDCAN_IR_ELO_Msk          (0x1UL << FDCAN_IR_ELO_Pos)                  /*!< 0x00010000 */
4616 #define FDCAN_IR_ELO              FDCAN_IR_ELO_Msk                             /*!<Error Logging Overflow                   */
4617 #define FDCAN_IR_EP_Pos           (17U)
4618 #define FDCAN_IR_EP_Msk           (0x1UL << FDCAN_IR_EP_Pos)                   /*!< 0x00020000 */
4619 #define FDCAN_IR_EP               FDCAN_IR_EP_Msk                              /*!<Error Passive                            */
4620 #define FDCAN_IR_EW_Pos           (18U)
4621 #define FDCAN_IR_EW_Msk           (0x1UL << FDCAN_IR_EW_Pos)                   /*!< 0x00040000 */
4622 #define FDCAN_IR_EW               FDCAN_IR_EW_Msk                              /*!<Warning Status                           */
4623 #define FDCAN_IR_BO_Pos           (19U)
4624 #define FDCAN_IR_BO_Msk           (0x1UL << FDCAN_IR_BO_Pos)                   /*!< 0x00080000 */
4625 #define FDCAN_IR_BO               FDCAN_IR_BO_Msk                              /*!<Bus_Off Status                           */
4626 #define FDCAN_IR_WDI_Pos          (20U)
4627 #define FDCAN_IR_WDI_Msk          (0x1UL << FDCAN_IR_WDI_Pos)                  /*!< 0x00100000 */
4628 #define FDCAN_IR_WDI              FDCAN_IR_WDI_Msk                             /*!<Watchdog Interrupt                       */
4629 #define FDCAN_IR_PEA_Pos          (21U)
4630 #define FDCAN_IR_PEA_Msk          (0x1UL << FDCAN_IR_PEA_Pos)                  /*!< 0x00200000 */
4631 #define FDCAN_IR_PEA              FDCAN_IR_PEA_Msk                             /*!<Protocol Error in Arbitration Phase      */
4632 #define FDCAN_IR_PED_Pos          (22U)
4633 #define FDCAN_IR_PED_Msk          (0x1UL << FDCAN_IR_PED_Pos)                  /*!< 0x00400000 */
4634 #define FDCAN_IR_PED              FDCAN_IR_PED_Msk                             /*!<Protocol Error in Data Phase             */
4635 #define FDCAN_IR_ARA_Pos          (23U)
4636 #define FDCAN_IR_ARA_Msk          (0x1UL << FDCAN_IR_ARA_Pos)                  /*!< 0x00800000 */
4637 #define FDCAN_IR_ARA              FDCAN_IR_ARA_Msk                             /*!<Access to Reserved Address               */
4638 
4639 /*****************  Bit definition for FDCAN_IE register  **********************/
4640 #define FDCAN_IE_RF0NE_Pos        (0U)
4641 #define FDCAN_IE_RF0NE_Msk        (0x1UL << FDCAN_IE_RF0NE_Pos)                /*!< 0x00000001 */
4642 #define FDCAN_IE_RF0NE            FDCAN_IE_RF0NE_Msk                           /*!<Rx FIFO 0 New Message Enable             */
4643 #define FDCAN_IE_RF0FE_Pos        (1U)
4644 #define FDCAN_IE_RF0FE_Msk        (0x1UL << FDCAN_IE_RF0FE_Pos)                /*!< 0x00000002 */
4645 #define FDCAN_IE_RF0FE            FDCAN_IE_RF0FE_Msk                           /*!<Rx FIFO 0 Full Enable                    */
4646 #define FDCAN_IE_RF0LE_Pos        (2U)
4647 #define FDCAN_IE_RF0LE_Msk        (0x1UL << FDCAN_IE_RF0LE_Pos)                /*!< 0x00000004 */
4648 #define FDCAN_IE_RF0LE            FDCAN_IE_RF0LE_Msk                           /*!<Rx FIFO 0 Message Lost Enable            */
4649 #define FDCAN_IE_RF1NE_Pos        (3U)
4650 #define FDCAN_IE_RF1NE_Msk        (0x1UL << FDCAN_IE_RF1NE_Pos)                /*!< 0x00000008 */
4651 #define FDCAN_IE_RF1NE            FDCAN_IE_RF1NE_Msk                           /*!<Rx FIFO 1 New Message Enable             */
4652 #define FDCAN_IE_RF1FE_Pos        (4U)
4653 #define FDCAN_IE_RF1FE_Msk        (0x1UL << FDCAN_IE_RF1FE_Pos)                /*!< 0x00000010 */
4654 #define FDCAN_IE_RF1FE            FDCAN_IE_RF1FE_Msk                           /*!<Rx FIFO 1 Full Enable                    */
4655 #define FDCAN_IE_RF1LE_Pos        (5U)
4656 #define FDCAN_IE_RF1LE_Msk        (0x1UL << FDCAN_IE_RF1LE_Pos)                /*!< 0x00000020 */
4657 #define FDCAN_IE_RF1LE            FDCAN_IE_RF1LE_Msk                           /*!<Rx FIFO 1 Message Lost Enable            */
4658 #define FDCAN_IE_HPME_Pos         (6U)
4659 #define FDCAN_IE_HPME_Msk         (0x1UL << FDCAN_IE_HPME_Pos)                 /*!< 0x00000040 */
4660 #define FDCAN_IE_HPME             FDCAN_IE_HPME_Msk                            /*!<High Priority Message Enable             */
4661 #define FDCAN_IE_TCE_Pos          (7U)
4662 #define FDCAN_IE_TCE_Msk          (0x1UL << FDCAN_IE_TCE_Pos)                  /*!< 0x00000080 */
4663 #define FDCAN_IE_TCE              FDCAN_IE_TCE_Msk                             /*!<Transmission Completed Enable            */
4664 #define FDCAN_IE_TCFE_Pos         (8U)
4665 #define FDCAN_IE_TCFE_Msk         (0x1UL << FDCAN_IE_TCFE_Pos)                 /*!< 0x00000100 */
4666 #define FDCAN_IE_TCFE             FDCAN_IE_TCFE_Msk                            /*!<Transmission Cancellation Finished Enable*/
4667 #define FDCAN_IE_TFEE_Pos         (9U)
4668 #define FDCAN_IE_TFEE_Msk         (0x1UL << FDCAN_IE_TFEE_Pos)                 /*!< 0x00000200 */
4669 #define FDCAN_IE_TFEE             FDCAN_IE_TFEE_Msk                            /*!<Tx FIFO Empty Enable                     */
4670 #define FDCAN_IE_TEFNE_Pos        (10U)
4671 #define FDCAN_IE_TEFNE_Msk        (0x1UL << FDCAN_IE_TEFNE_Pos)                /*!< 0x00000400 */
4672 #define FDCAN_IE_TEFNE            FDCAN_IE_TEFNE_Msk                           /*!<Tx Event FIFO New Entry Enable           */
4673 #define FDCAN_IE_TEFFE_Pos        (11U)
4674 #define FDCAN_IE_TEFFE_Msk        (0x1UL << FDCAN_IE_TEFFE_Pos)                /*!< 0x00000800 */
4675 #define FDCAN_IE_TEFFE            FDCAN_IE_TEFFE_Msk                           /*!<Tx Event FIFO Full Enable                */
4676 #define FDCAN_IE_TEFLE_Pos        (12U)
4677 #define FDCAN_IE_TEFLE_Msk        (0x1UL << FDCAN_IE_TEFLE_Pos)                /*!< 0x00001000 */
4678 #define FDCAN_IE_TEFLE            FDCAN_IE_TEFLE_Msk                           /*!<Tx Event FIFO Element Lost Enable        */
4679 #define FDCAN_IE_TSWE_Pos         (13U)
4680 #define FDCAN_IE_TSWE_Msk         (0x1UL << FDCAN_IE_TSWE_Pos)                 /*!< 0x00002000 */
4681 #define FDCAN_IE_TSWE             FDCAN_IE_TSWE_Msk                            /*!<Timestamp Wraparound Enable              */
4682 #define FDCAN_IE_MRAFE_Pos        (14U)
4683 #define FDCAN_IE_MRAFE_Msk        (0x1UL << FDCAN_IE_MRAFE_Pos)                /*!< 0x00004000 */
4684 #define FDCAN_IE_MRAFE            FDCAN_IE_MRAFE_Msk                           /*!<Message RAM Access Failure Enable        */
4685 #define FDCAN_IE_TOOE_Pos         (15U)
4686 #define FDCAN_IE_TOOE_Msk         (0x1UL << FDCAN_IE_TOOE_Pos)                 /*!< 0x00008000 */
4687 #define FDCAN_IE_TOOE             FDCAN_IE_TOOE_Msk                            /*!<Timeout Occurred Enable                  */
4688 #define FDCAN_IE_ELOE_Pos         (16U)
4689 #define FDCAN_IE_ELOE_Msk         (0x1UL << FDCAN_IE_ELOE_Pos)                 /*!< 0x00010000 */
4690 #define FDCAN_IE_ELOE             FDCAN_IE_ELOE_Msk                            /*!<Error Logging Overflow Enable            */
4691 #define FDCAN_IE_EPE_Pos          (17U)
4692 #define FDCAN_IE_EPE_Msk          (0x1UL << FDCAN_IE_EPE_Pos)                  /*!< 0x00020000 */
4693 #define FDCAN_IE_EPE              FDCAN_IE_EPE_Msk                             /*!<Error Passive Enable                     */
4694 #define FDCAN_IE_EWE_Pos          (18U)
4695 #define FDCAN_IE_EWE_Msk          (0x1UL << FDCAN_IE_EWE_Pos)                  /*!< 0x00040000 */
4696 #define FDCAN_IE_EWE              FDCAN_IE_EWE_Msk                             /*!<Warning Status Enable                    */
4697 #define FDCAN_IE_BOE_Pos          (19U)
4698 #define FDCAN_IE_BOE_Msk          (0x1UL << FDCAN_IE_BOE_Pos)                  /*!< 0x00080000 */
4699 #define FDCAN_IE_BOE              FDCAN_IE_BOE_Msk                             /*!<Bus_Off Status Enable                    */
4700 #define FDCAN_IE_WDIE_Pos         (20U)
4701 #define FDCAN_IE_WDIE_Msk         (0x1UL << FDCAN_IE_WDIE_Pos)                 /*!< 0x00100000 */
4702 #define FDCAN_IE_WDIE             FDCAN_IE_WDIE_Msk                            /*!<Watchdog Interrupt Enable                */
4703 #define FDCAN_IE_PEAE_Pos         (21U)
4704 #define FDCAN_IE_PEAE_Msk         (0x1UL << FDCAN_IE_PEAE_Pos)                 /*!< 0x00200000 */
4705 #define FDCAN_IE_PEAE             FDCAN_IE_PEAE_Msk                            /*!<Protocol Error in Arbitration Phase Enable*/
4706 #define FDCAN_IE_PEDE_Pos         (22U)
4707 #define FDCAN_IE_PEDE_Msk         (0x1UL << FDCAN_IE_PEDE_Pos)                 /*!< 0x00400000 */
4708 #define FDCAN_IE_PEDE             FDCAN_IE_PEDE_Msk                            /*!<Protocol Error in Data Phase Enable      */
4709 #define FDCAN_IE_ARAE_Pos         (23U)
4710 #define FDCAN_IE_ARAE_Msk         (0x1UL << FDCAN_IE_ARAE_Pos)                 /*!< 0x00800000 */
4711 #define FDCAN_IE_ARAE             FDCAN_IE_ARAE_Msk                            /*!<Access to Reserved Address Enable        */
4712 
4713 /*****************  Bit definition for FDCAN_ILS register  **********************/
4714 #define FDCAN_ILS_RXFIFO0_Pos     (0U)
4715 #define FDCAN_ILS_RXFIFO0_Msk     (0x1UL << FDCAN_ILS_RXFIFO0_Pos)             /*!< 0x00000001 */
4716 #define FDCAN_ILS_RXFIFO0         FDCAN_ILS_RXFIFO0_Msk                        /*!<Rx FIFO 0 Message Lost
4717                                                                                    Rx FIFO 0 is Full
4718                                                                                    Rx FIFO 0 Has New Message                */
4719 #define FDCAN_ILS_RXFIFO1_Pos     (1U)
4720 #define FDCAN_ILS_RXFIFO1_Msk     (0x1UL << FDCAN_ILS_RXFIFO1_Pos)             /*!< 0x00000002 */
4721 #define FDCAN_ILS_RXFIFO1         FDCAN_ILS_RXFIFO1_Msk                        /*!<Rx FIFO 1 Message Lost
4722                                                                                    Rx FIFO 1 is Full
4723                                                                                    Rx FIFO 1 Has New Message                */
4724 #define FDCAN_ILS_SMSG_Pos        (2U)
4725 #define FDCAN_ILS_SMSG_Msk        (0x1UL << FDCAN_ILS_SMSG_Pos)                /*!< 0x00000004 */
4726 #define FDCAN_ILS_SMSG            FDCAN_ILS_SMSG_Msk                           /*!<Transmission Cancellation Finished
4727                                                                                    Transmission Completed
4728                                                                                    High Priority Message                    */
4729 #define FDCAN_ILS_TFERR_Pos       (3U)
4730 #define FDCAN_ILS_TFERR_Msk       (0x1UL << FDCAN_ILS_TFERR_Pos)               /*!< 0x00000008 */
4731 #define FDCAN_ILS_TFERR           FDCAN_ILS_TFERR_Msk                          /*!<Tx Event FIFO Element Lost
4732                                                                                    Tx Event FIFO Full
4733                                                                                    Tx Event FIFO New Entry
4734                                                                                    Tx FIFO Empty Interrupt Line             */
4735 #define FDCAN_ILS_MISC_Pos        (4U)
4736 #define FDCAN_ILS_MISC_Msk        (0x1UL << FDCAN_ILS_MISC_Pos)                /*!< 0x00000010 */
4737 #define FDCAN_ILS_MISC            FDCAN_ILS_MISC_Msk                           /*!<Timeout Occurred
4738                                                                                     Message RAM Access Failure
4739                                                                                     Timestamp Wraparound                    */
4740 #define FDCAN_ILS_BERR_Pos        (5U)
4741 #define FDCAN_ILS_BERR_Msk        (0x1UL << FDCAN_ILS_BERR_Pos)                /*!< 0x00000020 */
4742 #define FDCAN_ILS_BERR            FDCAN_ILS_BERR_Msk                           /*!<Error Passive
4743                                                                                    Error Logging Overflow                   */
4744 #define FDCAN_ILS_PERR_Pos        (6U)
4745 #define FDCAN_ILS_PERR_Msk        (0x1UL << FDCAN_ILS_PERR_Pos)                /*!< 0x00000040 */
4746 #define FDCAN_ILS_PERR            FDCAN_ILS_PERR_Msk                           /*!<Access to Reserved Address Line
4747                                                                                    Protocol Error in Data Phase Line
4748                                                                                    Protocol Error in Arbitration Phase Line
4749                                                                                    Watchdog Interrupt Line
4750                                                                                    Bus_Off Status
4751                                                                                    Warning Status                           */
4752 
4753 /*****************  Bit definition for FDCAN_ILE register  **********************/
4754 #define FDCAN_ILE_EINT0_Pos       (0U)
4755 #define FDCAN_ILE_EINT0_Msk       (0x1UL << FDCAN_ILE_EINT0_Pos)               /*!< 0x00000001 */
4756 #define FDCAN_ILE_EINT0           FDCAN_ILE_EINT0_Msk                          /*!<Enable Interrupt Line 0                  */
4757 #define FDCAN_ILE_EINT1_Pos       (1U)
4758 #define FDCAN_ILE_EINT1_Msk       (0x1UL << FDCAN_ILE_EINT1_Pos)               /*!< 0x00000002 */
4759 #define FDCAN_ILE_EINT1           FDCAN_ILE_EINT1_Msk                          /*!<Enable Interrupt Line 1                  */
4760 
4761 /*****************  Bit definition for FDCAN_RXGFC register  ********************/
4762 #define FDCAN_RXGFC_RRFE_Pos      (0U)
4763 #define FDCAN_RXGFC_RRFE_Msk      (0x1UL << FDCAN_RXGFC_RRFE_Pos)              /*!< 0x00000001 */
4764 #define FDCAN_RXGFC_RRFE          FDCAN_RXGFC_RRFE_Msk                         /*!<Reject Remote Frames Extended            */
4765 #define FDCAN_RXGFC_RRFS_Pos      (1U)
4766 #define FDCAN_RXGFC_RRFS_Msk      (0x1UL << FDCAN_RXGFC_RRFS_Pos)              /*!< 0x00000002 */
4767 #define FDCAN_RXGFC_RRFS          FDCAN_RXGFC_RRFS_Msk                         /*!<Reject Remote Frames Standard            */
4768 #define FDCAN_RXGFC_ANFE_Pos      (2U)
4769 #define FDCAN_RXGFC_ANFE_Msk      (0x3UL << FDCAN_RXGFC_ANFE_Pos)              /*!< 0x0000000C */
4770 #define FDCAN_RXGFC_ANFE          FDCAN_RXGFC_ANFE_Msk                         /*!<Accept Non-matching Frames Extended      */
4771 #define FDCAN_RXGFC_ANFS_Pos      (4U)
4772 #define FDCAN_RXGFC_ANFS_Msk      (0x3UL << FDCAN_RXGFC_ANFS_Pos)              /*!< 0x00000030 */
4773 #define FDCAN_RXGFC_ANFS          FDCAN_RXGFC_ANFS_Msk                         /*!<Accept Non-matching Frames Standard      */
4774 #define FDCAN_RXGFC_F1OM_Pos      (8U)
4775 #define FDCAN_RXGFC_F1OM_Msk      (0x1UL << FDCAN_RXGFC_F1OM_Pos)              /*!< 0x00000100 */
4776 #define FDCAN_RXGFC_F1OM          FDCAN_RXGFC_F1OM_Msk                         /*!<FIFO 1 operation mode                    */
4777 #define FDCAN_RXGFC_F0OM_Pos      (9U)
4778 #define FDCAN_RXGFC_F0OM_Msk      (0x1UL << FDCAN_RXGFC_F0OM_Pos)              /*!< 0x00000200 */
4779 #define FDCAN_RXGFC_F0OM          FDCAN_RXGFC_F0OM_Msk                         /*!<FIFO 0 operation mode                    */
4780 #define FDCAN_RXGFC_LSS_Pos       (16U)
4781 #define FDCAN_RXGFC_LSS_Msk       (0x1FUL << FDCAN_RXGFC_LSS_Pos)              /*!< 0x001F0000 */
4782 #define FDCAN_RXGFC_LSS           FDCAN_RXGFC_LSS_Msk                          /*!<List Size Standard                       */
4783 #define FDCAN_RXGFC_LSE_Pos       (24U)
4784 #define FDCAN_RXGFC_LSE_Msk       (0xFUL << FDCAN_RXGFC_LSE_Pos)               /*!< 0x0F000000 */
4785 #define FDCAN_RXGFC_LSE           FDCAN_RXGFC_LSE_Msk                          /*!<List Size Extended                       */
4786 
4787 /*****************  Bit definition for FDCAN_XIDAM register  ********************/
4788 #define FDCAN_XIDAM_EIDM_Pos      (0U)
4789 #define FDCAN_XIDAM_EIDM_Msk      (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)       /*!< 0x1FFFFFFF */
4790 #define FDCAN_XIDAM_EIDM          FDCAN_XIDAM_EIDM_Msk                         /*!<Extended ID Mask                         */
4791 
4792 /*****************  Bit definition for FDCAN_HPMS register  *********************/
4793 #define FDCAN_HPMS_BIDX_Pos       (0U)
4794 #define FDCAN_HPMS_BIDX_Msk       (0x7UL << FDCAN_HPMS_BIDX_Pos)               /*!< 0x00000007 */
4795 #define FDCAN_HPMS_BIDX           FDCAN_HPMS_BIDX_Msk                          /*!<Buffer Index                             */
4796 #define FDCAN_HPMS_MSI_Pos        (6U)
4797 #define FDCAN_HPMS_MSI_Msk        (0x3UL << FDCAN_HPMS_MSI_Pos)                /*!< 0x000000C0 */
4798 #define FDCAN_HPMS_MSI            FDCAN_HPMS_MSI_Msk                           /*!<Message Storage Indicator                */
4799 #define FDCAN_HPMS_FIDX_Pos       (8U)
4800 #define FDCAN_HPMS_FIDX_Msk       (0x1FUL << FDCAN_HPMS_FIDX_Pos)              /*!< 0x00001F00 */
4801 #define FDCAN_HPMS_FIDX           FDCAN_HPMS_FIDX_Msk                          /*!<Filter Index                             */
4802 #define FDCAN_HPMS_FLST_Pos       (15U)
4803 #define FDCAN_HPMS_FLST_Msk       (0x1UL << FDCAN_HPMS_FLST_Pos)               /*!< 0x00008000 */
4804 #define FDCAN_HPMS_FLST           FDCAN_HPMS_FLST_Msk                          /*!<Filter List                              */
4805 
4806 /*****************  Bit definition for FDCAN_RXF0S register  ********************/
4807 #define FDCAN_RXF0S_F0FL_Pos      (0U)
4808 #define FDCAN_RXF0S_F0FL_Msk      (0xFUL << FDCAN_RXF0S_F0FL_Pos)              /*!< 0x0000000F */
4809 #define FDCAN_RXF0S_F0FL          FDCAN_RXF0S_F0FL_Msk                         /*!<Rx FIFO 0 Fill Level                     */
4810 #define FDCAN_RXF0S_F0GI_Pos      (8U)
4811 #define FDCAN_RXF0S_F0GI_Msk      (0x3UL << FDCAN_RXF0S_F0GI_Pos)              /*!< 0x00000300 */
4812 #define FDCAN_RXF0S_F0GI          FDCAN_RXF0S_F0GI_Msk                         /*!<Rx FIFO 0 Get Index                      */
4813 #define FDCAN_RXF0S_F0PI_Pos      (16U)
4814 #define FDCAN_RXF0S_F0PI_Msk      (0x3UL << FDCAN_RXF0S_F0PI_Pos)              /*!< 0x00030000 */
4815 #define FDCAN_RXF0S_F0PI          FDCAN_RXF0S_F0PI_Msk                         /*!<Rx FIFO 0 Put Index                      */
4816 #define FDCAN_RXF0S_F0F_Pos       (24U)
4817 #define FDCAN_RXF0S_F0F_Msk       (0x1UL << FDCAN_RXF0S_F0F_Pos)               /*!< 0x01000000 */
4818 #define FDCAN_RXF0S_F0F           FDCAN_RXF0S_F0F_Msk                          /*!<Rx FIFO 0 Full                           */
4819 #define FDCAN_RXF0S_RF0L_Pos      (25U)
4820 #define FDCAN_RXF0S_RF0L_Msk      (0x1UL << FDCAN_RXF0S_RF0L_Pos)              /*!< 0x02000000 */
4821 #define FDCAN_RXF0S_RF0L          FDCAN_RXF0S_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                   */
4822 
4823 /*****************  Bit definition for FDCAN_RXF0A register  ********************/
4824 #define FDCAN_RXF0A_F0AI_Pos      (0U)
4825 #define FDCAN_RXF0A_F0AI_Msk      (0x7UL << FDCAN_RXF0A_F0AI_Pos)              /*!< 0x00000007 */
4826 #define FDCAN_RXF0A_F0AI          FDCAN_RXF0A_F0AI_Msk                         /*!<Rx FIFO 0 Acknowledge Index              */
4827 
4828 /*****************  Bit definition for FDCAN_RXF1S register  ********************/
4829 #define FDCAN_RXF1S_F1FL_Pos      (0U)
4830 #define FDCAN_RXF1S_F1FL_Msk      (0xFUL << FDCAN_RXF1S_F1FL_Pos)              /*!< 0x0000000F */
4831 #define FDCAN_RXF1S_F1FL          FDCAN_RXF1S_F1FL_Msk                         /*!<Rx FIFO 1 Fill Level                     */
4832 #define FDCAN_RXF1S_F1GI_Pos      (8U)
4833 #define FDCAN_RXF1S_F1GI_Msk      (0x3UL << FDCAN_RXF1S_F1GI_Pos)              /*!< 0x00000300 */
4834 #define FDCAN_RXF1S_F1GI          FDCAN_RXF1S_F1GI_Msk                         /*!<Rx FIFO 1 Get Index                      */
4835 #define FDCAN_RXF1S_F1PI_Pos      (16U)
4836 #define FDCAN_RXF1S_F1PI_Msk      (0x3UL << FDCAN_RXF1S_F1PI_Pos)              /*!< 0x00030000 */
4837 #define FDCAN_RXF1S_F1PI          FDCAN_RXF1S_F1PI_Msk                         /*!<Rx FIFO 1 Put Index                      */
4838 #define FDCAN_RXF1S_F1F_Pos       (24U)
4839 #define FDCAN_RXF1S_F1F_Msk       (0x1UL << FDCAN_RXF1S_F1F_Pos)               /*!< 0x01000000 */
4840 #define FDCAN_RXF1S_F1F           FDCAN_RXF1S_F1F_Msk                          /*!<Rx FIFO 1 Full                           */
4841 #define FDCAN_RXF1S_RF1L_Pos      (25U)
4842 #define FDCAN_RXF1S_RF1L_Msk      (0x1UL << FDCAN_RXF1S_RF1L_Pos)              /*!< 0x02000000 */
4843 #define FDCAN_RXF1S_RF1L          FDCAN_RXF1S_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                   */
4844 
4845 /*****************  Bit definition for FDCAN_RXF1A register  ********************/
4846 #define FDCAN_RXF1A_F1AI_Pos      (0U)
4847 #define FDCAN_RXF1A_F1AI_Msk      (0x7UL << FDCAN_RXF1A_F1AI_Pos)              /*!< 0x00000007 */
4848 #define FDCAN_RXF1A_F1AI          FDCAN_RXF1A_F1AI_Msk                         /*!<Rx FIFO 1 Acknowledge Index              */
4849 
4850 /*****************  Bit definition for FDCAN_TXBC register  *********************/
4851 #define FDCAN_TXBC_TFQM_Pos       (24U)
4852 #define FDCAN_TXBC_TFQM_Msk       (0x1UL << FDCAN_TXBC_TFQM_Pos)               /*!< 0x01000000 */
4853 #define FDCAN_TXBC_TFQM           FDCAN_TXBC_TFQM_Msk                          /*!<Tx FIFO/Queue Mode                       */
4854 
4855 /*****************  Bit definition for FDCAN_TXFQS register  *********************/
4856 #define FDCAN_TXFQS_TFFL_Pos      (0U)
4857 #define FDCAN_TXFQS_TFFL_Msk      (0x7UL << FDCAN_TXFQS_TFFL_Pos)              /*!< 0x00000007 */
4858 #define FDCAN_TXFQS_TFFL          FDCAN_TXFQS_TFFL_Msk                         /*!<Tx FIFO Free Level                       */
4859 #define FDCAN_TXFQS_TFGI_Pos      (8U)
4860 #define FDCAN_TXFQS_TFGI_Msk      (0x3UL << FDCAN_TXFQS_TFGI_Pos)              /*!< 0x00000300 */
4861 #define FDCAN_TXFQS_TFGI          FDCAN_TXFQS_TFGI_Msk                         /*!<Tx FIFO Get Index                        */
4862 #define FDCAN_TXFQS_TFQPI_Pos     (16U)
4863 #define FDCAN_TXFQS_TFQPI_Msk     (0x3UL << FDCAN_TXFQS_TFQPI_Pos)             /*!< 0x00030000 */
4864 #define FDCAN_TXFQS_TFQPI         FDCAN_TXFQS_TFQPI_Msk                        /*!<Tx FIFO/Queue Put Index                  */
4865 #define FDCAN_TXFQS_TFQF_Pos      (21U)
4866 #define FDCAN_TXFQS_TFQF_Msk      (0x1UL << FDCAN_TXFQS_TFQF_Pos)              /*!< 0x00200000 */
4867 #define FDCAN_TXFQS_TFQF          FDCAN_TXFQS_TFQF_Msk                         /*!<Tx FIFO/Queue Full                       */
4868 
4869 /*****************  Bit definition for FDCAN_TXBRP register  *********************/
4870 #define FDCAN_TXBRP_TRP_Pos       (0U)
4871 #define FDCAN_TXBRP_TRP_Msk       (0x7UL << FDCAN_TXBRP_TRP_Pos)               /*!< 0x00000007 */
4872 #define FDCAN_TXBRP_TRP           FDCAN_TXBRP_TRP_Msk                          /*!<Transmission Request Pending             */
4873 
4874 /*****************  Bit definition for FDCAN_TXBAR register  *********************/
4875 #define FDCAN_TXBAR_AR_Pos        (0U)
4876 #define FDCAN_TXBAR_AR_Msk        (0x7UL << FDCAN_TXBAR_AR_Pos)                /*!< 0x00000007 */
4877 #define FDCAN_TXBAR_AR            FDCAN_TXBAR_AR_Msk                           /*!<Add Request                              */
4878 
4879 /*****************  Bit definition for FDCAN_TXBCR register  *********************/
4880 #define FDCAN_TXBCR_CR_Pos        (0U)
4881 #define FDCAN_TXBCR_CR_Msk        (0x7UL << FDCAN_TXBCR_CR_Pos)                /*!< 0x00000007 */
4882 #define FDCAN_TXBCR_CR            FDCAN_TXBCR_CR_Msk                           /*!<Cancellation Request                     */
4883 
4884 /*****************  Bit definition for FDCAN_TXBTO register  *********************/
4885 #define FDCAN_TXBTO_TO_Pos        (0U)
4886 #define FDCAN_TXBTO_TO_Msk        (0x7UL << FDCAN_TXBTO_TO_Pos)                /*!< 0x00000007 */
4887 #define FDCAN_TXBTO_TO            FDCAN_TXBTO_TO_Msk                           /*!<Transmission Occurred                    */
4888 
4889 /*****************  Bit definition for FDCAN_TXBCF register  *********************/
4890 #define FDCAN_TXBCF_CF_Pos        (0U)
4891 #define FDCAN_TXBCF_CF_Msk        (0x7UL << FDCAN_TXBCF_CF_Pos)                /*!< 0x00000007 */
4892 #define FDCAN_TXBCF_CF            FDCAN_TXBCF_CF_Msk                           /*!<Cancellation Finished                    */
4893 
4894 /*****************  Bit definition for FDCAN_TXBTIE register  ********************/
4895 #define FDCAN_TXBTIE_TIE_Pos      (0U)
4896 #define FDCAN_TXBTIE_TIE_Msk      (0x7UL << FDCAN_TXBTIE_TIE_Pos)              /*!< 0x00000007 */
4897 #define FDCAN_TXBTIE_TIE          FDCAN_TXBTIE_TIE_Msk                         /*!<Transmission Interrupt Enable            */
4898 
4899 /*****************  Bit definition for FDCAN_ TXBCIE register  *******************/
4900 #define FDCAN_TXBCIE_CFIE_Pos     (0U)
4901 #define FDCAN_TXBCIE_CFIE_Msk     (0x7UL << FDCAN_TXBCIE_CFIE_Pos)             /*!< 0x00000007 */
4902 #define FDCAN_TXBCIE_CFIE         FDCAN_TXBCIE_CFIE_Msk                        /*!<Cancellation Finished Interrupt Enable   */
4903 
4904 /*****************  Bit definition for FDCAN_TXEFS register  *********************/
4905 #define FDCAN_TXEFS_EFFL_Pos      (0U)
4906 #define FDCAN_TXEFS_EFFL_Msk      (0x7UL << FDCAN_TXEFS_EFFL_Pos)              /*!< 0x00000007 */
4907 #define FDCAN_TXEFS_EFFL          FDCAN_TXEFS_EFFL_Msk                         /*!<Event FIFO Fill Level                    */
4908 #define FDCAN_TXEFS_EFGI_Pos      (8U)
4909 #define FDCAN_TXEFS_EFGI_Msk      (0x3UL << FDCAN_TXEFS_EFGI_Pos)              /*!< 0x00000300 */
4910 #define FDCAN_TXEFS_EFGI          FDCAN_TXEFS_EFGI_Msk                         /*!<Event FIFO Get Index                     */
4911 #define FDCAN_TXEFS_EFPI_Pos      (16U)
4912 #define FDCAN_TXEFS_EFPI_Msk      (0x3UL << FDCAN_TXEFS_EFPI_Pos)              /*!< 0x00030000 */
4913 #define FDCAN_TXEFS_EFPI          FDCAN_TXEFS_EFPI_Msk                         /*!<Event FIFO Put Index                     */
4914 #define FDCAN_TXEFS_EFF_Pos       (24U)
4915 #define FDCAN_TXEFS_EFF_Msk       (0x1UL << FDCAN_TXEFS_EFF_Pos)               /*!< 0x01000000 */
4916 #define FDCAN_TXEFS_EFF           FDCAN_TXEFS_EFF_Msk                          /*!<Event FIFO Full                          */
4917 #define FDCAN_TXEFS_TEFL_Pos      (25U)
4918 #define FDCAN_TXEFS_TEFL_Msk      (0x1UL << FDCAN_TXEFS_TEFL_Pos)              /*!< 0x02000000 */
4919 #define FDCAN_TXEFS_TEFL          FDCAN_TXEFS_TEFL_Msk                         /*!<Tx Event FIFO Element Lost               */
4920 
4921 /*****************  Bit definition for FDCAN_TXEFA register  *********************/
4922 #define FDCAN_TXEFA_EFAI_Pos      (0U)
4923 #define FDCAN_TXEFA_EFAI_Msk      (0x3UL << FDCAN_TXEFA_EFAI_Pos)              /*!< 0x00000003 */
4924 #define FDCAN_TXEFA_EFAI          FDCAN_TXEFA_EFAI_Msk                         /*!<Event FIFO Acknowledge Index             */
4925 
4926 
4927 /*!<FDCAN config registers */
4928 /*****************  Bit definition for FDCAN_CKDIV register  *********************/
4929 #define FDCAN_CKDIV_PDIV_Pos      (0U)
4930 #define FDCAN_CKDIV_PDIV_Msk      (0xFUL << FDCAN_CKDIV_PDIV_Pos)              /*!< 0x0000000F */
4931 #define FDCAN_CKDIV_PDIV          FDCAN_CKDIV_PDIV_Msk                         /*!<Input Clock Divider                      */
4932 
4933 /******************************************************************************/
4934 /*                                                                            */
4935 /*                                    FLASH                                   */
4936 /*                                                                            */
4937 /******************************************************************************/
4938 /*******************  Bits definition for FLASH_ACR register  *****************/
4939 #define FLASH_ACR_LATENCY_Pos             (0U)
4940 #define FLASH_ACR_LATENCY_Msk             (0xFUL << FLASH_ACR_LATENCY_Pos)     /*!< 0x0000000F */
4941 #define FLASH_ACR_LATENCY                 FLASH_ACR_LATENCY_Msk
4942 #define FLASH_ACR_LATENCY_0WS             (0x00000000U)
4943 #define FLASH_ACR_LATENCY_1WS             (0x00000001U)
4944 #define FLASH_ACR_LATENCY_2WS             (0x00000002U)
4945 #define FLASH_ACR_LATENCY_3WS             (0x00000003U)
4946 #define FLASH_ACR_LATENCY_4WS             (0x00000004U)
4947 #define FLASH_ACR_LATENCY_5WS             (0x00000005U)
4948 #define FLASH_ACR_LATENCY_6WS             (0x00000006U)
4949 #define FLASH_ACR_LATENCY_7WS             (0x00000007U)
4950 #define FLASH_ACR_LATENCY_8WS             (0x00000008U)
4951 #define FLASH_ACR_LATENCY_9WS             (0x00000009U)
4952 #define FLASH_ACR_LATENCY_10WS            (0x0000000AU)
4953 #define FLASH_ACR_LATENCY_11WS            (0x0000000BU)
4954 #define FLASH_ACR_LATENCY_12WS            (0x0000000CU)
4955 #define FLASH_ACR_LATENCY_13WS            (0x0000000DU)
4956 #define FLASH_ACR_LATENCY_14WS            (0x0000000EU)
4957 #define FLASH_ACR_LATENCY_15WS            (0x0000000FU)
4958 #define FLASH_ACR_PRFTEN_Pos              (8U)
4959 #define FLASH_ACR_PRFTEN_Msk              (0x1UL << FLASH_ACR_PRFTEN_Pos)      /*!< 0x00000100 */
4960 #define FLASH_ACR_PRFTEN                  FLASH_ACR_PRFTEN_Msk
4961 #define FLASH_ACR_ICEN_Pos                (9U)
4962 #define FLASH_ACR_ICEN_Msk                (0x1UL << FLASH_ACR_ICEN_Pos)        /*!< 0x00000200 */
4963 #define FLASH_ACR_ICEN                    FLASH_ACR_ICEN_Msk
4964 #define FLASH_ACR_DCEN_Pos                (10U)
4965 #define FLASH_ACR_DCEN_Msk                (0x1UL << FLASH_ACR_DCEN_Pos)        /*!< 0x00000400 */
4966 #define FLASH_ACR_DCEN                    FLASH_ACR_DCEN_Msk
4967 #define FLASH_ACR_ICRST_Pos               (11U)
4968 #define FLASH_ACR_ICRST_Msk               (0x1UL << FLASH_ACR_ICRST_Pos)       /*!< 0x00000800 */
4969 #define FLASH_ACR_ICRST                   FLASH_ACR_ICRST_Msk
4970 #define FLASH_ACR_DCRST_Pos               (12U)
4971 #define FLASH_ACR_DCRST_Msk               (0x1UL << FLASH_ACR_DCRST_Pos)       /*!< 0x00001000 */
4972 #define FLASH_ACR_DCRST                   FLASH_ACR_DCRST_Msk
4973 #define FLASH_ACR_RUN_PD_Pos              (13U)
4974 #define FLASH_ACR_RUN_PD_Msk              (0x1UL << FLASH_ACR_RUN_PD_Pos)      /*!< 0x00002000 */
4975 #define FLASH_ACR_RUN_PD                  FLASH_ACR_RUN_PD_Msk                 /*!< Flash power down mode during run */
4976 #define FLASH_ACR_SLEEP_PD_Pos            (14U)
4977 #define FLASH_ACR_SLEEP_PD_Msk            (0x1UL << FLASH_ACR_SLEEP_PD_Pos)    /*!< 0x00004000 */
4978 #define FLASH_ACR_SLEEP_PD                FLASH_ACR_SLEEP_PD_Msk               /*!< Flash power down mode during sleep */
4979 #define FLASH_ACR_DBG_SWEN_Pos            (18U)
4980 #define FLASH_ACR_DBG_SWEN_Msk            (0x1UL << FLASH_ACR_DBG_SWEN_Pos)    /*!< 0x00040000 */
4981 #define FLASH_ACR_DBG_SWEN                FLASH_ACR_DBG_SWEN_Msk               /*!< Software disable for debugger */
4982 
4983 /*******************  Bits definition for FLASH_SR register  ******************/
4984 #define FLASH_SR_EOP_Pos                  (0U)
4985 #define FLASH_SR_EOP_Msk                  (0x1UL << FLASH_SR_EOP_Pos)          /*!< 0x00000001 */
4986 #define FLASH_SR_EOP                      FLASH_SR_EOP_Msk
4987 #define FLASH_SR_OPERR_Pos                (1U)
4988 #define FLASH_SR_OPERR_Msk                (0x1UL << FLASH_SR_OPERR_Pos)        /*!< 0x00000002 */
4989 #define FLASH_SR_OPERR                    FLASH_SR_OPERR_Msk
4990 #define FLASH_SR_PROGERR_Pos              (3U)
4991 #define FLASH_SR_PROGERR_Msk              (0x1UL << FLASH_SR_PROGERR_Pos)      /*!< 0x00000008 */
4992 #define FLASH_SR_PROGERR                  FLASH_SR_PROGERR_Msk
4993 #define FLASH_SR_WRPERR_Pos               (4U)
4994 #define FLASH_SR_WRPERR_Msk               (0x1UL << FLASH_SR_WRPERR_Pos)       /*!< 0x00000010 */
4995 #define FLASH_SR_WRPERR                   FLASH_SR_WRPERR_Msk
4996 #define FLASH_SR_PGAERR_Pos               (5U)
4997 #define FLASH_SR_PGAERR_Msk               (0x1UL << FLASH_SR_PGAERR_Pos)       /*!< 0x00000020 */
4998 #define FLASH_SR_PGAERR                   FLASH_SR_PGAERR_Msk
4999 #define FLASH_SR_SIZERR_Pos               (6U)
5000 #define FLASH_SR_SIZERR_Msk               (0x1UL << FLASH_SR_SIZERR_Pos)       /*!< 0x00000040 */
5001 #define FLASH_SR_SIZERR                   FLASH_SR_SIZERR_Msk
5002 #define FLASH_SR_PGSERR_Pos               (7U)
5003 #define FLASH_SR_PGSERR_Msk               (0x1UL << FLASH_SR_PGSERR_Pos)       /*!< 0x00000080 */
5004 #define FLASH_SR_PGSERR                   FLASH_SR_PGSERR_Msk
5005 #define FLASH_SR_MISERR_Pos               (8U)
5006 #define FLASH_SR_MISERR_Msk               (0x1UL << FLASH_SR_MISERR_Pos)       /*!< 0x00000100 */
5007 #define FLASH_SR_MISERR                   FLASH_SR_MISERR_Msk
5008 #define FLASH_SR_FASTERR_Pos              (9U)
5009 #define FLASH_SR_FASTERR_Msk              (0x1UL << FLASH_SR_FASTERR_Pos)      /*!< 0x00000200 */
5010 #define FLASH_SR_FASTERR                  FLASH_SR_FASTERR_Msk
5011 #define FLASH_SR_RDERR_Pos                (14U)
5012 #define FLASH_SR_RDERR_Msk                (0x1UL << FLASH_SR_RDERR_Pos)        /*!< 0x00004000 */
5013 #define FLASH_SR_RDERR                    FLASH_SR_RDERR_Msk
5014 #define FLASH_SR_OPTVERR_Pos              (15U)
5015 #define FLASH_SR_OPTVERR_Msk              (0x1UL << FLASH_SR_OPTVERR_Pos)      /*!< 0x00008000 */
5016 #define FLASH_SR_OPTVERR                  FLASH_SR_OPTVERR_Msk
5017 #define FLASH_SR_BSY_Pos                  (16U)
5018 #define FLASH_SR_BSY_Msk                  (0x1UL << FLASH_SR_BSY_Pos)          /*!< 0x00010000 */
5019 #define FLASH_SR_BSY                      FLASH_SR_BSY_Msk
5020 
5021 /*******************  Bits definition for FLASH_CR register  ******************/
5022 #define FLASH_CR_PG_Pos                   (0U)
5023 #define FLASH_CR_PG_Msk                   (0x1UL << FLASH_CR_PG_Pos)           /*!< 0x00000001 */
5024 #define FLASH_CR_PG                       FLASH_CR_PG_Msk
5025 #define FLASH_CR_PER_Pos                  (1U)
5026 #define FLASH_CR_PER_Msk                  (0x1UL << FLASH_CR_PER_Pos)          /*!< 0x00000002 */
5027 #define FLASH_CR_PER                      FLASH_CR_PER_Msk
5028 #define FLASH_CR_MER1_Pos                 (2U)
5029 #define FLASH_CR_MER1_Msk                 (0x1UL << FLASH_CR_MER1_Pos)         /*!< 0x00000004 */
5030 #define FLASH_CR_MER1                     FLASH_CR_MER1_Msk
5031 #define FLASH_CR_PNB_Pos                  (3U)
5032 #define FLASH_CR_PNB_Msk                  (0x7FUL << FLASH_CR_PNB_Pos)         /*!< 0x000003F8 */
5033 #define FLASH_CR_PNB                      FLASH_CR_PNB_Msk
5034 #define FLASH_CR_BKER_Pos                 (11U)
5035 #define FLASH_CR_BKER_Msk                 (0x1UL << FLASH_CR_BKER_Pos)         /*!< 0x00000800 */
5036 #define FLASH_CR_BKER                     FLASH_CR_BKER_Msk
5037 #define FLASH_CR_MER2_Pos                 (15U)
5038 #define FLASH_CR_MER2_Msk                 (0x1UL << FLASH_CR_MER2_Pos)         /*!< 0x00008000 */
5039 #define FLASH_CR_MER2                     FLASH_CR_MER2_Msk
5040 #define FLASH_CR_STRT_Pos                 (16U)
5041 #define FLASH_CR_STRT_Msk                 (0x1UL << FLASH_CR_STRT_Pos)         /*!< 0x00010000 */
5042 #define FLASH_CR_STRT                     FLASH_CR_STRT_Msk
5043 #define FLASH_CR_OPTSTRT_Pos              (17U)
5044 #define FLASH_CR_OPTSTRT_Msk              (0x1UL << FLASH_CR_OPTSTRT_Pos)      /*!< 0x00020000 */
5045 #define FLASH_CR_OPTSTRT                  FLASH_CR_OPTSTRT_Msk
5046 #define FLASH_CR_FSTPG_Pos                (18U)
5047 #define FLASH_CR_FSTPG_Msk                (0x1UL << FLASH_CR_FSTPG_Pos)        /*!< 0x00040000 */
5048 #define FLASH_CR_FSTPG                    FLASH_CR_FSTPG_Msk
5049 #define FLASH_CR_EOPIE_Pos                (24U)
5050 #define FLASH_CR_EOPIE_Msk                (0x1UL << FLASH_CR_EOPIE_Pos)        /*!< 0x01000000 */
5051 #define FLASH_CR_EOPIE                    FLASH_CR_EOPIE_Msk
5052 #define FLASH_CR_ERRIE_Pos                (25U)
5053 #define FLASH_CR_ERRIE_Msk                (0x1UL << FLASH_CR_ERRIE_Pos)        /*!< 0x02000000 */
5054 #define FLASH_CR_ERRIE                    FLASH_CR_ERRIE_Msk
5055 #define FLASH_CR_RDERRIE_Pos              (26U)
5056 #define FLASH_CR_RDERRIE_Msk              (0x1UL << FLASH_CR_RDERRIE_Pos)      /*!< 0x04000000 */
5057 #define FLASH_CR_RDERRIE                  FLASH_CR_RDERRIE_Msk
5058 #define FLASH_CR_OBL_LAUNCH_Pos           (27U)
5059 #define FLASH_CR_OBL_LAUNCH_Msk           (0x1UL << FLASH_CR_OBL_LAUNCH_Pos)   /*!< 0x08000000 */
5060 #define FLASH_CR_OBL_LAUNCH               FLASH_CR_OBL_LAUNCH_Msk
5061 #define FLASH_CR_SEC_PROT1_Pos            (28U)
5062 #define FLASH_CR_SEC_PROT1_Msk            (0x1UL << FLASH_CR_SEC_PROT1_Pos)    /*!< 0x10000000 */
5063 #define FLASH_CR_SEC_PROT1                FLASH_CR_SEC_PROT1_Msk
5064 #define FLASH_CR_SEC_PROT2_Pos            (29U)
5065 #define FLASH_CR_SEC_PROT2_Msk            (0x1UL << FLASH_CR_SEC_PROT2_Pos)    /*!< 0x20000000 */
5066 #define FLASH_CR_SEC_PROT2                FLASH_CR_SEC_PROT2_Msk
5067 #define FLASH_CR_OPTLOCK_Pos              (30U)
5068 #define FLASH_CR_OPTLOCK_Msk              (0x1UL << FLASH_CR_OPTLOCK_Pos)      /*!< 0x40000000 */
5069 #define FLASH_CR_OPTLOCK                  FLASH_CR_OPTLOCK_Msk
5070 #define FLASH_CR_LOCK_Pos                 (31U)
5071 #define FLASH_CR_LOCK_Msk                 (0x1UL << FLASH_CR_LOCK_Pos)         /*!< 0x80000000 */
5072 #define FLASH_CR_LOCK                     FLASH_CR_LOCK_Msk
5073 
5074 /*******************  Bits definition for FLASH_ECCR register  ***************/
5075 #define FLASH_ECCR_ADDR_ECC_Pos           (0U)
5076 #define FLASH_ECCR_ADDR_ECC_Msk           (0x7FFFFUL << FLASH_ECCR_ADDR_ECC_Pos)/*!< 0x0007FFFF */
5077 #define FLASH_ECCR_ADDR_ECC               FLASH_ECCR_ADDR_ECC_Msk
5078 #define FLASH_ECCR_BK_ECC_Pos             (21U)
5079 #define FLASH_ECCR_BK_ECC_Msk             (0x1UL << FLASH_ECCR_BK_ECC_Pos)     /*!< 0x00200000 */
5080 #define FLASH_ECCR_BK_ECC                 FLASH_ECCR_BK_ECC_Msk
5081 #define FLASH_ECCR_SYSF_ECC_Pos           (22U)
5082 #define FLASH_ECCR_SYSF_ECC_Msk           (0x1UL << FLASH_ECCR_SYSF_ECC_Pos)   /*!< 0x00400000 */
5083 #define FLASH_ECCR_SYSF_ECC               FLASH_ECCR_SYSF_ECC_Msk
5084 #define FLASH_ECCR_ECCIE_Pos              (24U)
5085 #define FLASH_ECCR_ECCIE_Msk              (0x1UL << FLASH_ECCR_ECCIE_Pos)      /*!< 0x01000000 */
5086 #define FLASH_ECCR_ECCIE                  FLASH_ECCR_ECCIE_Msk
5087 #define FLASH_ECCR_ECCC2_Pos              (28U)
5088 #define FLASH_ECCR_ECCC2_Msk              (0x1UL << FLASH_ECCR_ECCC2_Pos)      /*!< 0x10000000 */
5089 #define FLASH_ECCR_ECCC2                  FLASH_ECCR_ECCC2_Msk
5090 #define FLASH_ECCR_ECCD2_Pos              (29U)
5091 #define FLASH_ECCR_ECCD2_Msk              (0x1UL << FLASH_ECCR_ECCD2_Pos)      /*!< 0x20000000 */
5092 #define FLASH_ECCR_ECCD2                  FLASH_ECCR_ECCD2_Msk
5093 #define FLASH_ECCR_ECCC_Pos               (30U)
5094 #define FLASH_ECCR_ECCC_Msk               (0x1UL << FLASH_ECCR_ECCC_Pos)       /*!< 0x40000000 */
5095 #define FLASH_ECCR_ECCC                   FLASH_ECCR_ECCC_Msk
5096 #define FLASH_ECCR_ECCD_Pos               (31U)
5097 #define FLASH_ECCR_ECCD_Msk               (0x1UL << FLASH_ECCR_ECCD_Pos)       /*!< 0x80000000 */
5098 #define FLASH_ECCR_ECCD                   FLASH_ECCR_ECCD_Msk
5099 
5100 /*******************  Bits definition for FLASH_OPTR register  ***************/
5101 #define FLASH_OPTR_RDP_Pos                (0U)
5102 #define FLASH_OPTR_RDP_Msk                (0xFFUL << FLASH_OPTR_RDP_Pos)       /*!< 0x000000FF */
5103 #define FLASH_OPTR_RDP                    FLASH_OPTR_RDP_Msk
5104 #define FLASH_OPTR_BOR_LEV_Pos            (8U)
5105 #define FLASH_OPTR_BOR_LEV_Msk            (0x7UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000700 */
5106 #define FLASH_OPTR_BOR_LEV                FLASH_OPTR_BOR_LEV_Msk
5107 #define FLASH_OPTR_BOR_LEV_0              (0x0UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000000 */
5108 #define FLASH_OPTR_BOR_LEV_1              (0x1UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000100 */
5109 #define FLASH_OPTR_BOR_LEV_2              (0x2UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000200 */
5110 #define FLASH_OPTR_BOR_LEV_3              (0x3UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000300 */
5111 #define FLASH_OPTR_BOR_LEV_4              (0x4UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000400 */
5112 #define FLASH_OPTR_nRST_STOP_Pos          (12U)
5113 #define FLASH_OPTR_nRST_STOP_Msk          (0x1UL << FLASH_OPTR_nRST_STOP_Pos)  /*!< 0x00001000 */
5114 #define FLASH_OPTR_nRST_STOP              FLASH_OPTR_nRST_STOP_Msk
5115 #define FLASH_OPTR_nRST_STDBY_Pos         (13U)
5116 #define FLASH_OPTR_nRST_STDBY_Msk         (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
5117 #define FLASH_OPTR_nRST_STDBY             FLASH_OPTR_nRST_STDBY_Msk
5118 #define FLASH_OPTR_nRST_SHDW_Pos          (14U)
5119 #define FLASH_OPTR_nRST_SHDW_Msk          (0x1UL << FLASH_OPTR_nRST_SHDW_Pos)  /*!< 0x00004000 */
5120 #define FLASH_OPTR_nRST_SHDW              FLASH_OPTR_nRST_SHDW_Msk
5121 #define FLASH_OPTR_IWDG_SW_Pos            (16U)
5122 #define FLASH_OPTR_IWDG_SW_Msk            (0x1UL << FLASH_OPTR_IWDG_SW_Pos)    /*!< 0x00010000 */
5123 #define FLASH_OPTR_IWDG_SW                FLASH_OPTR_IWDG_SW_Msk
5124 #define FLASH_OPTR_IWDG_STOP_Pos          (17U)
5125 #define FLASH_OPTR_IWDG_STOP_Msk          (0x1UL << FLASH_OPTR_IWDG_STOP_Pos)  /*!< 0x00020000 */
5126 #define FLASH_OPTR_IWDG_STOP              FLASH_OPTR_IWDG_STOP_Msk
5127 #define FLASH_OPTR_IWDG_STDBY_Pos         (18U)
5128 #define FLASH_OPTR_IWDG_STDBY_Msk         (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
5129 #define FLASH_OPTR_IWDG_STDBY             FLASH_OPTR_IWDG_STDBY_Msk
5130 #define FLASH_OPTR_WWDG_SW_Pos            (19U)
5131 #define FLASH_OPTR_WWDG_SW_Msk            (0x1UL << FLASH_OPTR_WWDG_SW_Pos)    /*!< 0x00080000 */
5132 #define FLASH_OPTR_WWDG_SW                FLASH_OPTR_WWDG_SW_Msk
5133 #define FLASH_OPTR_BFB2_Pos               (20U)
5134 #define FLASH_OPTR_BFB2_Msk               (0x1UL << FLASH_OPTR_BFB2_Pos)       /*!< 0x00100000 */
5135 #define FLASH_OPTR_BFB2                   FLASH_OPTR_BFB2_Msk
5136 #define FLASH_OPTR_DBANK_Pos              (22U)
5137 #define FLASH_OPTR_DBANK_Msk              (0x1UL << FLASH_OPTR_DBANK_Pos)      /*!< 0x00400000 */
5138 #define FLASH_OPTR_DBANK                  FLASH_OPTR_DBANK_Msk
5139 #define FLASH_OPTR_nBOOT1_Pos             (23U)
5140 #define FLASH_OPTR_nBOOT1_Msk             (0x1UL << FLASH_OPTR_nBOOT1_Pos)     /*!< 0x00800000 */
5141 #define FLASH_OPTR_nBOOT1                 FLASH_OPTR_nBOOT1_Msk
5142 #define FLASH_OPTR_SRAM_PE_Pos            (24U)
5143 #define FLASH_OPTR_SRAM_PE_Msk            (0x1UL << FLASH_OPTR_SRAM_PE_Pos)    /*!< 0x01000000 */
5144 #define FLASH_OPTR_SRAM_PE                FLASH_OPTR_SRAM_PE_Msk
5145 #define FLASH_OPTR_CCMSRAM_RST_Pos        (25U)
5146 #define FLASH_OPTR_CCMSRAM_RST_Msk        (0x1UL << FLASH_OPTR_CCMSRAM_RST_Pos)/*!< 0x02000000 */
5147 #define FLASH_OPTR_CCMSRAM_RST            FLASH_OPTR_CCMSRAM_RST_Msk
5148 #define FLASH_OPTR_nSWBOOT0_Pos           (26U)
5149 #define FLASH_OPTR_nSWBOOT0_Msk           (0x1UL << FLASH_OPTR_nSWBOOT0_Pos)   /*!< 0x04000000 */
5150 #define FLASH_OPTR_nSWBOOT0               FLASH_OPTR_nSWBOOT0_Msk
5151 #define FLASH_OPTR_nBOOT0_Pos             (27U)
5152 #define FLASH_OPTR_nBOOT0_Msk             (0x1UL << FLASH_OPTR_nBOOT0_Pos)     /*!< 0x08000000 */
5153 #define FLASH_OPTR_nBOOT0                 FLASH_OPTR_nBOOT0_Msk
5154 #define FLASH_OPTR_NRST_MODE_Pos          (28U)
5155 #define FLASH_OPTR_NRST_MODE_Msk          (0x3UL << FLASH_OPTR_NRST_MODE_Pos)  /*!< 0x30000000 */
5156 #define FLASH_OPTR_NRST_MODE              FLASH_OPTR_NRST_MODE_Msk
5157 #define FLASH_OPTR_NRST_MODE_0            (0x1UL << FLASH_OPTR_NRST_MODE_Pos)  /*!< 0x10000000 */
5158 #define FLASH_OPTR_NRST_MODE_1            (0x2UL << FLASH_OPTR_NRST_MODE_Pos)  /*!< 0x20000000 */
5159 #define FLASH_OPTR_IRHEN_Pos              (30U)
5160 #define FLASH_OPTR_IRHEN_Msk              (0x1UL << FLASH_OPTR_IRHEN_Pos)      /*!< 0x40000000 */
5161 #define FLASH_OPTR_IRHEN                  FLASH_OPTR_IRHEN_Msk
5162 
5163 /******************  Bits definition for FLASH_PCROP1SR register  **********/
5164 #define FLASH_PCROP1SR_PCROP1_STRT_Pos    (0U)
5165 #define FLASH_PCROP1SR_PCROP1_STRT_Msk    (0x7FFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos)/*!< 0x00007FFF */
5166 #define FLASH_PCROP1SR_PCROP1_STRT        FLASH_PCROP1SR_PCROP1_STRT_Msk
5167 
5168 /******************  Bits definition for FLASH_PCROP1ER register  ***********/
5169 #define FLASH_PCROP1ER_PCROP1_END_Pos     (0U)
5170 #define FLASH_PCROP1ER_PCROP1_END_Msk     (0x7FFFUL << FLASH_PCROP1ER_PCROP1_END_Pos)/*!< 0x00007FFF */
5171 #define FLASH_PCROP1ER_PCROP1_END         FLASH_PCROP1ER_PCROP1_END_Msk
5172 #define FLASH_PCROP1ER_PCROP_RDP_Pos      (31U)
5173 #define FLASH_PCROP1ER_PCROP_RDP_Msk      (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos)/*!< 0x80000000 */
5174 #define FLASH_PCROP1ER_PCROP_RDP          FLASH_PCROP1ER_PCROP_RDP_Msk
5175 
5176 /******************  Bits definition for FLASH_WRP1AR register  ***************/
5177 #define FLASH_WRP1AR_WRP1A_STRT_Pos       (0U)
5178 #define FLASH_WRP1AR_WRP1A_STRT_Msk       (0x7FUL << FLASH_WRP1AR_WRP1A_STRT_Pos)/*!< 0x0000007F */
5179 #define FLASH_WRP1AR_WRP1A_STRT           FLASH_WRP1AR_WRP1A_STRT_Msk
5180 #define FLASH_WRP1AR_WRP1A_END_Pos        (16U)
5181 #define FLASH_WRP1AR_WRP1A_END_Msk        (0x7FUL << FLASH_WRP1AR_WRP1A_END_Pos)/*!< 0x007F0000 */
5182 #define FLASH_WRP1AR_WRP1A_END            FLASH_WRP1AR_WRP1A_END_Msk
5183 
5184 /******************  Bits definition for FLASH_WRPB1R register  ***************/
5185 #define FLASH_WRP1BR_WRP1B_STRT_Pos       (0U)
5186 #define FLASH_WRP1BR_WRP1B_STRT_Msk       (0x7FUL << FLASH_WRP1BR_WRP1B_STRT_Pos)/*!< 0x0000007F */
5187 #define FLASH_WRP1BR_WRP1B_STRT           FLASH_WRP1BR_WRP1B_STRT_Msk
5188 #define FLASH_WRP1BR_WRP1B_END_Pos        (16U)
5189 #define FLASH_WRP1BR_WRP1B_END_Msk        (0x7FUL << FLASH_WRP1BR_WRP1B_END_Pos)/*!< 0x007F0000 */
5190 #define FLASH_WRP1BR_WRP1B_END            FLASH_WRP1BR_WRP1B_END_Msk
5191 
5192 /******************  Bits definition for FLASH_PCROP2SR register  **********/
5193 #define FLASH_PCROP2SR_PCROP2_STRT_Pos    (0U)
5194 #define FLASH_PCROP2SR_PCROP2_STRT_Msk    (0x07FFFUL << FLASH_PCROP2SR_PCROP2_STRT_Pos)/*!< 0x00007FFF */
5195 #define FLASH_PCROP2SR_PCROP2_STRT        FLASH_PCROP2SR_PCROP2_STRT_Msk
5196 
5197 /******************  Bits definition for FLASH_PCROP2ER register  ***********/
5198 #define FLASH_PCROP2ER_PCROP2_END_Pos     (0U)
5199 #define FLASH_PCROP2ER_PCROP2_END_Msk     (0x07FFFUL << FLASH_PCROP2ER_PCROP2_END_Pos)/*!< 0x00007FFF */
5200 #define FLASH_PCROP2ER_PCROP2_END         FLASH_PCROP2ER_PCROP2_END_Msk
5201 
5202 /******************  Bits definition for FLASH_WRP2AR register  ***************/
5203 #define FLASH_WRP2AR_WRP2A_STRT_Pos       (0U)
5204 #define FLASH_WRP2AR_WRP2A_STRT_Msk       (0x7FUL << FLASH_WRP2AR_WRP2A_STRT_Pos)/*!< 0x000000FF */
5205 #define FLASH_WRP2AR_WRP2A_STRT           FLASH_WRP2AR_WRP2A_STRT_Msk
5206 #define FLASH_WRP2AR_WRP2A_END_Pos        (16U)
5207 #define FLASH_WRP2AR_WRP2A_END_Msk        (0x7FUL << FLASH_WRP2AR_WRP2A_END_Pos)/*!< 0x00FF0000 */
5208 #define FLASH_WRP2AR_WRP2A_END            FLASH_WRP2AR_WRP2A_END_Msk
5209 
5210 /******************  Bits definition for FLASH_WRP2BR register  ***************/
5211 #define FLASH_WRP2BR_WRP2B_STRT_Pos       (0U)
5212 #define FLASH_WRP2BR_WRP2B_STRT_Msk       (0x7FUL << FLASH_WRP2BR_WRP2B_STRT_Pos)/*!< 0x0000007F */
5213 #define FLASH_WRP2BR_WRP2B_STRT           FLASH_WRP2BR_WRP2B_STRT_Msk
5214 #define FLASH_WRP2BR_WRP2B_END_Pos        (16U)
5215 #define FLASH_WRP2BR_WRP2B_END_Msk        (0x7FUL << FLASH_WRP2BR_WRP2B_END_Pos)/*!< 0x007F0000 */
5216 #define FLASH_WRP2BR_WRP2B_END            FLASH_WRP2BR_WRP2B_END_Msk
5217 
5218 /******************  Bits definition for FLASH_SEC1R register  **************/
5219 #define FLASH_SEC1R_SEC_SIZE1_Pos         (0U)
5220 #define FLASH_SEC1R_SEC_SIZE1_Msk         (0xFFUL << FLASH_SEC1R_SEC_SIZE1_Pos)/*!< 0x000000FF */
5221 #define FLASH_SEC1R_SEC_SIZE1             FLASH_SEC1R_SEC_SIZE1_Msk
5222 #define FLASH_SEC1R_BOOT_LOCK_Pos         (16U)
5223 #define FLASH_SEC1R_BOOT_LOCK_Msk         (0x1UL << FLASH_SEC1R_BOOT_LOCK_Pos)/*!< 0x00010000 */
5224 #define FLASH_SEC1R_BOOT_LOCK             FLASH_SEC1R_BOOT_LOCK_Msk
5225 
5226 /******************  Bits definition for FLASH_SEC2R register  **************/
5227 #define FLASH_SEC2R_SEC_SIZE2_Pos         (0U)
5228 #define FLASH_SEC2R_SEC_SIZE2_Msk         (0xFFUL << FLASH_SEC2R_SEC_SIZE2_Pos)/*!< 0x000000FF */
5229 #define FLASH_SEC2R_SEC_SIZE2             FLASH_SEC2R_SEC_SIZE2_Msk
5230 
5231 /******************************************************************************/
5232 /*                                                                            */
5233 /*                Filter Mathematical ACcelerator unit (FMAC)                 */
5234 /*                                                                            */
5235 /******************************************************************************/
5236 /*****************  Bit definition for FMAC_X1BUFCFG register  ****************/
5237 #define FMAC_X1BUFCFG_X1_BASE_Pos     (0U)
5238 #define FMAC_X1BUFCFG_X1_BASE_Msk     (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos)    /*!< 0x000000FF */
5239 #define FMAC_X1BUFCFG_X1_BASE         FMAC_X1BUFCFG_X1_BASE_Msk                /*!< Base address of X1 buffer */
5240 #define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U)
5241 #define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos)/*!< 0x0000FF00 */
5242 #define FMAC_X1BUFCFG_X1_BUF_SIZE     FMAC_X1BUFCFG_X1_BUF_SIZE_Msk            /*!< Allocated size of X1 buffer in 16-bit words */
5243 #define FMAC_X1BUFCFG_FULL_WM_Pos     (24U)
5244 #define FMAC_X1BUFCFG_FULL_WM_Msk     (0x3UL  << FMAC_X1BUFCFG_FULL_WM_Pos)    /*!< 0x03000000 */
5245 #define FMAC_X1BUFCFG_FULL_WM         FMAC_X1BUFCFG_FULL_WM_Msk                /*!< Watermark for buffer full flag */
5246 /*****************  Bit definition for FMAC_X2BUFCFG register  ****************/
5247 #define FMAC_X2BUFCFG_X2_BASE_Pos     (0U)
5248 #define FMAC_X2BUFCFG_X2_BASE_Msk     (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos)    /*!< 0x000000FF */
5249 #define FMAC_X2BUFCFG_X2_BASE         FMAC_X2BUFCFG_X2_BASE_Msk                /*!< Base address of X2 buffer */
5250 #define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U)
5251 #define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos)/*!< 0x0000FF00 */
5252 #define FMAC_X2BUFCFG_X2_BUF_SIZE     FMAC_X2BUFCFG_X2_BUF_SIZE_Msk            /*!< Size of X2 buffer in 16-bit words */
5253 /*****************  Bit definition for FMAC_YBUFCFG register  *****************/
5254 #define FMAC_YBUFCFG_Y_BASE_Pos       (0U)
5255 #define FMAC_YBUFCFG_Y_BASE_Msk       (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos)      /*!< 0x000000FF */
5256 #define FMAC_YBUFCFG_Y_BASE           FMAC_YBUFCFG_Y_BASE_Msk                  /*!< Base address of Y buffer */
5257 #define FMAC_YBUFCFG_Y_BUF_SIZE_Pos   (8U)
5258 #define FMAC_YBUFCFG_Y_BUF_SIZE_Msk   (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos)  /*!< 0x0000FF00 */
5259 #define FMAC_YBUFCFG_Y_BUF_SIZE       FMAC_YBUFCFG_Y_BUF_SIZE_Msk              /*!< Size of Y buffer in 16-bit words */
5260 #define FMAC_YBUFCFG_EMPTY_WM_Pos     (24U)
5261 #define FMAC_YBUFCFG_EMPTY_WM_Msk     (0x3UL  << FMAC_YBUFCFG_EMPTY_WM_Pos)    /*!< 0x03000000 */
5262 #define FMAC_YBUFCFG_EMPTY_WM         FMAC_YBUFCFG_EMPTY_WM_Msk                /*!< Watermark for buffer empty flag */
5263 /******************  Bit definition for FMAC_PARAM register  ******************/
5264 #define FMAC_PARAM_P_Pos              (0U)
5265 #define FMAC_PARAM_P_Msk              (0xFFUL << FMAC_PARAM_P_Pos)             /*!< 0x000000FF */
5266 #define FMAC_PARAM_P                  FMAC_PARAM_P_Msk                         /*!< Input parameter P */
5267 #define FMAC_PARAM_Q_Pos              (8U)
5268 #define FMAC_PARAM_Q_Msk              (0xFFUL << FMAC_PARAM_Q_Pos)             /*!< 0x0000FF00 */
5269 #define FMAC_PARAM_Q                  FMAC_PARAM_Q_Msk                         /*!< Input parameter Q */
5270 #define FMAC_PARAM_R_Pos              (16U)
5271 #define FMAC_PARAM_R_Msk              (0xFFUL << FMAC_PARAM_R_Pos)             /*!< 0x00FF0000 */
5272 #define FMAC_PARAM_R                  FMAC_PARAM_R_Msk                         /*!< Input parameter R */
5273 #define FMAC_PARAM_FUNC_Pos           (24U)
5274 #define FMAC_PARAM_FUNC_Msk           (0x7FUL << FMAC_PARAM_FUNC_Pos)          /*!< 0x7F000000 */
5275 #define FMAC_PARAM_FUNC               FMAC_PARAM_FUNC_Msk                      /*!< Function */
5276 #define FMAC_PARAM_FUNC_0             (0x1UL  << FMAC_PARAM_FUNC_Pos)          /*!< 0x01000000 */
5277 #define FMAC_PARAM_FUNC_1             (0x2UL  << FMAC_PARAM_FUNC_Pos)          /*!< 0x02000000 */
5278 #define FMAC_PARAM_FUNC_2             (0x4UL  << FMAC_PARAM_FUNC_Pos)          /*!< 0x04000000 */
5279 #define FMAC_PARAM_FUNC_3             (0x8UL  << FMAC_PARAM_FUNC_Pos)          /*!< 0x08000000 */
5280 #define FMAC_PARAM_FUNC_4             (0x10UL << FMAC_PARAM_FUNC_Pos)          /*!< 0x10000000 */
5281 #define FMAC_PARAM_FUNC_5             (0x20UL << FMAC_PARAM_FUNC_Pos)          /*!< 0x20000000 */
5282 #define FMAC_PARAM_FUNC_6             (0x40UL << FMAC_PARAM_FUNC_Pos)          /*!< 0x40000000 */
5283 #define FMAC_PARAM_START_Pos          (31U)
5284 #define FMAC_PARAM_START_Msk          (0x1UL  << FMAC_PARAM_START_Pos)         /*!< 0x80000000 */
5285 #define FMAC_PARAM_START              FMAC_PARAM_START_Msk                     /*!< Enable execution */
5286 /********************  Bit definition for FMAC_CR register  *******************/
5287 #define FMAC_CR_RIEN_Pos              (0U)
5288 #define FMAC_CR_RIEN_Msk              (0x1UL  << FMAC_CR_RIEN_Pos)             /*!< 0x00000001 */
5289 #define FMAC_CR_RIEN                  FMAC_CR_RIEN_Msk                         /*!< Enable read interrupt */
5290 #define FMAC_CR_WIEN_Pos              (1U)
5291 #define FMAC_CR_WIEN_Msk              (0x1UL  << FMAC_CR_WIEN_Pos)             /*!< 0x00000002 */
5292 #define FMAC_CR_WIEN                  FMAC_CR_WIEN_Msk                         /*!< Enable write interrupt */
5293 #define FMAC_CR_OVFLIEN_Pos           (2U)
5294 #define FMAC_CR_OVFLIEN_Msk           (0x1UL  << FMAC_CR_OVFLIEN_Pos)          /*!< 0x00000004 */
5295 #define FMAC_CR_OVFLIEN               FMAC_CR_OVFLIEN_Msk                      /*!< Enable overflow error interrupts */
5296 #define FMAC_CR_UNFLIEN_Pos           (3U)
5297 #define FMAC_CR_UNFLIEN_Msk           (0x1UL  << FMAC_CR_UNFLIEN_Pos)          /*!< 0x00000008 */
5298 #define FMAC_CR_UNFLIEN               FMAC_CR_UNFLIEN_Msk                      /*!< Enable underflow error interrupts */
5299 #define FMAC_CR_SATIEN_Pos            (4U)
5300 #define FMAC_CR_SATIEN_Msk            (0x1UL  << FMAC_CR_SATIEN_Pos)           /*!< 0x00000010 */
5301 #define FMAC_CR_SATIEN                FMAC_CR_SATIEN_Msk                       /*!< Enable saturation error interrupts */
5302 #define FMAC_CR_DMAREN_Pos            (8U)
5303 #define FMAC_CR_DMAREN_Msk            (0x1UL  << FMAC_CR_DMAREN_Pos)           /*!< 0x00000100 */
5304 #define FMAC_CR_DMAREN                FMAC_CR_DMAREN_Msk                       /*!< Enable DMA read channel requests */
5305 #define FMAC_CR_DMAWEN_Pos            (9U)
5306 #define FMAC_CR_DMAWEN_Msk            (0x1UL  << FMAC_CR_DMAWEN_Pos)           /*!< 0x00000200 */
5307 #define FMAC_CR_DMAWEN                FMAC_CR_DMAWEN_Msk                       /*!< Enable DMA write channel requests */
5308 #define FMAC_CR_CLIPEN_Pos            (15U)
5309 #define FMAC_CR_CLIPEN_Msk            (0x1UL  << FMAC_CR_CLIPEN_Pos)           /*!< 0x00008000 */
5310 #define FMAC_CR_CLIPEN                FMAC_CR_CLIPEN_Msk                       /*!< Enable clipping */
5311 #define FMAC_CR_RESET_Pos             (16U)
5312 #define FMAC_CR_RESET_Msk             (0x1UL  << FMAC_CR_RESET_Pos)            /*!< 0x00010000 */
5313 #define FMAC_CR_RESET                 FMAC_CR_RESET_Msk                        /*!< Reset filter mathematical accelerator unit */
5314 /*******************  Bit definition for FMAC_SR register  ********************/
5315 #define FMAC_SR_YEMPTY_Pos            (0U)
5316 #define FMAC_SR_YEMPTY_Msk            (0x1UL  << FMAC_SR_YEMPTY_Pos)           /*!< 0x00000001 */
5317 #define FMAC_SR_YEMPTY                FMAC_SR_YEMPTY_Msk                       /*!< Y buffer empty flag */
5318 #define FMAC_SR_X1FULL_Pos            (1U)
5319 #define FMAC_SR_X1FULL_Msk            (0x1UL  << FMAC_SR_X1FULL_Pos)           /*!< 0x00000002 */
5320 #define FMAC_SR_X1FULL                FMAC_SR_X1FULL_Msk                       /*!< X1 buffer full flag */
5321 #define FMAC_SR_OVFL_Pos              (8U)
5322 #define FMAC_SR_OVFL_Msk              (0x1UL  << FMAC_SR_OVFL_Pos)             /*!< 0x00000100 */
5323 #define FMAC_SR_OVFL                  FMAC_SR_OVFL_Msk                         /*!< Overflow error flag */
5324 #define FMAC_SR_UNFL_Pos              (9U)
5325 #define FMAC_SR_UNFL_Msk              (0x1UL  << FMAC_SR_UNFL_Pos)             /*!< 0x00000200 */
5326 #define FMAC_SR_UNFL                  FMAC_SR_UNFL_Msk                         /*!< Underflow error flag */
5327 #define FMAC_SR_SAT_Pos               (10U)
5328 #define FMAC_SR_SAT_Msk               (0x1UL  << FMAC_SR_SAT_Pos)              /*!< 0x00000400 */
5329 #define FMAC_SR_SAT                   FMAC_SR_SAT_Msk                          /*!< Saturation error flag */
5330 /******************  Bit definition for FMAC_WDATA register  ******************/
5331 #define FMAC_WDATA_WDATA_Pos          (0U)
5332 #define FMAC_WDATA_WDATA_Msk          (0xFFFFUL << FMAC_WDATA_WDATA_Pos)       /*!< 0x0000FFFF */
5333 #define FMAC_WDATA_WDATA              FMAC_WDATA_WDATA_Msk                     /*!< Write data */
5334 /******************  Bit definition for FMACX_RDATA register  *****************/
5335 #define FMAC_RDATA_RDATA_Pos          (0U)
5336 #define FMAC_RDATA_RDATA_Msk          (0xFFFFUL << FMAC_RDATA_RDATA_Pos)       /*!< 0x0000FFFF */
5337 #define FMAC_RDATA_RDATA              FMAC_RDATA_RDATA_Msk                     /*!< Read data */
5338 
5339 /******************************************************************************/
5340 /*                                                                            */
5341 /*                          Flexible Memory Controller                        */
5342 /*                                                                            */
5343 /******************************************************************************/
5344 /******************  Bit definition for FMC_BCR1 register  *******************/
5345 #define FMC_BCR1_CCLKEN_Pos        (20U)
5346 #define FMC_BCR1_CCLKEN_Msk        (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */
5347 #define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continous clock enable     */
5348 #define FMC_BCR1_WFDIS_Pos         (21U)
5349 #define FMC_BCR1_WFDIS_Msk         (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */
5350 #define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */
5351 
5352 /******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/
5353 #define FMC_BCRx_MBKEN_Pos         (0U)
5354 #define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */
5355 #define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */
5356 #define FMC_BCRx_MUXEN_Pos         (1U)
5357 #define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */
5358 #define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */
5359 
5360 #define FMC_BCRx_MTYP_Pos          (2U)
5361 #define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */
5362 #define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */
5363 #define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                /*!< 0x00000004 */
5364 #define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                /*!< 0x00000008 */
5365 
5366 #define FMC_BCRx_MWID_Pos          (4U)
5367 #define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */
5368 #define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */
5369 #define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000010 */
5370 #define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000020 */
5371 
5372 #define FMC_BCRx_FACCEN_Pos        (6U)
5373 #define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */
5374 #define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */
5375 #define FMC_BCRx_BURSTEN_Pos       (8U)
5376 #define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */
5377 #define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */
5378 #define FMC_BCRx_WAITPOL_Pos       (9U)
5379 #define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */
5380 #define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */
5381 #define FMC_BCRx_WAITCFG_Pos       (11U)
5382 #define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */
5383 #define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */
5384 #define FMC_BCRx_WREN_Pos          (12U)
5385 #define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */
5386 #define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */
5387 #define FMC_BCRx_WAITEN_Pos        (13U)
5388 #define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */
5389 #define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */
5390 #define FMC_BCRx_EXTMOD_Pos        (14U)
5391 #define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */
5392 #define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */
5393 #define FMC_BCRx_ASYNCWAIT_Pos     (15U)
5394 #define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */
5395 #define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */
5396 
5397 #define FMC_BCRx_CPSIZE_Pos        (16U)
5398 #define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */
5399 #define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<CRAM page size             */
5400 #define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00010000 */
5401 #define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00020000 */
5402 #define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00040000 */
5403 
5404 #define FMC_BCRx_CBURSTRW_Pos      (19U)
5405 #define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */
5406 #define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */
5407 
5408 #define FMC_BCRx_NBLSET_Pos        (22U)
5409 #define FMC_BCRx_NBLSET_Msk        (0x3UL << FMC_BCRx_NBLSET_Pos)              /*!< 0x00C00000 */
5410 #define FMC_BCRx_NBLSET            FMC_BCRx_NBLSET_Msk                         /*!<Byte lane (NBL) setup      */
5411 #define FMC_BCRx_NBLSET_0          (0x1UL << FMC_BCRx_NBLSET_Pos)              /*!< 0x00500000 */
5412 #define FMC_BCRx_NBLSET_1          (0x2UL << FMC_BCRx_NBLSET_Pos)              /*!< 0x00800000 */
5413 
5414 /******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/
5415 #define FMC_BTRx_ADDSET_Pos        (0U)
5416 #define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */
5417 #define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */
5418 #define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000001 */
5419 #define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000002 */
5420 #define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000004 */
5421 #define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000008 */
5422 
5423 #define FMC_BTRx_ADDHLD_Pos        (4U)
5424 #define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */
5425 #define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
5426 #define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000010 */
5427 #define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000020 */
5428 #define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000040 */
5429 #define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000080 */
5430 
5431 #define FMC_BTRx_DATAST_Pos        (8U)
5432 #define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */
5433 #define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */
5434 #define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000100 */
5435 #define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000200 */
5436 #define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000400 */
5437 #define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000800 */
5438 #define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00001000 */
5439 #define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00002000 */
5440 #define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00004000 */
5441 #define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00008000 */
5442 
5443 #define FMC_BTRx_BUSTURN_Pos       (16U)
5444 #define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */
5445 #define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
5446 #define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00010000 */
5447 #define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00020000 */
5448 #define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00040000 */
5449 #define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00080000 */
5450 
5451 #define FMC_BTRx_CLKDIV_Pos        (20U)
5452 #define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */
5453 #define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */
5454 #define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00100000 */
5455 #define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00200000 */
5456 #define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00400000 */
5457 #define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00800000 */
5458 
5459 #define FMC_BTRx_DATLAT_Pos        (24U)
5460 #define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */
5461 #define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLAT[3:0] bits (Data latency) */
5462 #define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x01000000 */
5463 #define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x02000000 */
5464 #define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x04000000 */
5465 #define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x08000000 */
5466 
5467 #define FMC_BTRx_ACCMOD_Pos        (28U)
5468 #define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */
5469 #define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */
5470 #define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x10000000 */
5471 #define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x20000000 */
5472 
5473 #define FMC_BTRx_DATAHLD_Pos       (30U)
5474 #define FMC_BTRx_DATAHLD_Msk       (0x3UL << FMC_BTRx_DATAHLD_Pos)             /*!< 0xC0000000 */
5475 #define FMC_BTRx_DATAHLD           FMC_BTRx_DATAHLD_Msk                        /*!<DATAHLD[1:0] bits (Data hold phase duration) */
5476 #define FMC_BTRx_DATAHLD_0         (0x1UL << FMC_BTRx_DATAHLD_Pos)             /*!< 0x40000000 */
5477 #define FMC_BTRx_DATAHLD_1         (0x2UL << FMC_BTRx_DATAHLD_Pos)             /*!< 0x80000000 */
5478 
5479 /******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/
5480 #define FMC_BWTRx_ADDSET_Pos       (0U)
5481 #define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */
5482 #define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
5483 #define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000001 */
5484 #define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000002 */
5485 #define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000004 */
5486 #define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000008 */
5487 
5488 #define FMC_BWTRx_ADDHLD_Pos       (4U)
5489 #define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */
5490 #define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
5491 #define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000010 */
5492 #define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000020 */
5493 #define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000040 */
5494 #define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000080 */
5495 
5496 #define FMC_BWTRx_DATAST_Pos       (8U)
5497 #define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */
5498 #define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
5499 #define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000100 */
5500 #define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000200 */
5501 #define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000400 */
5502 #define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000800 */
5503 #define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00001000 */
5504 #define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00002000 */
5505 #define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00004000 */
5506 #define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00008000 */
5507 
5508 #define FMC_BWTRx_BUSTURN_Pos      (16U)
5509 #define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */
5510 #define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
5511 #define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00010000 */
5512 #define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00020000 */
5513 #define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00040000 */
5514 #define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00080000 */
5515 
5516 #define FMC_BWTRx_ACCMOD_Pos       (28U)
5517 #define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */
5518 #define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
5519 #define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x10000000 */
5520 #define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x20000000 */
5521 
5522 #define FMC_BWTRx_DATAHLD_Pos      (30U)
5523 #define FMC_BWTRx_DATAHLD_Msk      (0x3UL << FMC_BWTRx_DATAHLD_Pos)            /*!< 0xC0000000 */
5524 #define FMC_BWTRx_DATAHLD          FMC_BWTRx_DATAHLD_Msk                       /*!<DATAHLD[1:0] bits (Data hold phase duration) */
5525 #define FMC_BWTRx_DATAHLD_0        (0x1UL << FMC_BWTRx_DATAHLD_Pos)            /*!< 0x40000000 */
5526 #define FMC_BWTRx_DATAHLD_1        (0x2UL << FMC_BWTRx_DATAHLD_Pos)            /*!< 0x80000000 */
5527 
5528 /******************  Bit definition for FMC_PCSCNTR register ******************/
5529 #define FMC_PCSCNTR_CSCOUNT_Pos    (0U)
5530 #define FMC_PCSCNTR_CSCOUNT_Msk    (0xFFFFUL << FMC_PCSCNTR_CSCOUNT_Pos)       /*!< 0x0000FFFF */
5531 #define FMC_PCSCNTR_CSCOUNT        FMC_PCSCNTR_CSCOUNT_Msk                     /*!<CSCOUNT[15:0] bits (Chip select counter) */
5532 
5533 #define FMC_PCSCNTR_CNTB1EN_Pos    (16U)
5534 #define FMC_PCSCNTR_CNTB1EN_Msk    (0x1UL << FMC_PCSCNTR_CNTB1EN_Pos)          /*!< 0x00010000 */
5535 #define FMC_PCSCNTR_CNTB1EN        FMC_PCSCNTR_CNTB1EN_Msk                     /*!<Counter PSRAM/NOR Bank1_1 enable */
5536 
5537 #define FMC_PCSCNTR_CNTB2EN_Pos    (17U)
5538 #define FMC_PCSCNTR_CNTB2EN_Msk    (0x1UL << FMC_PCSCNTR_CNTB2EN_Pos)          /*!< 0x00020000 */
5539 #define FMC_PCSCNTR_CNTB2EN        FMC_PCSCNTR_CNTB2EN_Msk                     /*!<Counter PSRAM/NOR Bank1_2 enable */
5540 
5541 #define FMC_PCSCNTR_CNTB3EN_Pos    (18U)
5542 #define FMC_PCSCNTR_CNTB3EN_Msk    (0x1UL << FMC_PCSCNTR_CNTB3EN_Pos)          /*!< 0x00040000 */
5543 #define FMC_PCSCNTR_CNTB3EN        FMC_PCSCNTR_CNTB3EN_Msk                     /*!<Counter PSRAM/NOR Bank1_3 enable */
5544 
5545 #define FMC_PCSCNTR_CNTB4EN_Pos    (19U)
5546 #define FMC_PCSCNTR_CNTB4EN_Msk    (0x1UL << FMC_PCSCNTR_CNTB4EN_Pos)          /*!< 0x00080000 */
5547 #define FMC_PCSCNTR_CNTB4EN        FMC_PCSCNTR_CNTB4EN_Msk                     /*!<Counter PSRAM/NOR Bank1_4 enable */
5548 
5549 /******************  Bit definition for FMC_PCR register  ********************/
5550 #define FMC_PCR_PWAITEN_Pos        (1U)
5551 #define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */
5552 #define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */
5553 #define FMC_PCR_PBKEN_Pos          (2U)
5554 #define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */
5555 #define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */
5556 #define FMC_PCR_PTYP_Pos           (3U)
5557 #define FMC_PCR_PTYP_Msk           (0x1UL << FMC_PCR_PTYP_Pos)                 /*!< 0x00000008 */
5558 #define FMC_PCR_PTYP               FMC_PCR_PTYP_Msk                            /*!<Memory type                               */
5559 
5560 #define FMC_PCR_PWID_Pos           (4U)
5561 #define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */
5562 #define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */
5563 #define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000010 */
5564 #define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000020 */
5565 
5566 #define FMC_PCR_ECCEN_Pos          (6U)
5567 #define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */
5568 #define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */
5569 
5570 #define FMC_PCR_TCLR_Pos           (9U)
5571 #define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */
5572 #define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */
5573 #define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000200 */
5574 #define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000400 */
5575 #define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000800 */
5576 #define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001000 */
5577 
5578 #define FMC_PCR_TAR_Pos            (13U)
5579 #define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */
5580 #define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */
5581 #define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                  /*!< 0x00002000 */
5582 #define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                  /*!< 0x00004000 */
5583 #define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                  /*!< 0x00008000 */
5584 #define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                  /*!< 0x00010000 */
5585 
5586 #define FMC_PCR_ECCPS_Pos          (17U)
5587 #define FMC_PCR_ECCPS_Msk          (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */
5588 #define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */
5589 #define FMC_PCR_ECCPS_0            (0x1UL << FMC_PCR_ECCPS_Pos)                /*!< 0x00020000 */
5590 #define FMC_PCR_ECCPS_1            (0x2UL << FMC_PCR_ECCPS_Pos)                /*!< 0x00040000 */
5591 #define FMC_PCR_ECCPS_2            (0x4UL << FMC_PCR_ECCPS_Pos)                /*!< 0x00080000 */
5592 
5593 /*******************  Bit definition for FMC_SR register  ********************/
5594 #define FMC_SR_IRS_Pos             (0U)
5595 #define FMC_SR_IRS_Msk             (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */
5596 #define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */
5597 #define FMC_SR_ILS_Pos             (1U)
5598 #define FMC_SR_ILS_Msk             (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */
5599 #define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */
5600 #define FMC_SR_IFS_Pos             (2U)
5601 #define FMC_SR_IFS_Msk             (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */
5602 #define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */
5603 #define FMC_SR_IREN_Pos            (3U)
5604 #define FMC_SR_IREN_Msk            (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */
5605 #define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */
5606 #define FMC_SR_ILEN_Pos            (4U)
5607 #define FMC_SR_ILEN_Msk            (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */
5608 #define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */
5609 #define FMC_SR_IFEN_Pos            (5U)
5610 #define FMC_SR_IFEN_Msk            (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */
5611 #define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */
5612 #define FMC_SR_FEMPT_Pos           (6U)
5613 #define FMC_SR_FEMPT_Msk           (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */
5614 #define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */
5615 
5616 /******************  Bit definition for FMC_PMEM register  ******************/
5617 #define FMC_PMEM_MEMSET_Pos        (0U)
5618 #define FMC_PMEM_MEMSET_Msk        (0xFFUL << FMC_PMEM_MEMSET_Pos)             /*!< 0x000000FF */
5619 #define FMC_PMEM_MEMSET            FMC_PMEM_MEMSET_Msk                         /*!<MEMSET[7:0] bits (Common memory setup time) */
5620 #define FMC_PMEM_MEMSET_0          (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */
5621 #define FMC_PMEM_MEMSET_1          (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */
5622 #define FMC_PMEM_MEMSET_2          (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */
5623 #define FMC_PMEM_MEMSET_3          (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */
5624 #define FMC_PMEM_MEMSET_4          (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */
5625 #define FMC_PMEM_MEMSET_5          (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */
5626 #define FMC_PMEM_MEMSET_6          (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */
5627 #define FMC_PMEM_MEMSET_7          (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */
5628 
5629 #define FMC_PMEM_MEMWAIT_Pos       (8U)
5630 #define FMC_PMEM_MEMWAIT_Msk       (0xFFUL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x0000FF00 */
5631 #define FMC_PMEM_MEMWAIT           FMC_PMEM_MEMWAIT_Msk                        /*!<MEMWAIT[7:0] bits (Common memory wait time) */
5632 #define FMC_PMEM_MEMWAIT_0         (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */
5633 #define FMC_PMEM_MEMWAIT_1         (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */
5634 #define FMC_PMEM_MEMWAIT_2         (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */
5635 #define FMC_PMEM_MEMWAIT_3         (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */
5636 #define FMC_PMEM_MEMWAIT_4         (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */
5637 #define FMC_PMEM_MEMWAIT_5         (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */
5638 #define FMC_PMEM_MEMWAIT_6         (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */
5639 #define FMC_PMEM_MEMWAIT_7         (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */
5640 
5641 #define FMC_PMEM_MEMHOLD_Pos       (16U)
5642 #define FMC_PMEM_MEMHOLD_Msk       (0xFFUL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00FF0000 */
5643 #define FMC_PMEM_MEMHOLD           FMC_PMEM_MEMHOLD_Msk                        /*!<MEMHOLD[7:0] bits (Common memory hold time) */
5644 #define FMC_PMEM_MEMHOLD_0         (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */
5645 #define FMC_PMEM_MEMHOLD_1         (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */
5646 #define FMC_PMEM_MEMHOLD_2         (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */
5647 #define FMC_PMEM_MEMHOLD_3         (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */
5648 #define FMC_PMEM_MEMHOLD_4         (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */
5649 #define FMC_PMEM_MEMHOLD_5         (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */
5650 #define FMC_PMEM_MEMHOLD_6         (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */
5651 #define FMC_PMEM_MEMHOLD_7         (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */
5652 
5653 #define FMC_PMEM_MEMHIZ_Pos        (24U)
5654 #define FMC_PMEM_MEMHIZ_Msk        (0xFFUL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0xFF000000 */
5655 #define FMC_PMEM_MEMHIZ            FMC_PMEM_MEMHIZ_Msk                         /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
5656 #define FMC_PMEM_MEMHIZ_0          (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */
5657 #define FMC_PMEM_MEMHIZ_1          (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */
5658 #define FMC_PMEM_MEMHIZ_2          (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */
5659 #define FMC_PMEM_MEMHIZ_3          (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */
5660 #define FMC_PMEM_MEMHIZ_4          (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */
5661 #define FMC_PMEM_MEMHIZ_5          (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */
5662 #define FMC_PMEM_MEMHIZ_6          (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */
5663 #define FMC_PMEM_MEMHIZ_7          (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */
5664 
5665 /******************  Bit definition for FMC_PATT register  *******************/
5666 #define FMC_PATT_ATTSET_Pos        (0U)
5667 #define FMC_PATT_ATTSET_Msk        (0xFFUL << FMC_PATT_ATTSET_Pos)             /*!< 0x000000FF */
5668 #define FMC_PATT_ATTSET            FMC_PATT_ATTSET_Msk                         /*!<ATTSET[7:0] bits (Attribute memory setup time) */
5669 #define FMC_PATT_ATTSET_0          (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */
5670 #define FMC_PATT_ATTSET_1          (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */
5671 #define FMC_PATT_ATTSET_2          (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */
5672 #define FMC_PATT_ATTSET_3          (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */
5673 #define FMC_PATT_ATTSET_4          (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */
5674 #define FMC_PATT_ATTSET_5          (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */
5675 #define FMC_PATT_ATTSET_6          (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */
5676 #define FMC_PATT_ATTSET_7          (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */
5677 
5678 #define FMC_PATT_ATTWAIT_Pos       (8U)
5679 #define FMC_PATT_ATTWAIT_Msk       (0xFFUL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x0000FF00 */
5680 #define FMC_PATT_ATTWAIT           FMC_PATT_ATTWAIT_Msk                        /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
5681 #define FMC_PATT_ATTWAIT_0         (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */
5682 #define FMC_PATT_ATTWAIT_1         (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */
5683 #define FMC_PATT_ATTWAIT_2         (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */
5684 #define FMC_PATT_ATTWAIT_3         (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */
5685 #define FMC_PATT_ATTWAIT_4         (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */
5686 #define FMC_PATT_ATTWAIT_5         (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */
5687 #define FMC_PATT_ATTWAIT_6         (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */
5688 #define FMC_PATT_ATTWAIT_7         (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */
5689 
5690 #define FMC_PATT_ATTHOLD_Pos       (16U)
5691 #define FMC_PATT_ATTHOLD_Msk       (0xFFUL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00FF0000 */
5692 #define FMC_PATT_ATTHOLD           FMC_PATT_ATTHOLD_Msk                        /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
5693 #define FMC_PATT_ATTHOLD_0         (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */
5694 #define FMC_PATT_ATTHOLD_1         (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */
5695 #define FMC_PATT_ATTHOLD_2         (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */
5696 #define FMC_PATT_ATTHOLD_3         (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */
5697 #define FMC_PATT_ATTHOLD_4         (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */
5698 #define FMC_PATT_ATTHOLD_5         (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */
5699 #define FMC_PATT_ATTHOLD_6         (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */
5700 #define FMC_PATT_ATTHOLD_7         (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */
5701 
5702 #define FMC_PATT_ATTHIZ_Pos        (24U)
5703 #define FMC_PATT_ATTHIZ_Msk        (0xFFUL << FMC_PATT_ATTHIZ_Pos)             /*!< 0xFF000000 */
5704 #define FMC_PATT_ATTHIZ            FMC_PATT_ATTHIZ_Msk                         /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
5705 #define FMC_PATT_ATTHIZ_0          (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */
5706 #define FMC_PATT_ATTHIZ_1          (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */
5707 #define FMC_PATT_ATTHIZ_2          (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */
5708 #define FMC_PATT_ATTHIZ_3          (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */
5709 #define FMC_PATT_ATTHIZ_4          (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */
5710 #define FMC_PATT_ATTHIZ_5          (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */
5711 #define FMC_PATT_ATTHIZ_6          (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */
5712 #define FMC_PATT_ATTHIZ_7          (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */
5713 
5714 /******************  Bit definition for FMC_ECCR register  *******************/
5715 #define FMC_ECCR_ECC_Pos           (0U)
5716 #define FMC_ECCR_ECC_Msk           (0xFFFFFFFFUL << FMC_ECCR_ECC_Pos)          /*!< 0xFFFFFFFF */
5717 #define FMC_ECCR_ECC               FMC_ECCR_ECC_Msk                            /*!<ECC result */
5718 
5719 /******************************************************************************/
5720 /*                                                                            */
5721 /*                       General Purpose IOs (GPIO)                           */
5722 /*                                                                            */
5723 /******************************************************************************/
5724 /******************  Bits definition for GPIO_MODER register  *****************/
5725 #define GPIO_MODER_MODE0_Pos           (0U)
5726 #define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
5727 #define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk
5728 #define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
5729 #define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
5730 #define GPIO_MODER_MODE1_Pos           (2U)
5731 #define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
5732 #define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk
5733 #define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
5734 #define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
5735 #define GPIO_MODER_MODE2_Pos           (4U)
5736 #define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
5737 #define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk
5738 #define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
5739 #define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
5740 #define GPIO_MODER_MODE3_Pos           (6U)
5741 #define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
5742 #define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk
5743 #define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
5744 #define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
5745 #define GPIO_MODER_MODE4_Pos           (8U)
5746 #define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
5747 #define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk
5748 #define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
5749 #define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
5750 #define GPIO_MODER_MODE5_Pos           (10U)
5751 #define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
5752 #define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk
5753 #define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
5754 #define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
5755 #define GPIO_MODER_MODE6_Pos           (12U)
5756 #define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
5757 #define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk
5758 #define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
5759 #define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
5760 #define GPIO_MODER_MODE7_Pos           (14U)
5761 #define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
5762 #define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk
5763 #define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
5764 #define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
5765 #define GPIO_MODER_MODE8_Pos           (16U)
5766 #define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
5767 #define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk
5768 #define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
5769 #define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
5770 #define GPIO_MODER_MODE9_Pos           (18U)
5771 #define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
5772 #define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk
5773 #define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
5774 #define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
5775 #define GPIO_MODER_MODE10_Pos          (20U)
5776 #define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
5777 #define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk
5778 #define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
5779 #define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
5780 #define GPIO_MODER_MODE11_Pos          (22U)
5781 #define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
5782 #define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk
5783 #define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
5784 #define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
5785 #define GPIO_MODER_MODE12_Pos          (24U)
5786 #define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
5787 #define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk
5788 #define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
5789 #define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
5790 #define GPIO_MODER_MODE13_Pos          (26U)
5791 #define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
5792 #define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk
5793 #define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
5794 #define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
5795 #define GPIO_MODER_MODE14_Pos          (28U)
5796 #define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
5797 #define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk
5798 #define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
5799 #define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
5800 #define GPIO_MODER_MODE15_Pos          (30U)
5801 #define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
5802 #define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk
5803 #define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
5804 #define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
5805 
5806 /* Legacy defines */
5807 #define GPIO_MODER_MODER0                   GPIO_MODER_MODE0
5808 #define GPIO_MODER_MODER0_0                 GPIO_MODER_MODE0_0
5809 #define GPIO_MODER_MODER0_1                 GPIO_MODER_MODE0_1
5810 #define GPIO_MODER_MODER1                   GPIO_MODER_MODE1
5811 #define GPIO_MODER_MODER1_0                 GPIO_MODER_MODE1_0
5812 #define GPIO_MODER_MODER1_1                 GPIO_MODER_MODE1_1
5813 #define GPIO_MODER_MODER2                   GPIO_MODER_MODE2
5814 #define GPIO_MODER_MODER2_0                 GPIO_MODER_MODE2_0
5815 #define GPIO_MODER_MODER2_1                 GPIO_MODER_MODE2_1
5816 #define GPIO_MODER_MODER3                   GPIO_MODER_MODE3
5817 #define GPIO_MODER_MODER3_0                 GPIO_MODER_MODE3_0
5818 #define GPIO_MODER_MODER3_1                 GPIO_MODER_MODE3_1
5819 #define GPIO_MODER_MODER4                   GPIO_MODER_MODE4
5820 #define GPIO_MODER_MODER4_0                 GPIO_MODER_MODE4_0
5821 #define GPIO_MODER_MODER4_1                 GPIO_MODER_MODE4_1
5822 #define GPIO_MODER_MODER5                   GPIO_MODER_MODE5
5823 #define GPIO_MODER_MODER5_0                 GPIO_MODER_MODE5_0
5824 #define GPIO_MODER_MODER5_1                 GPIO_MODER_MODE5_1
5825 #define GPIO_MODER_MODER6                   GPIO_MODER_MODE6
5826 #define GPIO_MODER_MODER6_0                 GPIO_MODER_MODE6_0
5827 #define GPIO_MODER_MODER6_1                 GPIO_MODER_MODE6_1
5828 #define GPIO_MODER_MODER7                   GPIO_MODER_MODE7
5829 #define GPIO_MODER_MODER7_0                 GPIO_MODER_MODE7_0
5830 #define GPIO_MODER_MODER7_1                 GPIO_MODER_MODE7_1
5831 #define GPIO_MODER_MODER8                   GPIO_MODER_MODE8
5832 #define GPIO_MODER_MODER8_0                 GPIO_MODER_MODE8_0
5833 #define GPIO_MODER_MODER8_1                 GPIO_MODER_MODE8_1
5834 #define GPIO_MODER_MODER9                   GPIO_MODER_MODE9
5835 #define GPIO_MODER_MODER9_0                 GPIO_MODER_MODE9_0
5836 #define GPIO_MODER_MODER9_1                 GPIO_MODER_MODE9_1
5837 #define GPIO_MODER_MODER10                  GPIO_MODER_MODE10
5838 #define GPIO_MODER_MODER10_0                GPIO_MODER_MODE10_0
5839 #define GPIO_MODER_MODER10_1                GPIO_MODER_MODE10_1
5840 #define GPIO_MODER_MODER11                  GPIO_MODER_MODE11
5841 #define GPIO_MODER_MODER11_0                GPIO_MODER_MODE11_0
5842 #define GPIO_MODER_MODER11_1                GPIO_MODER_MODE11_1
5843 #define GPIO_MODER_MODER12                  GPIO_MODER_MODE12
5844 #define GPIO_MODER_MODER12_0                GPIO_MODER_MODE12_0
5845 #define GPIO_MODER_MODER12_1                GPIO_MODER_MODE12_1
5846 #define GPIO_MODER_MODER13                  GPIO_MODER_MODE13
5847 #define GPIO_MODER_MODER13_0                GPIO_MODER_MODE13_0
5848 #define GPIO_MODER_MODER13_1                GPIO_MODER_MODE13_1
5849 #define GPIO_MODER_MODER14                  GPIO_MODER_MODE14
5850 #define GPIO_MODER_MODER14_0                GPIO_MODER_MODE14_0
5851 #define GPIO_MODER_MODER14_1                GPIO_MODER_MODE14_1
5852 #define GPIO_MODER_MODER15                  GPIO_MODER_MODE15
5853 #define GPIO_MODER_MODER15_0                GPIO_MODER_MODE15_0
5854 #define GPIO_MODER_MODER15_1                GPIO_MODER_MODE15_1
5855 
5856 /******************  Bits definition for GPIO_OTYPER register  ****************/
5857 #define GPIO_OTYPER_OT0_Pos            (0U)
5858 #define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
5859 #define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
5860 #define GPIO_OTYPER_OT1_Pos            (1U)
5861 #define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
5862 #define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
5863 #define GPIO_OTYPER_OT2_Pos            (2U)
5864 #define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
5865 #define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
5866 #define GPIO_OTYPER_OT3_Pos            (3U)
5867 #define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
5868 #define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
5869 #define GPIO_OTYPER_OT4_Pos            (4U)
5870 #define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
5871 #define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
5872 #define GPIO_OTYPER_OT5_Pos            (5U)
5873 #define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
5874 #define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
5875 #define GPIO_OTYPER_OT6_Pos            (6U)
5876 #define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
5877 #define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
5878 #define GPIO_OTYPER_OT7_Pos            (7U)
5879 #define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
5880 #define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
5881 #define GPIO_OTYPER_OT8_Pos            (8U)
5882 #define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
5883 #define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
5884 #define GPIO_OTYPER_OT9_Pos            (9U)
5885 #define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
5886 #define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
5887 #define GPIO_OTYPER_OT10_Pos           (10U)
5888 #define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
5889 #define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
5890 #define GPIO_OTYPER_OT11_Pos           (11U)
5891 #define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
5892 #define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
5893 #define GPIO_OTYPER_OT12_Pos           (12U)
5894 #define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
5895 #define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
5896 #define GPIO_OTYPER_OT13_Pos           (13U)
5897 #define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
5898 #define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
5899 #define GPIO_OTYPER_OT14_Pos           (14U)
5900 #define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
5901 #define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
5902 #define GPIO_OTYPER_OT15_Pos           (15U)
5903 #define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
5904 #define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk
5905 
5906 /* Legacy defines */
5907 #define GPIO_OTYPER_OT_0                    GPIO_OTYPER_OT0
5908 #define GPIO_OTYPER_OT_1                    GPIO_OTYPER_OT1
5909 #define GPIO_OTYPER_OT_2                    GPIO_OTYPER_OT2
5910 #define GPIO_OTYPER_OT_3                    GPIO_OTYPER_OT3
5911 #define GPIO_OTYPER_OT_4                    GPIO_OTYPER_OT4
5912 #define GPIO_OTYPER_OT_5                    GPIO_OTYPER_OT5
5913 #define GPIO_OTYPER_OT_6                    GPIO_OTYPER_OT6
5914 #define GPIO_OTYPER_OT_7                    GPIO_OTYPER_OT7
5915 #define GPIO_OTYPER_OT_8                    GPIO_OTYPER_OT8
5916 #define GPIO_OTYPER_OT_9                    GPIO_OTYPER_OT9
5917 #define GPIO_OTYPER_OT_10                   GPIO_OTYPER_OT10
5918 #define GPIO_OTYPER_OT_11                   GPIO_OTYPER_OT11
5919 #define GPIO_OTYPER_OT_12                   GPIO_OTYPER_OT12
5920 #define GPIO_OTYPER_OT_13                   GPIO_OTYPER_OT13
5921 #define GPIO_OTYPER_OT_14                   GPIO_OTYPER_OT14
5922 #define GPIO_OTYPER_OT_15                   GPIO_OTYPER_OT15
5923 
5924 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
5925 #define GPIO_OSPEEDR_OSPEED0_Pos       (0U)
5926 #define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
5927 #define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk
5928 #define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000001 */
5929 #define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000002 */
5930 #define GPIO_OSPEEDR_OSPEED1_Pos       (2U)
5931 #define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
5932 #define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk
5933 #define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000004 */
5934 #define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000008 */
5935 #define GPIO_OSPEEDR_OSPEED2_Pos       (4U)
5936 #define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
5937 #define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk
5938 #define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000010 */
5939 #define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000020 */
5940 #define GPIO_OSPEEDR_OSPEED3_Pos       (6U)
5941 #define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
5942 #define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk
5943 #define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000040 */
5944 #define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000080 */
5945 #define GPIO_OSPEEDR_OSPEED4_Pos       (8U)
5946 #define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
5947 #define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk
5948 #define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000100 */
5949 #define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000200 */
5950 #define GPIO_OSPEEDR_OSPEED5_Pos       (10U)
5951 #define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
5952 #define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk
5953 #define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000400 */
5954 #define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000800 */
5955 #define GPIO_OSPEEDR_OSPEED6_Pos       (12U)
5956 #define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
5957 #define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk
5958 #define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00001000 */
5959 #define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00002000 */
5960 #define GPIO_OSPEEDR_OSPEED7_Pos       (14U)
5961 #define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
5962 #define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk
5963 #define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00004000 */
5964 #define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00008000 */
5965 #define GPIO_OSPEEDR_OSPEED8_Pos       (16U)
5966 #define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
5967 #define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk
5968 #define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00010000 */
5969 #define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00020000 */
5970 #define GPIO_OSPEEDR_OSPEED9_Pos       (18U)
5971 #define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
5972 #define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk
5973 #define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00040000 */
5974 #define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00080000 */
5975 #define GPIO_OSPEEDR_OSPEED10_Pos      (20U)
5976 #define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
5977 #define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk
5978 #define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00100000 */
5979 #define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00200000 */
5980 #define GPIO_OSPEEDR_OSPEED11_Pos      (22U)
5981 #define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
5982 #define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk
5983 #define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00400000 */
5984 #define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00800000 */
5985 #define GPIO_OSPEEDR_OSPEED12_Pos      (24U)
5986 #define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
5987 #define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk
5988 #define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x01000000 */
5989 #define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x02000000 */
5990 #define GPIO_OSPEEDR_OSPEED13_Pos      (26U)
5991 #define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
5992 #define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk
5993 #define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x04000000 */
5994 #define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x08000000 */
5995 #define GPIO_OSPEEDR_OSPEED14_Pos      (28U)
5996 #define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
5997 #define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk
5998 #define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x10000000 */
5999 #define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x20000000 */
6000 #define GPIO_OSPEEDR_OSPEED15_Pos      (30U)
6001 #define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
6002 #define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk
6003 #define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x40000000 */
6004 #define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x80000000 */
6005 
6006 /* Legacy defines */
6007 #define GPIO_OSPEEDER_OSPEEDR0              GPIO_OSPEEDR_OSPEED0
6008 #define GPIO_OSPEEDER_OSPEEDR0_0            GPIO_OSPEEDR_OSPEED0_0
6009 #define GPIO_OSPEEDER_OSPEEDR0_1            GPIO_OSPEEDR_OSPEED0_1
6010 #define GPIO_OSPEEDER_OSPEEDR1              GPIO_OSPEEDR_OSPEED1
6011 #define GPIO_OSPEEDER_OSPEEDR1_0            GPIO_OSPEEDR_OSPEED1_0
6012 #define GPIO_OSPEEDER_OSPEEDR1_1            GPIO_OSPEEDR_OSPEED1_1
6013 #define GPIO_OSPEEDER_OSPEEDR2              GPIO_OSPEEDR_OSPEED2
6014 #define GPIO_OSPEEDER_OSPEEDR2_0            GPIO_OSPEEDR_OSPEED2_0
6015 #define GPIO_OSPEEDER_OSPEEDR2_1            GPIO_OSPEEDR_OSPEED2_1
6016 #define GPIO_OSPEEDER_OSPEEDR3              GPIO_OSPEEDR_OSPEED3
6017 #define GPIO_OSPEEDER_OSPEEDR3_0            GPIO_OSPEEDR_OSPEED3_0
6018 #define GPIO_OSPEEDER_OSPEEDR3_1            GPIO_OSPEEDR_OSPEED3_1
6019 #define GPIO_OSPEEDER_OSPEEDR4              GPIO_OSPEEDR_OSPEED4
6020 #define GPIO_OSPEEDER_OSPEEDR4_0            GPIO_OSPEEDR_OSPEED4_0
6021 #define GPIO_OSPEEDER_OSPEEDR4_1            GPIO_OSPEEDR_OSPEED4_1
6022 #define GPIO_OSPEEDER_OSPEEDR5              GPIO_OSPEEDR_OSPEED5
6023 #define GPIO_OSPEEDER_OSPEEDR5_0            GPIO_OSPEEDR_OSPEED5_0
6024 #define GPIO_OSPEEDER_OSPEEDR5_1            GPIO_OSPEEDR_OSPEED5_1
6025 #define GPIO_OSPEEDER_OSPEEDR6              GPIO_OSPEEDR_OSPEED6
6026 #define GPIO_OSPEEDER_OSPEEDR6_0            GPIO_OSPEEDR_OSPEED6_0
6027 #define GPIO_OSPEEDER_OSPEEDR6_1            GPIO_OSPEEDR_OSPEED6_1
6028 #define GPIO_OSPEEDER_OSPEEDR7              GPIO_OSPEEDR_OSPEED7
6029 #define GPIO_OSPEEDER_OSPEEDR7_0            GPIO_OSPEEDR_OSPEED7_0
6030 #define GPIO_OSPEEDER_OSPEEDR7_1            GPIO_OSPEEDR_OSPEED7_1
6031 #define GPIO_OSPEEDER_OSPEEDR8              GPIO_OSPEEDR_OSPEED8
6032 #define GPIO_OSPEEDER_OSPEEDR8_0            GPIO_OSPEEDR_OSPEED8_0
6033 #define GPIO_OSPEEDER_OSPEEDR8_1            GPIO_OSPEEDR_OSPEED8_1
6034 #define GPIO_OSPEEDER_OSPEEDR9              GPIO_OSPEEDR_OSPEED9
6035 #define GPIO_OSPEEDER_OSPEEDR9_0            GPIO_OSPEEDR_OSPEED9_0
6036 #define GPIO_OSPEEDER_OSPEEDR9_1            GPIO_OSPEEDR_OSPEED9_1
6037 #define GPIO_OSPEEDER_OSPEEDR10             GPIO_OSPEEDR_OSPEED10
6038 #define GPIO_OSPEEDER_OSPEEDR10_0           GPIO_OSPEEDR_OSPEED10_0
6039 #define GPIO_OSPEEDER_OSPEEDR10_1           GPIO_OSPEEDR_OSPEED10_1
6040 #define GPIO_OSPEEDER_OSPEEDR11             GPIO_OSPEEDR_OSPEED11
6041 #define GPIO_OSPEEDER_OSPEEDR11_0           GPIO_OSPEEDR_OSPEED11_0
6042 #define GPIO_OSPEEDER_OSPEEDR11_1           GPIO_OSPEEDR_OSPEED11_1
6043 #define GPIO_OSPEEDER_OSPEEDR12             GPIO_OSPEEDR_OSPEED12
6044 #define GPIO_OSPEEDER_OSPEEDR12_0           GPIO_OSPEEDR_OSPEED12_0
6045 #define GPIO_OSPEEDER_OSPEEDR12_1           GPIO_OSPEEDR_OSPEED12_1
6046 #define GPIO_OSPEEDER_OSPEEDR13             GPIO_OSPEEDR_OSPEED13
6047 #define GPIO_OSPEEDER_OSPEEDR13_0           GPIO_OSPEEDR_OSPEED13_0
6048 #define GPIO_OSPEEDER_OSPEEDR13_1           GPIO_OSPEEDR_OSPEED13_1
6049 #define GPIO_OSPEEDER_OSPEEDR14             GPIO_OSPEEDR_OSPEED14
6050 #define GPIO_OSPEEDER_OSPEEDR14_0           GPIO_OSPEEDR_OSPEED14_0
6051 #define GPIO_OSPEEDER_OSPEEDR14_1           GPIO_OSPEEDR_OSPEED14_1
6052 #define GPIO_OSPEEDER_OSPEEDR15             GPIO_OSPEEDR_OSPEED15
6053 #define GPIO_OSPEEDER_OSPEEDR15_0           GPIO_OSPEEDR_OSPEED15_0
6054 #define GPIO_OSPEEDER_OSPEEDR15_1           GPIO_OSPEEDR_OSPEED15_1
6055 
6056 /******************  Bits definition for GPIO_PUPDR register  *****************/
6057 #define GPIO_PUPDR_PUPD0_Pos           (0U)
6058 #define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
6059 #define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk
6060 #define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
6061 #define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
6062 #define GPIO_PUPDR_PUPD1_Pos           (2U)
6063 #define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
6064 #define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk
6065 #define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
6066 #define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
6067 #define GPIO_PUPDR_PUPD2_Pos           (4U)
6068 #define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
6069 #define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk
6070 #define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
6071 #define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
6072 #define GPIO_PUPDR_PUPD3_Pos           (6U)
6073 #define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
6074 #define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk
6075 #define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
6076 #define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
6077 #define GPIO_PUPDR_PUPD4_Pos           (8U)
6078 #define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
6079 #define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk
6080 #define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
6081 #define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
6082 #define GPIO_PUPDR_PUPD5_Pos           (10U)
6083 #define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
6084 #define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk
6085 #define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
6086 #define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
6087 #define GPIO_PUPDR_PUPD6_Pos           (12U)
6088 #define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
6089 #define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk
6090 #define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
6091 #define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
6092 #define GPIO_PUPDR_PUPD7_Pos           (14U)
6093 #define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
6094 #define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk
6095 #define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
6096 #define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
6097 #define GPIO_PUPDR_PUPD8_Pos           (16U)
6098 #define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
6099 #define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk
6100 #define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
6101 #define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
6102 #define GPIO_PUPDR_PUPD9_Pos           (18U)
6103 #define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
6104 #define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk
6105 #define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
6106 #define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
6107 #define GPIO_PUPDR_PUPD10_Pos          (20U)
6108 #define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
6109 #define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk
6110 #define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
6111 #define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
6112 #define GPIO_PUPDR_PUPD11_Pos          (22U)
6113 #define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
6114 #define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk
6115 #define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
6116 #define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
6117 #define GPIO_PUPDR_PUPD12_Pos          (24U)
6118 #define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
6119 #define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk
6120 #define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
6121 #define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
6122 #define GPIO_PUPDR_PUPD13_Pos          (26U)
6123 #define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
6124 #define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk
6125 #define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
6126 #define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
6127 #define GPIO_PUPDR_PUPD14_Pos          (28U)
6128 #define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
6129 #define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk
6130 #define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
6131 #define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
6132 #define GPIO_PUPDR_PUPD15_Pos          (30U)
6133 #define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
6134 #define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk
6135 #define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
6136 #define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
6137 
6138 /* Legacy defines */
6139 #define GPIO_PUPDR_PUPDR0                   GPIO_PUPDR_PUPD0
6140 #define GPIO_PUPDR_PUPDR0_0                 GPIO_PUPDR_PUPD0_0
6141 #define GPIO_PUPDR_PUPDR0_1                 GPIO_PUPDR_PUPD0_1
6142 #define GPIO_PUPDR_PUPDR1                   GPIO_PUPDR_PUPD1
6143 #define GPIO_PUPDR_PUPDR1_0                 GPIO_PUPDR_PUPD1_0
6144 #define GPIO_PUPDR_PUPDR1_1                 GPIO_PUPDR_PUPD1_1
6145 #define GPIO_PUPDR_PUPDR2                   GPIO_PUPDR_PUPD2
6146 #define GPIO_PUPDR_PUPDR2_0                 GPIO_PUPDR_PUPD2_0
6147 #define GPIO_PUPDR_PUPDR2_1                 GPIO_PUPDR_PUPD2_1
6148 #define GPIO_PUPDR_PUPDR3                   GPIO_PUPDR_PUPD3
6149 #define GPIO_PUPDR_PUPDR3_0                 GPIO_PUPDR_PUPD3_0
6150 #define GPIO_PUPDR_PUPDR3_1                 GPIO_PUPDR_PUPD3_1
6151 #define GPIO_PUPDR_PUPDR4                   GPIO_PUPDR_PUPD4
6152 #define GPIO_PUPDR_PUPDR4_0                 GPIO_PUPDR_PUPD4_0
6153 #define GPIO_PUPDR_PUPDR4_1                 GPIO_PUPDR_PUPD4_1
6154 #define GPIO_PUPDR_PUPDR5                   GPIO_PUPDR_PUPD5
6155 #define GPIO_PUPDR_PUPDR5_0                 GPIO_PUPDR_PUPD5_0
6156 #define GPIO_PUPDR_PUPDR5_1                 GPIO_PUPDR_PUPD5_1
6157 #define GPIO_PUPDR_PUPDR6                   GPIO_PUPDR_PUPD6
6158 #define GPIO_PUPDR_PUPDR6_0                 GPIO_PUPDR_PUPD6_0
6159 #define GPIO_PUPDR_PUPDR6_1                 GPIO_PUPDR_PUPD6_1
6160 #define GPIO_PUPDR_PUPDR7                   GPIO_PUPDR_PUPD7
6161 #define GPIO_PUPDR_PUPDR7_0                 GPIO_PUPDR_PUPD7_0
6162 #define GPIO_PUPDR_PUPDR7_1                 GPIO_PUPDR_PUPD7_1
6163 #define GPIO_PUPDR_PUPDR8                   GPIO_PUPDR_PUPD8
6164 #define GPIO_PUPDR_PUPDR8_0                 GPIO_PUPDR_PUPD8_0
6165 #define GPIO_PUPDR_PUPDR8_1                 GPIO_PUPDR_PUPD8_1
6166 #define GPIO_PUPDR_PUPDR9                   GPIO_PUPDR_PUPD9
6167 #define GPIO_PUPDR_PUPDR9_0                 GPIO_PUPDR_PUPD9_0
6168 #define GPIO_PUPDR_PUPDR9_1                 GPIO_PUPDR_PUPD9_1
6169 #define GPIO_PUPDR_PUPDR10                  GPIO_PUPDR_PUPD10
6170 #define GPIO_PUPDR_PUPDR10_0                GPIO_PUPDR_PUPD10_0
6171 #define GPIO_PUPDR_PUPDR10_1                GPIO_PUPDR_PUPD10_1
6172 #define GPIO_PUPDR_PUPDR11                  GPIO_PUPDR_PUPD11
6173 #define GPIO_PUPDR_PUPDR11_0                GPIO_PUPDR_PUPD11_0
6174 #define GPIO_PUPDR_PUPDR11_1                GPIO_PUPDR_PUPD11_1
6175 #define GPIO_PUPDR_PUPDR12                  GPIO_PUPDR_PUPD12
6176 #define GPIO_PUPDR_PUPDR12_0                GPIO_PUPDR_PUPD12_0
6177 #define GPIO_PUPDR_PUPDR12_1                GPIO_PUPDR_PUPD12_1
6178 #define GPIO_PUPDR_PUPDR13                  GPIO_PUPDR_PUPD13
6179 #define GPIO_PUPDR_PUPDR13_0                GPIO_PUPDR_PUPD13_0
6180 #define GPIO_PUPDR_PUPDR13_1                GPIO_PUPDR_PUPD13_1
6181 #define GPIO_PUPDR_PUPDR14                  GPIO_PUPDR_PUPD14
6182 #define GPIO_PUPDR_PUPDR14_0                GPIO_PUPDR_PUPD14_0
6183 #define GPIO_PUPDR_PUPDR14_1                GPIO_PUPDR_PUPD14_1
6184 #define GPIO_PUPDR_PUPDR15                  GPIO_PUPDR_PUPD15
6185 #define GPIO_PUPDR_PUPDR15_0                GPIO_PUPDR_PUPD15_0
6186 #define GPIO_PUPDR_PUPDR15_1                GPIO_PUPDR_PUPD15_1
6187 
6188 /******************  Bits definition for GPIO_IDR register  *******************/
6189 #define GPIO_IDR_ID0_Pos               (0U)
6190 #define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
6191 #define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk
6192 #define GPIO_IDR_ID1_Pos               (1U)
6193 #define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
6194 #define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk
6195 #define GPIO_IDR_ID2_Pos               (2U)
6196 #define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
6197 #define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk
6198 #define GPIO_IDR_ID3_Pos               (3U)
6199 #define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
6200 #define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk
6201 #define GPIO_IDR_ID4_Pos               (4U)
6202 #define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
6203 #define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk
6204 #define GPIO_IDR_ID5_Pos               (5U)
6205 #define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
6206 #define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk
6207 #define GPIO_IDR_ID6_Pos               (6U)
6208 #define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
6209 #define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk
6210 #define GPIO_IDR_ID7_Pos               (7U)
6211 #define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
6212 #define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk
6213 #define GPIO_IDR_ID8_Pos               (8U)
6214 #define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
6215 #define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk
6216 #define GPIO_IDR_ID9_Pos               (9U)
6217 #define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
6218 #define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk
6219 #define GPIO_IDR_ID10_Pos              (10U)
6220 #define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
6221 #define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk
6222 #define GPIO_IDR_ID11_Pos              (11U)
6223 #define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
6224 #define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk
6225 #define GPIO_IDR_ID12_Pos              (12U)
6226 #define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
6227 #define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk
6228 #define GPIO_IDR_ID13_Pos              (13U)
6229 #define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
6230 #define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk
6231 #define GPIO_IDR_ID14_Pos              (14U)
6232 #define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
6233 #define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk
6234 #define GPIO_IDR_ID15_Pos              (15U)
6235 #define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
6236 #define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk
6237 
6238 /* Legacy defines */
6239 #define GPIO_IDR_IDR_0                      GPIO_IDR_ID0
6240 #define GPIO_IDR_IDR_1                      GPIO_IDR_ID1
6241 #define GPIO_IDR_IDR_2                      GPIO_IDR_ID2
6242 #define GPIO_IDR_IDR_3                      GPIO_IDR_ID3
6243 #define GPIO_IDR_IDR_4                      GPIO_IDR_ID4
6244 #define GPIO_IDR_IDR_5                      GPIO_IDR_ID5
6245 #define GPIO_IDR_IDR_6                      GPIO_IDR_ID6
6246 #define GPIO_IDR_IDR_7                      GPIO_IDR_ID7
6247 #define GPIO_IDR_IDR_8                      GPIO_IDR_ID8
6248 #define GPIO_IDR_IDR_9                      GPIO_IDR_ID9
6249 #define GPIO_IDR_IDR_10                     GPIO_IDR_ID10
6250 #define GPIO_IDR_IDR_11                     GPIO_IDR_ID11
6251 #define GPIO_IDR_IDR_12                     GPIO_IDR_ID12
6252 #define GPIO_IDR_IDR_13                     GPIO_IDR_ID13
6253 #define GPIO_IDR_IDR_14                     GPIO_IDR_ID14
6254 #define GPIO_IDR_IDR_15                     GPIO_IDR_ID15
6255 
6256 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
6257 #define GPIO_OTYPER_IDR_0                   GPIO_IDR_ID0
6258 #define GPIO_OTYPER_IDR_1                   GPIO_IDR_ID1
6259 #define GPIO_OTYPER_IDR_2                   GPIO_IDR_ID2
6260 #define GPIO_OTYPER_IDR_3                   GPIO_IDR_ID3
6261 #define GPIO_OTYPER_IDR_4                   GPIO_IDR_ID4
6262 #define GPIO_OTYPER_IDR_5                   GPIO_IDR_ID5
6263 #define GPIO_OTYPER_IDR_6                   GPIO_IDR_ID6
6264 #define GPIO_OTYPER_IDR_7                   GPIO_IDR_ID7
6265 #define GPIO_OTYPER_IDR_8                   GPIO_IDR_ID8
6266 #define GPIO_OTYPER_IDR_9                   GPIO_IDR_ID9
6267 #define GPIO_OTYPER_IDR_10                  GPIO_IDR_ID10
6268 #define GPIO_OTYPER_IDR_11                  GPIO_IDR_ID11
6269 #define GPIO_OTYPER_IDR_12                  GPIO_IDR_ID12
6270 #define GPIO_OTYPER_IDR_13                  GPIO_IDR_ID13
6271 #define GPIO_OTYPER_IDR_14                  GPIO_IDR_ID14
6272 #define GPIO_OTYPER_IDR_15                  GPIO_IDR_ID15
6273 
6274 /******************  Bits definition for GPIO_ODR register  *******************/
6275 #define GPIO_ODR_OD0_Pos               (0U)
6276 #define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
6277 #define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk
6278 #define GPIO_ODR_OD1_Pos               (1U)
6279 #define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
6280 #define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk
6281 #define GPIO_ODR_OD2_Pos               (2U)
6282 #define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
6283 #define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk
6284 #define GPIO_ODR_OD3_Pos               (3U)
6285 #define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
6286 #define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk
6287 #define GPIO_ODR_OD4_Pos               (4U)
6288 #define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
6289 #define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk
6290 #define GPIO_ODR_OD5_Pos               (5U)
6291 #define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
6292 #define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk
6293 #define GPIO_ODR_OD6_Pos               (6U)
6294 #define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
6295 #define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk
6296 #define GPIO_ODR_OD7_Pos               (7U)
6297 #define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
6298 #define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk
6299 #define GPIO_ODR_OD8_Pos               (8U)
6300 #define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
6301 #define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk
6302 #define GPIO_ODR_OD9_Pos               (9U)
6303 #define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
6304 #define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk
6305 #define GPIO_ODR_OD10_Pos              (10U)
6306 #define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
6307 #define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk
6308 #define GPIO_ODR_OD11_Pos              (11U)
6309 #define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
6310 #define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk
6311 #define GPIO_ODR_OD12_Pos              (12U)
6312 #define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
6313 #define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk
6314 #define GPIO_ODR_OD13_Pos              (13U)
6315 #define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
6316 #define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk
6317 #define GPIO_ODR_OD14_Pos              (14U)
6318 #define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
6319 #define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk
6320 #define GPIO_ODR_OD15_Pos              (15U)
6321 #define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
6322 #define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk
6323 
6324 /* Legacy defines */
6325 #define GPIO_ODR_ODR_0                      GPIO_ODR_OD0
6326 #define GPIO_ODR_ODR_1                      GPIO_ODR_OD1
6327 #define GPIO_ODR_ODR_2                      GPIO_ODR_OD2
6328 #define GPIO_ODR_ODR_3                      GPIO_ODR_OD3
6329 #define GPIO_ODR_ODR_4                      GPIO_ODR_OD4
6330 #define GPIO_ODR_ODR_5                      GPIO_ODR_OD5
6331 #define GPIO_ODR_ODR_6                      GPIO_ODR_OD6
6332 #define GPIO_ODR_ODR_7                      GPIO_ODR_OD7
6333 #define GPIO_ODR_ODR_8                      GPIO_ODR_OD8
6334 #define GPIO_ODR_ODR_9                      GPIO_ODR_OD9
6335 #define GPIO_ODR_ODR_10                     GPIO_ODR_OD10
6336 #define GPIO_ODR_ODR_11                     GPIO_ODR_OD11
6337 #define GPIO_ODR_ODR_12                     GPIO_ODR_OD12
6338 #define GPIO_ODR_ODR_13                     GPIO_ODR_OD13
6339 #define GPIO_ODR_ODR_14                     GPIO_ODR_OD14
6340 #define GPIO_ODR_ODR_15                     GPIO_ODR_OD15
6341 
6342 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
6343 #define GPIO_OTYPER_ODR_0                   GPIO_ODR_OD0
6344 #define GPIO_OTYPER_ODR_1                   GPIO_ODR_OD1
6345 #define GPIO_OTYPER_ODR_2                   GPIO_ODR_OD2
6346 #define GPIO_OTYPER_ODR_3                   GPIO_ODR_OD3
6347 #define GPIO_OTYPER_ODR_4                   GPIO_ODR_OD4
6348 #define GPIO_OTYPER_ODR_5                   GPIO_ODR_OD5
6349 #define GPIO_OTYPER_ODR_6                   GPIO_ODR_OD6
6350 #define GPIO_OTYPER_ODR_7                   GPIO_ODR_OD7
6351 #define GPIO_OTYPER_ODR_8                   GPIO_ODR_OD8
6352 #define GPIO_OTYPER_ODR_9                   GPIO_ODR_OD9
6353 #define GPIO_OTYPER_ODR_10                  GPIO_ODR_OD10
6354 #define GPIO_OTYPER_ODR_11                  GPIO_ODR_OD11
6355 #define GPIO_OTYPER_ODR_12                  GPIO_ODR_OD12
6356 #define GPIO_OTYPER_ODR_13                  GPIO_ODR_OD13
6357 #define GPIO_OTYPER_ODR_14                  GPIO_ODR_OD14
6358 #define GPIO_OTYPER_ODR_15                  GPIO_ODR_OD15
6359 
6360 /******************  Bits definition for GPIO_BSRR register  ******************/
6361 #define GPIO_BSRR_BS0_Pos              (0U)
6362 #define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
6363 #define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
6364 #define GPIO_BSRR_BS1_Pos              (1U)
6365 #define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
6366 #define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
6367 #define GPIO_BSRR_BS2_Pos              (2U)
6368 #define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
6369 #define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
6370 #define GPIO_BSRR_BS3_Pos              (3U)
6371 #define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
6372 #define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
6373 #define GPIO_BSRR_BS4_Pos              (4U)
6374 #define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
6375 #define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
6376 #define GPIO_BSRR_BS5_Pos              (5U)
6377 #define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
6378 #define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
6379 #define GPIO_BSRR_BS6_Pos              (6U)
6380 #define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
6381 #define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
6382 #define GPIO_BSRR_BS7_Pos              (7U)
6383 #define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
6384 #define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
6385 #define GPIO_BSRR_BS8_Pos              (8U)
6386 #define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
6387 #define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
6388 #define GPIO_BSRR_BS9_Pos              (9U)
6389 #define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
6390 #define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
6391 #define GPIO_BSRR_BS10_Pos             (10U)
6392 #define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
6393 #define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
6394 #define GPIO_BSRR_BS11_Pos             (11U)
6395 #define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
6396 #define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
6397 #define GPIO_BSRR_BS12_Pos             (12U)
6398 #define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
6399 #define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
6400 #define GPIO_BSRR_BS13_Pos             (13U)
6401 #define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
6402 #define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
6403 #define GPIO_BSRR_BS14_Pos             (14U)
6404 #define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
6405 #define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
6406 #define GPIO_BSRR_BS15_Pos             (15U)
6407 #define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
6408 #define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
6409 #define GPIO_BSRR_BR0_Pos              (16U)
6410 #define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
6411 #define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
6412 #define GPIO_BSRR_BR1_Pos              (17U)
6413 #define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
6414 #define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
6415 #define GPIO_BSRR_BR2_Pos              (18U)
6416 #define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
6417 #define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
6418 #define GPIO_BSRR_BR3_Pos              (19U)
6419 #define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
6420 #define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
6421 #define GPIO_BSRR_BR4_Pos              (20U)
6422 #define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
6423 #define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
6424 #define GPIO_BSRR_BR5_Pos              (21U)
6425 #define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
6426 #define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
6427 #define GPIO_BSRR_BR6_Pos              (22U)
6428 #define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
6429 #define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
6430 #define GPIO_BSRR_BR7_Pos              (23U)
6431 #define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
6432 #define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
6433 #define GPIO_BSRR_BR8_Pos              (24U)
6434 #define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
6435 #define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
6436 #define GPIO_BSRR_BR9_Pos              (25U)
6437 #define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
6438 #define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
6439 #define GPIO_BSRR_BR10_Pos             (26U)
6440 #define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
6441 #define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
6442 #define GPIO_BSRR_BR11_Pos             (27U)
6443 #define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
6444 #define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
6445 #define GPIO_BSRR_BR12_Pos             (28U)
6446 #define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
6447 #define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
6448 #define GPIO_BSRR_BR13_Pos             (29U)
6449 #define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
6450 #define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
6451 #define GPIO_BSRR_BR14_Pos             (30U)
6452 #define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
6453 #define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
6454 #define GPIO_BSRR_BR15_Pos             (31U)
6455 #define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
6456 #define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk
6457 
6458 /* Legacy defines */
6459 #define GPIO_BSRR_BS_0                      GPIO_BSRR_BS0
6460 #define GPIO_BSRR_BS_1                      GPIO_BSRR_BS1
6461 #define GPIO_BSRR_BS_2                      GPIO_BSRR_BS2
6462 #define GPIO_BSRR_BS_3                      GPIO_BSRR_BS3
6463 #define GPIO_BSRR_BS_4                      GPIO_BSRR_BS4
6464 #define GPIO_BSRR_BS_5                      GPIO_BSRR_BS5
6465 #define GPIO_BSRR_BS_6                      GPIO_BSRR_BS6
6466 #define GPIO_BSRR_BS_7                      GPIO_BSRR_BS7
6467 #define GPIO_BSRR_BS_8                      GPIO_BSRR_BS8
6468 #define GPIO_BSRR_BS_9                      GPIO_BSRR_BS9
6469 #define GPIO_BSRR_BS_10                     GPIO_BSRR_BS10
6470 #define GPIO_BSRR_BS_11                     GPIO_BSRR_BS11
6471 #define GPIO_BSRR_BS_12                     GPIO_BSRR_BS12
6472 #define GPIO_BSRR_BS_13                     GPIO_BSRR_BS13
6473 #define GPIO_BSRR_BS_14                     GPIO_BSRR_BS14
6474 #define GPIO_BSRR_BS_15                     GPIO_BSRR_BS15
6475 #define GPIO_BSRR_BR_0                      GPIO_BSRR_BR0
6476 #define GPIO_BSRR_BR_1                      GPIO_BSRR_BR1
6477 #define GPIO_BSRR_BR_2                      GPIO_BSRR_BR2
6478 #define GPIO_BSRR_BR_3                      GPIO_BSRR_BR3
6479 #define GPIO_BSRR_BR_4                      GPIO_BSRR_BR4
6480 #define GPIO_BSRR_BR_5                      GPIO_BSRR_BR5
6481 #define GPIO_BSRR_BR_6                      GPIO_BSRR_BR6
6482 #define GPIO_BSRR_BR_7                      GPIO_BSRR_BR7
6483 #define GPIO_BSRR_BR_8                      GPIO_BSRR_BR8
6484 #define GPIO_BSRR_BR_9                      GPIO_BSRR_BR9
6485 #define GPIO_BSRR_BR_10                     GPIO_BSRR_BR10
6486 #define GPIO_BSRR_BR_11                     GPIO_BSRR_BR11
6487 #define GPIO_BSRR_BR_12                     GPIO_BSRR_BR12
6488 #define GPIO_BSRR_BR_13                     GPIO_BSRR_BR13
6489 #define GPIO_BSRR_BR_14                     GPIO_BSRR_BR14
6490 #define GPIO_BSRR_BR_15                     GPIO_BSRR_BR15
6491 
6492 /****************** Bit definition for GPIO_LCKR register *********************/
6493 #define GPIO_LCKR_LCK0_Pos             (0U)
6494 #define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
6495 #define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
6496 #define GPIO_LCKR_LCK1_Pos             (1U)
6497 #define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
6498 #define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
6499 #define GPIO_LCKR_LCK2_Pos             (2U)
6500 #define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
6501 #define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
6502 #define GPIO_LCKR_LCK3_Pos             (3U)
6503 #define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
6504 #define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
6505 #define GPIO_LCKR_LCK4_Pos             (4U)
6506 #define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
6507 #define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
6508 #define GPIO_LCKR_LCK5_Pos             (5U)
6509 #define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
6510 #define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
6511 #define GPIO_LCKR_LCK6_Pos             (6U)
6512 #define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
6513 #define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
6514 #define GPIO_LCKR_LCK7_Pos             (7U)
6515 #define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
6516 #define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
6517 #define GPIO_LCKR_LCK8_Pos             (8U)
6518 #define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
6519 #define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
6520 #define GPIO_LCKR_LCK9_Pos             (9U)
6521 #define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
6522 #define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
6523 #define GPIO_LCKR_LCK10_Pos            (10U)
6524 #define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
6525 #define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
6526 #define GPIO_LCKR_LCK11_Pos            (11U)
6527 #define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
6528 #define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
6529 #define GPIO_LCKR_LCK12_Pos            (12U)
6530 #define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
6531 #define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
6532 #define GPIO_LCKR_LCK13_Pos            (13U)
6533 #define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
6534 #define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
6535 #define GPIO_LCKR_LCK14_Pos            (14U)
6536 #define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
6537 #define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
6538 #define GPIO_LCKR_LCK15_Pos            (15U)
6539 #define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
6540 #define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
6541 #define GPIO_LCKR_LCKK_Pos             (16U)
6542 #define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
6543 #define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk
6544 
6545 /****************** Bit definition for GPIO_AFRL register *********************/
6546 #define GPIO_AFRL_AFSEL0_Pos           (0U)
6547 #define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
6548 #define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk
6549 #define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000001 */
6550 #define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000002 */
6551 #define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000004 */
6552 #define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000008 */
6553 #define GPIO_AFRL_AFSEL1_Pos           (4U)
6554 #define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
6555 #define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk
6556 #define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000010 */
6557 #define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000020 */
6558 #define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000040 */
6559 #define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000080 */
6560 #define GPIO_AFRL_AFSEL2_Pos           (8U)
6561 #define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
6562 #define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk
6563 #define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000100 */
6564 #define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000200 */
6565 #define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000400 */
6566 #define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000800 */
6567 #define GPIO_AFRL_AFSEL3_Pos           (12U)
6568 #define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
6569 #define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk
6570 #define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00001000 */
6571 #define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00002000 */
6572 #define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00004000 */
6573 #define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00008000 */
6574 #define GPIO_AFRL_AFSEL4_Pos           (16U)
6575 #define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
6576 #define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk
6577 #define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00010000 */
6578 #define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00020000 */
6579 #define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00040000 */
6580 #define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00080000 */
6581 #define GPIO_AFRL_AFSEL5_Pos           (20U)
6582 #define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
6583 #define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk
6584 #define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00100000 */
6585 #define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00200000 */
6586 #define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00400000 */
6587 #define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00800000 */
6588 #define GPIO_AFRL_AFSEL6_Pos           (24U)
6589 #define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
6590 #define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk
6591 #define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x01000000 */
6592 #define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x02000000 */
6593 #define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x04000000 */
6594 #define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x08000000 */
6595 #define GPIO_AFRL_AFSEL7_Pos           (28U)
6596 #define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
6597 #define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk
6598 #define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x10000000 */
6599 #define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x20000000 */
6600 #define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x40000000 */
6601 #define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x80000000 */
6602 
6603 /* Legacy defines */
6604 #define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0
6605 #define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1
6606 #define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2
6607 #define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3
6608 #define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4
6609 #define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5
6610 #define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6
6611 #define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7
6612 
6613 /****************** Bit definition for GPIO_AFRH register *********************/
6614 #define GPIO_AFRH_AFSEL8_Pos           (0U)
6615 #define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
6616 #define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk
6617 #define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000001 */
6618 #define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000002 */
6619 #define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000004 */
6620 #define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000008 */
6621 #define GPIO_AFRH_AFSEL9_Pos           (4U)
6622 #define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
6623 #define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk
6624 #define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000010 */
6625 #define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000020 */
6626 #define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000040 */
6627 #define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000080 */
6628 #define GPIO_AFRH_AFSEL10_Pos          (8U)
6629 #define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
6630 #define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk
6631 #define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000100 */
6632 #define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000200 */
6633 #define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000400 */
6634 #define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000800 */
6635 #define GPIO_AFRH_AFSEL11_Pos          (12U)
6636 #define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
6637 #define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk
6638 #define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00001000 */
6639 #define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00002000 */
6640 #define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00004000 */
6641 #define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00008000 */
6642 #define GPIO_AFRH_AFSEL12_Pos          (16U)
6643 #define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
6644 #define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk
6645 #define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00010000 */
6646 #define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00020000 */
6647 #define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00040000 */
6648 #define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00080000 */
6649 #define GPIO_AFRH_AFSEL13_Pos          (20U)
6650 #define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
6651 #define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk
6652 #define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00100000 */
6653 #define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00200000 */
6654 #define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00400000 */
6655 #define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00800000 */
6656 #define GPIO_AFRH_AFSEL14_Pos          (24U)
6657 #define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
6658 #define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk
6659 #define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x01000000 */
6660 #define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x02000000 */
6661 #define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x04000000 */
6662 #define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x08000000 */
6663 #define GPIO_AFRH_AFSEL15_Pos          (28U)
6664 #define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
6665 #define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk
6666 #define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x10000000 */
6667 #define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x20000000 */
6668 #define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x40000000 */
6669 #define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x80000000 */
6670 
6671 /* Legacy defines */
6672 #define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8
6673 #define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9
6674 #define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10
6675 #define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11
6676 #define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12
6677 #define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13
6678 #define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14
6679 #define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15
6680 
6681 /******************  Bits definition for GPIO_BRR register  ******************/
6682 #define GPIO_BRR_BR0_Pos               (0U)
6683 #define GPIO_BRR_BR0_Msk               (0x1UL << GPIO_BRR_BR0_Pos)             /*!< 0x00000001 */
6684 #define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk
6685 #define GPIO_BRR_BR1_Pos               (1U)
6686 #define GPIO_BRR_BR1_Msk               (0x1UL << GPIO_BRR_BR1_Pos)             /*!< 0x00000002 */
6687 #define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk
6688 #define GPIO_BRR_BR2_Pos               (2U)
6689 #define GPIO_BRR_BR2_Msk               (0x1UL << GPIO_BRR_BR2_Pos)             /*!< 0x00000004 */
6690 #define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk
6691 #define GPIO_BRR_BR3_Pos               (3U)
6692 #define GPIO_BRR_BR3_Msk               (0x1UL << GPIO_BRR_BR3_Pos)             /*!< 0x00000008 */
6693 #define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk
6694 #define GPIO_BRR_BR4_Pos               (4U)
6695 #define GPIO_BRR_BR4_Msk               (0x1UL << GPIO_BRR_BR4_Pos)             /*!< 0x00000010 */
6696 #define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk
6697 #define GPIO_BRR_BR5_Pos               (5U)
6698 #define GPIO_BRR_BR5_Msk               (0x1UL << GPIO_BRR_BR5_Pos)             /*!< 0x00000020 */
6699 #define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk
6700 #define GPIO_BRR_BR6_Pos               (6U)
6701 #define GPIO_BRR_BR6_Msk               (0x1UL << GPIO_BRR_BR6_Pos)             /*!< 0x00000040 */
6702 #define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk
6703 #define GPIO_BRR_BR7_Pos               (7U)
6704 #define GPIO_BRR_BR7_Msk               (0x1UL << GPIO_BRR_BR7_Pos)             /*!< 0x00000080 */
6705 #define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk
6706 #define GPIO_BRR_BR8_Pos               (8U)
6707 #define GPIO_BRR_BR8_Msk               (0x1UL << GPIO_BRR_BR8_Pos)             /*!< 0x00000100 */
6708 #define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk
6709 #define GPIO_BRR_BR9_Pos               (9U)
6710 #define GPIO_BRR_BR9_Msk               (0x1UL << GPIO_BRR_BR9_Pos)             /*!< 0x00000200 */
6711 #define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk
6712 #define GPIO_BRR_BR10_Pos              (10U)
6713 #define GPIO_BRR_BR10_Msk              (0x1UL << GPIO_BRR_BR10_Pos)            /*!< 0x00000400 */
6714 #define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk
6715 #define GPIO_BRR_BR11_Pos              (11U)
6716 #define GPIO_BRR_BR11_Msk              (0x1UL << GPIO_BRR_BR11_Pos)            /*!< 0x00000800 */
6717 #define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk
6718 #define GPIO_BRR_BR12_Pos              (12U)
6719 #define GPIO_BRR_BR12_Msk              (0x1UL << GPIO_BRR_BR12_Pos)            /*!< 0x00001000 */
6720 #define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk
6721 #define GPIO_BRR_BR13_Pos              (13U)
6722 #define GPIO_BRR_BR13_Msk              (0x1UL << GPIO_BRR_BR13_Pos)            /*!< 0x00002000 */
6723 #define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk
6724 #define GPIO_BRR_BR14_Pos              (14U)
6725 #define GPIO_BRR_BR14_Msk              (0x1UL << GPIO_BRR_BR14_Pos)            /*!< 0x00004000 */
6726 #define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk
6727 #define GPIO_BRR_BR15_Pos              (15U)
6728 #define GPIO_BRR_BR15_Msk              (0x1UL << GPIO_BRR_BR15_Pos)            /*!< 0x00008000 */
6729 #define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk
6730 
6731 /* Legacy defines */
6732 #define GPIO_BRR_BR_0                       GPIO_BRR_BR0
6733 #define GPIO_BRR_BR_1                       GPIO_BRR_BR1
6734 #define GPIO_BRR_BR_2                       GPIO_BRR_BR2
6735 #define GPIO_BRR_BR_3                       GPIO_BRR_BR3
6736 #define GPIO_BRR_BR_4                       GPIO_BRR_BR4
6737 #define GPIO_BRR_BR_5                       GPIO_BRR_BR5
6738 #define GPIO_BRR_BR_6                       GPIO_BRR_BR6
6739 #define GPIO_BRR_BR_7                       GPIO_BRR_BR7
6740 #define GPIO_BRR_BR_8                       GPIO_BRR_BR8
6741 #define GPIO_BRR_BR_9                       GPIO_BRR_BR9
6742 #define GPIO_BRR_BR_10                      GPIO_BRR_BR10
6743 #define GPIO_BRR_BR_11                      GPIO_BRR_BR11
6744 #define GPIO_BRR_BR_12                      GPIO_BRR_BR12
6745 #define GPIO_BRR_BR_13                      GPIO_BRR_BR13
6746 #define GPIO_BRR_BR_14                      GPIO_BRR_BR14
6747 #define GPIO_BRR_BR_15                      GPIO_BRR_BR15
6748 
6749 
6750 /******************************************************************************/
6751 /*                                                                            */
6752 /*                      Inter-integrated Circuit Interface (I2C)              */
6753 /*                                                                            */
6754 /******************************************************************************/
6755 /*******************  Bit definition for I2C_CR1 register  *******************/
6756 #define I2C_CR1_PE_Pos               (0U)
6757 #define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */
6758 #define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable                   */
6759 #define I2C_CR1_TXIE_Pos             (1U)
6760 #define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */
6761 #define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable                 */
6762 #define I2C_CR1_RXIE_Pos             (2U)
6763 #define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */
6764 #define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable                 */
6765 #define I2C_CR1_ADDRIE_Pos           (3U)
6766 #define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */
6767 #define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable      */
6768 #define I2C_CR1_NACKIE_Pos           (4U)
6769 #define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */
6770 #define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable      */
6771 #define I2C_CR1_STOPIE_Pos           (5U)
6772 #define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */
6773 #define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable     */
6774 #define I2C_CR1_TCIE_Pos             (6U)
6775 #define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */
6776 #define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable  */
6777 #define I2C_CR1_ERRIE_Pos            (7U)
6778 #define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */
6779 #define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable             */
6780 #define I2C_CR1_DNF_Pos              (8U)
6781 #define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */
6782 #define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter                */
6783 #define I2C_CR1_ANFOFF_Pos           (12U)
6784 #define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */
6785 #define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF             */
6786 #define I2C_CR1_SWRST_Pos            (13U)
6787 #define I2C_CR1_SWRST_Msk            (0x1UL << I2C_CR1_SWRST_Pos)              /*!< 0x00002000 */
6788 #define I2C_CR1_SWRST                I2C_CR1_SWRST_Msk                         /*!< Software reset                      */
6789 #define I2C_CR1_TXDMAEN_Pos          (14U)
6790 #define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */
6791 #define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable    */
6792 #define I2C_CR1_RXDMAEN_Pos          (15U)
6793 #define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */
6794 #define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable       */
6795 #define I2C_CR1_SBC_Pos              (16U)
6796 #define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */
6797 #define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control                  */
6798 #define I2C_CR1_NOSTRETCH_Pos        (17U)
6799 #define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */
6800 #define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable            */
6801 #define I2C_CR1_WUPEN_Pos            (18U)
6802 #define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */
6803 #define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable             */
6804 #define I2C_CR1_GCEN_Pos             (19U)
6805 #define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */
6806 #define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable                 */
6807 #define I2C_CR1_SMBHEN_Pos           (20U)
6808 #define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */
6809 #define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable           */
6810 #define I2C_CR1_SMBDEN_Pos           (21U)
6811 #define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */
6812 #define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
6813 #define I2C_CR1_ALERTEN_Pos          (22U)
6814 #define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */
6815 #define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable                  */
6816 #define I2C_CR1_PECEN_Pos            (23U)
6817 #define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */
6818 #define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable                          */
6819 
6820 /******************  Bit definition for I2C_CR2 register  ********************/
6821 #define I2C_CR2_SADD_Pos             (0U)
6822 #define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */
6823 #define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode)                             */
6824 #define I2C_CR2_RD_WRN_Pos           (10U)
6825 #define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */
6826 #define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode)                        */
6827 #define I2C_CR2_ADD10_Pos            (11U)
6828 #define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */
6829 #define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode)                    */
6830 #define I2C_CR2_HEAD10R_Pos          (12U)
6831 #define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */
6832 #define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
6833 #define I2C_CR2_START_Pos            (13U)
6834 #define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */
6835 #define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation                                        */
6836 #define I2C_CR2_STOP_Pos             (14U)
6837 #define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */
6838 #define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode)                           */
6839 #define I2C_CR2_NACK_Pos             (15U)
6840 #define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */
6841 #define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode)                            */
6842 #define I2C_CR2_NBYTES_Pos           (16U)
6843 #define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */
6844 #define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes                                         */
6845 #define I2C_CR2_RELOAD_Pos           (24U)
6846 #define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */
6847 #define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode                                      */
6848 #define I2C_CR2_AUTOEND_Pos          (25U)
6849 #define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */
6850 #define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode)                        */
6851 #define I2C_CR2_PECBYTE_Pos          (26U)
6852 #define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */
6853 #define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte                              */
6854 
6855 /*******************  Bit definition for I2C_OAR1 register  ******************/
6856 #define I2C_OAR1_OA1_Pos             (0U)
6857 #define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */
6858 #define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1   */
6859 #define I2C_OAR1_OA1MODE_Pos         (10U)
6860 #define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */
6861 #define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
6862 #define I2C_OAR1_OA1EN_Pos           (15U)
6863 #define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */
6864 #define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable      */
6865 
6866 /*******************  Bit definition for I2C_OAR2 register  ******************/
6867 #define I2C_OAR2_OA2_Pos             (1U)
6868 #define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */
6869 #define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
6870 #define I2C_OAR2_OA2MSK_Pos          (8U)
6871 #define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */
6872 #define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
6873 #define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
6874 #define I2C_OAR2_OA2MASK01_Pos       (8U)
6875 #define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */
6876 #define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
6877 #define I2C_OAR2_OA2MASK02_Pos       (9U)
6878 #define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */
6879 #define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
6880 #define I2C_OAR2_OA2MASK03_Pos       (8U)
6881 #define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */
6882 #define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
6883 #define I2C_OAR2_OA2MASK04_Pos       (10U)
6884 #define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */
6885 #define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
6886 #define I2C_OAR2_OA2MASK05_Pos       (8U)
6887 #define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */
6888 #define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
6889 #define I2C_OAR2_OA2MASK06_Pos       (9U)
6890 #define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */
6891 #define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
6892 #define I2C_OAR2_OA2MASK07_Pos       (8U)
6893 #define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */
6894 #define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
6895 #define I2C_OAR2_OA2EN_Pos           (15U)
6896 #define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */
6897 #define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
6898 
6899 /*******************  Bit definition for I2C_TIMINGR register *******************/
6900 #define I2C_TIMINGR_SCLL_Pos         (0U)
6901 #define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */
6902 #define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode)  */
6903 #define I2C_TIMINGR_SCLH_Pos         (8U)
6904 #define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */
6905 #define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
6906 #define I2C_TIMINGR_SDADEL_Pos       (16U)
6907 #define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */
6908 #define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time                */
6909 #define I2C_TIMINGR_SCLDEL_Pos       (20U)
6910 #define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */
6911 #define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time               */
6912 #define I2C_TIMINGR_PRESC_Pos        (28U)
6913 #define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */
6914 #define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler             */
6915 
6916 /******************* Bit definition for I2C_TIMEOUTR register *******************/
6917 #define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
6918 #define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */
6919 #define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A                 */
6920 #define I2C_TIMEOUTR_TIDLE_Pos       (12U)
6921 #define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */
6922 #define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection  */
6923 #define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
6924 #define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */
6925 #define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable          */
6926 #define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
6927 #define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */
6928 #define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B                 */
6929 #define I2C_TIMEOUTR_TEXTEN_Pos      (31U)
6930 #define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */
6931 #define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
6932 
6933 /******************  Bit definition for I2C_ISR register  *********************/
6934 #define I2C_ISR_TXE_Pos              (0U)
6935 #define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */
6936 #define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty    */
6937 #define I2C_ISR_TXIS_Pos             (1U)
6938 #define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */
6939 #define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status       */
6940 #define I2C_ISR_RXNE_Pos             (2U)
6941 #define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */
6942 #define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
6943 #define I2C_ISR_ADDR_Pos             (3U)
6944 #define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */
6945 #define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)    */
6946 #define I2C_ISR_NACKF_Pos            (4U)
6947 #define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */
6948 #define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag              */
6949 #define I2C_ISR_STOPF_Pos            (5U)
6950 #define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */
6951 #define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag             */
6952 #define I2C_ISR_TC_Pos               (6U)
6953 #define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */
6954 #define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
6955 #define I2C_ISR_TCR_Pos              (7U)
6956 #define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */
6957 #define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload        */
6958 #define I2C_ISR_BERR_Pos             (8U)
6959 #define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */
6960 #define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error                       */
6961 #define I2C_ISR_ARLO_Pos             (9U)
6962 #define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */
6963 #define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost                */
6964 #define I2C_ISR_OVR_Pos              (10U)
6965 #define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */
6966 #define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun                */
6967 #define I2C_ISR_PECERR_Pos           (11U)
6968 #define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */
6969 #define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception          */
6970 #define I2C_ISR_TIMEOUT_Pos          (12U)
6971 #define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */
6972 #define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag  */
6973 #define I2C_ISR_ALERT_Pos            (13U)
6974 #define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */
6975 #define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert                     */
6976 #define I2C_ISR_BUSY_Pos             (15U)
6977 #define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */
6978 #define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy                        */
6979 #define I2C_ISR_DIR_Pos              (16U)
6980 #define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */
6981 #define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
6982 #define I2C_ISR_ADDCODE_Pos          (17U)
6983 #define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */
6984 #define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
6985 
6986 /******************  Bit definition for I2C_ICR register  *********************/
6987 #define I2C_ICR_ADDRCF_Pos           (3U)
6988 #define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */
6989 #define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag  */
6990 #define I2C_ICR_NACKCF_Pos           (4U)
6991 #define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */
6992 #define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag             */
6993 #define I2C_ICR_STOPCF_Pos           (5U)
6994 #define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */
6995 #define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag   */
6996 #define I2C_ICR_BERRCF_Pos           (8U)
6997 #define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */
6998 #define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag        */
6999 #define I2C_ICR_ARLOCF_Pos           (9U)
7000 #define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */
7001 #define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
7002 #define I2C_ICR_OVRCF_Pos            (10U)
7003 #define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */
7004 #define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
7005 #define I2C_ICR_PECCF_Pos            (11U)
7006 #define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */
7007 #define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag        */
7008 #define I2C_ICR_TIMOUTCF_Pos         (12U)
7009 #define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */
7010 #define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag          */
7011 #define I2C_ICR_ALERTCF_Pos          (13U)
7012 #define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */
7013 #define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag            */
7014 
7015 /******************  Bit definition for I2C_PECR register  *********************/
7016 #define I2C_PECR_PEC_Pos             (0U)
7017 #define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */
7018 #define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
7019 
7020 /******************  Bit definition for I2C_RXDR register  *********************/
7021 #define I2C_RXDR_RXDATA_Pos          (0U)
7022 #define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */
7023 #define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
7024 
7025 /******************  Bit definition for I2C_TXDR register  *********************/
7026 #define I2C_TXDR_TXDATA_Pos          (0U)
7027 #define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */
7028 #define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
7029 
7030 /******************************************************************************/
7031 /*                                                                            */
7032 /*                           Independent WATCHDOG                             */
7033 /*                                                                            */
7034 /******************************************************************************/
7035 /*******************  Bit definition for IWDG_KR register  ********************/
7036 #define IWDG_KR_KEY_Pos      (0U)
7037 #define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */
7038 #define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
7039 
7040 /*******************  Bit definition for IWDG_PR register  ********************/
7041 #define IWDG_PR_PR_Pos       (0U)
7042 #define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */
7043 #define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */
7044 #define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                         /*!< 0x00000001 */
7045 #define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                         /*!< 0x00000002 */
7046 #define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                         /*!< 0x00000004 */
7047 
7048 /*******************  Bit definition for IWDG_RLR register  *******************/
7049 #define IWDG_RLR_RL_Pos      (0U)
7050 #define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */
7051 #define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */
7052 
7053 /*******************  Bit definition for IWDG_SR register  ********************/
7054 #define IWDG_SR_PVU_Pos      (0U)
7055 #define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */
7056 #define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
7057 #define IWDG_SR_RVU_Pos      (1U)
7058 #define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */
7059 #define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
7060 #define IWDG_SR_WVU_Pos      (2U)
7061 #define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */
7062 #define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
7063 
7064 /*******************  Bit definition for IWDG_KR register  ********************/
7065 #define IWDG_WINR_WIN_Pos    (0U)
7066 #define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */
7067 #define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
7068 
7069 /******************************************************************************/
7070 /*                                                                            */
7071 /*                         Operational Amplifier (OPAMP)                      */
7072 /*                                                                            */
7073 /******************************************************************************/
7074 /*********************  Bit definition for OPAMPx_CSR register  ***************/
7075 #define OPAMP_CSR_OPAMPxEN_Pos       (0U)
7076 #define OPAMP_CSR_OPAMPxEN_Msk       (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)         /*!< 0x00000001 */
7077 #define OPAMP_CSR_OPAMPxEN           OPAMP_CSR_OPAMPxEN_Msk                    /*!< OPAMP enable */
7078 #define OPAMP_CSR_FORCEVP_Pos        (1U)
7079 #define OPAMP_CSR_FORCEVP_Msk        (0x1UL << OPAMP_CSR_FORCEVP_Pos)          /*!< 0x00000002 */
7080 #define OPAMP_CSR_FORCEVP            OPAMP_CSR_FORCEVP_Msk                     /*!< Connect the internal references to the plus input of the OPAMPX */
7081 #define OPAMP_CSR_VPSEL_Pos          (2U)
7082 #define OPAMP_CSR_VPSEL_Msk          (0x3UL << OPAMP_CSR_VPSEL_Pos)            /*!< 0x0000000C */
7083 #define OPAMP_CSR_VPSEL              OPAMP_CSR_VPSEL_Msk                       /*!< Non inverting input selection */
7084 #define OPAMP_CSR_VPSEL_0            (0x1UL << OPAMP_CSR_VPSEL_Pos)            /*!< 0x00000004 */
7085 #define OPAMP_CSR_VPSEL_1            (0x2UL << OPAMP_CSR_VPSEL_Pos)            /*!< 0x00000008 */
7086 #define OPAMP_CSR_USERTRIM_Pos       (4U)
7087 #define OPAMP_CSR_USERTRIM_Msk       (0x1UL << OPAMP_CSR_USERTRIM_Pos)         /*!< 0x00000010 */
7088 #define OPAMP_CSR_USERTRIM           OPAMP_CSR_USERTRIM_Msk                    /*!< User trimming enable */
7089 #define OPAMP_CSR_VMSEL_Pos          (5U)
7090 #define OPAMP_CSR_VMSEL_Msk          (0x3UL << OPAMP_CSR_VMSEL_Pos)            /*!< 0x00000060 */
7091 #define OPAMP_CSR_VMSEL              OPAMP_CSR_VMSEL_Msk                       /*!< Inverting input selection */
7092 #define OPAMP_CSR_VMSEL_0            (0x1UL << OPAMP_CSR_VMSEL_Pos)            /*!< 0x00000020 */
7093 #define OPAMP_CSR_VMSEL_1            (0x2UL << OPAMP_CSR_VMSEL_Pos)            /*!< 0x00000040 */
7094 #define OPAMP_CSR_HIGHSPEEDEN_Pos    (7U)
7095 #define OPAMP_CSR_HIGHSPEEDEN_Msk    (0x1UL << OPAMP_CSR_HIGHSPEEDEN_Pos)      /*!< 0x00000080 */
7096 #define OPAMP_CSR_HIGHSPEEDEN        OPAMP_CSR_HIGHSPEEDEN_Msk                 /*!< High speed mode enable */
7097 #define OPAMP_CSR_OPAMPINTEN_Pos     (8U)
7098 #define OPAMP_CSR_OPAMPINTEN_Msk     (0x1UL << OPAMP_CSR_OPAMPINTEN_Pos)       /*!< 0x00000100 */
7099 #define OPAMP_CSR_OPAMPINTEN         OPAMP_CSR_OPAMPINTEN_Msk                  /*!< Internal output enable */
7100 #define OPAMP_CSR_CALON_Pos          (11U)
7101 #define OPAMP_CSR_CALON_Msk          (0x1UL << OPAMP_CSR_CALON_Pos)            /*!< 0x00000800 */
7102 #define OPAMP_CSR_CALON              OPAMP_CSR_CALON_Msk                       /*!< Calibration mode enable */
7103 #define OPAMP_CSR_CALSEL_Pos         (12U)
7104 #define OPAMP_CSR_CALSEL_Msk         (0x3UL << OPAMP_CSR_CALSEL_Pos)           /*!< 0x00003000 */
7105 #define OPAMP_CSR_CALSEL             OPAMP_CSR_CALSEL_Msk                      /*!< Calibration selection */
7106 #define OPAMP_CSR_CALSEL_0           (0x1UL << OPAMP_CSR_CALSEL_Pos)           /*!< 0x00001000 */
7107 #define OPAMP_CSR_CALSEL_1           (0x2UL << OPAMP_CSR_CALSEL_Pos)           /*!< 0x00002000 */
7108 #define OPAMP_CSR_PGGAIN_Pos         (14U)
7109 #define OPAMP_CSR_PGGAIN_Msk         (0x1FUL << OPAMP_CSR_PGGAIN_Pos)          /*!< 0x0007C000 */
7110 #define OPAMP_CSR_PGGAIN             OPAMP_CSR_PGGAIN_Msk                      /*!< Gain in PGA mode */
7111 #define OPAMP_CSR_PGGAIN_0           (0x1UL << OPAMP_CSR_PGGAIN_Pos)           /*!< 0x00004000 */
7112 #define OPAMP_CSR_PGGAIN_1           (0x2UL << OPAMP_CSR_PGGAIN_Pos)           /*!< 0x00008000 */
7113 #define OPAMP_CSR_PGGAIN_2           (0x4UL << OPAMP_CSR_PGGAIN_Pos)           /*!< 0x00010000 */
7114 #define OPAMP_CSR_PGGAIN_3           (0x8UL << OPAMP_CSR_PGGAIN_Pos)           /*!< 0x00020000 */
7115 #define OPAMP_CSR_PGGAIN_4           (0x10UL << OPAMP_CSR_PGGAIN_Pos)          /*!< 0x00040000 */
7116 #define OPAMP_CSR_TRIMOFFSETP_Pos    (19U)
7117 #define OPAMP_CSR_TRIMOFFSETP_Msk    (0x1FUL << OPAMP_CSR_TRIMOFFSETP_Pos)     /*!< 0x00F80000 */
7118 #define OPAMP_CSR_TRIMOFFSETP        OPAMP_CSR_TRIMOFFSETP_Msk                 /*!< Offset trimming value (PMOS) */
7119 #define OPAMP_CSR_TRIMOFFSETN_Pos    (24U)
7120 #define OPAMP_CSR_TRIMOFFSETN_Msk    (0x1FUL << OPAMP_CSR_TRIMOFFSETN_Pos)     /*!< 0x1F000000 */
7121 #define OPAMP_CSR_TRIMOFFSETN        OPAMP_CSR_TRIMOFFSETN_Msk                 /*!< Offset trimming value (NMOS) */
7122 #define OPAMP_CSR_OUTCAL_Pos         (30U)
7123 #define OPAMP_CSR_OUTCAL_Msk         (0x1UL << OPAMP_CSR_OUTCAL_Pos)           /*!< 0x40000000 */
7124 #define OPAMP_CSR_OUTCAL             OPAMP_CSR_OUTCAL_Msk                      /*!< OPAMP ouput status flag */
7125 #define OPAMP_CSR_LOCK_Pos           (31U)
7126 #define OPAMP_CSR_LOCK_Msk           (0x1UL << OPAMP_CSR_LOCK_Pos)             /*!< 0x80000000 */
7127 #define OPAMP_CSR_LOCK               OPAMP_CSR_LOCK_Msk                        /*!< OPAMP control/status register lock */
7128 
7129 /*********************  Bit definition for OPAMPx_TCMR register  ***************/
7130 
7131 #define OPAMP_TCMR_VMSSEL_Pos        (0U)
7132 #define OPAMP_TCMR_VMSSEL_Msk        (0x1UL << OPAMP_TCMR_VMSSEL_Pos)          /*!< 0x00000001 */
7133 #define OPAMP_TCMR_VMSSEL            OPAMP_TCMR_VMSSEL_Msk                     /*!< Secondary inverting input selection */
7134 #define OPAMP_TCMR_VPSSEL_Pos        (1U)
7135 #define OPAMP_TCMR_VPSSEL_Msk        (0x3UL << OPAMP_TCMR_VPSSEL_Pos)          /*!< 0x00000006 */
7136 #define OPAMP_TCMR_VPSSEL            OPAMP_TCMR_VPSSEL_Msk                     /*!< Secondary non inverting input selection */
7137 #define OPAMP_TCMR_VPSSEL_0          (0x1UL << OPAMP_TCMR_VPSSEL_Pos)          /*!< 0x00000002 */
7138 #define OPAMP_TCMR_VPSSEL_1          (0x2UL << OPAMP_TCMR_VPSSEL_Pos)          /*!< 0x00000004 */
7139 #define OPAMP_TCMR_T1CMEN_Pos        (3U)
7140 #define OPAMP_TCMR_T1CMEN_Msk        (0x1UL << OPAMP_TCMR_T1CMEN_Pos)          /*!< 0x00000008 */
7141 #define OPAMP_TCMR_T1CMEN            OPAMP_TCMR_T1CMEN_Msk                     /*!< Timer 1 controlled mux mode enable */
7142 #define OPAMP_TCMR_T8CMEN_Pos        (4U)
7143 #define OPAMP_TCMR_T8CMEN_Msk        (0x1UL << OPAMP_TCMR_T8CMEN_Pos)          /*!< 0x00000010 */
7144 #define OPAMP_TCMR_T8CMEN            OPAMP_TCMR_T8CMEN_Msk                     /*!< Timer 8 controlled mux mode enable */
7145 #define OPAMP_TCMR_T20CMEN_Pos       (5U)
7146 #define OPAMP_TCMR_T20CMEN_Msk       (0x1UL << OPAMP_TCMR_T20CMEN_Pos)         /*!< 0x00000020 */
7147 #define OPAMP_TCMR_T20CMEN           OPAMP_TCMR_T20CMEN_Msk                    /*!< Timer 20 controlled mux mode enable */
7148 #define OPAMP_TCMR_LOCK_Pos          (31U)
7149 #define OPAMP_TCMR_LOCK_Msk          (0x1UL << OPAMP_TCMR_LOCK_Pos)            /*!< 0x80000000 */
7150 #define OPAMP_TCMR_LOCK              OPAMP_TCMR_LOCK_Msk                       /*!< OPAMP SW control register lock */
7151 
7152 
7153 /******************************************************************************/
7154 /*                                                                            */
7155 /*                             Power Control                                  */
7156 /*                                                                            */
7157 /******************************************************************************/
7158 
7159 /********************  Bit definition for PWR_CR1 register  ********************/
7160 
7161 #define PWR_CR1_LPR_Pos              (14U)
7162 #define PWR_CR1_LPR_Msk              (0x1UL << PWR_CR1_LPR_Pos)                /*!< 0x00004000 */
7163 #define PWR_CR1_LPR                  PWR_CR1_LPR_Msk                           /*!< Regulator low-power mode */
7164 #define PWR_CR1_VOS_Pos              (9U)
7165 #define PWR_CR1_VOS_Msk              (0x3UL << PWR_CR1_VOS_Pos)                /*!< 0x00000600 */
7166 #define PWR_CR1_VOS                  PWR_CR1_VOS_Msk                           /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
7167 #define PWR_CR1_VOS_0                (0x1UL << PWR_CR1_VOS_Pos)                /*!< 0x00000200 */
7168 #define PWR_CR1_VOS_1                (0x2UL << PWR_CR1_VOS_Pos)                /*!< 0x00000400 */
7169 #define PWR_CR1_DBP_Pos              (8U)
7170 #define PWR_CR1_DBP_Msk              (0x1UL << PWR_CR1_DBP_Pos)                /*!< 0x00000100 */
7171 #define PWR_CR1_DBP                  PWR_CR1_DBP_Msk                           /*!< Disable Back-up domain Protection */
7172 #define PWR_CR1_LPMS_Pos             (0U)
7173 #define PWR_CR1_LPMS_Msk             (0x7UL << PWR_CR1_LPMS_Pos)               /*!< 0x00000007 */
7174 #define PWR_CR1_LPMS                 PWR_CR1_LPMS_Msk                          /*!< Low-power mode selection field */
7175 #define PWR_CR1_LPMS_STOP0           (0x00000000U)                             /*!< Stop 0 mode */
7176 #define PWR_CR1_LPMS_STOP1_Pos       (0U)
7177 #define PWR_CR1_LPMS_STOP1_Msk       (0x1UL << PWR_CR1_LPMS_STOP1_Pos)         /*!< 0x00000001 */
7178 #define PWR_CR1_LPMS_STOP1           PWR_CR1_LPMS_STOP1_Msk                    /*!< Stop 1 mode */
7179 #define PWR_CR1_LPMS_STANDBY_Pos     (0U)
7180 #define PWR_CR1_LPMS_STANDBY_Msk     (0x3UL << PWR_CR1_LPMS_STANDBY_Pos)       /*!< 0x00000003 */
7181 #define PWR_CR1_LPMS_STANDBY         PWR_CR1_LPMS_STANDBY_Msk                  /*!< Stand-by mode */
7182 #define PWR_CR1_LPMS_SHUTDOWN_Pos    (2U)
7183 #define PWR_CR1_LPMS_SHUTDOWN_Msk    (0x1UL << PWR_CR1_LPMS_SHUTDOWN_Pos)      /*!< 0x00000004 */
7184 #define PWR_CR1_LPMS_SHUTDOWN        PWR_CR1_LPMS_SHUTDOWN_Msk                 /*!< Shut-down mode */
7185 
7186 
7187 /********************  Bit definition for PWR_CR2 register  ********************/
7188 
7189 /*!< PVME  Peripheral Voltage Monitor Enable */
7190 #define PWR_CR2_PVME_Pos             (4U)
7191 #define PWR_CR2_PVME_Msk             (0xFUL << PWR_CR2_PVME_Pos)               /*!< 0x000000F0 */
7192 #define PWR_CR2_PVME                 PWR_CR2_PVME_Msk                          /*!< PVM bits field */
7193 #define PWR_CR2_PVME4_Pos            (7U)
7194 #define PWR_CR2_PVME4_Msk            (0x1UL << PWR_CR2_PVME4_Pos)              /*!< 0x00000080 */
7195 #define PWR_CR2_PVME4                PWR_CR2_PVME4_Msk                         /*!< PVM 4 Enable */
7196 #define PWR_CR2_PVME3_Pos            (6U)
7197 #define PWR_CR2_PVME3_Msk            (0x1UL << PWR_CR2_PVME3_Pos)              /*!< 0x00000040 */
7198 #define PWR_CR2_PVME3                PWR_CR2_PVME3_Msk                         /*!< PVM 3 Enable */
7199 #define PWR_CR2_PVME2_Pos            (5U)
7200 #define PWR_CR2_PVME2_Msk            (0x1UL << PWR_CR2_PVME2_Pos)              /*!< 0x00000020 */
7201 #define PWR_CR2_PVME2                PWR_CR2_PVME2_Msk                         /*!< PVM 2 Enable */
7202 #define PWR_CR2_PVME1_Pos            (4U)
7203 #define PWR_CR2_PVME1_Msk            (0x1UL << PWR_CR2_PVME1_Pos)              /*!< 0x00000010 */
7204 #define PWR_CR2_PVME1                PWR_CR2_PVME1_Msk                         /*!< PVM 1 Enable */
7205 
7206 /*!< PVD level configuration */
7207 #define PWR_CR2_PLS_Pos              (1U)
7208 #define PWR_CR2_PLS_Msk              (0x7UL << PWR_CR2_PLS_Pos)                /*!< 0x0000000E */
7209 #define PWR_CR2_PLS                  PWR_CR2_PLS_Msk                           /*!< PVD level selection */
7210 #define PWR_CR2_PLS_LEV0             (0x00000000U)                             /*!< PVD level 0 */
7211 #define PWR_CR2_PLS_LEV1_Pos         (1U)
7212 #define PWR_CR2_PLS_LEV1_Msk         (0x1UL << PWR_CR2_PLS_LEV1_Pos)           /*!< 0x00000002 */
7213 #define PWR_CR2_PLS_LEV1             PWR_CR2_PLS_LEV1_Msk                      /*!< PVD level 1 */
7214 #define PWR_CR2_PLS_LEV2_Pos         (2U)
7215 #define PWR_CR2_PLS_LEV2_Msk         (0x1UL << PWR_CR2_PLS_LEV2_Pos)           /*!< 0x00000004 */
7216 #define PWR_CR2_PLS_LEV2             PWR_CR2_PLS_LEV2_Msk                      /*!< PVD level 2 */
7217 #define PWR_CR2_PLS_LEV3_Pos         (1U)
7218 #define PWR_CR2_PLS_LEV3_Msk         (0x3UL << PWR_CR2_PLS_LEV3_Pos)           /*!< 0x00000006 */
7219 #define PWR_CR2_PLS_LEV3             PWR_CR2_PLS_LEV3_Msk                      /*!< PVD level 3 */
7220 #define PWR_CR2_PLS_LEV4_Pos         (3U)
7221 #define PWR_CR2_PLS_LEV4_Msk         (0x1UL << PWR_CR2_PLS_LEV4_Pos)           /*!< 0x00000008 */
7222 #define PWR_CR2_PLS_LEV4             PWR_CR2_PLS_LEV4_Msk                      /*!< PVD level 4 */
7223 #define PWR_CR2_PLS_LEV5_Pos         (1U)
7224 #define PWR_CR2_PLS_LEV5_Msk         (0x5UL << PWR_CR2_PLS_LEV5_Pos)           /*!< 0x0000000A */
7225 #define PWR_CR2_PLS_LEV5             PWR_CR2_PLS_LEV5_Msk                      /*!< PVD level 5 */
7226 #define PWR_CR2_PLS_LEV6_Pos         (2U)
7227 #define PWR_CR2_PLS_LEV6_Msk         (0x3UL << PWR_CR2_PLS_LEV6_Pos)           /*!< 0x0000000C */
7228 #define PWR_CR2_PLS_LEV6             PWR_CR2_PLS_LEV6_Msk                      /*!< PVD level 6 */
7229 #define PWR_CR2_PLS_LEV7_Pos         (1U)
7230 #define PWR_CR2_PLS_LEV7_Msk         (0x7UL << PWR_CR2_PLS_LEV7_Pos)           /*!< 0x0000000E */
7231 #define PWR_CR2_PLS_LEV7             PWR_CR2_PLS_LEV7_Msk                      /*!< PVD level 7 */
7232 #define PWR_CR2_PVDE_Pos             (0U)
7233 #define PWR_CR2_PVDE_Msk             (0x1UL << PWR_CR2_PVDE_Pos)               /*!< 0x00000001 */
7234 #define PWR_CR2_PVDE                 PWR_CR2_PVDE_Msk                          /*!< Power Voltage Detector Enable */
7235 
7236 /********************  Bit definition for PWR_CR3 register  ********************/
7237 #define PWR_CR3_EIWF_Pos             (15U)
7238 #define PWR_CR3_EIWF_Msk             (0x1UL << PWR_CR3_EIWF_Pos)               /*!< 0x00008000 */
7239 #define PWR_CR3_EIWF                 PWR_CR3_EIWF_Msk                          /*!< Enable Internal Wake-up line */
7240 #define PWR_CR3_UCPD_DBDIS_Pos       (14U)
7241 #define PWR_CR3_UCPD_DBDIS_Msk       (0x1UL << PWR_CR3_UCPD_DBDIS_Pos)         /*!< 0x00004000 */
7242 #define PWR_CR3_UCPD_DBDIS           PWR_CR3_UCPD_DBDIS_Msk                    /*!< USB Type-C and Power Delivery Dead Battery disable. */
7243 #define PWR_CR3_UCPD_STDBY_Pos       (13U)
7244 #define PWR_CR3_UCPD_STDBY_Msk       (0x1UL << PWR_CR3_UCPD_STDBY_Pos)         /*!< 0x00002000 */
7245 #define PWR_CR3_UCPD_STDBY           PWR_CR3_UCPD_STDBY_Msk                    /*!< USB Type-C and Power Delivery standby mode. */
7246 #define PWR_CR3_APC_Pos              (10U)
7247 #define PWR_CR3_APC_Msk              (0x1UL << PWR_CR3_APC_Pos)                /*!< 0x00000400 */
7248 #define PWR_CR3_APC                  PWR_CR3_APC_Msk                           /*!< Apply pull-up and pull-down configuration */
7249 #define PWR_CR3_RRS_Pos              (8U)
7250 #define PWR_CR3_RRS_Msk              (0x1UL << PWR_CR3_RRS_Pos)                /*!< 0x00000100 */
7251 #define PWR_CR3_RRS                  PWR_CR3_RRS_Msk                           /*!< SRAM2 Retention in Stand-by mode */
7252 #define PWR_CR3_EWUP5_Pos            (4U)
7253 #define PWR_CR3_EWUP5_Msk            (0x1UL << PWR_CR3_EWUP5_Pos)              /*!< 0x00000010 */
7254 #define PWR_CR3_EWUP5                PWR_CR3_EWUP5_Msk                         /*!< Enable Wake-Up Pin 5 */
7255 #define PWR_CR3_EWUP4_Pos            (3U)
7256 #define PWR_CR3_EWUP4_Msk            (0x1UL << PWR_CR3_EWUP4_Pos)              /*!< 0x00000008 */
7257 #define PWR_CR3_EWUP4                PWR_CR3_EWUP4_Msk                         /*!< Enable Wake-Up Pin 4 */
7258 #define PWR_CR3_EWUP3_Pos            (2U)
7259 #define PWR_CR3_EWUP3_Msk            (0x1UL << PWR_CR3_EWUP3_Pos)              /*!< 0x00000004 */
7260 #define PWR_CR3_EWUP3                PWR_CR3_EWUP3_Msk                         /*!< Enable Wake-Up Pin 3 */
7261 #define PWR_CR3_EWUP2_Pos            (1U)
7262 #define PWR_CR3_EWUP2_Msk            (0x1UL << PWR_CR3_EWUP2_Pos)              /*!< 0x00000002 */
7263 #define PWR_CR3_EWUP2                PWR_CR3_EWUP2_Msk                         /*!< Enable Wake-Up Pin 2 */
7264 #define PWR_CR3_EWUP1_Pos            (0U)
7265 #define PWR_CR3_EWUP1_Msk            (0x1UL << PWR_CR3_EWUP1_Pos)              /*!< 0x00000001 */
7266 #define PWR_CR3_EWUP1                PWR_CR3_EWUP1_Msk                         /*!< Enable Wake-Up Pin 1 */
7267 #define PWR_CR3_EWUP_Pos             (0U)
7268 #define PWR_CR3_EWUP_Msk             (0x1FUL << PWR_CR3_EWUP_Pos)              /*!< 0x0000001F */
7269 #define PWR_CR3_EWUP                 PWR_CR3_EWUP_Msk                          /*!< Enable Wake-Up Pins  */
7270 
7271 /********************  Bit definition for PWR_CR4 register  ********************/
7272 #define PWR_CR4_VBRS_Pos             (9U)
7273 #define PWR_CR4_VBRS_Msk             (0x1UL << PWR_CR4_VBRS_Pos)               /*!< 0x00000200 */
7274 #define PWR_CR4_VBRS                 PWR_CR4_VBRS_Msk                          /*!< VBAT Battery charging Resistor Selection */
7275 #define PWR_CR4_VBE_Pos              (8U)
7276 #define PWR_CR4_VBE_Msk              (0x1UL << PWR_CR4_VBE_Pos)                /*!< 0x00000100 */
7277 #define PWR_CR4_VBE                  PWR_CR4_VBE_Msk                           /*!< VBAT Battery charging Enable  */
7278 #define PWR_CR4_WP5_Pos              (4U)
7279 #define PWR_CR4_WP5_Msk              (0x1UL << PWR_CR4_WP5_Pos)                /*!< 0x00000010 */
7280 #define PWR_CR4_WP5                  PWR_CR4_WP5_Msk                           /*!< Wake-Up Pin 5 polarity */
7281 #define PWR_CR4_WP4_Pos              (3U)
7282 #define PWR_CR4_WP4_Msk              (0x1UL << PWR_CR4_WP4_Pos)                /*!< 0x00000008 */
7283 #define PWR_CR4_WP4                  PWR_CR4_WP4_Msk                           /*!< Wake-Up Pin 4 polarity */
7284 #define PWR_CR4_WP3_Pos              (2U)
7285 #define PWR_CR4_WP3_Msk              (0x1UL << PWR_CR4_WP3_Pos)                /*!< 0x00000004 */
7286 #define PWR_CR4_WP3                  PWR_CR4_WP3_Msk                           /*!< Wake-Up Pin 3 polarity */
7287 #define PWR_CR4_WP2_Pos              (1U)
7288 #define PWR_CR4_WP2_Msk              (0x1UL << PWR_CR4_WP2_Pos)                /*!< 0x00000002 */
7289 #define PWR_CR4_WP2                  PWR_CR4_WP2_Msk                           /*!< Wake-Up Pin 2 polarity */
7290 #define PWR_CR4_WP1_Pos              (0U)
7291 #define PWR_CR4_WP1_Msk              (0x1UL << PWR_CR4_WP1_Pos)                /*!< 0x00000001 */
7292 #define PWR_CR4_WP1                  PWR_CR4_WP1_Msk                           /*!< Wake-Up Pin 1 polarity */
7293 
7294 /********************  Bit definition for PWR_SR1 register  ********************/
7295 #define PWR_SR1_WUFI_Pos             (15U)
7296 #define PWR_SR1_WUFI_Msk             (0x1UL << PWR_SR1_WUFI_Pos)               /*!< 0x00008000 */
7297 #define PWR_SR1_WUFI                 PWR_SR1_WUFI_Msk                          /*!< Wake-Up Flag Internal */
7298 #define PWR_SR1_SBF_Pos              (8U)
7299 #define PWR_SR1_SBF_Msk              (0x1UL << PWR_SR1_SBF_Pos)                /*!< 0x00000100 */
7300 #define PWR_SR1_SBF                  PWR_SR1_SBF_Msk                           /*!< Stand-By Flag */
7301 #define PWR_SR1_WUF_Pos              (0U)
7302 #define PWR_SR1_WUF_Msk              (0x1FUL << PWR_SR1_WUF_Pos)               /*!< 0x0000001F */
7303 #define PWR_SR1_WUF                  PWR_SR1_WUF_Msk                           /*!< Wake-up Flags */
7304 #define PWR_SR1_WUF5_Pos             (4U)
7305 #define PWR_SR1_WUF5_Msk             (0x1UL << PWR_SR1_WUF5_Pos)               /*!< 0x00000010 */
7306 #define PWR_SR1_WUF5                 PWR_SR1_WUF5_Msk                          /*!< Wake-up Flag 5 */
7307 #define PWR_SR1_WUF4_Pos             (3U)
7308 #define PWR_SR1_WUF4_Msk             (0x1UL << PWR_SR1_WUF4_Pos)               /*!< 0x00000008 */
7309 #define PWR_SR1_WUF4                 PWR_SR1_WUF4_Msk                          /*!< Wake-up Flag 4 */
7310 #define PWR_SR1_WUF3_Pos             (2U)
7311 #define PWR_SR1_WUF3_Msk             (0x1UL << PWR_SR1_WUF3_Pos)               /*!< 0x00000004 */
7312 #define PWR_SR1_WUF3                 PWR_SR1_WUF3_Msk                          /*!< Wake-up Flag 3 */
7313 #define PWR_SR1_WUF2_Pos             (1U)
7314 #define PWR_SR1_WUF2_Msk             (0x1UL << PWR_SR1_WUF2_Pos)               /*!< 0x00000002 */
7315 #define PWR_SR1_WUF2                 PWR_SR1_WUF2_Msk                          /*!< Wake-up Flag 2 */
7316 #define PWR_SR1_WUF1_Pos             (0U)
7317 #define PWR_SR1_WUF1_Msk             (0x1UL << PWR_SR1_WUF1_Pos)               /*!< 0x00000001 */
7318 #define PWR_SR1_WUF1                 PWR_SR1_WUF1_Msk                          /*!< Wake-up Flag 1 */
7319 
7320 /********************  Bit definition for PWR_SR2 register  ********************/
7321 #define PWR_SR2_PVMO4_Pos            (15U)
7322 #define PWR_SR2_PVMO4_Msk            (0x1UL << PWR_SR2_PVMO4_Pos)              /*!< 0x00008000 */
7323 #define PWR_SR2_PVMO4                PWR_SR2_PVMO4_Msk                         /*!< Peripheral Voltage Monitoring Output 4 */
7324 #define PWR_SR2_PVMO3_Pos            (14U)
7325 #define PWR_SR2_PVMO3_Msk            (0x1UL << PWR_SR2_PVMO3_Pos)              /*!< 0x00004000 */
7326 #define PWR_SR2_PVMO3                PWR_SR2_PVMO3_Msk                         /*!< Peripheral Voltage Monitoring Output 3 */
7327 #define PWR_SR2_PVMO2_Pos            (13U)
7328 #define PWR_SR2_PVMO2_Msk            (0x1UL << PWR_SR2_PVMO2_Pos)              /*!< 0x00002000 */
7329 #define PWR_SR2_PVMO2                PWR_SR2_PVMO2_Msk                         /*!< Peripheral Voltage Monitoring Output 2 */
7330 #define PWR_SR2_PVMO1_Pos            (12U)
7331 #define PWR_SR2_PVMO1_Msk            (0x1UL << PWR_SR2_PVMO1_Pos)              /*!< 0x00001000 */
7332 #define PWR_SR2_PVMO1                PWR_SR2_PVMO1_Msk                         /*!< Peripheral Voltage Monitoring Output 1 */
7333 #define PWR_SR2_PVDO_Pos             (11U)
7334 #define PWR_SR2_PVDO_Msk             (0x1UL << PWR_SR2_PVDO_Pos)               /*!< 0x00000800 */
7335 #define PWR_SR2_PVDO                 PWR_SR2_PVDO_Msk                          /*!< Power Voltage Detector Output */
7336 #define PWR_SR2_VOSF_Pos             (10U)
7337 #define PWR_SR2_VOSF_Msk             (0x1UL << PWR_SR2_VOSF_Pos)               /*!< 0x00000400 */
7338 #define PWR_SR2_VOSF                 PWR_SR2_VOSF_Msk                          /*!< Voltage Scaling Flag */
7339 #define PWR_SR2_REGLPF_Pos           (9U)
7340 #define PWR_SR2_REGLPF_Msk           (0x1UL << PWR_SR2_REGLPF_Pos)             /*!< 0x00000200 */
7341 #define PWR_SR2_REGLPF               PWR_SR2_REGLPF_Msk                        /*!< Low-power Regulator Flag */
7342 #define PWR_SR2_REGLPS_Pos           (8U)
7343 #define PWR_SR2_REGLPS_Msk           (0x1UL << PWR_SR2_REGLPS_Pos)             /*!< 0x00000100 */
7344 #define PWR_SR2_REGLPS               PWR_SR2_REGLPS_Msk                        /*!< Low-power Regulator Started */
7345 
7346 /********************  Bit definition for PWR_SCR register  ********************/
7347 #define PWR_SCR_CSBF_Pos             (8U)
7348 #define PWR_SCR_CSBF_Msk             (0x1UL << PWR_SCR_CSBF_Pos)               /*!< 0x00000100 */
7349 #define PWR_SCR_CSBF                 PWR_SCR_CSBF_Msk                          /*!< Clear Stand-By Flag */
7350 #define PWR_SCR_CWUF_Pos             (0U)
7351 #define PWR_SCR_CWUF_Msk             (0x1FUL << PWR_SCR_CWUF_Pos)              /*!< 0x0000001F */
7352 #define PWR_SCR_CWUF                 PWR_SCR_CWUF_Msk                          /*!< Clear Wake-up Flags  */
7353 #define PWR_SCR_CWUF5_Pos            (4U)
7354 #define PWR_SCR_CWUF5_Msk            (0x1UL << PWR_SCR_CWUF5_Pos)              /*!< 0x00000010 */
7355 #define PWR_SCR_CWUF5                PWR_SCR_CWUF5_Msk                         /*!< Clear Wake-up Flag 5 */
7356 #define PWR_SCR_CWUF4_Pos            (3U)
7357 #define PWR_SCR_CWUF4_Msk            (0x1UL << PWR_SCR_CWUF4_Pos)              /*!< 0x00000008 */
7358 #define PWR_SCR_CWUF4                PWR_SCR_CWUF4_Msk                         /*!< Clear Wake-up Flag 4 */
7359 #define PWR_SCR_CWUF3_Pos            (2U)
7360 #define PWR_SCR_CWUF3_Msk            (0x1UL << PWR_SCR_CWUF3_Pos)              /*!< 0x00000004 */
7361 #define PWR_SCR_CWUF3                PWR_SCR_CWUF3_Msk                         /*!< Clear Wake-up Flag 3 */
7362 #define PWR_SCR_CWUF2_Pos            (1U)
7363 #define PWR_SCR_CWUF2_Msk            (0x1UL << PWR_SCR_CWUF2_Pos)              /*!< 0x00000002 */
7364 #define PWR_SCR_CWUF2                PWR_SCR_CWUF2_Msk                         /*!< Clear Wake-up Flag 2 */
7365 #define PWR_SCR_CWUF1_Pos            (0U)
7366 #define PWR_SCR_CWUF1_Msk            (0x1UL << PWR_SCR_CWUF1_Pos)              /*!< 0x00000001 */
7367 #define PWR_SCR_CWUF1                PWR_SCR_CWUF1_Msk                         /*!< Clear Wake-up Flag 1 */
7368 
7369 /********************  Bit definition for PWR_PUCRA register  ********************/
7370 #define PWR_PUCRA_PA15_Pos           (15U)
7371 #define PWR_PUCRA_PA15_Msk           (0x1UL << PWR_PUCRA_PA15_Pos)             /*!< 0x00008000 */
7372 #define PWR_PUCRA_PA15               PWR_PUCRA_PA15_Msk                        /*!< Port PA15 Pull-Up set */
7373 #define PWR_PUCRA_PA13_Pos           (13U)
7374 #define PWR_PUCRA_PA13_Msk           (0x1UL << PWR_PUCRA_PA13_Pos)             /*!< 0x00002000 */
7375 #define PWR_PUCRA_PA13               PWR_PUCRA_PA13_Msk                        /*!< Port PA13 Pull-Up set */
7376 #define PWR_PUCRA_PA12_Pos           (12U)
7377 #define PWR_PUCRA_PA12_Msk           (0x1UL << PWR_PUCRA_PA12_Pos)             /*!< 0x00001000 */
7378 #define PWR_PUCRA_PA12               PWR_PUCRA_PA12_Msk                        /*!< Port PA12 Pull-Up set */
7379 #define PWR_PUCRA_PA11_Pos           (11U)
7380 #define PWR_PUCRA_PA11_Msk           (0x1UL << PWR_PUCRA_PA11_Pos)             /*!< 0x00000800 */
7381 #define PWR_PUCRA_PA11               PWR_PUCRA_PA11_Msk                        /*!< Port PA11 Pull-Up set */
7382 #define PWR_PUCRA_PA10_Pos           (10U)
7383 #define PWR_PUCRA_PA10_Msk           (0x1UL << PWR_PUCRA_PA10_Pos)             /*!< 0x00000400 */
7384 #define PWR_PUCRA_PA10               PWR_PUCRA_PA10_Msk                        /*!< Port PA10 Pull-Up set */
7385 #define PWR_PUCRA_PA9_Pos            (9U)
7386 #define PWR_PUCRA_PA9_Msk            (0x1UL << PWR_PUCRA_PA9_Pos)              /*!< 0x00000200 */
7387 #define PWR_PUCRA_PA9                PWR_PUCRA_PA9_Msk                         /*!< Port PA9 Pull-Up set  */
7388 #define PWR_PUCRA_PA8_Pos            (8U)
7389 #define PWR_PUCRA_PA8_Msk            (0x1UL << PWR_PUCRA_PA8_Pos)              /*!< 0x00000100 */
7390 #define PWR_PUCRA_PA8                PWR_PUCRA_PA8_Msk                         /*!< Port PA8 Pull-Up set  */
7391 #define PWR_PUCRA_PA7_Pos            (7U)
7392 #define PWR_PUCRA_PA7_Msk            (0x1UL << PWR_PUCRA_PA7_Pos)              /*!< 0x00000080 */
7393 #define PWR_PUCRA_PA7                PWR_PUCRA_PA7_Msk                         /*!< Port PA7 Pull-Up set  */
7394 #define PWR_PUCRA_PA6_Pos            (6U)
7395 #define PWR_PUCRA_PA6_Msk            (0x1UL << PWR_PUCRA_PA6_Pos)              /*!< 0x00000040 */
7396 #define PWR_PUCRA_PA6                PWR_PUCRA_PA6_Msk                         /*!< Port PA6 Pull-Up set  */
7397 #define PWR_PUCRA_PA5_Pos            (5U)
7398 #define PWR_PUCRA_PA5_Msk            (0x1UL << PWR_PUCRA_PA5_Pos)              /*!< 0x00000020 */
7399 #define PWR_PUCRA_PA5                PWR_PUCRA_PA5_Msk                         /*!< Port PA5 Pull-Up set  */
7400 #define PWR_PUCRA_PA4_Pos            (4U)
7401 #define PWR_PUCRA_PA4_Msk            (0x1UL << PWR_PUCRA_PA4_Pos)              /*!< 0x00000010 */
7402 #define PWR_PUCRA_PA4                PWR_PUCRA_PA4_Msk                         /*!< Port PA4 Pull-Up set  */
7403 #define PWR_PUCRA_PA3_Pos            (3U)
7404 #define PWR_PUCRA_PA3_Msk            (0x1UL << PWR_PUCRA_PA3_Pos)              /*!< 0x00000008 */
7405 #define PWR_PUCRA_PA3                PWR_PUCRA_PA3_Msk                         /*!< Port PA3 Pull-Up set  */
7406 #define PWR_PUCRA_PA2_Pos            (2U)
7407 #define PWR_PUCRA_PA2_Msk            (0x1UL << PWR_PUCRA_PA2_Pos)              /*!< 0x00000004 */
7408 #define PWR_PUCRA_PA2                PWR_PUCRA_PA2_Msk                         /*!< Port PA2 Pull-Up set  */
7409 #define PWR_PUCRA_PA1_Pos            (1U)
7410 #define PWR_PUCRA_PA1_Msk            (0x1UL << PWR_PUCRA_PA1_Pos)              /*!< 0x00000002 */
7411 #define PWR_PUCRA_PA1                PWR_PUCRA_PA1_Msk                         /*!< Port PA1 Pull-Up set  */
7412 #define PWR_PUCRA_PA0_Pos            (0U)
7413 #define PWR_PUCRA_PA0_Msk            (0x1UL << PWR_PUCRA_PA0_Pos)              /*!< 0x00000001 */
7414 #define PWR_PUCRA_PA0                PWR_PUCRA_PA0_Msk                         /*!< Port PA0 Pull-Up set  */
7415 
7416 /********************  Bit definition for PWR_PDCRA register  ********************/
7417 #define PWR_PDCRA_PA14_Pos           (14U)
7418 #define PWR_PDCRA_PA14_Msk           (0x1UL << PWR_PDCRA_PA14_Pos)             /*!< 0x00004000 */
7419 #define PWR_PDCRA_PA14               PWR_PDCRA_PA14_Msk                        /*!< Port PA14 Pull-Down set */
7420 #define PWR_PDCRA_PA12_Pos           (12U)
7421 #define PWR_PDCRA_PA12_Msk           (0x1UL << PWR_PDCRA_PA12_Pos)             /*!< 0x00001000 */
7422 #define PWR_PDCRA_PA12               PWR_PDCRA_PA12_Msk                        /*!< Port PA12 Pull-Down set */
7423 #define PWR_PDCRA_PA11_Pos           (11U)
7424 #define PWR_PDCRA_PA11_Msk           (0x1UL << PWR_PDCRA_PA11_Pos)             /*!< 0x00000800 */
7425 #define PWR_PDCRA_PA11               PWR_PDCRA_PA11_Msk                        /*!< Port PA11 Pull-Down set */
7426 #define PWR_PDCRA_PA10_Pos           (10U)
7427 #define PWR_PDCRA_PA10_Msk           (0x1UL << PWR_PDCRA_PA10_Pos)             /*!< 0x00000400 */
7428 #define PWR_PDCRA_PA10               PWR_PDCRA_PA10_Msk                        /*!< Port PA10 Pull-Down set */
7429 #define PWR_PDCRA_PA9_Pos            (9U)
7430 #define PWR_PDCRA_PA9_Msk            (0x1UL << PWR_PDCRA_PA9_Pos)              /*!< 0x00000200 */
7431 #define PWR_PDCRA_PA9                PWR_PDCRA_PA9_Msk                         /*!< Port PA9 Pull-Down set  */
7432 #define PWR_PDCRA_PA8_Pos            (8U)
7433 #define PWR_PDCRA_PA8_Msk            (0x1UL << PWR_PDCRA_PA8_Pos)              /*!< 0x00000100 */
7434 #define PWR_PDCRA_PA8                PWR_PDCRA_PA8_Msk                         /*!< Port PA8 Pull-Down set  */
7435 #define PWR_PDCRA_PA7_Pos            (7U)
7436 #define PWR_PDCRA_PA7_Msk            (0x1UL << PWR_PDCRA_PA7_Pos)              /*!< 0x00000080 */
7437 #define PWR_PDCRA_PA7                PWR_PDCRA_PA7_Msk                         /*!< Port PA7 Pull-Down set  */
7438 #define PWR_PDCRA_PA6_Pos            (6U)
7439 #define PWR_PDCRA_PA6_Msk            (0x1UL << PWR_PDCRA_PA6_Pos)              /*!< 0x00000040 */
7440 #define PWR_PDCRA_PA6                PWR_PDCRA_PA6_Msk                         /*!< Port PA6 Pull-Down set  */
7441 #define PWR_PDCRA_PA5_Pos            (5U)
7442 #define PWR_PDCRA_PA5_Msk            (0x1UL << PWR_PDCRA_PA5_Pos)              /*!< 0x00000020 */
7443 #define PWR_PDCRA_PA5                PWR_PDCRA_PA5_Msk                         /*!< Port PA5 Pull-Down set  */
7444 #define PWR_PDCRA_PA4_Pos            (4U)
7445 #define PWR_PDCRA_PA4_Msk            (0x1UL << PWR_PDCRA_PA4_Pos)              /*!< 0x00000010 */
7446 #define PWR_PDCRA_PA4                PWR_PDCRA_PA4_Msk                         /*!< Port PA4 Pull-Down set  */
7447 #define PWR_PDCRA_PA3_Pos            (3U)
7448 #define PWR_PDCRA_PA3_Msk            (0x1UL << PWR_PDCRA_PA3_Pos)              /*!< 0x00000008 */
7449 #define PWR_PDCRA_PA3                PWR_PDCRA_PA3_Msk                         /*!< Port PA3 Pull-Down set  */
7450 #define PWR_PDCRA_PA2_Pos            (2U)
7451 #define PWR_PDCRA_PA2_Msk            (0x1UL << PWR_PDCRA_PA2_Pos)              /*!< 0x00000004 */
7452 #define PWR_PDCRA_PA2                PWR_PDCRA_PA2_Msk                         /*!< Port PA2 Pull-Down set  */
7453 #define PWR_PDCRA_PA1_Pos            (1U)
7454 #define PWR_PDCRA_PA1_Msk            (0x1UL << PWR_PDCRA_PA1_Pos)              /*!< 0x00000002 */
7455 #define PWR_PDCRA_PA1                PWR_PDCRA_PA1_Msk                         /*!< Port PA1 Pull-Down set  */
7456 #define PWR_PDCRA_PA0_Pos            (0U)
7457 #define PWR_PDCRA_PA0_Msk            (0x1UL << PWR_PDCRA_PA0_Pos)              /*!< 0x00000001 */
7458 #define PWR_PDCRA_PA0                PWR_PDCRA_PA0_Msk                         /*!< Port PA0 Pull-Down set  */
7459 
7460 /********************  Bit definition for PWR_PUCRB register  ********************/
7461 
7462 #define PWR_PUCRB_PB15_Pos           (15U)
7463 #define PWR_PUCRB_PB15_Msk           (0x1UL << PWR_PUCRB_PB15_Pos)             /*!< 0x00008000 */
7464 #define PWR_PUCRB_PB15               PWR_PUCRB_PB15_Msk                        /*!< Port PB15 Pull-Up set */
7465 #define PWR_PUCRB_PB14_Pos           (14U)
7466 #define PWR_PUCRB_PB14_Msk           (0x1UL << PWR_PUCRB_PB14_Pos)             /*!< 0x00004000 */
7467 #define PWR_PUCRB_PB14               PWR_PUCRB_PB14_Msk                        /*!< Port PB14 Pull-Up set */
7468 #define PWR_PUCRB_PB13_Pos           (13U)
7469 #define PWR_PUCRB_PB13_Msk           (0x1UL << PWR_PUCRB_PB13_Pos)             /*!< 0x00002000 */
7470 #define PWR_PUCRB_PB13               PWR_PUCRB_PB13_Msk                        /*!< Port PB13 Pull-Up set */
7471 #define PWR_PUCRB_PB12_Pos           (12U)
7472 #define PWR_PUCRB_PB12_Msk           (0x1UL << PWR_PUCRB_PB12_Pos)             /*!< 0x00001000 */
7473 #define PWR_PUCRB_PB12               PWR_PUCRB_PB12_Msk                        /*!< Port PB12 Pull-Up set */
7474 #define PWR_PUCRB_PB11_Pos           (11U)
7475 #define PWR_PUCRB_PB11_Msk           (0x1UL << PWR_PUCRB_PB11_Pos)             /*!< 0x00000800 */
7476 #define PWR_PUCRB_PB11               PWR_PUCRB_PB11_Msk                        /*!< Port PB11 Pull-Up set */
7477 #define PWR_PUCRB_PB10_Pos           (10U)
7478 #define PWR_PUCRB_PB10_Msk           (0x1UL << PWR_PUCRB_PB10_Pos)             /*!< 0x00000400 */
7479 #define PWR_PUCRB_PB10               PWR_PUCRB_PB10_Msk                        /*!< Port PB10 Pull-Up set */
7480 #define PWR_PUCRB_PB9_Pos            (9U)
7481 #define PWR_PUCRB_PB9_Msk            (0x1UL << PWR_PUCRB_PB9_Pos)              /*!< 0x00000200 */
7482 #define PWR_PUCRB_PB9                PWR_PUCRB_PB9_Msk                         /*!< Port PB9 Pull-Up set  */
7483 #define PWR_PUCRB_PB8_Pos            (8U)
7484 #define PWR_PUCRB_PB8_Msk            (0x1UL << PWR_PUCRB_PB8_Pos)              /*!< 0x00000100 */
7485 #define PWR_PUCRB_PB8                PWR_PUCRB_PB8_Msk                         /*!< Port PB8 Pull-Up set  */
7486 #define PWR_PUCRB_PB7_Pos            (7U)
7487 #define PWR_PUCRB_PB7_Msk            (0x1UL << PWR_PUCRB_PB7_Pos)              /*!< 0x00000080 */
7488 #define PWR_PUCRB_PB7                PWR_PUCRB_PB7_Msk                         /*!< Port PB7 Pull-Up set  */
7489 #define PWR_PUCRB_PB6_Pos            (6U)
7490 #define PWR_PUCRB_PB6_Msk            (0x1UL << PWR_PUCRB_PB6_Pos)              /*!< 0x00000040 */
7491 #define PWR_PUCRB_PB6                PWR_PUCRB_PB6_Msk                         /*!< Port PB6 Pull-Up set  */
7492 #define PWR_PUCRB_PB5_Pos            (5U)
7493 #define PWR_PUCRB_PB5_Msk            (0x1UL << PWR_PUCRB_PB5_Pos)              /*!< 0x00000020 */
7494 #define PWR_PUCRB_PB5                PWR_PUCRB_PB5_Msk                         /*!< Port PB5 Pull-Up set  */
7495 #define PWR_PUCRB_PB4_Pos            (4U)
7496 #define PWR_PUCRB_PB4_Msk            (0x1UL << PWR_PUCRB_PB4_Pos)              /*!< 0x00000010 */
7497 #define PWR_PUCRB_PB4                PWR_PUCRB_PB4_Msk                         /*!< Port PB4 Pull-Up set  */
7498 #define PWR_PUCRB_PB3_Pos            (3U)
7499 #define PWR_PUCRB_PB3_Msk            (0x1UL << PWR_PUCRB_PB3_Pos)              /*!< 0x00000008 */
7500 #define PWR_PUCRB_PB3                PWR_PUCRB_PB3_Msk                         /*!< Port PB3 Pull-Up set  */
7501 #define PWR_PUCRB_PB2_Pos            (2U)
7502 #define PWR_PUCRB_PB2_Msk            (0x1UL << PWR_PUCRB_PB2_Pos)              /*!< 0x00000004 */
7503 #define PWR_PUCRB_PB2                PWR_PUCRB_PB2_Msk                         /*!< Port PB2 Pull-Up set  */
7504 #define PWR_PUCRB_PB1_Pos            (1U)
7505 #define PWR_PUCRB_PB1_Msk            (0x1UL << PWR_PUCRB_PB1_Pos)              /*!< 0x00000002 */
7506 #define PWR_PUCRB_PB1                PWR_PUCRB_PB1_Msk                         /*!< Port PB1 Pull-Up set  */
7507 #define PWR_PUCRB_PB0_Pos            (0U)
7508 #define PWR_PUCRB_PB0_Msk            (0x1UL << PWR_PUCRB_PB0_Pos)              /*!< 0x00000001 */
7509 #define PWR_PUCRB_PB0                PWR_PUCRB_PB0_Msk                         /*!< Port PB0 Pull-Up set  */
7510 
7511 /********************  Bit definition for PWR_PDCRB register  ********************/
7512 #define PWR_PDCRB_PB15_Pos           (15U)
7513 #define PWR_PDCRB_PB15_Msk           (0x1UL << PWR_PDCRB_PB15_Pos)             /*!< 0x00008000 */
7514 #define PWR_PDCRB_PB15               PWR_PDCRB_PB15_Msk                        /*!< Port PB15 Pull-Down set */
7515 #define PWR_PDCRB_PB14_Pos           (14U)
7516 #define PWR_PDCRB_PB14_Msk           (0x1UL << PWR_PDCRB_PB14_Pos)             /*!< 0x00004000 */
7517 #define PWR_PDCRB_PB14               PWR_PDCRB_PB14_Msk                        /*!< Port PB14 Pull-Down set */
7518 #define PWR_PDCRB_PB13_Pos           (13U)
7519 #define PWR_PDCRB_PB13_Msk           (0x1UL << PWR_PDCRB_PB13_Pos)             /*!< 0x00002000 */
7520 #define PWR_PDCRB_PB13               PWR_PDCRB_PB13_Msk                        /*!< Port PB13 Pull-Down set */
7521 #define PWR_PDCRB_PB12_Pos           (12U)
7522 #define PWR_PDCRB_PB12_Msk           (0x1UL << PWR_PDCRB_PB12_Pos)             /*!< 0x00001000 */
7523 #define PWR_PDCRB_PB12               PWR_PDCRB_PB12_Msk                        /*!< Port PB12 Pull-Down set */
7524 #define PWR_PDCRB_PB11_Pos           (11U)
7525 #define PWR_PDCRB_PB11_Msk           (0x1UL << PWR_PDCRB_PB11_Pos)             /*!< 0x00000800 */
7526 #define PWR_PDCRB_PB11               PWR_PDCRB_PB11_Msk                        /*!< Port PB11 Pull-Down set */
7527 #define PWR_PDCRB_PB10_Pos           (10U)
7528 #define PWR_PDCRB_PB10_Msk           (0x1UL << PWR_PDCRB_PB10_Pos)             /*!< 0x00000400 */
7529 #define PWR_PDCRB_PB10               PWR_PDCRB_PB10_Msk                        /*!< Port PB10 Pull-Down set */
7530 #define PWR_PDCRB_PB9_Pos            (9U)
7531 #define PWR_PDCRB_PB9_Msk            (0x1UL << PWR_PDCRB_PB9_Pos)              /*!< 0x00000200 */
7532 #define PWR_PDCRB_PB9                PWR_PDCRB_PB9_Msk                         /*!< Port PB9 Pull-Down set  */
7533 #define PWR_PDCRB_PB8_Pos            (8U)
7534 #define PWR_PDCRB_PB8_Msk            (0x1UL << PWR_PDCRB_PB8_Pos)              /*!< 0x00000100 */
7535 #define PWR_PDCRB_PB8                PWR_PDCRB_PB8_Msk                         /*!< Port PB8 Pull-Down set  */
7536 #define PWR_PDCRB_PB7_Pos            (7U)
7537 #define PWR_PDCRB_PB7_Msk            (0x1UL << PWR_PDCRB_PB7_Pos)              /*!< 0x00000080 */
7538 #define PWR_PDCRB_PB7                PWR_PDCRB_PB7_Msk                         /*!< Port PB7 Pull-Down set  */
7539 #define PWR_PDCRB_PB6_Pos            (6U)
7540 #define PWR_PDCRB_PB6_Msk            (0x1UL << PWR_PDCRB_PB6_Pos)              /*!< 0x00000040 */
7541 #define PWR_PDCRB_PB6                PWR_PDCRB_PB6_Msk                         /*!< Port PB6 Pull-Down set  */
7542 #define PWR_PDCRB_PB5_Pos            (5U)
7543 #define PWR_PDCRB_PB5_Msk            (0x1UL << PWR_PDCRB_PB5_Pos)              /*!< 0x00000020 */
7544 #define PWR_PDCRB_PB5                PWR_PDCRB_PB5_Msk                         /*!< Port PB5 Pull-Down set  */
7545 #define PWR_PDCRB_PB3_Pos            (3U)
7546 #define PWR_PDCRB_PB3_Msk            (0x1UL << PWR_PDCRB_PB3_Pos)              /*!< 0x00000008 */
7547 #define PWR_PDCRB_PB3                PWR_PDCRB_PB3_Msk                         /*!< Port PB3 Pull-Down set  */
7548 #define PWR_PDCRB_PB2_Pos            (2U)
7549 #define PWR_PDCRB_PB2_Msk            (0x1UL << PWR_PDCRB_PB2_Pos)              /*!< 0x00000004 */
7550 #define PWR_PDCRB_PB2                PWR_PDCRB_PB2_Msk                         /*!< Port PB2 Pull-Down set  */
7551 #define PWR_PDCRB_PB1_Pos            (1U)
7552 #define PWR_PDCRB_PB1_Msk            (0x1UL << PWR_PDCRB_PB1_Pos)              /*!< 0x00000002 */
7553 #define PWR_PDCRB_PB1                PWR_PDCRB_PB1_Msk                         /*!< Port PB1 Pull-Down set  */
7554 #define PWR_PDCRB_PB0_Pos            (0U)
7555 #define PWR_PDCRB_PB0_Msk            (0x1UL << PWR_PDCRB_PB0_Pos)              /*!< 0x00000001 */
7556 #define PWR_PDCRB_PB0                PWR_PDCRB_PB0_Msk                         /*!< Port PB0 Pull-Down set  */
7557 
7558 /********************  Bit definition for PWR_PUCRC register  ********************/
7559 #define PWR_PUCRC_PC15_Pos           (15U)
7560 #define PWR_PUCRC_PC15_Msk           (0x1UL << PWR_PUCRC_PC15_Pos)             /*!< 0x00008000 */
7561 #define PWR_PUCRC_PC15               PWR_PUCRC_PC15_Msk                        /*!< Port PC15 Pull-Up set */
7562 #define PWR_PUCRC_PC14_Pos           (14U)
7563 #define PWR_PUCRC_PC14_Msk           (0x1UL << PWR_PUCRC_PC14_Pos)             /*!< 0x00004000 */
7564 #define PWR_PUCRC_PC14               PWR_PUCRC_PC14_Msk                        /*!< Port PC14 Pull-Up set */
7565 #define PWR_PUCRC_PC13_Pos           (13U)
7566 #define PWR_PUCRC_PC13_Msk           (0x1UL << PWR_PUCRC_PC13_Pos)             /*!< 0x00002000 */
7567 #define PWR_PUCRC_PC13               PWR_PUCRC_PC13_Msk                        /*!< Port PC13 Pull-Up set */
7568 #define PWR_PUCRC_PC12_Pos           (12U)
7569 #define PWR_PUCRC_PC12_Msk           (0x1UL << PWR_PUCRC_PC12_Pos)             /*!< 0x00001000 */
7570 #define PWR_PUCRC_PC12               PWR_PUCRC_PC12_Msk                        /*!< Port PC12 Pull-Up set */
7571 #define PWR_PUCRC_PC11_Pos           (11U)
7572 #define PWR_PUCRC_PC11_Msk           (0x1UL << PWR_PUCRC_PC11_Pos)             /*!< 0x00000800 */
7573 #define PWR_PUCRC_PC11               PWR_PUCRC_PC11_Msk                        /*!< Port PC11 Pull-Up set */
7574 #define PWR_PUCRC_PC10_Pos           (10U)
7575 #define PWR_PUCRC_PC10_Msk           (0x1UL << PWR_PUCRC_PC10_Pos)             /*!< 0x00000400 */
7576 #define PWR_PUCRC_PC10               PWR_PUCRC_PC10_Msk                        /*!< Port PC10 Pull-Up set */
7577 #define PWR_PUCRC_PC9_Pos            (9U)
7578 #define PWR_PUCRC_PC9_Msk            (0x1UL << PWR_PUCRC_PC9_Pos)              /*!< 0x00000200 */
7579 #define PWR_PUCRC_PC9                PWR_PUCRC_PC9_Msk                         /*!< Port PC9 Pull-Up set  */
7580 #define PWR_PUCRC_PC8_Pos            (8U)
7581 #define PWR_PUCRC_PC8_Msk            (0x1UL << PWR_PUCRC_PC8_Pos)              /*!< 0x00000100 */
7582 #define PWR_PUCRC_PC8                PWR_PUCRC_PC8_Msk                         /*!< Port PC8 Pull-Up set  */
7583 #define PWR_PUCRC_PC7_Pos            (7U)
7584 #define PWR_PUCRC_PC7_Msk            (0x1UL << PWR_PUCRC_PC7_Pos)              /*!< 0x00000080 */
7585 #define PWR_PUCRC_PC7                PWR_PUCRC_PC7_Msk                         /*!< Port PC7 Pull-Up set  */
7586 #define PWR_PUCRC_PC6_Pos            (6U)
7587 #define PWR_PUCRC_PC6_Msk            (0x1UL << PWR_PUCRC_PC6_Pos)              /*!< 0x00000040 */
7588 #define PWR_PUCRC_PC6                PWR_PUCRC_PC6_Msk                         /*!< Port PC6 Pull-Up set  */
7589 #define PWR_PUCRC_PC5_Pos            (5U)
7590 #define PWR_PUCRC_PC5_Msk            (0x1UL << PWR_PUCRC_PC5_Pos)              /*!< 0x00000020 */
7591 #define PWR_PUCRC_PC5                PWR_PUCRC_PC5_Msk                         /*!< Port PC5 Pull-Up set  */
7592 #define PWR_PUCRC_PC4_Pos            (4U)
7593 #define PWR_PUCRC_PC4_Msk            (0x1UL << PWR_PUCRC_PC4_Pos)              /*!< 0x00000010 */
7594 #define PWR_PUCRC_PC4                PWR_PUCRC_PC4_Msk                         /*!< Port PC4 Pull-Up set  */
7595 #define PWR_PUCRC_PC3_Pos            (3U)
7596 #define PWR_PUCRC_PC3_Msk            (0x1UL << PWR_PUCRC_PC3_Pos)              /*!< 0x00000008 */
7597 #define PWR_PUCRC_PC3                PWR_PUCRC_PC3_Msk                         /*!< Port PC3 Pull-Up set  */
7598 #define PWR_PUCRC_PC2_Pos            (2U)
7599 #define PWR_PUCRC_PC2_Msk            (0x1UL << PWR_PUCRC_PC2_Pos)              /*!< 0x00000004 */
7600 #define PWR_PUCRC_PC2                PWR_PUCRC_PC2_Msk                         /*!< Port PC2 Pull-Up set  */
7601 #define PWR_PUCRC_PC1_Pos            (1U)
7602 #define PWR_PUCRC_PC1_Msk            (0x1UL << PWR_PUCRC_PC1_Pos)              /*!< 0x00000002 */
7603 #define PWR_PUCRC_PC1                PWR_PUCRC_PC1_Msk                         /*!< Port PC1 Pull-Up set  */
7604 #define PWR_PUCRC_PC0_Pos            (0U)
7605 #define PWR_PUCRC_PC0_Msk            (0x1UL << PWR_PUCRC_PC0_Pos)              /*!< 0x00000001 */
7606 #define PWR_PUCRC_PC0                PWR_PUCRC_PC0_Msk                         /*!< Port PC0 Pull-Up set  */
7607 
7608 /********************  Bit definition for PWR_PDCRC register  ********************/
7609 #define PWR_PDCRC_PC15_Pos           (15U)
7610 #define PWR_PDCRC_PC15_Msk           (0x1UL << PWR_PDCRC_PC15_Pos)             /*!< 0x00008000 */
7611 #define PWR_PDCRC_PC15               PWR_PDCRC_PC15_Msk                        /*!< Port PC15 Pull-Down set */
7612 #define PWR_PDCRC_PC14_Pos           (14U)
7613 #define PWR_PDCRC_PC14_Msk           (0x1UL << PWR_PDCRC_PC14_Pos)             /*!< 0x00004000 */
7614 #define PWR_PDCRC_PC14               PWR_PDCRC_PC14_Msk                        /*!< Port PC14 Pull-Down set */
7615 #define PWR_PDCRC_PC13_Pos           (13U)
7616 #define PWR_PDCRC_PC13_Msk           (0x1UL << PWR_PDCRC_PC13_Pos)             /*!< 0x00002000 */
7617 #define PWR_PDCRC_PC13               PWR_PDCRC_PC13_Msk                        /*!< Port PC13 Pull-Down set */
7618 #define PWR_PDCRC_PC12_Pos           (12U)
7619 #define PWR_PDCRC_PC12_Msk           (0x1UL << PWR_PDCRC_PC12_Pos)             /*!< 0x00001000 */
7620 #define PWR_PDCRC_PC12               PWR_PDCRC_PC12_Msk                        /*!< Port PC12 Pull-Down set */
7621 #define PWR_PDCRC_PC11_Pos           (11U)
7622 #define PWR_PDCRC_PC11_Msk           (0x1UL << PWR_PDCRC_PC11_Pos)             /*!< 0x00000800 */
7623 #define PWR_PDCRC_PC11               PWR_PDCRC_PC11_Msk                        /*!< Port PC11 Pull-Down set */
7624 #define PWR_PDCRC_PC10_Pos           (10U)
7625 #define PWR_PDCRC_PC10_Msk           (0x1UL << PWR_PDCRC_PC10_Pos)             /*!< 0x00000400 */
7626 #define PWR_PDCRC_PC10               PWR_PDCRC_PC10_Msk                        /*!< Port PC10 Pull-Down set */
7627 #define PWR_PDCRC_PC9_Pos            (9U)
7628 #define PWR_PDCRC_PC9_Msk            (0x1UL << PWR_PDCRC_PC9_Pos)              /*!< 0x00000200 */
7629 #define PWR_PDCRC_PC9                PWR_PDCRC_PC9_Msk                         /*!< Port PC9 Pull-Down set  */
7630 #define PWR_PDCRC_PC8_Pos            (8U)
7631 #define PWR_PDCRC_PC8_Msk            (0x1UL << PWR_PDCRC_PC8_Pos)              /*!< 0x00000100 */
7632 #define PWR_PDCRC_PC8                PWR_PDCRC_PC8_Msk                         /*!< Port PC8 Pull-Down set  */
7633 #define PWR_PDCRC_PC7_Pos            (7U)
7634 #define PWR_PDCRC_PC7_Msk            (0x1UL << PWR_PDCRC_PC7_Pos)              /*!< 0x00000080 */
7635 #define PWR_PDCRC_PC7                PWR_PDCRC_PC7_Msk                         /*!< Port PC7 Pull-Down set  */
7636 #define PWR_PDCRC_PC6_Pos            (6U)
7637 #define PWR_PDCRC_PC6_Msk            (0x1UL << PWR_PDCRC_PC6_Pos)              /*!< 0x00000040 */
7638 #define PWR_PDCRC_PC6                PWR_PDCRC_PC6_Msk                         /*!< Port PC6 Pull-Down set  */
7639 #define PWR_PDCRC_PC5_Pos            (5U)
7640 #define PWR_PDCRC_PC5_Msk            (0x1UL << PWR_PDCRC_PC5_Pos)              /*!< 0x00000020 */
7641 #define PWR_PDCRC_PC5                PWR_PDCRC_PC5_Msk                         /*!< Port PC5 Pull-Down set  */
7642 #define PWR_PDCRC_PC4_Pos            (4U)
7643 #define PWR_PDCRC_PC4_Msk            (0x1UL << PWR_PDCRC_PC4_Pos)              /*!< 0x00000010 */
7644 #define PWR_PDCRC_PC4                PWR_PDCRC_PC4_Msk                         /*!< Port PC4 Pull-Down set  */
7645 #define PWR_PDCRC_PC3_Pos            (3U)
7646 #define PWR_PDCRC_PC3_Msk            (0x1UL << PWR_PDCRC_PC3_Pos)              /*!< 0x00000008 */
7647 #define PWR_PDCRC_PC3                PWR_PDCRC_PC3_Msk                         /*!< Port PC3 Pull-Down set  */
7648 #define PWR_PDCRC_PC2_Pos            (2U)
7649 #define PWR_PDCRC_PC2_Msk            (0x1UL << PWR_PDCRC_PC2_Pos)              /*!< 0x00000004 */
7650 #define PWR_PDCRC_PC2                PWR_PDCRC_PC2_Msk                         /*!< Port PC2 Pull-Down set  */
7651 #define PWR_PDCRC_PC1_Pos            (1U)
7652 #define PWR_PDCRC_PC1_Msk            (0x1UL << PWR_PDCRC_PC1_Pos)              /*!< 0x00000002 */
7653 #define PWR_PDCRC_PC1                PWR_PDCRC_PC1_Msk                         /*!< Port PC1 Pull-Down set  */
7654 #define PWR_PDCRC_PC0_Pos            (0U)
7655 #define PWR_PDCRC_PC0_Msk            (0x1UL << PWR_PDCRC_PC0_Pos)              /*!< 0x00000001 */
7656 #define PWR_PDCRC_PC0                PWR_PDCRC_PC0_Msk                         /*!< Port PC0 Pull-Down set  */
7657 
7658 /********************  Bit definition for PWR_PUCRD register  ********************/
7659 #define PWR_PUCRD_PD15_Pos           (15U)
7660 #define PWR_PUCRD_PD15_Msk           (0x1UL << PWR_PUCRD_PD15_Pos)             /*!< 0x00008000 */
7661 #define PWR_PUCRD_PD15               PWR_PUCRD_PD15_Msk                        /*!< Port PD15 Pull-Up set */
7662 #define PWR_PUCRD_PD14_Pos           (14U)
7663 #define PWR_PUCRD_PD14_Msk           (0x1UL << PWR_PUCRD_PD14_Pos)             /*!< 0x00004000 */
7664 #define PWR_PUCRD_PD14               PWR_PUCRD_PD14_Msk                        /*!< Port PD14 Pull-Up set */
7665 #define PWR_PUCRD_PD13_Pos           (13U)
7666 #define PWR_PUCRD_PD13_Msk           (0x1UL << PWR_PUCRD_PD13_Pos)             /*!< 0x00002000 */
7667 #define PWR_PUCRD_PD13               PWR_PUCRD_PD13_Msk                        /*!< Port PD13 Pull-Up set */
7668 #define PWR_PUCRD_PD12_Pos           (12U)
7669 #define PWR_PUCRD_PD12_Msk           (0x1UL << PWR_PUCRD_PD12_Pos)             /*!< 0x00001000 */
7670 #define PWR_PUCRD_PD12               PWR_PUCRD_PD12_Msk                        /*!< Port PD12 Pull-Up set */
7671 #define PWR_PUCRD_PD11_Pos           (11U)
7672 #define PWR_PUCRD_PD11_Msk           (0x1UL << PWR_PUCRD_PD11_Pos)             /*!< 0x00000800 */
7673 #define PWR_PUCRD_PD11               PWR_PUCRD_PD11_Msk                        /*!< Port PD11 Pull-Up set */
7674 #define PWR_PUCRD_PD10_Pos           (10U)
7675 #define PWR_PUCRD_PD10_Msk           (0x1UL << PWR_PUCRD_PD10_Pos)             /*!< 0x00000400 */
7676 #define PWR_PUCRD_PD10               PWR_PUCRD_PD10_Msk                        /*!< Port PD10 Pull-Up set */
7677 #define PWR_PUCRD_PD9_Pos            (9U)
7678 #define PWR_PUCRD_PD9_Msk            (0x1UL << PWR_PUCRD_PD9_Pos)              /*!< 0x00000200 */
7679 #define PWR_PUCRD_PD9                PWR_PUCRD_PD9_Msk                         /*!< Port PD9 Pull-Up set  */
7680 #define PWR_PUCRD_PD8_Pos            (8U)
7681 #define PWR_PUCRD_PD8_Msk            (0x1UL << PWR_PUCRD_PD8_Pos)              /*!< 0x00000100 */
7682 #define PWR_PUCRD_PD8                PWR_PUCRD_PD8_Msk                         /*!< Port PD8 Pull-Up set  */
7683 #define PWR_PUCRD_PD7_Pos            (7U)
7684 #define PWR_PUCRD_PD7_Msk            (0x1UL << PWR_PUCRD_PD7_Pos)              /*!< 0x00000080 */
7685 #define PWR_PUCRD_PD7                PWR_PUCRD_PD7_Msk                         /*!< Port PD7 Pull-Up set  */
7686 #define PWR_PUCRD_PD6_Pos            (6U)
7687 #define PWR_PUCRD_PD6_Msk            (0x1UL << PWR_PUCRD_PD6_Pos)              /*!< 0x00000040 */
7688 #define PWR_PUCRD_PD6                PWR_PUCRD_PD6_Msk                         /*!< Port PD6 Pull-Up set  */
7689 #define PWR_PUCRD_PD5_Pos            (5U)
7690 #define PWR_PUCRD_PD5_Msk            (0x1UL << PWR_PUCRD_PD5_Pos)              /*!< 0x00000020 */
7691 #define PWR_PUCRD_PD5                PWR_PUCRD_PD5_Msk                         /*!< Port PD5 Pull-Up set  */
7692 #define PWR_PUCRD_PD4_Pos            (4U)
7693 #define PWR_PUCRD_PD4_Msk            (0x1UL << PWR_PUCRD_PD4_Pos)              /*!< 0x00000010 */
7694 #define PWR_PUCRD_PD4                PWR_PUCRD_PD4_Msk                         /*!< Port PD4 Pull-Up set  */
7695 #define PWR_PUCRD_PD3_Pos            (3U)
7696 #define PWR_PUCRD_PD3_Msk            (0x1UL << PWR_PUCRD_PD3_Pos)              /*!< 0x00000008 */
7697 #define PWR_PUCRD_PD3                PWR_PUCRD_PD3_Msk                         /*!< Port PD3 Pull-Up set  */
7698 #define PWR_PUCRD_PD2_Pos            (2U)
7699 #define PWR_PUCRD_PD2_Msk            (0x1UL << PWR_PUCRD_PD2_Pos)              /*!< 0x00000004 */
7700 #define PWR_PUCRD_PD2                PWR_PUCRD_PD2_Msk                         /*!< Port PD2 Pull-Up set  */
7701 #define PWR_PUCRD_PD1_Pos            (1U)
7702 #define PWR_PUCRD_PD1_Msk            (0x1UL << PWR_PUCRD_PD1_Pos)              /*!< 0x00000002 */
7703 #define PWR_PUCRD_PD1                PWR_PUCRD_PD1_Msk                         /*!< Port PD1 Pull-Up set  */
7704 #define PWR_PUCRD_PD0_Pos            (0U)
7705 #define PWR_PUCRD_PD0_Msk            (0x1UL << PWR_PUCRD_PD0_Pos)              /*!< 0x00000001 */
7706 #define PWR_PUCRD_PD0                PWR_PUCRD_PD0_Msk                         /*!< Port PD0 Pull-Up set  */
7707 
7708 /********************  Bit definition for PWR_PDCRD register  ********************/
7709 #define PWR_PDCRD_PD15_Pos           (15U)
7710 #define PWR_PDCRD_PD15_Msk           (0x1UL << PWR_PDCRD_PD15_Pos)             /*!< 0x00008000 */
7711 #define PWR_PDCRD_PD15               PWR_PDCRD_PD15_Msk                        /*!< Port PD15 Pull-Down set */
7712 #define PWR_PDCRD_PD14_Pos           (14U)
7713 #define PWR_PDCRD_PD14_Msk           (0x1UL << PWR_PDCRD_PD14_Pos)             /*!< 0x00004000 */
7714 #define PWR_PDCRD_PD14               PWR_PDCRD_PD14_Msk                        /*!< Port PD14 Pull-Down set */
7715 #define PWR_PDCRD_PD13_Pos           (13U)
7716 #define PWR_PDCRD_PD13_Msk           (0x1UL << PWR_PDCRD_PD13_Pos)             /*!< 0x00002000 */
7717 #define PWR_PDCRD_PD13               PWR_PDCRD_PD13_Msk                        /*!< Port PD13 Pull-Down set */
7718 #define PWR_PDCRD_PD12_Pos           (12U)
7719 #define PWR_PDCRD_PD12_Msk           (0x1UL << PWR_PDCRD_PD12_Pos)             /*!< 0x00001000 */
7720 #define PWR_PDCRD_PD12               PWR_PDCRD_PD12_Msk                        /*!< Port PD12 Pull-Down set */
7721 #define PWR_PDCRD_PD11_Pos           (11U)
7722 #define PWR_PDCRD_PD11_Msk           (0x1UL << PWR_PDCRD_PD11_Pos)             /*!< 0x00000800 */
7723 #define PWR_PDCRD_PD11               PWR_PDCRD_PD11_Msk                        /*!< Port PD11 Pull-Down set */
7724 #define PWR_PDCRD_PD10_Pos           (10U)
7725 #define PWR_PDCRD_PD10_Msk           (0x1UL << PWR_PDCRD_PD10_Pos)             /*!< 0x00000400 */
7726 #define PWR_PDCRD_PD10               PWR_PDCRD_PD10_Msk                        /*!< Port PD10 Pull-Down set */
7727 #define PWR_PDCRD_PD9_Pos            (9U)
7728 #define PWR_PDCRD_PD9_Msk            (0x1UL << PWR_PDCRD_PD9_Pos)              /*!< 0x00000200 */
7729 #define PWR_PDCRD_PD9                PWR_PDCRD_PD9_Msk                         /*!< Port PD9 Pull-Down set  */
7730 #define PWR_PDCRD_PD8_Pos            (8U)
7731 #define PWR_PDCRD_PD8_Msk            (0x1UL << PWR_PDCRD_PD8_Pos)              /*!< 0x00000100 */
7732 #define PWR_PDCRD_PD8                PWR_PDCRD_PD8_Msk                         /*!< Port PD8 Pull-Down set  */
7733 #define PWR_PDCRD_PD7_Pos            (7U)
7734 #define PWR_PDCRD_PD7_Msk            (0x1UL << PWR_PDCRD_PD7_Pos)              /*!< 0x00000080 */
7735 #define PWR_PDCRD_PD7                PWR_PDCRD_PD7_Msk                         /*!< Port PD7 Pull-Down set  */
7736 #define PWR_PDCRD_PD6_Pos            (6U)
7737 #define PWR_PDCRD_PD6_Msk            (0x1UL << PWR_PDCRD_PD6_Pos)              /*!< 0x00000040 */
7738 #define PWR_PDCRD_PD6                PWR_PDCRD_PD6_Msk                         /*!< Port PD6 Pull-Down set  */
7739 #define PWR_PDCRD_PD5_Pos            (5U)
7740 #define PWR_PDCRD_PD5_Msk            (0x1UL << PWR_PDCRD_PD5_Pos)              /*!< 0x00000020 */
7741 #define PWR_PDCRD_PD5                PWR_PDCRD_PD5_Msk                         /*!< Port PD5 Pull-Down set  */
7742 #define PWR_PDCRD_PD4_Pos            (4U)
7743 #define PWR_PDCRD_PD4_Msk            (0x1UL << PWR_PDCRD_PD4_Pos)              /*!< 0x00000010 */
7744 #define PWR_PDCRD_PD4                PWR_PDCRD_PD4_Msk                         /*!< Port PD4 Pull-Down set  */
7745 #define PWR_PDCRD_PD3_Pos            (3U)
7746 #define PWR_PDCRD_PD3_Msk            (0x1UL << PWR_PDCRD_PD3_Pos)              /*!< 0x00000008 */
7747 #define PWR_PDCRD_PD3                PWR_PDCRD_PD3_Msk                         /*!< Port PD3 Pull-Down set  */
7748 #define PWR_PDCRD_PD2_Pos            (2U)
7749 #define PWR_PDCRD_PD2_Msk            (0x1UL << PWR_PDCRD_PD2_Pos)              /*!< 0x00000004 */
7750 #define PWR_PDCRD_PD2                PWR_PDCRD_PD2_Msk                         /*!< Port PD2 Pull-Down set  */
7751 #define PWR_PDCRD_PD1_Pos            (1U)
7752 #define PWR_PDCRD_PD1_Msk            (0x1UL << PWR_PDCRD_PD1_Pos)              /*!< 0x00000002 */
7753 #define PWR_PDCRD_PD1                PWR_PDCRD_PD1_Msk                         /*!< Port PD1 Pull-Down set  */
7754 #define PWR_PDCRD_PD0_Pos            (0U)
7755 #define PWR_PDCRD_PD0_Msk            (0x1UL << PWR_PDCRD_PD0_Pos)              /*!< 0x00000001 */
7756 #define PWR_PDCRD_PD0                PWR_PDCRD_PD0_Msk                         /*!< Port PD0 Pull-Down set  */
7757 
7758 /********************  Bit definition for PWR_PUCRE register  ********************/
7759 #define PWR_PUCRE_PE15_Pos           (15U)
7760 #define PWR_PUCRE_PE15_Msk           (0x1UL << PWR_PUCRE_PE15_Pos)             /*!< 0x00008000 */
7761 #define PWR_PUCRE_PE15               PWR_PUCRE_PE15_Msk                        /*!< Port PE15 Pull-Up set */
7762 #define PWR_PUCRE_PE14_Pos           (14U)
7763 #define PWR_PUCRE_PE14_Msk           (0x1UL << PWR_PUCRE_PE14_Pos)             /*!< 0x00004000 */
7764 #define PWR_PUCRE_PE14               PWR_PUCRE_PE14_Msk                        /*!< Port PE14 Pull-Up set */
7765 #define PWR_PUCRE_PE13_Pos           (13U)
7766 #define PWR_PUCRE_PE13_Msk           (0x1UL << PWR_PUCRE_PE13_Pos)             /*!< 0x00002000 */
7767 #define PWR_PUCRE_PE13               PWR_PUCRE_PE13_Msk                        /*!< Port PE13 Pull-Up set */
7768 #define PWR_PUCRE_PE12_Pos           (12U)
7769 #define PWR_PUCRE_PE12_Msk           (0x1UL << PWR_PUCRE_PE12_Pos)             /*!< 0x00001000 */
7770 #define PWR_PUCRE_PE12               PWR_PUCRE_PE12_Msk                        /*!< Port PE12 Pull-Up set */
7771 #define PWR_PUCRE_PE11_Pos           (11U)
7772 #define PWR_PUCRE_PE11_Msk           (0x1UL << PWR_PUCRE_PE11_Pos)             /*!< 0x00000800 */
7773 #define PWR_PUCRE_PE11               PWR_PUCRE_PE11_Msk                        /*!< Port PE11 Pull-Up set */
7774 #define PWR_PUCRE_PE10_Pos           (10U)
7775 #define PWR_PUCRE_PE10_Msk           (0x1UL << PWR_PUCRE_PE10_Pos)             /*!< 0x00000400 */
7776 #define PWR_PUCRE_PE10               PWR_PUCRE_PE10_Msk                        /*!< Port PE10 Pull-Up set */
7777 #define PWR_PUCRE_PE9_Pos            (9U)
7778 #define PWR_PUCRE_PE9_Msk            (0x1UL << PWR_PUCRE_PE9_Pos)              /*!< 0x00000200 */
7779 #define PWR_PUCRE_PE9                PWR_PUCRE_PE9_Msk                         /*!< Port PE9 Pull-Up set  */
7780 #define PWR_PUCRE_PE8_Pos            (8U)
7781 #define PWR_PUCRE_PE8_Msk            (0x1UL << PWR_PUCRE_PE8_Pos)              /*!< 0x00000100 */
7782 #define PWR_PUCRE_PE8                PWR_PUCRE_PE8_Msk                         /*!< Port PE8 Pull-Up set  */
7783 #define PWR_PUCRE_PE7_Pos            (7U)
7784 #define PWR_PUCRE_PE7_Msk            (0x1UL << PWR_PUCRE_PE7_Pos)              /*!< 0x00000080 */
7785 #define PWR_PUCRE_PE7                PWR_PUCRE_PE7_Msk                         /*!< Port PE7 Pull-Up set  */
7786 #define PWR_PUCRE_PE6_Pos            (6U)
7787 #define PWR_PUCRE_PE6_Msk            (0x1UL << PWR_PUCRE_PE6_Pos)              /*!< 0x00000040 */
7788 #define PWR_PUCRE_PE6                PWR_PUCRE_PE6_Msk                         /*!< Port PE6 Pull-Up set  */
7789 #define PWR_PUCRE_PE5_Pos            (5U)
7790 #define PWR_PUCRE_PE5_Msk            (0x1UL << PWR_PUCRE_PE5_Pos)              /*!< 0x00000020 */
7791 #define PWR_PUCRE_PE5                PWR_PUCRE_PE5_Msk                         /*!< Port PE5 Pull-Up set  */
7792 #define PWR_PUCRE_PE4_Pos            (4U)
7793 #define PWR_PUCRE_PE4_Msk            (0x1UL << PWR_PUCRE_PE4_Pos)              /*!< 0x00000010 */
7794 #define PWR_PUCRE_PE4                PWR_PUCRE_PE4_Msk                         /*!< Port PE4 Pull-Up set  */
7795 #define PWR_PUCRE_PE3_Pos            (3U)
7796 #define PWR_PUCRE_PE3_Msk            (0x1UL << PWR_PUCRE_PE3_Pos)              /*!< 0x00000008 */
7797 #define PWR_PUCRE_PE3                PWR_PUCRE_PE3_Msk                         /*!< Port PE3 Pull-Up set  */
7798 #define PWR_PUCRE_PE2_Pos            (2U)
7799 #define PWR_PUCRE_PE2_Msk            (0x1UL << PWR_PUCRE_PE2_Pos)              /*!< 0x00000004 */
7800 #define PWR_PUCRE_PE2                PWR_PUCRE_PE2_Msk                         /*!< Port PE2 Pull-Up set  */
7801 #define PWR_PUCRE_PE1_Pos            (1U)
7802 #define PWR_PUCRE_PE1_Msk            (0x1UL << PWR_PUCRE_PE1_Pos)              /*!< 0x00000002 */
7803 #define PWR_PUCRE_PE1                PWR_PUCRE_PE1_Msk                         /*!< Port PE1 Pull-Up set  */
7804 #define PWR_PUCRE_PE0_Pos            (0U)
7805 #define PWR_PUCRE_PE0_Msk            (0x1UL << PWR_PUCRE_PE0_Pos)              /*!< 0x00000001 */
7806 #define PWR_PUCRE_PE0                PWR_PUCRE_PE0_Msk                         /*!< Port PE0 Pull-Up set  */
7807 
7808 /********************  Bit definition for PWR_PDCRE register  ********************/
7809 #define PWR_PDCRE_PE15_Pos           (15U)
7810 #define PWR_PDCRE_PE15_Msk           (0x1UL << PWR_PDCRE_PE15_Pos)             /*!< 0x00008000 */
7811 #define PWR_PDCRE_PE15               PWR_PDCRE_PE15_Msk                        /*!< Port PE15 Pull-Down set */
7812 #define PWR_PDCRE_PE14_Pos           (14U)
7813 #define PWR_PDCRE_PE14_Msk           (0x1UL << PWR_PDCRE_PE14_Pos)             /*!< 0x00004000 */
7814 #define PWR_PDCRE_PE14               PWR_PDCRE_PE14_Msk                        /*!< Port PE14 Pull-Down set */
7815 #define PWR_PDCRE_PE13_Pos           (13U)
7816 #define PWR_PDCRE_PE13_Msk           (0x1UL << PWR_PDCRE_PE13_Pos)             /*!< 0x00002000 */
7817 #define PWR_PDCRE_PE13               PWR_PDCRE_PE13_Msk                        /*!< Port PE13 Pull-Down set */
7818 #define PWR_PDCRE_PE12_Pos           (12U)
7819 #define PWR_PDCRE_PE12_Msk           (0x1UL << PWR_PDCRE_PE12_Pos)             /*!< 0x00001000 */
7820 #define PWR_PDCRE_PE12               PWR_PDCRE_PE12_Msk                        /*!< Port PE12 Pull-Down set */
7821 #define PWR_PDCRE_PE11_Pos           (11U)
7822 #define PWR_PDCRE_PE11_Msk           (0x1UL << PWR_PDCRE_PE11_Pos)             /*!< 0x00000800 */
7823 #define PWR_PDCRE_PE11               PWR_PDCRE_PE11_Msk                        /*!< Port PE11 Pull-Down set */
7824 #define PWR_PDCRE_PE10_Pos           (10U)
7825 #define PWR_PDCRE_PE10_Msk           (0x1UL << PWR_PDCRE_PE10_Pos)             /*!< 0x00000400 */
7826 #define PWR_PDCRE_PE10               PWR_PDCRE_PE10_Msk                        /*!< Port PE10 Pull-Down set */
7827 #define PWR_PDCRE_PE9_Pos            (9U)
7828 #define PWR_PDCRE_PE9_Msk            (0x1UL << PWR_PDCRE_PE9_Pos)              /*!< 0x00000200 */
7829 #define PWR_PDCRE_PE9                PWR_PDCRE_PE9_Msk                         /*!< Port PE9 Pull-Down set  */
7830 #define PWR_PDCRE_PE8_Pos            (8U)
7831 #define PWR_PDCRE_PE8_Msk            (0x1UL << PWR_PDCRE_PE8_Pos)              /*!< 0x00000100 */
7832 #define PWR_PDCRE_PE8                PWR_PDCRE_PE8_Msk                         /*!< Port PE8 Pull-Down set  */
7833 #define PWR_PDCRE_PE7_Pos            (7U)
7834 #define PWR_PDCRE_PE7_Msk            (0x1UL << PWR_PDCRE_PE7_Pos)              /*!< 0x00000080 */
7835 #define PWR_PDCRE_PE7                PWR_PDCRE_PE7_Msk                         /*!< Port PE7 Pull-Down set  */
7836 #define PWR_PDCRE_PE6_Pos            (6U)
7837 #define PWR_PDCRE_PE6_Msk            (0x1UL << PWR_PDCRE_PE6_Pos)              /*!< 0x00000040 */
7838 #define PWR_PDCRE_PE6                PWR_PDCRE_PE6_Msk                         /*!< Port PE6 Pull-Down set  */
7839 #define PWR_PDCRE_PE5_Pos            (5U)
7840 #define PWR_PDCRE_PE5_Msk            (0x1UL << PWR_PDCRE_PE5_Pos)              /*!< 0x00000020 */
7841 #define PWR_PDCRE_PE5                PWR_PDCRE_PE5_Msk                         /*!< Port PE5 Pull-Down set  */
7842 #define PWR_PDCRE_PE4_Pos            (4U)
7843 #define PWR_PDCRE_PE4_Msk            (0x1UL << PWR_PDCRE_PE4_Pos)              /*!< 0x00000010 */
7844 #define PWR_PDCRE_PE4                PWR_PDCRE_PE4_Msk                         /*!< Port PE4 Pull-Down set  */
7845 #define PWR_PDCRE_PE3_Pos            (3U)
7846 #define PWR_PDCRE_PE3_Msk            (0x1UL << PWR_PDCRE_PE3_Pos)              /*!< 0x00000008 */
7847 #define PWR_PDCRE_PE3                PWR_PDCRE_PE3_Msk                         /*!< Port PE3 Pull-Down set  */
7848 #define PWR_PDCRE_PE2_Pos            (2U)
7849 #define PWR_PDCRE_PE2_Msk            (0x1UL << PWR_PDCRE_PE2_Pos)              /*!< 0x00000004 */
7850 #define PWR_PDCRE_PE2                PWR_PDCRE_PE2_Msk                         /*!< Port PE2 Pull-Down set  */
7851 #define PWR_PDCRE_PE1_Pos            (1U)
7852 #define PWR_PDCRE_PE1_Msk            (0x1UL << PWR_PDCRE_PE1_Pos)              /*!< 0x00000002 */
7853 #define PWR_PDCRE_PE1                PWR_PDCRE_PE1_Msk                         /*!< Port PE1 Pull-Down set  */
7854 #define PWR_PDCRE_PE0_Pos            (0U)
7855 #define PWR_PDCRE_PE0_Msk            (0x1UL << PWR_PDCRE_PE0_Pos)              /*!< 0x00000001 */
7856 #define PWR_PDCRE_PE0                PWR_PDCRE_PE0_Msk                         /*!< Port PE0 Pull-Down set  */
7857 
7858 /********************  Bit definition for PWR_PUCRF register  ********************/
7859 #define PWR_PUCRF_PF15_Pos           (15U)
7860 #define PWR_PUCRF_PF15_Msk           (0x1UL << PWR_PUCRF_PF15_Pos)             /*!< 0x00008000 */
7861 #define PWR_PUCRF_PF15               PWR_PUCRF_PF15_Msk                        /*!< Port PF15 Pull-Up set */
7862 #define PWR_PUCRF_PF14_Pos           (14U)
7863 #define PWR_PUCRF_PF14_Msk           (0x1UL << PWR_PUCRF_PF14_Pos)             /*!< 0x00004000 */
7864 #define PWR_PUCRF_PF14               PWR_PUCRF_PF14_Msk                        /*!< Port PF14 Pull-Up set */
7865 #define PWR_PUCRF_PF13_Pos           (13U)
7866 #define PWR_PUCRF_PF13_Msk           (0x1UL << PWR_PUCRF_PF13_Pos)             /*!< 0x00002000 */
7867 #define PWR_PUCRF_PF13               PWR_PUCRF_PF13_Msk                        /*!< Port PF13 Pull-Up set */
7868 #define PWR_PUCRF_PF12_Pos           (12U)
7869 #define PWR_PUCRF_PF12_Msk           (0x1UL << PWR_PUCRF_PF12_Pos)             /*!< 0x00001000 */
7870 #define PWR_PUCRF_PF12               PWR_PUCRF_PF12_Msk                        /*!< Port PF12 Pull-Up set */
7871 #define PWR_PUCRF_PF11_Pos           (11U)
7872 #define PWR_PUCRF_PF11_Msk           (0x1UL << PWR_PUCRF_PF11_Pos)             /*!< 0x00000800 */
7873 #define PWR_PUCRF_PF11               PWR_PUCRF_PF11_Msk                        /*!< Port PF11 Pull-Up set */
7874 #define PWR_PUCRF_PF10_Pos           (10U)
7875 #define PWR_PUCRF_PF10_Msk           (0x1UL << PWR_PUCRF_PF10_Pos)             /*!< 0x00000400 */
7876 #define PWR_PUCRF_PF10               PWR_PUCRF_PF10_Msk                        /*!< Port PF10 Pull-Up set */
7877 #define PWR_PUCRF_PF9_Pos            (9U)
7878 #define PWR_PUCRF_PF9_Msk            (0x1UL << PWR_PUCRF_PF9_Pos)              /*!< 0x00000200 */
7879 #define PWR_PUCRF_PF9                PWR_PUCRF_PF9_Msk                         /*!< Port PF9 Pull-Up set  */
7880 #define PWR_PUCRF_PF8_Pos            (8U)
7881 #define PWR_PUCRF_PF8_Msk            (0x1UL << PWR_PUCRF_PF8_Pos)              /*!< 0x00000100 */
7882 #define PWR_PUCRF_PF8                PWR_PUCRF_PF8_Msk                         /*!< Port PF8 Pull-Up set  */
7883 #define PWR_PUCRF_PF7_Pos            (7U)
7884 #define PWR_PUCRF_PF7_Msk            (0x1UL << PWR_PUCRF_PF7_Pos)              /*!< 0x00000080 */
7885 #define PWR_PUCRF_PF7                PWR_PUCRF_PF7_Msk                         /*!< Port PF7 Pull-Up set  */
7886 #define PWR_PUCRF_PF6_Pos            (6U)
7887 #define PWR_PUCRF_PF6_Msk            (0x1UL << PWR_PUCRF_PF6_Pos)              /*!< 0x00000040 */
7888 #define PWR_PUCRF_PF6                PWR_PUCRF_PF6_Msk                         /*!< Port PF6 Pull-Up set  */
7889 #define PWR_PUCRF_PF5_Pos            (5U)
7890 #define PWR_PUCRF_PF5_Msk            (0x1UL << PWR_PUCRF_PF5_Pos)              /*!< 0x00000020 */
7891 #define PWR_PUCRF_PF5                PWR_PUCRF_PF5_Msk                         /*!< Port PF5 Pull-Up set  */
7892 #define PWR_PUCRF_PF4_Pos            (4U)
7893 #define PWR_PUCRF_PF4_Msk            (0x1UL << PWR_PUCRF_PF4_Pos)              /*!< 0x00000010 */
7894 #define PWR_PUCRF_PF4                PWR_PUCRF_PF4_Msk                         /*!< Port PF4 Pull-Up set  */
7895 #define PWR_PUCRF_PF3_Pos            (3U)
7896 #define PWR_PUCRF_PF3_Msk            (0x1UL << PWR_PUCRF_PF3_Pos)              /*!< 0x00000008 */
7897 #define PWR_PUCRF_PF3                PWR_PUCRF_PF3_Msk                         /*!< Port PF3 Pull-Up set  */
7898 #define PWR_PUCRF_PF2_Pos            (2U)
7899 #define PWR_PUCRF_PF2_Msk            (0x1UL << PWR_PUCRF_PF2_Pos)              /*!< 0x00000004 */
7900 #define PWR_PUCRF_PF2                PWR_PUCRF_PF2_Msk                         /*!< Port PF2 Pull-Up set  */
7901 #define PWR_PUCRF_PF1_Pos            (1U)
7902 #define PWR_PUCRF_PF1_Msk            (0x1UL << PWR_PUCRF_PF1_Pos)              /*!< 0x00000002 */
7903 #define PWR_PUCRF_PF1                PWR_PUCRF_PF1_Msk                         /*!< Port PF1 Pull-Up set  */
7904 #define PWR_PUCRF_PF0_Pos            (0U)
7905 #define PWR_PUCRF_PF0_Msk            (0x1UL << PWR_PUCRF_PF0_Pos)              /*!< 0x00000001 */
7906 #define PWR_PUCRF_PF0                PWR_PUCRF_PF0_Msk                         /*!< Port PF0 Pull-Up set  */
7907 
7908 /********************  Bit definition for PWR_PDCRF register  ********************/
7909 #define PWR_PDCRF_PF15_Pos           (15U)
7910 #define PWR_PDCRF_PF15_Msk           (0x1UL << PWR_PDCRF_PF15_Pos)             /*!< 0x00008000 */
7911 #define PWR_PDCRF_PF15               PWR_PDCRF_PF15_Msk                        /*!< Port PF15 Pull-Down set */
7912 #define PWR_PDCRF_PF14_Pos           (14U)
7913 #define PWR_PDCRF_PF14_Msk           (0x1UL << PWR_PDCRF_PF14_Pos)             /*!< 0x00004000 */
7914 #define PWR_PDCRF_PF14               PWR_PDCRF_PF14_Msk                        /*!< Port PF14 Pull-Down set */
7915 #define PWR_PDCRF_PF13_Pos           (13U)
7916 #define PWR_PDCRF_PF13_Msk           (0x1UL << PWR_PDCRF_PF13_Pos)             /*!< 0x00002000 */
7917 #define PWR_PDCRF_PF13               PWR_PDCRF_PF13_Msk                        /*!< Port PF13 Pull-Down set */
7918 #define PWR_PDCRF_PF12_Pos           (12U)
7919 #define PWR_PDCRF_PF12_Msk           (0x1UL << PWR_PDCRF_PF12_Pos)             /*!< 0x00001000 */
7920 #define PWR_PDCRF_PF12               PWR_PDCRF_PF12_Msk                        /*!< Port PF12 Pull-Down set */
7921 #define PWR_PDCRF_PF11_Pos           (11U)
7922 #define PWR_PDCRF_PF11_Msk           (0x1UL << PWR_PDCRF_PF11_Pos)             /*!< 0x00000800 */
7923 #define PWR_PDCRF_PF11               PWR_PDCRF_PF11_Msk                        /*!< Port PF11 Pull-Down set */
7924 #define PWR_PDCRF_PF10_Pos           (10U)
7925 #define PWR_PDCRF_PF10_Msk           (0x1UL << PWR_PDCRF_PF10_Pos)             /*!< 0x00000400 */
7926 #define PWR_PDCRF_PF10               PWR_PDCRF_PF10_Msk                        /*!< Port PF10 Pull-Down set */
7927 #define PWR_PDCRF_PF9_Pos            (9U)
7928 #define PWR_PDCRF_PF9_Msk            (0x1UL << PWR_PDCRF_PF9_Pos)              /*!< 0x00000200 */
7929 #define PWR_PDCRF_PF9                PWR_PDCRF_PF9_Msk                         /*!< Port PF9 Pull-Down set  */
7930 #define PWR_PDCRF_PF8_Pos            (8U)
7931 #define PWR_PDCRF_PF8_Msk            (0x1UL << PWR_PDCRF_PF8_Pos)              /*!< 0x00000100 */
7932 #define PWR_PDCRF_PF8                PWR_PDCRF_PF8_Msk                         /*!< Port PF8 Pull-Down set  */
7933 #define PWR_PDCRF_PF7_Pos            (7U)
7934 #define PWR_PDCRF_PF7_Msk            (0x1UL << PWR_PDCRF_PF7_Pos)              /*!< 0x00000080 */
7935 #define PWR_PDCRF_PF7                PWR_PDCRF_PF7_Msk                         /*!< Port PF7 Pull-Down set  */
7936 #define PWR_PDCRF_PF6_Pos            (6U)
7937 #define PWR_PDCRF_PF6_Msk            (0x1UL << PWR_PDCRF_PF6_Pos)              /*!< 0x00000040 */
7938 #define PWR_PDCRF_PF6                PWR_PDCRF_PF6_Msk                         /*!< Port PF6 Pull-Down set  */
7939 #define PWR_PDCRF_PF5_Pos            (5U)
7940 #define PWR_PDCRF_PF5_Msk            (0x1UL << PWR_PDCRF_PF5_Pos)              /*!< 0x00000020 */
7941 #define PWR_PDCRF_PF5                PWR_PDCRF_PF5_Msk                         /*!< Port PF5 Pull-Down set  */
7942 #define PWR_PDCRF_PF4_Pos            (4U)
7943 #define PWR_PDCRF_PF4_Msk            (0x1UL << PWR_PDCRF_PF4_Pos)              /*!< 0x00000010 */
7944 #define PWR_PDCRF_PF4                PWR_PDCRF_PF4_Msk                         /*!< Port PF4 Pull-Down set  */
7945 #define PWR_PDCRF_PF3_Pos            (3U)
7946 #define PWR_PDCRF_PF3_Msk            (0x1UL << PWR_PDCRF_PF3_Pos)              /*!< 0x00000008 */
7947 #define PWR_PDCRF_PF3                PWR_PDCRF_PF3_Msk                         /*!< Port PF3 Pull-Down set  */
7948 #define PWR_PDCRF_PF2_Pos            (2U)
7949 #define PWR_PDCRF_PF2_Msk            (0x1UL << PWR_PDCRF_PF2_Pos)              /*!< 0x00000004 */
7950 #define PWR_PDCRF_PF2                PWR_PDCRF_PF2_Msk                         /*!< Port PF2 Pull-Down set  */
7951 #define PWR_PDCRF_PF1_Pos            (1U)
7952 #define PWR_PDCRF_PF1_Msk            (0x1UL << PWR_PDCRF_PF1_Pos)              /*!< 0x00000002 */
7953 #define PWR_PDCRF_PF1                PWR_PDCRF_PF1_Msk                         /*!< Port PF1 Pull-Down set  */
7954 #define PWR_PDCRF_PF0_Pos            (0U)
7955 #define PWR_PDCRF_PF0_Msk            (0x1UL << PWR_PDCRF_PF0_Pos)              /*!< 0x00000001 */
7956 #define PWR_PDCRF_PF0                PWR_PDCRF_PF0_Msk                         /*!< Port PF0 Pull-Down set  */
7957 
7958 /********************  Bit definition for PWR_PUCRG register  ********************/
7959 #define PWR_PUCRG_PG15_Pos           (15U)
7960 #define PWR_PUCRG_PG15_Msk           (0x1UL << PWR_PUCRG_PG15_Pos)             /*!< 0x00008000 */
7961 #define PWR_PUCRG_PG15               PWR_PUCRG_PG15_Msk                        /*!< Port PG15 Pull-Up set */
7962 #define PWR_PUCRG_PG14_Pos           (14U)
7963 #define PWR_PUCRG_PG14_Msk           (0x1UL << PWR_PUCRG_PG14_Pos)             /*!< 0x00004000 */
7964 #define PWR_PUCRG_PG14               PWR_PUCRG_PG14_Msk                        /*!< Port PG14 Pull-Up set */
7965 #define PWR_PUCRG_PG13_Pos           (13U)
7966 #define PWR_PUCRG_PG13_Msk           (0x1UL << PWR_PUCRG_PG13_Pos)             /*!< 0x00002000 */
7967 #define PWR_PUCRG_PG13               PWR_PUCRG_PG13_Msk                        /*!< Port PG13 Pull-Up set */
7968 #define PWR_PUCRG_PG12_Pos           (12U)
7969 #define PWR_PUCRG_PG12_Msk           (0x1UL << PWR_PUCRG_PG12_Pos)             /*!< 0x00001000 */
7970 #define PWR_PUCRG_PG12               PWR_PUCRG_PG12_Msk                        /*!< Port PG12 Pull-Up set */
7971 #define PWR_PUCRG_PG11_Pos           (11U)
7972 #define PWR_PUCRG_PG11_Msk           (0x1UL << PWR_PUCRG_PG11_Pos)             /*!< 0x00000800 */
7973 #define PWR_PUCRG_PG11               PWR_PUCRG_PG11_Msk                        /*!< Port PG11 Pull-Up set */
7974 #define PWR_PUCRG_PG10_Pos           (10U)
7975 #define PWR_PUCRG_PG10_Msk           (0x1UL << PWR_PUCRG_PG10_Pos)             /*!< 0x00000400 */
7976 #define PWR_PUCRG_PG10               PWR_PUCRG_PG10_Msk                        /*!< Port PG10 Pull-Up set */
7977 #define PWR_PUCRG_PG9_Pos            (9U)
7978 #define PWR_PUCRG_PG9_Msk            (0x1UL << PWR_PUCRG_PG9_Pos)              /*!< 0x00000200 */
7979 #define PWR_PUCRG_PG9                PWR_PUCRG_PG9_Msk                         /*!< Port PG9 Pull-Up set  */
7980 #define PWR_PUCRG_PG8_Pos            (8U)
7981 #define PWR_PUCRG_PG8_Msk            (0x1UL << PWR_PUCRG_PG8_Pos)              /*!< 0x00000100 */
7982 #define PWR_PUCRG_PG8                PWR_PUCRG_PG8_Msk                         /*!< Port PG8 Pull-Up set  */
7983 #define PWR_PUCRG_PG7_Pos            (7U)
7984 #define PWR_PUCRG_PG7_Msk            (0x1UL << PWR_PUCRG_PG7_Pos)              /*!< 0x00000080 */
7985 #define PWR_PUCRG_PG7                PWR_PUCRG_PG7_Msk                         /*!< Port PG7 Pull-Up set  */
7986 #define PWR_PUCRG_PG6_Pos            (6U)
7987 #define PWR_PUCRG_PG6_Msk            (0x1UL << PWR_PUCRG_PG6_Pos)              /*!< 0x00000040 */
7988 #define PWR_PUCRG_PG6                PWR_PUCRG_PG6_Msk                         /*!< Port PG6 Pull-Up set  */
7989 #define PWR_PUCRG_PG5_Pos            (5U)
7990 #define PWR_PUCRG_PG5_Msk            (0x1UL << PWR_PUCRG_PG5_Pos)              /*!< 0x00000020 */
7991 #define PWR_PUCRG_PG5                PWR_PUCRG_PG5_Msk                         /*!< Port PG5 Pull-Up set  */
7992 #define PWR_PUCRG_PG4_Pos            (4U)
7993 #define PWR_PUCRG_PG4_Msk            (0x1UL << PWR_PUCRG_PG4_Pos)              /*!< 0x00000010 */
7994 #define PWR_PUCRG_PG4                PWR_PUCRG_PG4_Msk                         /*!< Port PG4 Pull-Up set  */
7995 #define PWR_PUCRG_PG3_Pos            (3U)
7996 #define PWR_PUCRG_PG3_Msk            (0x1UL << PWR_PUCRG_PG3_Pos)              /*!< 0x00000008 */
7997 #define PWR_PUCRG_PG3                PWR_PUCRG_PG3_Msk                         /*!< Port PG3 Pull-Up set  */
7998 #define PWR_PUCRG_PG2_Pos            (2U)
7999 #define PWR_PUCRG_PG2_Msk            (0x1UL << PWR_PUCRG_PG2_Pos)              /*!< 0x00000004 */
8000 #define PWR_PUCRG_PG2                PWR_PUCRG_PG2_Msk                         /*!< Port PG2 Pull-Up set  */
8001 #define PWR_PUCRG_PG1_Pos            (1U)
8002 #define PWR_PUCRG_PG1_Msk            (0x1UL << PWR_PUCRG_PG1_Pos)              /*!< 0x00000002 */
8003 #define PWR_PUCRG_PG1                PWR_PUCRG_PG1_Msk                         /*!< Port PG1 Pull-Up set  */
8004 #define PWR_PUCRG_PG0_Pos            (0U)
8005 #define PWR_PUCRG_PG0_Msk            (0x1UL << PWR_PUCRG_PG0_Pos)              /*!< 0x00000001 */
8006 #define PWR_PUCRG_PG0                PWR_PUCRG_PG0_Msk                         /*!< Port PG0 Pull-Up set  */
8007 
8008 /********************  Bit definition for PWR_PDCRG register  ********************/
8009 #define PWR_PDCRG_PG10_Pos           (10U)
8010 #define PWR_PDCRG_PG10_Msk           (0x1UL << PWR_PDCRG_PG10_Pos)             /*!< 0x00000400 */
8011 #define PWR_PDCRG_PG10               PWR_PDCRG_PG10_Msk                        /*!< Port PG10 Pull-Down set */
8012 #define PWR_PDCRG_PG9_Pos            (9U)
8013 #define PWR_PDCRG_PG9_Msk            (0x1UL << PWR_PDCRG_PG9_Pos)              /*!< 0x00000200 */
8014 #define PWR_PDCRG_PG9                PWR_PDCRG_PG9_Msk                         /*!< Port PG9 Pull-Down set  */
8015 #define PWR_PDCRG_PG8_Pos            (8U)
8016 #define PWR_PDCRG_PG8_Msk            (0x1UL << PWR_PDCRG_PG8_Pos)              /*!< 0x00000100 */
8017 #define PWR_PDCRG_PG8                PWR_PDCRG_PG8_Msk                         /*!< Port PG8 Pull-Down set  */
8018 #define PWR_PDCRG_PG7_Pos            (7U)
8019 #define PWR_PDCRG_PG7_Msk            (0x1UL << PWR_PDCRG_PG7_Pos)              /*!< 0x00000080 */
8020 #define PWR_PDCRG_PG7                PWR_PDCRG_PG7_Msk                         /*!< Port PG7 Pull-Down set  */
8021 #define PWR_PDCRG_PG6_Pos            (6U)
8022 #define PWR_PDCRG_PG6_Msk            (0x1UL << PWR_PDCRG_PG6_Pos)              /*!< 0x00000040 */
8023 #define PWR_PDCRG_PG6                PWR_PDCRG_PG6_Msk                         /*!< Port PG6 Pull-Down set  */
8024 #define PWR_PDCRG_PG5_Pos            (5U)
8025 #define PWR_PDCRG_PG5_Msk            (0x1UL << PWR_PDCRG_PG5_Pos)              /*!< 0x00000020 */
8026 #define PWR_PDCRG_PG5                PWR_PDCRG_PG5_Msk                         /*!< Port PG5 Pull-Down set  */
8027 #define PWR_PDCRG_PG4_Pos            (4U)
8028 #define PWR_PDCRG_PG4_Msk            (0x1UL << PWR_PDCRG_PG4_Pos)              /*!< 0x00000010 */
8029 #define PWR_PDCRG_PG4                PWR_PDCRG_PG4_Msk                         /*!< Port PG4 Pull-Down set  */
8030 #define PWR_PDCRG_PG3_Pos            (3U)
8031 #define PWR_PDCRG_PG3_Msk            (0x1UL << PWR_PDCRG_PG3_Pos)              /*!< 0x00000008 */
8032 #define PWR_PDCRG_PG3                PWR_PDCRG_PG3_Msk                         /*!< Port PG3 Pull-Down set  */
8033 #define PWR_PDCRG_PG2_Pos            (2U)
8034 #define PWR_PDCRG_PG2_Msk            (0x1UL << PWR_PDCRG_PG2_Pos)              /*!< 0x00000004 */
8035 #define PWR_PDCRG_PG2                PWR_PDCRG_PG2_Msk                         /*!< Port PG2 Pull-Down set  */
8036 #define PWR_PDCRG_PG1_Pos            (1U)
8037 #define PWR_PDCRG_PG1_Msk            (0x1UL << PWR_PDCRG_PG1_Pos)              /*!< 0x00000002 */
8038 #define PWR_PDCRG_PG1                PWR_PDCRG_PG1_Msk                         /*!< Port PG1 Pull-Down set  */
8039 #define PWR_PDCRG_PG0_Pos            (0U)
8040 #define PWR_PDCRG_PG0_Msk            (0x1UL << PWR_PDCRG_PG0_Pos)              /*!< 0x00000001 */
8041 #define PWR_PDCRG_PG0                PWR_PDCRG_PG0_Msk                         /*!< Port PG0 Pull-Down set  */
8042 
8043 /********************  Bit definition for PWR_CR5 register  ********************/
8044 #define PWR_CR5_R1MODE_Pos           (8U)
8045 #define PWR_CR5_R1MODE_Msk           (0x1U << PWR_CR5_R1MODE_Pos)              /*!< 0x00000100 */
8046 #define PWR_CR5_R1MODE               PWR_CR5_R1MODE_Msk                        /*!< selection for Main Regulator in Range1 */
8047 
8048 /******************************************************************************/
8049 /*                                                                            */
8050 /*                                    QUADSPI                                 */
8051 /*                                                                            */
8052 /******************************************************************************/
8053 /*****************  Bit definition for QUADSPI_CR register  *******************/
8054 #define QUADSPI_CR_EN_Pos              (0U)
8055 #define QUADSPI_CR_EN_Msk              (0x1UL << QUADSPI_CR_EN_Pos)            /*!< 0x00000001 */
8056 #define QUADSPI_CR_EN                  QUADSPI_CR_EN_Msk                       /*!< Enable */
8057 #define QUADSPI_CR_ABORT_Pos           (1U)
8058 #define QUADSPI_CR_ABORT_Msk           (0x1UL << QUADSPI_CR_ABORT_Pos)         /*!< 0x00000002 */
8059 #define QUADSPI_CR_ABORT               QUADSPI_CR_ABORT_Msk                    /*!< Abort request */
8060 #define QUADSPI_CR_DMAEN_Pos           (2U)
8061 #define QUADSPI_CR_DMAEN_Msk           (0x1UL << QUADSPI_CR_DMAEN_Pos)         /*!< 0x00000004 */
8062 #define QUADSPI_CR_DMAEN               QUADSPI_CR_DMAEN_Msk                    /*!< DMA Enable */
8063 #define QUADSPI_CR_TCEN_Pos            (3U)
8064 #define QUADSPI_CR_TCEN_Msk            (0x1UL << QUADSPI_CR_TCEN_Pos)          /*!< 0x00000008 */
8065 #define QUADSPI_CR_TCEN                QUADSPI_CR_TCEN_Msk                     /*!< Timeout Counter Enable */
8066 #define QUADSPI_CR_SSHIFT_Pos          (4U)
8067 #define QUADSPI_CR_SSHIFT_Msk          (0x1UL << QUADSPI_CR_SSHIFT_Pos)        /*!< 0x00000010 */
8068 #define QUADSPI_CR_SSHIFT              QUADSPI_CR_SSHIFT_Msk                   /*!< Sample Shift */
8069 #define QUADSPI_CR_DFM_Pos             (6U)
8070 #define QUADSPI_CR_DFM_Msk             (0x1UL << QUADSPI_CR_DFM_Pos)           /*!< 0x00000040 */
8071 #define QUADSPI_CR_DFM                 QUADSPI_CR_DFM_Msk                      /*!< Dual-flash mode */
8072 #define QUADSPI_CR_FSEL_Pos            (7U)
8073 #define QUADSPI_CR_FSEL_Msk            (0x1UL << QUADSPI_CR_FSEL_Pos)          /*!< 0x00000080 */
8074 #define QUADSPI_CR_FSEL                QUADSPI_CR_FSEL_Msk                     /*!< Flash memory selection */
8075 #define QUADSPI_CR_FTHRES_Pos          (8U)
8076 #define QUADSPI_CR_FTHRES_Msk          (0xFUL << QUADSPI_CR_FTHRES_Pos)        /*!< 0x00000F00 */
8077 #define QUADSPI_CR_FTHRES              QUADSPI_CR_FTHRES_Msk                   /*!< FTHRES[3:0] FIFO Level */
8078 #define QUADSPI_CR_TEIE_Pos            (16U)
8079 #define QUADSPI_CR_TEIE_Msk            (0x1UL << QUADSPI_CR_TEIE_Pos)          /*!< 0x00010000 */
8080 #define QUADSPI_CR_TEIE                QUADSPI_CR_TEIE_Msk                     /*!< Transfer Error Interrupt Enable */
8081 #define QUADSPI_CR_TCIE_Pos            (17U)
8082 #define QUADSPI_CR_TCIE_Msk            (0x1UL << QUADSPI_CR_TCIE_Pos)          /*!< 0x00020000 */
8083 #define QUADSPI_CR_TCIE                QUADSPI_CR_TCIE_Msk                     /*!< Transfer Complete Interrupt Enable */
8084 #define QUADSPI_CR_FTIE_Pos            (18U)
8085 #define QUADSPI_CR_FTIE_Msk            (0x1UL << QUADSPI_CR_FTIE_Pos)          /*!< 0x00040000 */
8086 #define QUADSPI_CR_FTIE                QUADSPI_CR_FTIE_Msk                     /*!< FIFO Threshold Interrupt Enable */
8087 #define QUADSPI_CR_SMIE_Pos            (19U)
8088 #define QUADSPI_CR_SMIE_Msk            (0x1UL << QUADSPI_CR_SMIE_Pos)          /*!< 0x00080000 */
8089 #define QUADSPI_CR_SMIE                QUADSPI_CR_SMIE_Msk                     /*!< Status Match Interrupt Enable */
8090 #define QUADSPI_CR_TOIE_Pos            (20U)
8091 #define QUADSPI_CR_TOIE_Msk            (0x1UL << QUADSPI_CR_TOIE_Pos)          /*!< 0x00100000 */
8092 #define QUADSPI_CR_TOIE                QUADSPI_CR_TOIE_Msk                     /*!< TimeOut Interrupt Enable */
8093 #define QUADSPI_CR_APMS_Pos            (22U)
8094 #define QUADSPI_CR_APMS_Msk            (0x1UL << QUADSPI_CR_APMS_Pos)          /*!< 0x00400000 */
8095 #define QUADSPI_CR_APMS                QUADSPI_CR_APMS_Msk                     /*!< Automatic Polling Mode Stop */
8096 #define QUADSPI_CR_PMM_Pos             (23U)
8097 #define QUADSPI_CR_PMM_Msk             (0x1UL << QUADSPI_CR_PMM_Pos)           /*!< 0x00800000 */
8098 #define QUADSPI_CR_PMM                 QUADSPI_CR_PMM_Msk                      /*!< Polling Match Mode */
8099 #define QUADSPI_CR_PRESCALER_Pos       (24U)
8100 #define QUADSPI_CR_PRESCALER_Msk       (0xFFUL << QUADSPI_CR_PRESCALER_Pos)    /*!< 0xFF000000 */
8101 #define QUADSPI_CR_PRESCALER           QUADSPI_CR_PRESCALER_Msk                /*!< PRESCALER[7:0] Clock prescaler */
8102 
8103 /*****************  Bit definition for QUADSPI_DCR register  ******************/
8104 #define QUADSPI_DCR_CKMODE_Pos         (0U)
8105 #define QUADSPI_DCR_CKMODE_Msk         (0x1UL << QUADSPI_DCR_CKMODE_Pos)       /*!< 0x00000001 */
8106 #define QUADSPI_DCR_CKMODE             QUADSPI_DCR_CKMODE_Msk                  /*!< Mode 0 / Mode 3 */
8107 #define QUADSPI_DCR_CSHT_Pos           (8U)
8108 #define QUADSPI_DCR_CSHT_Msk           (0x7UL << QUADSPI_DCR_CSHT_Pos)         /*!< 0x00000700 */
8109 #define QUADSPI_DCR_CSHT               QUADSPI_DCR_CSHT_Msk                    /*!< CSHT[2:0]: ChipSelect High Time */
8110 #define QUADSPI_DCR_CSHT_0             (0x1UL << QUADSPI_DCR_CSHT_Pos)         /*!< 0x00000100 */
8111 #define QUADSPI_DCR_CSHT_1             (0x2UL << QUADSPI_DCR_CSHT_Pos)         /*!< 0x00000200 */
8112 #define QUADSPI_DCR_CSHT_2             (0x4UL << QUADSPI_DCR_CSHT_Pos)         /*!< 0x00000400 */
8113 #define QUADSPI_DCR_FSIZE_Pos          (16U)
8114 #define QUADSPI_DCR_FSIZE_Msk          (0x1FUL << QUADSPI_DCR_FSIZE_Pos)       /*!< 0x001F0000 */
8115 #define QUADSPI_DCR_FSIZE              QUADSPI_DCR_FSIZE_Msk                   /*!< FSIZE[4:0]: Flash Size */
8116 
8117 /******************  Bit definition for QUADSPI_SR register  *******************/
8118 #define QUADSPI_SR_TEF_Pos             (0U)
8119 #define QUADSPI_SR_TEF_Msk             (0x1UL << QUADSPI_SR_TEF_Pos)           /*!< 0x00000001 */
8120 #define QUADSPI_SR_TEF                 QUADSPI_SR_TEF_Msk                      /*!< Transfer Error Flag */
8121 #define QUADSPI_SR_TCF_Pos             (1U)
8122 #define QUADSPI_SR_TCF_Msk             (0x1UL << QUADSPI_SR_TCF_Pos)           /*!< 0x00000002 */
8123 #define QUADSPI_SR_TCF                 QUADSPI_SR_TCF_Msk                      /*!< Transfer Complete Flag */
8124 #define QUADSPI_SR_FTF_Pos             (2U)
8125 #define QUADSPI_SR_FTF_Msk             (0x1UL << QUADSPI_SR_FTF_Pos)           /*!< 0x00000004 */
8126 #define QUADSPI_SR_FTF                 QUADSPI_SR_FTF_Msk                      /*!< FIFO Threshlod Flag */
8127 #define QUADSPI_SR_SMF_Pos             (3U)
8128 #define QUADSPI_SR_SMF_Msk             (0x1UL << QUADSPI_SR_SMF_Pos)           /*!< 0x00000008 */
8129 #define QUADSPI_SR_SMF                 QUADSPI_SR_SMF_Msk                      /*!< Status Match Flag */
8130 #define QUADSPI_SR_TOF_Pos             (4U)
8131 #define QUADSPI_SR_TOF_Msk             (0x1UL << QUADSPI_SR_TOF_Pos)           /*!< 0x00000010 */
8132 #define QUADSPI_SR_TOF                 QUADSPI_SR_TOF_Msk                      /*!< Timeout Flag */
8133 #define QUADSPI_SR_BUSY_Pos            (5U)
8134 #define QUADSPI_SR_BUSY_Msk            (0x1UL << QUADSPI_SR_BUSY_Pos)          /*!< 0x00000020 */
8135 #define QUADSPI_SR_BUSY                QUADSPI_SR_BUSY_Msk                     /*!< Busy */
8136 #define QUADSPI_SR_FLEVEL_Pos          (8U)
8137 #define QUADSPI_SR_FLEVEL_Msk          (0x1FUL << QUADSPI_SR_FLEVEL_Pos)       /*!< 0x00001F00 */
8138 #define QUADSPI_SR_FLEVEL              QUADSPI_SR_FLEVEL_Msk                   /*!< FIFO Threshlod Flag */
8139 
8140 /******************  Bit definition for QUADSPI_FCR register  ******************/
8141 #define QUADSPI_FCR_CTEF_Pos           (0U)
8142 #define QUADSPI_FCR_CTEF_Msk           (0x1UL << QUADSPI_FCR_CTEF_Pos)         /*!< 0x00000001 */
8143 #define QUADSPI_FCR_CTEF               QUADSPI_FCR_CTEF_Msk                    /*!< Clear Transfer Error Flag */
8144 #define QUADSPI_FCR_CTCF_Pos           (1U)
8145 #define QUADSPI_FCR_CTCF_Msk           (0x1UL << QUADSPI_FCR_CTCF_Pos)         /*!< 0x00000002 */
8146 #define QUADSPI_FCR_CTCF               QUADSPI_FCR_CTCF_Msk                    /*!< Clear Transfer Complete Flag */
8147 #define QUADSPI_FCR_CSMF_Pos           (3U)
8148 #define QUADSPI_FCR_CSMF_Msk           (0x1UL << QUADSPI_FCR_CSMF_Pos)         /*!< 0x00000008 */
8149 #define QUADSPI_FCR_CSMF               QUADSPI_FCR_CSMF_Msk                    /*!< Clear Status Match Flag */
8150 #define QUADSPI_FCR_CTOF_Pos           (4U)
8151 #define QUADSPI_FCR_CTOF_Msk           (0x1UL << QUADSPI_FCR_CTOF_Pos)         /*!< 0x00000010 */
8152 #define QUADSPI_FCR_CTOF               QUADSPI_FCR_CTOF_Msk                    /*!< Clear Timeout Flag */
8153 
8154 /******************  Bit definition for QUADSPI_DLR register  ******************/
8155 #define QUADSPI_DLR_DL_Pos             (0U)
8156 #define QUADSPI_DLR_DL_Msk             (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)    /*!< 0xFFFFFFFF */
8157 #define QUADSPI_DLR_DL                 QUADSPI_DLR_DL_Msk                      /*!< DL[31:0]: Data Length */
8158 
8159 /******************  Bit definition for QUADSPI_CCR register  ******************/
8160 #define QUADSPI_CCR_INSTRUCTION_Pos    (0U)
8161 #define QUADSPI_CCR_INSTRUCTION_Msk    (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
8162 #define QUADSPI_CCR_INSTRUCTION        QUADSPI_CCR_INSTRUCTION_Msk             /*!< INSTRUCTION[7:0]: Instruction */
8163 #define QUADSPI_CCR_IMODE_Pos          (8U)
8164 #define QUADSPI_CCR_IMODE_Msk          (0x3UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000300 */
8165 #define QUADSPI_CCR_IMODE              QUADSPI_CCR_IMODE_Msk                   /*!< IMODE[1:0]: Instruction Mode */
8166 #define QUADSPI_CCR_IMODE_0            (0x1UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000100 */
8167 #define QUADSPI_CCR_IMODE_1            (0x2UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000200 */
8168 #define QUADSPI_CCR_ADMODE_Pos         (10U)
8169 #define QUADSPI_CCR_ADMODE_Msk         (0x3UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000C00 */
8170 #define QUADSPI_CCR_ADMODE             QUADSPI_CCR_ADMODE_Msk                  /*!< ADMODE[1:0]: Address Mode */
8171 #define QUADSPI_CCR_ADMODE_0           (0x1UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000400 */
8172 #define QUADSPI_CCR_ADMODE_1           (0x2UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000800 */
8173 #define QUADSPI_CCR_ADSIZE_Pos         (12U)
8174 #define QUADSPI_CCR_ADSIZE_Msk         (0x3UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00003000 */
8175 #define QUADSPI_CCR_ADSIZE             QUADSPI_CCR_ADSIZE_Msk                  /*!< ADSIZE[1:0]: Address Size */
8176 #define QUADSPI_CCR_ADSIZE_0           (0x1UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00001000 */
8177 #define QUADSPI_CCR_ADSIZE_1           (0x2UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00002000 */
8178 #define QUADSPI_CCR_ABMODE_Pos         (14U)
8179 #define QUADSPI_CCR_ABMODE_Msk         (0x3UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x0000C000 */
8180 #define QUADSPI_CCR_ABMODE             QUADSPI_CCR_ABMODE_Msk                  /*!< ABMODE[1:0]: Alternate Bytes Mode */
8181 #define QUADSPI_CCR_ABMODE_0           (0x1UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00004000 */
8182 #define QUADSPI_CCR_ABMODE_1           (0x2UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00008000 */
8183 #define QUADSPI_CCR_ABSIZE_Pos         (16U)
8184 #define QUADSPI_CCR_ABSIZE_Msk         (0x3UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00030000 */
8185 #define QUADSPI_CCR_ABSIZE             QUADSPI_CCR_ABSIZE_Msk                  /*!< ABSIZE[1:0]: Instruction Mode */
8186 #define QUADSPI_CCR_ABSIZE_0           (0x1UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00010000 */
8187 #define QUADSPI_CCR_ABSIZE_1           (0x2UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00020000 */
8188 #define QUADSPI_CCR_DCYC_Pos           (18U)
8189 #define QUADSPI_CCR_DCYC_Msk           (0x1FUL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x007C0000 */
8190 #define QUADSPI_CCR_DCYC               QUADSPI_CCR_DCYC_Msk                    /*!< DCYC[4:0]: Dummy Cycles */
8191 #define QUADSPI_CCR_DMODE_Pos          (24U)
8192 #define QUADSPI_CCR_DMODE_Msk          (0x3UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x03000000 */
8193 #define QUADSPI_CCR_DMODE              QUADSPI_CCR_DMODE_Msk                   /*!< DMODE[1:0]: Data Mode */
8194 #define QUADSPI_CCR_DMODE_0            (0x1UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x01000000 */
8195 #define QUADSPI_CCR_DMODE_1            (0x2UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x02000000 */
8196 #define QUADSPI_CCR_FMODE_Pos          (26U)
8197 #define QUADSPI_CCR_FMODE_Msk          (0x3UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x0C000000 */
8198 #define QUADSPI_CCR_FMODE              QUADSPI_CCR_FMODE_Msk                   /*!< FMODE[1:0]: Functional Mode */
8199 #define QUADSPI_CCR_FMODE_0            (0x1UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x04000000 */
8200 #define QUADSPI_CCR_FMODE_1            (0x2UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x08000000 */
8201 #define QUADSPI_CCR_SIOO_Pos           (28U)
8202 #define QUADSPI_CCR_SIOO_Msk           (0x1UL << QUADSPI_CCR_SIOO_Pos)         /*!< 0x10000000 */
8203 #define QUADSPI_CCR_SIOO               QUADSPI_CCR_SIOO_Msk                    /*!< SIOO: Send Instruction Only Once Mode */
8204 #define QUADSPI_CCR_DHHC_Pos           (30U)
8205 #define QUADSPI_CCR_DHHC_Msk           (0x1UL << QUADSPI_CCR_DHHC_Pos)         /*!< 0x40000000 */
8206 #define QUADSPI_CCR_DHHC               QUADSPI_CCR_DHHC_Msk                    /*!< DHHC: DDR hold */
8207 #define QUADSPI_CCR_DDRM_Pos           (31U)
8208 #define QUADSPI_CCR_DDRM_Msk           (0x1UL << QUADSPI_CCR_DDRM_Pos)         /*!< 0x80000000 */
8209 #define QUADSPI_CCR_DDRM               QUADSPI_CCR_DDRM_Msk                    /*!< DDRM: Double Data Rate Mode */
8210 
8211 /******************  Bit definition for QUADSPI_AR register  *******************/
8212 #define QUADSPI_AR_ADDRESS_Pos         (0U)
8213 #define QUADSPI_AR_ADDRESS_Msk         (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos)/*!< 0xFFFFFFFF */
8214 #define QUADSPI_AR_ADDRESS             QUADSPI_AR_ADDRESS_Msk                  /*!< ADDRESS[31:0]: Address */
8215 
8216 /******************  Bit definition for QUADSPI_ABR register  ******************/
8217 #define QUADSPI_ABR_ALTERNATE_Pos      (0U)
8218 #define QUADSPI_ABR_ALTERNATE_Msk      (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos)/*!< 0xFFFFFFFF */
8219 #define QUADSPI_ABR_ALTERNATE          QUADSPI_ABR_ALTERNATE_Msk               /*!< ALTERNATE[31:0]: Alternate Bytes */
8220 
8221 /******************  Bit definition for QUADSPI_DR register  *******************/
8222 #define QUADSPI_DR_DATA_Pos            (0U)
8223 #define QUADSPI_DR_DATA_Msk            (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)   /*!< 0xFFFFFFFF */
8224 #define QUADSPI_DR_DATA                QUADSPI_DR_DATA_Msk                     /*!< DATA[31:0]: Data */
8225 
8226 /******************  Bit definition for QUADSPI_PSMKR register  ****************/
8227 #define QUADSPI_PSMKR_MASK_Pos         (0U)
8228 #define QUADSPI_PSMKR_MASK_Msk         (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos)/*!< 0xFFFFFFFF */
8229 #define QUADSPI_PSMKR_MASK             QUADSPI_PSMKR_MASK_Msk                  /*!< MASK[31:0]: Status Mask */
8230 
8231 /******************  Bit definition for QUADSPI_PSMAR register  ****************/
8232 #define QUADSPI_PSMAR_MATCH_Pos        (0U)
8233 #define QUADSPI_PSMAR_MATCH_Msk        (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos)/*!< 0xFFFFFFFF */
8234 #define QUADSPI_PSMAR_MATCH            QUADSPI_PSMAR_MATCH_Msk                 /*!< MATCH[31:0]: Status Match */
8235 
8236 /******************  Bit definition for QUADSPI_PIR register  *****************/
8237 #define QUADSPI_PIR_INTERVAL_Pos       (0U)
8238 #define QUADSPI_PIR_INTERVAL_Msk       (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos)  /*!< 0x0000FFFF */
8239 #define QUADSPI_PIR_INTERVAL           QUADSPI_PIR_INTERVAL_Msk                /*!< INTERVAL[15:0]: Polling Interval */
8240 
8241 /******************  Bit definition for QUADSPI_LPTR register  *****************/
8242 #define QUADSPI_LPTR_TIMEOUT_Pos       (0U)
8243 #define QUADSPI_LPTR_TIMEOUT_Msk       (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos)  /*!< 0x0000FFFF */
8244 #define QUADSPI_LPTR_TIMEOUT           QUADSPI_LPTR_TIMEOUT_Msk                /*!< TIMEOUT[15:0]: Timeout period */
8245 
8246 /******************************************************************************/
8247 /*                                                                            */
8248 /*                         Reset and Clock Control                            */
8249 /*                                                                            */
8250 /******************************************************************************/
8251 /*
8252 * @brief Specific device feature definitions  (not present on all devices in the STM32G4 serie)
8253 */
8254 
8255 #define RCC_HSI48_SUPPORT
8256 #define RCC_PLLP_DIV_2_31_SUPPORT
8257 
8258 /********************  Bit definition for RCC_CR register  ********************/
8259 #define RCC_CR_HSION_Pos                     (8U)
8260 #define RCC_CR_HSION_Msk                     (0x1UL << RCC_CR_HSION_Pos)       /*!< 0x00000100 */
8261 #define RCC_CR_HSION                         RCC_CR_HSION_Msk                  /*!< Internal High Speed oscillator (HSI16) clock enable */
8262 #define RCC_CR_HSIKERON_Pos                  (9U)
8263 #define RCC_CR_HSIKERON_Msk                  (0x1UL << RCC_CR_HSIKERON_Pos)    /*!< 0x00000200 */
8264 #define RCC_CR_HSIKERON                      RCC_CR_HSIKERON_Msk               /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
8265 #define RCC_CR_HSIRDY_Pos                    (10U)
8266 #define RCC_CR_HSIRDY_Msk                    (0x1UL << RCC_CR_HSIRDY_Pos)      /*!< 0x00000400 */
8267 #define RCC_CR_HSIRDY                        RCC_CR_HSIRDY_Msk                 /*!< Internal High Speed oscillator (HSI16) clock ready flag */
8268 
8269 #define RCC_CR_HSEON_Pos                     (16U)
8270 #define RCC_CR_HSEON_Msk                     (0x1UL << RCC_CR_HSEON_Pos)       /*!< 0x00010000 */
8271 #define RCC_CR_HSEON                         RCC_CR_HSEON_Msk                  /*!< External High Speed oscillator (HSE) clock enable */
8272 #define RCC_CR_HSERDY_Pos                    (17U)
8273 #define RCC_CR_HSERDY_Msk                    (0x1UL << RCC_CR_HSERDY_Pos)      /*!< 0x00020000 */
8274 #define RCC_CR_HSERDY                        RCC_CR_HSERDY_Msk                 /*!< External High Speed oscillator (HSE) clock ready */
8275 #define RCC_CR_HSEBYP_Pos                    (18U)
8276 #define RCC_CR_HSEBYP_Msk                    (0x1UL << RCC_CR_HSEBYP_Pos)      /*!< 0x00040000 */
8277 #define RCC_CR_HSEBYP                        RCC_CR_HSEBYP_Msk                 /*!< External High Speed oscillator (HSE) clock bypass */
8278 #define RCC_CR_CSSON_Pos                     (19U)
8279 #define RCC_CR_CSSON_Msk                     (0x1UL << RCC_CR_CSSON_Pos)       /*!< 0x00080000 */
8280 #define RCC_CR_CSSON                         RCC_CR_CSSON_Msk                  /*!< HSE Clock Security System enable */
8281 
8282 #define RCC_CR_PLLON_Pos                     (24U)
8283 #define RCC_CR_PLLON_Msk                     (0x1UL << RCC_CR_PLLON_Pos)       /*!< 0x01000000 */
8284 #define RCC_CR_PLLON                         RCC_CR_PLLON_Msk                  /*!< System PLL clock enable */
8285 #define RCC_CR_PLLRDY_Pos                    (25U)
8286 #define RCC_CR_PLLRDY_Msk                    (0x1UL << RCC_CR_PLLRDY_Pos)      /*!< 0x02000000 */
8287 #define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< System PLL clock ready */
8288 
8289 /********************  Bit definition for RCC_ICSCR register  ***************/
8290 /*!< HSICAL configuration */
8291 #define RCC_ICSCR_HSICAL_Pos                 (16U)
8292 #define RCC_ICSCR_HSICAL_Msk                 (0xFFUL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00FF0000 */
8293 #define RCC_ICSCR_HSICAL                     RCC_ICSCR_HSICAL_Msk              /*!< HSICAL[7:0] bits */
8294 #define RCC_ICSCR_HSICAL_0                   (0x01UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00010000 */
8295 #define RCC_ICSCR_HSICAL_1                   (0x02UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00020000 */
8296 #define RCC_ICSCR_HSICAL_2                   (0x04UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00040000 */
8297 #define RCC_ICSCR_HSICAL_3                   (0x08UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00080000 */
8298 #define RCC_ICSCR_HSICAL_4                   (0x10UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00100000 */
8299 #define RCC_ICSCR_HSICAL_5                   (0x20UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00200000 */
8300 #define RCC_ICSCR_HSICAL_6                   (0x40UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00400000 */
8301 #define RCC_ICSCR_HSICAL_7                   (0x80UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00800000 */
8302 
8303 /*!< HSITRIM configuration */
8304 #define RCC_ICSCR_HSITRIM_Pos                (24U)
8305 #define RCC_ICSCR_HSITRIM_Msk                (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
8306 #define RCC_ICSCR_HSITRIM                    RCC_ICSCR_HSITRIM_Msk             /*!< HSITRIM[6:0] bits */
8307 #define RCC_ICSCR_HSITRIM_0                  (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
8308 #define RCC_ICSCR_HSITRIM_1                  (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
8309 #define RCC_ICSCR_HSITRIM_2                  (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
8310 #define RCC_ICSCR_HSITRIM_3                  (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
8311 #define RCC_ICSCR_HSITRIM_4                  (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
8312 #define RCC_ICSCR_HSITRIM_5                  (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
8313 #define RCC_ICSCR_HSITRIM_6                  (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */
8314 
8315 /********************  Bit definition for RCC_CFGR register  ******************/
8316 /*!< SW configuration */
8317 #define RCC_CFGR_SW_Pos                      (0U)
8318 #define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)        /*!< 0x00000003 */
8319 #define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
8320 #define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)        /*!< 0x00000001 */
8321 #define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)        /*!< 0x00000002 */
8322 
8323 #define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI16 oscillator selection as system clock */
8324 #define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE oscillator selection as system clock */
8325 #define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selection as system clock */
8326 
8327 /*!< SWS configuration */
8328 #define RCC_CFGR_SWS_Pos                     (2U)
8329 #define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)       /*!< 0x0000000C */
8330 #define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
8331 #define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000004 */
8332 #define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000008 */
8333 
8334 #define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI16 oscillator used as system clock */
8335 #define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
8336 #define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
8337 
8338 /*!< HPRE configuration */
8339 #define RCC_CFGR_HPRE_Pos                    (4U)
8340 #define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)      /*!< 0x000000F0 */
8341 #define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
8342 #define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000010 */
8343 #define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000020 */
8344 #define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000040 */
8345 #define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000080 */
8346 
8347 #define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
8348 #define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
8349 #define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
8350 #define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
8351 #define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
8352 #define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
8353 #define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
8354 #define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
8355 #define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
8356 
8357 /*!< PPRE1 configuration */
8358 #define RCC_CFGR_PPRE1_Pos                   (8U)
8359 #define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000700 */
8360 #define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB2 prescaler) */
8361 #define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000100 */
8362 #define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000200 */
8363 #define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000400 */
8364 
8365 #define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
8366 #define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
8367 #define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
8368 #define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
8369 #define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
8370 
8371 /*!< PPRE2 configuration */
8372 #define RCC_CFGR_PPRE2_Pos                   (11U)
8373 #define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00003800 */
8374 #define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
8375 #define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00000800 */
8376 #define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00001000 */
8377 #define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00002000 */
8378 
8379 #define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
8380 #define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
8381 #define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
8382 #define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
8383 #define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
8384 
8385 /*!< MCOSEL configuration */
8386 #define RCC_CFGR_MCOSEL_Pos                  (24U)
8387 #define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x0F000000 */
8388 #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCOSEL [3:0] bits (Clock output selection) */
8389 #define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x01000000 */
8390 #define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x02000000 */
8391 #define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x04000000 */
8392 #define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x08000000 */
8393 
8394 #define RCC_CFGR_MCOPRE_Pos                  (28U)
8395 #define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x70000000 */
8396 #define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
8397 #define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x10000000 */
8398 #define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x20000000 */
8399 #define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x40000000 */
8400 
8401 #define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
8402 #define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
8403 #define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
8404 #define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
8405 #define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
8406 
8407 /* Legacy aliases */
8408 #define RCC_CFGR_MCO_PRE                     RCC_CFGR_MCOPRE
8409 #define RCC_CFGR_MCO_PRE_1                   RCC_CFGR_MCOPRE_DIV1
8410 #define RCC_CFGR_MCO_PRE_2                   RCC_CFGR_MCOPRE_DIV2
8411 #define RCC_CFGR_MCO_PRE_4                   RCC_CFGR_MCOPRE_DIV4
8412 #define RCC_CFGR_MCO_PRE_8                   RCC_CFGR_MCOPRE_DIV8
8413 #define RCC_CFGR_MCO_PRE_16                  RCC_CFGR_MCOPRE_DIV16
8414 
8415 /********************  Bit definition for RCC_PLLCFGR register  ***************/
8416 #define RCC_PLLCFGR_PLLSRC_Pos               (0U)
8417 #define RCC_PLLCFGR_PLLSRC_Msk               (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
8418 #define RCC_PLLCFGR_PLLSRC                   RCC_PLLCFGR_PLLSRC_Msk
8419 #define RCC_PLLCFGR_PLLSRC_0                 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
8420 #define RCC_PLLCFGR_PLLSRC_1                 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
8421 
8422 #define RCC_PLLCFGR_PLLSRC_HSI_Pos           (1U)
8423 #define RCC_PLLCFGR_PLLSRC_HSI_Msk           (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos)/*!< 0x00000002 */
8424 #define RCC_PLLCFGR_PLLSRC_HSI               RCC_PLLCFGR_PLLSRC_HSI_Msk        /*!< HSI16 oscillator source clock selected */
8425 #define RCC_PLLCFGR_PLLSRC_HSE_Pos           (0U)
8426 #define RCC_PLLCFGR_PLLSRC_HSE_Msk           (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)/*!< 0x00000003 */
8427 #define RCC_PLLCFGR_PLLSRC_HSE               RCC_PLLCFGR_PLLSRC_HSE_Msk        /*!< HSE oscillator source clock selected */
8428 
8429 #define RCC_PLLCFGR_PLLM_Pos                 (4U)
8430 #define RCC_PLLCFGR_PLLM_Msk                 (0xFUL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x000000F0 */
8431 #define RCC_PLLCFGR_PLLM                     RCC_PLLCFGR_PLLM_Msk
8432 #define RCC_PLLCFGR_PLLM_0                   (0x1UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000010 */
8433 #define RCC_PLLCFGR_PLLM_1                   (0x2UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000020 */
8434 #define RCC_PLLCFGR_PLLM_2                   (0x4UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000040 */
8435 #define RCC_PLLCFGR_PLLM_3                   (0x8UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000080 */
8436 
8437 #define RCC_PLLCFGR_PLLN_Pos                 (8U)
8438 #define RCC_PLLCFGR_PLLN_Msk                 (0x7FUL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00007F00 */
8439 #define RCC_PLLCFGR_PLLN                     RCC_PLLCFGR_PLLN_Msk
8440 #define RCC_PLLCFGR_PLLN_0                   (0x01UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000100 */
8441 #define RCC_PLLCFGR_PLLN_1                   (0x02UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000200 */
8442 #define RCC_PLLCFGR_PLLN_2                   (0x04UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000400 */
8443 #define RCC_PLLCFGR_PLLN_3                   (0x08UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000800 */
8444 #define RCC_PLLCFGR_PLLN_4                   (0x10UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00001000 */
8445 #define RCC_PLLCFGR_PLLN_5                   (0x20UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00002000 */
8446 #define RCC_PLLCFGR_PLLN_6                   (0x40UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00004000 */
8447 
8448 #define RCC_PLLCFGR_PLLPEN_Pos               (16U)
8449 #define RCC_PLLCFGR_PLLPEN_Msk               (0x1UL << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
8450 #define RCC_PLLCFGR_PLLPEN                   RCC_PLLCFGR_PLLPEN_Msk
8451 #define RCC_PLLCFGR_PLLP_Pos                 (17U)
8452 #define RCC_PLLCFGR_PLLP_Msk                 (0x1UL << RCC_PLLCFGR_PLLP_Pos)   /*!< 0x00020000 */
8453 #define RCC_PLLCFGR_PLLP                     RCC_PLLCFGR_PLLP_Msk
8454 #define RCC_PLLCFGR_PLLQEN_Pos               (20U)
8455 #define RCC_PLLCFGR_PLLQEN_Msk               (0x1UL << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */
8456 #define RCC_PLLCFGR_PLLQEN                   RCC_PLLCFGR_PLLQEN_Msk
8457 
8458 #define RCC_PLLCFGR_PLLQ_Pos                 (21U)
8459 #define RCC_PLLCFGR_PLLQ_Msk                 (0x3UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00600000 */
8460 #define RCC_PLLCFGR_PLLQ                     RCC_PLLCFGR_PLLQ_Msk
8461 #define RCC_PLLCFGR_PLLQ_0                   (0x1UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00200000 */
8462 #define RCC_PLLCFGR_PLLQ_1                   (0x2UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00400000 */
8463 
8464 #define RCC_PLLCFGR_PLLREN_Pos               (24U)
8465 #define RCC_PLLCFGR_PLLREN_Msk               (0x1UL << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */
8466 #define RCC_PLLCFGR_PLLREN                   RCC_PLLCFGR_PLLREN_Msk
8467 #define RCC_PLLCFGR_PLLR_Pos                 (25U)
8468 #define RCC_PLLCFGR_PLLR_Msk                 (0x3UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x06000000 */
8469 #define RCC_PLLCFGR_PLLR                     RCC_PLLCFGR_PLLR_Msk
8470 #define RCC_PLLCFGR_PLLR_0                   (0x1UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x02000000 */
8471 #define RCC_PLLCFGR_PLLR_1                   (0x2UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x04000000 */
8472 
8473 #define RCC_PLLCFGR_PLLPDIV_Pos              (27U)
8474 #define RCC_PLLCFGR_PLLPDIV_Msk              (0x1FUL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0xF8000000 */
8475 #define RCC_PLLCFGR_PLLPDIV                  RCC_PLLCFGR_PLLPDIV_Msk
8476 #define RCC_PLLCFGR_PLLPDIV_0                (0x01UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x08000000 */
8477 #define RCC_PLLCFGR_PLLPDIV_1                (0x02UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x10000000 */
8478 #define RCC_PLLCFGR_PLLPDIV_2                (0x04UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x20000000 */
8479 #define RCC_PLLCFGR_PLLPDIV_3                (0x08UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x40000000 */
8480 #define RCC_PLLCFGR_PLLPDIV_4                (0x10UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x80000000 */
8481 
8482 /********************  Bit definition for RCC_CIER register  ******************/
8483 #define RCC_CIER_LSIRDYIE_Pos                (0U)
8484 #define RCC_CIER_LSIRDYIE_Msk                (0x1UL << RCC_CIER_LSIRDYIE_Pos)  /*!< 0x00000001 */
8485 #define RCC_CIER_LSIRDYIE                    RCC_CIER_LSIRDYIE_Msk
8486 #define RCC_CIER_LSERDYIE_Pos                (1U)
8487 #define RCC_CIER_LSERDYIE_Msk                (0x1UL << RCC_CIER_LSERDYIE_Pos)  /*!< 0x00000002 */
8488 #define RCC_CIER_LSERDYIE                    RCC_CIER_LSERDYIE_Msk
8489 #define RCC_CIER_HSIRDYIE_Pos                (3U)
8490 #define RCC_CIER_HSIRDYIE_Msk                (0x1UL << RCC_CIER_HSIRDYIE_Pos)  /*!< 0x00000008 */
8491 #define RCC_CIER_HSIRDYIE                    RCC_CIER_HSIRDYIE_Msk
8492 #define RCC_CIER_HSERDYIE_Pos                (4U)
8493 #define RCC_CIER_HSERDYIE_Msk                (0x1UL << RCC_CIER_HSERDYIE_Pos)  /*!< 0x00000010 */
8494 #define RCC_CIER_HSERDYIE                    RCC_CIER_HSERDYIE_Msk
8495 #define RCC_CIER_PLLRDYIE_Pos                (5U)
8496 #define RCC_CIER_PLLRDYIE_Msk                (0x1UL << RCC_CIER_PLLRDYIE_Pos)  /*!< 0x00000020 */
8497 #define RCC_CIER_PLLRDYIE                    RCC_CIER_PLLRDYIE_Msk
8498 #define RCC_CIER_LSECSSIE_Pos                (9U)
8499 #define RCC_CIER_LSECSSIE_Msk                (0x1UL << RCC_CIER_LSECSSIE_Pos)  /*!< 0x00000200 */
8500 #define RCC_CIER_LSECSSIE                    RCC_CIER_LSECSSIE_Msk
8501 #define RCC_CIER_HSI48RDYIE_Pos              (10U)
8502 #define RCC_CIER_HSI48RDYIE_Msk              (0x1UL << RCC_CIER_HSI48RDYIE_Pos)/*!< 0x00000400 */
8503 #define RCC_CIER_HSI48RDYIE                  RCC_CIER_HSI48RDYIE_Msk
8504 
8505 /********************  Bit definition for RCC_CIFR register  ******************/
8506 #define RCC_CIFR_LSIRDYF_Pos                 (0U)
8507 #define RCC_CIFR_LSIRDYF_Msk                 (0x1UL << RCC_CIFR_LSIRDYF_Pos)   /*!< 0x00000001 */
8508 #define RCC_CIFR_LSIRDYF                     RCC_CIFR_LSIRDYF_Msk
8509 #define RCC_CIFR_LSERDYF_Pos                 (1U)
8510 #define RCC_CIFR_LSERDYF_Msk                 (0x1UL << RCC_CIFR_LSERDYF_Pos)   /*!< 0x00000002 */
8511 #define RCC_CIFR_LSERDYF                     RCC_CIFR_LSERDYF_Msk
8512 #define RCC_CIFR_HSIRDYF_Pos                 (3U)
8513 #define RCC_CIFR_HSIRDYF_Msk                 (0x1UL << RCC_CIFR_HSIRDYF_Pos)   /*!< 0x00000008 */
8514 #define RCC_CIFR_HSIRDYF                     RCC_CIFR_HSIRDYF_Msk
8515 #define RCC_CIFR_HSERDYF_Pos                 (4U)
8516 #define RCC_CIFR_HSERDYF_Msk                 (0x1UL << RCC_CIFR_HSERDYF_Pos)   /*!< 0x00000010 */
8517 #define RCC_CIFR_HSERDYF                     RCC_CIFR_HSERDYF_Msk
8518 #define RCC_CIFR_PLLRDYF_Pos                 (5U)
8519 #define RCC_CIFR_PLLRDYF_Msk                 (0x1UL << RCC_CIFR_PLLRDYF_Pos)   /*!< 0x00000020 */
8520 #define RCC_CIFR_PLLRDYF                     RCC_CIFR_PLLRDYF_Msk
8521 #define RCC_CIFR_CSSF_Pos                    (8U)
8522 #define RCC_CIFR_CSSF_Msk                    (0x1UL << RCC_CIFR_CSSF_Pos)      /*!< 0x00000100 */
8523 #define RCC_CIFR_CSSF                        RCC_CIFR_CSSF_Msk
8524 #define RCC_CIFR_LSECSSF_Pos                 (9U)
8525 #define RCC_CIFR_LSECSSF_Msk                 (0x1UL << RCC_CIFR_LSECSSF_Pos)   /*!< 0x00000200 */
8526 #define RCC_CIFR_LSECSSF                     RCC_CIFR_LSECSSF_Msk
8527 #define RCC_CIFR_HSI48RDYF_Pos               (10U)
8528 #define RCC_CIFR_HSI48RDYF_Msk               (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000400 */
8529 #define RCC_CIFR_HSI48RDYF                   RCC_CIFR_HSI48RDYF_Msk
8530 
8531 /********************  Bit definition for RCC_CICR register  ******************/
8532 #define RCC_CICR_LSIRDYC_Pos                 (0U)
8533 #define RCC_CICR_LSIRDYC_Msk                 (0x1UL << RCC_CICR_LSIRDYC_Pos)   /*!< 0x00000001 */
8534 #define RCC_CICR_LSIRDYC                     RCC_CICR_LSIRDYC_Msk
8535 #define RCC_CICR_LSERDYC_Pos                 (1U)
8536 #define RCC_CICR_LSERDYC_Msk                 (0x1UL << RCC_CICR_LSERDYC_Pos)   /*!< 0x00000002 */
8537 #define RCC_CICR_LSERDYC                     RCC_CICR_LSERDYC_Msk
8538 #define RCC_CICR_HSIRDYC_Pos                 (3U)
8539 #define RCC_CICR_HSIRDYC_Msk                 (0x1UL << RCC_CICR_HSIRDYC_Pos)   /*!< 0x00000008 */
8540 #define RCC_CICR_HSIRDYC                     RCC_CICR_HSIRDYC_Msk
8541 #define RCC_CICR_HSERDYC_Pos                 (4U)
8542 #define RCC_CICR_HSERDYC_Msk                 (0x1UL << RCC_CICR_HSERDYC_Pos)   /*!< 0x00000010 */
8543 #define RCC_CICR_HSERDYC                     RCC_CICR_HSERDYC_Msk
8544 #define RCC_CICR_PLLRDYC_Pos                 (5U)
8545 #define RCC_CICR_PLLRDYC_Msk                 (0x1UL << RCC_CICR_PLLRDYC_Pos)   /*!< 0x00000020 */
8546 #define RCC_CICR_PLLRDYC                     RCC_CICR_PLLRDYC_Msk
8547 #define RCC_CICR_CSSC_Pos                    (8U)
8548 #define RCC_CICR_CSSC_Msk                    (0x1UL << RCC_CICR_CSSC_Pos)      /*!< 0x00000100 */
8549 #define RCC_CICR_CSSC                        RCC_CICR_CSSC_Msk
8550 #define RCC_CICR_LSECSSC_Pos                 (9U)
8551 #define RCC_CICR_LSECSSC_Msk                 (0x1UL << RCC_CICR_LSECSSC_Pos)   /*!< 0x00000200 */
8552 #define RCC_CICR_LSECSSC                     RCC_CICR_LSECSSC_Msk
8553 #define RCC_CICR_HSI48RDYC_Pos               (10U)
8554 #define RCC_CICR_HSI48RDYC_Msk               (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000400 */
8555 #define RCC_CICR_HSI48RDYC                   RCC_CICR_HSI48RDYC_Msk
8556 
8557 /********************  Bit definition for RCC_AHB1RSTR register  **************/
8558 #define RCC_AHB1RSTR_DMA1RST_Pos             (0U)
8559 #define RCC_AHB1RSTR_DMA1RST_Msk             (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)/*!< 0x00000001 */
8560 #define RCC_AHB1RSTR_DMA1RST                 RCC_AHB1RSTR_DMA1RST_Msk
8561 #define RCC_AHB1RSTR_DMA2RST_Pos             (1U)
8562 #define RCC_AHB1RSTR_DMA2RST_Msk             (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)/*!< 0x00000002 */
8563 #define RCC_AHB1RSTR_DMA2RST                 RCC_AHB1RSTR_DMA2RST_Msk
8564 #define RCC_AHB1RSTR_DMAMUX1RST_Pos          (2U)
8565 #define RCC_AHB1RSTR_DMAMUX1RST_Msk          (0x1UL << RCC_AHB1RSTR_DMAMUX1RST_Pos)/*!< 0x00000004 */
8566 #define RCC_AHB1RSTR_DMAMUX1RST              RCC_AHB1RSTR_DMAMUX1RST_Msk
8567 #define RCC_AHB1RSTR_CORDICRST_Pos           (3U)
8568 #define RCC_AHB1RSTR_CORDICRST_Msk           (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos)/*!< 0x00000008 */
8569 #define RCC_AHB1RSTR_CORDICRST               RCC_AHB1RSTR_CORDICRST_Msk
8570 #define RCC_AHB1RSTR_FMACRST_Pos             (4U)
8571 #define RCC_AHB1RSTR_FMACRST_Msk             (0x1UL << RCC_AHB1RSTR_FMACRST_Pos)  /*!< 0x00000010 */
8572 #define RCC_AHB1RSTR_FMACRST                 RCC_AHB1RSTR_FMACRST_Msk
8573 #define RCC_AHB1RSTR_FLASHRST_Pos            (8U)
8574 #define RCC_AHB1RSTR_FLASHRST_Msk            (0x1UL << RCC_AHB1RSTR_FLASHRST_Pos)/*!< 0x00000100 */
8575 #define RCC_AHB1RSTR_FLASHRST                RCC_AHB1RSTR_FLASHRST_Msk
8576 #define RCC_AHB1RSTR_CRCRST_Pos              (12U)
8577 #define RCC_AHB1RSTR_CRCRST_Msk              (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)/*!< 0x00001000 */
8578 #define RCC_AHB1RSTR_CRCRST                  RCC_AHB1RSTR_CRCRST_Msk
8579 
8580 /********************  Bit definition for RCC_AHB2RSTR register  **************/
8581 #define RCC_AHB2RSTR_GPIOARST_Pos            (0U)
8582 #define RCC_AHB2RSTR_GPIOARST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)/*!< 0x00000001 */
8583 #define RCC_AHB2RSTR_GPIOARST                RCC_AHB2RSTR_GPIOARST_Msk
8584 #define RCC_AHB2RSTR_GPIOBRST_Pos            (1U)
8585 #define RCC_AHB2RSTR_GPIOBRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)/*!< 0x00000002 */
8586 #define RCC_AHB2RSTR_GPIOBRST                RCC_AHB2RSTR_GPIOBRST_Msk
8587 #define RCC_AHB2RSTR_GPIOCRST_Pos            (2U)
8588 #define RCC_AHB2RSTR_GPIOCRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)/*!< 0x00000004 */
8589 #define RCC_AHB2RSTR_GPIOCRST                RCC_AHB2RSTR_GPIOCRST_Msk
8590 #define RCC_AHB2RSTR_GPIODRST_Pos            (3U)
8591 #define RCC_AHB2RSTR_GPIODRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos)/*!< 0x00000008 */
8592 #define RCC_AHB2RSTR_GPIODRST                RCC_AHB2RSTR_GPIODRST_Msk
8593 #define RCC_AHB2RSTR_GPIOERST_Pos            (4U)
8594 #define RCC_AHB2RSTR_GPIOERST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos)/*!< 0x00000010 */
8595 #define RCC_AHB2RSTR_GPIOERST                RCC_AHB2RSTR_GPIOERST_Msk
8596 #define RCC_AHB2RSTR_GPIOFRST_Pos            (5U)
8597 #define RCC_AHB2RSTR_GPIOFRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOFRST_Pos)/*!< 0x00000020 */
8598 #define RCC_AHB2RSTR_GPIOFRST                RCC_AHB2RSTR_GPIOFRST_Msk
8599 #define RCC_AHB2RSTR_GPIOGRST_Pos            (6U)
8600 #define RCC_AHB2RSTR_GPIOGRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOGRST_Pos)/*!< 0x00000040 */
8601 #define RCC_AHB2RSTR_GPIOGRST                RCC_AHB2RSTR_GPIOGRST_Msk
8602 #define RCC_AHB2RSTR_ADC12RST_Pos            (13U)
8603 #define RCC_AHB2RSTR_ADC12RST_Msk            (0x1UL << RCC_AHB2RSTR_ADC12RST_Pos)/*!< 0x00002000 */
8604 #define RCC_AHB2RSTR_ADC12RST                RCC_AHB2RSTR_ADC12RST_Msk
8605 #define RCC_AHB2RSTR_ADC345RST_Pos           (14U)
8606 #define RCC_AHB2RSTR_ADC345RST_Msk           (0x1UL << RCC_AHB2RSTR_ADC345RST_Pos)/*!< 0x00004000 */
8607 #define RCC_AHB2RSTR_ADC345RST               RCC_AHB2RSTR_ADC345RST_Msk
8608 #define RCC_AHB2RSTR_DAC1RST_Pos             (16U)
8609 #define RCC_AHB2RSTR_DAC1RST_Msk             (0x1UL << RCC_AHB2RSTR_DAC1RST_Pos)/*!< 0x00010000 */
8610 #define RCC_AHB2RSTR_DAC1RST                 RCC_AHB2RSTR_DAC1RST_Msk
8611 #define RCC_AHB2RSTR_DAC2RST_Pos             (17U)
8612 #define RCC_AHB2RSTR_DAC2RST_Msk             (0x1UL << RCC_AHB2RSTR_DAC2RST_Pos)/*!< 0x00020000 */
8613 #define RCC_AHB2RSTR_DAC2RST                 RCC_AHB2RSTR_DAC2RST_Msk
8614 #define RCC_AHB2RSTR_DAC3RST_Pos             (18U)
8615 #define RCC_AHB2RSTR_DAC3RST_Msk             (0x1UL << RCC_AHB2RSTR_DAC3RST_Pos)/*!< 0x00040000 */
8616 #define RCC_AHB2RSTR_DAC3RST                 RCC_AHB2RSTR_DAC3RST_Msk
8617 #define RCC_AHB2RSTR_DAC4RST_Pos             (19U)
8618 #define RCC_AHB2RSTR_DAC4RST_Msk             (0x1UL << RCC_AHB2RSTR_DAC4RST_Pos)/*!< 0x00080000 */
8619 #define RCC_AHB2RSTR_DAC4RST                 RCC_AHB2RSTR_DAC4RST_Msk
8620 #define RCC_AHB2RSTR_RNGRST_Pos              (26U)
8621 #define RCC_AHB2RSTR_RNGRST_Msk              (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)/*!< 0x04000000 */
8622 #define RCC_AHB2RSTR_RNGRST                  RCC_AHB2RSTR_RNGRST_Msk
8623 
8624 /********************  Bit definition for RCC_AHB3RSTR register  **************/
8625 #define RCC_AHB3RSTR_FMCRST_Pos              (0U)
8626 #define RCC_AHB3RSTR_FMCRST_Msk              (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)/*!< 0x00000001 */
8627 #define RCC_AHB3RSTR_FMCRST                  RCC_AHB3RSTR_FMCRST_Msk
8628 #define RCC_AHB3RSTR_QSPIRST_Pos             (8U)
8629 #define RCC_AHB3RSTR_QSPIRST_Msk             (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)/*!< 0x00000100 */
8630 #define RCC_AHB3RSTR_QSPIRST                 RCC_AHB3RSTR_QSPIRST_Msk
8631 
8632 /********************  Bit definition for RCC_APB1RSTR1 register  **************/
8633 #define RCC_APB1RSTR1_TIM2RST_Pos            (0U)
8634 #define RCC_APB1RSTR1_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)/*!< 0x00000001 */
8635 #define RCC_APB1RSTR1_TIM2RST                RCC_APB1RSTR1_TIM2RST_Msk
8636 #define RCC_APB1RSTR1_TIM3RST_Pos            (1U)
8637 #define RCC_APB1RSTR1_TIM3RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos)/*!< 0x00000002 */
8638 #define RCC_APB1RSTR1_TIM3RST                RCC_APB1RSTR1_TIM3RST_Msk
8639 #define RCC_APB1RSTR1_TIM4RST_Pos            (2U)
8640 #define RCC_APB1RSTR1_TIM4RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)/*!< 0x00000004 */
8641 #define RCC_APB1RSTR1_TIM4RST                RCC_APB1RSTR1_TIM4RST_Msk
8642 #define RCC_APB1RSTR1_TIM5RST_Pos            (3U)
8643 #define RCC_APB1RSTR1_TIM5RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos)/*!< 0x00000008 */
8644 #define RCC_APB1RSTR1_TIM5RST                RCC_APB1RSTR1_TIM5RST_Msk
8645 #define RCC_APB1RSTR1_TIM6RST_Pos            (4U)
8646 #define RCC_APB1RSTR1_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)/*!< 0x00000010 */
8647 #define RCC_APB1RSTR1_TIM6RST                RCC_APB1RSTR1_TIM6RST_Msk
8648 #define RCC_APB1RSTR1_TIM7RST_Pos            (5U)
8649 #define RCC_APB1RSTR1_TIM7RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos)/*!< 0x00000020 */
8650 #define RCC_APB1RSTR1_TIM7RST                RCC_APB1RSTR1_TIM7RST_Msk
8651 #define RCC_APB1RSTR1_CRSRST_Pos             (8U)
8652 #define RCC_APB1RSTR1_CRSRST_Msk             (0x1UL << RCC_APB1RSTR1_CRSRST_Pos)/*!< 0x00000100 */
8653 #define RCC_APB1RSTR1_CRSRST                 RCC_APB1RSTR1_CRSRST_Msk
8654 #define RCC_APB1RSTR1_SPI2RST_Pos            (14U)
8655 #define RCC_APB1RSTR1_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)/*!< 0x00004000 */
8656 #define RCC_APB1RSTR1_SPI2RST                RCC_APB1RSTR1_SPI2RST_Msk
8657 #define RCC_APB1RSTR1_SPI3RST_Pos            (15U)
8658 #define RCC_APB1RSTR1_SPI3RST_Msk            (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos)/*!< 0x00008000 */
8659 #define RCC_APB1RSTR1_SPI3RST                RCC_APB1RSTR1_SPI3RST_Msk
8660 #define RCC_APB1RSTR1_USART2RST_Pos          (17U)
8661 #define RCC_APB1RSTR1_USART2RST_Msk          (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */
8662 #define RCC_APB1RSTR1_USART2RST              RCC_APB1RSTR1_USART2RST_Msk
8663 #define RCC_APB1RSTR1_USART3RST_Pos          (18U)
8664 #define RCC_APB1RSTR1_USART3RST_Msk          (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)/*!< 0x00040000 */
8665 #define RCC_APB1RSTR1_USART3RST              RCC_APB1RSTR1_USART3RST_Msk
8666 #define RCC_APB1RSTR1_UART4RST_Pos           (19U)
8667 #define RCC_APB1RSTR1_UART4RST_Msk           (0x1UL << RCC_APB1RSTR1_UART4RST_Pos)/*!< 0x00080000 */
8668 #define RCC_APB1RSTR1_UART4RST               RCC_APB1RSTR1_UART4RST_Msk
8669 #define RCC_APB1RSTR1_UART5RST_Pos           (20U)
8670 #define RCC_APB1RSTR1_UART5RST_Msk           (0x1UL << RCC_APB1RSTR1_UART5RST_Pos)/*!< 0x00100000 */
8671 #define RCC_APB1RSTR1_UART5RST               RCC_APB1RSTR1_UART5RST_Msk
8672 #define RCC_APB1RSTR1_I2C1RST_Pos            (21U)
8673 #define RCC_APB1RSTR1_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)/*!< 0x00200000 */
8674 #define RCC_APB1RSTR1_I2C1RST                RCC_APB1RSTR1_I2C1RST_Msk
8675 #define RCC_APB1RSTR1_I2C2RST_Pos            (22U)
8676 #define RCC_APB1RSTR1_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)/*!< 0x00400000 */
8677 #define RCC_APB1RSTR1_I2C2RST                RCC_APB1RSTR1_I2C2RST_Msk
8678 #define RCC_APB1RSTR1_USBRST_Pos             (23U)
8679 #define RCC_APB1RSTR1_USBRST_Msk             (0x1UL << RCC_APB1RSTR1_USBRST_Pos)/*!< 0x00800000 */
8680 #define RCC_APB1RSTR1_USBRST                 RCC_APB1RSTR1_USBRST_Msk
8681 #define RCC_APB1RSTR1_FDCANRST_Pos           (25U)
8682 #define RCC_APB1RSTR1_FDCANRST_Msk           (0x1UL << RCC_APB1RSTR1_FDCANRST_Pos)/*!< 0x02000000 */
8683 #define RCC_APB1RSTR1_FDCANRST               RCC_APB1RSTR1_FDCANRST_Msk
8684 #define RCC_APB1RSTR1_PWRRST_Pos             (28U)
8685 #define RCC_APB1RSTR1_PWRRST_Msk             (0x1UL << RCC_APB1RSTR1_PWRRST_Pos)/*!< 0x10000000 */
8686 #define RCC_APB1RSTR1_PWRRST                 RCC_APB1RSTR1_PWRRST_Msk
8687 #define RCC_APB1RSTR1_I2C3RST_Pos            (30U)
8688 #define RCC_APB1RSTR1_I2C3RST_Msk            (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)/*!< 0x40000000 */
8689 #define RCC_APB1RSTR1_I2C3RST                RCC_APB1RSTR1_I2C3RST_Msk
8690 #define RCC_APB1RSTR1_LPTIM1RST_Pos          (31U)
8691 #define RCC_APB1RSTR1_LPTIM1RST_Msk          (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x80000000 */
8692 #define RCC_APB1RSTR1_LPTIM1RST              RCC_APB1RSTR1_LPTIM1RST_Msk
8693 
8694 /********************  Bit definition for RCC_APB1RSTR2 register  **************/
8695 #define RCC_APB1RSTR2_LPUART1RST_Pos         (0U)
8696 #define RCC_APB1RSTR2_LPUART1RST_Msk         (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos)/*!< 0x00000001 */
8697 #define RCC_APB1RSTR2_LPUART1RST             RCC_APB1RSTR2_LPUART1RST_Msk
8698 #define RCC_APB1RSTR2_I2C4RST_Pos            (1U)
8699 #define RCC_APB1RSTR2_I2C4RST_Msk            (0x1UL << RCC_APB1RSTR2_I2C4RST_Pos)/*!< 0x00000002 */
8700 #define RCC_APB1RSTR2_I2C4RST                RCC_APB1RSTR2_I2C4RST_Msk
8701 #define RCC_APB1RSTR2_UCPD1RST_Pos           (8U)
8702 #define RCC_APB1RSTR2_UCPD1RST_Msk           (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos)/*!< 0x00000100 */
8703 #define RCC_APB1RSTR2_UCPD1RST               RCC_APB1RSTR2_UCPD1RST_Msk
8704 
8705 /********************  Bit definition for RCC_APB2RSTR register  **************/
8706 #define RCC_APB2RSTR_SYSCFGRST_Pos           (0U)
8707 #define RCC_APB2RSTR_SYSCFGRST_Msk           (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)/*!< 0x00000001 */
8708 #define RCC_APB2RSTR_SYSCFGRST               RCC_APB2RSTR_SYSCFGRST_Msk
8709 #define RCC_APB2RSTR_TIM1RST_Pos             (11U)
8710 #define RCC_APB2RSTR_TIM1RST_Msk             (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)/*!< 0x00000800 */
8711 #define RCC_APB2RSTR_TIM1RST                 RCC_APB2RSTR_TIM1RST_Msk
8712 #define RCC_APB2RSTR_SPI1RST_Pos             (12U)
8713 #define RCC_APB2RSTR_SPI1RST_Msk             (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)/*!< 0x00001000 */
8714 #define RCC_APB2RSTR_SPI1RST                 RCC_APB2RSTR_SPI1RST_Msk
8715 #define RCC_APB2RSTR_TIM8RST_Pos             (13U)
8716 #define RCC_APB2RSTR_TIM8RST_Msk             (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)/*!< 0x00002000 */
8717 #define RCC_APB2RSTR_TIM8RST                 RCC_APB2RSTR_TIM8RST_Msk
8718 #define RCC_APB2RSTR_USART1RST_Pos           (14U)
8719 #define RCC_APB2RSTR_USART1RST_Msk           (0x1UL << RCC_APB2RSTR_USART1RST_Pos)/*!< 0x00004000 */
8720 #define RCC_APB2RSTR_USART1RST               RCC_APB2RSTR_USART1RST_Msk
8721 #define RCC_APB2RSTR_SPI4RST_Pos             (15U)
8722 #define RCC_APB2RSTR_SPI4RST_Msk             (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)/*!< 0x00008000 */
8723 #define RCC_APB2RSTR_SPI4RST                 RCC_APB2RSTR_SPI4RST_Msk
8724 #define RCC_APB2RSTR_TIM15RST_Pos            (16U)
8725 #define RCC_APB2RSTR_TIM15RST_Msk            (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)/*!< 0x00010000 */
8726 #define RCC_APB2RSTR_TIM15RST                RCC_APB2RSTR_TIM15RST_Msk
8727 #define RCC_APB2RSTR_TIM16RST_Pos            (17U)
8728 #define RCC_APB2RSTR_TIM16RST_Msk            (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)/*!< 0x00020000 */
8729 #define RCC_APB2RSTR_TIM16RST                RCC_APB2RSTR_TIM16RST_Msk
8730 #define RCC_APB2RSTR_TIM17RST_Pos            (18U)
8731 #define RCC_APB2RSTR_TIM17RST_Msk            (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)/*!< 0x00040000 */
8732 #define RCC_APB2RSTR_TIM17RST                RCC_APB2RSTR_TIM17RST_Msk
8733 #define RCC_APB2RSTR_TIM20RST_Pos            (20U)
8734 #define RCC_APB2RSTR_TIM20RST_Msk            (0x1UL << RCC_APB2RSTR_TIM20RST_Pos)/*!< 0x00100000 */
8735 #define RCC_APB2RSTR_TIM20RST                RCC_APB2RSTR_TIM20RST_Msk
8736 #define RCC_APB2RSTR_SAI1RST_Pos             (21U)
8737 #define RCC_APB2RSTR_SAI1RST_Msk             (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)/*!< 0x00200000 */
8738 #define RCC_APB2RSTR_SAI1RST                 RCC_APB2RSTR_SAI1RST_Msk
8739 
8740 /********************  Bit definition for RCC_AHB1ENR register  ***************/
8741 #define RCC_AHB1ENR_DMA1EN_Pos               (0U)
8742 #define RCC_AHB1ENR_DMA1EN_Msk               (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
8743 #define RCC_AHB1ENR_DMA1EN                   RCC_AHB1ENR_DMA1EN_Msk
8744 #define RCC_AHB1ENR_DMA2EN_Pos               (1U)
8745 #define RCC_AHB1ENR_DMA2EN_Msk               (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
8746 #define RCC_AHB1ENR_DMA2EN                   RCC_AHB1ENR_DMA2EN_Msk
8747 #define RCC_AHB1ENR_DMAMUX1EN_Pos            (2U)
8748 #define RCC_AHB1ENR_DMAMUX1EN_Msk            (0x1UL << RCC_AHB1ENR_DMAMUX1EN_Pos)/*!< 0x00000004 */
8749 #define RCC_AHB1ENR_DMAMUX1EN                RCC_AHB1ENR_DMAMUX1EN_Msk
8750 #define RCC_AHB1ENR_CORDICEN_Pos             (3U)
8751 #define RCC_AHB1ENR_CORDICEN_Msk             (0x1UL << RCC_AHB1ENR_CORDICEN_Pos)/*!< 0x00000008 */
8752 #define RCC_AHB1ENR_CORDICEN                 RCC_AHB1ENR_CORDICEN_Msk
8753 #define RCC_AHB1ENR_FMACEN_Pos               (4U)
8754 #define RCC_AHB1ENR_FMACEN_Msk               (0x1UL << RCC_AHB1ENR_FMACEN_Pos)  /*!< 0x00000010 */
8755 #define RCC_AHB1ENR_FMACEN                   RCC_AHB1ENR_FMACEN_Msk
8756 #define RCC_AHB1ENR_FLASHEN_Pos              (8U)
8757 #define RCC_AHB1ENR_FLASHEN_Msk              (0x1UL << RCC_AHB1ENR_FLASHEN_Pos)/*!< 0x00000100 */
8758 #define RCC_AHB1ENR_FLASHEN                  RCC_AHB1ENR_FLASHEN_Msk
8759 #define RCC_AHB1ENR_CRCEN_Pos                (12U)
8760 #define RCC_AHB1ENR_CRCEN_Msk                (0x1UL << RCC_AHB1ENR_CRCEN_Pos)  /*!< 0x00001000 */
8761 #define RCC_AHB1ENR_CRCEN                    RCC_AHB1ENR_CRCEN_Msk
8762 
8763 /********************  Bit definition for RCC_AHB2ENR register  ***************/
8764 #define RCC_AHB2ENR_GPIOAEN_Pos              (0U)
8765 #define RCC_AHB2ENR_GPIOAEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos)/*!< 0x00000001 */
8766 #define RCC_AHB2ENR_GPIOAEN                  RCC_AHB2ENR_GPIOAEN_Msk
8767 #define RCC_AHB2ENR_GPIOBEN_Pos              (1U)
8768 #define RCC_AHB2ENR_GPIOBEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos)/*!< 0x00000002 */
8769 #define RCC_AHB2ENR_GPIOBEN                  RCC_AHB2ENR_GPIOBEN_Msk
8770 #define RCC_AHB2ENR_GPIOCEN_Pos              (2U)
8771 #define RCC_AHB2ENR_GPIOCEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos)/*!< 0x00000004 */
8772 #define RCC_AHB2ENR_GPIOCEN                  RCC_AHB2ENR_GPIOCEN_Msk
8773 #define RCC_AHB2ENR_GPIODEN_Pos              (3U)
8774 #define RCC_AHB2ENR_GPIODEN_Msk              (0x1UL << RCC_AHB2ENR_GPIODEN_Pos)/*!< 0x00000008 */
8775 #define RCC_AHB2ENR_GPIODEN                  RCC_AHB2ENR_GPIODEN_Msk
8776 #define RCC_AHB2ENR_GPIOEEN_Pos              (4U)
8777 #define RCC_AHB2ENR_GPIOEEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos)/*!< 0x00000010 */
8778 #define RCC_AHB2ENR_GPIOEEN                  RCC_AHB2ENR_GPIOEEN_Msk
8779 #define RCC_AHB2ENR_GPIOFEN_Pos              (5U)
8780 #define RCC_AHB2ENR_GPIOFEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOFEN_Pos)/*!< 0x00000020 */
8781 #define RCC_AHB2ENR_GPIOFEN                  RCC_AHB2ENR_GPIOFEN_Msk
8782 #define RCC_AHB2ENR_GPIOGEN_Pos              (6U)
8783 #define RCC_AHB2ENR_GPIOGEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOGEN_Pos)/*!< 0x00000040 */
8784 #define RCC_AHB2ENR_GPIOGEN                  RCC_AHB2ENR_GPIOGEN_Msk
8785 #define RCC_AHB2ENR_ADC12EN_Pos              (13U)
8786 #define RCC_AHB2ENR_ADC12EN_Msk              (0x1UL << RCC_AHB2ENR_ADC12EN_Pos)  /*!< 0x00002000 */
8787 #define RCC_AHB2ENR_ADC12EN                  RCC_AHB2ENR_ADC12EN_Msk
8788 #define RCC_AHB2ENR_ADC345EN_Pos             (14U)
8789 #define RCC_AHB2ENR_ADC345EN_Msk             (0x1UL << RCC_AHB2ENR_ADC345EN_Pos)  /*!< 0x00004000 */
8790 #define RCC_AHB2ENR_ADC345EN                 RCC_AHB2ENR_ADC345EN_Msk
8791 #define RCC_AHB2ENR_DAC1EN_Pos               (16U)
8792 #define RCC_AHB2ENR_DAC1EN_Msk               (0x1UL << RCC_AHB2ENR_DAC1EN_Pos)  /*!< 0x00010000 */
8793 #define RCC_AHB2ENR_DAC1EN                   RCC_AHB2ENR_DAC1EN_Msk
8794 #define RCC_AHB2ENR_DAC2EN_Pos               (17U)
8795 #define RCC_AHB2ENR_DAC2EN_Msk               (0x1UL << RCC_AHB2ENR_DAC2EN_Pos)  /*!< 0x00020000 */
8796 #define RCC_AHB2ENR_DAC2EN                   RCC_AHB2ENR_DAC2EN_Msk
8797 #define RCC_AHB2ENR_DAC3EN_Pos               (18U)
8798 #define RCC_AHB2ENR_DAC3EN_Msk               (0x1UL << RCC_AHB2ENR_DAC3EN_Pos)  /*!< 0x00040000 */
8799 #define RCC_AHB2ENR_DAC3EN                   RCC_AHB2ENR_DAC3EN_Msk
8800 #define RCC_AHB2ENR_DAC4EN_Pos               (19U)
8801 #define RCC_AHB2ENR_DAC4EN_Msk               (0x1UL << RCC_AHB2ENR_DAC4EN_Pos)  /*!< 0x00080000 */
8802 #define RCC_AHB2ENR_DAC4EN                   RCC_AHB2ENR_DAC4EN_Msk
8803 #define RCC_AHB2ENR_RNGEN_Pos                (26U)
8804 #define RCC_AHB2ENR_RNGEN_Msk                (0x1UL << RCC_AHB2ENR_RNGEN_Pos)  /*!< 0x04000000 */
8805 #define RCC_AHB2ENR_RNGEN                    RCC_AHB2ENR_RNGEN_Msk
8806 
8807 /********************  Bit definition for RCC_AHB3ENR register  ***************/
8808 #define RCC_AHB3ENR_FMCEN_Pos                (0U)
8809 #define RCC_AHB3ENR_FMCEN_Msk                (0x1UL << RCC_AHB3ENR_FMCEN_Pos)  /*!< 0x00000001 */
8810 #define RCC_AHB3ENR_FMCEN                    RCC_AHB3ENR_FMCEN_Msk
8811 #define RCC_AHB3ENR_QSPIEN_Pos               (8U)
8812 #define RCC_AHB3ENR_QSPIEN_Msk               (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)  /*!< 0x00000100 */
8813 #define RCC_AHB3ENR_QSPIEN                   RCC_AHB3ENR_QSPIEN_Msk
8814 
8815 /********************  Bit definition for RCC_APB1ENR1 register  ***************/
8816 #define RCC_APB1ENR1_TIM2EN_Pos              (0U)
8817 #define RCC_APB1ENR1_TIM2EN_Msk              (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)/*!< 0x00000001 */
8818 #define RCC_APB1ENR1_TIM2EN                  RCC_APB1ENR1_TIM2EN_Msk
8819 #define RCC_APB1ENR1_TIM3EN_Pos              (1U)
8820 #define RCC_APB1ENR1_TIM3EN_Msk              (0x1UL << RCC_APB1ENR1_TIM3EN_Pos)/*!< 0x00000002 */
8821 #define RCC_APB1ENR1_TIM3EN                  RCC_APB1ENR1_TIM3EN_Msk
8822 #define RCC_APB1ENR1_TIM4EN_Pos              (2U)
8823 #define RCC_APB1ENR1_TIM4EN_Msk              (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)/*!< 0x00000004 */
8824 #define RCC_APB1ENR1_TIM4EN                  RCC_APB1ENR1_TIM4EN_Msk
8825 #define RCC_APB1ENR1_TIM5EN_Pos              (3U)
8826 #define RCC_APB1ENR1_TIM5EN_Msk              (0x1UL << RCC_APB1ENR1_TIM5EN_Pos)/*!< 0x00000008 */
8827 #define RCC_APB1ENR1_TIM5EN                  RCC_APB1ENR1_TIM5EN_Msk
8828 #define RCC_APB1ENR1_TIM6EN_Pos              (4U)
8829 #define RCC_APB1ENR1_TIM6EN_Msk              (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)/*!< 0x00000010 */
8830 #define RCC_APB1ENR1_TIM6EN                  RCC_APB1ENR1_TIM6EN_Msk
8831 #define RCC_APB1ENR1_TIM7EN_Pos              (5U)
8832 #define RCC_APB1ENR1_TIM7EN_Msk              (0x1UL << RCC_APB1ENR1_TIM7EN_Pos)/*!< 0x00000020 */
8833 #define RCC_APB1ENR1_TIM7EN                  RCC_APB1ENR1_TIM7EN_Msk
8834 #define RCC_APB1ENR1_CRSEN_Pos               (8U)
8835 #define RCC_APB1ENR1_CRSEN_Msk               (0x1UL << RCC_APB1ENR1_CRSEN_Pos) /*!< 0x00000100 */
8836 #define RCC_APB1ENR1_CRSEN                   RCC_APB1ENR1_CRSEN_Msk
8837 #define RCC_APB1ENR1_RTCAPBEN_Pos            (10U)
8838 #define RCC_APB1ENR1_RTCAPBEN_Msk            (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos)/*!< 0x00000400 */
8839 #define RCC_APB1ENR1_RTCAPBEN                RCC_APB1ENR1_RTCAPBEN_Msk
8840 #define RCC_APB1ENR1_WWDGEN_Pos              (11U)
8841 #define RCC_APB1ENR1_WWDGEN_Msk              (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)/*!< 0x00000800 */
8842 #define RCC_APB1ENR1_WWDGEN                  RCC_APB1ENR1_WWDGEN_Msk
8843 #define RCC_APB1ENR1_SPI2EN_Pos              (14U)
8844 #define RCC_APB1ENR1_SPI2EN_Msk              (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)/*!< 0x00004000 */
8845 #define RCC_APB1ENR1_SPI2EN                  RCC_APB1ENR1_SPI2EN_Msk
8846 #define RCC_APB1ENR1_SPI3EN_Pos              (15U)
8847 #define RCC_APB1ENR1_SPI3EN_Msk              (0x1UL << RCC_APB1ENR1_SPI3EN_Pos)/*!< 0x00008000 */
8848 #define RCC_APB1ENR1_SPI3EN                  RCC_APB1ENR1_SPI3EN_Msk
8849 #define RCC_APB1ENR1_USART2EN_Pos            (17U)
8850 #define RCC_APB1ENR1_USART2EN_Msk            (0x1UL << RCC_APB1ENR1_USART2EN_Pos)/*!< 0x00020000 */
8851 #define RCC_APB1ENR1_USART2EN                RCC_APB1ENR1_USART2EN_Msk
8852 #define RCC_APB1ENR1_USART3EN_Pos            (18U)
8853 #define RCC_APB1ENR1_USART3EN_Msk            (0x1UL << RCC_APB1ENR1_USART3EN_Pos)/*!< 0x00040000 */
8854 #define RCC_APB1ENR1_USART3EN                RCC_APB1ENR1_USART3EN_Msk
8855 #define RCC_APB1ENR1_UART4EN_Pos             (19U)
8856 #define RCC_APB1ENR1_UART4EN_Msk             (0x1UL << RCC_APB1ENR1_UART4EN_Pos)/*!< 0x00080000 */
8857 #define RCC_APB1ENR1_UART4EN                 RCC_APB1ENR1_UART4EN_Msk
8858 #define RCC_APB1ENR1_UART5EN_Pos             (20U)
8859 #define RCC_APB1ENR1_UART5EN_Msk             (0x1UL << RCC_APB1ENR1_UART5EN_Pos)/*!< 0x00100000 */
8860 #define RCC_APB1ENR1_UART5EN                 RCC_APB1ENR1_UART5EN_Msk
8861 #define RCC_APB1ENR1_I2C1EN_Pos              (21U)
8862 #define RCC_APB1ENR1_I2C1EN_Msk              (0x1UL << RCC_APB1ENR1_I2C1EN_Pos)/*!< 0x00200000 */
8863 #define RCC_APB1ENR1_I2C1EN                  RCC_APB1ENR1_I2C1EN_Msk
8864 #define RCC_APB1ENR1_I2C2EN_Pos              (22U)
8865 #define RCC_APB1ENR1_I2C2EN_Msk              (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)/*!< 0x00400000 */
8866 #define RCC_APB1ENR1_I2C2EN                  RCC_APB1ENR1_I2C2EN_Msk
8867 #define RCC_APB1ENR1_USBEN_Pos               (23U)
8868 #define RCC_APB1ENR1_USBEN_Msk               (0x1UL << RCC_APB1ENR1_USBEN_Pos)/*!< 0x00800000 */
8869 #define RCC_APB1ENR1_USBEN                   RCC_APB1ENR1_USBEN_Msk
8870 #define RCC_APB1ENR1_FDCANEN_Pos             (25U)
8871 #define RCC_APB1ENR1_FDCANEN_Msk             (0x1UL << RCC_APB1ENR1_FDCANEN_Pos)/*!< 0x02000000 */
8872 #define RCC_APB1ENR1_FDCANEN                 RCC_APB1ENR1_FDCANEN_Msk
8873 #define RCC_APB1ENR1_PWREN_Pos               (28U)
8874 #define RCC_APB1ENR1_PWREN_Msk               (0x1UL << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */
8875 #define RCC_APB1ENR1_PWREN                   RCC_APB1ENR1_PWREN_Msk
8876 #define RCC_APB1ENR1_I2C3EN_Pos              (30U)
8877 #define RCC_APB1ENR1_I2C3EN_Msk              (0x1UL << RCC_APB1ENR1_I2C3EN_Pos)/*!< 0x40000000 */
8878 #define RCC_APB1ENR1_I2C3EN                  RCC_APB1ENR1_I2C3EN_Msk
8879 #define RCC_APB1ENR1_LPTIM1EN_Pos            (31U)
8880 #define RCC_APB1ENR1_LPTIM1EN_Msk            (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)/*!< 0x80000000 */
8881 #define RCC_APB1ENR1_LPTIM1EN                RCC_APB1ENR1_LPTIM1EN_Msk
8882 
8883 /********************  Bit definition for RCC_APB1RSTR2 register  **************/
8884 #define RCC_APB1ENR2_LPUART1EN_Pos           (0U)
8885 #define RCC_APB1ENR2_LPUART1EN_Msk           (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos)/*!< 0x00000001 */
8886 #define RCC_APB1ENR2_LPUART1EN               RCC_APB1ENR2_LPUART1EN_Msk
8887 #define RCC_APB1ENR2_I2C4EN_Pos              (1U)
8888 #define RCC_APB1ENR2_I2C4EN_Msk              (0x1UL << RCC_APB1ENR2_I2C4EN_Pos)/*!< 0x00000002 */
8889 #define RCC_APB1ENR2_I2C4EN                  RCC_APB1ENR2_I2C4EN_Msk
8890 #define RCC_APB1ENR2_UCPD1EN_Pos             (8U)
8891 #define RCC_APB1ENR2_UCPD1EN_Msk             (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos)/*!< 0x00000100 */
8892 #define RCC_APB1ENR2_UCPD1EN                 RCC_APB1ENR2_UCPD1EN_Msk
8893 
8894 /********************  Bit definition for RCC_APB2ENR register  ***************/
8895 #define RCC_APB2ENR_SYSCFGEN_Pos             (0U)
8896 #define RCC_APB2ENR_SYSCFGEN_Msk             (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)/*!< 0x00000001 */
8897 #define RCC_APB2ENR_SYSCFGEN                 RCC_APB2ENR_SYSCFGEN_Msk
8898 #define RCC_APB2ENR_TIM1EN_Pos               (11U)
8899 #define RCC_APB2ENR_TIM1EN_Msk               (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
8900 #define RCC_APB2ENR_TIM1EN                   RCC_APB2ENR_TIM1EN_Msk
8901 #define RCC_APB2ENR_SPI1EN_Pos               (12U)
8902 #define RCC_APB2ENR_SPI1EN_Msk               (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
8903 #define RCC_APB2ENR_SPI1EN                   RCC_APB2ENR_SPI1EN_Msk
8904 #define RCC_APB2ENR_TIM8EN_Pos               (13U)
8905 #define RCC_APB2ENR_TIM8EN_Msk               (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */
8906 #define RCC_APB2ENR_TIM8EN                   RCC_APB2ENR_TIM8EN_Msk
8907 #define RCC_APB2ENR_USART1EN_Pos             (14U)
8908 #define RCC_APB2ENR_USART1EN_Msk             (0x1UL << RCC_APB2ENR_USART1EN_Pos)/*!< 0x00004000 */
8909 #define RCC_APB2ENR_USART1EN                 RCC_APB2ENR_USART1EN_Msk
8910 #define RCC_APB2ENR_SPI4EN_Pos               (15U)
8911 #define RCC_APB2ENR_SPI4EN_Msk               (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00008000 */
8912 #define RCC_APB2ENR_SPI4EN                   RCC_APB2ENR_SPI4EN_Msk
8913 #define RCC_APB2ENR_TIM15EN_Pos              (16U)
8914 #define RCC_APB2ENR_TIM15EN_Msk              (0x1UL << RCC_APB2ENR_TIM15EN_Pos)/*!< 0x00010000 */
8915 #define RCC_APB2ENR_TIM15EN                  RCC_APB2ENR_TIM15EN_Msk
8916 #define RCC_APB2ENR_TIM16EN_Pos              (17U)
8917 #define RCC_APB2ENR_TIM16EN_Msk              (0x1UL << RCC_APB2ENR_TIM16EN_Pos)/*!< 0x00020000 */
8918 #define RCC_APB2ENR_TIM16EN                  RCC_APB2ENR_TIM16EN_Msk
8919 #define RCC_APB2ENR_TIM17EN_Pos              (18U)
8920 #define RCC_APB2ENR_TIM17EN_Msk              (0x1UL << RCC_APB2ENR_TIM17EN_Pos)/*!< 0x00040000 */
8921 #define RCC_APB2ENR_TIM17EN                  RCC_APB2ENR_TIM17EN_Msk
8922 #define RCC_APB2ENR_TIM20EN_Pos              (20U)
8923 #define RCC_APB2ENR_TIM20EN_Msk              (0x1UL << RCC_APB2ENR_TIM20EN_Pos)/*!< 0x00100000 */
8924 #define RCC_APB2ENR_TIM20EN                  RCC_APB2ENR_TIM20EN_Msk
8925 #define RCC_APB2ENR_SAI1EN_Pos               (21U)
8926 #define RCC_APB2ENR_SAI1EN_Msk               (0x1UL << RCC_APB2ENR_SAI1EN_Pos)/*!< 0x00200000 */
8927 #define RCC_APB2ENR_SAI1EN                   RCC_APB2ENR_SAI1EN_Msk
8928 
8929 /********************  Bit definition for RCC_AHB1SMENR register  ***************/
8930 #define RCC_AHB1SMENR_DMA1SMEN_Pos           (0U)
8931 #define RCC_AHB1SMENR_DMA1SMEN_Msk           (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos)/*!< 0x00000001 */
8932 #define RCC_AHB1SMENR_DMA1SMEN               RCC_AHB1SMENR_DMA1SMEN_Msk
8933 #define RCC_AHB1SMENR_DMA2SMEN_Pos           (1U)
8934 #define RCC_AHB1SMENR_DMA2SMEN_Msk           (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos)/*!< 0x00000002 */
8935 #define RCC_AHB1SMENR_DMA2SMEN               RCC_AHB1SMENR_DMA2SMEN_Msk
8936 #define RCC_AHB1SMENR_DMAMUX1SMEN_Pos        (2U)
8937 #define RCC_AHB1SMENR_DMAMUX1SMEN_Msk        (0x1UL << RCC_AHB1SMENR_DMAMUX1SMEN_Pos)/*!< 0x00000004 */
8938 #define RCC_AHB1SMENR_DMAMUX1SMEN            RCC_AHB1SMENR_DMAMUX1SMEN_Msk
8939 #define RCC_AHB1SMENR_CORDICSMEN_Pos         (3U)
8940 #define RCC_AHB1SMENR_CORDICSMEN_Msk         (0x1UL << RCC_AHB1SMENR_CORDICSMEN_Pos)/*!< 0x00000008 */
8941 #define RCC_AHB1SMENR_CORDICSMEN             RCC_AHB1SMENR_CORDICSMEN_Msk
8942 #define RCC_AHB1SMENR_FMACSMEN_Pos           (4U)
8943 #define RCC_AHB1SMENR_FMACSMEN_Msk           (0x1UL << RCC_AHB1SMENR_FMACSMEN_Pos)  /*!< 0x00000010 */
8944 #define RCC_AHB1SMENR_FMACSMEN               RCC_AHB1SMENR_FMACSMEN_Msk
8945 #define RCC_AHB1SMENR_FLASHSMEN_Pos          (8U)
8946 #define RCC_AHB1SMENR_FLASHSMEN_Msk          (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos)/*!< 0x00000100 */
8947 #define RCC_AHB1SMENR_FLASHSMEN              RCC_AHB1SMENR_FLASHSMEN_Msk
8948 #define RCC_AHB1SMENR_SRAM1SMEN_Pos          (9U)
8949 #define RCC_AHB1SMENR_SRAM1SMEN_Msk          (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos)/*!< 0x00000200 */
8950 #define RCC_AHB1SMENR_SRAM1SMEN              RCC_AHB1SMENR_SRAM1SMEN_Msk
8951 #define RCC_AHB1SMENR_CRCSMEN_Pos            (12U)
8952 #define RCC_AHB1SMENR_CRCSMEN_Msk            (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)/*!< 0x00001000 */
8953 #define RCC_AHB1SMENR_CRCSMEN                RCC_AHB1SMENR_CRCSMEN_Msk
8954 
8955 /********************  Bit definition for RCC_AHB2SMENR register  *************/
8956 #define RCC_AHB2SMENR_GPIOASMEN_Pos          (0U)
8957 #define RCC_AHB2SMENR_GPIOASMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos)/*!< 0x00000001 */
8958 #define RCC_AHB2SMENR_GPIOASMEN              RCC_AHB2SMENR_GPIOASMEN_Msk
8959 #define RCC_AHB2SMENR_GPIOBSMEN_Pos          (1U)
8960 #define RCC_AHB2SMENR_GPIOBSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos)/*!< 0x00000002 */
8961 #define RCC_AHB2SMENR_GPIOBSMEN              RCC_AHB2SMENR_GPIOBSMEN_Msk
8962 #define RCC_AHB2SMENR_GPIOCSMEN_Pos          (2U)
8963 #define RCC_AHB2SMENR_GPIOCSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos)/*!< 0x00000004 */
8964 #define RCC_AHB2SMENR_GPIOCSMEN              RCC_AHB2SMENR_GPIOCSMEN_Msk
8965 #define RCC_AHB2SMENR_GPIODSMEN_Pos          (3U)
8966 #define RCC_AHB2SMENR_GPIODSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIODSMEN_Pos)/*!< 0x00000008 */
8967 #define RCC_AHB2SMENR_GPIODSMEN              RCC_AHB2SMENR_GPIODSMEN_Msk
8968 #define RCC_AHB2SMENR_GPIOESMEN_Pos          (4U)
8969 #define RCC_AHB2SMENR_GPIOESMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOESMEN_Pos)/*!< 0x00000010 */
8970 #define RCC_AHB2SMENR_GPIOESMEN              RCC_AHB2SMENR_GPIOESMEN_Msk
8971 #define RCC_AHB2SMENR_GPIOFSMEN_Pos          (5U)
8972 #define RCC_AHB2SMENR_GPIOFSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOFSMEN_Pos)/*!< 0x00000020 */
8973 #define RCC_AHB2SMENR_GPIOFSMEN              RCC_AHB2SMENR_GPIOFSMEN_Msk
8974 #define RCC_AHB2SMENR_GPIOGSMEN_Pos          (6U)
8975 #define RCC_AHB2SMENR_GPIOGSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOGSMEN_Pos)/*!< 0x00000040 */
8976 #define RCC_AHB2SMENR_GPIOGSMEN              RCC_AHB2SMENR_GPIOGSMEN_Msk
8977 #define RCC_AHB2SMENR_CCMSRAMSMEN_Pos        (9U)
8978 #define RCC_AHB2SMENR_CCMSRAMSMEN_Msk        (0x1UL << RCC_AHB2SMENR_CCMSRAMSMEN_Pos)  /*!< 0x00000200 */
8979 #define RCC_AHB2SMENR_CCMSRAMSMEN            RCC_AHB2SMENR_CCMSRAMSMEN_Msk
8980 #define RCC_AHB2SMENR_SRAM2SMEN_Pos          (10U)
8981 #define RCC_AHB2SMENR_SRAM2SMEN_Msk          (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos)/*!< 0x00000400 */
8982 #define RCC_AHB2SMENR_SRAM2SMEN              RCC_AHB2SMENR_SRAM2SMEN_Msk
8983 #define RCC_AHB2SMENR_ADC12SMEN_Pos          (13U)
8984 #define RCC_AHB2SMENR_ADC12SMEN_Msk          (0x1UL << RCC_AHB2SMENR_ADC12SMEN_Pos)/*!< 0x00002000 */
8985 #define RCC_AHB2SMENR_ADC12SMEN              RCC_AHB2SMENR_ADC12SMEN_Msk
8986 #define RCC_AHB2SMENR_ADC345SMEN_Pos         (14U)
8987 #define RCC_AHB2SMENR_ADC345SMEN_Msk         (0x1UL << RCC_AHB2SMENR_ADC345SMEN_Pos)/*!< 0x00004000 */
8988 #define RCC_AHB2SMENR_ADC345SMEN             RCC_AHB2SMENR_ADC345SMEN_Msk
8989 #define RCC_AHB2SMENR_DAC1SMEN_Pos           (16U)
8990 #define RCC_AHB2SMENR_DAC1SMEN_Msk           (0x1UL << RCC_AHB2SMENR_DAC1SMEN_Pos)/*!< 0x00010000 */
8991 #define RCC_AHB2SMENR_DAC1SMEN               RCC_AHB2SMENR_DAC1SMEN_Msk
8992 #define RCC_AHB2SMENR_DAC2SMEN_Pos           (17U)
8993 #define RCC_AHB2SMENR_DAC2SMEN_Msk           (0x1UL << RCC_AHB2SMENR_DAC2SMEN_Pos)/*!< 0x00020000 */
8994 #define RCC_AHB2SMENR_DAC2SMEN               RCC_AHB2SMENR_DAC2SMEN_Msk
8995 #define RCC_AHB2SMENR_DAC3SMEN_Pos           (18U)
8996 #define RCC_AHB2SMENR_DAC3SMEN_Msk           (0x1UL << RCC_AHB2SMENR_DAC3SMEN_Pos)/*!< 0x00040000 */
8997 #define RCC_AHB2SMENR_DAC3SMEN               RCC_AHB2SMENR_DAC3SMEN_Msk
8998 #define RCC_AHB2SMENR_DAC4SMEN_Pos           (19U)
8999 #define RCC_AHB2SMENR_DAC4SMEN_Msk           (0x1UL << RCC_AHB2SMENR_DAC4SMEN_Pos)/*!< 0x00080000 */
9000 #define RCC_AHB2SMENR_DAC4SMEN               RCC_AHB2SMENR_DAC4SMEN_Msk
9001 #define RCC_AHB2SMENR_RNGSMEN_Pos            (26U)
9002 #define RCC_AHB2SMENR_RNGSMEN_Msk            (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos)/*!< 0x04000000 */
9003 #define RCC_AHB2SMENR_RNGSMEN                RCC_AHB2SMENR_RNGSMEN_Msk
9004 
9005 /********************  Bit definition for RCC_AHB3SMENR register  *************/
9006 #define RCC_AHB3SMENR_FMCSMEN_Pos            (0U)
9007 #define RCC_AHB3SMENR_FMCSMEN_Msk            (0x1UL << RCC_AHB3SMENR_FMCSMEN_Pos)/*!< 0x00000001 */
9008 #define RCC_AHB3SMENR_FMCSMEN                RCC_AHB3SMENR_FMCSMEN_Msk
9009 #define RCC_AHB3SMENR_QSPISMEN_Pos           (8U)
9010 #define RCC_AHB3SMENR_QSPISMEN_Msk           (0x1UL << RCC_AHB3SMENR_QSPISMEN_Pos)/*!< 0x00000100 */
9011 #define RCC_AHB3SMENR_QSPISMEN               RCC_AHB3SMENR_QSPISMEN_Msk
9012 
9013 /********************  Bit definition for RCC_APB1SMENR1 register  *************/
9014 #define RCC_APB1SMENR1_TIM2SMEN_Pos          (0U)
9015 #define RCC_APB1SMENR1_TIM2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)/*!< 0x00000001 */
9016 #define RCC_APB1SMENR1_TIM2SMEN              RCC_APB1SMENR1_TIM2SMEN_Msk
9017 #define RCC_APB1SMENR1_TIM3SMEN_Pos          (1U)
9018 #define RCC_APB1SMENR1_TIM3SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos)/*!< 0x00000002 */
9019 #define RCC_APB1SMENR1_TIM3SMEN              RCC_APB1SMENR1_TIM3SMEN_Msk
9020 #define RCC_APB1SMENR1_TIM4SMEN_Pos          (2U)
9021 #define RCC_APB1SMENR1_TIM4SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos)/*!< 0x00000004 */
9022 #define RCC_APB1SMENR1_TIM4SMEN              RCC_APB1SMENR1_TIM4SMEN_Msk
9023 #define RCC_APB1SMENR1_TIM5SMEN_Pos          (3U)
9024 #define RCC_APB1SMENR1_TIM5SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM5SMEN_Pos)/*!< 0x00000008 */
9025 #define RCC_APB1SMENR1_TIM5SMEN              RCC_APB1SMENR1_TIM5SMEN_Msk
9026 #define RCC_APB1SMENR1_TIM6SMEN_Pos          (4U)
9027 #define RCC_APB1SMENR1_TIM6SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos)/*!< 0x00000010 */
9028 #define RCC_APB1SMENR1_TIM6SMEN              RCC_APB1SMENR1_TIM6SMEN_Msk
9029 #define RCC_APB1SMENR1_TIM7SMEN_Pos          (5U)
9030 #define RCC_APB1SMENR1_TIM7SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM7SMEN_Pos)/*!< 0x00000020 */
9031 #define RCC_APB1SMENR1_TIM7SMEN              RCC_APB1SMENR1_TIM7SMEN_Msk
9032 #define RCC_APB1SMENR1_CRSSMEN_Pos           (8U)
9033 #define RCC_APB1SMENR1_CRSSMEN_Msk           (0x1UL << RCC_APB1SMENR1_CRSSMEN_Pos)/*!< 0x00000100 */
9034 #define RCC_APB1SMENR1_CRSSMEN               RCC_APB1SMENR1_CRSSMEN_Msk
9035 #define RCC_APB1SMENR1_RTCAPBSMEN_Pos        (10U)
9036 #define RCC_APB1SMENR1_RTCAPBSMEN_Msk        (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos)/*!< 0x00000400 */
9037 #define RCC_APB1SMENR1_RTCAPBSMEN            RCC_APB1SMENR1_RTCAPBSMEN_Msk
9038 #define RCC_APB1SMENR1_WWDGSMEN_Pos          (11U)
9039 #define RCC_APB1SMENR1_WWDGSMEN_Msk          (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)/*!< 0x00000800 */
9040 #define RCC_APB1SMENR1_WWDGSMEN              RCC_APB1SMENR1_WWDGSMEN_Msk
9041 #define RCC_APB1SMENR1_SPI2SMEN_Pos          (14U)
9042 #define RCC_APB1SMENR1_SPI2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)/*!< 0x00004000 */
9043 #define RCC_APB1SMENR1_SPI2SMEN              RCC_APB1SMENR1_SPI2SMEN_Msk
9044 #define RCC_APB1SMENR1_SPI3SMEN_Pos          (15U)
9045 #define RCC_APB1SMENR1_SPI3SMEN_Msk          (0x1UL << RCC_APB1SMENR1_SPI3SMEN_Pos)/*!< 0x00008000 */
9046 #define RCC_APB1SMENR1_SPI3SMEN              RCC_APB1SMENR1_SPI3SMEN_Msk
9047 #define RCC_APB1SMENR1_USART2SMEN_Pos        (17U)
9048 #define RCC_APB1SMENR1_USART2SMEN_Msk        (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)/*!< 0x00020000 */
9049 #define RCC_APB1SMENR1_USART2SMEN            RCC_APB1SMENR1_USART2SMEN_Msk
9050 #define RCC_APB1SMENR1_USART3SMEN_Pos        (18U)
9051 #define RCC_APB1SMENR1_USART3SMEN_Msk        (0x1UL << RCC_APB1SMENR1_USART3SMEN_Pos)/*!< 0x00040000 */
9052 #define RCC_APB1SMENR1_USART3SMEN            RCC_APB1SMENR1_USART3SMEN_Msk
9053 #define RCC_APB1SMENR1_UART4SMEN_Pos         (19U)
9054 #define RCC_APB1SMENR1_UART4SMEN_Msk         (0x1UL << RCC_APB1SMENR1_UART4SMEN_Pos)/*!< 0x00080000 */
9055 #define RCC_APB1SMENR1_UART4SMEN             RCC_APB1SMENR1_UART4SMEN_Msk
9056 #define RCC_APB1SMENR1_UART5SMEN_Pos         (20U)
9057 #define RCC_APB1SMENR1_UART5SMEN_Msk         (0x1UL << RCC_APB1SMENR1_UART5SMEN_Pos)/*!< 0x00100000 */
9058 #define RCC_APB1SMENR1_UART5SMEN             RCC_APB1SMENR1_UART5SMEN_Msk
9059 #define RCC_APB1SMENR1_I2C1SMEN_Pos          (21U)
9060 #define RCC_APB1SMENR1_I2C1SMEN_Msk          (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)/*!< 0x00200000 */
9061 #define RCC_APB1SMENR1_I2C1SMEN              RCC_APB1SMENR1_I2C1SMEN_Msk
9062 #define RCC_APB1SMENR1_I2C2SMEN_Pos          (22U)
9063 #define RCC_APB1SMENR1_I2C2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)/*!< 0x00400000 */
9064 #define RCC_APB1SMENR1_I2C2SMEN              RCC_APB1SMENR1_I2C2SMEN_Msk
9065 #define RCC_APB1SMENR1_USBSMEN_Pos           (23U)
9066 #define RCC_APB1SMENR1_USBSMEN_Msk           (0x1UL << RCC_APB1SMENR1_USBSMEN_Pos)/*!< 0x00800000 */
9067 #define RCC_APB1SMENR1_USBSMEN               RCC_APB1SMENR1_USBSMEN_Msk
9068 #define RCC_APB1SMENR1_FDCANSMEN_Pos         (25U)
9069 #define RCC_APB1SMENR1_FDCANSMEN_Msk         (0x1UL << RCC_APB1SMENR1_FDCANSMEN_Pos)/*!< 0x02000000 */
9070 #define RCC_APB1SMENR1_FDCANSMEN             RCC_APB1SMENR1_FDCANSMEN_Msk
9071 #define RCC_APB1SMENR1_PWRSMEN_Pos           (28U)
9072 #define RCC_APB1SMENR1_PWRSMEN_Msk           (0x1UL << RCC_APB1SMENR1_PWRSMEN_Pos)/*!< 0x10000000 */
9073 #define RCC_APB1SMENR1_PWRSMEN               RCC_APB1SMENR1_PWRSMEN_Msk
9074 #define RCC_APB1SMENR1_I2C3SMEN_Pos          (30U)
9075 #define RCC_APB1SMENR1_I2C3SMEN_Msk          (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos)/*!< 0x40000000 */
9076 #define RCC_APB1SMENR1_I2C3SMEN              RCC_APB1SMENR1_I2C3SMEN_Msk
9077 #define RCC_APB1SMENR1_LPTIM1SMEN_Pos        (31U)
9078 #define RCC_APB1SMENR1_LPTIM1SMEN_Msk        (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos)/*!< 0x80000000 */
9079 #define RCC_APB1SMENR1_LPTIM1SMEN            RCC_APB1SMENR1_LPTIM1SMEN_Msk
9080 
9081 /********************  Bit definition for RCC_APB1SMENR2 register  *************/
9082 #define RCC_APB1SMENR2_LPUART1SMEN_Pos       (0U)
9083 #define RCC_APB1SMENR2_LPUART1SMEN_Msk       (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos)/*!< 0x00000001 */
9084 #define RCC_APB1SMENR2_LPUART1SMEN           RCC_APB1SMENR2_LPUART1SMEN_Msk
9085 #define RCC_APB1SMENR2_I2C4SMEN_Pos          (1U)
9086 #define RCC_APB1SMENR2_I2C4SMEN_Msk          (0x1UL << RCC_APB1SMENR2_I2C4SMEN_Pos)/*!< 0x00000002 */
9087 #define RCC_APB1SMENR2_I2C4SMEN              RCC_APB1SMENR2_I2C4SMEN_Msk
9088 #define RCC_APB1SMENR2_UCPD1SMEN_Pos         (8U)
9089 #define RCC_APB1SMENR2_UCPD1SMEN_Msk         (0x1UL << RCC_APB1SMENR2_UCPD1SMEN_Pos)/*!< 0x00000100 */
9090 #define RCC_APB1SMENR2_UCPD1SMEN             RCC_APB1SMENR2_UCPD1SMEN_Msk
9091 
9092 /********************  Bit definition for RCC_APB2SMENR register  *************/
9093 #define RCC_APB2SMENR_SYSCFGSMEN_Pos         (0U)
9094 #define RCC_APB2SMENR_SYSCFGSMEN_Msk         (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos)/*!< 0x00000001 */
9095 #define RCC_APB2SMENR_SYSCFGSMEN             RCC_APB2SMENR_SYSCFGSMEN_Msk
9096 #define RCC_APB2SMENR_TIM1SMEN_Pos           (11U)
9097 #define RCC_APB2SMENR_TIM1SMEN_Msk           (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)/*!< 0x00000800 */
9098 #define RCC_APB2SMENR_TIM1SMEN               RCC_APB2SMENR_TIM1SMEN_Msk
9099 #define RCC_APB2SMENR_SPI1SMEN_Pos           (12U)
9100 #define RCC_APB2SMENR_SPI1SMEN_Msk           (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)/*!< 0x00001000 */
9101 #define RCC_APB2SMENR_SPI1SMEN               RCC_APB2SMENR_SPI1SMEN_Msk
9102 #define RCC_APB2SMENR_TIM8SMEN_Pos           (13U)
9103 #define RCC_APB2SMENR_TIM8SMEN_Msk           (0x1UL << RCC_APB2SMENR_TIM8SMEN_Pos)/*!< 0x00002000 */
9104 #define RCC_APB2SMENR_TIM8SMEN               RCC_APB2SMENR_TIM8SMEN_Msk
9105 #define RCC_APB2SMENR_USART1SMEN_Pos         (14U)
9106 #define RCC_APB2SMENR_USART1SMEN_Msk         (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)/*!< 0x00004000 */
9107 #define RCC_APB2SMENR_USART1SMEN             RCC_APB2SMENR_USART1SMEN_Msk
9108 #define RCC_APB2SMENR_SPI4SMEN_Pos           (15U)
9109 #define RCC_APB2SMENR_SPI4SMEN_Msk           (0x1UL << RCC_APB2SMENR_SPI4SMEN_Pos)/*!< 0x00008000 */
9110 #define RCC_APB2SMENR_SPI4SMEN               RCC_APB2SMENR_SPI4SMEN_Msk
9111 #define RCC_APB2SMENR_TIM15SMEN_Pos          (16U)
9112 #define RCC_APB2SMENR_TIM15SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos)/*!< 0x00010000 */
9113 #define RCC_APB2SMENR_TIM15SMEN              RCC_APB2SMENR_TIM15SMEN_Msk
9114 #define RCC_APB2SMENR_TIM16SMEN_Pos          (17U)
9115 #define RCC_APB2SMENR_TIM16SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)/*!< 0x00020000 */
9116 #define RCC_APB2SMENR_TIM16SMEN              RCC_APB2SMENR_TIM16SMEN_Msk
9117 #define RCC_APB2SMENR_TIM17SMEN_Pos          (18U)
9118 #define RCC_APB2SMENR_TIM17SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */
9119 #define RCC_APB2SMENR_TIM17SMEN              RCC_APB2SMENR_TIM17SMEN_Msk
9120 #define RCC_APB2SMENR_TIM20SMEN_Pos          (20U)
9121 #define RCC_APB2SMENR_TIM20SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM20SMEN_Pos)/*!< 0x00100000 */
9122 #define RCC_APB2SMENR_TIM20SMEN              RCC_APB2SMENR_TIM20SMEN_Msk
9123 #define RCC_APB2SMENR_SAI1SMEN_Pos           (21U)
9124 #define RCC_APB2SMENR_SAI1SMEN_Msk           (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos)/*!< 0x00200000 */
9125 #define RCC_APB2SMENR_SAI1SMEN               RCC_APB2SMENR_SAI1SMEN_Msk
9126 
9127 /********************  Bit definition for RCC_CCIPR register  ******************/
9128 #define RCC_CCIPR_USART1SEL_Pos              (0U)
9129 #define RCC_CCIPR_USART1SEL_Msk              (0x3UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000003 */
9130 #define RCC_CCIPR_USART1SEL                  RCC_CCIPR_USART1SEL_Msk
9131 #define RCC_CCIPR_USART1SEL_0                (0x1UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000001 */
9132 #define RCC_CCIPR_USART1SEL_1                (0x2UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000002 */
9133 
9134 #define RCC_CCIPR_USART2SEL_Pos              (2U)
9135 #define RCC_CCIPR_USART2SEL_Msk              (0x3UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x0000000C */
9136 #define RCC_CCIPR_USART2SEL                  RCC_CCIPR_USART2SEL_Msk
9137 #define RCC_CCIPR_USART2SEL_0                (0x1UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x00000004 */
9138 #define RCC_CCIPR_USART2SEL_1                (0x2UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x00000008 */
9139 
9140 #define RCC_CCIPR_USART3SEL_Pos              (4U)
9141 #define RCC_CCIPR_USART3SEL_Msk              (0x3UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000030 */
9142 #define RCC_CCIPR_USART3SEL                  RCC_CCIPR_USART3SEL_Msk
9143 #define RCC_CCIPR_USART3SEL_0                (0x1UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000010 */
9144 #define RCC_CCIPR_USART3SEL_1                (0x2UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000020 */
9145 
9146 #define RCC_CCIPR_UART4SEL_Pos               (6U)
9147 #define RCC_CCIPR_UART4SEL_Msk               (0x3UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x000000C0 */
9148 #define RCC_CCIPR_UART4SEL                   RCC_CCIPR_UART4SEL_Msk
9149 #define RCC_CCIPR_UART4SEL_0                 (0x1UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000040 */
9150 #define RCC_CCIPR_UART4SEL_1                 (0x2UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000080 */
9151 
9152 #define RCC_CCIPR_UART5SEL_Pos               (8U)
9153 #define RCC_CCIPR_UART5SEL_Msk               (0x3UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000300 */
9154 #define RCC_CCIPR_UART5SEL                   RCC_CCIPR_UART5SEL_Msk
9155 #define RCC_CCIPR_UART5SEL_0                 (0x1UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000100 */
9156 #define RCC_CCIPR_UART5SEL_1                 (0x2UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000200 */
9157 
9158 #define RCC_CCIPR_LPUART1SEL_Pos             (10U)
9159 #define RCC_CCIPR_LPUART1SEL_Msk             (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000C00 */
9160 #define RCC_CCIPR_LPUART1SEL                 RCC_CCIPR_LPUART1SEL_Msk
9161 #define RCC_CCIPR_LPUART1SEL_0               (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000400 */
9162 #define RCC_CCIPR_LPUART1SEL_1               (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000800 */
9163 
9164 #define RCC_CCIPR_I2C1SEL_Pos                (12U)
9165 #define RCC_CCIPR_I2C1SEL_Msk                (0x3UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00003000 */
9166 #define RCC_CCIPR_I2C1SEL                    RCC_CCIPR_I2C1SEL_Msk
9167 #define RCC_CCIPR_I2C1SEL_0                  (0x1UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00001000 */
9168 #define RCC_CCIPR_I2C1SEL_1                  (0x2UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00002000 */
9169 
9170 #define RCC_CCIPR_I2C2SEL_Pos                (14U)
9171 #define RCC_CCIPR_I2C2SEL_Msk                (0x3UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x0000C000 */
9172 #define RCC_CCIPR_I2C2SEL                    RCC_CCIPR_I2C2SEL_Msk
9173 #define RCC_CCIPR_I2C2SEL_0                  (0x1UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x00004000 */
9174 #define RCC_CCIPR_I2C2SEL_1                  (0x2UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x00008000 */
9175 
9176 #define RCC_CCIPR_I2C3SEL_Pos                (16U)
9177 #define RCC_CCIPR_I2C3SEL_Msk                (0x3UL << RCC_CCIPR_I2C3SEL_Pos)  /*!< 0x00030000 */
9178 #define RCC_CCIPR_I2C3SEL                    RCC_CCIPR_I2C3SEL_Msk
9179 #define RCC_CCIPR_I2C3SEL_0                  (0x1UL << RCC_CCIPR_I2C3SEL_Pos)  /*!< 0x00010000 */
9180 #define RCC_CCIPR_I2C3SEL_1                  (0x2UL << RCC_CCIPR_I2C3SEL_Pos)  /*!< 0x00020000 */
9181 
9182 #define RCC_CCIPR_LPTIM1SEL_Pos              (18U)
9183 #define RCC_CCIPR_LPTIM1SEL_Msk              (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x000C0000 */
9184 #define RCC_CCIPR_LPTIM1SEL                  RCC_CCIPR_LPTIM1SEL_Msk
9185 #define RCC_CCIPR_LPTIM1SEL_0                (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x00040000 */
9186 #define RCC_CCIPR_LPTIM1SEL_1                (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x00080000 */
9187 
9188 #define RCC_CCIPR_SAI1SEL_Pos                (20U)
9189 #define RCC_CCIPR_SAI1SEL_Msk                (0x3UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00300000 */
9190 #define RCC_CCIPR_SAI1SEL                    RCC_CCIPR_SAI1SEL_Msk
9191 #define RCC_CCIPR_SAI1SEL_0                  (0x1UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00100000 */
9192 #define RCC_CCIPR_SAI1SEL_1                  (0x2UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00200000 */
9193 
9194 #define RCC_CCIPR_I2S23SEL_Pos               (22U)
9195 #define RCC_CCIPR_I2S23SEL_Msk               (0x3UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00C00000 */
9196 #define RCC_CCIPR_I2S23SEL                   RCC_CCIPR_I2S23SEL_Msk
9197 #define RCC_CCIPR_I2S23SEL_0                 (0x1UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00400000 */
9198 #define RCC_CCIPR_I2S23SEL_1                 (0x2UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00800000 */
9199 
9200 #define RCC_CCIPR_FDCANSEL_Pos               (24U)
9201 #define RCC_CCIPR_FDCANSEL_Msk               (0x3UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x03000000 */
9202 #define RCC_CCIPR_FDCANSEL                   RCC_CCIPR_FDCANSEL_Msk
9203 #define RCC_CCIPR_FDCANSEL_0                 (0x1UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x01000000 */
9204 #define RCC_CCIPR_FDCANSEL_1                 (0x2UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x02000000 */
9205 
9206 #define RCC_CCIPR_CLK48SEL_Pos               (26U)
9207 #define RCC_CCIPR_CLK48SEL_Msk               (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */
9208 #define RCC_CCIPR_CLK48SEL                   RCC_CCIPR_CLK48SEL_Msk
9209 #define RCC_CCIPR_CLK48SEL_0                 (0x1UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */
9210 #define RCC_CCIPR_CLK48SEL_1                 (0x2UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */
9211 
9212 #define RCC_CCIPR_ADC12SEL_Pos               (28U)
9213 #define RCC_CCIPR_ADC12SEL_Msk               (0x3UL << RCC_CCIPR_ADC12SEL_Pos)   /*!< 0x30000000 */
9214 #define RCC_CCIPR_ADC12SEL                   RCC_CCIPR_ADC12SEL_Msk
9215 #define RCC_CCIPR_ADC12SEL_0                 (0x1UL << RCC_CCIPR_ADC12SEL_Pos)   /*!< 0x10000000 */
9216 #define RCC_CCIPR_ADC12SEL_1                 (0x2UL << RCC_CCIPR_ADC12SEL_Pos)   /*!< 0x20000000 */
9217 
9218 #define RCC_CCIPR_ADC345SEL_Pos              (30U)
9219 #define RCC_CCIPR_ADC345SEL_Msk              (0x3UL << RCC_CCIPR_ADC345SEL_Pos)   /*!< 0x80000000 */
9220 #define RCC_CCIPR_ADC345SEL                  RCC_CCIPR_ADC345SEL_Msk
9221 #define RCC_CCIPR_ADC345SEL_0                (0x1UL << RCC_CCIPR_ADC345SEL_Pos)   /*!< 0x40000000 */
9222 #define RCC_CCIPR_ADC345SEL_1                (0x2UL << RCC_CCIPR_ADC345SEL_Pos)   /*!< 0x80000000 */
9223 
9224 /********************  Bit definition for RCC_BDCR register  ******************/
9225 #define RCC_BDCR_LSEON_Pos                   (0U)
9226 #define RCC_BDCR_LSEON_Msk                   (0x1UL << RCC_BDCR_LSEON_Pos)     /*!< 0x00000001 */
9227 #define RCC_BDCR_LSEON                       RCC_BDCR_LSEON_Msk
9228 #define RCC_BDCR_LSERDY_Pos                  (1U)
9229 #define RCC_BDCR_LSERDY_Msk                  (0x1UL << RCC_BDCR_LSERDY_Pos)    /*!< 0x00000002 */
9230 #define RCC_BDCR_LSERDY                      RCC_BDCR_LSERDY_Msk
9231 #define RCC_BDCR_LSEBYP_Pos                  (2U)
9232 #define RCC_BDCR_LSEBYP_Msk                  (0x1UL << RCC_BDCR_LSEBYP_Pos)    /*!< 0x00000004 */
9233 #define RCC_BDCR_LSEBYP                      RCC_BDCR_LSEBYP_Msk
9234 
9235 #define RCC_BDCR_LSEDRV_Pos                  (3U)
9236 #define RCC_BDCR_LSEDRV_Msk                  (0x3UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000018 */
9237 #define RCC_BDCR_LSEDRV                      RCC_BDCR_LSEDRV_Msk
9238 #define RCC_BDCR_LSEDRV_0                    (0x1UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000008 */
9239 #define RCC_BDCR_LSEDRV_1                    (0x2UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000010 */
9240 
9241 #define RCC_BDCR_LSECSSON_Pos                (5U)
9242 #define RCC_BDCR_LSECSSON_Msk                (0x1UL << RCC_BDCR_LSECSSON_Pos)  /*!< 0x00000020 */
9243 #define RCC_BDCR_LSECSSON                    RCC_BDCR_LSECSSON_Msk
9244 #define RCC_BDCR_LSECSSD_Pos                 (6U)
9245 #define RCC_BDCR_LSECSSD_Msk                 (0x1UL << RCC_BDCR_LSECSSD_Pos)   /*!< 0x00000040 */
9246 #define RCC_BDCR_LSECSSD                     RCC_BDCR_LSECSSD_Msk
9247 
9248 #define RCC_BDCR_RTCSEL_Pos                  (8U)
9249 #define RCC_BDCR_RTCSEL_Msk                  (0x3UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000300 */
9250 #define RCC_BDCR_RTCSEL                      RCC_BDCR_RTCSEL_Msk
9251 #define RCC_BDCR_RTCSEL_0                    (0x1UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000100 */
9252 #define RCC_BDCR_RTCSEL_1                    (0x2UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000200 */
9253 
9254 #define RCC_BDCR_RTCEN_Pos                   (15U)
9255 #define RCC_BDCR_RTCEN_Msk                   (0x1UL << RCC_BDCR_RTCEN_Pos)     /*!< 0x00008000 */
9256 #define RCC_BDCR_RTCEN                       RCC_BDCR_RTCEN_Msk
9257 #define RCC_BDCR_BDRST_Pos                   (16U)
9258 #define RCC_BDCR_BDRST_Msk                   (0x1UL << RCC_BDCR_BDRST_Pos)     /*!< 0x00010000 */
9259 #define RCC_BDCR_BDRST                       RCC_BDCR_BDRST_Msk
9260 #define RCC_BDCR_LSCOEN_Pos                  (24U)
9261 #define RCC_BDCR_LSCOEN_Msk                  (0x1UL << RCC_BDCR_LSCOEN_Pos)    /*!< 0x01000000 */
9262 #define RCC_BDCR_LSCOEN                      RCC_BDCR_LSCOEN_Msk
9263 #define RCC_BDCR_LSCOSEL_Pos                 (25U)
9264 #define RCC_BDCR_LSCOSEL_Msk                 (0x1UL << RCC_BDCR_LSCOSEL_Pos)   /*!< 0x02000000 */
9265 #define RCC_BDCR_LSCOSEL                     RCC_BDCR_LSCOSEL_Msk
9266 
9267 /********************  Bit definition for RCC_CSR register  *******************/
9268 #define RCC_CSR_LSION_Pos                    (0U)
9269 #define RCC_CSR_LSION_Msk                    (0x1UL << RCC_CSR_LSION_Pos)      /*!< 0x00000001 */
9270 #define RCC_CSR_LSION                        RCC_CSR_LSION_Msk
9271 #define RCC_CSR_LSIRDY_Pos                   (1U)
9272 #define RCC_CSR_LSIRDY_Msk                   (0x1UL << RCC_CSR_LSIRDY_Pos)     /*!< 0x00000002 */
9273 #define RCC_CSR_LSIRDY                       RCC_CSR_LSIRDY_Msk
9274 
9275 #define RCC_CSR_RMVF_Pos                     (23U)
9276 #define RCC_CSR_RMVF_Msk                     (0x1UL << RCC_CSR_RMVF_Pos)       /*!< 0x00800000 */
9277 #define RCC_CSR_RMVF                         RCC_CSR_RMVF_Msk
9278 #define RCC_CSR_OBLRSTF_Pos                  (25U)
9279 #define RCC_CSR_OBLRSTF_Msk                  (0x1UL << RCC_CSR_OBLRSTF_Pos)    /*!< 0x02000000 */
9280 #define RCC_CSR_OBLRSTF                      RCC_CSR_OBLRSTF_Msk
9281 #define RCC_CSR_PINRSTF_Pos                  (26U)
9282 #define RCC_CSR_PINRSTF_Msk                  (0x1UL << RCC_CSR_PINRSTF_Pos)    /*!< 0x04000000 */
9283 #define RCC_CSR_PINRSTF                      RCC_CSR_PINRSTF_Msk
9284 #define RCC_CSR_BORRSTF_Pos                  (27U)
9285 #define RCC_CSR_BORRSTF_Msk                  (0x1UL << RCC_CSR_BORRSTF_Pos)    /*!< 0x08000000 */
9286 #define RCC_CSR_BORRSTF                      RCC_CSR_BORRSTF_Msk
9287 #define RCC_CSR_SFTRSTF_Pos                  (28U)
9288 #define RCC_CSR_SFTRSTF_Msk                  (0x1UL << RCC_CSR_SFTRSTF_Pos)    /*!< 0x10000000 */
9289 #define RCC_CSR_SFTRSTF                      RCC_CSR_SFTRSTF_Msk
9290 #define RCC_CSR_IWDGRSTF_Pos                 (29U)
9291 #define RCC_CSR_IWDGRSTF_Msk                 (0x1UL << RCC_CSR_IWDGRSTF_Pos)   /*!< 0x20000000 */
9292 #define RCC_CSR_IWDGRSTF                     RCC_CSR_IWDGRSTF_Msk
9293 #define RCC_CSR_WWDGRSTF_Pos                 (30U)
9294 #define RCC_CSR_WWDGRSTF_Msk                 (0x1UL << RCC_CSR_WWDGRSTF_Pos)   /*!< 0x40000000 */
9295 #define RCC_CSR_WWDGRSTF                     RCC_CSR_WWDGRSTF_Msk
9296 #define RCC_CSR_LPWRRSTF_Pos                 (31U)
9297 #define RCC_CSR_LPWRRSTF_Msk                 (0x1UL << RCC_CSR_LPWRRSTF_Pos)   /*!< 0x80000000 */
9298 #define RCC_CSR_LPWRRSTF                     RCC_CSR_LPWRRSTF_Msk
9299 
9300 /********************  Bit definition for RCC_CRRCR register  *****************/
9301 #define RCC_CRRCR_HSI48ON_Pos                (0U)
9302 #define RCC_CRRCR_HSI48ON_Msk                (0x1UL << RCC_CRRCR_HSI48ON_Pos)  /*!< 0x00000001 */
9303 #define RCC_CRRCR_HSI48ON                    RCC_CRRCR_HSI48ON_Msk
9304 #define RCC_CRRCR_HSI48RDY_Pos               (1U)
9305 #define RCC_CRRCR_HSI48RDY_Msk               (0x1UL << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
9306 #define RCC_CRRCR_HSI48RDY                   RCC_CRRCR_HSI48RDY_Msk
9307 
9308 /*!< HSI48CAL configuration */
9309 #define RCC_CRRCR_HSI48CAL_Pos               (7U)
9310 #define RCC_CRRCR_HSI48CAL_Msk               (0x1FFUL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x0000FF80 */
9311 #define RCC_CRRCR_HSI48CAL                   RCC_CRRCR_HSI48CAL_Msk             /*!< HSI48CAL[8:0] bits */
9312 #define RCC_CRRCR_HSI48CAL_0                 (0x001UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000080 */
9313 #define RCC_CRRCR_HSI48CAL_1                 (0x002UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000100 */
9314 #define RCC_CRRCR_HSI48CAL_2                 (0x004UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000200 */
9315 #define RCC_CRRCR_HSI48CAL_3                 (0x008UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000400 */
9316 #define RCC_CRRCR_HSI48CAL_4                 (0x010UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000800 */
9317 #define RCC_CRRCR_HSI48CAL_5                 (0x020UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00001000 */
9318 #define RCC_CRRCR_HSI48CAL_6                 (0x040UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00002000 */
9319 #define RCC_CRRCR_HSI48CAL_7                 (0x080UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00004000 */
9320 #define RCC_CRRCR_HSI48CAL_8                 (0x100UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00008000 */
9321 
9322 /********************  Bit definition for RCC_CCIPR2 register  ******************/
9323 #define RCC_CCIPR2_I2C4SEL_Pos               (0U)
9324 #define RCC_CCIPR2_I2C4SEL_Msk               (0x3UL << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000003 */
9325 #define RCC_CCIPR2_I2C4SEL                   RCC_CCIPR2_I2C4SEL_Msk
9326 #define RCC_CCIPR2_I2C4SEL_0                 (0x1UL << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000001 */
9327 #define RCC_CCIPR2_I2C4SEL_1                 (0x2UL << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000002 */
9328 
9329 #define RCC_CCIPR2_QSPISEL_Pos               (20U)
9330 #define RCC_CCIPR2_QSPISEL_Msk               (0x3UL << RCC_CCIPR2_QSPISEL_Pos) /*!< 0x00030000 */
9331 #define RCC_CCIPR2_QSPISEL                   RCC_CCIPR2_QSPISEL_Msk
9332 #define RCC_CCIPR2_QSPISEL_0                 (0x1UL << RCC_CCIPR2_QSPISEL_Pos) /*!< 0x00010000 */
9333 #define RCC_CCIPR2_QSPISEL_1                 (0x2UL << RCC_CCIPR2_QSPISEL_Pos) /*!< 0x00020000 */
9334 
9335 /******************************************************************************/
9336 /*                                                                            */
9337 /*                                    RNG                                     */
9338 /*                                                                            */
9339 /******************************************************************************/
9340 /********************  Bits definition for RNG_CR register  *******************/
9341 #define RNG_CR_RNGEN_Pos    (2U)
9342 #define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */
9343 #define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk
9344 #define RNG_CR_IE_Pos       (3U)
9345 #define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */
9346 #define RNG_CR_IE           RNG_CR_IE_Msk
9347 #define RNG_CR_CED_Pos      (5U)
9348 #define RNG_CR_CED_Msk      (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000020 */
9349 #define RNG_CR_CED          RNG_CR_IE_Msk
9350 
9351 /********************  Bits definition for RNG_SR register  *******************/
9352 #define RNG_SR_DRDY_Pos     (0U)
9353 #define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */
9354 #define RNG_SR_DRDY         RNG_SR_DRDY_Msk
9355 #define RNG_SR_CECS_Pos     (1U)
9356 #define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */
9357 #define RNG_SR_CECS         RNG_SR_CECS_Msk
9358 #define RNG_SR_SECS_Pos     (2U)
9359 #define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */
9360 #define RNG_SR_SECS         RNG_SR_SECS_Msk
9361 #define RNG_SR_CEIS_Pos     (5U)
9362 #define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */
9363 #define RNG_SR_CEIS         RNG_SR_CEIS_Msk
9364 #define RNG_SR_SEIS_Pos     (6U)
9365 #define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */
9366 #define RNG_SR_SEIS         RNG_SR_SEIS_Msk
9367 
9368 /******************************************************************************/
9369 /*                                                                            */
9370 /*                           Real-Time Clock (RTC)                            */
9371 /*                                                                            */
9372 /******************************************************************************/
9373 
9374 /********************  Bits definition for RTC_TR register  *******************/
9375 #define RTC_TR_PM_Pos                (22U)
9376 #define RTC_TR_PM_Msk                (0x1UL << RTC_TR_PM_Pos)                  /*!< 0x00400000 */
9377 #define RTC_TR_PM                    RTC_TR_PM_Msk
9378 #define RTC_TR_HT_Pos                (20U)
9379 #define RTC_TR_HT_Msk                (0x3UL << RTC_TR_HT_Pos)                  /*!< 0x00300000 */
9380 #define RTC_TR_HT                    RTC_TR_HT_Msk
9381 #define RTC_TR_HT_0                  (0x1UL << RTC_TR_HT_Pos)                  /*!< 0x00100000 */
9382 #define RTC_TR_HT_1                  (0x2UL << RTC_TR_HT_Pos)                  /*!< 0x00200000 */
9383 #define RTC_TR_HU_Pos                (16U)
9384 #define RTC_TR_HU_Msk                (0xFUL << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */
9385 #define RTC_TR_HU                    RTC_TR_HU_Msk
9386 #define RTC_TR_HU_0                  (0x1UL << RTC_TR_HU_Pos)                  /*!< 0x00010000 */
9387 #define RTC_TR_HU_1                  (0x2UL << RTC_TR_HU_Pos)                  /*!< 0x00020000 */
9388 #define RTC_TR_HU_2                  (0x4UL << RTC_TR_HU_Pos)                  /*!< 0x00040000 */
9389 #define RTC_TR_HU_3                  (0x8UL << RTC_TR_HU_Pos)                  /*!< 0x00080000 */
9390 #define RTC_TR_MNT_Pos               (12U)
9391 #define RTC_TR_MNT_Msk               (0x7UL << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */
9392 #define RTC_TR_MNT                   RTC_TR_MNT_Msk
9393 #define RTC_TR_MNT_0                 (0x1UL << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */
9394 #define RTC_TR_MNT_1                 (0x2UL << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */
9395 #define RTC_TR_MNT_2                 (0x4UL << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */
9396 #define RTC_TR_MNU_Pos               (8U)
9397 #define RTC_TR_MNU_Msk               (0xFUL << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */
9398 #define RTC_TR_MNU                   RTC_TR_MNU_Msk
9399 #define RTC_TR_MNU_0                 (0x1UL << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */
9400 #define RTC_TR_MNU_1                 (0x2UL << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */
9401 #define RTC_TR_MNU_2                 (0x4UL << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */
9402 #define RTC_TR_MNU_3                 (0x8UL << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */
9403 #define RTC_TR_ST_Pos                (4U)
9404 #define RTC_TR_ST_Msk                (0x7UL << RTC_TR_ST_Pos)                  /*!< 0x00000070 */
9405 #define RTC_TR_ST                    RTC_TR_ST_Msk
9406 #define RTC_TR_ST_0                  (0x1UL << RTC_TR_ST_Pos)                  /*!< 0x00000010 */
9407 #define RTC_TR_ST_1                  (0x2UL << RTC_TR_ST_Pos)                  /*!< 0x00000020 */
9408 #define RTC_TR_ST_2                  (0x4UL << RTC_TR_ST_Pos)                  /*!< 0x00000040 */
9409 #define RTC_TR_SU_Pos                (0U)
9410 #define RTC_TR_SU_Msk                (0xFUL << RTC_TR_SU_Pos)                  /*!< 0x0000000F */
9411 #define RTC_TR_SU                    RTC_TR_SU_Msk
9412 #define RTC_TR_SU_0                  (0x1UL << RTC_TR_SU_Pos)                  /*!< 0x00000001 */
9413 #define RTC_TR_SU_1                  (0x2UL << RTC_TR_SU_Pos)                  /*!< 0x00000002 */
9414 #define RTC_TR_SU_2                  (0x4UL << RTC_TR_SU_Pos)                  /*!< 0x00000004 */
9415 #define RTC_TR_SU_3                  (0x8UL << RTC_TR_SU_Pos)                  /*!< 0x00000008 */
9416 
9417 /********************  Bits definition for RTC_DR register  *******************/
9418 #define RTC_DR_YT_Pos                (20U)
9419 #define RTC_DR_YT_Msk                (0xFUL << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */
9420 #define RTC_DR_YT                    RTC_DR_YT_Msk
9421 #define RTC_DR_YT_0                  (0x1UL << RTC_DR_YT_Pos)                  /*!< 0x00100000 */
9422 #define RTC_DR_YT_1                  (0x2UL << RTC_DR_YT_Pos)                  /*!< 0x00200000 */
9423 #define RTC_DR_YT_2                  (0x4UL << RTC_DR_YT_Pos)                  /*!< 0x00400000 */
9424 #define RTC_DR_YT_3                  (0x8UL << RTC_DR_YT_Pos)                  /*!< 0x00800000 */
9425 #define RTC_DR_YU_Pos                (16U)
9426 #define RTC_DR_YU_Msk                (0xFUL << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */
9427 #define RTC_DR_YU                    RTC_DR_YU_Msk
9428 #define RTC_DR_YU_0                  (0x1UL << RTC_DR_YU_Pos)                  /*!< 0x00010000 */
9429 #define RTC_DR_YU_1                  (0x2UL << RTC_DR_YU_Pos)                  /*!< 0x00020000 */
9430 #define RTC_DR_YU_2                  (0x4UL << RTC_DR_YU_Pos)                  /*!< 0x00040000 */
9431 #define RTC_DR_YU_3                  (0x8UL << RTC_DR_YU_Pos)                  /*!< 0x00080000 */
9432 #define RTC_DR_WDU_Pos               (13U)
9433 #define RTC_DR_WDU_Msk               (0x7UL << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */
9434 #define RTC_DR_WDU                   RTC_DR_WDU_Msk
9435 #define RTC_DR_WDU_0                 (0x1UL << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */
9436 #define RTC_DR_WDU_1                 (0x2UL << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */
9437 #define RTC_DR_WDU_2                 (0x4UL << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */
9438 #define RTC_DR_MT_Pos                (12U)
9439 #define RTC_DR_MT_Msk                (0x1UL << RTC_DR_MT_Pos)                  /*!< 0x00001000 */
9440 #define RTC_DR_MT                    RTC_DR_MT_Msk
9441 #define RTC_DR_MU_Pos                (8U)
9442 #define RTC_DR_MU_Msk                (0xFUL << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */
9443 #define RTC_DR_MU                    RTC_DR_MU_Msk
9444 #define RTC_DR_MU_0                  (0x1UL << RTC_DR_MU_Pos)                  /*!< 0x00000100 */
9445 #define RTC_DR_MU_1                  (0x2UL << RTC_DR_MU_Pos)                  /*!< 0x00000200 */
9446 #define RTC_DR_MU_2                  (0x4UL << RTC_DR_MU_Pos)                  /*!< 0x00000400 */
9447 #define RTC_DR_MU_3                  (0x8UL << RTC_DR_MU_Pos)                  /*!< 0x00000800 */
9448 #define RTC_DR_DT_Pos                (4U)
9449 #define RTC_DR_DT_Msk                (0x3UL << RTC_DR_DT_Pos)                  /*!< 0x00000030 */
9450 #define RTC_DR_DT                    RTC_DR_DT_Msk
9451 #define RTC_DR_DT_0                  (0x1UL << RTC_DR_DT_Pos)                  /*!< 0x00000010 */
9452 #define RTC_DR_DT_1                  (0x2UL << RTC_DR_DT_Pos)                  /*!< 0x00000020 */
9453 #define RTC_DR_DU_Pos                (0U)
9454 #define RTC_DR_DU_Msk                (0xFUL << RTC_DR_DU_Pos)                  /*!< 0x0000000F */
9455 #define RTC_DR_DU                    RTC_DR_DU_Msk
9456 #define RTC_DR_DU_0                  (0x1UL << RTC_DR_DU_Pos)                  /*!< 0x00000001 */
9457 #define RTC_DR_DU_1                  (0x2UL << RTC_DR_DU_Pos)                  /*!< 0x00000002 */
9458 #define RTC_DR_DU_2                  (0x4UL << RTC_DR_DU_Pos)                  /*!< 0x00000004 */
9459 #define RTC_DR_DU_3                  (0x8UL << RTC_DR_DU_Pos)                  /*!< 0x00000008 */
9460 
9461 /********************  Bits definition for RTC_SSR register  ******************/
9462 #define RTC_SSR_SS_Pos               (0U)
9463 #define RTC_SSR_SS_Msk               (0xFFFFUL << RTC_SSR_SS_Pos)              /*!< 0x0000FFFF */
9464 #define RTC_SSR_SS                   RTC_SSR_SS_Msk
9465 
9466 /********************  Bits definition for RTC_ICSR register  ******************/
9467 #define RTC_ICSR_RECALPF_Pos         (16U)
9468 #define RTC_ICSR_RECALPF_Msk         (0x1UL << RTC_ICSR_RECALPF_Pos)           /*!< 0x00010000 */
9469 #define RTC_ICSR_RECALPF             RTC_ICSR_RECALPF_Msk
9470 #define RTC_ICSR_INIT_Pos            (7U)
9471 #define RTC_ICSR_INIT_Msk            (0x1UL << RTC_ICSR_INIT_Pos)              /*!< 0x00000080 */
9472 #define RTC_ICSR_INIT                RTC_ICSR_INIT_Msk
9473 #define RTC_ICSR_INITF_Pos           (6U)
9474 #define RTC_ICSR_INITF_Msk           (0x1UL << RTC_ICSR_INITF_Pos)             /*!< 0x00000040 */
9475 #define RTC_ICSR_INITF               RTC_ICSR_INITF_Msk
9476 #define RTC_ICSR_RSF_Pos             (5U)
9477 #define RTC_ICSR_RSF_Msk             (0x1UL << RTC_ICSR_RSF_Pos)               /*!< 0x00000020 */
9478 #define RTC_ICSR_RSF                 RTC_ICSR_RSF_Msk
9479 #define RTC_ICSR_INITS_Pos           (4U)
9480 #define RTC_ICSR_INITS_Msk           (0x1UL << RTC_ICSR_INITS_Pos)             /*!< 0x00000010 */
9481 #define RTC_ICSR_INITS               RTC_ICSR_INITS_Msk
9482 #define RTC_ICSR_SHPF_Pos            (3U)
9483 #define RTC_ICSR_SHPF_Msk            (0x1UL << RTC_ICSR_SHPF_Pos)              /*!< 0x00000008 */
9484 #define RTC_ICSR_SHPF                RTC_ICSR_SHPF_Msk
9485 #define RTC_ICSR_WUTWF_Pos           (2U)
9486 #define RTC_ICSR_WUTWF_Msk           (0x1UL << RTC_ICSR_WUTWF_Pos)             /*!< 0x00000004 */
9487 #define RTC_ICSR_WUTWF               RTC_ICSR_WUTWF_Msk
9488 #define RTC_ICSR_ALRBWF_Pos          (1U)
9489 #define RTC_ICSR_ALRBWF_Msk          (0x1UL << RTC_ICSR_ALRBWF_Pos)            /*!< 0x00000002 */
9490 #define RTC_ICSR_ALRBWF              RTC_ICSR_ALRBWF_Msk
9491 #define RTC_ICSR_ALRAWF_Pos          (0U)
9492 #define RTC_ICSR_ALRAWF_Msk          (0x1UL << RTC_ICSR_ALRAWF_Pos)            /*!< 0x00000001 */
9493 #define RTC_ICSR_ALRAWF              RTC_ICSR_ALRAWF_Msk
9494 
9495 /********************  Bits definition for RTC_PRER register  *****************/
9496 #define RTC_PRER_PREDIV_A_Pos        (16U)
9497 #define RTC_PRER_PREDIV_A_Msk        (0x7FUL << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */
9498 #define RTC_PRER_PREDIV_A            RTC_PRER_PREDIV_A_Msk
9499 #define RTC_PRER_PREDIV_S_Pos        (0U)
9500 #define RTC_PRER_PREDIV_S_Msk        (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */
9501 #define RTC_PRER_PREDIV_S            RTC_PRER_PREDIV_S_Msk
9502 
9503 /********************  Bits definition for RTC_WUTR register  *****************/
9504 #define RTC_WUTR_WUT_Pos             (0U)
9505 #define RTC_WUTR_WUT_Msk             (0xFFFFUL << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */
9506 #define RTC_WUTR_WUT                 RTC_WUTR_WUT_Msk
9507 
9508 /********************  Bits definition for RTC_CR register  *******************/
9509 #define RTC_CR_OUT2EN_Pos            (31U)
9510 #define RTC_CR_OUT2EN_Msk            (0x1UL << RTC_CR_OUT2EN_Pos)              /*!< 0x80000000 */
9511 #define RTC_CR_OUT2EN                RTC_CR_OUT2EN_Msk                         /*!<RTC_OUT2 output enable */
9512 #define RTC_CR_TAMPALRM_TYPE_Pos     (30U)
9513 #define RTC_CR_TAMPALRM_TYPE_Msk     (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)       /*!< 0x40000000 */
9514 #define RTC_CR_TAMPALRM_TYPE         RTC_CR_TAMPALRM_TYPE_Msk                  /*!<TAMPALARM output type  */
9515 #define RTC_CR_TAMPALRM_PU_Pos       (29U)
9516 #define RTC_CR_TAMPALRM_PU_Msk       (0x1UL << RTC_CR_TAMPALRM_PU_Pos)         /*!< 0x20000000 */
9517 #define RTC_CR_TAMPALRM_PU           RTC_CR_TAMPALRM_PU_Msk                    /*!<TAMPALARM output pull-up config */
9518 #define RTC_CR_TAMPOE_Pos            (26U)
9519 #define RTC_CR_TAMPOE_Msk            (0x1UL << RTC_CR_TAMPOE_Pos)              /*!< 0x04000000 */
9520 #define RTC_CR_TAMPOE                RTC_CR_TAMPOE_Msk                         /*!<Tamper detection output enable on TAMPALARM  */
9521 #define RTC_CR_TAMPTS_Pos            (25U)
9522 #define RTC_CR_TAMPTS_Msk            (0x1UL << RTC_CR_TAMPTS_Pos)              /*!< 0x02000000 */
9523 #define RTC_CR_TAMPTS                RTC_CR_TAMPTS_Msk                         /*!<Activate timestamp on tamper detection event  */
9524 #define RTC_CR_ITSE_Pos              (24U)
9525 #define RTC_CR_ITSE_Msk              (0x1UL << RTC_CR_ITSE_Pos)                /*!< 0x01000000 */
9526 #define RTC_CR_ITSE                  RTC_CR_ITSE_Msk                           /*!<Timestamp on internal event enable  */
9527 #define RTC_CR_COE_Pos               (23U)
9528 #define RTC_CR_COE_Msk               (0x1UL << RTC_CR_COE_Pos)                 /*!< 0x00800000 */
9529 #define RTC_CR_COE                   RTC_CR_COE_Msk
9530 #define RTC_CR_OSEL_Pos              (21U)
9531 #define RTC_CR_OSEL_Msk              (0x3UL << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */
9532 #define RTC_CR_OSEL                  RTC_CR_OSEL_Msk
9533 #define RTC_CR_OSEL_0                (0x1UL << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */
9534 #define RTC_CR_OSEL_1                (0x2UL << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */
9535 #define RTC_CR_POL_Pos               (20U)
9536 #define RTC_CR_POL_Msk               (0x1UL << RTC_CR_POL_Pos)                 /*!< 0x00100000 */
9537 #define RTC_CR_POL                   RTC_CR_POL_Msk
9538 #define RTC_CR_COSEL_Pos             (19U)
9539 #define RTC_CR_COSEL_Msk             (0x1UL << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */
9540 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk
9541 #define RTC_CR_BKP_Pos               (18U)
9542 #define RTC_CR_BKP_Msk               (0x1UL << RTC_CR_BKP_Pos)                 /*!< 0x00040000 */
9543 #define RTC_CR_BKP                   RTC_CR_BKP_Msk
9544 #define RTC_CR_SUB1H_Pos             (17U)
9545 #define RTC_CR_SUB1H_Msk             (0x1UL << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */
9546 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk
9547 #define RTC_CR_ADD1H_Pos             (16U)
9548 #define RTC_CR_ADD1H_Msk             (0x1UL << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */
9549 #define RTC_CR_ADD1H                 RTC_CR_ADD1H_Msk
9550 #define RTC_CR_TSIE_Pos              (15U)
9551 #define RTC_CR_TSIE_Msk              (0x1UL << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */
9552 #define RTC_CR_TSIE                  RTC_CR_TSIE_Msk
9553 #define RTC_CR_WUTIE_Pos             (14U)
9554 #define RTC_CR_WUTIE_Msk             (0x1UL << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */
9555 #define RTC_CR_WUTIE                 RTC_CR_WUTIE_Msk
9556 #define RTC_CR_ALRBIE_Pos            (13U)
9557 #define RTC_CR_ALRBIE_Msk            (0x1UL << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */
9558 #define RTC_CR_ALRBIE                RTC_CR_ALRBIE_Msk
9559 #define RTC_CR_ALRAIE_Pos            (12U)
9560 #define RTC_CR_ALRAIE_Msk            (0x1UL << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */
9561 #define RTC_CR_ALRAIE                RTC_CR_ALRAIE_Msk
9562 #define RTC_CR_TSE_Pos               (11U)
9563 #define RTC_CR_TSE_Msk               (0x1UL << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */
9564 #define RTC_CR_TSE                   RTC_CR_TSE_Msk
9565 #define RTC_CR_WUTE_Pos              (10U)
9566 #define RTC_CR_WUTE_Msk              (0x1UL << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */
9567 #define RTC_CR_WUTE                  RTC_CR_WUTE_Msk
9568 #define RTC_CR_ALRBE_Pos             (9U)
9569 #define RTC_CR_ALRBE_Msk             (0x1UL << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */
9570 #define RTC_CR_ALRBE                 RTC_CR_ALRBE_Msk
9571 #define RTC_CR_ALRAE_Pos             (8U)
9572 #define RTC_CR_ALRAE_Msk             (0x1UL << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */
9573 #define RTC_CR_ALRAE                 RTC_CR_ALRAE_Msk
9574 #define RTC_CR_FMT_Pos               (6U)
9575 #define RTC_CR_FMT_Msk               (0x1UL << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */
9576 #define RTC_CR_FMT                   RTC_CR_FMT_Msk
9577 #define RTC_CR_BYPSHAD_Pos           (5U)
9578 #define RTC_CR_BYPSHAD_Msk           (0x1UL << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */
9579 #define RTC_CR_BYPSHAD               RTC_CR_BYPSHAD_Msk
9580 #define RTC_CR_REFCKON_Pos           (4U)
9581 #define RTC_CR_REFCKON_Msk           (0x1UL << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */
9582 #define RTC_CR_REFCKON               RTC_CR_REFCKON_Msk
9583 #define RTC_CR_TSEDGE_Pos            (3U)
9584 #define RTC_CR_TSEDGE_Msk            (0x1UL << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */
9585 #define RTC_CR_TSEDGE                RTC_CR_TSEDGE_Msk
9586 #define RTC_CR_WUCKSEL_Pos           (0U)
9587 #define RTC_CR_WUCKSEL_Msk           (0x7UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */
9588 #define RTC_CR_WUCKSEL               RTC_CR_WUCKSEL_Msk
9589 #define RTC_CR_WUCKSEL_0             (0x1UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */
9590 #define RTC_CR_WUCKSEL_1             (0x2UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */
9591 #define RTC_CR_WUCKSEL_2             (0x4UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */
9592 
9593 /********************  Bits definition for RTC_WPR register  ******************/
9594 #define RTC_WPR_KEY_Pos              (0U)
9595 #define RTC_WPR_KEY_Msk              (0xFFUL << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */
9596 #define RTC_WPR_KEY                  RTC_WPR_KEY_Msk
9597 
9598 /********************  Bits definition for RTC_CALR register  *****************/
9599 #define RTC_CALR_CALP_Pos            (15U)
9600 #define RTC_CALR_CALP_Msk            (0x1UL << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */
9601 #define RTC_CALR_CALP                RTC_CALR_CALP_Msk
9602 #define RTC_CALR_CALW8_Pos           (14U)
9603 #define RTC_CALR_CALW8_Msk           (0x1UL << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */
9604 #define RTC_CALR_CALW8               RTC_CALR_CALW8_Msk
9605 #define RTC_CALR_CALW16_Pos          (13U)
9606 #define RTC_CALR_CALW16_Msk          (0x1UL << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */
9607 #define RTC_CALR_CALW16              RTC_CALR_CALW16_Msk
9608 #define RTC_CALR_CALM_Pos            (0U)
9609 #define RTC_CALR_CALM_Msk            (0x1FFUL << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */
9610 #define RTC_CALR_CALM                RTC_CALR_CALM_Msk
9611 #define RTC_CALR_CALM_0              (0x001UL << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */
9612 #define RTC_CALR_CALM_1              (0x002UL << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */
9613 #define RTC_CALR_CALM_2              (0x004UL << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */
9614 #define RTC_CALR_CALM_3              (0x008UL << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */
9615 #define RTC_CALR_CALM_4              (0x010UL << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */
9616 #define RTC_CALR_CALM_5              (0x020UL << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */
9617 #define RTC_CALR_CALM_6              (0x040UL << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */
9618 #define RTC_CALR_CALM_7              (0x080UL << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */
9619 #define RTC_CALR_CALM_8              (0x100UL << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */
9620 
9621 /********************  Bits definition for RTC_SHIFTR register  ***************/
9622 #define RTC_SHIFTR_SUBFS_Pos         (0U)
9623 #define RTC_SHIFTR_SUBFS_Msk         (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */
9624 #define RTC_SHIFTR_SUBFS             RTC_SHIFTR_SUBFS_Msk
9625 #define RTC_SHIFTR_ADD1S_Pos         (31U)
9626 #define RTC_SHIFTR_ADD1S_Msk         (0x1UL << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */
9627 #define RTC_SHIFTR_ADD1S             RTC_SHIFTR_ADD1S_Msk
9628 
9629 /********************  Bits definition for RTC_TSTR register  *****************/
9630 #define RTC_TSTR_PM_Pos              (22U)
9631 #define RTC_TSTR_PM_Msk              (0x1UL << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */
9632 #define RTC_TSTR_PM                  RTC_TSTR_PM_Msk
9633 #define RTC_TSTR_HT_Pos              (20U)
9634 #define RTC_TSTR_HT_Msk              (0x3UL << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */
9635 #define RTC_TSTR_HT                  RTC_TSTR_HT_Msk
9636 #define RTC_TSTR_HT_0                (0x1UL << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */
9637 #define RTC_TSTR_HT_1                (0x2UL << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */
9638 #define RTC_TSTR_HU_Pos              (16U)
9639 #define RTC_TSTR_HU_Msk              (0xFUL << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */
9640 #define RTC_TSTR_HU                  RTC_TSTR_HU_Msk
9641 #define RTC_TSTR_HU_0                (0x1UL << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */
9642 #define RTC_TSTR_HU_1                (0x2UL << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */
9643 #define RTC_TSTR_HU_2                (0x4UL << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */
9644 #define RTC_TSTR_HU_3                (0x8UL << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */
9645 #define RTC_TSTR_MNT_Pos             (12U)
9646 #define RTC_TSTR_MNT_Msk             (0x7UL << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */
9647 #define RTC_TSTR_MNT                 RTC_TSTR_MNT_Msk
9648 #define RTC_TSTR_MNT_0               (0x1UL << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */
9649 #define RTC_TSTR_MNT_1               (0x2UL << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */
9650 #define RTC_TSTR_MNT_2               (0x4UL << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */
9651 #define RTC_TSTR_MNU_Pos             (8U)
9652 #define RTC_TSTR_MNU_Msk             (0xFUL << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */
9653 #define RTC_TSTR_MNU                 RTC_TSTR_MNU_Msk
9654 #define RTC_TSTR_MNU_0               (0x1UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */
9655 #define RTC_TSTR_MNU_1               (0x2UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */
9656 #define RTC_TSTR_MNU_2               (0x4UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */
9657 #define RTC_TSTR_MNU_3               (0x8UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */
9658 #define RTC_TSTR_ST_Pos              (4U)
9659 #define RTC_TSTR_ST_Msk              (0x7UL << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */
9660 #define RTC_TSTR_ST                  RTC_TSTR_ST_Msk
9661 #define RTC_TSTR_ST_0                (0x1UL << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */
9662 #define RTC_TSTR_ST_1                (0x2UL << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */
9663 #define RTC_TSTR_ST_2                (0x4UL << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */
9664 #define RTC_TSTR_SU_Pos              (0U)
9665 #define RTC_TSTR_SU_Msk              (0xFUL << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */
9666 #define RTC_TSTR_SU                  RTC_TSTR_SU_Msk
9667 #define RTC_TSTR_SU_0                (0x1UL << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */
9668 #define RTC_TSTR_SU_1                (0x2UL << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */
9669 #define RTC_TSTR_SU_2                (0x4UL << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */
9670 #define RTC_TSTR_SU_3                (0x8UL << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */
9671 
9672 /********************  Bits definition for RTC_TSDR register  *****************/
9673 #define RTC_TSDR_WDU_Pos             (13U)
9674 #define RTC_TSDR_WDU_Msk             (0x7UL << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */
9675 #define RTC_TSDR_WDU                 RTC_TSDR_WDU_Msk
9676 #define RTC_TSDR_WDU_0               (0x1UL << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */
9677 #define RTC_TSDR_WDU_1               (0x2UL << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */
9678 #define RTC_TSDR_WDU_2               (0x4UL << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */
9679 #define RTC_TSDR_MT_Pos              (12U)
9680 #define RTC_TSDR_MT_Msk              (0x1UL << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */
9681 #define RTC_TSDR_MT                  RTC_TSDR_MT_Msk
9682 #define RTC_TSDR_MU_Pos              (8U)
9683 #define RTC_TSDR_MU_Msk              (0xFUL << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */
9684 #define RTC_TSDR_MU                  RTC_TSDR_MU_Msk
9685 #define RTC_TSDR_MU_0                (0x1UL << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */
9686 #define RTC_TSDR_MU_1                (0x2UL << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */
9687 #define RTC_TSDR_MU_2                (0x4UL << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */
9688 #define RTC_TSDR_MU_3                (0x8UL << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */
9689 #define RTC_TSDR_DT_Pos              (4U)
9690 #define RTC_TSDR_DT_Msk              (0x3UL << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */
9691 #define RTC_TSDR_DT                  RTC_TSDR_DT_Msk
9692 #define RTC_TSDR_DT_0                (0x1UL << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */
9693 #define RTC_TSDR_DT_1                (0x2UL << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */
9694 #define RTC_TSDR_DU_Pos              (0U)
9695 #define RTC_TSDR_DU_Msk              (0xFUL << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */
9696 #define RTC_TSDR_DU                  RTC_TSDR_DU_Msk
9697 #define RTC_TSDR_DU_0                (0x1UL << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */
9698 #define RTC_TSDR_DU_1                (0x2UL << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */
9699 #define RTC_TSDR_DU_2                (0x4UL << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */
9700 #define RTC_TSDR_DU_3                (0x8UL << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */
9701 
9702 /********************  Bits definition for RTC_TSSSR register  ****************/
9703 #define RTC_TSSSR_SS_Pos             (0U)
9704 #define RTC_TSSSR_SS_Msk             (0xFFFFUL << RTC_TSSSR_SS_Pos)            /*!< 0x0000FFFF */
9705 #define RTC_TSSSR_SS                 RTC_TSSSR_SS_Msk
9706 
9707 /********************  Bits definition for RTC_ALRMAR register  ***************/
9708 #define RTC_ALRMAR_MSK4_Pos          (31U)
9709 #define RTC_ALRMAR_MSK4_Msk          (0x1UL << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */
9710 #define RTC_ALRMAR_MSK4              RTC_ALRMAR_MSK4_Msk
9711 #define RTC_ALRMAR_WDSEL_Pos         (30U)
9712 #define RTC_ALRMAR_WDSEL_Msk         (0x1UL << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */
9713 #define RTC_ALRMAR_WDSEL             RTC_ALRMAR_WDSEL_Msk
9714 #define RTC_ALRMAR_DT_Pos            (28U)
9715 #define RTC_ALRMAR_DT_Msk            (0x3UL << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */
9716 #define RTC_ALRMAR_DT                RTC_ALRMAR_DT_Msk
9717 #define RTC_ALRMAR_DT_0              (0x1UL << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */
9718 #define RTC_ALRMAR_DT_1              (0x2UL << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */
9719 #define RTC_ALRMAR_DU_Pos            (24U)
9720 #define RTC_ALRMAR_DU_Msk            (0xFUL << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */
9721 #define RTC_ALRMAR_DU                RTC_ALRMAR_DU_Msk
9722 #define RTC_ALRMAR_DU_0              (0x1UL << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */
9723 #define RTC_ALRMAR_DU_1              (0x2UL << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */
9724 #define RTC_ALRMAR_DU_2              (0x4UL << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */
9725 #define RTC_ALRMAR_DU_3              (0x8UL << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */
9726 #define RTC_ALRMAR_MSK3_Pos          (23U)
9727 #define RTC_ALRMAR_MSK3_Msk          (0x1UL << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */
9728 #define RTC_ALRMAR_MSK3              RTC_ALRMAR_MSK3_Msk
9729 #define RTC_ALRMAR_PM_Pos            (22U)
9730 #define RTC_ALRMAR_PM_Msk            (0x1UL << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */
9731 #define RTC_ALRMAR_PM                RTC_ALRMAR_PM_Msk
9732 #define RTC_ALRMAR_HT_Pos            (20U)
9733 #define RTC_ALRMAR_HT_Msk            (0x3UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */
9734 #define RTC_ALRMAR_HT                RTC_ALRMAR_HT_Msk
9735 #define RTC_ALRMAR_HT_0              (0x1UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */
9736 #define RTC_ALRMAR_HT_1              (0x2UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */
9737 #define RTC_ALRMAR_HU_Pos            (16U)
9738 #define RTC_ALRMAR_HU_Msk            (0xFUL << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */
9739 #define RTC_ALRMAR_HU                RTC_ALRMAR_HU_Msk
9740 #define RTC_ALRMAR_HU_0              (0x1UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */
9741 #define RTC_ALRMAR_HU_1              (0x2UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */
9742 #define RTC_ALRMAR_HU_2              (0x4UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */
9743 #define RTC_ALRMAR_HU_3              (0x8UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */
9744 #define RTC_ALRMAR_MSK2_Pos          (15U)
9745 #define RTC_ALRMAR_MSK2_Msk          (0x1UL << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */
9746 #define RTC_ALRMAR_MSK2              RTC_ALRMAR_MSK2_Msk
9747 #define RTC_ALRMAR_MNT_Pos           (12U)
9748 #define RTC_ALRMAR_MNT_Msk           (0x7UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */
9749 #define RTC_ALRMAR_MNT               RTC_ALRMAR_MNT_Msk
9750 #define RTC_ALRMAR_MNT_0             (0x1UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */
9751 #define RTC_ALRMAR_MNT_1             (0x2UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */
9752 #define RTC_ALRMAR_MNT_2             (0x4UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */
9753 #define RTC_ALRMAR_MNU_Pos           (8U)
9754 #define RTC_ALRMAR_MNU_Msk           (0xFUL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */
9755 #define RTC_ALRMAR_MNU               RTC_ALRMAR_MNU_Msk
9756 #define RTC_ALRMAR_MNU_0             (0x1UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */
9757 #define RTC_ALRMAR_MNU_1             (0x2UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */
9758 #define RTC_ALRMAR_MNU_2             (0x4UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */
9759 #define RTC_ALRMAR_MNU_3             (0x8UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */
9760 #define RTC_ALRMAR_MSK1_Pos          (7U)
9761 #define RTC_ALRMAR_MSK1_Msk          (0x1UL << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */
9762 #define RTC_ALRMAR_MSK1              RTC_ALRMAR_MSK1_Msk
9763 #define RTC_ALRMAR_ST_Pos            (4U)
9764 #define RTC_ALRMAR_ST_Msk            (0x7UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */
9765 #define RTC_ALRMAR_ST                RTC_ALRMAR_ST_Msk
9766 #define RTC_ALRMAR_ST_0              (0x1UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */
9767 #define RTC_ALRMAR_ST_1              (0x2UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */
9768 #define RTC_ALRMAR_ST_2              (0x4UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */
9769 #define RTC_ALRMAR_SU_Pos            (0U)
9770 #define RTC_ALRMAR_SU_Msk            (0xFUL << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */
9771 #define RTC_ALRMAR_SU                RTC_ALRMAR_SU_Msk
9772 #define RTC_ALRMAR_SU_0              (0x1UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */
9773 #define RTC_ALRMAR_SU_1              (0x2UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */
9774 #define RTC_ALRMAR_SU_2              (0x4UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */
9775 #define RTC_ALRMAR_SU_3              (0x8UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */
9776 
9777 /********************  Bits definition for RTC_ALRMASSR register  *************/
9778 #define RTC_ALRMASSR_MASKSS_Pos      (24U)
9779 #define RTC_ALRMASSR_MASKSS_Msk      (0xFUL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */
9780 #define RTC_ALRMASSR_MASKSS          RTC_ALRMASSR_MASKSS_Msk
9781 #define RTC_ALRMASSR_MASKSS_0        (0x1UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */
9782 #define RTC_ALRMASSR_MASKSS_1        (0x2UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */
9783 #define RTC_ALRMASSR_MASKSS_2        (0x4UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */
9784 #define RTC_ALRMASSR_MASKSS_3        (0x8UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */
9785 #define RTC_ALRMASSR_SS_Pos          (0U)
9786 #define RTC_ALRMASSR_SS_Msk          (0x7FFFUL << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */
9787 #define RTC_ALRMASSR_SS              RTC_ALRMASSR_SS_Msk
9788 
9789 /********************  Bits definition for RTC_ALRMBR register  ***************/
9790 #define RTC_ALRMBR_MSK4_Pos          (31U)
9791 #define RTC_ALRMBR_MSK4_Msk          (0x1UL << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */
9792 #define RTC_ALRMBR_MSK4              RTC_ALRMBR_MSK4_Msk
9793 #define RTC_ALRMBR_WDSEL_Pos         (30U)
9794 #define RTC_ALRMBR_WDSEL_Msk         (0x1UL << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */
9795 #define RTC_ALRMBR_WDSEL             RTC_ALRMBR_WDSEL_Msk
9796 #define RTC_ALRMBR_DT_Pos            (28U)
9797 #define RTC_ALRMBR_DT_Msk            (0x3UL << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */
9798 #define RTC_ALRMBR_DT                RTC_ALRMBR_DT_Msk
9799 #define RTC_ALRMBR_DT_0              (0x1UL << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */
9800 #define RTC_ALRMBR_DT_1              (0x2UL << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */
9801 #define RTC_ALRMBR_DU_Pos            (24U)
9802 #define RTC_ALRMBR_DU_Msk            (0xFUL << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */
9803 #define RTC_ALRMBR_DU                RTC_ALRMBR_DU_Msk
9804 #define RTC_ALRMBR_DU_0              (0x1UL << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */
9805 #define RTC_ALRMBR_DU_1              (0x2UL << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */
9806 #define RTC_ALRMBR_DU_2              (0x4UL << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */
9807 #define RTC_ALRMBR_DU_3              (0x8UL << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */
9808 #define RTC_ALRMBR_MSK3_Pos          (23U)
9809 #define RTC_ALRMBR_MSK3_Msk          (0x1UL << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */
9810 #define RTC_ALRMBR_MSK3              RTC_ALRMBR_MSK3_Msk
9811 #define RTC_ALRMBR_PM_Pos            (22U)
9812 #define RTC_ALRMBR_PM_Msk            (0x1UL << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */
9813 #define RTC_ALRMBR_PM                RTC_ALRMBR_PM_Msk
9814 #define RTC_ALRMBR_HT_Pos            (20U)
9815 #define RTC_ALRMBR_HT_Msk            (0x3UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */
9816 #define RTC_ALRMBR_HT                RTC_ALRMBR_HT_Msk
9817 #define RTC_ALRMBR_HT_0              (0x1UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */
9818 #define RTC_ALRMBR_HT_1              (0x2UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */
9819 #define RTC_ALRMBR_HU_Pos            (16U)
9820 #define RTC_ALRMBR_HU_Msk            (0xFUL << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */
9821 #define RTC_ALRMBR_HU                RTC_ALRMBR_HU_Msk
9822 #define RTC_ALRMBR_HU_0              (0x1UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */
9823 #define RTC_ALRMBR_HU_1              (0x2UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */
9824 #define RTC_ALRMBR_HU_2              (0x4UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */
9825 #define RTC_ALRMBR_HU_3              (0x8UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */
9826 #define RTC_ALRMBR_MSK2_Pos          (15U)
9827 #define RTC_ALRMBR_MSK2_Msk          (0x1UL << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */
9828 #define RTC_ALRMBR_MSK2              RTC_ALRMBR_MSK2_Msk
9829 #define RTC_ALRMBR_MNT_Pos           (12U)
9830 #define RTC_ALRMBR_MNT_Msk           (0x7UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */
9831 #define RTC_ALRMBR_MNT               RTC_ALRMBR_MNT_Msk
9832 #define RTC_ALRMBR_MNT_0             (0x1UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */
9833 #define RTC_ALRMBR_MNT_1             (0x2UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */
9834 #define RTC_ALRMBR_MNT_2             (0x4UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */
9835 #define RTC_ALRMBR_MNU_Pos           (8U)
9836 #define RTC_ALRMBR_MNU_Msk           (0xFUL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */
9837 #define RTC_ALRMBR_MNU               RTC_ALRMBR_MNU_Msk
9838 #define RTC_ALRMBR_MNU_0             (0x1UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */
9839 #define RTC_ALRMBR_MNU_1             (0x2UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */
9840 #define RTC_ALRMBR_MNU_2             (0x4UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */
9841 #define RTC_ALRMBR_MNU_3             (0x8UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */
9842 #define RTC_ALRMBR_MSK1_Pos          (7U)
9843 #define RTC_ALRMBR_MSK1_Msk          (0x1UL << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */
9844 #define RTC_ALRMBR_MSK1              RTC_ALRMBR_MSK1_Msk
9845 #define RTC_ALRMBR_ST_Pos            (4U)
9846 #define RTC_ALRMBR_ST_Msk            (0x7UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */
9847 #define RTC_ALRMBR_ST                RTC_ALRMBR_ST_Msk
9848 #define RTC_ALRMBR_ST_0              (0x1UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */
9849 #define RTC_ALRMBR_ST_1              (0x2UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */
9850 #define RTC_ALRMBR_ST_2              (0x4UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */
9851 #define RTC_ALRMBR_SU_Pos            (0U)
9852 #define RTC_ALRMBR_SU_Msk            (0xFUL << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */
9853 #define RTC_ALRMBR_SU                RTC_ALRMBR_SU_Msk
9854 #define RTC_ALRMBR_SU_0              (0x1UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */
9855 #define RTC_ALRMBR_SU_1              (0x2UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */
9856 #define RTC_ALRMBR_SU_2              (0x4UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */
9857 #define RTC_ALRMBR_SU_3              (0x8UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */
9858 
9859 /********************  Bits definition for RTC_ALRMASSR register  *************/
9860 #define RTC_ALRMBSSR_MASKSS_Pos      (24U)
9861 #define RTC_ALRMBSSR_MASKSS_Msk      (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x0F000000 */
9862 #define RTC_ALRMBSSR_MASKSS          RTC_ALRMBSSR_MASKSS_Msk
9863 #define RTC_ALRMBSSR_MASKSS_0        (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */
9864 #define RTC_ALRMBSSR_MASKSS_1        (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */
9865 #define RTC_ALRMBSSR_MASKSS_2        (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */
9866 #define RTC_ALRMBSSR_MASKSS_3        (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */
9867 #define RTC_ALRMBSSR_SS_Pos          (0U)
9868 #define RTC_ALRMBSSR_SS_Msk          (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */
9869 #define RTC_ALRMBSSR_SS              RTC_ALRMBSSR_SS_Msk
9870 
9871 /********************  Bits definition for RTC_SR register  *******************/
9872 #define RTC_SR_ITSF_Pos              (5U)
9873 #define RTC_SR_ITSF_Msk              (0x1UL << RTC_SR_ITSF_Pos)                /*!< 0x00000020 */
9874 #define RTC_SR_ITSF                  RTC_SR_ITSF_Msk
9875 #define RTC_SR_TSOVF_Pos             (4U)
9876 #define RTC_SR_TSOVF_Msk             (0x1UL << RTC_SR_TSOVF_Pos)               /*!< 0x00000010 */
9877 #define RTC_SR_TSOVF                 RTC_SR_TSOVF_Msk
9878 #define RTC_SR_TSF_Pos               (3U)
9879 #define RTC_SR_TSF_Msk               (0x1UL << RTC_SR_TSF_Pos)                 /*!< 0x00000008 */
9880 #define RTC_SR_TSF                   RTC_SR_TSF_Msk
9881 #define RTC_SR_WUTF_Pos              (2U)
9882 #define RTC_SR_WUTF_Msk              (0x1UL << RTC_SR_WUTF_Pos)                /*!< 0x00000004 */
9883 #define RTC_SR_WUTF                  RTC_SR_WUTF_Msk
9884 #define RTC_SR_ALRBF_Pos             (1U)
9885 #define RTC_SR_ALRBF_Msk             (0x1UL << RTC_SR_ALRBF_Pos)               /*!< 0x00000002 */
9886 #define RTC_SR_ALRBF                 RTC_SR_ALRBF_Msk
9887 #define RTC_SR_ALRAF_Pos             (0U)
9888 #define RTC_SR_ALRAF_Msk             (0x1UL << RTC_SR_ALRAF_Pos)               /*!< 0x00000001 */
9889 #define RTC_SR_ALRAF                 RTC_SR_ALRAF_Msk
9890 
9891 /********************  Bits definition for RTC_MISR register  *****************/
9892 #define RTC_MISR_ITSMF_Pos           (5U)
9893 #define RTC_MISR_ITSMF_Msk           (0x1UL << RTC_MISR_ITSMF_Pos)             /*!< 0x00000020 */
9894 #define RTC_MISR_ITSMF               RTC_MISR_ITSMF_Msk
9895 #define RTC_MISR_TSOVMF_Pos          (4U)
9896 #define RTC_MISR_TSOVMF_Msk          (0x1UL << RTC_MISR_TSOVMF_Pos)            /*!< 0x00000010 */
9897 #define RTC_MISR_TSOVMF              RTC_MISR_TSOVMF_Msk
9898 #define RTC_MISR_TSMF_Pos            (3U)
9899 #define RTC_MISR_TSMF_Msk            (0x1UL << RTC_MISR_TSMF_Pos)              /*!< 0x00000008 */
9900 #define RTC_MISR_TSMF                RTC_MISR_TSMF_Msk
9901 #define RTC_MISR_WUTMF_Pos           (2U)
9902 #define RTC_MISR_WUTMF_Msk           (0x1UL << RTC_MISR_WUTMF_Pos)             /*!< 0x00000004 */
9903 #define RTC_MISR_WUTMF               RTC_MISR_WUTMF_Msk
9904 #define RTC_MISR_ALRBMF_Pos          (1U)
9905 #define RTC_MISR_ALRBMF_Msk          (0x1UL << RTC_MISR_ALRBMF_Pos)            /*!< 0x00000002 */
9906 #define RTC_MISR_ALRBMF              RTC_MISR_ALRBMF_Msk
9907 #define RTC_MISR_ALRAMF_Pos          (0U)
9908 #define RTC_MISR_ALRAMF_Msk          (0x1UL << RTC_MISR_ALRAMF_Pos)            /*!< 0x00000001 */
9909 #define RTC_MISR_ALRAMF              RTC_MISR_ALRAMF_Msk
9910 
9911 /********************  Bits definition for RTC_SCR register  ******************/
9912 #define RTC_SCR_CITSF_Pos            (5U)
9913 #define RTC_SCR_CITSF_Msk            (0x1UL << RTC_SCR_CITSF_Pos)              /*!< 0x00000020 */
9914 #define RTC_SCR_CITSF                RTC_SCR_CITSF_Msk
9915 #define RTC_SCR_CTSOVF_Pos           (4U)
9916 #define RTC_SCR_CTSOVF_Msk           (0x1UL << RTC_SCR_CTSOVF_Pos)             /*!< 0x00000010 */
9917 #define RTC_SCR_CTSOVF               RTC_SCR_CTSOVF_Msk
9918 #define RTC_SCR_CTSF_Pos             (3U)
9919 #define RTC_SCR_CTSF_Msk             (0x1UL << RTC_SCR_CTSF_Pos)               /*!< 0x00000008 */
9920 #define RTC_SCR_CTSF                 RTC_SCR_CTSF_Msk
9921 #define RTC_SCR_CWUTF_Pos            (2U)
9922 #define RTC_SCR_CWUTF_Msk            (0x1UL << RTC_SCR_CWUTF_Pos)              /*!< 0x00000004 */
9923 #define RTC_SCR_CWUTF                RTC_SCR_CWUTF_Msk
9924 #define RTC_SCR_CALRBF_Pos           (1U)
9925 #define RTC_SCR_CALRBF_Msk           (0x1UL << RTC_SCR_CALRBF_Pos)             /*!< 0x00000002 */
9926 #define RTC_SCR_CALRBF               RTC_SCR_CALRBF_Msk
9927 #define RTC_SCR_CALRAF_Pos           (0U)
9928 #define RTC_SCR_CALRAF_Msk           (0x1UL << RTC_SCR_CALRAF_Pos)             /*!< 0x00000001 */
9929 #define RTC_SCR_CALRAF               RTC_SCR_CALRAF_Msk
9930 
9931 /******************************************************************************/
9932 /*                                                                            */
9933 /*                     Tamper and backup register (TAMP)                      */
9934 /*                                                                            */
9935 /******************************************************************************/
9936 /********************  Bits definition for TAMP_CR1 register  *****************/
9937 #define TAMP_CR1_TAMP1E_Pos          (0U)
9938 #define TAMP_CR1_TAMP1E_Msk          (0x1UL << TAMP_CR1_TAMP1E_Pos)            /*!< 0x00000001 */
9939 #define TAMP_CR1_TAMP1E              TAMP_CR1_TAMP1E_Msk
9940 #define TAMP_CR1_TAMP2E_Pos          (1U)
9941 #define TAMP_CR1_TAMP2E_Msk          (0x1UL << TAMP_CR1_TAMP2E_Pos)            /*!< 0x00000002 */
9942 #define TAMP_CR1_TAMP2E              TAMP_CR1_TAMP2E_Msk
9943 #define TAMP_CR1_TAMP3E_Pos          (2U)
9944 #define TAMP_CR1_TAMP3E_Msk          (0x1UL << TAMP_CR1_TAMP3E_Pos)            /*!< 0x00000004 */
9945 #define TAMP_CR1_TAMP3E              TAMP_CR1_TAMP3E_Msk
9946 #define TAMP_CR1_ITAMP3E_Pos         (18U)
9947 #define TAMP_CR1_ITAMP3E_Msk         (0x1UL << TAMP_CR1_ITAMP3E_Pos)           /*!< 0x00040000 */
9948 #define TAMP_CR1_ITAMP3E             TAMP_CR1_ITAMP3E_Msk
9949 #define TAMP_CR1_ITAMP4E_Pos         (19U)
9950 #define TAMP_CR1_ITAMP4E_Msk         (0x1UL << TAMP_CR1_ITAMP4E_Pos)           /*!< 0x00080000 */
9951 #define TAMP_CR1_ITAMP4E             TAMP_CR1_ITAMP4E_Msk
9952 #define TAMP_CR1_ITAMP5E_Pos         (20U)
9953 #define TAMP_CR1_ITAMP5E_Msk         (0x1UL << TAMP_CR1_ITAMP5E_Pos)           /*!< 0x00100000 */
9954 #define TAMP_CR1_ITAMP5E             TAMP_CR1_ITAMP5E_Msk
9955 #define TAMP_CR1_ITAMP6E_Pos         (21U)
9956 #define TAMP_CR1_ITAMP6E_Msk         (0x1UL << TAMP_CR1_ITAMP6E_Pos)           /*!< 0x00200000 */
9957 #define TAMP_CR1_ITAMP6E             TAMP_CR1_ITAMP6E_Msk
9958 
9959 /********************  Bits definition for TAMP_CR2 register  *****************/
9960 #define TAMP_CR2_TAMP1NOERASE_Pos    (0U)
9961 #define TAMP_CR2_TAMP1NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)      /*!< 0x00000001 */
9962 #define TAMP_CR2_TAMP1NOERASE        TAMP_CR2_TAMP1NOERASE_Msk
9963 #define TAMP_CR2_TAMP2NOERASE_Pos    (1U)
9964 #define TAMP_CR2_TAMP2NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)      /*!< 0x00000002 */
9965 #define TAMP_CR2_TAMP2NOERASE        TAMP_CR2_TAMP2NOERASE_Msk
9966 #define TAMP_CR2_TAMP3NOERASE_Pos    (2U)
9967 #define TAMP_CR2_TAMP3NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos)      /*!< 0x00000004 */
9968 #define TAMP_CR2_TAMP3NOERASE        TAMP_CR2_TAMP3NOERASE_Msk
9969 #define TAMP_CR2_TAMP1MF_Pos         (16U)
9970 #define TAMP_CR2_TAMP1MF_Msk         (0x1UL << TAMP_CR2_TAMP1MF_Pos)           /*!< 0x00010000 */
9971 #define TAMP_CR2_TAMP1MF             TAMP_CR2_TAMP1MF_Msk
9972 #define TAMP_CR2_TAMP2MF_Pos         (17U)
9973 #define TAMP_CR2_TAMP2MF_Msk         (0x1UL << TAMP_CR2_TAMP2MF_Pos)           /*!< 0x00020000 */
9974 #define TAMP_CR2_TAMP2MF             TAMP_CR2_TAMP2MF_Msk
9975 #define TAMP_CR2_TAMP3MF_Pos         (18U)
9976 #define TAMP_CR2_TAMP3MF_Msk         (0x1UL << TAMP_CR2_TAMP3MF_Pos)           /*!< 0x00040000 */
9977 #define TAMP_CR2_TAMP3MF             TAMP_CR2_TAMP3MF_Msk
9978 #define TAMP_CR2_TAMP1TRG_Pos        (24U)
9979 #define TAMP_CR2_TAMP1TRG_Msk        (0x1UL << TAMP_CR2_TAMP1TRG_Pos)          /*!< 0x01000000 */
9980 #define TAMP_CR2_TAMP1TRG            TAMP_CR2_TAMP1TRG_Msk
9981 #define TAMP_CR2_TAMP2TRG_Pos        (25U)
9982 #define TAMP_CR2_TAMP2TRG_Msk        (0x1UL << TAMP_CR2_TAMP2TRG_Pos)          /*!< 0x02000000 */
9983 #define TAMP_CR2_TAMP2TRG            TAMP_CR2_TAMP2TRG_Msk
9984 #define TAMP_CR2_TAMP3TRG_Pos        (26U)
9985 #define TAMP_CR2_TAMP3TRG_Msk        (0x1UL << TAMP_CR2_TAMP3TRG_Pos)          /*!< 0x04000000 */
9986 #define TAMP_CR2_TAMP3TRG            TAMP_CR2_TAMP3TRG_Msk
9987 
9988 /********************  Bits definition for TAMP_FLTCR register  ***************/
9989 #define TAMP_FLTCR_TAMPFREQ_0        (0x00000001UL)
9990 #define TAMP_FLTCR_TAMPFREQ_1        (0x00000002UL)
9991 #define TAMP_FLTCR_TAMPFREQ_2        (0x00000004UL)
9992 #define TAMP_FLTCR_TAMPFREQ_Pos      (0U)
9993 #define TAMP_FLTCR_TAMPFREQ_Msk      (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)        /*!< 0x00000007 */
9994 #define TAMP_FLTCR_TAMPFREQ          TAMP_FLTCR_TAMPFREQ_Msk
9995 #define TAMP_FLTCR_TAMPFLT_0         (0x00000008UL)
9996 #define TAMP_FLTCR_TAMPFLT_1         (0x00000010UL)
9997 #define TAMP_FLTCR_TAMPFLT_Pos       (3U)
9998 #define TAMP_FLTCR_TAMPFLT_Msk       (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)         /*!< 0x00000018 */
9999 #define TAMP_FLTCR_TAMPFLT           TAMP_FLTCR_TAMPFLT_Msk
10000 #define TAMP_FLTCR_TAMPPRCH_0        (0x00000020UL)
10001 #define TAMP_FLTCR_TAMPPRCH_1        (0x00000040UL)
10002 #define TAMP_FLTCR_TAMPPRCH_Pos      (5U)
10003 #define TAMP_FLTCR_TAMPPRCH_Msk      (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)        /*!< 0x00000060 */
10004 #define TAMP_FLTCR_TAMPPRCH          TAMP_FLTCR_TAMPPRCH_Msk
10005 #define TAMP_FLTCR_TAMPPUDIS_Pos     (7U)
10006 #define TAMP_FLTCR_TAMPPUDIS_Msk     (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)       /*!< 0x00000080 */
10007 #define TAMP_FLTCR_TAMPPUDIS         TAMP_FLTCR_TAMPPUDIS_Msk
10008 
10009 /********************  Bits definition for TAMP_IER register  *****************/
10010 #define TAMP_IER_TAMP1IE_Pos         (0U)
10011 #define TAMP_IER_TAMP1IE_Msk         (0x1UL << TAMP_IER_TAMP1IE_Pos)           /*!< 0x00000001 */
10012 #define TAMP_IER_TAMP1IE             TAMP_IER_TAMP1IE_Msk
10013 #define TAMP_IER_TAMP2IE_Pos         (1U)
10014 #define TAMP_IER_TAMP2IE_Msk         (0x1UL << TAMP_IER_TAMP2IE_Pos)           /*!< 0x00000002 */
10015 #define TAMP_IER_TAMP2IE             TAMP_IER_TAMP2IE_Msk
10016 #define TAMP_IER_TAMP3IE_Pos         (2U)
10017 #define TAMP_IER_TAMP3IE_Msk         (0x1UL << TAMP_IER_TAMP3IE_Pos)           /*!< 0x00000004 */
10018 #define TAMP_IER_TAMP3IE             TAMP_IER_TAMP3IE_Msk
10019 #define TAMP_IER_ITAMP3IE_Pos        (18U)
10020 #define TAMP_IER_ITAMP3IE_Msk        (0x1UL << TAMP_IER_ITAMP3IE_Pos)          /*!< 0x00040000 */
10021 #define TAMP_IER_ITAMP3IE            TAMP_IER_ITAMP3IE_Msk
10022 #define TAMP_IER_ITAMP4IE_Pos        (19U)
10023 #define TAMP_IER_ITAMP4IE_Msk        (0x1UL << TAMP_IER_ITAMP4IE_Pos)          /*!< 0x00080000 */
10024 #define TAMP_IER_ITAMP4IE            TAMP_IER_ITAMP4IE_Msk
10025 #define TAMP_IER_ITAMP5IE_Pos        (20U)
10026 #define TAMP_IER_ITAMP5IE_Msk        (0x1UL << TAMP_IER_ITAMP5IE_Pos)          /*!< 0x00100000 */
10027 #define TAMP_IER_ITAMP5IE            TAMP_IER_ITAMP5IE_Msk
10028 #define TAMP_IER_ITAMP6IE_Pos        (21U)
10029 #define TAMP_IER_ITAMP6IE_Msk        (0x1UL << TAMP_IER_ITAMP6IE_Pos)          /*!< 0x00200000 */
10030 #define TAMP_IER_ITAMP6IE            TAMP_IER_ITAMP6IE_Msk
10031 
10032 /********************  Bits definition for TAMP_SR register  ******************/
10033 #define TAMP_SR_TAMP1F_Pos           (0U)
10034 #define TAMP_SR_TAMP1F_Msk           (0x1UL << TAMP_SR_TAMP1F_Pos)       /*!< 0x00000001 */
10035 #define TAMP_SR_TAMP1F               TAMP_SR_TAMP1F_Msk
10036 #define TAMP_SR_TAMP2F_Pos           (1U)
10037 #define TAMP_SR_TAMP2F_Msk           (0x1UL << TAMP_SR_TAMP2F_Pos)       /*!< 0x00000002 */
10038 #define TAMP_SR_TAMP2F               TAMP_SR_TAMP2F_Msk
10039 #define TAMP_SR_TAMP3F_Pos           (2U)
10040 #define TAMP_SR_TAMP3F_Msk           (0x1UL << TAMP_SR_TAMP3F_Pos)       /*!< 0x00000004 */
10041 #define TAMP_SR_TAMP3F               TAMP_SR_TAMP3F_Msk
10042 #define TAMP_SR_ITAMP3F_Pos          (18U)
10043 #define TAMP_SR_ITAMP3F_Msk          (0x1UL << TAMP_SR_ITAMP3F_Pos)      /*!< 0x00040000 */
10044 #define TAMP_SR_ITAMP3F              TAMP_SR_ITAMP3F_Msk
10045 #define TAMP_SR_ITAMP4F_Pos          (19U)
10046 #define TAMP_SR_ITAMP4F_Msk          (0x1UL << TAMP_SR_ITAMP4F_Pos)      /*!< 0x00080000 */
10047 #define TAMP_SR_ITAMP4F              TAMP_SR_ITAMP4F_Msk
10048 #define TAMP_SR_ITAMP5F_Pos          (20U)
10049 #define TAMP_SR_ITAMP5F_Msk          (0x1UL << TAMP_SR_ITAMP5F_Pos)      /*!< 0x00100000 */
10050 #define TAMP_SR_ITAMP5F              TAMP_SR_ITAMP5F_Msk
10051 #define TAMP_SR_ITAMP6F_Pos          (21U)
10052 #define TAMP_SR_ITAMP6F_Msk          (0x1UL << TAMP_SR_ITAMP6F_Pos)      /*!< 0x00200000 */
10053 #define TAMP_SR_ITAMP6F              TAMP_SR_ITAMP6F_Msk
10054 
10055 /********************  Bits definition for TAMP_MISR register  ****************/
10056 #define TAMP_MISR_TAMP1MF_Pos        (0U)
10057 #define TAMP_MISR_TAMP1MF_Msk        (0x1UL << TAMP_MISR_TAMP1MF_Pos)       /*!< 0x00000001 */
10058 #define TAMP_MISR_TAMP1MF            TAMP_MISR_TAMP1MF_Msk
10059 #define TAMP_MISR_TAMP2MF_Pos        (1U)
10060 #define TAMP_MISR_TAMP2MF_Msk        (0x1UL << TAMP_MISR_TAMP2MF_Pos)       /*!< 0x00000002 */
10061 #define TAMP_MISR_TAMP2MF            TAMP_MISR_TAMP2MF_Msk
10062 #define TAMP_MISR_TAMP3MF_Pos        (2U)
10063 #define TAMP_MISR_TAMP3MF_Msk        (0x1UL << TAMP_MISR_TAMP3MF_Pos)       /*!< 0x00000004 */
10064 #define TAMP_MISR_TAMP3MF            TAMP_MISR_TAMP3MF_Msk
10065 #define TAMP_MISR_ITAMP3MF_Pos       (18U)
10066 #define TAMP_MISR_ITAMP3MF_Msk       (0x1UL << TAMP_MISR_ITAMP3MF_Pos)      /*!< 0x00040000 */
10067 #define TAMP_MISR_ITAMP3MF           TAMP_MISR_ITAMP3MF_Msk
10068 #define TAMP_MISR_ITAMP4MF_Pos       (19U)
10069 #define TAMP_MISR_ITAMP4MF_Msk       (0x1UL << TAMP_MISR_ITAMP4MF_Pos)      /*!< 0x00080000 */
10070 #define TAMP_MISR_ITAMP4MF           TAMP_MISR_ITAMP4MF_Msk
10071 #define TAMP_MISR_ITAMP5MF_Pos       (20U)
10072 #define TAMP_MISR_ITAMP5MF_Msk       (0x1UL << TAMP_MISR_ITAMP5MF_Pos)      /*!< 0x00100000 */
10073 #define TAMP_MISR_ITAMP5MF           TAMP_MISR_ITAMP5MF_Msk
10074 #define TAMP_MISR_ITAMP6MF_Pos       (21U)
10075 #define TAMP_MISR_ITAMP6MF_Msk       (0x1UL << TAMP_MISR_ITAMP6MF_Pos)      /*!< 0x00200000 */
10076 #define TAMP_MISR_ITAMP6MF           TAMP_MISR_ITAMP6MF_Msk
10077 
10078 /********************  Bits definition for TAMP_SCR register  *****************/
10079 #define TAMP_SCR_CTAMP1F_Pos         (0U)
10080 #define TAMP_SCR_CTAMP1F_Msk         (0x1UL << TAMP_SCR_CTAMP1F_Pos)       /*!< 0x00000001 */
10081 #define TAMP_SCR_CTAMP1F             TAMP_SCR_CTAMP1F_Msk
10082 #define TAMP_SCR_CTAMP2F_Pos         (1U)
10083 #define TAMP_SCR_CTAMP2F_Msk         (0x1UL << TAMP_SCR_CTAMP2F_Pos)       /*!< 0x00000002 */
10084 #define TAMP_SCR_CTAMP2F             TAMP_SCR_CTAMP2F_Msk
10085 #define TAMP_SCR_CTAMP3F_Pos         (2U)
10086 #define TAMP_SCR_CTAMP3F_Msk         (0x1UL << TAMP_SCR_CTAMP3F_Pos)       /*!< 0x00000004 */
10087 #define TAMP_SCR_CTAMP3F             TAMP_SCR_CTAMP3F_Msk
10088 #define TAMP_SCR_CITAMP3F_Pos        (18U)
10089 #define TAMP_SCR_CITAMP3F_Msk        (0x1UL << TAMP_SCR_CITAMP3F_Pos)      /*!< 0x00040000 */
10090 #define TAMP_SCR_CITAMP3F            TAMP_SCR_CITAMP3F_Msk
10091 #define TAMP_SCR_CITAMP4F_Pos        (19U)
10092 #define TAMP_SCR_CITAMP4F_Msk        (0x1UL << TAMP_SCR_CITAMP4F_Pos)      /*!< 0x00080000 */
10093 #define TAMP_SCR_CITAMP4F            TAMP_SCR_CITAMP4F_Msk
10094 #define TAMP_SCR_CITAMP5F_Pos        (20U)
10095 #define TAMP_SCR_CITAMP5F_Msk        (0x1UL << TAMP_SCR_CITAMP5F_Pos)      /*!< 0x00100000 */
10096 #define TAMP_SCR_CITAMP5F            TAMP_SCR_CITAMP5F_Msk
10097 #define TAMP_SCR_CITAMP6F_Pos        (21U)
10098 #define TAMP_SCR_CITAMP6F_Msk        (0x1UL << TAMP_SCR_CITAMP6F_Pos)      /*!< 0x00200000 */
10099 #define TAMP_SCR_CITAMP6F            TAMP_SCR_CITAMP6F_Msk
10100 
10101 /********************  Bits definition for TAMP_BKP0R register  ***************/
10102 #define TAMP_BKP0R_Pos               (0U)
10103 #define TAMP_BKP0R_Msk               (0xFFFFFFFFUL << TAMP_BKP0R_Pos)         /*!< 0xFFFFFFFF */
10104 #define TAMP_BKP0R                   TAMP_BKP0R_Msk
10105 
10106 /********************  Bits definition for TAMP_BKP1R register  ***************/
10107 #define TAMP_BKP1R_Pos               (0U)
10108 #define TAMP_BKP1R_Msk               (0xFFFFFFFFUL << TAMP_BKP1R_Pos)          /*!< 0xFFFFFFFF */
10109 #define TAMP_BKP1R                   TAMP_BKP1R_Msk
10110 
10111 /********************  Bits definition for TAMP_BKP2R register  ***************/
10112 #define TAMP_BKP2R_Pos               (0U)
10113 #define TAMP_BKP2R_Msk               (0xFFFFFFFFUL << TAMP_BKP2R_Pos)          /*!< 0xFFFFFFFF */
10114 #define TAMP_BKP2R                   TAMP_BKP2R_Msk
10115 
10116 /********************  Bits definition for TAMP_BKP3R register  ***************/
10117 #define TAMP_BKP3R_Pos               (0U)
10118 #define TAMP_BKP3R_Msk               (0xFFFFFFFFUL << TAMP_BKP3R_Pos)          /*!< 0xFFFFFFFF */
10119 #define TAMP_BKP3R                   TAMP_BKP3R_Msk
10120 
10121 /********************  Bits definition for TAMP_BKP4R register  ***************/
10122 #define TAMP_BKP4R_Pos               (0U)
10123 #define TAMP_BKP4R_Msk               (0xFFFFFFFFUL << TAMP_BKP4R_Pos)          /*!< 0xFFFFFFFF */
10124 #define TAMP_BKP4R                   TAMP_BKP4R_Msk
10125 
10126 /********************  Bits definition for TAMP_BKP5R register  ***************/
10127 #define TAMP_BKP5R_Pos               (0U)
10128 #define TAMP_BKP5R_Msk               (0xFFFFFFFFUL << TAMP_BKP5R_Pos)          /*!< 0xFFFFFFFF */
10129 #define TAMP_BKP5R                   TAMP_BKP5R_Msk
10130 
10131 /********************  Bits definition for TAMP_BKP6R register  ***************/
10132 #define TAMP_BKP6R_Pos               (0U)
10133 #define TAMP_BKP6R_Msk               (0xFFFFFFFFUL << TAMP_BKP6R_Pos)          /*!< 0xFFFFFFFF */
10134 #define TAMP_BKP6R                   TAMP_BKP6R_Msk
10135 
10136 /********************  Bits definition for TAMP_BKP7R register  ***************/
10137 #define TAMP_BKP7R_Pos               (0U)
10138 #define TAMP_BKP7R_Msk               (0xFFFFFFFFUL << TAMP_BKP7R_Pos)          /*!< 0xFFFFFFFF */
10139 #define TAMP_BKP7R                   TAMP_BKP7R_Msk
10140 
10141 /********************  Bits definition for TAMP_BKP8R register  ***************/
10142 #define TAMP_BKP8R_Pos               (0U)
10143 #define TAMP_BKP8R_Msk               (0xFFFFFFFFUL << TAMP_BKP8R_Pos)          /*!< 0xFFFFFFFF */
10144 #define TAMP_BKP8R                   TAMP_BKP8R_Msk
10145 
10146 /********************  Bits definition for TAMP_BKP9R register  ***************/
10147 #define TAMP_BKP9R_Pos               (0U)
10148 #define TAMP_BKP9R_Msk               (0xFFFFFFFFUL << TAMP_BKP9R_Pos)          /*!< 0xFFFFFFFF */
10149 #define TAMP_BKP9R                   TAMP_BKP9R_Msk
10150 
10151 /********************  Bits definition for TAMP_BKP10R register  ***************/
10152 #define TAMP_BKP10R_Pos               (0U)
10153 #define TAMP_BKP10R_Msk               (0xFFFFFFFFUL << TAMP_BKP10R_Pos)          /*!< 0xFFFFFFFF */
10154 #define TAMP_BKP10R                   TAMP_BKP10R_Msk
10155 
10156 /********************  Bits definition for TAMP_BKP11R register  ***************/
10157 #define TAMP_BKP11R_Pos               (0U)
10158 #define TAMP_BKP11R_Msk               (0xFFFFFFFFUL << TAMP_BKP11R_Pos)          /*!< 0xFFFFFFFF */
10159 #define TAMP_BKP11R                   TAMP_BKP11R_Msk
10160 
10161 /********************  Bits definition for TAMP_BKP12R register  ***************/
10162 #define TAMP_BKP12R_Pos               (0U)
10163 #define TAMP_BKP12R_Msk               (0xFFFFFFFFUL << TAMP_BKP12R_Pos)          /*!< 0xFFFFFFFF */
10164 #define TAMP_BKP12R                   TAMP_BKP12R_Msk
10165 
10166 /********************  Bits definition for TAMP_BKP13R register  ***************/
10167 #define TAMP_BKP13R_Pos               (0U)
10168 #define TAMP_BKP13R_Msk               (0xFFFFFFFFUL << TAMP_BKP13R_Pos)          /*!< 0xFFFFFFFF */
10169 #define TAMP_BKP13R                   TAMP_BKP13R_Msk
10170 
10171 /********************  Bits definition for TAMP_BKP14R register  ***************/
10172 #define TAMP_BKP14R_Pos               (0U)
10173 #define TAMP_BKP14R_Msk               (0xFFFFFFFFUL << TAMP_BKP14R_Pos)          /*!< 0xFFFFFFFF */
10174 #define TAMP_BKP14R                   TAMP_BKP14R_Msk
10175 
10176 /********************  Bits definition for TAMP_BKP15R register  ***************/
10177 #define TAMP_BKP15R_Pos               (0U)
10178 #define TAMP_BKP15R_Msk               (0xFFFFFFFFUL << TAMP_BKP15R_Pos)          /*!< 0xFFFFFFFF */
10179 #define TAMP_BKP15R                   TAMP_BKP15R_Msk
10180 
10181 /********************  Bits definition for TAMP_BKP16R register  ***************/
10182 #define TAMP_BKP16R_Pos               (0U)
10183 #define TAMP_BKP16R_Msk               (0xFFFFFFFFUL << TAMP_BKP16R_Pos)          /*!< 0xFFFFFFFF */
10184 #define TAMP_BKP16R                   TAMP_BKP16R_Msk
10185 
10186 /********************  Bits definition for TAMP_BKP17R register  ***************/
10187 #define TAMP_BKP17R_Pos               (0U)
10188 #define TAMP_BKP17R_Msk               (0xFFFFFFFFUL << TAMP_BKP17R_Pos)          /*!< 0xFFFFFFFF */
10189 #define TAMP_BKP17R                   TAMP_BKP17R_Msk
10190 
10191 /********************  Bits definition for TAMP_BKP18R register  ***************/
10192 #define TAMP_BKP18R_Pos               (0U)
10193 #define TAMP_BKP18R_Msk               (0xFFFFFFFFUL << TAMP_BKP18R_Pos)          /*!< 0xFFFFFFFF */
10194 #define TAMP_BKP18R                   TAMP_BKP18R_Msk
10195 
10196 /********************  Bits definition for TAMP_BKP19R register  ***************/
10197 #define TAMP_BKP19R_Pos               (0U)
10198 #define TAMP_BKP19R_Msk               (0xFFFFFFFFUL << TAMP_BKP19R_Pos)          /*!< 0xFFFFFFFF */
10199 #define TAMP_BKP19R                   TAMP_BKP19R_Msk
10200 
10201 /********************  Bits definition for TAMP_BKP20R register  ***************/
10202 #define TAMP_BKP20R_Pos               (0U)
10203 #define TAMP_BKP20R_Msk               (0xFFFFFFFFUL << TAMP_BKP20R_Pos)          /*!< 0xFFFFFFFF */
10204 #define TAMP_BKP20R                   TAMP_BKP20R_Msk
10205 
10206 /********************  Bits definition for TAMP_BKP21R register  ***************/
10207 #define TAMP_BKP21R_Pos               (0U)
10208 #define TAMP_BKP21R_Msk               (0xFFFFFFFFUL << TAMP_BKP21R_Pos)          /*!< 0xFFFFFFFF */
10209 #define TAMP_BKP21R                   TAMP_BKP21R_Msk
10210 
10211 /********************  Bits definition for TAMP_BKP22R register  ***************/
10212 #define TAMP_BKP22R_Pos               (0U)
10213 #define TAMP_BKP22R_Msk               (0xFFFFFFFFUL << TAMP_BKP22R_Pos)          /*!< 0xFFFFFFFF */
10214 #define TAMP_BKP22R                   TAMP_BKP22R_Msk
10215 
10216 /********************  Bits definition for TAMP_BKP23R register  ***************/
10217 #define TAMP_BKP23R_Pos               (0U)
10218 #define TAMP_BKP23R_Msk               (0xFFFFFFFFUL << TAMP_BKP23R_Pos)          /*!< 0xFFFFFFFF */
10219 #define TAMP_BKP23R                   TAMP_BKP23R_Msk
10220 
10221 /********************  Bits definition for TAMP_BKP24R register  ***************/
10222 #define TAMP_BKP24R_Pos               (0U)
10223 #define TAMP_BKP24R_Msk               (0xFFFFFFFFUL << TAMP_BKP24R_Pos)          /*!< 0xFFFFFFFF */
10224 #define TAMP_BKP24R                   TAMP_BKP24R_Msk
10225 
10226 /********************  Bits definition for TAMP_BKP25R register  ***************/
10227 #define TAMP_BKP25R_Pos               (0U)
10228 #define TAMP_BKP25R_Msk               (0xFFFFFFFFUL << TAMP_BKP25R_Pos)          /*!< 0xFFFFFFFF */
10229 #define TAMP_BKP25R                   TAMP_BKP25R_Msk
10230 
10231 /********************  Bits definition for TAMP_BKP26R register  ***************/
10232 #define TAMP_BKP26R_Pos               (0U)
10233 #define TAMP_BKP26R_Msk               (0xFFFFFFFFUL << TAMP_BKP26R_Pos)          /*!< 0xFFFFFFFF */
10234 #define TAMP_BKP26R                   TAMP_BKP26R_Msk
10235 
10236 /********************  Bits definition for TAMP_BKP27R register  ***************/
10237 #define TAMP_BKP27R_Pos               (0U)
10238 #define TAMP_BKP27R_Msk               (0xFFFFFFFFUL << TAMP_BKP27R_Pos)          /*!< 0xFFFFFFFF */
10239 #define TAMP_BKP27R                   TAMP_BKP27R_Msk
10240 
10241 /********************  Bits definition for TAMP_BKP28R register  ***************/
10242 #define TAMP_BKP28R_Pos               (0U)
10243 #define TAMP_BKP28R_Msk               (0xFFFFFFFFUL << TAMP_BKP28R_Pos)          /*!< 0xFFFFFFFF */
10244 #define TAMP_BKP28R                   TAMP_BKP28R_Msk
10245 
10246 /********************  Bits definition for TAMP_BKP29R register  ***************/
10247 #define TAMP_BKP29R_Pos               (0U)
10248 #define TAMP_BKP29R_Msk               (0xFFFFFFFFUL << TAMP_BKP29R_Pos)          /*!< 0xFFFFFFFF */
10249 #define TAMP_BKP29R                   TAMP_BKP29R_Msk
10250 
10251 /********************  Bits definition for TAMP_BKP30R register  ***************/
10252 #define TAMP_BKP30R_Pos               (0U)
10253 #define TAMP_BKP30R_Msk               (0xFFFFFFFFUL << TAMP_BKP30R_Pos)          /*!< 0xFFFFFFFF */
10254 #define TAMP_BKP30R                   TAMP_BKP30R_Msk
10255 
10256 /********************  Bits definition for TAMP_BKP31R register  ***************/
10257 #define TAMP_BKP31R_Pos               (0U)
10258 #define TAMP_BKP31R_Msk               (0xFFFFFFFFUL << TAMP_BKP31R_Pos)          /*!< 0xFFFFFFFF */
10259 #define TAMP_BKP31R                   TAMP_BKP31R_Msk
10260 
10261 
10262 /******************************************************************************/
10263 /*                                                                            */
10264 /*                          Serial Audio Interface                            */
10265 /*                                                                            */
10266 /******************************************************************************/
10267 /********************  Bit definition for SAI_GCR register  *******************/
10268 #define SAI_GCR_SYNCIN_Pos         (0U)
10269 #define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000003 */
10270 #define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
10271 #define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000001 */
10272 #define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000002 */
10273 
10274 #define SAI_GCR_SYNCOUT_Pos        (4U)
10275 #define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000030 */
10276 #define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
10277 #define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000010 */
10278 #define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000020 */
10279 
10280 /*******************  Bit definition for SAI_xCR1 register  *******************/
10281 #define SAI_xCR1_MODE_Pos          (0U)
10282 #define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000003 */
10283 #define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */
10284 #define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000001 */
10285 #define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000002 */
10286 
10287 #define SAI_xCR1_PRTCFG_Pos        (2U)
10288 #define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x0000000C */
10289 #define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
10290 #define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x00000004 */
10291 #define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x00000008 */
10292 
10293 #define SAI_xCR1_DS_Pos            (5U)
10294 #define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                  /*!< 0x000000E0 */
10295 #define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */
10296 #define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                  /*!< 0x00000020 */
10297 #define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                  /*!< 0x00000040 */
10298 #define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                  /*!< 0x00000080 */
10299 
10300 #define SAI_xCR1_LSBFIRST_Pos      (8U)
10301 #define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)            /*!< 0x00000100 */
10302 #define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */
10303 #define SAI_xCR1_CKSTR_Pos         (9U)
10304 #define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)               /*!< 0x00000200 */
10305 #define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */
10306 
10307 #define SAI_xCR1_SYNCEN_Pos        (10U)
10308 #define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000C00 */
10309 #define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */
10310 #define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000400 */
10311 #define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000800 */
10312 
10313 #define SAI_xCR1_MONO_Pos          (12U)
10314 #define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                /*!< 0x00001000 */
10315 #define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */
10316 #define SAI_xCR1_OUTDRIV_Pos       (13U)
10317 #define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)             /*!< 0x00002000 */
10318 #define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */
10319 #define SAI_xCR1_SAIEN_Pos         (16U)
10320 #define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)               /*!< 0x00010000 */
10321 #define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */
10322 #define SAI_xCR1_DMAEN_Pos         (17U)
10323 #define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)               /*!< 0x00020000 */
10324 #define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */
10325 #define SAI_xCR1_NODIV_Pos         (19U)
10326 #define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)               /*!< 0x00080000 */
10327 #define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */
10328 
10329 #define SAI_xCR1_MCKDIV_Pos        (20U)
10330 #define SAI_xCR1_MCKDIV_Msk        (0x3FUL << SAI_xCR1_MCKDIV_Pos)             /*!< 0x03F00000 */
10331 #define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[5:0] (Master ClocK Divider)  */
10332 #define SAI_xCR1_MCKDIV_0          (0x00100000U)                               /*!<Bit 0  */
10333 #define SAI_xCR1_MCKDIV_1          (0x00200000U)                               /*!<Bit 1  */
10334 #define SAI_xCR1_MCKDIV_2          (0x00400000U)                               /*!<Bit 2  */
10335 #define SAI_xCR1_MCKDIV_3          (0x00800000U)                               /*!<Bit 3  */
10336 #define SAI_xCR1_MCKDIV_4          (0x01000000U)                               /*!<Bit 4  */
10337 #define SAI_xCR1_MCKDIV_5          (0x02000000U)                               /*!<Bit 5  */
10338 
10339 #define SAI_xCR1_OSR_Pos           (26U)
10340 #define SAI_xCR1_OSR_Msk           (0x1UL << SAI_xCR1_OSR_Pos)                 /*!< 0x04000000 */
10341 #define SAI_xCR1_OSR               SAI_xCR1_OSR_Msk                            /*!<Oversampling ratio for master clock */
10342 
10343 #define SAI_xCR1_MCKEN_Pos         (27U)
10344 #define SAI_xCR1_MCKEN_Msk         (0x1UL << SAI_xCR1_MCKEN_Pos)               /*!< 0x08000000 */
10345 #define SAI_xCR1_MCKEN             SAI_xCR1_MCKEN_Msk                          /*!<Master clock generation enable */
10346 
10347 /*******************  Bit definition for SAI_xCR2 register  *******************/
10348 #define SAI_xCR2_FTH_Pos           (0U)
10349 #define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000007 */
10350 #define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */
10351 #define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000001 */
10352 #define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000002 */
10353 #define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000004 */
10354 
10355 #define SAI_xCR2_FFLUSH_Pos        (3U)
10356 #define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)              /*!< 0x00000008 */
10357 #define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */
10358 #define SAI_xCR2_TRIS_Pos          (4U)
10359 #define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                /*!< 0x00000010 */
10360 #define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */
10361 #define SAI_xCR2_MUTE_Pos          (5U)
10362 #define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                /*!< 0x00000020 */
10363 #define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */
10364 #define SAI_xCR2_MUTEVAL_Pos       (6U)
10365 #define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)             /*!< 0x00000040 */
10366 #define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */
10367 
10368 
10369 #define SAI_xCR2_MUTECNT_Pos       (7U)
10370 #define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001F80 */
10371 #define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */
10372 #define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000080 */
10373 #define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000100 */
10374 #define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000200 */
10375 #define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000400 */
10376 #define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000800 */
10377 #define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001000 */
10378 
10379 #define SAI_xCR2_CPL_Pos           (13U)
10380 #define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                 /*!< 0x00002000 */
10381 #define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!<CPL mode                    */
10382 #define SAI_xCR2_COMP_Pos          (14U)
10383 #define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                /*!< 0x0000C000 */
10384 #define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */
10385 #define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                /*!< 0x00004000 */
10386 #define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                /*!< 0x00008000 */
10387 
10388 
10389 /******************  Bit definition for SAI_xFRCR register  *******************/
10390 #define SAI_xFRCR_FRL_Pos          (0U)
10391 #define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)               /*!< 0x000000FF */
10392 #define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](Frame length)  */
10393 #define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000001 */
10394 #define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000002 */
10395 #define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000004 */
10396 #define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000008 */
10397 #define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000010 */
10398 #define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000020 */
10399 #define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000040 */
10400 #define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000080 */
10401 
10402 #define SAI_xFRCR_FSALL_Pos        (8U)
10403 #define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00007F00 */
10404 #define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FRL[6:0] (Frame synchronization active level length)  */
10405 #define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00000100 */
10406 #define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00000200 */
10407 #define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00000400 */
10408 #define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00000800 */
10409 #define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00001000 */
10410 #define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00002000 */
10411 #define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00004000 */
10412 
10413 #define SAI_xFRCR_FSDEF_Pos        (16U)
10414 #define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)              /*!< 0x00010000 */
10415 #define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!< Frame Synchronization Definition */
10416 #define SAI_xFRCR_FSPOL_Pos        (17U)
10417 #define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)              /*!< 0x00020000 */
10418 #define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */
10419 #define SAI_xFRCR_FSOFF_Pos        (18U)
10420 #define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)              /*!< 0x00040000 */
10421 #define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */
10422 
10423 /******************  Bit definition for SAI_xSLOTR register  *******************/
10424 #define SAI_xSLOTR_FBOFF_Pos       (0U)
10425 #define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x0000001F */
10426 #define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FRL[4:0](First Bit Offset)  */
10427 #define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000001 */
10428 #define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000002 */
10429 #define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000004 */
10430 #define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000008 */
10431 #define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000010 */
10432 
10433 #define SAI_xSLOTR_SLOTSZ_Pos      (6U)
10434 #define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x000000C0 */
10435 #define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */
10436 #define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x00000040 */
10437 #define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x00000080 */
10438 
10439 #define SAI_xSLOTR_NBSLOT_Pos      (8U)
10440 #define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000F00 */
10441 #define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
10442 #define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000100 */
10443 #define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000200 */
10444 #define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000400 */
10445 #define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000800 */
10446 
10447 #define SAI_xSLOTR_SLOTEN_Pos      (16U)
10448 #define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)         /*!< 0xFFFF0000 */
10449 #define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */
10450 
10451 /*******************  Bit definition for SAI_xIMR register  *******************/
10452 #define SAI_xIMR_OVRUDRIE_Pos      (0U)
10453 #define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)            /*!< 0x00000001 */
10454 #define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */
10455 #define SAI_xIMR_MUTEDETIE_Pos     (1U)
10456 #define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)           /*!< 0x00000002 */
10457 #define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */
10458 #define SAI_xIMR_WCKCFGIE_Pos      (2U)
10459 #define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)            /*!< 0x00000004 */
10460 #define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */
10461 #define SAI_xIMR_FREQIE_Pos        (3U)
10462 #define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)              /*!< 0x00000008 */
10463 #define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */
10464 #define SAI_xIMR_CNRDYIE_Pos       (4U)
10465 #define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)             /*!< 0x00000010 */
10466 #define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */
10467 #define SAI_xIMR_AFSDETIE_Pos      (5U)
10468 #define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)            /*!< 0x00000020 */
10469 #define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */
10470 #define SAI_xIMR_LFSDETIE_Pos      (6U)
10471 #define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)            /*!< 0x00000040 */
10472 #define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */
10473 
10474 /********************  Bit definition for SAI_xSR register  *******************/
10475 #define SAI_xSR_OVRUDR_Pos         (0U)
10476 #define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)               /*!< 0x00000001 */
10477 #define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */
10478 #define SAI_xSR_MUTEDET_Pos        (1U)
10479 #define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)              /*!< 0x00000002 */
10480 #define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */
10481 #define SAI_xSR_WCKCFG_Pos         (2U)
10482 #define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)               /*!< 0x00000004 */
10483 #define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */
10484 #define SAI_xSR_FREQ_Pos           (3U)
10485 #define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                 /*!< 0x00000008 */
10486 #define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */
10487 #define SAI_xSR_CNRDY_Pos          (4U)
10488 #define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                /*!< 0x00000010 */
10489 #define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */
10490 #define SAI_xSR_AFSDET_Pos         (5U)
10491 #define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)               /*!< 0x00000020 */
10492 #define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */
10493 #define SAI_xSR_LFSDET_Pos         (6U)
10494 #define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)               /*!< 0x00000040 */
10495 #define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */
10496 
10497 #define SAI_xSR_FLVL_Pos           (16U)
10498 #define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00070000 */
10499 #define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */
10500 #define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00010000 */
10501 #define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00020000 */
10502 #define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00040000 */
10503 
10504 /******************  Bit definition for SAI_xCLRFR register  ******************/
10505 #define SAI_xCLRFR_COVRUDR_Pos     (0U)
10506 #define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)           /*!< 0x00000001 */
10507 #define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */
10508 #define SAI_xCLRFR_CMUTEDET_Pos    (1U)
10509 #define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)          /*!< 0x00000002 */
10510 #define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */
10511 #define SAI_xCLRFR_CWCKCFG_Pos     (2U)
10512 #define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)           /*!< 0x00000004 */
10513 #define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */
10514 #define SAI_xCLRFR_CFREQ_Pos       (3U)
10515 #define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)             /*!< 0x00000008 */
10516 #define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */
10517 #define SAI_xCLRFR_CCNRDY_Pos      (4U)
10518 #define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)            /*!< 0x00000010 */
10519 #define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */
10520 #define SAI_xCLRFR_CAFSDET_Pos     (5U)
10521 #define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)           /*!< 0x00000020 */
10522 #define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */
10523 #define SAI_xCLRFR_CLFSDET_Pos     (6U)
10524 #define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)           /*!< 0x00000040 */
10525 #define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */
10526 
10527 /******************  Bit definition for SAI_xDR register  ******************/
10528 #define SAI_xDR_DATA_Pos           (0U)
10529 #define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)          /*!< 0xFFFFFFFF */
10530 #define SAI_xDR_DATA               SAI_xDR_DATA_Msk
10531 
10532 /******************  Bit definition for SAI_PDMCR register  *******************/
10533 #define SAI_PDMCR_PDMEN_Pos        (0U)
10534 #define SAI_PDMCR_PDMEN_Msk        (0x1UL << SAI_PDMCR_PDMEN_Pos)              /*!< 0x00000001 */
10535 #define SAI_PDMCR_PDMEN            SAI_PDMCR_PDMEN_Msk                         /*!<PDM enable */
10536 
10537 #define SAI_PDMCR_MICNBR_Pos       (4U)
10538 #define SAI_PDMCR_MICNBR_Msk       (0x3UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000030 */
10539 #define SAI_PDMCR_MICNBR           SAI_PDMCR_MICNBR_Msk                        /*!<MICNBR[1:0] (Number of microphones) */
10540 #define SAI_PDMCR_MICNBR_0         (0x1UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000010 */
10541 #define SAI_PDMCR_MICNBR_1         (0x2UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000020 */
10542 
10543 #define SAI_PDMCR_CKEN1_Pos        (8U)
10544 #define SAI_PDMCR_CKEN1_Msk        (0x1UL << SAI_PDMCR_CKEN1_Pos)              /*!< 0x00000100 */
10545 #define SAI_PDMCR_CKEN1            SAI_PDMCR_CKEN1_Msk                         /*!<Clock 1 enable */
10546 #define SAI_PDMCR_CKEN2_Pos        (9U)
10547 #define SAI_PDMCR_CKEN2_Msk        (0x1UL << SAI_PDMCR_CKEN2_Pos)              /*!< 0x00000200 */
10548 #define SAI_PDMCR_CKEN2            SAI_PDMCR_CKEN2_Msk                         /*!<Clock 2 enable */
10549 #define SAI_PDMCR_CKEN3_Pos        (10U)
10550 #define SAI_PDMCR_CKEN3_Msk        (0x1UL << SAI_PDMCR_CKEN3_Pos)              /*!< 0x00000400 */
10551 #define SAI_PDMCR_CKEN3            SAI_PDMCR_CKEN3_Msk                         /*!<Clock 3 enable */
10552 #define SAI_PDMCR_CKEN4_Pos        (11U)
10553 #define SAI_PDMCR_CKEN4_Msk        (0x1UL << SAI_PDMCR_CKEN4_Pos)              /*!< 0x00000800 */
10554 #define SAI_PDMCR_CKEN4            SAI_PDMCR_CKEN4_Msk                         /*!<Clock 4 enable */
10555 
10556 /******************  Bit definition for SAI_PDMDLY register  ******************/
10557 #define SAI_PDMDLY_DLYM1L_Pos      (0U)
10558 #define SAI_PDMDLY_DLYM1L_Msk      (0x7UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000007 */
10559 #define SAI_PDMDLY_DLYM1L          SAI_PDMDLY_DLYM1L_Msk                       /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
10560 #define SAI_PDMDLY_DLYM1L_0        (0x1UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000001 */
10561 #define SAI_PDMDLY_DLYM1L_1        (0x2UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000002 */
10562 #define SAI_PDMDLY_DLYM1L_2        (0x4UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000004 */
10563 
10564 #define SAI_PDMDLY_DLYM1R_Pos      (4U)
10565 #define SAI_PDMDLY_DLYM1R_Msk      (0x7UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000070 */
10566 #define SAI_PDMDLY_DLYM1R          SAI_PDMDLY_DLYM1R_Msk                       /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
10567 #define SAI_PDMDLY_DLYM1R_0        (0x1UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000010 */
10568 #define SAI_PDMDLY_DLYM1R_1        (0x2UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000020 */
10569 #define SAI_PDMDLY_DLYM1R_2        (0x4UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000040 */
10570 
10571 #define SAI_PDMDLY_DLYM2L_Pos      (8U)
10572 #define SAI_PDMDLY_DLYM2L_Msk      (0x7UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000700 */
10573 #define SAI_PDMDLY_DLYM2L          SAI_PDMDLY_DLYM2L_Msk                       /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
10574 #define SAI_PDMDLY_DLYM2L_0        (0x1UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000100 */
10575 #define SAI_PDMDLY_DLYM2L_1        (0x2UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000200 */
10576 #define SAI_PDMDLY_DLYM2L_2        (0x4UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000400 */
10577 
10578 #define SAI_PDMDLY_DLYM2R_Pos      (12U)
10579 #define SAI_PDMDLY_DLYM2R_Msk      (0x7UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00007000 */
10580 #define SAI_PDMDLY_DLYM2R          SAI_PDMDLY_DLYM2R_Msk                       /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2) */
10581 #define SAI_PDMDLY_DLYM2R_0        (0x1UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00001000 */
10582 #define SAI_PDMDLY_DLYM2R_1        (0x2UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00002000 */
10583 #define SAI_PDMDLY_DLYM2R_2        (0x4UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00004000 */
10584 
10585 #define SAI_PDMDLY_DLYM3L_Pos      (16U)
10586 #define SAI_PDMDLY_DLYM3L_Msk      (0x7UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00070000 */
10587 #define SAI_PDMDLY_DLYM3L          SAI_PDMDLY_DLYM3L_Msk                       /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3) */
10588 #define SAI_PDMDLY_DLYM3L_0        (0x1UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00010000 */
10589 #define SAI_PDMDLY_DLYM3L_1        (0x2UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00020000 */
10590 #define SAI_PDMDLY_DLYM3L_2        (0x4UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00040000 */
10591 
10592 #define SAI_PDMDLY_DLYM3R_Pos      (20U)
10593 #define SAI_PDMDLY_DLYM3R_Msk      (0x7UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00700000 */
10594 #define SAI_PDMDLY_DLYM3R          SAI_PDMDLY_DLYM3R_Msk                       /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3) */
10595 #define SAI_PDMDLY_DLYM3R_0        (0x1UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00100000 */
10596 #define SAI_PDMDLY_DLYM3R_1        (0x2UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00200000 */
10597 #define SAI_PDMDLY_DLYM3R_2        (0x4UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00400000 */
10598 
10599 #define SAI_PDMDLY_DLYM4L_Pos      (24U)
10600 #define SAI_PDMDLY_DLYM4L_Msk      (0x7UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x07000000 */
10601 #define SAI_PDMDLY_DLYM4L          SAI_PDMDLY_DLYM4L_Msk                       /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4) */
10602 #define SAI_PDMDLY_DLYM4L_0        (0x1UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x01000000 */
10603 #define SAI_PDMDLY_DLYM4L_1        (0x2UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x02000000 */
10604 #define SAI_PDMDLY_DLYM4L_2        (0x4UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x04000000 */
10605 
10606 #define SAI_PDMDLY_DLYM4R_Pos      (28U)
10607 #define SAI_PDMDLY_DLYM4R_Msk      (0x7UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x70000000 */
10608 #define SAI_PDMDLY_DLYM4R          SAI_PDMDLY_DLYM4R_Msk                       /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4) */
10609 #define SAI_PDMDLY_DLYM4R_0        (0x1UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x10000000 */
10610 #define SAI_PDMDLY_DLYM4R_1        (0x2UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x20000000 */
10611 #define SAI_PDMDLY_DLYM4R_2        (0x4UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x40000000 */
10612 
10613 
10614 /******************************************************************************/
10615 /*                                                                            */
10616 /*                        Serial Peripheral Interface (SPI)                   */
10617 /*                                                                            */
10618 /******************************************************************************/
10619 /*
10620  * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
10621  */
10622 #define SPI_I2S_SUPPORT                       /*!< I2S support */
10623 
10624 /*******************  Bit definition for SPI_CR1 register  ********************/
10625 #define SPI_CR1_CPHA_Pos            (0U)
10626 #define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                /*!< 0x00000001 */
10627 #define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */
10628 #define SPI_CR1_CPOL_Pos            (1U)
10629 #define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                /*!< 0x00000002 */
10630 #define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */
10631 #define SPI_CR1_MSTR_Pos            (2U)
10632 #define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                /*!< 0x00000004 */
10633 #define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */
10634 
10635 #define SPI_CR1_BR_Pos              (3U)
10636 #define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                  /*!< 0x00000038 */
10637 #define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */
10638 #define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                  /*!< 0x00000008 */
10639 #define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                  /*!< 0x00000010 */
10640 #define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                  /*!< 0x00000020 */
10641 
10642 #define SPI_CR1_SPE_Pos             (6U)
10643 #define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000040 */
10644 #define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */
10645 #define SPI_CR1_LSBFIRST_Pos        (7U)
10646 #define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)            /*!< 0x00000080 */
10647 #define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */
10648 #define SPI_CR1_SSI_Pos             (8U)
10649 #define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00000100 */
10650 #define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */
10651 #define SPI_CR1_SSM_Pos             (9U)
10652 #define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                 /*!< 0x00000200 */
10653 #define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */
10654 #define SPI_CR1_RXONLY_Pos          (10U)
10655 #define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)              /*!< 0x00000400 */
10656 #define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */
10657 #define SPI_CR1_CRCL_Pos            (11U)
10658 #define SPI_CR1_CRCL_Msk            (0x1UL << SPI_CR1_CRCL_Pos)                /*!< 0x00000800 */
10659 #define SPI_CR1_CRCL                SPI_CR1_CRCL_Msk                           /*!< CRC Length */
10660 #define SPI_CR1_CRCNEXT_Pos         (12U)
10661 #define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)             /*!< 0x00001000 */
10662 #define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */
10663 #define SPI_CR1_CRCEN_Pos           (13U)
10664 #define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)               /*!< 0x00002000 */
10665 #define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */
10666 #define SPI_CR1_BIDIOE_Pos          (14U)
10667 #define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)              /*!< 0x00004000 */
10668 #define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */
10669 #define SPI_CR1_BIDIMODE_Pos        (15U)
10670 #define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)            /*!< 0x00008000 */
10671 #define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */
10672 
10673 /*******************  Bit definition for SPI_CR2 register  ********************/
10674 #define SPI_CR2_RXDMAEN_Pos         (0U)
10675 #define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)             /*!< 0x00000001 */
10676 #define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
10677 #define SPI_CR2_TXDMAEN_Pos         (1U)
10678 #define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)             /*!< 0x00000002 */
10679 #define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
10680 #define SPI_CR2_SSOE_Pos            (2U)
10681 #define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                /*!< 0x00000004 */
10682 #define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
10683 #define SPI_CR2_NSSP_Pos            (3U)
10684 #define SPI_CR2_NSSP_Msk            (0x1UL << SPI_CR2_NSSP_Pos)                /*!< 0x00000008 */
10685 #define SPI_CR2_NSSP                SPI_CR2_NSSP_Msk                           /*!< NSS pulse management Enable */
10686 #define SPI_CR2_FRF_Pos             (4U)
10687 #define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                 /*!< 0x00000010 */
10688 #define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
10689 #define SPI_CR2_ERRIE_Pos           (5U)
10690 #define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)               /*!< 0x00000020 */
10691 #define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
10692 #define SPI_CR2_RXNEIE_Pos          (6U)
10693 #define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)              /*!< 0x00000040 */
10694 #define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
10695 #define SPI_CR2_TXEIE_Pos           (7U)
10696 #define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)               /*!< 0x00000080 */
10697 #define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
10698 #define SPI_CR2_DS_Pos              (8U)
10699 #define SPI_CR2_DS_Msk              (0xFUL << SPI_CR2_DS_Pos)                  /*!< 0x00000F00 */
10700 #define SPI_CR2_DS                  SPI_CR2_DS_Msk                             /*!< DS[3:0] Data Size */
10701 #define SPI_CR2_DS_0                (0x1UL << SPI_CR2_DS_Pos)                  /*!< 0x00000100 */
10702 #define SPI_CR2_DS_1                (0x2UL << SPI_CR2_DS_Pos)                  /*!< 0x00000200 */
10703 #define SPI_CR2_DS_2                (0x4UL << SPI_CR2_DS_Pos)                  /*!< 0x00000400 */
10704 #define SPI_CR2_DS_3                (0x8UL << SPI_CR2_DS_Pos)                  /*!< 0x00000800 */
10705 #define SPI_CR2_FRXTH_Pos           (12U)
10706 #define SPI_CR2_FRXTH_Msk           (0x1UL << SPI_CR2_FRXTH_Pos)               /*!< 0x00001000 */
10707 #define SPI_CR2_FRXTH               SPI_CR2_FRXTH_Msk                          /*!< FIFO reception Threshold */
10708 #define SPI_CR2_LDMARX_Pos          (13U)
10709 #define SPI_CR2_LDMARX_Msk          (0x1UL << SPI_CR2_LDMARX_Pos)              /*!< 0x00002000 */
10710 #define SPI_CR2_LDMARX              SPI_CR2_LDMARX_Msk                         /*!< Last DMA transfer for reception */
10711 #define SPI_CR2_LDMATX_Pos          (14U)
10712 #define SPI_CR2_LDMATX_Msk          (0x1UL << SPI_CR2_LDMATX_Pos)              /*!< 0x00004000 */
10713 #define SPI_CR2_LDMATX              SPI_CR2_LDMATX_Msk                         /*!< Last DMA transfer for transmission */
10714 
10715 /********************  Bit definition for SPI_SR register  ********************/
10716 #define SPI_SR_RXNE_Pos             (0U)
10717 #define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                 /*!< 0x00000001 */
10718 #define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
10719 #define SPI_SR_TXE_Pos              (1U)
10720 #define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                  /*!< 0x00000002 */
10721 #define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
10722 #define SPI_SR_CHSIDE_Pos           (2U)
10723 #define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)               /*!< 0x00000004 */
10724 #define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
10725 #define SPI_SR_UDR_Pos              (3U)
10726 #define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000008 */
10727 #define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
10728 #define SPI_SR_CRCERR_Pos           (4U)
10729 #define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)               /*!< 0x00000010 */
10730 #define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
10731 #define SPI_SR_MODF_Pos             (5U)
10732 #define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000020 */
10733 #define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
10734 #define SPI_SR_OVR_Pos              (6U)
10735 #define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */
10736 #define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
10737 #define SPI_SR_BSY_Pos              (7U)
10738 #define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                  /*!< 0x00000080 */
10739 #define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
10740 #define SPI_SR_FRE_Pos              (8U)
10741 #define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                  /*!< 0x00000100 */
10742 #define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */
10743 #define SPI_SR_FRLVL_Pos            (9U)
10744 #define SPI_SR_FRLVL_Msk            (0x3UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000600 */
10745 #define SPI_SR_FRLVL                SPI_SR_FRLVL_Msk                           /*!< FIFO Reception Level */
10746 #define SPI_SR_FRLVL_0              (0x1UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000200 */
10747 #define SPI_SR_FRLVL_1              (0x2UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000400 */
10748 #define SPI_SR_FTLVL_Pos            (11U)
10749 #define SPI_SR_FTLVL_Msk            (0x3UL << SPI_SR_FTLVL_Pos)                /*!< 0x00001800 */
10750 #define SPI_SR_FTLVL                SPI_SR_FTLVL_Msk                           /*!< FIFO Transmission Level */
10751 #define SPI_SR_FTLVL_0              (0x1UL << SPI_SR_FTLVL_Pos)                /*!< 0x00000800 */
10752 #define SPI_SR_FTLVL_1              (0x2UL << SPI_SR_FTLVL_Pos)                /*!< 0x00001000 */
10753 
10754 /********************  Bit definition for SPI_DR register  ********************/
10755 #define SPI_DR_DR_Pos               (0U)
10756 #define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                /*!< 0x0000FFFF */
10757 #define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */
10758 
10759 /*******************  Bit definition for SPI_CRCPR register  ******************/
10760 #define SPI_CRCPR_CRCPOLY_Pos       (0U)
10761 #define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)        /*!< 0x0000FFFF */
10762 #define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */
10763 
10764 /******************  Bit definition for SPI_RXCRCR register  ******************/
10765 #define SPI_RXCRCR_RXCRC_Pos        (0U)
10766 #define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)         /*!< 0x0000FFFF */
10767 #define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */
10768 
10769 /******************  Bit definition for SPI_TXCRCR register  ******************/
10770 #define SPI_TXCRCR_TXCRC_Pos        (0U)
10771 #define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)         /*!< 0x0000FFFF */
10772 #define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */
10773 
10774 /******************  Bit definition for SPI_I2SCFGR register  *****************/
10775 #define SPI_I2SCFGR_CHLEN_Pos       (0U)
10776 #define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000001 */
10777 #define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
10778 #define SPI_I2SCFGR_DATLEN_Pos      (1U)
10779 #define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000006 */
10780 #define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */
10781 #define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000002 */
10782 #define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000004 */
10783 #define SPI_I2SCFGR_CKPOL_Pos       (3U)
10784 #define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000008 */
10785 #define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */
10786 #define SPI_I2SCFGR_I2SSTD_Pos      (4U)
10787 #define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */
10788 #define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
10789 #define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000010 */
10790 #define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000020 */
10791 #define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
10792 #define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */
10793 #define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */
10794 #define SPI_I2SCFGR_I2SCFG_Pos      (8U)
10795 #define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000300 */
10796 #define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
10797 #define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000100 */
10798 #define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000200 */
10799 #define SPI_I2SCFGR_I2SE_Pos        (10U)
10800 #define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)            /*!< 0x00000400 */
10801 #define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */
10802 #define SPI_I2SCFGR_I2SMOD_Pos      (11U)
10803 #define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000800 */
10804 #define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
10805 #define SPI_I2SCFGR_ASTRTEN_Pos     (12U)
10806 #define SPI_I2SCFGR_ASTRTEN_Msk     (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)         /*!< 0x00001000 */
10807 #define SPI_I2SCFGR_ASTRTEN         SPI_I2SCFGR_ASTRTEN_Msk                    /*!<Asynchronous start enable */
10808 
10809 /******************  Bit definition for SPI_I2SPR register  *******************/
10810 #define SPI_I2SPR_I2SDIV_Pos        (0U)
10811 #define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)           /*!< 0x000000FF */
10812 #define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */
10813 #define SPI_I2SPR_ODD_Pos           (8U)
10814 #define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)               /*!< 0x00000100 */
10815 #define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
10816 #define SPI_I2SPR_MCKOE_Pos         (9U)
10817 #define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)             /*!< 0x00000200 */
10818 #define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */
10819 
10820 /******************************************************************************/
10821 /*                                                                            */
10822 /*                                 SYSCFG                                     */
10823 /*                                                                            */
10824 /******************************************************************************/
10825 /******************  Bit definition for SYSCFG_MEMRMP register ***************/
10826 #define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)
10827 #define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000007 */
10828 #define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
10829 #define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000001 */
10830 #define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000002 */
10831 #define SYSCFG_MEMRMP_MEM_MODE_2        (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000004 */
10832 
10833 #define SYSCFG_MEMRMP_FB_MODE_Pos       (8U)
10834 #define SYSCFG_MEMRMP_FB_MODE_Msk       (0x1UL << SYSCFG_MEMRMP_FB_MODE_Pos)   /*!< 0x00000100 */
10835 #define SYSCFG_MEMRMP_FB_MODE           SYSCFG_MEMRMP_FB_MODE_Msk              /*!< User Flash Bank mode selection */
10836 
10837 /******************  Bit definition for SYSCFG_CFGR1 register ******************/
10838 #define SYSCFG_CFGR1_BOOSTEN_Pos        (8U)
10839 #define SYSCFG_CFGR1_BOOSTEN_Msk        (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos)    /*!< 0x00000100 */
10840 #define SYSCFG_CFGR1_BOOSTEN            SYSCFG_CFGR1_BOOSTEN_Msk               /*!< I/O analog switch voltage booster enable */
10841 #define SYSCFG_CFGR1_ANASWVDD_Pos       (9U)
10842 #define SYSCFG_CFGR1_ANASWVDD_Msk       (0x1UL << SYSCFG_CFGR1_ANASWVDD_Pos)    /*!< 0x00000200 */
10843 #define SYSCFG_CFGR1_ANASWVDD           SYSCFG_CFGR1_ANASWVDD_Msk               /*!< GPIO analog switch control voltage selection */
10844 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos    (16U)
10845 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)/*!< 0x00010000 */
10846 #define SYSCFG_CFGR1_I2C_PB6_FMP        SYSCFG_CFGR1_I2C_PB6_FMP_Msk           /*!< I2C PB6 Fast mode plus */
10847 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos    (17U)
10848 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)/*!< 0x00020000 */
10849 #define SYSCFG_CFGR1_I2C_PB7_FMP        SYSCFG_CFGR1_I2C_PB7_FMP_Msk           /*!< I2C PB7 Fast mode plus */
10850 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos    (18U)
10851 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)/*!< 0x00040000 */
10852 #define SYSCFG_CFGR1_I2C_PB8_FMP        SYSCFG_CFGR1_I2C_PB8_FMP_Msk           /*!< I2C PB8 Fast mode plus */
10853 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos    (19U)
10854 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)/*!< 0x00080000 */
10855 #define SYSCFG_CFGR1_I2C_PB9_FMP        SYSCFG_CFGR1_I2C_PB9_FMP_Msk           /*!< I2C PB9 Fast mode plus */
10856 #define SYSCFG_CFGR1_I2C1_FMP_Pos       (20U)
10857 #define SYSCFG_CFGR1_I2C1_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)   /*!< 0x00100000 */
10858 #define SYSCFG_CFGR1_I2C1_FMP           SYSCFG_CFGR1_I2C1_FMP_Msk              /*!< I2C1 Fast mode plus */
10859 #define SYSCFG_CFGR1_I2C2_FMP_Pos       (21U)
10860 #define SYSCFG_CFGR1_I2C2_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos)   /*!< 0x00200000 */
10861 #define SYSCFG_CFGR1_I2C2_FMP           SYSCFG_CFGR1_I2C2_FMP_Msk              /*!< I2C2 Fast mode plus */
10862 #define SYSCFG_CFGR1_I2C3_FMP_Pos       (22U)
10863 #define SYSCFG_CFGR1_I2C3_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos)   /*!< 0x00400000 */
10864 #define SYSCFG_CFGR1_I2C3_FMP           SYSCFG_CFGR1_I2C3_FMP_Msk              /*!< I2C3 Fast mode plus */
10865 #define SYSCFG_CFGR1_I2C4_FMP_Pos       (23U)
10866 #define SYSCFG_CFGR1_I2C4_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C4_FMP_Pos)   /*!< 0x00800000 */
10867 #define SYSCFG_CFGR1_I2C4_FMP           SYSCFG_CFGR1_I2C4_FMP_Msk              /*!< I2C4 Fast mode plus */
10868 #define SYSCFG_CFGR1_FPU_IE_0           (0x04000000U)                          /*!<  Invalid operation Interrupt enable */
10869 #define SYSCFG_CFGR1_FPU_IE_1           (0x08000000U)                          /*!<  Divide-by-zero Interrupt enable */
10870 #define SYSCFG_CFGR1_FPU_IE_2           (0x10000000U)                          /*!<  Underflow Interrupt enable */
10871 #define SYSCFG_CFGR1_FPU_IE_3           (0x20000000U)                          /*!<  Overflow Interrupt enable */
10872 #define SYSCFG_CFGR1_FPU_IE_4           (0x40000000U)                          /*!<  Input denormal Interrupt enable */
10873 #define SYSCFG_CFGR1_FPU_IE_5           (0x80000000U)                          /*!<  Inexact Interrupt enable (interrupt disabled at reset) */
10874 
10875 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
10876 #define SYSCFG_EXTICR1_EXTI0_Pos        (0U)
10877 #define SYSCFG_EXTICR1_EXTI0_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x0000000F */
10878 #define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */
10879 #define SYSCFG_EXTICR1_EXTI1_Pos        (4U)
10880 #define SYSCFG_EXTICR1_EXTI1_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x000000F0 */
10881 #define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */
10882 #define SYSCFG_EXTICR1_EXTI2_Pos        (8U)
10883 #define SYSCFG_EXTICR1_EXTI2_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000F00 */
10884 #define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */
10885 #define SYSCFG_EXTICR1_EXTI3_Pos        (12U)
10886 #define SYSCFG_EXTICR1_EXTI3_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x0000F000 */
10887 #define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */
10888 
10889 /**
10890   * @brief   EXTI0 configuration
10891   */
10892 #define SYSCFG_EXTICR1_EXTI0_PA             (0x00000000U)                      /*!<PA[0] pin */
10893 #define SYSCFG_EXTICR1_EXTI0_PB             (0x00000001U)                      /*!<PB[0] pin */
10894 #define SYSCFG_EXTICR1_EXTI0_PC             (0x00000002U)                      /*!<PC[0] pin */
10895 #define SYSCFG_EXTICR1_EXTI0_PD             (0x00000003U)                      /*!<PD[0] pin */
10896 #define SYSCFG_EXTICR1_EXTI0_PE             (0x00000004U)                      /*!<PE[0] pin */
10897 #define SYSCFG_EXTICR1_EXTI0_PF             (0x00000005U)                      /*!<PF[0] pin */
10898 #define SYSCFG_EXTICR1_EXTI0_PG             (0x00000006U)                      /*!<PG[0] pin */
10899 
10900 /**
10901   * @brief   EXTI1 configuration
10902   */
10903 #define SYSCFG_EXTICR1_EXTI1_PA             (0x00000000U)                      /*!<PA[1] pin */
10904 #define SYSCFG_EXTICR1_EXTI1_PB             (0x00000010U)                      /*!<PB[1] pin */
10905 #define SYSCFG_EXTICR1_EXTI1_PC             (0x00000020U)                      /*!<PC[1] pin */
10906 #define SYSCFG_EXTICR1_EXTI1_PD             (0x00000030U)                      /*!<PD[1] pin */
10907 #define SYSCFG_EXTICR1_EXTI1_PE             (0x00000040U)                      /*!<PE[1] pin */
10908 #define SYSCFG_EXTICR1_EXTI1_PF             (0x00000050U)                      /*!<PF[1] pin */
10909 #define SYSCFG_EXTICR1_EXTI1_PG             (0x00000060U)                      /*!<PG[1] pin */
10910 
10911 /**
10912   * @brief   EXTI2 configuration
10913   */
10914 #define SYSCFG_EXTICR1_EXTI2_PA             (0x00000000U)                      /*!<PA[2] pin */
10915 #define SYSCFG_EXTICR1_EXTI2_PB             (0x00000100U)                      /*!<PB[2] pin */
10916 #define SYSCFG_EXTICR1_EXTI2_PC             (0x00000200U)                      /*!<PC[2] pin */
10917 #define SYSCFG_EXTICR1_EXTI2_PD             (0x00000300U)                      /*!<PD[2] pin */
10918 #define SYSCFG_EXTICR1_EXTI2_PE             (0x00000400U)                      /*!<PE[2] pin */
10919 #define SYSCFG_EXTICR1_EXTI2_PF             (0x00000500U)                      /*!<PF[2] pin */
10920 #define SYSCFG_EXTICR1_EXTI2_PG             (0x00000600U)                      /*!<PG[2] pin */
10921 
10922 /**
10923   * @brief   EXTI3 configuration
10924   */
10925 #define SYSCFG_EXTICR1_EXTI3_PA             (0x00000000U)                      /*!<PA[3] pin */
10926 #define SYSCFG_EXTICR1_EXTI3_PB             (0x00001000U)                      /*!<PB[3] pin */
10927 #define SYSCFG_EXTICR1_EXTI3_PC             (0x00002000U)                      /*!<PC[3] pin */
10928 #define SYSCFG_EXTICR1_EXTI3_PD             (0x00003000U)                      /*!<PD[3] pin */
10929 #define SYSCFG_EXTICR1_EXTI3_PE             (0x00004000U)                      /*!<PE[3] pin */
10930 #define SYSCFG_EXTICR1_EXTI3_PF             (0x00005000U)                      /*!<PF[3] pin */
10931 #define SYSCFG_EXTICR1_EXTI3_PG             (0x00006000U)                      /*!<PG[3] pin */
10932 
10933 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
10934 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
10935 #define SYSCFG_EXTICR2_EXTI4_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x0000000F */
10936 #define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */
10937 #define SYSCFG_EXTICR2_EXTI5_Pos        (4U)
10938 #define SYSCFG_EXTICR2_EXTI5_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x000000F0 */
10939 #define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */
10940 #define SYSCFG_EXTICR2_EXTI6_Pos        (8U)
10941 #define SYSCFG_EXTICR2_EXTI6_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000F00 */
10942 #define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */
10943 #define SYSCFG_EXTICR2_EXTI7_Pos        (12U)
10944 #define SYSCFG_EXTICR2_EXTI7_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x0000F000 */
10945 #define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */
10946 
10947 /**
10948   * @brief   EXTI4 configuration
10949   */
10950 #define SYSCFG_EXTICR2_EXTI4_PA             (0x00000000U)                      /*!<PA[4] pin */
10951 #define SYSCFG_EXTICR2_EXTI4_PB             (0x00000001U)                      /*!<PB[4] pin */
10952 #define SYSCFG_EXTICR2_EXTI4_PC             (0x00000002U)                      /*!<PC[4] pin */
10953 #define SYSCFG_EXTICR2_EXTI4_PD             (0x00000003U)                      /*!<PD[4] pin */
10954 #define SYSCFG_EXTICR2_EXTI4_PE             (0x00000004U)                      /*!<PE[4] pin */
10955 #define SYSCFG_EXTICR2_EXTI4_PF             (0x00000005U)                      /*!<PF[4] pin */
10956 #define SYSCFG_EXTICR2_EXTI4_PG             (0x00000006U)                      /*!<PG[4] pin */
10957 
10958 /**
10959   * @brief   EXTI5 configuration
10960   */
10961 #define SYSCFG_EXTICR2_EXTI5_PA             (0x00000000U)                      /*!<PA[5] pin */
10962 #define SYSCFG_EXTICR2_EXTI5_PB             (0x00000010U)                      /*!<PB[5] pin */
10963 #define SYSCFG_EXTICR2_EXTI5_PC             (0x00000020U)                      /*!<PC[5] pin */
10964 #define SYSCFG_EXTICR2_EXTI5_PD             (0x00000030U)                      /*!<PD[5] pin */
10965 #define SYSCFG_EXTICR2_EXTI5_PE             (0x00000040U)                      /*!<PE[5] pin */
10966 #define SYSCFG_EXTICR2_EXTI5_PF             (0x00000050U)                      /*!<PF[5] pin */
10967 #define SYSCFG_EXTICR2_EXTI5_PG             (0x00000060U)                      /*!<PG[5] pin */
10968 
10969 /**
10970   * @brief   EXTI6 configuration
10971   */
10972 #define SYSCFG_EXTICR2_EXTI6_PA             (0x00000000U)                      /*!<PA[6] pin */
10973 #define SYSCFG_EXTICR2_EXTI6_PB             (0x00000100U)                      /*!<PB[6] pin */
10974 #define SYSCFG_EXTICR2_EXTI6_PC             (0x00000200U)                      /*!<PC[6] pin */
10975 #define SYSCFG_EXTICR2_EXTI6_PD             (0x00000300U)                      /*!<PD[6] pin */
10976 #define SYSCFG_EXTICR2_EXTI6_PE             (0x00000400U)                      /*!<PE[6] pin */
10977 #define SYSCFG_EXTICR2_EXTI6_PF             (0x00000500U)                      /*!<PF[6] pin */
10978 #define SYSCFG_EXTICR2_EXTI6_PG             (0x00000600U)                      /*!<PG[6] pin */
10979 
10980 /**
10981   * @brief   EXTI7 configuration
10982   */
10983 #define SYSCFG_EXTICR2_EXTI7_PA             (0x00000000U)                      /*!<PA[7] pin */
10984 #define SYSCFG_EXTICR2_EXTI7_PB             (0x00001000U)                      /*!<PB[7] pin */
10985 #define SYSCFG_EXTICR2_EXTI7_PC             (0x00002000U)                      /*!<PC[7] pin */
10986 #define SYSCFG_EXTICR2_EXTI7_PD             (0x00003000U)                      /*!<PD[7] pin */
10987 #define SYSCFG_EXTICR2_EXTI7_PE             (0x00004000U)                      /*!<PE[7] pin */
10988 #define SYSCFG_EXTICR2_EXTI7_PF             (0x00005000U)                      /*!<PF[7] pin */
10989 #define SYSCFG_EXTICR2_EXTI7_PG             (0x00006000U)                      /*!<PG[7] pin */
10990 
10991 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
10992 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
10993 #define SYSCFG_EXTICR3_EXTI8_Msk        (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x0000000F */
10994 #define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */
10995 #define SYSCFG_EXTICR3_EXTI9_Pos        (4U)
10996 #define SYSCFG_EXTICR3_EXTI9_Msk        (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x000000F0 */
10997 #define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */
10998 #define SYSCFG_EXTICR3_EXTI10_Pos       (8U)
10999 #define SYSCFG_EXTICR3_EXTI10_Msk       (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000F00 */
11000 #define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */
11001 #define SYSCFG_EXTICR3_EXTI11_Pos       (12U)
11002 #define SYSCFG_EXTICR3_EXTI11_Msk       (0x7UL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x0000F000 */
11003 #define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */
11004 
11005 /**
11006   * @brief   EXTI8 configuration
11007   */
11008 #define SYSCFG_EXTICR3_EXTI8_PA             (0x00000000U)                      /*!<PA[8] pin */
11009 #define SYSCFG_EXTICR3_EXTI8_PB             (0x00000001U)                      /*!<PB[8] pin */
11010 #define SYSCFG_EXTICR3_EXTI8_PC             (0x00000002U)                      /*!<PC[8] pin */
11011 #define SYSCFG_EXTICR3_EXTI8_PD             (0x00000003U)                      /*!<PD[8] pin */
11012 #define SYSCFG_EXTICR3_EXTI8_PE             (0x00000004U)                      /*!<PE[8] pin */
11013 #define SYSCFG_EXTICR3_EXTI8_PF             (0x00000005U)                      /*!<PF[8] pin */
11014 #define SYSCFG_EXTICR3_EXTI8_PG             (0x00000006U)                      /*!<PG[8] pin */
11015 
11016 /**
11017   * @brief   EXTI9 configuration
11018   */
11019 #define SYSCFG_EXTICR3_EXTI9_PA             (0x00000000U)                      /*!<PA[9] pin */
11020 #define SYSCFG_EXTICR3_EXTI9_PB             (0x00000010U)                      /*!<PB[9] pin */
11021 #define SYSCFG_EXTICR3_EXTI9_PC             (0x00000020U)                      /*!<PC[9] pin */
11022 #define SYSCFG_EXTICR3_EXTI9_PD             (0x00000030U)                      /*!<PD[9] pin */
11023 #define SYSCFG_EXTICR3_EXTI9_PE             (0x00000040U)                      /*!<PE[9] pin */
11024 #define SYSCFG_EXTICR3_EXTI9_PF             (0x00000050U)                      /*!<PF[9] pin */
11025 #define SYSCFG_EXTICR3_EXTI9_PG             (0x00000060U)                      /*!<PG[9] pin */
11026 
11027 /**
11028   * @brief   EXTI10 configuration
11029   */
11030 #define SYSCFG_EXTICR3_EXTI10_PA            (0x00000000U)                      /*!<PA[10] pin */
11031 #define SYSCFG_EXTICR3_EXTI10_PB            (0x00000100U)                      /*!<PB[10] pin */
11032 #define SYSCFG_EXTICR3_EXTI10_PC            (0x00000200U)                      /*!<PC[10] pin */
11033 #define SYSCFG_EXTICR3_EXTI10_PD            (0x00000300U)                      /*!<PD[10] pin */
11034 #define SYSCFG_EXTICR3_EXTI10_PE            (0x00000400U)                      /*!<PE[10] pin */
11035 #define SYSCFG_EXTICR3_EXTI10_PF            (0x00000500U)                      /*!<PF[10] pin */
11036 
11037 /**
11038   * @brief   EXTI11 configuration
11039   */
11040 #define SYSCFG_EXTICR3_EXTI11_PA            (0x00000000U)                      /*!<PA[11] pin */
11041 #define SYSCFG_EXTICR3_EXTI11_PB            (0x00001000U)                      /*!<PB[11] pin */
11042 #define SYSCFG_EXTICR3_EXTI11_PC            (0x00002000U)                      /*!<PC[11] pin */
11043 #define SYSCFG_EXTICR3_EXTI11_PD            (0x00003000U)                      /*!<PD[11] pin */
11044 #define SYSCFG_EXTICR3_EXTI11_PE            (0x00004000U)                      /*!<PE[11] pin */
11045 #define SYSCFG_EXTICR3_EXTI11_PF            (0x00005000U)                      /*!<PF[11] pin */
11046 
11047 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
11048 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
11049 #define SYSCFG_EXTICR4_EXTI12_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x00000007 */
11050 #define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */
11051 #define SYSCFG_EXTICR4_EXTI13_Pos       (4U)
11052 #define SYSCFG_EXTICR4_EXTI13_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x00000070 */
11053 #define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */
11054 #define SYSCFG_EXTICR4_EXTI14_Pos       (8U)
11055 #define SYSCFG_EXTICR4_EXTI14_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000700 */
11056 #define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */
11057 #define SYSCFG_EXTICR4_EXTI15_Pos       (12U)
11058 #define SYSCFG_EXTICR4_EXTI15_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x00007000 */
11059 #define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */
11060 
11061 /**
11062   * @brief   EXTI12 configuration
11063   */
11064 #define SYSCFG_EXTICR4_EXTI12_PA            (0x00000000U)                      /*!<PA[12] pin */
11065 #define SYSCFG_EXTICR4_EXTI12_PB            (0x00000001U)                      /*!<PB[12] pin */
11066 #define SYSCFG_EXTICR4_EXTI12_PC            (0x00000002U)                      /*!<PC[12] pin */
11067 #define SYSCFG_EXTICR4_EXTI12_PD            (0x00000003U)                      /*!<PD[12] pin */
11068 #define SYSCFG_EXTICR4_EXTI12_PE            (0x00000004U)                      /*!<PE[12] pin */
11069 #define SYSCFG_EXTICR4_EXTI12_PF            (0x00000005U)                      /*!<PF[12] pin */
11070 
11071 /**
11072   * @brief   EXTI13 configuration
11073   */
11074 #define SYSCFG_EXTICR4_EXTI13_PA            (0x00000000U)                      /*!<PA[13] pin */
11075 #define SYSCFG_EXTICR4_EXTI13_PB            (0x00000010U)                      /*!<PB[13] pin */
11076 #define SYSCFG_EXTICR4_EXTI13_PC            (0x00000020U)                      /*!<PC[13] pin */
11077 #define SYSCFG_EXTICR4_EXTI13_PD            (0x00000030U)                      /*!<PD[13] pin */
11078 #define SYSCFG_EXTICR4_EXTI13_PE            (0x00000040U)                      /*!<PE[13] pin */
11079 #define SYSCFG_EXTICR4_EXTI13_PF            (0x00000050U)                      /*!<PF[13] pin */
11080 
11081 /**
11082   * @brief   EXTI14 configuration
11083   */
11084 #define SYSCFG_EXTICR4_EXTI14_PA            (0x00000000U)                      /*!<PA[14] pin */
11085 #define SYSCFG_EXTICR4_EXTI14_PB            (0x00000100U)                      /*!<PB[14] pin */
11086 #define SYSCFG_EXTICR4_EXTI14_PC            (0x00000200U)                      /*!<PC[14] pin */
11087 #define SYSCFG_EXTICR4_EXTI14_PD            (0x00000300U)                      /*!<PD[14] pin */
11088 #define SYSCFG_EXTICR4_EXTI14_PE            (0x00000400U)                      /*!<PE[14] pin */
11089 #define SYSCFG_EXTICR4_EXTI14_PF            (0x00000500U)                      /*!<PF[14] pin */
11090 
11091 /**
11092   * @brief   EXTI15 configuration
11093   */
11094 #define SYSCFG_EXTICR4_EXTI15_PA            (0x00000000U)                      /*!<PA[15] pin */
11095 #define SYSCFG_EXTICR4_EXTI15_PB            (0x00001000U)                      /*!<PB[15] pin */
11096 #define SYSCFG_EXTICR4_EXTI15_PC            (0x00002000U)                      /*!<PC[15] pin */
11097 #define SYSCFG_EXTICR4_EXTI15_PD            (0x00003000U)                      /*!<PD[15] pin */
11098 #define SYSCFG_EXTICR4_EXTI15_PE            (0x00004000U)                      /*!<PE[15] pin */
11099 #define SYSCFG_EXTICR4_EXTI15_PF            (0x00005000U)                      /*!<PF[15] pin */
11100 
11101 /******************  Bit definition for SYSCFG_SCSR register  ****************/
11102 #define SYSCFG_SCSR_CCMER_Pos         (0U)
11103 #define SYSCFG_SCSR_CCMER_Msk         (0x1UL << SYSCFG_SCSR_CCMER_Pos)      /*!< 0x00000001 */
11104 #define SYSCFG_SCSR_CCMER             SYSCFG_SCSR_CCMER_Msk                 /*!< CCMSRAM  Erase Request */
11105 #define SYSCFG_SCSR_CCMBSY_Pos        (1U)
11106 #define SYSCFG_SCSR_CCMBSY_Msk        (0x1UL << SYSCFG_SCSR_CCMBSY_Pos)     /*!< 0x00000002 */
11107 #define SYSCFG_SCSR_CCMBSY            SYSCFG_SCSR_CCMBSY_Msk                /*!< CCMSRAM  Erase Ongoing */
11108 
11109 /******************  Bit definition for SYSCFG_CFGR2 register  ****************/
11110 #define SYSCFG_CFGR2_CLL_Pos            (0U)
11111 #define SYSCFG_CFGR2_CLL_Msk            (0x1UL << SYSCFG_CFGR2_CLL_Pos)        /*!< 0x00000001 */
11112 #define SYSCFG_CFGR2_CLL                SYSCFG_CFGR2_CLL_Msk                   /*!< Core Lockup Lock */
11113 #define SYSCFG_CFGR2_SPL_Pos            (1U)
11114 #define SYSCFG_CFGR2_SPL_Msk            (0x1UL << SYSCFG_CFGR2_SPL_Pos)        /*!< 0x00000002 */
11115 #define SYSCFG_CFGR2_SPL                SYSCFG_CFGR2_SPL_Msk                   /*!< SRAM Parity Lock*/
11116 #define SYSCFG_CFGR2_PVDL_Pos           (2U)
11117 #define SYSCFG_CFGR2_PVDL_Msk           (0x1UL << SYSCFG_CFGR2_PVDL_Pos)       /*!< 0x00000004 */
11118 #define SYSCFG_CFGR2_PVDL               SYSCFG_CFGR2_PVDL_Msk                  /*!<  PVD Lock */
11119 #define SYSCFG_CFGR2_ECCL_Pos           (3U)
11120 #define SYSCFG_CFGR2_ECCL_Msk           (0x1UL << SYSCFG_CFGR2_ECCL_Pos)       /*!< 0x00000008 */
11121 #define SYSCFG_CFGR2_ECCL               SYSCFG_CFGR2_ECCL_Msk                  /*!< ECC Lock*/
11122 #define SYSCFG_CFGR2_SPF_Pos            (8U)
11123 #define SYSCFG_CFGR2_SPF_Msk            (0x1UL << SYSCFG_CFGR2_SPF_Pos)        /*!< 0x00000100 */
11124 #define SYSCFG_CFGR2_SPF                SYSCFG_CFGR2_SPF_Msk                   /*!< SRAM Parity Flag */
11125 
11126 /******************  Bit definition for SYSCFG_SWPR register  ****************/
11127 #define SYSCFG_SWPR_PAGE0_Pos          (0U)
11128 #define SYSCFG_SWPR_PAGE0_Msk          (0x1UL << SYSCFG_SWPR_PAGE0_Pos)       /*!< 0x00000001 */
11129 #define SYSCFG_SWPR_PAGE0              (SYSCFG_SWPR_PAGE0_Msk)                /*!< CCMSRAM  Write protection page 0 */
11130 #define SYSCFG_SWPR_PAGE1_Pos          (1U)
11131 #define SYSCFG_SWPR_PAGE1_Msk          (0x1UL << SYSCFG_SWPR_PAGE1_Pos)       /*!< 0x00000002 */
11132 #define SYSCFG_SWPR_PAGE1              (SYSCFG_SWPR_PAGE1_Msk)                /*!< CCMSRAM  Write protection page 1 */
11133 #define SYSCFG_SWPR_PAGE2_Pos          (2U)
11134 #define SYSCFG_SWPR_PAGE2_Msk          (0x1UL << SYSCFG_SWPR_PAGE2_Pos)       /*!< 0x00000004 */
11135 #define SYSCFG_SWPR_PAGE2              (SYSCFG_SWPR_PAGE2_Msk)                /*!< CCMSRAM  Write protection page 2 */
11136 #define SYSCFG_SWPR_PAGE3_Pos          (3U)
11137 #define SYSCFG_SWPR_PAGE3_Msk          (0x1UL << SYSCFG_SWPR_PAGE3_Pos)       /*!< 0x00000008 */
11138 #define SYSCFG_SWPR_PAGE3              (SYSCFG_SWPR_PAGE3_Msk)                /*!< CCMSRAM  Write protection page 3 */
11139 #define SYSCFG_SWPR_PAGE4_Pos          (4U)
11140 #define SYSCFG_SWPR_PAGE4_Msk          (0x1UL << SYSCFG_SWPR_PAGE4_Pos)       /*!< 0x00000010 */
11141 #define SYSCFG_SWPR_PAGE4              (SYSCFG_SWPR_PAGE4_Msk)                /*!< CCMSRAM  Write protection page 4 */
11142 #define SYSCFG_SWPR_PAGE5_Pos          (5U)
11143 #define SYSCFG_SWPR_PAGE5_Msk          (0x1UL << SYSCFG_SWPR_PAGE5_Pos)       /*!< 0x00000020 */
11144 #define SYSCFG_SWPR_PAGE5              (SYSCFG_SWPR_PAGE5_Msk)                /*!< CCMSRAM  Write protection page 5 */
11145 #define SYSCFG_SWPR_PAGE6_Pos          (6U)
11146 #define SYSCFG_SWPR_PAGE6_Msk          (0x1UL << SYSCFG_SWPR_PAGE6_Pos)       /*!< 0x00000040 */
11147 #define SYSCFG_SWPR_PAGE6              (SYSCFG_SWPR_PAGE6_Msk)                /*!< CCMSRAM  Write protection page 6 */
11148 #define SYSCFG_SWPR_PAGE7_Pos          (7U)
11149 #define SYSCFG_SWPR_PAGE7_Msk          (0x1UL << SYSCFG_SWPR_PAGE7_Pos)       /*!< 0x00000080 */
11150 #define SYSCFG_SWPR_PAGE7              (SYSCFG_SWPR_PAGE7_Msk)                /*!< CCMSRAM  Write protection page 7 */
11151 #define SYSCFG_SWPR_PAGE8_Pos          (8U)
11152 #define SYSCFG_SWPR_PAGE8_Msk          (0x1UL << SYSCFG_SWPR_PAGE8_Pos)       /*!< 0x00000100 */
11153 #define SYSCFG_SWPR_PAGE8              (SYSCFG_SWPR_PAGE8_Msk)                /*!< CCMSRAM  Write protection page 8 */
11154 #define SYSCFG_SWPR_PAGE9_Pos          (9U)
11155 #define SYSCFG_SWPR_PAGE9_Msk          (0x1UL << SYSCFG_SWPR_PAGE9_Pos)       /*!< 0x00000200 */
11156 #define SYSCFG_SWPR_PAGE9              (SYSCFG_SWPR_PAGE9_Msk)                /*!< CCMSRAM  Write protection page 9 */
11157 #define SYSCFG_SWPR_PAGE10_Pos         (10U)
11158 #define SYSCFG_SWPR_PAGE10_Msk         (0x1UL << SYSCFG_SWPR_PAGE10_Pos)      /*!< 0x00000400 */
11159 #define SYSCFG_SWPR_PAGE10             (SYSCFG_SWPR_PAGE10_Msk)               /*!< CCMSRAM  Write protection page 10*/
11160 #define SYSCFG_SWPR_PAGE11_Pos         (11U)
11161 #define SYSCFG_SWPR_PAGE11_Msk         (0x1UL << SYSCFG_SWPR_PAGE11_Pos)      /*!< 0x00000800 */
11162 #define SYSCFG_SWPR_PAGE11             (SYSCFG_SWPR_PAGE11_Msk)               /*!< CCMSRAM  Write protection page 11*/
11163 #define SYSCFG_SWPR_PAGE12_Pos         (12U)
11164 #define SYSCFG_SWPR_PAGE12_Msk         (0x1UL << SYSCFG_SWPR_PAGE12_Pos)      /*!< 0x00001000 */
11165 #define SYSCFG_SWPR_PAGE12             (SYSCFG_SWPR_PAGE12_Msk)               /*!< CCMSRAM  Write protection page 12*/
11166 #define SYSCFG_SWPR_PAGE13_Pos         (13U)
11167 #define SYSCFG_SWPR_PAGE13_Msk         (0x1UL << SYSCFG_SWPR_PAGE13_Pos)      /*!< 0x00002000 */
11168 #define SYSCFG_SWPR_PAGE13             (SYSCFG_SWPR_PAGE13_Msk)               /*!< CCMSRAM  Write protection page 13*/
11169 #define SYSCFG_SWPR_PAGE14_Pos         (14U)
11170 #define SYSCFG_SWPR_PAGE14_Msk         (0x1UL << SYSCFG_SWPR_PAGE14_Pos)      /*!< 0x00004000 */
11171 #define SYSCFG_SWPR_PAGE14             (SYSCFG_SWPR_PAGE14_Msk)               /*!< CCMSRAM  Write protection page 14*/
11172 #define SYSCFG_SWPR_PAGE15_Pos         (15U)
11173 #define SYSCFG_SWPR_PAGE15_Msk         (0x1UL << SYSCFG_SWPR_PAGE15_Pos)      /*!< 0x00008000 */
11174 #define SYSCFG_SWPR_PAGE15             (SYSCFG_SWPR_PAGE15_Msk)               /*!< CCMSRAM  Write protection page 15*/
11175 #define SYSCFG_SWPR_PAGE16_Pos         (16U)
11176 #define SYSCFG_SWPR_PAGE16_Msk         (0x1UL << SYSCFG_SWPR_PAGE16_Pos)      /*!< 0x00010000 */
11177 #define SYSCFG_SWPR_PAGE16             (SYSCFG_SWPR_PAGE16_Msk)               /*!< CCMSRAM  Write protection page 16*/
11178 #define SYSCFG_SWPR_PAGE17_Pos         (17U)
11179 #define SYSCFG_SWPR_PAGE17_Msk         (0x1UL << SYSCFG_SWPR_PAGE17_Pos)      /*!< 0x00020000 */
11180 #define SYSCFG_SWPR_PAGE17             (SYSCFG_SWPR_PAGE17_Msk)               /*!< CCMSRAM  Write protection page 17*/
11181 #define SYSCFG_SWPR_PAGE18_Pos         (18U)
11182 #define SYSCFG_SWPR_PAGE18_Msk         (0x1UL << SYSCFG_SWPR_PAGE18_Pos)      /*!< 0x00040000 */
11183 #define SYSCFG_SWPR_PAGE18             (SYSCFG_SWPR_PAGE18_Msk)               /*!< CCMSRAM  Write protection page 18*/
11184 #define SYSCFG_SWPR_PAGE19_Pos         (19U)
11185 #define SYSCFG_SWPR_PAGE19_Msk         (0x1UL << SYSCFG_SWPR_PAGE19_Pos)      /*!< 0x00080000 */
11186 #define SYSCFG_SWPR_PAGE19             (SYSCFG_SWPR_PAGE19_Msk)               /*!< CCMSRAM  Write protection page 19*/
11187 #define SYSCFG_SWPR_PAGE20_Pos         (20U)
11188 #define SYSCFG_SWPR_PAGE20_Msk         (0x1UL << SYSCFG_SWPR_PAGE20_Pos)      /*!< 0x00100000 */
11189 #define SYSCFG_SWPR_PAGE20             (SYSCFG_SWPR_PAGE20_Msk)               /*!< CCMSRAM  Write protection page 20*/
11190 #define SYSCFG_SWPR_PAGE21_Pos         (21U)
11191 #define SYSCFG_SWPR_PAGE21_Msk         (0x1UL << SYSCFG_SWPR_PAGE21_Pos)      /*!< 0x00200000 */
11192 #define SYSCFG_SWPR_PAGE21             (SYSCFG_SWPR_PAGE21_Msk)               /*!< CCMSRAM  Write protection page 21*/
11193 #define SYSCFG_SWPR_PAGE22_Pos         (22U)
11194 #define SYSCFG_SWPR_PAGE22_Msk         (0x1UL << SYSCFG_SWPR_PAGE22_Pos)      /*!< 0x00400000 */
11195 #define SYSCFG_SWPR_PAGE22             (SYSCFG_SWPR_PAGE22_Msk)               /*!< CCMSRAM  Write protection page 22*/
11196 #define SYSCFG_SWPR_PAGE23_Pos         (23U)
11197 #define SYSCFG_SWPR_PAGE23_Msk         (0x1UL << SYSCFG_SWPR_PAGE23_Pos)      /*!< 0x00800000 */
11198 #define SYSCFG_SWPR_PAGE23             (SYSCFG_SWPR_PAGE23_Msk)               /*!< CCMSRAM  Write protection page 23*/
11199 #define SYSCFG_SWPR_PAGE24_Pos         (24U)
11200 #define SYSCFG_SWPR_PAGE24_Msk         (0x1UL << SYSCFG_SWPR_PAGE24_Pos)      /*!< 0x01000000 */
11201 #define SYSCFG_SWPR_PAGE24             (SYSCFG_SWPR_PAGE24_Msk)               /*!< CCMSRAM  Write protection page 24*/
11202 #define SYSCFG_SWPR_PAGE25_Pos         (25U)
11203 #define SYSCFG_SWPR_PAGE25_Msk         (0x1UL << SYSCFG_SWPR_PAGE25_Pos)      /*!< 0x02000000 */
11204 #define SYSCFG_SWPR_PAGE25             (SYSCFG_SWPR_PAGE25_Msk)               /*!< CCMSRAM  Write protection page 25*/
11205 #define SYSCFG_SWPR_PAGE26_Pos         (26U)
11206 #define SYSCFG_SWPR_PAGE26_Msk         (0x1UL << SYSCFG_SWPR_PAGE26_Pos)      /*!< 0x04000000 */
11207 #define SYSCFG_SWPR_PAGE26             (SYSCFG_SWPR_PAGE26_Msk)               /*!< CCMSRAM  Write protection page 26*/
11208 #define SYSCFG_SWPR_PAGE27_Pos         (27U)
11209 #define SYSCFG_SWPR_PAGE27_Msk         (0x1UL << SYSCFG_SWPR_PAGE27_Pos)      /*!< 0x08000000 */
11210 #define SYSCFG_SWPR_PAGE27             (SYSCFG_SWPR_PAGE27_Msk)               /*!< CCMSRAM  Write protection page 27*/
11211 #define SYSCFG_SWPR_PAGE28_Pos         (28U)
11212 #define SYSCFG_SWPR_PAGE28_Msk         (0x1UL << SYSCFG_SWPR_PAGE28_Pos)      /*!< 0x10000000 */
11213 #define SYSCFG_SWPR_PAGE28             (SYSCFG_SWPR_PAGE28_Msk)               /*!< CCMSRAM  Write protection page 28*/
11214 #define SYSCFG_SWPR_PAGE29_Pos         (29U)
11215 #define SYSCFG_SWPR_PAGE29_Msk         (0x1UL << SYSCFG_SWPR_PAGE29_Pos)      /*!< 0x20000000 */
11216 #define SYSCFG_SWPR_PAGE29             (SYSCFG_SWPR_PAGE29_Msk)               /*!< CCMSRAM  Write protection page 29*/
11217 #define SYSCFG_SWPR_PAGE30_Pos         (30U)
11218 #define SYSCFG_SWPR_PAGE30_Msk         (0x1UL << SYSCFG_SWPR_PAGE30_Pos)      /*!< 0x40000000 */
11219 #define SYSCFG_SWPR_PAGE30             (SYSCFG_SWPR_PAGE30_Msk)               /*!< CCMSRAM  Write protection page 30*/
11220 #define SYSCFG_SWPR_PAGE31_Pos         (31U)
11221 #define SYSCFG_SWPR_PAGE31_Msk         (0x1UL << SYSCFG_SWPR_PAGE31_Pos)      /*!< 0x80000000 */
11222 #define SYSCFG_SWPR_PAGE31             (SYSCFG_SWPR_PAGE31_Msk)               /*!< CCMSRAM  Write protection page 31*/
11223 
11224 /******************  Bit definition for SYSCFG_SKR register  ****************/
11225 #define SYSCFG_SKR_KEY_Pos              (0U)
11226 #define SYSCFG_SKR_KEY_Msk              (0xFFUL << SYSCFG_SKR_KEY_Pos)         /*!< 0x000000FF */
11227 #define SYSCFG_SKR_KEY                  SYSCFG_SKR_KEY_Msk                     /*!< CCMSRAM  write protection key for software erase  */
11228 
11229 /******************************************************************************/
11230 /*                                                                            */
11231 /*                                    TIM                                     */
11232 /*                                                                            */
11233 /******************************************************************************/
11234 /*******************  Bit definition for TIM_CR1 register  ********************/
11235 #define TIM_CR1_CEN_Pos           (0U)
11236 #define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */
11237 #define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
11238 #define TIM_CR1_UDIS_Pos          (1U)
11239 #define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */
11240 #define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
11241 #define TIM_CR1_URS_Pos           (2U)
11242 #define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */
11243 #define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
11244 #define TIM_CR1_OPM_Pos           (3U)
11245 #define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */
11246 #define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
11247 #define TIM_CR1_DIR_Pos           (4U)
11248 #define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */
11249 #define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
11250 
11251 #define TIM_CR1_CMS_Pos           (5U)
11252 #define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */
11253 #define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
11254 #define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000020 */
11255 #define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000040 */
11256 
11257 #define TIM_CR1_ARPE_Pos          (7U)
11258 #define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */
11259 #define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
11260 
11261 #define TIM_CR1_CKD_Pos           (8U)
11262 #define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */
11263 #define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
11264 #define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000100 */
11265 #define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000200 */
11266 
11267 #define TIM_CR1_UIFREMAP_Pos      (11U)
11268 #define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */
11269 #define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
11270 
11271 #define TIM_CR1_DITHEN_Pos      (12U)
11272 #define TIM_CR1_DITHEN_Msk      (0x1UL << TIM_CR1_DITHEN_Pos)                  /*!< 0x00001000 */
11273 #define TIM_CR1_DITHEN          TIM_CR1_DITHEN_Msk                             /*!<Dithering enable */
11274 
11275 /*******************  Bit definition for TIM_CR2 register  ********************/
11276 #define TIM_CR2_CCPC_Pos          (0U)
11277 #define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */
11278 #define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
11279 #define TIM_CR2_CCUS_Pos          (2U)
11280 #define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */
11281 #define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
11282 #define TIM_CR2_CCDS_Pos          (3U)
11283 #define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */
11284 #define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
11285 
11286 #define TIM_CR2_MMS_Pos           (4U)
11287 #define TIM_CR2_MMS_Msk           (0x200007UL << TIM_CR2_MMS_Pos)              /*!< 0x02000070 */
11288 #define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[3:0] bits (Master Mode Selection) */
11289 #define TIM_CR2_MMS_0             (0x000001UL << TIM_CR2_MMS_Pos)              /*!< 0x00000010 */
11290 #define TIM_CR2_MMS_1             (0x000002UL << TIM_CR2_MMS_Pos)              /*!< 0x00000020 */
11291 #define TIM_CR2_MMS_2             (0x000004UL << TIM_CR2_MMS_Pos)              /*!< 0x00000040 */
11292 #define TIM_CR2_MMS_3             (0x200000UL << TIM_CR2_MMS_Pos)              /*!< 0x02000000 */
11293 
11294 #define TIM_CR2_TI1S_Pos          (7U)
11295 #define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */
11296 #define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
11297 #define TIM_CR2_OIS1_Pos          (8U)
11298 #define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */
11299 #define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
11300 #define TIM_CR2_OIS1N_Pos         (9U)
11301 #define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */
11302 #define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
11303 #define TIM_CR2_OIS2_Pos          (10U)
11304 #define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */
11305 #define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
11306 #define TIM_CR2_OIS2N_Pos         (11U)
11307 #define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */
11308 #define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
11309 #define TIM_CR2_OIS3_Pos          (12U)
11310 #define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */
11311 #define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
11312 #define TIM_CR2_OIS3N_Pos         (13U)
11313 #define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */
11314 #define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
11315 #define TIM_CR2_OIS4_Pos          (14U)
11316 #define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */
11317 #define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
11318 #define TIM_CR2_OIS4N_Pos         (15U)
11319 #define TIM_CR2_OIS4N_Msk         (0x1UL << TIM_CR2_OIS4N_Pos)                 /*!< 0x00008000 */
11320 #define TIM_CR2_OIS4N             TIM_CR2_OIS4N_Msk                            /*!<Output Idle state 4 (OC4N output) */
11321 #define TIM_CR2_OIS5_Pos          (16U)
11322 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
11323 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */
11324 #define TIM_CR2_OIS6_Pos          (18U)
11325 #define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
11326 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */
11327 
11328 #define TIM_CR2_MMS2_Pos          (20U)
11329 #define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */
11330 #define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
11331 #define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00100000 */
11332 #define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00200000 */
11333 #define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00400000 */
11334 #define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00800000 */
11335 
11336 /*******************  Bit definition for TIM_SMCR register  *******************/
11337 #define TIM_SMCR_SMS_Pos          (0U)
11338 #define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */
11339 #define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
11340 #define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000001 */
11341 #define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000002 */
11342 #define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000004 */
11343 #define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010000 */
11344 
11345 #define TIM_SMCR_OCCS_Pos         (3U)
11346 #define TIM_SMCR_OCCS_Msk         (0x1UL << TIM_SMCR_OCCS_Pos)                 /*!< 0x00000008 */
11347 #define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
11348 
11349 #define TIM_SMCR_TS_Pos           (4U)
11350 #define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */
11351 #define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
11352 #define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)               /*!< 0x00000010 */
11353 #define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)               /*!< 0x00000020 */
11354 #define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)               /*!< 0x00000040 */
11355 #define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)               /*!< 0x00100000 */
11356 #define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)               /*!< 0x00200000 */
11357 
11358 #define TIM_SMCR_MSM_Pos          (7U)
11359 #define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */
11360 #define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
11361 
11362 #define TIM_SMCR_ETF_Pos          (8U)
11363 #define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */
11364 #define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
11365 #define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000100 */
11366 #define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000200 */
11367 #define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000400 */
11368 #define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000800 */
11369 
11370 #define TIM_SMCR_ETPS_Pos         (12U)
11371 #define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */
11372 #define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
11373 #define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00001000 */
11374 #define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00002000 */
11375 
11376 #define TIM_SMCR_ECE_Pos          (14U)
11377 #define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */
11378 #define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
11379 #define TIM_SMCR_ETP_Pos          (15U)
11380 #define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */
11381 #define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
11382 
11383 #define TIM_SMCR_SMSPE_Pos        (24U)
11384 #define TIM_SMCR_SMSPE_Msk        (0x1UL << TIM_SMCR_SMSPE_Pos)                /*!< 0x02000000 */
11385 #define TIM_SMCR_SMSPE            TIM_SMCR_SMSPE_Msk                           /*!<SMS preload enable */
11386 
11387 #define TIM_SMCR_SMSPS_Pos        (25U)
11388 #define TIM_SMCR_SMSPS_Msk        (0x1UL << TIM_SMCR_SMSPS_Pos)                /*!< 0x04000000 */
11389 #define TIM_SMCR_SMSPS            TIM_SMCR_SMSPS_Msk                           /*!<SMS preload source */
11390 
11391 /*******************  Bit definition for TIM_DIER register  *******************/
11392 #define TIM_DIER_UIE_Pos          (0U)
11393 #define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */
11394 #define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
11395 #define TIM_DIER_CC1IE_Pos        (1U)
11396 #define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */
11397 #define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
11398 #define TIM_DIER_CC2IE_Pos        (2U)
11399 #define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */
11400 #define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
11401 #define TIM_DIER_CC3IE_Pos        (3U)
11402 #define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */
11403 #define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
11404 #define TIM_DIER_CC4IE_Pos        (4U)
11405 #define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */
11406 #define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
11407 #define TIM_DIER_COMIE_Pos        (5U)
11408 #define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */
11409 #define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
11410 #define TIM_DIER_TIE_Pos          (6U)
11411 #define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */
11412 #define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
11413 #define TIM_DIER_BIE_Pos          (7U)
11414 #define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */
11415 #define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
11416 #define TIM_DIER_UDE_Pos          (8U)
11417 #define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */
11418 #define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
11419 #define TIM_DIER_CC1DE_Pos        (9U)
11420 #define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */
11421 #define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
11422 #define TIM_DIER_CC2DE_Pos        (10U)
11423 #define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */
11424 #define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
11425 #define TIM_DIER_CC3DE_Pos        (11U)
11426 #define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */
11427 #define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
11428 #define TIM_DIER_CC4DE_Pos        (12U)
11429 #define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */
11430 #define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
11431 #define TIM_DIER_COMDE_Pos        (13U)
11432 #define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */
11433 #define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
11434 #define TIM_DIER_TDE_Pos          (14U)
11435 #define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */
11436 #define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
11437 #define TIM_DIER_IDXIE_Pos        (20U)
11438 #define TIM_DIER_IDXIE_Msk        (0x1UL << TIM_DIER_IDXIE_Pos)                /*!< 0x00100000 */
11439 #define TIM_DIER_IDXIE            TIM_DIER_IDXIE_Msk                           /*!<Encoder index interrupt enable */
11440 #define TIM_DIER_DIRIE_Pos        (21U)
11441 #define TIM_DIER_DIRIE_Msk        (0x1UL << TIM_DIER_DIRIE_Pos)                /*!< 0x00200000 */
11442 #define TIM_DIER_DIRIE            TIM_DIER_DIRIE_Msk                           /*!<Encoder direction change interrupt enable */
11443 #define TIM_DIER_IERRIE_Pos       (22U)
11444 #define TIM_DIER_IERRIE_Msk       (0x1UL << TIM_DIER_IERRIE_Pos)               /*!< 0x00400000 */
11445 #define TIM_DIER_IERRIE           TIM_DIER_IERRIE_Msk                          /*!<Encoder index error enable */
11446 #define TIM_DIER_TERRIE_Pos       (23U)
11447 #define TIM_DIER_TERRIE_Msk       (0x1UL << TIM_DIER_TERRIE_Pos)               /*!< 0x00800000 */
11448 #define TIM_DIER_TERRIE           TIM_DIER_TERRIE_Msk                          /*!<Encoder transition error enable */
11449 
11450 /********************  Bit definition for TIM_SR register  ********************/
11451 #define TIM_SR_UIF_Pos            (0U)
11452 #define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */
11453 #define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
11454 #define TIM_SR_CC1IF_Pos          (1U)
11455 #define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */
11456 #define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
11457 #define TIM_SR_CC2IF_Pos          (2U)
11458 #define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */
11459 #define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
11460 #define TIM_SR_CC3IF_Pos          (3U)
11461 #define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */
11462 #define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
11463 #define TIM_SR_CC4IF_Pos          (4U)
11464 #define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */
11465 #define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
11466 #define TIM_SR_COMIF_Pos          (5U)
11467 #define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */
11468 #define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
11469 #define TIM_SR_TIF_Pos            (6U)
11470 #define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */
11471 #define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
11472 #define TIM_SR_BIF_Pos            (7U)
11473 #define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */
11474 #define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
11475 #define TIM_SR_B2IF_Pos           (8U)
11476 #define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */
11477 #define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */
11478 #define TIM_SR_CC1OF_Pos          (9U)
11479 #define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */
11480 #define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
11481 #define TIM_SR_CC2OF_Pos          (10U)
11482 #define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */
11483 #define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
11484 #define TIM_SR_CC3OF_Pos          (11U)
11485 #define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */
11486 #define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
11487 #define TIM_SR_CC4OF_Pos          (12U)
11488 #define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */
11489 #define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
11490 #define TIM_SR_SBIF_Pos           (13U)
11491 #define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */
11492 #define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */
11493 #define TIM_SR_CC5IF_Pos          (16U)
11494 #define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */
11495 #define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
11496 #define TIM_SR_CC6IF_Pos          (17U)
11497 #define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */
11498 #define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
11499 #define TIM_SR_IDXF_Pos           (20U)
11500 #define TIM_SR_IDXF_Msk           (0x1UL << TIM_SR_IDXF_Pos)                   /*!< 0x00100000 */
11501 #define TIM_SR_IDXF               TIM_SR_IDXF_Msk                              /*!<Encoder index interrupt flag */
11502 #define TIM_SR_DIRF_Pos           (21U)
11503 #define TIM_SR_DIRF_Msk           (0x1UL << TIM_SR_DIRF_Pos)                   /*!< 0x00200000 */
11504 #define TIM_SR_DIRF               TIM_SR_DIRF_Msk                              /*!<Encoder direction change interrupt flag */
11505 #define TIM_SR_IERRF_Pos          (22U)
11506 #define TIM_SR_IERRF_Msk          (0x1UL << TIM_SR_IERRF_Pos)                  /*!< 0x00400000 */
11507 #define TIM_SR_IERRF              TIM_SR_IERRF_Msk                             /*!<Encoder index error flag */
11508 #define TIM_SR_TERRF_Pos          (23U)
11509 #define TIM_SR_TERRF_Msk          (0x1UL << TIM_SR_TERRF_Pos)                  /*!< 0x00800000 */
11510 #define TIM_SR_TERRF              TIM_SR_TERRF_Msk                             /*!<Encoder transition error flag */
11511 
11512 /*******************  Bit definition for TIM_EGR register  ********************/
11513 #define TIM_EGR_UG_Pos            (0U)
11514 #define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */
11515 #define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
11516 #define TIM_EGR_CC1G_Pos          (1U)
11517 #define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */
11518 #define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
11519 #define TIM_EGR_CC2G_Pos          (2U)
11520 #define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */
11521 #define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
11522 #define TIM_EGR_CC3G_Pos          (3U)
11523 #define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */
11524 #define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
11525 #define TIM_EGR_CC4G_Pos          (4U)
11526 #define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */
11527 #define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
11528 #define TIM_EGR_COMG_Pos          (5U)
11529 #define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */
11530 #define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
11531 #define TIM_EGR_TG_Pos            (6U)
11532 #define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */
11533 #define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
11534 #define TIM_EGR_BG_Pos            (7U)
11535 #define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */
11536 #define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
11537 #define TIM_EGR_B2G_Pos           (8U)
11538 #define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */
11539 #define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */
11540 
11541 
11542 /******************  Bit definition for TIM_CCMR1 register  *******************/
11543 #define TIM_CCMR1_CC1S_Pos        (0U)
11544 #define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */
11545 #define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
11546 #define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000001 */
11547 #define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000002 */
11548 
11549 #define TIM_CCMR1_OC1FE_Pos       (2U)
11550 #define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */
11551 #define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
11552 #define TIM_CCMR1_OC1PE_Pos       (3U)
11553 #define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */
11554 #define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
11555 
11556 #define TIM_CCMR1_OC1M_Pos        (4U)
11557 #define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */
11558 #define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
11559 #define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000010 */
11560 #define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000020 */
11561 #define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000040 */
11562 #define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010000 */
11563 
11564 #define TIM_CCMR1_OC1CE_Pos       (7U)
11565 #define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */
11566 #define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */
11567 
11568 #define TIM_CCMR1_CC2S_Pos        (8U)
11569 #define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */
11570 #define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
11571 #define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000100 */
11572 #define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000200 */
11573 
11574 #define TIM_CCMR1_OC2FE_Pos       (10U)
11575 #define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */
11576 #define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
11577 #define TIM_CCMR1_OC2PE_Pos       (11U)
11578 #define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */
11579 #define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
11580 
11581 #define TIM_CCMR1_OC2M_Pos        (12U)
11582 #define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */
11583 #define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
11584 #define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00001000 */
11585 #define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00002000 */
11586 #define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00004000 */
11587 #define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01000000 */
11588 
11589 #define TIM_CCMR1_OC2CE_Pos       (15U)
11590 #define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */
11591 #define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
11592 
11593 /*----------------------------------------------------------------------------*/
11594 #define TIM_CCMR1_IC1PSC_Pos      (2U)
11595 #define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */
11596 #define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
11597 #define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000004 */
11598 #define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000008 */
11599 
11600 #define TIM_CCMR1_IC1F_Pos        (4U)
11601 #define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */
11602 #define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
11603 #define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000010 */
11604 #define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000020 */
11605 #define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000040 */
11606 #define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000080 */
11607 
11608 #define TIM_CCMR1_IC2PSC_Pos      (10U)
11609 #define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */
11610 #define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
11611 #define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000400 */
11612 #define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000800 */
11613 
11614 #define TIM_CCMR1_IC2F_Pos        (12U)
11615 #define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */
11616 #define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
11617 #define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00001000 */
11618 #define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00002000 */
11619 #define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00004000 */
11620 #define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00008000 */
11621 
11622 /******************  Bit definition for TIM_CCMR2 register  *******************/
11623 #define TIM_CCMR2_CC3S_Pos        (0U)
11624 #define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */
11625 #define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
11626 #define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000001 */
11627 #define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000002 */
11628 
11629 #define TIM_CCMR2_OC3FE_Pos       (2U)
11630 #define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */
11631 #define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
11632 #define TIM_CCMR2_OC3PE_Pos       (3U)
11633 #define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */
11634 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
11635 
11636 #define TIM_CCMR2_OC3M_Pos        (4U)
11637 #define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010070 */
11638 #define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
11639 #define TIM_CCMR2_OC3M_0          (0x0001UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000010 */
11640 #define TIM_CCMR2_OC3M_1          (0x0002UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000020 */
11641 #define TIM_CCMR2_OC3M_2          (0x0004UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000040 */
11642 #define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010000 */
11643 
11644 #define TIM_CCMR2_OC3CE_Pos       (7U)
11645 #define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */
11646 #define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
11647 
11648 #define TIM_CCMR2_CC4S_Pos        (8U)
11649 #define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */
11650 #define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
11651 #define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000100 */
11652 #define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000200 */
11653 
11654 #define TIM_CCMR2_OC4FE_Pos       (10U)
11655 #define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */
11656 #define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
11657 #define TIM_CCMR2_OC4PE_Pos       (11U)
11658 #define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */
11659 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
11660 
11661 #define TIM_CCMR2_OC4M_Pos        (12U)
11662 #define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01007000 */
11663 #define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
11664 #define TIM_CCMR2_OC4M_0          (0x0001UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00001000 */
11665 #define TIM_CCMR2_OC4M_1          (0x0002UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00002000 */
11666 #define TIM_CCMR2_OC4M_2          (0x0004UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00004000 */
11667 #define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01000000 */
11668 
11669 #define TIM_CCMR2_OC4CE_Pos       (15U)
11670 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
11671 #define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
11672 
11673 /*----------------------------------------------------------------------------*/
11674 #define TIM_CCMR2_IC3PSC_Pos      (2U)
11675 #define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */
11676 #define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
11677 #define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000004 */
11678 #define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000008 */
11679 
11680 #define TIM_CCMR2_IC3F_Pos        (4U)
11681 #define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */
11682 #define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
11683 #define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000010 */
11684 #define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000020 */
11685 #define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000040 */
11686 #define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000080 */
11687 
11688 #define TIM_CCMR2_IC4PSC_Pos      (10U)
11689 #define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */
11690 #define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
11691 #define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000400 */
11692 #define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000800 */
11693 
11694 #define TIM_CCMR2_IC4F_Pos        (12U)
11695 #define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */
11696 #define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
11697 #define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00001000 */
11698 #define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00002000 */
11699 #define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00004000 */
11700 #define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00008000 */
11701 
11702 /******************  Bit definition for TIM_CCMR3 register  *******************/
11703 #define TIM_CCMR3_OC5FE_Pos       (2U)
11704 #define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */
11705 #define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
11706 #define TIM_CCMR3_OC5PE_Pos       (3U)
11707 #define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */
11708 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
11709 
11710 #define TIM_CCMR3_OC5M_Pos        (4U)
11711 #define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010070 */
11712 #define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
11713 #define TIM_CCMR3_OC5M_0          (0x0001UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000010 */
11714 #define TIM_CCMR3_OC5M_1          (0x0002UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000020 */
11715 #define TIM_CCMR3_OC5M_2          (0x0004UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000040 */
11716 #define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010000 */
11717 
11718 #define TIM_CCMR3_OC5CE_Pos       (7U)
11719 #define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */
11720 #define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
11721 
11722 #define TIM_CCMR3_OC6FE_Pos       (10U)
11723 #define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */
11724 #define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
11725 #define TIM_CCMR3_OC6PE_Pos       (11U)
11726 #define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */
11727 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
11728 
11729 #define TIM_CCMR3_OC6M_Pos        (12U)
11730 #define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01007000 */
11731 #define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
11732 #define TIM_CCMR3_OC6M_0          (0x0001UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00001000 */
11733 #define TIM_CCMR3_OC6M_1          (0x0002UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00002000 */
11734 #define TIM_CCMR3_OC6M_2          (0x0004UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00004000 */
11735 #define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01000000 */
11736 
11737 #define TIM_CCMR3_OC6CE_Pos       (15U)
11738 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
11739 #define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
11740 
11741 /*******************  Bit definition for TIM_CCER register  *******************/
11742 #define TIM_CCER_CC1E_Pos         (0U)
11743 #define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */
11744 #define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
11745 #define TIM_CCER_CC1P_Pos         (1U)
11746 #define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */
11747 #define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
11748 #define TIM_CCER_CC1NE_Pos        (2U)
11749 #define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */
11750 #define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
11751 #define TIM_CCER_CC1NP_Pos        (3U)
11752 #define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */
11753 #define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
11754 #define TIM_CCER_CC2E_Pos         (4U)
11755 #define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */
11756 #define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
11757 #define TIM_CCER_CC2P_Pos         (5U)
11758 #define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */
11759 #define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
11760 #define TIM_CCER_CC2NE_Pos        (6U)
11761 #define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */
11762 #define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
11763 #define TIM_CCER_CC2NP_Pos        (7U)
11764 #define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */
11765 #define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
11766 #define TIM_CCER_CC3E_Pos         (8U)
11767 #define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */
11768 #define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
11769 #define TIM_CCER_CC3P_Pos         (9U)
11770 #define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */
11771 #define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
11772 #define TIM_CCER_CC3NE_Pos        (10U)
11773 #define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */
11774 #define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
11775 #define TIM_CCER_CC3NP_Pos        (11U)
11776 #define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */
11777 #define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
11778 #define TIM_CCER_CC4E_Pos         (12U)
11779 #define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */
11780 #define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
11781 #define TIM_CCER_CC4P_Pos         (13U)
11782 #define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */
11783 #define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
11784 #define TIM_CCER_CC4NE_Pos        (14U)
11785 #define TIM_CCER_CC4NE_Msk        (0x1UL << TIM_CCER_CC4NE_Pos)                /*!< 0x00004000 */
11786 #define TIM_CCER_CC4NE            TIM_CCER_CC4NE_Msk                           /*!<Capture/Compare 4 Complementary output enable */
11787 #define TIM_CCER_CC4NP_Pos        (15U)
11788 #define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */
11789 #define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
11790 #define TIM_CCER_CC5E_Pos         (16U)
11791 #define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */
11792 #define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
11793 #define TIM_CCER_CC5P_Pos         (17U)
11794 #define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */
11795 #define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
11796 #define TIM_CCER_CC6E_Pos         (20U)
11797 #define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */
11798 #define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
11799 #define TIM_CCER_CC6P_Pos         (21U)
11800 #define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */
11801 #define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
11802 
11803 /*******************  Bit definition for TIM_CNT register  ********************/
11804 #define TIM_CNT_CNT_Pos           (0U)
11805 #define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */
11806 #define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
11807 #define TIM_CNT_UIFCPY_Pos        (31U)
11808 #define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */
11809 #define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */
11810 
11811 /*******************  Bit definition for TIM_PSC register  ********************/
11812 #define TIM_PSC_PSC_Pos           (0U)
11813 #define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */
11814 #define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
11815 
11816 /*******************  Bit definition for TIM_ARR register  ********************/
11817 #define TIM_ARR_ARR_Pos           (0U)
11818 #define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */
11819 #define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */
11820 
11821 /*******************  Bit definition for TIM_RCR register  ********************/
11822 #define TIM_RCR_REP_Pos           (0U)
11823 #define TIM_RCR_REP_Msk           (0xFFFFUL << TIM_RCR_REP_Pos)                /*!< 0x0000FFFF */
11824 #define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
11825 
11826 /*******************  Bit definition for TIM_CCR1 register  *******************/
11827 #define TIM_CCR1_CCR1_Pos         (0U)
11828 #define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */
11829 #define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
11830 
11831 /*******************  Bit definition for TIM_CCR2 register  *******************/
11832 #define TIM_CCR2_CCR2_Pos         (0U)
11833 #define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */
11834 #define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
11835 
11836 /*******************  Bit definition for TIM_CCR3 register  *******************/
11837 #define TIM_CCR3_CCR3_Pos         (0U)
11838 #define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */
11839 #define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
11840 
11841 /*******************  Bit definition for TIM_CCR4 register  *******************/
11842 #define TIM_CCR4_CCR4_Pos         (0U)
11843 #define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */
11844 #define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
11845 
11846 /*******************  Bit definition for TIM_CCR5 register  *******************/
11847 #define TIM_CCR5_CCR5_Pos         (0U)
11848 #define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */
11849 #define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
11850 #define TIM_CCR5_GC5C1_Pos        (29U)
11851 #define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */
11852 #define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
11853 #define TIM_CCR5_GC5C2_Pos        (30U)
11854 #define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */
11855 #define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
11856 #define TIM_CCR5_GC5C3_Pos        (31U)
11857 #define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */
11858 #define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
11859 
11860 /*******************  Bit definition for TIM_CCR6 register  *******************/
11861 #define TIM_CCR6_CCR6_Pos         (0U)
11862 #define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */
11863 #define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
11864 
11865 /*******************  Bit definition for TIM_BDTR register  *******************/
11866 #define TIM_BDTR_DTG_Pos          (0U)
11867 #define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */
11868 #define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
11869 #define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000001 */
11870 #define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000002 */
11871 #define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000004 */
11872 #define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000008 */
11873 #define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000010 */
11874 #define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000020 */
11875 #define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000040 */
11876 #define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000080 */
11877 
11878 #define TIM_BDTR_LOCK_Pos         (8U)
11879 #define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */
11880 #define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
11881 #define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000100 */
11882 #define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000200 */
11883 
11884 #define TIM_BDTR_OSSI_Pos         (10U)
11885 #define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */
11886 #define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
11887 #define TIM_BDTR_OSSR_Pos         (11U)
11888 #define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */
11889 #define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
11890 #define TIM_BDTR_BKE_Pos          (12U)
11891 #define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */
11892 #define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
11893 #define TIM_BDTR_BKP_Pos          (13U)
11894 #define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */
11895 #define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
11896 #define TIM_BDTR_AOE_Pos          (14U)
11897 #define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */
11898 #define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
11899 #define TIM_BDTR_MOE_Pos          (15U)
11900 #define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */
11901 #define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
11902 
11903 #define TIM_BDTR_BKF_Pos          (16U)
11904 #define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */
11905 #define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */
11906 #define TIM_BDTR_BK2F_Pos         (20U)
11907 #define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */
11908 #define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */
11909 
11910 #define TIM_BDTR_BK2E_Pos         (24U)
11911 #define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */
11912 #define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */
11913 #define TIM_BDTR_BK2P_Pos         (25U)
11914 #define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
11915 #define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */
11916 
11917 #define TIM_BDTR_BKDSRM_Pos       (26U)
11918 #define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
11919 #define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break disarming/re-arming */
11920 #define TIM_BDTR_BK2DSRM_Pos      (27U)
11921 #define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
11922 #define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 disarming/re-arming */
11923 
11924 #define TIM_BDTR_BKBID_Pos        (28U)
11925 #define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
11926 #define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break BIDirectional */
11927 #define TIM_BDTR_BK2BID_Pos       (29U)
11928 #define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
11929 #define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 BIDirectional */
11930 
11931 /*******************  Bit definition for TIM_DCR register  ********************/
11932 #define TIM_DCR_DBA_Pos           (0U)
11933 #define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */
11934 #define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
11935 #define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000001 */
11936 #define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000002 */
11937 #define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000004 */
11938 #define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000008 */
11939 #define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000010 */
11940 
11941 #define TIM_DCR_DBL_Pos           (8U)
11942 #define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */
11943 #define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
11944 #define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000100 */
11945 #define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000200 */
11946 #define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000400 */
11947 #define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000800 */
11948 #define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                  /*!< 0x00001000 */
11949 
11950 /*******************  Bit definition for TIM1_AF1 register  *******************/
11951 #define TIM1_AF1_BKINE_Pos        (0U)
11952 #define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */
11953 #define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BRK BKIN input enable */
11954 #define TIM1_AF1_BKCMP1E_Pos      (1U)
11955 #define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
11956 #define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BRK COMP1 enable */
11957 #define TIM1_AF1_BKCMP2E_Pos      (2U)
11958 #define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
11959 #define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BRK COMP2 enable */
11960 #define TIM1_AF1_BKCMP3E_Pos      (3U)
11961 #define TIM1_AF1_BKCMP3E_Msk      (0x1UL << TIM1_AF1_BKCMP3E_Pos)              /*!< 0x00000008 */
11962 #define TIM1_AF1_BKCMP3E          TIM1_AF1_BKCMP3E_Msk                         /*!<BRK COMP3 enable */
11963 #define TIM1_AF1_BKCMP4E_Pos      (4U)
11964 #define TIM1_AF1_BKCMP4E_Msk      (0x1UL << TIM1_AF1_BKCMP4E_Pos)              /*!< 0x00000010 */
11965 #define TIM1_AF1_BKCMP4E          TIM1_AF1_BKCMP4E_Msk                         /*!<BRK COMP4 enable */
11966 #define TIM1_AF1_BKCMP5E_Pos      (5U)
11967 #define TIM1_AF1_BKCMP5E_Msk      (0x1UL << TIM1_AF1_BKCMP5E_Pos)              /*!< 0x00000020 */
11968 #define TIM1_AF1_BKCMP5E          TIM1_AF1_BKCMP5E_Msk                         /*!<BRK COMP5 enable */
11969 #define TIM1_AF1_BKCMP6E_Pos      (6U)
11970 #define TIM1_AF1_BKCMP6E_Msk      (0x1UL << TIM1_AF1_BKCMP6E_Pos)              /*!< 0x00000040 */
11971 #define TIM1_AF1_BKCMP6E          TIM1_AF1_BKCMP6E_Msk                         /*!<BRK COMP6 enable */
11972 #define TIM1_AF1_BKCMP7E_Pos      (7U)
11973 #define TIM1_AF1_BKCMP7E_Msk      (0x1UL << TIM1_AF1_BKCMP7E_Pos)              /*!< 0x00000080 */
11974 #define TIM1_AF1_BKCMP7E          TIM1_AF1_BKCMP7E_Msk                         /*!<BRK COMP7 enable */
11975 #define TIM1_AF1_BKINP_Pos        (9U)
11976 #define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */
11977 #define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRK BKIN input polarity */
11978 #define TIM1_AF1_BKCMP1P_Pos      (10U)
11979 #define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
11980 #define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BRK COMP1 input polarity */
11981 #define TIM1_AF1_BKCMP2P_Pos      (11U)
11982 #define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
11983 #define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BRK COMP2 input polarity */
11984 #define TIM1_AF1_BKCMP3P_Pos      (12U)
11985 #define TIM1_AF1_BKCMP3P_Msk      (0x1UL << TIM1_AF1_BKCMP3P_Pos)              /*!< 0x00001000 */
11986 #define TIM1_AF1_BKCMP3P          TIM1_AF1_BKCMP3P_Msk                         /*!<BRK COMP3 input polarity */
11987 #define TIM1_AF1_BKCMP4P_Pos      (13U)
11988 #define TIM1_AF1_BKCMP4P_Msk      (0x1UL << TIM1_AF1_BKCMP4P_Pos)              /*!< 0x00002000 */
11989 #define TIM1_AF1_BKCMP4P          TIM1_AF1_BKCMP4P_Msk                         /*!<BRK COMP4 input polarity */
11990 #define TIM1_AF1_ETRSEL_Pos       (14U)
11991 #define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
11992 #define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
11993 #define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00004000 */
11994 #define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00008000 */
11995 #define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00010000 */
11996 #define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00020000 */
11997 
11998 /*******************  Bit definition for TIM1_AF2 register  *********************/
11999 #define TIM1_AF2_BK2INE_Pos        (0U)
12000 #define TIM1_AF2_BK2INE_Msk        (0x1UL << TIM1_AF2_BK2INE_Pos)                /*!< 0x00000001 */
12001 #define TIM1_AF2_BK2INE            TIM1_AF2_BK2INE_Msk                           /*!<BRK2 BKIN input enable */
12002 #define TIM1_AF2_BK2CMP1E_Pos      (1U)
12003 #define TIM1_AF2_BK2CMP1E_Msk      (0x1UL << TIM1_AF2_BK2CMP1E_Pos)              /*!< 0x00000002 */
12004 #define TIM1_AF2_BK2CMP1E          TIM1_AF2_BK2CMP1E_Msk                         /*!<BRK2 COMP1 enable */
12005 #define TIM1_AF2_BK2CMP2E_Pos      (2U)
12006 #define TIM1_AF2_BK2CMP2E_Msk      (0x1UL << TIM1_AF2_BK2CMP2E_Pos)              /*!< 0x00000004 */
12007 #define TIM1_AF2_BK2CMP2E          TIM1_AF2_BK2CMP2E_Msk                         /*!<BRK2 COMP2 enable */
12008 #define TIM1_AF2_BK2CMP3E_Pos      (3U)
12009 #define TIM1_AF2_BK2CMP3E_Msk      (0x1UL << TIM1_AF2_BK2CMP3E_Pos)              /*!< 0x00000008 */
12010 #define TIM1_AF2_BK2CMP3E          TIM1_AF2_BK2CMP3E_Msk                         /*!<BRK2 COMP3 enable */
12011 #define TIM1_AF2_BK2CMP4E_Pos      (4U)
12012 #define TIM1_AF2_BK2CMP4E_Msk      (0x1UL << TIM1_AF2_BK2CMP4E_Pos)              /*!< 0x00000010 */
12013 #define TIM1_AF2_BK2CMP4E          TIM1_AF2_BK2CMP4E_Msk                         /*!<BRK2 COMP4 enable */
12014 #define TIM1_AF2_BK2CMP5E_Pos      (5U)
12015 #define TIM1_AF2_BK2CMP5E_Msk      (0x1UL << TIM1_AF2_BK2CMP5E_Pos)              /*!< 0x00000020 */
12016 #define TIM1_AF2_BK2CMP5E          TIM1_AF2_BK2CMP5E_Msk                         /*!<BRK2 COMP5 enable */
12017 #define TIM1_AF2_BK2CMP6E_Pos      (6U)
12018 #define TIM1_AF2_BK2CMP6E_Msk      (0x1UL << TIM1_AF2_BK2CMP6E_Pos)              /*!< 0x00000040 */
12019 #define TIM1_AF2_BK2CMP6E          TIM1_AF2_BK2CMP6E_Msk                         /*!<BRK2 COMP6 enable */
12020 #define TIM1_AF2_BK2CMP7E_Pos      (7U)
12021 #define TIM1_AF2_BK2CMP7E_Msk      (0x1UL << TIM1_AF2_BK2CMP7E_Pos)              /*!< 0x00000080 */
12022 #define TIM1_AF2_BK2CMP7E          TIM1_AF2_BK2CMP7E_Msk                         /*!<BRK2 COMP7 enable */
12023 #define TIM1_AF2_BK2INP_Pos        (9U)
12024 #define TIM1_AF2_BK2INP_Msk        (0x1UL << TIM1_AF2_BK2INP_Pos)                /*!< 0x00000200 */
12025 #define TIM1_AF2_BK2INP            TIM1_AF2_BK2INP_Msk                           /*!<BRK2 BKIN input polarity */
12026 #define TIM1_AF2_BK2CMP1P_Pos      (10U)
12027 #define TIM1_AF2_BK2CMP1P_Msk      (0x1UL << TIM1_AF2_BK2CMP1P_Pos)              /*!< 0x00000400 */
12028 #define TIM1_AF2_BK2CMP1P          TIM1_AF2_BK2CMP1P_Msk                         /*!<BRK2 COMP1 input polarity */
12029 #define TIM1_AF2_BK2CMP2P_Pos      (11U)
12030 #define TIM1_AF2_BK2CMP2P_Msk      (0x1UL << TIM1_AF2_BK2CMP2P_Pos)              /*!< 0x00000800 */
12031 #define TIM1_AF2_BK2CMP2P          TIM1_AF2_BK2CMP2P_Msk                         /*!<BRK2 COMP2 input polarity */
12032 #define TIM1_AF2_BK2CMP3P_Pos      (12U)
12033 #define TIM1_AF2_BK2CMP3P_Msk      (0x1UL << TIM1_AF2_BK2CMP3P_Pos)              /*!< 0x00000400 */
12034 #define TIM1_AF2_BK2CMP3P          TIM1_AF2_BK2CMP3P_Msk                         /*!<BRK2 COMP3 input polarity */
12035 #define TIM1_AF2_BK2CMP4P_Pos      (13U)
12036 #define TIM1_AF2_BK2CMP4P_Msk      (0x1UL << TIM1_AF2_BK2CMP4P_Pos)              /*!< 0x00000800 */
12037 #define TIM1_AF2_BK2CMP4P          TIM1_AF2_BK2CMP4P_Msk                         /*!<BRK2 COMP4 input polarity */
12038 #define TIM1_AF2_OCRSEL_Pos        (16U)
12039 #define TIM1_AF2_OCRSEL_Msk        (0x7UL << TIM1_AF2_OCRSEL_Pos)                /*!< 0x00070000 */
12040 #define TIM1_AF2_OCRSEL            TIM1_AF2_OCRSEL_Msk                           /*!<BRK2 COMP2 input polarity */
12041 #define TIM1_AF2_OCRSEL_0         (0x1UL << TIM1_AF2_OCRSEL_Pos)                 /*!< 0x00010000 */
12042 #define TIM1_AF2_OCRSEL_1         (0x2UL << TIM1_AF2_OCRSEL_Pos)                 /*!< 0x00020000 */
12043 #define TIM1_AF2_OCRSEL_2         (0x4UL << TIM1_AF2_OCRSEL_Pos)                 /*!< 0x00040000 */
12044 
12045 /*******************  Bit definition for TIM_OR register  *********************/
12046 #define TIM_OR_HSE32EN_Pos       (0U)
12047 #define TIM_OR_HSE32EN_Msk       (0x1UL << TIM_OR_HSE32EN_Pos)                  /*!< 0x00000001 */
12048 #define TIM_OR_HSE32EN           TIM_OR_HSE32EN_Msk                             /*!< HSE/32 clock enable */
12049 
12050 /*******************  Bit definition for TIM_TISEL register  *********************/
12051 #define TIM_TISEL_TI1SEL_Pos      (0U)
12052 #define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */
12053 #define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
12054 #define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000001 */
12055 #define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000002 */
12056 #define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000004 */
12057 #define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000008 */
12058 
12059 #define TIM_TISEL_TI2SEL_Pos      (8U)
12060 #define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */
12061 #define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
12062 #define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000100 */
12063 #define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000200 */
12064 #define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000400 */
12065 #define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000800 */
12066 
12067 #define TIM_TISEL_TI3SEL_Pos      (16U)
12068 #define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */
12069 #define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/
12070 #define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00010000 */
12071 #define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00020000 */
12072 #define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00040000 */
12073 #define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00080000 */
12074 
12075 #define TIM_TISEL_TI4SEL_Pos      (24U)
12076 #define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */
12077 #define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/
12078 #define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x01000000 */
12079 #define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x02000000 */
12080 #define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x04000000 */
12081 #define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x08000000 */
12082 
12083 /*******************  Bit definition for TIM_DTR2 register  *********************/
12084 #define TIM_DTR2_DTGF_Pos      (0U)
12085 #define TIM_DTR2_DTGF_Msk      (0xFFUL << TIM_DTR2_DTGF_Pos)                /*!< 0x0000000F */
12086 #define TIM_DTR2_DTGF          TIM_DTR2_DTGF_Msk                            /*!<DTGF[7:0] bits (Deadtime falling edge generator setup)*/
12087 #define TIM_DTR2_DTGF_0        (0x01UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000001 */
12088 #define TIM_DTR2_DTGF_1        (0x02UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000002 */
12089 #define TIM_DTR2_DTGF_2        (0x04UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000004 */
12090 #define TIM_DTR2_DTGF_3        (0x08UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000008 */
12091 #define TIM_DTR2_DTGF_4        (0x10UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000010 */
12092 #define TIM_DTR2_DTGF_5        (0x20UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000020 */
12093 #define TIM_DTR2_DTGF_6        (0x40UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000040 */
12094 #define TIM_DTR2_DTGF_7        (0x80UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000080 */
12095 
12096 #define TIM_DTR2_DTAE_Pos      (16U)
12097 #define TIM_DTR2_DTAE_Msk      (0x1UL << TIM_DTR2_DTAE_Pos)                 /*!< 0x00004000 */
12098 #define TIM_DTR2_DTAE          TIM_DTR2_DTAE_Msk                            /*!<Deadtime asymmetric enable */
12099 #define TIM_DTR2_DTPE_Pos      (17U)
12100 #define TIM_DTR2_DTPE_Msk      (0x1UL << TIM_DTR2_DTPE_Pos)                 /*!< 0x00008000 */
12101 #define TIM_DTR2_DTPE          TIM_DTR2_DTPE_Msk                            /*!<Deadtime prelaod enable */
12102 
12103 /*******************  Bit definition for TIM_ECR register  *********************/
12104 #define TIM_ECR_IE_Pos       (0U)
12105 #define TIM_ECR_IE_Msk       (0x1UL << TIM_ECR_IE_Pos)                   /*!< 0x00000001 */
12106 #define TIM_ECR_IE           TIM_ECR_IE_Msk                              /*!<Index enable */
12107 
12108 #define TIM_ECR_IDIR_Pos      (1U)
12109 #define TIM_ECR_IDIR_Msk      (0x3UL << TIM_ECR_IDIR_Pos)                 /*!< 0x00000006 */
12110 #define TIM_ECR_IDIR          TIM_ECR_IDIR_Msk                            /*!<IDIR[1:0] bits (Index direction)*/
12111 #define TIM_ECR_IDIR_0        (0x01UL << TIM_ECR_IDIR_Pos)                /*!< 0x00000001 */
12112 #define TIM_ECR_IDIR_1        (0x02UL << TIM_ECR_IDIR_Pos)                /*!< 0x00000002 */
12113 
12114 #define TIM_ECR_FIDX_Pos      (5U)
12115 #define TIM_ECR_FIDX_Msk      (0x1UL << TIM_ECR_FIDX_Pos)                 /*!< 0x00000020 */
12116 #define TIM_ECR_FIDX          TIM_ECR_FIDX_Msk                            /*!<First index enable */
12117 
12118 #define TIM_ECR_IPOS_Pos      (6U)
12119 #define TIM_ECR_IPOS_Msk      (0x3UL << TIM_ECR_IPOS_Pos)                 /*!< 0x0000000C0 */
12120 #define TIM_ECR_IPOS          TIM_ECR_IPOS_Msk                            /*!<IPOS[1:0] bits (Index positioning)*/
12121 #define TIM_ECR_IPOS_0        (0x01UL << TIM_ECR_IPOS_Pos)                /*!< 0x00000001 */
12122 #define TIM_ECR_IPOS_1        (0x02UL << TIM_ECR_IPOS_Pos)                /*!< 0x00000002 */
12123 
12124 #define TIM_ECR_PW_Pos        (16U)
12125 #define TIM_ECR_PW_Msk        (0xFFUL << TIM_ECR_PW_Pos)                  /*!< 0x00FF0000 */
12126 #define TIM_ECR_PW            TIM_ECR_PW_Msk                              /*!<PW[7:0] bits (Pulse width)*/
12127 #define TIM_ECR_PW_0          (0x01UL << TIM_ECR_PW_Pos)                  /*!< 0x00010000 */
12128 #define TIM_ECR_PW_1          (0x02UL << TIM_ECR_PW_Pos)                  /*!< 0x00020000 */
12129 #define TIM_ECR_PW_2          (0x04UL << TIM_ECR_PW_Pos)                  /*!< 0x00040000 */
12130 #define TIM_ECR_PW_3          (0x08UL << TIM_ECR_PW_Pos)                  /*!< 0x00080000 */
12131 #define TIM_ECR_PW_4          (0x10UL << TIM_ECR_PW_Pos)                  /*!< 0x00100000 */
12132 #define TIM_ECR_PW_5          (0x20UL << TIM_ECR_PW_Pos)                  /*!< 0x00200000 */
12133 #define TIM_ECR_PW_6          (0x40UL << TIM_ECR_PW_Pos)                  /*!< 0x00400000 */
12134 #define TIM_ECR_PW_7          (0x80UL << TIM_ECR_PW_Pos)                  /*!< 0x00800000 */
12135 
12136 #define TIM_ECR_PWPRSC_Pos    (24U)
12137 #define TIM_ECR_PWPRSC_Msk    (0x7UL << TIM_ECR_PWPRSC_Pos)               /*!< 0x07000000 */
12138 #define TIM_ECR_PWPRSC        TIM_ECR_PWPRSC_Msk                          /*!<PWPRSC[2:0] bits (Pulse width prescaler)*/
12139 #define TIM_ECR_PWPRSC_0      (0x01UL << TIM_ECR_PWPRSC_Pos)              /*!< 0x01000000 */
12140 #define TIM_ECR_PWPRSC_1      (0x02UL << TIM_ECR_PWPRSC_Pos)              /*!< 0x02000000 */
12141 #define TIM_ECR_PWPRSC_2      (0x04UL << TIM_ECR_PWPRSC_Pos)              /*!< 0x04000000 */
12142 
12143 /*******************  Bit definition for TIM_DMAR register  *******************/
12144 #define TIM_DMAR_DMAB_Pos         (0U)
12145 #define TIM_DMAR_DMAB_Msk         (0xFFFFFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0xFFFFFFFF */
12146 #define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                       /*!<DMA register for burst accesses */
12147 
12148 /******************************************************************************/
12149 /*                                                                            */
12150 /*                         Low Power Timer (LPTIM)                           */
12151 /*                                                                            */
12152 /******************************************************************************/
12153 /******************  Bit definition for LPTIM_ISR register  *******************/
12154 #define LPTIM_ISR_CMPM_Pos          (0U)
12155 #define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */
12156 #define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
12157 #define LPTIM_ISR_ARRM_Pos          (1U)
12158 #define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */
12159 #define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
12160 #define LPTIM_ISR_EXTTRIG_Pos       (2U)
12161 #define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */
12162 #define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
12163 #define LPTIM_ISR_CMPOK_Pos         (3U)
12164 #define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */
12165 #define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
12166 #define LPTIM_ISR_ARROK_Pos         (4U)
12167 #define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */
12168 #define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
12169 #define LPTIM_ISR_UP_Pos            (5U)
12170 #define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */
12171 #define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
12172 #define LPTIM_ISR_DOWN_Pos          (6U)
12173 #define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */
12174 #define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
12175 
12176 /******************  Bit definition for LPTIM_ICR register  *******************/
12177 #define LPTIM_ICR_CMPMCF_Pos        (0U)
12178 #define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */
12179 #define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
12180 #define LPTIM_ICR_ARRMCF_Pos        (1U)
12181 #define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */
12182 #define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
12183 #define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
12184 #define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */
12185 #define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
12186 #define LPTIM_ICR_CMPOKCF_Pos       (3U)
12187 #define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */
12188 #define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
12189 #define LPTIM_ICR_ARROKCF_Pos       (4U)
12190 #define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */
12191 #define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
12192 #define LPTIM_ICR_UPCF_Pos          (5U)
12193 #define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */
12194 #define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
12195 #define LPTIM_ICR_DOWNCF_Pos        (6U)
12196 #define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */
12197 #define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
12198 
12199 /******************  Bit definition for LPTIM_IER register ********************/
12200 #define LPTIM_IER_CMPMIE_Pos        (0U)
12201 #define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */
12202 #define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
12203 #define LPTIM_IER_ARRMIE_Pos        (1U)
12204 #define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */
12205 #define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
12206 #define LPTIM_IER_EXTTRIGIE_Pos     (2U)
12207 #define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */
12208 #define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
12209 #define LPTIM_IER_CMPOKIE_Pos       (3U)
12210 #define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */
12211 #define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
12212 #define LPTIM_IER_ARROKIE_Pos       (4U)
12213 #define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */
12214 #define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
12215 #define LPTIM_IER_UPIE_Pos          (5U)
12216 #define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */
12217 #define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
12218 #define LPTIM_IER_DOWNIE_Pos        (6U)
12219 #define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */
12220 #define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
12221 
12222 /******************  Bit definition for LPTIM_CFGR register *******************/
12223 #define LPTIM_CFGR_CKSEL_Pos        (0U)
12224 #define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */
12225 #define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
12226 
12227 #define LPTIM_CFGR_CKPOL_Pos        (1U)
12228 #define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */
12229 #define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
12230 #define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000002 */
12231 #define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000004 */
12232 
12233 #define LPTIM_CFGR_CKFLT_Pos        (3U)
12234 #define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */
12235 #define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
12236 #define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000008 */
12237 #define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000010 */
12238 
12239 #define LPTIM_CFGR_TRGFLT_Pos       (6U)
12240 #define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */
12241 #define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
12242 #define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000040 */
12243 #define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000080 */
12244 
12245 #define LPTIM_CFGR_PRESC_Pos        (9U)
12246 #define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */
12247 #define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
12248 #define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000200 */
12249 #define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000400 */
12250 #define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000800 */
12251 
12252 #define LPTIM_CFGR_TRIGSEL_Pos      (13U)
12253 #define LPTIM_CFGR_TRIGSEL_Msk      (0x10007UL << LPTIM_CFGR_TRIGSEL_Pos)      /*!< 0x0200E000 */
12254 #define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
12255 #define LPTIM_CFGR_TRIGSEL_0        (0x00001UL << LPTIM_CFGR_TRIGSEL_Pos)      /*!< 0x00002000 */
12256 #define LPTIM_CFGR_TRIGSEL_1        (0x00002UL << LPTIM_CFGR_TRIGSEL_Pos)      /*!< 0x00004000 */
12257 #define LPTIM_CFGR_TRIGSEL_2        (0x00004UL << LPTIM_CFGR_TRIGSEL_Pos)      /*!< 0x00008000 */
12258 #define LPTIM_CFGR_TRIGSEL_3        (0x10000UL << LPTIM_CFGR_TRIGSEL_Pos)      /*!< 0x02000000 */
12259 
12260 #define LPTIM_CFGR_TRIGEN_Pos       (17U)
12261 #define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */
12262 #define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
12263 #define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00020000 */
12264 #define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00040000 */
12265 
12266 #define LPTIM_CFGR_TIMOUT_Pos       (19U)
12267 #define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */
12268 #define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
12269 #define LPTIM_CFGR_WAVE_Pos         (20U)
12270 #define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */
12271 #define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
12272 #define LPTIM_CFGR_WAVPOL_Pos       (21U)
12273 #define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */
12274 #define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
12275 #define LPTIM_CFGR_PRELOAD_Pos      (22U)
12276 #define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */
12277 #define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
12278 #define LPTIM_CFGR_COUNTMODE_Pos    (23U)
12279 #define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */
12280 #define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
12281 #define LPTIM_CFGR_ENC_Pos          (24U)
12282 #define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */
12283 #define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
12284 
12285 /******************  Bit definition for LPTIM_CR register  ********************/
12286 #define LPTIM_CR_ENABLE_Pos         (0U)
12287 #define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */
12288 #define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
12289 #define LPTIM_CR_SNGSTRT_Pos        (1U)
12290 #define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)            /*!< 0x00000002 */
12291 #define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
12292 #define LPTIM_CR_CNTSTRT_Pos        (2U)
12293 #define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */
12294 #define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
12295 #define LPTIM_CR_COUNTRST_Pos       (3U)
12296 #define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */
12297 #define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Counter reset */
12298 #define LPTIM_CR_RSTARE_Pos         (4U)
12299 #define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */
12300 #define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Reset after read enable */
12301 
12302 /******************  Bit definition for LPTIM_CMP register  *******************/
12303 #define LPTIM_CMP_CMP_Pos           (0U)
12304 #define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */
12305 #define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
12306 
12307 /******************  Bit definition for LPTIM_ARR register  *******************/
12308 #define LPTIM_ARR_ARR_Pos           (0U)
12309 #define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */
12310 #define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
12311 
12312 /******************  Bit definition for LPTIM_CNT register  *******************/
12313 #define LPTIM_CNT_CNT_Pos           (0U)
12314 #define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */
12315 #define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
12316 
12317 /******************  Bit definition for LPTIM_OR register  *******************/
12318 #define LPTIM_OR_IN1_Pos             (0U)
12319 #define LPTIM_OR_IN1_Msk             (0xDUL << LPTIM_OR_IN1_Pos)                 /*!< 0x0000000D */
12320 #define LPTIM_OR_IN1                 LPTIM_OR_IN1_Msk                            /*!< IN1[2:0] bits (Remap selection) */
12321 #define LPTIM_OR_IN1_0               (0x1UL << LPTIM_OR_IN1_Pos)                 /*!< 0x00000001 */
12322 #define LPTIM_OR_IN1_1               (0x4UL << LPTIM_OR_IN1_Pos)                 /*!< 0x00000004 */
12323 #define LPTIM_OR_IN1_2               (0x8UL << LPTIM_OR_IN1_Pos)                 /*!< 0x00000008 */
12324 
12325 #define LPTIM_OR_IN2_Pos             (1U)
12326 #define LPTIM_OR_IN2_Msk             (0x19UL << LPTIM_OR_IN2_Pos)                 /*!< 0x00000032 */
12327 #define LPTIM_OR_IN2                 LPTIM_OR_IN2_Msk                            /*!< IN2[2:0] bits (Remap selection) */
12328 #define LPTIM_OR_IN2_0               (0x1UL << LPTIM_OR_IN2_Pos)                 /*!< 0x00000002 */
12329 #define LPTIM_OR_IN2_1               (0x8UL << LPTIM_OR_IN2_Pos)                 /*!< 0x00000010 */
12330 #define LPTIM_OR_IN2_2               (0x10UL << LPTIM_OR_IN2_Pos)                 /*!< 0x00000020 */
12331 /******************************************************************************/
12332 /*                                                                            */
12333 /*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
12334 /*                                                                            */
12335 /******************************************************************************/
12336 /******************  Bit definition for USART_CR1 register  *******************/
12337 #define USART_CR1_UE_Pos             (0U)
12338 #define USART_CR1_UE_Msk             (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
12339 #define USART_CR1_UE                 USART_CR1_UE_Msk                          /*!< USART Enable */
12340 #define USART_CR1_UESM_Pos           (1U)
12341 #define USART_CR1_UESM_Msk           (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
12342 #define USART_CR1_UESM               USART_CR1_UESM_Msk                        /*!< USART Enable in STOP Mode */
12343 #define USART_CR1_RE_Pos             (2U)
12344 #define USART_CR1_RE_Msk             (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
12345 #define USART_CR1_RE                 USART_CR1_RE_Msk                          /*!< Receiver Enable */
12346 #define USART_CR1_TE_Pos             (3U)
12347 #define USART_CR1_TE_Msk             (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
12348 #define USART_CR1_TE                 USART_CR1_TE_Msk                          /*!< Transmitter Enable */
12349 #define USART_CR1_IDLEIE_Pos         (4U)
12350 #define USART_CR1_IDLEIE_Msk         (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
12351 #define USART_CR1_IDLEIE             USART_CR1_IDLEIE_Msk                      /*!< IDLE Interrupt Enable */
12352 #define USART_CR1_RXNEIE_Pos         (5U)
12353 #define USART_CR1_RXNEIE_Msk         (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
12354 #define USART_CR1_RXNEIE             USART_CR1_RXNEIE_Msk                      /*!< RXNE Interrupt Enable */
12355 #define USART_CR1_RXNEIE_RXFNEIE_Pos USART_CR1_RXNEIE_Pos
12356 #define USART_CR1_RXNEIE_RXFNEIE_Msk USART_CR1_RXNEIE_Msk                      /*!< 0x00000020 */
12357 #define USART_CR1_RXNEIE_RXFNEIE     USART_CR1_RXNEIE_Msk                      /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
12358 #define USART_CR1_TCIE_Pos           (6U)
12359 #define USART_CR1_TCIE_Msk           (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
12360 #define USART_CR1_TCIE               USART_CR1_TCIE_Msk                        /*!< Transmission Complete Interrupt Enable */
12361 #define USART_CR1_TXEIE_Pos          (7U)
12362 #define USART_CR1_TXEIE_Msk          (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
12363 #define USART_CR1_TXEIE              USART_CR1_TXEIE_Msk                       /*!< TXE Interrupt Enable */
12364 #define USART_CR1_TXEIE_TXFNFIE_Pos  USART_CR1_TXEIE_Pos
12365 #define USART_CR1_TXEIE_TXFNFIE_Msk  USART_CR1_TXEIE_Msk                       /*!< 0x00000080 */
12366 #define USART_CR1_TXEIE_TXFNFIE      USART_CR1_TXEIE_Msk                       /*!< TXE and TX FIFO Not Full Interrupt Enable */
12367 #define USART_CR1_PEIE_Pos           (8U)
12368 #define USART_CR1_PEIE_Msk           (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
12369 #define USART_CR1_PEIE               USART_CR1_PEIE_Msk                        /*!< PE Interrupt Enable */
12370 #define USART_CR1_PS_Pos             (9U)
12371 #define USART_CR1_PS_Msk             (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
12372 #define USART_CR1_PS                 USART_CR1_PS_Msk                          /*!< Parity Selection */
12373 #define USART_CR1_PCE_Pos            (10U)
12374 #define USART_CR1_PCE_Msk            (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
12375 #define USART_CR1_PCE                USART_CR1_PCE_Msk                         /*!< Parity Control Enable */
12376 #define USART_CR1_WAKE_Pos           (11U)
12377 #define USART_CR1_WAKE_Msk           (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
12378 #define USART_CR1_WAKE               USART_CR1_WAKE_Msk                        /*!< Receiver Wakeup method */
12379 #define USART_CR1_M_Pos              (12U)
12380 #define USART_CR1_M_Msk              (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
12381 #define USART_CR1_M                  USART_CR1_M_Msk                           /*!< Word length */
12382 #define USART_CR1_M0_Pos             (12U)
12383 #define USART_CR1_M0_Msk             (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
12384 #define USART_CR1_M0                 USART_CR1_M0_Msk                          /*!< Word length - Bit 0 */
12385 #define USART_CR1_MME_Pos            (13U)
12386 #define USART_CR1_MME_Msk            (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
12387 #define USART_CR1_MME                USART_CR1_MME_Msk                         /*!< Mute Mode Enable */
12388 #define USART_CR1_CMIE_Pos           (14U)
12389 #define USART_CR1_CMIE_Msk           (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
12390 #define USART_CR1_CMIE               USART_CR1_CMIE_Msk                        /*!< Character match interrupt enable */
12391 #define USART_CR1_OVER8_Pos          (15U)
12392 #define USART_CR1_OVER8_Msk          (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
12393 #define USART_CR1_OVER8              USART_CR1_OVER8_Msk                       /*!< Oversampling by 8-bit or 16-bit mode */
12394 #define USART_CR1_DEDT_Pos           (16U)
12395 #define USART_CR1_DEDT_Msk           (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
12396 #define USART_CR1_DEDT               USART_CR1_DEDT_Msk                        /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
12397 #define USART_CR1_DEDT_0             (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
12398 #define USART_CR1_DEDT_1             (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
12399 #define USART_CR1_DEDT_2             (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
12400 #define USART_CR1_DEDT_3             (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
12401 #define USART_CR1_DEDT_4             (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
12402 #define USART_CR1_DEAT_Pos           (21U)
12403 #define USART_CR1_DEAT_Msk           (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
12404 #define USART_CR1_DEAT               USART_CR1_DEAT_Msk                        /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
12405 #define USART_CR1_DEAT_0             (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
12406 #define USART_CR1_DEAT_1             (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
12407 #define USART_CR1_DEAT_2             (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
12408 #define USART_CR1_DEAT_3             (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
12409 #define USART_CR1_DEAT_4             (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
12410 #define USART_CR1_RTOIE_Pos          (26U)
12411 #define USART_CR1_RTOIE_Msk          (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
12412 #define USART_CR1_RTOIE              USART_CR1_RTOIE_Msk                       /*!< Receive Time Out interrupt enable */
12413 #define USART_CR1_EOBIE_Pos          (27U)
12414 #define USART_CR1_EOBIE_Msk          (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
12415 #define USART_CR1_EOBIE              USART_CR1_EOBIE_Msk                       /*!< End of Block interrupt enable */
12416 #define USART_CR1_M1_Pos             (28U)
12417 #define USART_CR1_M1_Msk             (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
12418 #define USART_CR1_M1                 USART_CR1_M1_Msk                          /*!< Word length - Bit 1 */
12419 #define USART_CR1_FIFOEN_Pos         (29U)
12420 #define USART_CR1_FIFOEN_Msk         (0x1UL << USART_CR1_FIFOEN_Pos)           /*!< 0x20000000 */
12421 #define USART_CR1_FIFOEN             USART_CR1_FIFOEN_Msk                      /*!< FIFO mode enable */
12422 #define USART_CR1_TXFEIE_Pos         (30U)
12423 #define USART_CR1_TXFEIE_Msk         (0x1UL << USART_CR1_TXFEIE_Pos)           /*!< 0x40000000 */
12424 #define USART_CR1_TXFEIE             USART_CR1_TXFEIE_Msk                      /*!< TXFIFO empty interrupt enable */
12425 #define USART_CR1_RXFFIE_Pos         (31U)
12426 #define USART_CR1_RXFFIE_Msk         (0x1UL << USART_CR1_RXFFIE_Pos)           /*!< 0x80000000 */
12427 #define USART_CR1_RXFFIE             USART_CR1_RXFFIE_Msk                      /*!< RXFIFO Full interrupt enable */
12428 
12429 /******************  Bit definition for USART_CR2 register  *******************/
12430 #define USART_CR2_SLVEN_Pos          (0U)
12431 #define USART_CR2_SLVEN_Msk          (0x1UL << USART_CR2_SLVEN_Pos)            /*!< 0x00000001 */
12432 #define USART_CR2_SLVEN              USART_CR2_SLVEN_Msk                       /*!< Synchronous Slave mode enable */
12433 #define USART_CR2_DIS_NSS_Pos        (3U)
12434 #define USART_CR2_DIS_NSS_Msk        (0x1UL << USART_CR2_DIS_NSS_Pos)          /*!< 0x00000008 */
12435 #define USART_CR2_DIS_NSS            USART_CR2_DIS_NSS_Msk                     /*!< Slave Select (NSS) pin management */
12436 #define USART_CR2_ADDM7_Pos          (4U)
12437 #define USART_CR2_ADDM7_Msk          (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
12438 #define USART_CR2_ADDM7              USART_CR2_ADDM7_Msk                       /*!< 7-bit or 4-bit Address Detection */
12439 #define USART_CR2_LBDL_Pos           (5U)
12440 #define USART_CR2_LBDL_Msk           (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
12441 #define USART_CR2_LBDL               USART_CR2_LBDL_Msk                        /*!< LIN Break Detection Length */
12442 #define USART_CR2_LBDIE_Pos          (6U)
12443 #define USART_CR2_LBDIE_Msk          (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
12444 #define USART_CR2_LBDIE              USART_CR2_LBDIE_Msk                       /*!< LIN Break Detection Interrupt Enable */
12445 #define USART_CR2_LBCL_Pos           (8U)
12446 #define USART_CR2_LBCL_Msk           (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
12447 #define USART_CR2_LBCL               USART_CR2_LBCL_Msk                        /*!< Last Bit Clock pulse */
12448 #define USART_CR2_CPHA_Pos           (9U)
12449 #define USART_CR2_CPHA_Msk           (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
12450 #define USART_CR2_CPHA               USART_CR2_CPHA_Msk                        /*!< Clock Phase */
12451 #define USART_CR2_CPOL_Pos           (10U)
12452 #define USART_CR2_CPOL_Msk           (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
12453 #define USART_CR2_CPOL               USART_CR2_CPOL_Msk                        /*!< Clock Polarity */
12454 #define USART_CR2_CLKEN_Pos          (11U)
12455 #define USART_CR2_CLKEN_Msk          (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
12456 #define USART_CR2_CLKEN              USART_CR2_CLKEN_Msk                       /*!< Clock Enable */
12457 #define USART_CR2_STOP_Pos           (12U)
12458 #define USART_CR2_STOP_Msk           (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
12459 #define USART_CR2_STOP               USART_CR2_STOP_Msk                        /*!< STOP[1:0] bits (STOP bits) */
12460 #define USART_CR2_STOP_0             (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
12461 #define USART_CR2_STOP_1             (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
12462 #define USART_CR2_LINEN_Pos          (14U)
12463 #define USART_CR2_LINEN_Msk          (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
12464 #define USART_CR2_LINEN              USART_CR2_LINEN_Msk                       /*!< LIN mode enable */
12465 #define USART_CR2_SWAP_Pos           (15U)
12466 #define USART_CR2_SWAP_Msk           (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
12467 #define USART_CR2_SWAP               USART_CR2_SWAP_Msk                        /*!< SWAP TX/RX pins */
12468 #define USART_CR2_RXINV_Pos          (16U)
12469 #define USART_CR2_RXINV_Msk          (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
12470 #define USART_CR2_RXINV              USART_CR2_RXINV_Msk                       /*!< RX pin active level inversion */
12471 #define USART_CR2_TXINV_Pos          (17U)
12472 #define USART_CR2_TXINV_Msk          (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
12473 #define USART_CR2_TXINV              USART_CR2_TXINV_Msk                       /*!< TX pin active level inversion */
12474 #define USART_CR2_DATAINV_Pos        (18U)
12475 #define USART_CR2_DATAINV_Msk        (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
12476 #define USART_CR2_DATAINV            USART_CR2_DATAINV_Msk                     /*!< Binary data inversion */
12477 #define USART_CR2_MSBFIRST_Pos       (19U)
12478 #define USART_CR2_MSBFIRST_Msk       (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
12479 #define USART_CR2_MSBFIRST           USART_CR2_MSBFIRST_Msk                    /*!< Most Significant Bit First */
12480 #define USART_CR2_ABREN_Pos          (20U)
12481 #define USART_CR2_ABREN_Msk          (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
12482 #define USART_CR2_ABREN              USART_CR2_ABREN_Msk                       /*!< Auto Baud-Rate Enable*/
12483 #define USART_CR2_ABRMODE_Pos        (21U)
12484 #define USART_CR2_ABRMODE_Msk        (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
12485 #define USART_CR2_ABRMODE            USART_CR2_ABRMODE_Msk                     /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
12486 #define USART_CR2_ABRMODE_0          (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
12487 #define USART_CR2_ABRMODE_1          (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
12488 #define USART_CR2_RTOEN_Pos          (23U)
12489 #define USART_CR2_RTOEN_Msk          (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
12490 #define USART_CR2_RTOEN              USART_CR2_RTOEN_Msk                       /*!< Receiver Time-Out enable */
12491 #define USART_CR2_ADD_Pos            (24U)
12492 #define USART_CR2_ADD_Msk            (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
12493 #define USART_CR2_ADD                USART_CR2_ADD_Msk                         /*!< Address of the USART node */
12494 
12495 /******************  Bit definition for USART_CR3 register  *******************/
12496 #define USART_CR3_EIE_Pos            (0U)
12497 #define USART_CR3_EIE_Msk            (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
12498 #define USART_CR3_EIE                USART_CR3_EIE_Msk                         /*!< Error Interrupt Enable */
12499 #define USART_CR3_IREN_Pos           (1U)
12500 #define USART_CR3_IREN_Msk           (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
12501 #define USART_CR3_IREN               USART_CR3_IREN_Msk                        /*!< IrDA mode Enable */
12502 #define USART_CR3_IRLP_Pos           (2U)
12503 #define USART_CR3_IRLP_Msk           (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
12504 #define USART_CR3_IRLP               USART_CR3_IRLP_Msk                        /*!< IrDA Low-Power */
12505 #define USART_CR3_HDSEL_Pos          (3U)
12506 #define USART_CR3_HDSEL_Msk          (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
12507 #define USART_CR3_HDSEL              USART_CR3_HDSEL_Msk                       /*!< Half-Duplex Selection */
12508 #define USART_CR3_NACK_Pos           (4U)
12509 #define USART_CR3_NACK_Msk           (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
12510 #define USART_CR3_NACK               USART_CR3_NACK_Msk                        /*!< SmartCard NACK enable */
12511 #define USART_CR3_SCEN_Pos           (5U)
12512 #define USART_CR3_SCEN_Msk           (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
12513 #define USART_CR3_SCEN               USART_CR3_SCEN_Msk                        /*!< SmartCard mode enable */
12514 #define USART_CR3_DMAR_Pos           (6U)
12515 #define USART_CR3_DMAR_Msk           (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
12516 #define USART_CR3_DMAR               USART_CR3_DMAR_Msk                        /*!< DMA Enable Receiver */
12517 #define USART_CR3_DMAT_Pos           (7U)
12518 #define USART_CR3_DMAT_Msk           (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
12519 #define USART_CR3_DMAT               USART_CR3_DMAT_Msk                        /*!< DMA Enable Transmitter */
12520 #define USART_CR3_RTSE_Pos           (8U)
12521 #define USART_CR3_RTSE_Msk           (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
12522 #define USART_CR3_RTSE               USART_CR3_RTSE_Msk                        /*!< RTS Enable */
12523 #define USART_CR3_CTSE_Pos           (9U)
12524 #define USART_CR3_CTSE_Msk           (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
12525 #define USART_CR3_CTSE               USART_CR3_CTSE_Msk                        /*!< CTS Enable */
12526 #define USART_CR3_CTSIE_Pos          (10U)
12527 #define USART_CR3_CTSIE_Msk          (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
12528 #define USART_CR3_CTSIE              USART_CR3_CTSIE_Msk                       /*!< CTS Interrupt Enable */
12529 #define USART_CR3_ONEBIT_Pos         (11U)
12530 #define USART_CR3_ONEBIT_Msk         (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
12531 #define USART_CR3_ONEBIT             USART_CR3_ONEBIT_Msk                      /*!< One sample bit method enable */
12532 #define USART_CR3_OVRDIS_Pos         (12U)
12533 #define USART_CR3_OVRDIS_Msk         (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
12534 #define USART_CR3_OVRDIS             USART_CR3_OVRDIS_Msk                      /*!< Overrun Disable */
12535 #define USART_CR3_DDRE_Pos           (13U)
12536 #define USART_CR3_DDRE_Msk           (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
12537 #define USART_CR3_DDRE               USART_CR3_DDRE_Msk                        /*!< DMA Disable on Reception Error */
12538 #define USART_CR3_DEM_Pos            (14U)
12539 #define USART_CR3_DEM_Msk            (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
12540 #define USART_CR3_DEM                USART_CR3_DEM_Msk                         /*!< Driver Enable Mode */
12541 #define USART_CR3_DEP_Pos            (15U)
12542 #define USART_CR3_DEP_Msk            (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
12543 #define USART_CR3_DEP                USART_CR3_DEP_Msk                         /*!< Driver Enable Polarity Selection */
12544 #define USART_CR3_SCARCNT_Pos        (17U)
12545 #define USART_CR3_SCARCNT_Msk        (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
12546 #define USART_CR3_SCARCNT            USART_CR3_SCARCNT_Msk                     /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
12547 #define USART_CR3_SCARCNT_0          (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
12548 #define USART_CR3_SCARCNT_1          (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
12549 #define USART_CR3_SCARCNT_2          (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
12550 #define USART_CR3_WUS_Pos            (20U)
12551 #define USART_CR3_WUS_Msk            (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
12552 #define USART_CR3_WUS                USART_CR3_WUS_Msk                         /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
12553 #define USART_CR3_WUS_0              (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
12554 #define USART_CR3_WUS_1              (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
12555 #define USART_CR3_WUFIE_Pos          (22U)
12556 #define USART_CR3_WUFIE_Msk          (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
12557 #define USART_CR3_WUFIE              USART_CR3_WUFIE_Msk                       /*!< Wake Up Interrupt Enable */
12558 #define USART_CR3_TXFTIE_Pos         (23U)
12559 #define USART_CR3_TXFTIE_Msk         (0x1UL << USART_CR3_TXFTIE_Pos)           /*!< 0x00800000 */
12560 #define USART_CR3_TXFTIE             USART_CR3_TXFTIE_Msk                      /*!< TXFIFO threshold interrupt enable */
12561 #define USART_CR3_TCBGTIE_Pos        (24U)
12562 #define USART_CR3_TCBGTIE_Msk        (0x1UL << USART_CR3_TCBGTIE_Pos)          /*!< 0x01000000 */
12563 #define USART_CR3_TCBGTIE            USART_CR3_TCBGTIE_Msk                     /*!< Transmission Complete Before Guard Time Interrupt Enable */
12564 #define USART_CR3_RXFTCFG_Pos        (25U)
12565 #define USART_CR3_RXFTCFG_Msk        (0x7UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x0E000000 */
12566 #define USART_CR3_RXFTCFG            USART_CR3_RXFTCFG_Msk                     /*!< RXFIFO FIFO threshold configuration */
12567 #define USART_CR3_RXFTCFG_0          (0x1UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x02000000 */
12568 #define USART_CR3_RXFTCFG_1          (0x2UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x04000000 */
12569 #define USART_CR3_RXFTCFG_2          (0x4UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x08000000 */
12570 #define USART_CR3_RXFTIE_Pos         (28U)
12571 #define USART_CR3_RXFTIE_Msk         (0x1UL << USART_CR3_RXFTIE_Pos)           /*!< 0x10000000 */
12572 #define USART_CR3_RXFTIE             USART_CR3_RXFTIE_Msk                      /*!< RXFIFO threshold interrupt enable */
12573 #define USART_CR3_TXFTCFG_Pos        (29U)
12574 #define USART_CR3_TXFTCFG_Msk        (0x7UL << USART_CR3_TXFTCFG_Pos)          /*!< 0xE0000000 */
12575 #define USART_CR3_TXFTCFG            USART_CR3_TXFTCFG_Msk                     /*!< TXFIFO threshold configuration */
12576 #define USART_CR3_TXFTCFG_0          (0x1UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x20000000 */
12577 #define USART_CR3_TXFTCFG_1          (0x2UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x40000000 */
12578 #define USART_CR3_TXFTCFG_2          (0x4UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x80000000 */
12579 
12580 /******************  Bit definition for USART_BRR register  *******************/
12581 #define USART_BRR_LPUART_Pos         (0U)
12582 #define USART_BRR_LPUART_Msk         (0xFFFFFUL << USART_BRR_LPUART_Pos)       /*!< 0x000FFFFF */
12583 #define USART_BRR_LPUART             USART_BRR_LPUART_Msk                      /*!< LPUART Baud rate register [19:0] */
12584 #define USART_BRR_BRR_Pos            (0U)
12585 #define USART_BRR_BRR_Msk            (0xFFFFUL << USART_BRR_BRR_Pos)           /*!< 0x0000FFFF */
12586 #define USART_BRR_BRR                USART_BRR_BRR_Msk                         /*!< USART Baud rate register [15:0] */
12587 
12588 /******************  Bit definition for USART_GTPR register  ******************/
12589 #define USART_GTPR_PSC_Pos           (0U)
12590 #define USART_GTPR_PSC_Msk           (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
12591 #define USART_GTPR_PSC               USART_GTPR_PSC_Msk                        /*!< PSC[7:0] bits (Prescaler value) */
12592 #define USART_GTPR_GT_Pos            (8U)
12593 #define USART_GTPR_GT_Msk            (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
12594 #define USART_GTPR_GT                USART_GTPR_GT_Msk                         /*!< GT[7:0] bits (Guard time value) */
12595 
12596 /*******************  Bit definition for USART_RTOR register  *****************/
12597 #define USART_RTOR_RTO_Pos           (0U)
12598 #define USART_RTOR_RTO_Msk           (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
12599 #define USART_RTOR_RTO               USART_RTOR_RTO_Msk                        /*!< Receiver Time Out Value */
12600 #define USART_RTOR_BLEN_Pos          (24U)
12601 #define USART_RTOR_BLEN_Msk          (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
12602 #define USART_RTOR_BLEN              USART_RTOR_BLEN_Msk                       /*!< Block Length */
12603 
12604 /*******************  Bit definition for USART_RQR register  ******************/
12605 #define USART_RQR_ABRRQ_Pos          (0U)
12606 #define USART_RQR_ABRRQ_Msk          (0x1UL << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
12607 #define USART_RQR_ABRRQ              USART_RQR_ABRRQ_Msk                       /*!< Auto-Baud Rate Request */
12608 #define USART_RQR_SBKRQ_Pos          (1U)
12609 #define USART_RQR_SBKRQ_Msk          (0x1UL << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
12610 #define USART_RQR_SBKRQ              USART_RQR_SBKRQ_Msk                       /*!< Send Break Request */
12611 #define USART_RQR_MMRQ_Pos           (2U)
12612 #define USART_RQR_MMRQ_Msk           (0x1UL << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
12613 #define USART_RQR_MMRQ               USART_RQR_MMRQ_Msk                        /*!< Mute Mode Request */
12614 #define USART_RQR_RXFRQ_Pos          (3U)
12615 #define USART_RQR_RXFRQ_Msk          (0x1UL << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
12616 #define USART_RQR_RXFRQ              USART_RQR_RXFRQ_Msk                       /*!< Receive Data flush Request */
12617 #define USART_RQR_TXFRQ_Pos          (4U)
12618 #define USART_RQR_TXFRQ_Msk          (0x1UL << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
12619 #define USART_RQR_TXFRQ              USART_RQR_TXFRQ_Msk                       /*!< Transmit data flush Request */
12620 
12621 /*******************  Bit definition for USART_ISR register  ******************/
12622 #define USART_ISR_PE_Pos             (0U)
12623 #define USART_ISR_PE_Msk             (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
12624 #define USART_ISR_PE                 USART_ISR_PE_Msk                          /*!< Parity Error */
12625 #define USART_ISR_FE_Pos             (1U)
12626 #define USART_ISR_FE_Msk             (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
12627 #define USART_ISR_FE                 USART_ISR_FE_Msk                          /*!< Framing Error */
12628 #define USART_ISR_NE_Pos             (2U)
12629 #define USART_ISR_NE_Msk             (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
12630 #define USART_ISR_NE                 USART_ISR_NE_Msk                          /*!< Noise detected Flag */
12631 #define USART_ISR_ORE_Pos            (3U)
12632 #define USART_ISR_ORE_Msk            (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
12633 #define USART_ISR_ORE                USART_ISR_ORE_Msk                         /*!< OverRun Error */
12634 #define USART_ISR_IDLE_Pos           (4U)
12635 #define USART_ISR_IDLE_Msk           (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
12636 #define USART_ISR_IDLE               USART_ISR_IDLE_Msk                        /*!< IDLE line detected */
12637 #define USART_ISR_RXNE_Pos           (5U)
12638 #define USART_ISR_RXNE_Msk           (0x1UL << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
12639 #define USART_ISR_RXNE               USART_ISR_RXNE_Msk                        /*!< Read Data Register Not Empty */
12640 #define USART_ISR_RXNE_RXFNE_Pos     USART_ISR_RXNE_Pos
12641 #define USART_ISR_RXNE_RXFNE_Msk     USART_ISR_RXNE_Msk                        /*!< 0x00000020 */
12642 #define USART_ISR_RXNE_RXFNE         USART_ISR_RXNE_Msk                        /*!< Read Data Register or RX FIFO Not Empty */
12643 #define USART_ISR_TC_Pos             (6U)
12644 #define USART_ISR_TC_Msk             (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
12645 #define USART_ISR_TC                 USART_ISR_TC_Msk                          /*!< Transmission Complete */
12646 #define USART_ISR_TXE_Pos            (7U)
12647 #define USART_ISR_TXE_Msk            (0x1UL << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
12648 #define USART_ISR_TXE                USART_ISR_TXE_Msk                         /*!< Transmit Data Register Empty */
12649 #define USART_ISR_TXE_TXFNF_Pos      USART_ISR_TXE_Pos
12650 #define USART_ISR_TXE_TXFNF_Msk      USART_ISR_TXE_Msk                       /*!< 0x00000080 */
12651 #define USART_ISR_TXE_TXFNF          USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
12652 #define USART_ISR_LBDF_Pos           (8U)
12653 #define USART_ISR_LBDF_Msk           (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
12654 #define USART_ISR_LBDF               USART_ISR_LBDF_Msk                        /*!< LIN Break Detection Flag */
12655 #define USART_ISR_CTSIF_Pos          (9U)
12656 #define USART_ISR_CTSIF_Msk          (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
12657 #define USART_ISR_CTSIF              USART_ISR_CTSIF_Msk                       /*!< CTS interrupt flag */
12658 #define USART_ISR_CTS_Pos            (10U)
12659 #define USART_ISR_CTS_Msk            (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
12660 #define USART_ISR_CTS                USART_ISR_CTS_Msk                         /*!< CTS flag */
12661 #define USART_ISR_RTOF_Pos           (11U)
12662 #define USART_ISR_RTOF_Msk           (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
12663 #define USART_ISR_RTOF               USART_ISR_RTOF_Msk                        /*!< Receiver Time Out */
12664 #define USART_ISR_EOBF_Pos           (12U)
12665 #define USART_ISR_EOBF_Msk           (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
12666 #define USART_ISR_EOBF               USART_ISR_EOBF_Msk                        /*!< End Of Block Flag */
12667 #define USART_ISR_UDR_Pos            (13U)
12668 #define USART_ISR_UDR_Msk            (0x1UL << USART_ISR_UDR_Pos)              /*!< 0x00002000 */
12669 #define USART_ISR_UDR                USART_ISR_UDR_Msk                         /*!< SPI slave underrun error flag */
12670 #define USART_ISR_ABRE_Pos           (14U)
12671 #define USART_ISR_ABRE_Msk           (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
12672 #define USART_ISR_ABRE               USART_ISR_ABRE_Msk                        /*!< Auto-Baud Rate Error */
12673 #define USART_ISR_ABRF_Pos           (15U)
12674 #define USART_ISR_ABRF_Msk           (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
12675 #define USART_ISR_ABRF               USART_ISR_ABRF_Msk                        /*!< Auto-Baud Rate Flag */
12676 #define USART_ISR_BUSY_Pos           (16U)
12677 #define USART_ISR_BUSY_Msk           (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
12678 #define USART_ISR_BUSY               USART_ISR_BUSY_Msk                        /*!< Busy Flag */
12679 #define USART_ISR_CMF_Pos            (17U)
12680 #define USART_ISR_CMF_Msk            (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
12681 #define USART_ISR_CMF                USART_ISR_CMF_Msk                         /*!< Character Match Flag */
12682 #define USART_ISR_SBKF_Pos           (18U)
12683 #define USART_ISR_SBKF_Msk           (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
12684 #define USART_ISR_SBKF               USART_ISR_SBKF_Msk                        /*!< Send Break Flag */
12685 #define USART_ISR_RWU_Pos            (19U)
12686 #define USART_ISR_RWU_Msk            (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
12687 #define USART_ISR_RWU                USART_ISR_RWU_Msk                         /*!< Receive Wake Up from mute mode Flag */
12688 #define USART_ISR_WUF_Pos            (20U)
12689 #define USART_ISR_WUF_Msk            (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
12690 #define USART_ISR_WUF                USART_ISR_WUF_Msk                         /*!< Wake Up from stop mode Flag */
12691 #define USART_ISR_TEACK_Pos          (21U)
12692 #define USART_ISR_TEACK_Msk          (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
12693 #define USART_ISR_TEACK              USART_ISR_TEACK_Msk                       /*!< Transmit Enable Acknowledge Flag */
12694 #define USART_ISR_REACK_Pos          (22U)
12695 #define USART_ISR_REACK_Msk          (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
12696 #define USART_ISR_REACK              USART_ISR_REACK_Msk                       /*!< Receive Enable Acknowledge Flag */
12697 #define USART_ISR_TXFE_Pos           (23U)
12698 #define USART_ISR_TXFE_Msk           (0x1UL << USART_ISR_TXFE_Pos)             /*!< 0x00800000 */
12699 #define USART_ISR_TXFE               USART_ISR_TXFE_Msk                        /*!< TXFIFO Empty */
12700 #define USART_ISR_RXFF_Pos           (24U)
12701 #define USART_ISR_RXFF_Msk           (0x1UL << USART_ISR_RXFF_Pos)             /*!< 0x01000000 */
12702 #define USART_ISR_RXFF               USART_ISR_RXFF_Msk                        /*!< RXFIFO Full */
12703 #define USART_ISR_TCBGT_Pos          (25U)
12704 #define USART_ISR_TCBGT_Msk          (0x1UL << USART_ISR_TCBGT_Pos)            /*!< 0x02000000 */
12705 #define USART_ISR_TCBGT              USART_ISR_TCBGT_Msk                       /*!< Transmission Complete Before Guard Time completion */
12706 #define USART_ISR_RXFT_Pos           (26U)
12707 #define USART_ISR_RXFT_Msk           (0x1UL << USART_ISR_RXFT_Pos)             /*!< 0x04000000 */
12708 #define USART_ISR_RXFT               USART_ISR_RXFT_Msk                        /*!< RXFIFO threshold flag */
12709 #define USART_ISR_TXFT_Pos           (27U)
12710 #define USART_ISR_TXFT_Msk           (0x1UL << USART_ISR_TXFT_Pos)             /*!< 0x08000000 */
12711 #define USART_ISR_TXFT               USART_ISR_TXFT_Msk                        /*!< TXFIFO threshold flag */
12712 
12713 /*******************  Bit definition for USART_ICR register  ******************/
12714 #define USART_ICR_PECF_Pos           (0U)
12715 #define USART_ICR_PECF_Msk           (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
12716 #define USART_ICR_PECF               USART_ICR_PECF_Msk                        /*!< Parity Error Clear Flag */
12717 #define USART_ICR_FECF_Pos           (1U)
12718 #define USART_ICR_FECF_Msk           (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
12719 #define USART_ICR_FECF               USART_ICR_FECF_Msk                        /*!< Framing Error Clear Flag */
12720 #define USART_ICR_NECF_Pos           (2U)
12721 #define USART_ICR_NECF_Msk           (0x1UL << USART_ICR_NECF_Pos)             /*!< 0x00000004 */
12722 #define USART_ICR_NECF               USART_ICR_NECF_Msk                        /*!< Noise detected Clear Flag */
12723 #define USART_ICR_ORECF_Pos          (3U)
12724 #define USART_ICR_ORECF_Msk          (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
12725 #define USART_ICR_ORECF              USART_ICR_ORECF_Msk                       /*!< OverRun Error Clear Flag */
12726 #define USART_ICR_IDLECF_Pos         (4U)
12727 #define USART_ICR_IDLECF_Msk         (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
12728 #define USART_ICR_IDLECF             USART_ICR_IDLECF_Msk                      /*!< IDLE line detected Clear Flag */
12729 #define USART_ICR_TXFECF_Pos         (5U)
12730 #define USART_ICR_TXFECF_Msk         (0x1UL << USART_ICR_TXFECF_Pos)           /*!< 0x00000020 */
12731 #define USART_ICR_TXFECF             USART_ICR_TXFECF_Msk                      /*!< TXFIFO empty Clear flag */
12732 #define USART_ICR_TCCF_Pos           (6U)
12733 #define USART_ICR_TCCF_Msk           (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
12734 #define USART_ICR_TCCF               USART_ICR_TCCF_Msk                        /*!< Transmission Complete Clear Flag */
12735 #define USART_ICR_TCBGTCF_Pos        (7U)
12736 #define USART_ICR_TCBGTCF_Msk        (0x1UL << USART_ICR_TCBGTCF_Pos)          /*!< 0x00000080 */
12737 #define USART_ICR_TCBGTCF            USART_ICR_TCBGTCF_Msk                     /*!< Transmission Complete Before Guard Time Clear Flag */
12738 #define USART_ICR_LBDCF_Pos          (8U)
12739 #define USART_ICR_LBDCF_Msk          (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
12740 #define USART_ICR_LBDCF              USART_ICR_LBDCF_Msk                       /*!< LIN Break Detection Clear Flag */
12741 #define USART_ICR_CTSCF_Pos          (9U)
12742 #define USART_ICR_CTSCF_Msk          (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
12743 #define USART_ICR_CTSCF              USART_ICR_CTSCF_Msk                       /*!< CTS Interrupt Clear Flag */
12744 #define USART_ICR_RTOCF_Pos          (11U)
12745 #define USART_ICR_RTOCF_Msk          (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
12746 #define USART_ICR_RTOCF              USART_ICR_RTOCF_Msk                       /*!< Receiver Time Out Clear Flag */
12747 #define USART_ICR_EOBCF_Pos          (12U)
12748 #define USART_ICR_EOBCF_Msk          (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
12749 #define USART_ICR_EOBCF              USART_ICR_EOBCF_Msk                       /*!< End Of Block Clear Flag */
12750 #define USART_ICR_UDRCF_Pos          (13U)
12751 #define USART_ICR_UDRCF_Msk          (0x1UL << USART_ICR_UDRCF_Pos)            /*!< 0x00002000 */
12752 #define USART_ICR_UDRCF              USART_ICR_UDRCF_Msk                       /*!< SPI Slave Underrun Clear Flag */
12753 #define USART_ICR_CMCF_Pos           (17U)
12754 #define USART_ICR_CMCF_Msk           (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
12755 #define USART_ICR_CMCF               USART_ICR_CMCF_Msk                        /*!< Character Match Clear Flag */
12756 #define USART_ICR_WUCF_Pos           (20U)
12757 #define USART_ICR_WUCF_Msk           (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
12758 #define USART_ICR_WUCF               USART_ICR_WUCF_Msk                        /*!< Wake Up from stop mode Clear Flag */
12759 
12760 /*******************  Bit definition for USART_RDR register  ******************/
12761 #define USART_RDR_RDR_Pos            (0U)
12762 #define USART_RDR_RDR_Msk            (0x1FFUL << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
12763 #define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
12764 
12765 /*******************  Bit definition for USART_TDR register  ******************/
12766 #define USART_TDR_TDR_Pos            (0U)
12767 #define USART_TDR_TDR_Msk            (0x1FFUL << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
12768 #define USART_TDR_TDR                USART_TDR_TDR_Msk                         /*!< TDR[8:0] bits (Transmit Data value) */
12769 
12770 /*******************  Bit definition for USART_PRESC register  ****************/
12771 #define USART_PRESC_PRESCALER_Pos    (0U)
12772 #define USART_PRESC_PRESCALER_Msk    (0xFUL << USART_PRESC_PRESCALER_Pos)      /*!< 0x0000000F */
12773 #define USART_PRESC_PRESCALER        USART_PRESC_PRESCALER_Msk                 /*!< PRESCALER[3:0] bits (Clock prescaler) */
12774 #define USART_PRESC_PRESCALER_0      (0x1UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000001 */
12775 #define USART_PRESC_PRESCALER_1      (0x2UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000002 */
12776 #define USART_PRESC_PRESCALER_2      (0x4UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000004 */
12777 #define USART_PRESC_PRESCALER_3      (0x8UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000008 */
12778 
12779 /******************************************************************************/
12780 /*                                                                            */
12781 /*                                 VREFBUF                                    */
12782 /*                                                                            */
12783 /******************************************************************************/
12784 /*******************  Bit definition for VREFBUF_CSR register  ****************/
12785 #define VREFBUF_CSR_ENVR_Pos    (0U)
12786 #define VREFBUF_CSR_ENVR_Msk    (0x1UL << VREFBUF_CSR_ENVR_Pos)                /*!< 0x00000001 */
12787 #define VREFBUF_CSR_ENVR        VREFBUF_CSR_ENVR_Msk                           /*!<Voltage reference buffer enable */
12788 #define VREFBUF_CSR_HIZ_Pos     (1U)
12789 #define VREFBUF_CSR_HIZ_Msk     (0x1UL << VREFBUF_CSR_HIZ_Pos)                 /*!< 0x00000002 */
12790 #define VREFBUF_CSR_HIZ         VREFBUF_CSR_HIZ_Msk                            /*!<High impedance mode             */
12791 #define VREFBUF_CSR_VRR_Pos     (3U)
12792 #define VREFBUF_CSR_VRR_Msk     (0x1UL << VREFBUF_CSR_VRR_Pos)                 /*!< 0x00000008 */
12793 #define VREFBUF_CSR_VRR         VREFBUF_CSR_VRR_Msk                            /*!<Voltage reference buffer ready  */
12794 #define VREFBUF_CSR_VRS_Pos     (4U)
12795 #define VREFBUF_CSR_VRS_Msk     (0x3UL << VREFBUF_CSR_VRS_Pos)                 /*!< 0x00000030 */
12796 #define VREFBUF_CSR_VRS         VREFBUF_CSR_VRS_Msk                            /*!<VRS[5:0] bits (Voltage reference scale) */
12797 #define VREFBUF_CSR_VRS_0       (0x1UL << VREFBUF_CSR_VRS_Pos)                 /*!< 0x00000010 */
12798 #define VREFBUF_CSR_VRS_1       (0x2UL << VREFBUF_CSR_VRS_Pos)                 /*!< 0x00000020 */
12799 
12800 /*******************  Bit definition for VREFBUF_CCR register  ******************/
12801 #define VREFBUF_CCR_TRIM_Pos    (0U)
12802 #define VREFBUF_CCR_TRIM_Msk    (0x3FUL << VREFBUF_CCR_TRIM_Pos)               /*!< 0x0000003F */
12803 #define VREFBUF_CCR_TRIM        VREFBUF_CCR_TRIM_Msk                           /*!<TRIM[5:0] bits (Trimming code)  */
12804 
12805 /******************************************************************************/
12806 /*                                                                            */
12807 /*                         USB Device FS Endpoint registers                   */
12808 /*                                                                            */
12809 /******************************************************************************/
12810 #define USB_EP0R                             USB_BASE                    /*!< endpoint 0 register address */
12811 #define USB_EP1R                             (USB_BASE + 0x0x00000004)   /*!< endpoint 1 register address */
12812 #define USB_EP2R                             (USB_BASE + 0x0x00000008)   /*!< endpoint 2 register address */
12813 #define USB_EP3R                             (USB_BASE + 0x0x0000000C)   /*!< endpoint 3 register address */
12814 #define USB_EP4R                             (USB_BASE + 0x0x00000010)   /*!< endpoint 4 register address */
12815 #define USB_EP5R                             (USB_BASE + 0x0x00000014)   /*!< endpoint 5 register address */
12816 #define USB_EP6R                             (USB_BASE + 0x0x00000018)   /*!< endpoint 6 register address */
12817 #define USB_EP7R                             (USB_BASE + 0x0x0000001C)   /*!< endpoint 7 register address */
12818 
12819 /* bit positions */
12820 #define USB_EP_CTR_RX                            ((uint16_t)0x8000U)           /*!<  EndPoint Correct TRansfer RX */
12821 #define USB_EP_DTOG_RX                           ((uint16_t)0x4000U)           /*!<  EndPoint Data TOGGLE RX */
12822 #define USB_EPRX_STAT                            ((uint16_t)0x3000U)           /*!<  EndPoint RX STATus bit field */
12823 #define USB_EP_SETUP                             ((uint16_t)0x0800U)           /*!<  EndPoint SETUP */
12824 #define USB_EP_T_FIELD                           ((uint16_t)0x0600U)           /*!<  EndPoint TYPE */
12825 #define USB_EP_KIND                              ((uint16_t)0x0100U)           /*!<  EndPoint KIND */
12826 #define USB_EP_CTR_TX                            ((uint16_t)0x0080U)           /*!<  EndPoint Correct TRansfer TX */
12827 #define USB_EP_DTOG_TX                           ((uint16_t)0x0040U)           /*!<  EndPoint Data TOGGLE TX */
12828 #define USB_EPTX_STAT                            ((uint16_t)0x0030U)           /*!<  EndPoint TX STATus bit field */
12829 #define USB_EPADDR_FIELD                         ((uint16_t)0x000FU)           /*!<  EndPoint ADDRess FIELD */
12830 
12831 /* EndPoint REGister MASK (no toggle fields) */
12832 #define USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
12833                                                                          /*!< EP_TYPE[1:0] EndPoint TYPE */
12834 #define USB_EP_TYPE_MASK                         ((uint16_t)0x0600U)           /*!< EndPoint TYPE Mask */
12835 #define USB_EP_BULK                              ((uint16_t)0x0000U)           /*!< EndPoint BULK */
12836 #define USB_EP_CONTROL                           ((uint16_t)0x0200U)           /*!< EndPoint CONTROL */
12837 #define USB_EP_ISOCHRONOUS                       ((uint16_t)0x0400U)           /*!< EndPoint ISOCHRONOUS */
12838 #define USB_EP_INTERRUPT                         ((uint16_t)0x0600U)           /*!< EndPoint INTERRUPT */
12839 #define USB_EP_T_MASK                        ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
12840 
12841 #define USB_EPKIND_MASK                      ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
12842                                                                          /*!< STAT_TX[1:0] STATus for TX transfer */
12843 #define USB_EP_TX_DIS                            ((uint16_t)0x0000U)           /*!< EndPoint TX DISabled */
12844 #define USB_EP_TX_STALL                          ((uint16_t)0x0010U)           /*!< EndPoint TX STALLed */
12845 #define USB_EP_TX_NAK                            ((uint16_t)0x0020U)           /*!< EndPoint TX NAKed */
12846 #define USB_EP_TX_VALID                          ((uint16_t)0x0030U)           /*!< EndPoint TX VALID */
12847 #define USB_EPTX_DTOG1                           ((uint16_t)0x0010U)           /*!< EndPoint TX Data TOGgle bit1 */
12848 #define USB_EPTX_DTOG2                           ((uint16_t)0x0020U)           /*!< EndPoint TX Data TOGgle bit2 */
12849 #define USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
12850                                                                          /*!< STAT_RX[1:0] STATus for RX transfer */
12851 #define USB_EP_RX_DIS                            ((uint16_t)0x0000U)           /*!< EndPoint RX DISabled */
12852 #define USB_EP_RX_STALL                          ((uint16_t)0x1000U)           /*!< EndPoint RX STALLed */
12853 #define USB_EP_RX_NAK                            ((uint16_t)0x2000U)           /*!< EndPoint RX NAKed */
12854 #define USB_EP_RX_VALID                          ((uint16_t)0x3000U)           /*!< EndPoint RX VALID */
12855 #define USB_EPRX_DTOG1                           ((uint16_t)0x1000U)           /*!< EndPoint RX Data TOGgle bit1 */
12856 #define USB_EPRX_DTOG2                           ((uint16_t)0x2000U)           /*!< EndPoint RX Data TOGgle bit1 */
12857 #define USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
12858 
12859 /******************************************************************************/
12860 /*                                                                            */
12861 /*                         USB Device FS General registers                    */
12862 /*                                                                            */
12863 /******************************************************************************/
12864 #define USB_CNTR                             (USB_BASE + 0x00000040U)     /*!< Control register */
12865 #define USB_ISTR                             (USB_BASE + 0x00000044U)     /*!< Interrupt status register */
12866 #define USB_FNR                              (USB_BASE + 0x00000048U)     /*!< Frame number register */
12867 #define USB_DADDR                            (USB_BASE + 0x0000004CU)     /*!< Device address register */
12868 #define USB_BTABLE                           (USB_BASE + 0x00000050U)     /*!< Buffer Table address register */
12869 #define USB_LPMCSR                           (USB_BASE + 0x00000054U)     /*!< LPM Control and Status register */
12870 #define USB_BCDR                             (USB_BASE + 0x00000058U)     /*!< Battery Charging detector register*/
12871 
12872 /******************  Bits definition for USB_CNTR register  *******************/
12873 #define USB_CNTR_CTRM                            ((uint16_t)0x8000U)           /*!< Correct TRansfer Mask */
12874 #define USB_CNTR_PMAOVRM                         ((uint16_t)0x4000U)           /*!< DMA OVeR/underrun Mask */
12875 #define USB_CNTR_ERRM                            ((uint16_t)0x2000U)           /*!< ERRor Mask */
12876 #define USB_CNTR_WKUPM                           ((uint16_t)0x1000U)           /*!< WaKe UP Mask */
12877 #define USB_CNTR_SUSPM                           ((uint16_t)0x0800U)           /*!< SUSPend Mask */
12878 #define USB_CNTR_RESETM                          ((uint16_t)0x0400U)           /*!< RESET Mask   */
12879 #define USB_CNTR_SOFM                            ((uint16_t)0x0200U)           /*!< Start Of Frame Mask */
12880 #define USB_CNTR_ESOFM                           ((uint16_t)0x0100U)           /*!< Expected Start Of Frame Mask */
12881 #define USB_CNTR_L1REQM                          ((uint16_t)0x0080U)           /*!< LPM L1 state request interrupt mask */
12882 #define USB_CNTR_L1RESUME                        ((uint16_t)0x0020U)           /*!< LPM L1 Resume request */
12883 #define USB_CNTR_RESUME                          ((uint16_t)0x0010U)           /*!< RESUME request */
12884 #define USB_CNTR_FSUSP                           ((uint16_t)0x0008U)           /*!< Force SUSPend */
12885 #define USB_CNTR_LPMODE                          ((uint16_t)0x0004U)           /*!< Low-power MODE */
12886 #define USB_CNTR_PDWN                            ((uint16_t)0x0002U)           /*!< Power DoWN */
12887 #define USB_CNTR_FRES                            ((uint16_t)0x0001U)           /*!< Force USB RESet */
12888 
12889 /******************  Bits definition for USB_ISTR register  *******************/
12890 #define USB_ISTR_EP_ID                           ((uint16_t)0x000FU)           /*!< EndPoint IDentifier (read-only bit)  */
12891 #define USB_ISTR_DIR                             ((uint16_t)0x0010U)           /*!< DIRection of transaction (read-only bit)  */
12892 #define USB_ISTR_L1REQ                           ((uint16_t)0x0080U)           /*!< LPM L1 state request  */
12893 #define USB_ISTR_ESOF                            ((uint16_t)0x0100U)           /*!< Expected Start Of Frame (clear-only bit) */
12894 #define USB_ISTR_SOF                             ((uint16_t)0x0200U)           /*!< Start Of Frame (clear-only bit) */
12895 #define USB_ISTR_RESET                           ((uint16_t)0x0400U)           /*!< RESET (clear-only bit) */
12896 #define USB_ISTR_SUSP                            ((uint16_t)0x0800U)           /*!< SUSPend (clear-only bit) */
12897 #define USB_ISTR_WKUP                            ((uint16_t)0x1000U)           /*!< WaKe UP (clear-only bit) */
12898 #define USB_ISTR_ERR                             ((uint16_t)0x2000U)           /*!< ERRor (clear-only bit) */
12899 #define USB_ISTR_PMAOVR                          ((uint16_t)0x4000U)           /*!< DMA OVeR/underrun (clear-only bit) */
12900 #define USB_ISTR_CTR                             ((uint16_t)0x8000U)           /*!< Correct TRansfer (clear-only bit) */
12901 
12902 #define USB_CLR_L1REQ                        (~USB_ISTR_L1REQ)           /*!< clear LPM L1  bit */
12903 #define USB_CLR_ESOF                         (~USB_ISTR_ESOF)            /*!< clear Expected Start Of Frame bit */
12904 #define USB_CLR_SOF                          (~USB_ISTR_SOF)             /*!< clear Start Of Frame bit */
12905 #define USB_CLR_RESET                        (~USB_ISTR_RESET)           /*!< clear RESET bit */
12906 #define USB_CLR_SUSP                         (~USB_ISTR_SUSP)            /*!< clear SUSPend bit */
12907 #define USB_CLR_WKUP                         (~USB_ISTR_WKUP)            /*!< clear WaKe UP bit */
12908 #define USB_CLR_ERR                          (~USB_ISTR_ERR)             /*!< clear ERRor bit */
12909 #define USB_CLR_PMAOVR                       (~USB_ISTR_PMAOVR)          /*!< clear DMA OVeR/underrun bit*/
12910 #define USB_CLR_CTR                          (~USB_ISTR_CTR)             /*!< clear Correct TRansfer bit */
12911 
12912 /******************  Bits definition for USB_FNR register  ********************/
12913 #define USB_FNR_FN                               ((uint16_t)0x07FFU)           /*!< Frame Number */
12914 #define USB_FNR_LSOF                             ((uint16_t)0x1800U)           /*!< Lost SOF */
12915 #define USB_FNR_LCK                              ((uint16_t)0x2000U)           /*!< LoCKed */
12916 #define USB_FNR_RXDM                             ((uint16_t)0x4000U)           /*!< status of D- data line */
12917 #define USB_FNR_RXDP                             ((uint16_t)0x8000U)           /*!< status of D+ data line */
12918 
12919 /******************  Bits definition for USB_DADDR register    ****************/
12920 #define USB_DADDR_ADD                            ((uint8_t)0x7FU)              /*!< ADD[6:0] bits (Device Address) */
12921 #define USB_DADDR_ADD0                           ((uint8_t)0x01U)              /*!< Bit 0 */
12922 #define USB_DADDR_ADD1                           ((uint8_t)0x02U)              /*!< Bit 1 */
12923 #define USB_DADDR_ADD2                           ((uint8_t)0x04U)              /*!< Bit 2 */
12924 #define USB_DADDR_ADD3                           ((uint8_t)0x08U)              /*!< Bit 3 */
12925 #define USB_DADDR_ADD4                           ((uint8_t)0x10U)              /*!< Bit 4 */
12926 #define USB_DADDR_ADD5                           ((uint8_t)0x20U)              /*!< Bit 5 */
12927 #define USB_DADDR_ADD6                           ((uint8_t)0x40U)              /*!< Bit 6 */
12928 
12929 #define USB_DADDR_EF                             ((uint8_t)0x80U)              /*!< Enable Function */
12930 
12931 /******************  Bit definition for USB_BTABLE register  ******************/
12932 #define USB_BTABLE_BTABLE                        ((uint16_t)0xFFF8U)           /*!< Buffer Table */
12933 
12934 /******************  Bits definition for USB_BCDR register  *******************/
12935 #define USB_BCDR_BCDEN                           ((uint16_t)0x0001U)           /*!< Battery charging detector (BCD) enable */
12936 #define USB_BCDR_DCDEN                           ((uint16_t)0x0002U)           /*!< Data contact detection (DCD) mode enable */
12937 #define USB_BCDR_PDEN                            ((uint16_t)0x0004U)           /*!< Primary detection (PD) mode enable */
12938 #define USB_BCDR_SDEN                            ((uint16_t)0x0008U)           /*!< Secondary detection (SD) mode enable */
12939 #define USB_BCDR_DCDET                           ((uint16_t)0x0010U)           /*!< Data contact detection (DCD) status */
12940 #define USB_BCDR_PDET                            ((uint16_t)0x0020U)           /*!< Primary detection (PD) status */
12941 #define USB_BCDR_SDET                            ((uint16_t)0x0040U)           /*!< Secondary detection (SD) status */
12942 #define USB_BCDR_PS2DET                          ((uint16_t)0x0080U)           /*!< PS2 port or proprietary charger detected */
12943 #define USB_BCDR_DPPU                            ((uint16_t)0x8000U)           /*!< DP Pull-up Enable */
12944 
12945 /*******************  Bit definition for LPMCSR register  *********************/
12946 #define USB_LPMCSR_LMPEN                         ((uint16_t)0x0001U)           /*!< LPM support enable  */
12947 #define USB_LPMCSR_LPMACK                        ((uint16_t)0x0002U)           /*!< LPM Token acknowledge enable*/
12948 #define USB_LPMCSR_REMWAKE                       ((uint16_t)0x0008U)           /*!< bRemoteWake value received with last ACKed LPM Token */
12949 #define USB_LPMCSR_BESL                          ((uint16_t)0x00F0U)           /*!< BESL value received with last ACKed LPM Token  */
12950 
12951 /*!< Buffer descriptor table */
12952 /*****************  Bit definition for USB_ADDR0_TX register  *****************/
12953 #define USB_ADDR0_TX_ADDR0_TX_Pos                (1U)
12954 #define USB_ADDR0_TX_ADDR0_TX_Msk                (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos)/*!< 0x0000FFFE */
12955 #define USB_ADDR0_TX_ADDR0_TX                    USB_ADDR0_TX_ADDR0_TX_Msk     /*!< Transmission Buffer Address 0 */
12956 
12957 /*****************  Bit definition for USB_ADDR1_TX register  *****************/
12958 #define USB_ADDR1_TX_ADDR1_TX_Pos                (1U)
12959 #define USB_ADDR1_TX_ADDR1_TX_Msk                (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos)/*!< 0x0000FFFE */
12960 #define USB_ADDR1_TX_ADDR1_TX                    USB_ADDR1_TX_ADDR1_TX_Msk     /*!< Transmission Buffer Address 1 */
12961 
12962 /*****************  Bit definition for USB_ADDR2_TX register  *****************/
12963 #define USB_ADDR2_TX_ADDR2_TX_Pos                (1U)
12964 #define USB_ADDR2_TX_ADDR2_TX_Msk                (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos)/*!< 0x0000FFFE */
12965 #define USB_ADDR2_TX_ADDR2_TX                    USB_ADDR2_TX_ADDR2_TX_Msk     /*!< Transmission Buffer Address 2 */
12966 
12967 /*****************  Bit definition for USB_ADDR3_TX register  *****************/
12968 #define USB_ADDR3_TX_ADDR3_TX_Pos                (1U)
12969 #define USB_ADDR3_TX_ADDR3_TX_Msk                (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos)/*!< 0x0000FFFE */
12970 #define USB_ADDR3_TX_ADDR3_TX                    USB_ADDR3_TX_ADDR3_TX_Msk     /*!< Transmission Buffer Address 3 */
12971 
12972 /*****************  Bit definition for USB_ADDR4_TX register  *****************/
12973 #define USB_ADDR4_TX_ADDR4_TX_Pos                (1U)
12974 #define USB_ADDR4_TX_ADDR4_TX_Msk                (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos)/*!< 0x0000FFFE */
12975 #define USB_ADDR4_TX_ADDR4_TX                    USB_ADDR4_TX_ADDR4_TX_Msk     /*!< Transmission Buffer Address 4 */
12976 
12977 /*****************  Bit definition for USB_ADDR5_TX register  *****************/
12978 #define USB_ADDR5_TX_ADDR5_TX_Pos                (1U)
12979 #define USB_ADDR5_TX_ADDR5_TX_Msk                (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos)/*!< 0x0000FFFE */
12980 #define USB_ADDR5_TX_ADDR5_TX                    USB_ADDR5_TX_ADDR5_TX_Msk     /*!< Transmission Buffer Address 5 */
12981 
12982 /*****************  Bit definition for USB_ADDR6_TX register  *****************/
12983 #define USB_ADDR6_TX_ADDR6_TX_Pos                (1U)
12984 #define USB_ADDR6_TX_ADDR6_TX_Msk                (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos)/*!< 0x0000FFFE */
12985 #define USB_ADDR6_TX_ADDR6_TX                    USB_ADDR6_TX_ADDR6_TX_Msk     /*!< Transmission Buffer Address 6 */
12986 
12987 /*****************  Bit definition for USB_ADDR7_TX register  *****************/
12988 #define USB_ADDR7_TX_ADDR7_TX_Pos                (1U)
12989 #define USB_ADDR7_TX_ADDR7_TX_Msk                (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos)/*!< 0x0000FFFE */
12990 #define USB_ADDR7_TX_ADDR7_TX                    USB_ADDR7_TX_ADDR7_TX_Msk     /*!< Transmission Buffer Address 7 */
12991 
12992 /*----------------------------------------------------------------------------*/
12993 
12994 /*****************  Bit definition for USB_COUNT0_TX register  ****************/
12995 #define USB_COUNT0_TX_COUNT0_TX_Pos              (0U)
12996 #define USB_COUNT0_TX_COUNT0_TX_Msk              (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos)/*!< 0x000003FF */
12997 #define USB_COUNT0_TX_COUNT0_TX                  USB_COUNT0_TX_COUNT0_TX_Msk   /*!< Transmission Byte Count 0 */
12998 
12999 /*****************  Bit definition for USB_COUNT1_TX register  ****************/
13000 #define USB_COUNT1_TX_COUNT1_TX_Pos              (0U)
13001 #define USB_COUNT1_TX_COUNT1_TX_Msk              (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos)/*!< 0x000003FF */
13002 #define USB_COUNT1_TX_COUNT1_TX                  USB_COUNT1_TX_COUNT1_TX_Msk   /*!< Transmission Byte Count 1 */
13003 
13004 /*****************  Bit definition for USB_COUNT2_TX register  ****************/
13005 #define USB_COUNT2_TX_COUNT2_TX_Pos              (0U)
13006 #define USB_COUNT2_TX_COUNT2_TX_Msk              (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos)/*!< 0x000003FF */
13007 #define USB_COUNT2_TX_COUNT2_TX                  USB_COUNT2_TX_COUNT2_TX_Msk   /*!< Transmission Byte Count 2 */
13008 
13009 /*****************  Bit definition for USB_COUNT3_TX register  ****************/
13010 #define USB_COUNT3_TX_COUNT3_TX_Pos              (0U)
13011 #define USB_COUNT3_TX_COUNT3_TX_Msk              (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos)/*!< 0x000003FF */
13012 #define USB_COUNT3_TX_COUNT3_TX                  USB_COUNT3_TX_COUNT3_TX_Msk   /*!< Transmission Byte Count 3 */
13013 
13014 /*****************  Bit definition for USB_COUNT4_TX register  ****************/
13015 #define USB_COUNT4_TX_COUNT4_TX_Pos              (0U)
13016 #define USB_COUNT4_TX_COUNT4_TX_Msk              (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos)/*!< 0x000003FF */
13017 #define USB_COUNT4_TX_COUNT4_TX                  USB_COUNT4_TX_COUNT4_TX_Msk   /*!< Transmission Byte Count 4 */
13018 
13019 /*****************  Bit definition for USB_COUNT5_TX register  ****************/
13020 #define USB_COUNT5_TX_COUNT5_TX_Pos              (0U)
13021 #define USB_COUNT5_TX_COUNT5_TX_Msk              (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos)/*!< 0x000003FF */
13022 #define USB_COUNT5_TX_COUNT5_TX                  USB_COUNT5_TX_COUNT5_TX_Msk   /*!< Transmission Byte Count 5 */
13023 
13024 /*****************  Bit definition for USB_COUNT6_TX register  ****************/
13025 #define USB_COUNT6_TX_COUNT6_TX_Pos              (0U)
13026 #define USB_COUNT6_TX_COUNT6_TX_Msk              (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos)/*!< 0x000003FF */
13027 #define USB_COUNT6_TX_COUNT6_TX                  USB_COUNT6_TX_COUNT6_TX_Msk   /*!< Transmission Byte Count 6 */
13028 
13029 /*****************  Bit definition for USB_COUNT7_TX register  ****************/
13030 #define USB_COUNT7_TX_COUNT7_TX_Pos              (0U)
13031 #define USB_COUNT7_TX_COUNT7_TX_Msk              (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos)/*!< 0x000003FF */
13032 #define USB_COUNT7_TX_COUNT7_TX                  USB_COUNT7_TX_COUNT7_TX_Msk   /*!< Transmission Byte Count 7 */
13033 
13034 /*----------------------------------------------------------------------------*/
13035 
13036 /****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
13037 #define USB_COUNT0_TX_0_COUNT0_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 0 (low) */
13038 
13039 /****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
13040 #define USB_COUNT0_TX_1_COUNT0_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 0 (high) */
13041 
13042 /****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
13043 #define USB_COUNT1_TX_0_COUNT1_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 1 (low) */
13044 
13045 /****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
13046 #define USB_COUNT1_TX_1_COUNT1_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 1 (high) */
13047 
13048 /****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
13049 #define USB_COUNT2_TX_0_COUNT2_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 2 (low) */
13050 
13051 /****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
13052 #define USB_COUNT2_TX_1_COUNT2_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 2 (high) */
13053 
13054 /****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
13055 #define USB_COUNT3_TX_0_COUNT3_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 3 (low) */
13056 
13057 /****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
13058 #define USB_COUNT3_TX_1_COUNT3_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 3 (high) */
13059 
13060 /****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
13061 #define USB_COUNT4_TX_0_COUNT4_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 4 (low) */
13062 
13063 /****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
13064 #define USB_COUNT4_TX_1_COUNT4_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 4 (high) */
13065 
13066 /****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
13067 #define USB_COUNT5_TX_0_COUNT5_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 5 (low) */
13068 
13069 /****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
13070 #define USB_COUNT5_TX_1_COUNT5_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 5 (high) */
13071 
13072 /****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
13073 #define USB_COUNT6_TX_0_COUNT6_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 6 (low) */
13074 
13075 /****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
13076 #define USB_COUNT6_TX_1_COUNT6_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 6 (high) */
13077 
13078 /****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
13079 #define USB_COUNT7_TX_0_COUNT7_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 7 (low) */
13080 
13081 /****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
13082 #define USB_COUNT7_TX_1_COUNT7_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 7 (high) */
13083 
13084 /*----------------------------------------------------------------------------*/
13085 
13086 /*****************  Bit definition for USB_ADDR0_RX register  *****************/
13087 #define USB_ADDR0_RX_ADDR0_RX_Pos                (1U)
13088 #define USB_ADDR0_RX_ADDR0_RX_Msk                (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos)/*!< 0x0000FFFE */
13089 #define USB_ADDR0_RX_ADDR0_RX                    USB_ADDR0_RX_ADDR0_RX_Msk     /*!< Reception Buffer Address 0 */
13090 
13091 /*****************  Bit definition for USB_ADDR1_RX register  *****************/
13092 #define USB_ADDR1_RX_ADDR1_RX_Pos                (1U)
13093 #define USB_ADDR1_RX_ADDR1_RX_Msk                (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos)/*!< 0x0000FFFE */
13094 #define USB_ADDR1_RX_ADDR1_RX                    USB_ADDR1_RX_ADDR1_RX_Msk     /*!< Reception Buffer Address 1 */
13095 
13096 /*****************  Bit definition for USB_ADDR2_RX register  *****************/
13097 #define USB_ADDR2_RX_ADDR2_RX_Pos                (1U)
13098 #define USB_ADDR2_RX_ADDR2_RX_Msk                (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos)/*!< 0x0000FFFE */
13099 #define USB_ADDR2_RX_ADDR2_RX                    USB_ADDR2_RX_ADDR2_RX_Msk     /*!< Reception Buffer Address 2 */
13100 
13101 /*****************  Bit definition for USB_ADDR3_RX register  *****************/
13102 #define USB_ADDR3_RX_ADDR3_RX_Pos                (1U)
13103 #define USB_ADDR3_RX_ADDR3_RX_Msk                (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos)/*!< 0x0000FFFE */
13104 #define USB_ADDR3_RX_ADDR3_RX                    USB_ADDR3_RX_ADDR3_RX_Msk     /*!< Reception Buffer Address 3 */
13105 
13106 /*****************  Bit definition for USB_ADDR4_RX register  *****************/
13107 #define USB_ADDR4_RX_ADDR4_RX_Pos                (1U)
13108 #define USB_ADDR4_RX_ADDR4_RX_Msk                (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos)/*!< 0x0000FFFE */
13109 #define USB_ADDR4_RX_ADDR4_RX                    USB_ADDR4_RX_ADDR4_RX_Msk     /*!< Reception Buffer Address 4 */
13110 
13111 /*****************  Bit definition for USB_ADDR5_RX register  *****************/
13112 #define USB_ADDR5_RX_ADDR5_RX_Pos                (1U)
13113 #define USB_ADDR5_RX_ADDR5_RX_Msk                (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos)/*!< 0x0000FFFE */
13114 #define USB_ADDR5_RX_ADDR5_RX                    USB_ADDR5_RX_ADDR5_RX_Msk     /*!< Reception Buffer Address 5 */
13115 
13116 /*****************  Bit definition for USB_ADDR6_RX register  *****************/
13117 #define USB_ADDR6_RX_ADDR6_RX_Pos                (1U)
13118 #define USB_ADDR6_RX_ADDR6_RX_Msk                (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos)/*!< 0x0000FFFE */
13119 #define USB_ADDR6_RX_ADDR6_RX                    USB_ADDR6_RX_ADDR6_RX_Msk     /*!< Reception Buffer Address 6 */
13120 
13121 /*****************  Bit definition for USB_ADDR7_RX register  *****************/
13122 #define USB_ADDR7_RX_ADDR7_RX_Pos                (1U)
13123 #define USB_ADDR7_RX_ADDR7_RX_Msk                (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos)/*!< 0x0000FFFE */
13124 #define USB_ADDR7_RX_ADDR7_RX                    USB_ADDR7_RX_ADDR7_RX_Msk     /*!< Reception Buffer Address 7 */
13125 
13126 /*----------------------------------------------------------------------------*/
13127 
13128 /*****************  Bit definition for USB_COUNT0_RX register  ****************/
13129 #define USB_COUNT0_RX_COUNT0_RX_Pos              (0U)
13130 #define USB_COUNT0_RX_COUNT0_RX_Msk              (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos)/*!< 0x000003FF */
13131 #define USB_COUNT0_RX_COUNT0_RX                  USB_COUNT0_RX_COUNT0_RX_Msk   /*!< Reception Byte Count */
13132 
13133 #define USB_COUNT0_RX_NUM_BLOCK_Pos              (10U)
13134 #define USB_COUNT0_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
13135 #define USB_COUNT0_RX_NUM_BLOCK                  USB_COUNT0_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
13136 #define USB_COUNT0_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
13137 #define USB_COUNT0_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
13138 #define USB_COUNT0_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
13139 #define USB_COUNT0_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
13140 #define USB_COUNT0_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
13141 
13142 #define USB_COUNT0_RX_BLSIZE_Pos                 (15U)
13143 #define USB_COUNT0_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT0_RX_BLSIZE_Pos)/*!< 0x00008000 */
13144 #define USB_COUNT0_RX_BLSIZE                     USB_COUNT0_RX_BLSIZE_Msk      /*!< BLock SIZE */
13145 
13146 /*****************  Bit definition for USB_COUNT1_RX register  ****************/
13147 #define USB_COUNT1_RX_COUNT1_RX_Pos              (0U)
13148 #define USB_COUNT1_RX_COUNT1_RX_Msk              (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos)/*!< 0x000003FF */
13149 #define USB_COUNT1_RX_COUNT1_RX                  USB_COUNT1_RX_COUNT1_RX_Msk   /*!< Reception Byte Count */
13150 
13151 #define USB_COUNT1_RX_NUM_BLOCK_Pos              (10U)
13152 #define USB_COUNT1_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
13153 #define USB_COUNT1_RX_NUM_BLOCK                  USB_COUNT1_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
13154 #define USB_COUNT1_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
13155 #define USB_COUNT1_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
13156 #define USB_COUNT1_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
13157 #define USB_COUNT1_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
13158 #define USB_COUNT1_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
13159 
13160 #define USB_COUNT1_RX_BLSIZE_Pos                 (15U)
13161 #define USB_COUNT1_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT1_RX_BLSIZE_Pos)/*!< 0x00008000 */
13162 #define USB_COUNT1_RX_BLSIZE                     USB_COUNT1_RX_BLSIZE_Msk      /*!< BLock SIZE */
13163 
13164 /*****************  Bit definition for USB_COUNT2_RX register  ****************/
13165 #define USB_COUNT2_RX_COUNT2_RX_Pos              (0U)
13166 #define USB_COUNT2_RX_COUNT2_RX_Msk              (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos)/*!< 0x000003FF */
13167 #define USB_COUNT2_RX_COUNT2_RX                  USB_COUNT2_RX_COUNT2_RX_Msk   /*!< Reception Byte Count */
13168 
13169 #define USB_COUNT2_RX_NUM_BLOCK_Pos              (10U)
13170 #define USB_COUNT2_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
13171 #define USB_COUNT2_RX_NUM_BLOCK                  USB_COUNT2_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
13172 #define USB_COUNT2_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
13173 #define USB_COUNT2_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
13174 #define USB_COUNT2_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
13175 #define USB_COUNT2_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
13176 #define USB_COUNT2_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
13177 
13178 #define USB_COUNT2_RX_BLSIZE_Pos                 (15U)
13179 #define USB_COUNT2_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT2_RX_BLSIZE_Pos)/*!< 0x00008000 */
13180 #define USB_COUNT2_RX_BLSIZE                     USB_COUNT2_RX_BLSIZE_Msk      /*!< BLock SIZE */
13181 
13182 /*****************  Bit definition for USB_COUNT3_RX register  ****************/
13183 #define USB_COUNT3_RX_COUNT3_RX_Pos              (0U)
13184 #define USB_COUNT3_RX_COUNT3_RX_Msk              (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos)/*!< 0x000003FF */
13185 #define USB_COUNT3_RX_COUNT3_RX                  USB_COUNT3_RX_COUNT3_RX_Msk   /*!< Reception Byte Count */
13186 
13187 #define USB_COUNT3_RX_NUM_BLOCK_Pos              (10U)
13188 #define USB_COUNT3_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
13189 #define USB_COUNT3_RX_NUM_BLOCK                  USB_COUNT3_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
13190 #define USB_COUNT3_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
13191 #define USB_COUNT3_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
13192 #define USB_COUNT3_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
13193 #define USB_COUNT3_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
13194 #define USB_COUNT3_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
13195 
13196 #define USB_COUNT3_RX_BLSIZE_Pos                 (15U)
13197 #define USB_COUNT3_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT3_RX_BLSIZE_Pos)/*!< 0x00008000 */
13198 #define USB_COUNT3_RX_BLSIZE                     USB_COUNT3_RX_BLSIZE_Msk      /*!< BLock SIZE */
13199 
13200 /*****************  Bit definition for USB_COUNT4_RX register  ****************/
13201 #define USB_COUNT4_RX_COUNT4_RX_Pos              (0U)
13202 #define USB_COUNT4_RX_COUNT4_RX_Msk              (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos)/*!< 0x000003FF */
13203 #define USB_COUNT4_RX_COUNT4_RX                  USB_COUNT4_RX_COUNT4_RX_Msk   /*!< Reception Byte Count */
13204 
13205 #define USB_COUNT4_RX_NUM_BLOCK_Pos              (10U)
13206 #define USB_COUNT4_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
13207 #define USB_COUNT4_RX_NUM_BLOCK                  USB_COUNT4_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
13208 #define USB_COUNT4_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
13209 #define USB_COUNT4_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
13210 #define USB_COUNT4_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
13211 #define USB_COUNT4_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
13212 #define USB_COUNT4_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
13213 
13214 #define USB_COUNT4_RX_BLSIZE_Pos                 (15U)
13215 #define USB_COUNT4_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT4_RX_BLSIZE_Pos)/*!< 0x00008000 */
13216 #define USB_COUNT4_RX_BLSIZE                     USB_COUNT4_RX_BLSIZE_Msk      /*!< BLock SIZE */
13217 
13218 /*****************  Bit definition for USB_COUNT5_RX register  ****************/
13219 #define USB_COUNT5_RX_COUNT5_RX_Pos              (0U)
13220 #define USB_COUNT5_RX_COUNT5_RX_Msk              (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos)/*!< 0x000003FF */
13221 #define USB_COUNT5_RX_COUNT5_RX                  USB_COUNT5_RX_COUNT5_RX_Msk   /*!< Reception Byte Count */
13222 
13223 #define USB_COUNT5_RX_NUM_BLOCK_Pos              (10U)
13224 #define USB_COUNT5_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
13225 #define USB_COUNT5_RX_NUM_BLOCK                  USB_COUNT5_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
13226 #define USB_COUNT5_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
13227 #define USB_COUNT5_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
13228 #define USB_COUNT5_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
13229 #define USB_COUNT5_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
13230 #define USB_COUNT5_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
13231 
13232 #define USB_COUNT5_RX_BLSIZE_Pos                 (15U)
13233 #define USB_COUNT5_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT5_RX_BLSIZE_Pos)/*!< 0x00008000 */
13234 #define USB_COUNT5_RX_BLSIZE                     USB_COUNT5_RX_BLSIZE_Msk      /*!< BLock SIZE */
13235 
13236 /*****************  Bit definition for USB_COUNT6_RX register  ****************/
13237 #define USB_COUNT6_RX_COUNT6_RX_Pos              (0U)
13238 #define USB_COUNT6_RX_COUNT6_RX_Msk              (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos)/*!< 0x000003FF */
13239 #define USB_COUNT6_RX_COUNT6_RX                  USB_COUNT6_RX_COUNT6_RX_Msk   /*!< Reception Byte Count */
13240 
13241 #define USB_COUNT6_RX_NUM_BLOCK_Pos              (10U)
13242 #define USB_COUNT6_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
13243 #define USB_COUNT6_RX_NUM_BLOCK                  USB_COUNT6_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
13244 #define USB_COUNT6_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
13245 #define USB_COUNT6_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
13246 #define USB_COUNT6_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
13247 #define USB_COUNT6_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
13248 #define USB_COUNT6_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
13249 
13250 #define USB_COUNT6_RX_BLSIZE_Pos                 (15U)
13251 #define USB_COUNT6_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT6_RX_BLSIZE_Pos)/*!< 0x00008000 */
13252 #define USB_COUNT6_RX_BLSIZE                     USB_COUNT6_RX_BLSIZE_Msk      /*!< BLock SIZE */
13253 
13254 /*****************  Bit definition for USB_COUNT7_RX register  ****************/
13255 #define USB_COUNT7_RX_COUNT7_RX_Pos              (0U)
13256 #define USB_COUNT7_RX_COUNT7_RX_Msk              (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos)/*!< 0x000003FF */
13257 #define USB_COUNT7_RX_COUNT7_RX                  USB_COUNT7_RX_COUNT7_RX_Msk   /*!< Reception Byte Count */
13258 
13259 #define USB_COUNT7_RX_NUM_BLOCK_Pos              (10U)
13260 #define USB_COUNT7_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
13261 #define USB_COUNT7_RX_NUM_BLOCK                  USB_COUNT7_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
13262 #define USB_COUNT7_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
13263 #define USB_COUNT7_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
13264 #define USB_COUNT7_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
13265 #define USB_COUNT7_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
13266 #define USB_COUNT7_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
13267 
13268 #define USB_COUNT7_RX_BLSIZE_Pos                 (15U)
13269 #define USB_COUNT7_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT7_RX_BLSIZE_Pos)/*!< 0x00008000 */
13270 #define USB_COUNT7_RX_BLSIZE                     USB_COUNT7_RX_BLSIZE_Msk      /*!< BLock SIZE */
13271 
13272 /*----------------------------------------------------------------------------*/
13273 
13274 /****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
13275 #define USB_COUNT0_RX_0_COUNT0_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
13276 
13277 #define USB_COUNT0_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
13278 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
13279 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
13280 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
13281 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
13282 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
13283 
13284 #define USB_COUNT0_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
13285 
13286 /****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
13287 #define USB_COUNT0_RX_1_COUNT0_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
13288 
13289 #define USB_COUNT0_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
13290 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 1 */
13291 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
13292 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
13293 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
13294 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
13295 
13296 #define USB_COUNT0_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
13297 
13298 /****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
13299 #define USB_COUNT1_RX_0_COUNT1_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
13300 
13301 #define USB_COUNT1_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
13302 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
13303 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
13304 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
13305 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
13306 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
13307 
13308 #define USB_COUNT1_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
13309 
13310 /****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
13311 #define USB_COUNT1_RX_1_COUNT1_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
13312 
13313 #define USB_COUNT1_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
13314 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
13315 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
13316 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
13317 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
13318 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
13319 
13320 #define USB_COUNT1_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
13321 
13322 /****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
13323 #define USB_COUNT2_RX_0_COUNT2_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
13324 
13325 #define USB_COUNT2_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
13326 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
13327 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
13328 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
13329 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
13330 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
13331 
13332 #define USB_COUNT2_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
13333 
13334 /****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
13335 #define USB_COUNT2_RX_1_COUNT2_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
13336 
13337 #define USB_COUNT2_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
13338 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
13339 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
13340 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
13341 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
13342 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
13343 
13344 #define USB_COUNT2_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
13345 
13346 /****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
13347 #define USB_COUNT3_RX_0_COUNT3_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
13348 
13349 #define USB_COUNT3_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
13350 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
13351 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
13352 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
13353 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
13354 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
13355 
13356 #define USB_COUNT3_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
13357 
13358 /****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
13359 #define USB_COUNT3_RX_1_COUNT3_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
13360 
13361 #define USB_COUNT3_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
13362 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
13363 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
13364 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
13365 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
13366 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
13367 
13368 #define USB_COUNT3_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
13369 
13370 /****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
13371 #define USB_COUNT4_RX_0_COUNT4_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
13372 
13373 #define USB_COUNT4_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
13374 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
13375 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
13376 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
13377 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
13378 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
13379 
13380 #define USB_COUNT4_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
13381 
13382 /****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
13383 #define USB_COUNT4_RX_1_COUNT4_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
13384 
13385 #define USB_COUNT4_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
13386 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
13387 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
13388 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
13389 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
13390 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
13391 
13392 #define USB_COUNT4_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
13393 
13394 /****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
13395 #define USB_COUNT5_RX_0_COUNT5_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
13396 
13397 #define USB_COUNT5_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
13398 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
13399 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
13400 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
13401 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
13402 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
13403 
13404 #define USB_COUNT5_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
13405 
13406 /****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
13407 #define USB_COUNT5_RX_1_COUNT5_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
13408 
13409 #define USB_COUNT5_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
13410 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
13411 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
13412 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
13413 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
13414 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
13415 
13416 #define USB_COUNT5_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
13417 
13418 /***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
13419 #define USB_COUNT6_RX_0_COUNT6_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
13420 
13421 #define USB_COUNT6_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
13422 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
13423 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
13424 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
13425 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
13426 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
13427 
13428 #define USB_COUNT6_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
13429 
13430 /****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
13431 #define USB_COUNT6_RX_1_COUNT6_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
13432 
13433 #define USB_COUNT6_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
13434 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
13435 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
13436 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
13437 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
13438 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
13439 
13440 #define USB_COUNT6_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
13441 
13442 /***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
13443 #define USB_COUNT7_RX_0_COUNT7_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
13444 
13445 #define USB_COUNT7_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
13446 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
13447 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
13448 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
13449 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
13450 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
13451 
13452 #define USB_COUNT7_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
13453 
13454 /***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
13455 #define USB_COUNT7_RX_1_COUNT7_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
13456 
13457 #define USB_COUNT7_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
13458 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
13459 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
13460 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
13461 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
13462 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
13463 
13464 #define USB_COUNT7_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
13465 
13466 /******************************************************************************/
13467 /*                                                                            */
13468 /*                                    UCPD                                    */
13469 /*                                                                            */
13470 /******************************************************************************/
13471 /********************  Bits definition for UCPD_CFG1 register  *******************/
13472 #define UCPD_CFG1_HBITCLKDIV_Pos            (0U)
13473 #define UCPD_CFG1_HBITCLKDIV_Msk            (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x0000003F */
13474 #define UCPD_CFG1_HBITCLKDIV                UCPD_CFG1_HBITCLKDIV_Msk             /*!< Number of cycles (minus 1) for a half bit clock */
13475 #define UCPD_CFG1_HBITCLKDIV_0              (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000001 */
13476 #define UCPD_CFG1_HBITCLKDIV_1              (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000002 */
13477 #define UCPD_CFG1_HBITCLKDIV_2              (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000004 */
13478 #define UCPD_CFG1_HBITCLKDIV_3              (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000008 */
13479 #define UCPD_CFG1_HBITCLKDIV_4              (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000010 */
13480 #define UCPD_CFG1_HBITCLKDIV_5              (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000020 */
13481 #define UCPD_CFG1_IFRGAP_Pos                (6U)
13482 #define UCPD_CFG1_IFRGAP_Msk                (0x1FUL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x000007C0 */
13483 #define UCPD_CFG1_IFRGAP                    UCPD_CFG1_IFRGAP_Msk                 /*!< Clock divider value to generates Interframe gap */
13484 #define UCPD_CFG1_IFRGAP_0                  (0x01UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000040 */
13485 #define UCPD_CFG1_IFRGAP_1                  (0x02UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000080 */
13486 #define UCPD_CFG1_IFRGAP_2                  (0x04UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000100 */
13487 #define UCPD_CFG1_IFRGAP_3                  (0x08UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000200 */
13488 #define UCPD_CFG1_IFRGAP_4                  (0x10UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000400 */
13489 #define UCPD_CFG1_TRANSWIN_Pos              (11U)
13490 #define UCPD_CFG1_TRANSWIN_Msk              (0x1FUL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x0000F800 */
13491 #define UCPD_CFG1_TRANSWIN                  UCPD_CFG1_TRANSWIN_Msk               /*!< Number of cycles (minus 1) of the half bit clock */
13492 #define UCPD_CFG1_TRANSWIN_0                (0x01UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00000800 */
13493 #define UCPD_CFG1_TRANSWIN_1                (0x02UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00001000 */
13494 #define UCPD_CFG1_TRANSWIN_2                (0x04UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00002000 */
13495 #define UCPD_CFG1_TRANSWIN_3                (0x08UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00004000 */
13496 #define UCPD_CFG1_TRANSWIN_4                (0x10UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00008000 */
13497 #define UCPD_CFG1_PSC_UCPDCLK_Pos           (17U)
13498 #define UCPD_CFG1_PSC_UCPDCLK_Msk           (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x000E0000 */
13499 #define UCPD_CFG1_PSC_UCPDCLK               UCPD_CFG1_PSC_UCPDCLK_Msk            /*!< Prescaler for UCPDCLK */
13500 #define UCPD_CFG1_PSC_UCPDCLK_0             (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00020000 */
13501 #define UCPD_CFG1_PSC_UCPDCLK_1             (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00040000 */
13502 #define UCPD_CFG1_PSC_UCPDCLK_2             (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00080000 */
13503 #define UCPD_CFG1_RXORDSETEN_Pos            (20U)
13504 #define UCPD_CFG1_RXORDSETEN_Msk            (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x1FF00000 */
13505 #define UCPD_CFG1_RXORDSETEN                UCPD_CFG1_RXORDSETEN_Msk             /*!< Receiver ordered set detection enable */
13506 #define UCPD_CFG1_RXORDSETEN_0              (0x001UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00100000 */
13507 #define UCPD_CFG1_RXORDSETEN_1              (0x002UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00200000 */
13508 #define UCPD_CFG1_RXORDSETEN_2              (0x004UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00400000 */
13509 #define UCPD_CFG1_RXORDSETEN_3              (0x008UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00800000 */
13510 #define UCPD_CFG1_RXORDSETEN_4              (0x010UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x01000000 */
13511 #define UCPD_CFG1_RXORDSETEN_5              (0x020UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x02000000 */
13512 #define UCPD_CFG1_RXORDSETEN_6              (0x040UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x04000000 */
13513 #define UCPD_CFG1_RXORDSETEN_7              (0x080UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x08000000 */
13514 #define UCPD_CFG1_RXORDSETEN_8              (0x100UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x10000000 */
13515 #define UCPD_CFG1_TXDMAEN_Pos               (29U)
13516 #define UCPD_CFG1_TXDMAEN_Msk               (0x1UL << UCPD_CFG1_TXDMAEN_Pos)     /*!< 0x20000000 */
13517 #define UCPD_CFG1_TXDMAEN                   UCPD_CFG1_TXDMAEN_Msk                /*!< DMA transmission requests enable   */
13518 #define UCPD_CFG1_RXDMAEN_Pos               (30U)
13519 #define UCPD_CFG1_RXDMAEN_Msk               (0x1UL << UCPD_CFG1_RXDMAEN_Pos)     /*!< 0x40000000 */
13520 #define UCPD_CFG1_RXDMAEN                   UCPD_CFG1_RXDMAEN_Msk                /*!< DMA reception requests enable   */
13521 #define UCPD_CFG1_UCPDEN_Pos                (31U)
13522 #define UCPD_CFG1_UCPDEN_Msk                (0x1UL << UCPD_CFG1_UCPDEN_Pos)      /*!< 0x80000000 */
13523 #define UCPD_CFG1_UCPDEN                    UCPD_CFG1_UCPDEN_Msk                 /*!< USB Power Delivery Block Enable */
13524 
13525 /********************  Bits definition for UCPD_CFG2 register  *******************/
13526 #define UCPD_CFG2_RXFILTDIS_Pos             (0U)
13527 #define UCPD_CFG2_RXFILTDIS_Msk             (0x1UL << UCPD_CFG2_RXFILTDIS_Pos)   /*!< 0x00000001 */
13528 #define UCPD_CFG2_RXFILTDIS                 UCPD_CFG2_RXFILTDIS_Msk              /*!< Enables an Rx pre-filter for the BMC decoder */
13529 #define UCPD_CFG2_RXFILT2N3_Pos             (1U)
13530 #define UCPD_CFG2_RXFILT2N3_Msk             (0x1UL << UCPD_CFG2_RXFILT2N3_Pos)   /*!< 0x00000002 */
13531 #define UCPD_CFG2_RXFILT2N3                 UCPD_CFG2_RXFILT2N3_Msk              /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */
13532 #define UCPD_CFG2_FORCECLK_Pos              (2U)
13533 #define UCPD_CFG2_FORCECLK_Msk              (0x1UL << UCPD_CFG2_FORCECLK_Pos)    /*!< 0x00000004 */
13534 #define UCPD_CFG2_FORCECLK                  UCPD_CFG2_FORCECLK_Msk               /*!< Controls forcing of the clock request UCPDCLK_REQ */
13535 #define UCPD_CFG2_WUPEN_Pos                 (3U)
13536 #define UCPD_CFG2_WUPEN_Msk                 (0x1UL << UCPD_CFG2_WUPEN_Pos)       /*!< 0x00000008 */
13537 #define UCPD_CFG2_WUPEN                     UCPD_CFG2_WUPEN_Msk                  /*!< Wakeup from STOP enable */
13538 
13539 /********************  Bits definition for UCPD_CR register  ********************/
13540 #define UCPD_CR_TXMODE_Pos                  (0U)
13541 #define UCPD_CR_TXMODE_Msk                  (0x3UL << UCPD_CR_TXMODE_Pos)        /*!< 0x00000003 */
13542 #define UCPD_CR_TXMODE                      UCPD_CR_TXMODE_Msk                   /*!< Type of Tx packet  */
13543 #define UCPD_CR_TXMODE_0                    (0x1UL << UCPD_CR_TXMODE_Pos)        /*!< 0x00000001 */
13544 #define UCPD_CR_TXMODE_1                    (0x2UL << UCPD_CR_TXMODE_Pos)        /*!< 0x00000002 */
13545 #define UCPD_CR_TXSEND_Pos                  (2U)
13546 #define UCPD_CR_TXSEND_Msk                  (0x1UL << UCPD_CR_TXSEND_Pos)        /*!< 0x00000004 */
13547 #define UCPD_CR_TXSEND                      UCPD_CR_TXSEND_Msk                   /*!< Type of Tx packet  */
13548 #define UCPD_CR_TXHRST_Pos                  (3U)
13549 #define UCPD_CR_TXHRST_Msk                  (0x1UL << UCPD_CR_TXHRST_Pos)        /*!< 0x00000008 */
13550 #define UCPD_CR_TXHRST                      UCPD_CR_TXHRST_Msk                   /*!< Command to send a Tx Hard Reset  */
13551 #define UCPD_CR_RXMODE_Pos                  (4U)
13552 #define UCPD_CR_RXMODE_Msk                  (0x1UL << UCPD_CR_RXMODE_Pos)        /*!< 0x00000010 */
13553 #define UCPD_CR_RXMODE                      UCPD_CR_RXMODE_Msk                   /*!< Receiver mode  */
13554 #define UCPD_CR_PHYRXEN_Pos                 (5U)
13555 #define UCPD_CR_PHYRXEN_Msk                 (0x1UL << UCPD_CR_PHYRXEN_Pos)       /*!< 0x00000020 */
13556 #define UCPD_CR_PHYRXEN                     UCPD_CR_PHYRXEN_Msk                  /*!< Controls enable of USB Power Delivery receiver  */
13557 #define UCPD_CR_PHYCCSEL_Pos                (6U)
13558 #define UCPD_CR_PHYCCSEL_Msk                (0x1UL << UCPD_CR_PHYCCSEL_Pos)      /*!< 0x00000040 */
13559 #define UCPD_CR_PHYCCSEL                    UCPD_CR_PHYCCSEL_Msk                 /*!<  */
13560 #define UCPD_CR_ANASUBMODE_Pos              (7U)
13561 #define UCPD_CR_ANASUBMODE_Msk              (0x3UL << UCPD_CR_ANASUBMODE_Pos)    /*!< 0x00000180 */
13562 #define UCPD_CR_ANASUBMODE                  UCPD_CR_ANASUBMODE_Msk               /*!< Analog PHY sub-mode   */
13563 #define UCPD_CR_ANASUBMODE_0                (0x1UL << UCPD_CR_ANASUBMODE_Pos)    /*!< 0x00000080 */
13564 #define UCPD_CR_ANASUBMODE_1                (0x2UL << UCPD_CR_ANASUBMODE_Pos)    /*!< 0x00000100 */
13565 #define UCPD_CR_ANAMODE_Pos                 (9U)
13566 #define UCPD_CR_ANAMODE_Msk                 (0x1UL << UCPD_CR_ANAMODE_Pos)       /*!< 0x00000200 */
13567 #define UCPD_CR_ANAMODE                     UCPD_CR_ANAMODE_Msk                  /*!< Analog PHY working mode   */
13568 #define UCPD_CR_CCENABLE_Pos                (10U)
13569 #define UCPD_CR_CCENABLE_Msk                (0x3UL << UCPD_CR_CCENABLE_Pos)      /*!< 0x00000C00 */
13570 #define UCPD_CR_CCENABLE                    UCPD_CR_CCENABLE_Msk                 /*!<  */
13571 #define UCPD_CR_CCENABLE_0                  (0x1UL << UCPD_CR_CCENABLE_Pos)      /*!< 0x00000400 */
13572 #define UCPD_CR_CCENABLE_1                  (0x2UL << UCPD_CR_CCENABLE_Pos)      /*!< 0x00000800 */
13573 #define UCPD_CR_FRSRXEN_Pos                 (16U)
13574 #define UCPD_CR_FRSRXEN_Msk                 (0x1UL << UCPD_CR_FRSRXEN_Pos)       /*!< 0x00010000 */
13575 #define UCPD_CR_FRSRXEN                     UCPD_CR_FRSRXEN_Msk                  /*!< Enable FRS request detection function */
13576 #define UCPD_CR_FRSTX_Pos                   (17U)
13577 #define UCPD_CR_FRSTX_Msk                   (0x1UL << UCPD_CR_FRSTX_Pos)         /*!< 0x00020000 */
13578 #define UCPD_CR_FRSTX                       UCPD_CR_FRSTX_Msk                    /*!< Signal Fast Role Swap request */
13579 #define UCPD_CR_RDCH_Pos                    (18U)
13580 #define UCPD_CR_RDCH_Msk                    (0x1UL << UCPD_CR_RDCH_Pos)          /*!< 0x00040000 */
13581 #define UCPD_CR_RDCH                        UCPD_CR_RDCH_Msk                     /*!<  */
13582 #define UCPD_CR_CC1TCDIS_Pos                (20U)
13583 #define UCPD_CR_CC1TCDIS_Msk                (0x1UL << UCPD_CR_CC1TCDIS_Pos)      /*!< 0x00100000 */
13584 #define UCPD_CR_CC1TCDIS                    UCPD_CR_CC1TCDIS_Msk                 /*!< The bit allows the Type-C detector for CC0 to be disabled. */
13585 #define UCPD_CR_CC2TCDIS_Pos                (21U)
13586 #define UCPD_CR_CC2TCDIS_Msk                (0x1UL << UCPD_CR_CC2TCDIS_Pos)      /*!< 0x00200000 */
13587 #define UCPD_CR_CC2TCDIS                    UCPD_CR_CC2TCDIS_Msk                 /*!< The bit allows the Type-C detector for CC2 to be disabled. */
13588 
13589 /********************  Bits definition for UCPD_IMR register  *******************/
13590 #define UCPD_IMR_TXISIE_Pos                 (0U)
13591 #define UCPD_IMR_TXISIE_Msk                 (0x1UL << UCPD_IMR_TXISIE_Pos)       /*!< 0x00000001 */
13592 #define UCPD_IMR_TXISIE                     UCPD_IMR_TXISIE_Msk                  /*!< Enable TXIS interrupt  */
13593 #define UCPD_IMR_TXMSGDISCIE_Pos            (1U)
13594 #define UCPD_IMR_TXMSGDISCIE_Msk            (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos)  /*!< 0x00000002 */
13595 #define UCPD_IMR_TXMSGDISCIE                UCPD_IMR_TXMSGDISCIE_Msk             /*!< Enable TXMSGDISC interrupt  */
13596 #define UCPD_IMR_TXMSGSENTIE_Pos            (2U)
13597 #define UCPD_IMR_TXMSGSENTIE_Msk            (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos)  /*!< 0x00000004 */
13598 #define UCPD_IMR_TXMSGSENTIE                UCPD_IMR_TXMSGSENTIE_Msk             /*!< Enable TXMSGSENT interrupt  */
13599 #define UCPD_IMR_TXMSGABTIE_Pos             (3U)
13600 #define UCPD_IMR_TXMSGABTIE_Msk             (0x1UL << UCPD_IMR_TXMSGABTIE_Pos)   /*!< 0x00000008 */
13601 #define UCPD_IMR_TXMSGABTIE                 UCPD_IMR_TXMSGABTIE_Msk              /*!< Enable TXMSGABT interrupt  */
13602 #define UCPD_IMR_HRSTDISCIE_Pos             (4U)
13603 #define UCPD_IMR_HRSTDISCIE_Msk             (0x1UL << UCPD_IMR_HRSTDISCIE_Pos)   /*!< 0x00000010 */
13604 #define UCPD_IMR_HRSTDISCIE                 UCPD_IMR_HRSTDISCIE_Msk              /*!< Enable HRSTDISC interrupt  */
13605 #define UCPD_IMR_HRSTSENTIE_Pos             (5U)
13606 #define UCPD_IMR_HRSTSENTIE_Msk             (0x1UL << UCPD_IMR_HRSTSENTIE_Pos)   /*!< 0x00000020 */
13607 #define UCPD_IMR_HRSTSENTIE                 UCPD_IMR_HRSTSENTIE_Msk              /*!< Enable HRSTSENT interrupt  */
13608 #define UCPD_IMR_TXUNDIE_Pos                (6U)
13609 #define UCPD_IMR_TXUNDIE_Msk                (0x1UL << UCPD_IMR_TXUNDIE_Pos)      /*!< 0x00000040 */
13610 #define UCPD_IMR_TXUNDIE                    UCPD_IMR_TXUNDIE_Msk                 /*!< Enable TXUND interrupt  */
13611 #define UCPD_IMR_RXNEIE_Pos                 (8U)
13612 #define UCPD_IMR_RXNEIE_Msk                 (0x1UL << UCPD_IMR_RXNEIE_Pos)       /*!< 0x00000100 */
13613 #define UCPD_IMR_RXNEIE                     UCPD_IMR_RXNEIE_Msk                  /*!< Enable RXNE interrupt  */
13614 #define UCPD_IMR_RXORDDETIE_Pos             (9U)
13615 #define UCPD_IMR_RXORDDETIE_Msk             (0x1UL << UCPD_IMR_RXORDDETIE_Pos)   /*!< 0x00000200 */
13616 #define UCPD_IMR_RXORDDETIE                 UCPD_IMR_RXORDDETIE_Msk              /*!< Enable RXORDDET interrupt  */
13617 #define UCPD_IMR_RXHRSTDETIE_Pos            (10U)
13618 #define UCPD_IMR_RXHRSTDETIE_Msk            (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos)  /*!< 0x00000400 */
13619 #define UCPD_IMR_RXHRSTDETIE                UCPD_IMR_RXHRSTDETIE_Msk             /*!< Enable RXHRSTDET interrupt  */
13620 #define UCPD_IMR_RXOVRIE_Pos                (11U)
13621 #define UCPD_IMR_RXOVRIE_Msk                (0x1UL << UCPD_IMR_RXOVRIE_Pos)      /*!< 0x00000800 */
13622 #define UCPD_IMR_RXOVRIE                    UCPD_IMR_RXOVRIE_Msk                 /*!< Enable RXOVR interrupt  */
13623 #define UCPD_IMR_RXMSGENDIE_Pos             (12U)
13624 #define UCPD_IMR_RXMSGENDIE_Msk             (0x1UL << UCPD_IMR_RXMSGENDIE_Pos)   /*!< 0x00001000 */
13625 #define UCPD_IMR_RXMSGENDIE                 UCPD_IMR_RXMSGENDIE_Msk              /*!< Enable RXMSGEND interrupt  */
13626 #define UCPD_IMR_TYPECEVT1IE_Pos            (14U)
13627 #define UCPD_IMR_TYPECEVT1IE_Msk            (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos)  /*!< 0x00004000 */
13628 #define UCPD_IMR_TYPECEVT1IE                UCPD_IMR_TYPECEVT1IE_Msk             /*!< Enable TYPECEVT1IE interrupt  */
13629 #define UCPD_IMR_TYPECEVT2IE_Pos            (15U)
13630 #define UCPD_IMR_TYPECEVT2IE_Msk            (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos)  /*!< 0x00008000 */
13631 #define UCPD_IMR_TYPECEVT2IE                UCPD_IMR_TYPECEVT2IE_Msk             /*!< Enable TYPECEVT2IE interrupt  */
13632 #define UCPD_IMR_FRSEVTIE_Pos               (20U)
13633 #define UCPD_IMR_FRSEVTIE_Msk               (0x1UL << UCPD_IMR_FRSEVTIE_Pos)     /*!< 0x00100000 */
13634 #define UCPD_IMR_FRSEVTIE                   UCPD_IMR_FRSEVTIE_Msk                /*!< Fast Role Swap interrupt  */
13635 
13636 /********************  Bits definition for UCPD_SR register  ********************/
13637 #define UCPD_SR_TXIS_Pos                    (0U)
13638 #define UCPD_SR_TXIS_Msk                    (0x1UL << UCPD_SR_TXIS_Pos)          /*!< 0x00000001 */
13639 #define UCPD_SR_TXIS                        UCPD_SR_TXIS_Msk                     /*!< Transmit interrupt status  */
13640 #define UCPD_SR_TXMSGDISC_Pos               (1U)
13641 #define UCPD_SR_TXMSGDISC_Msk               (0x1UL << UCPD_SR_TXMSGDISC_Pos)     /*!< 0x00000002 */
13642 #define UCPD_SR_TXMSGDISC                   UCPD_SR_TXMSGDISC_Msk                /*!< Transmit message discarded interrupt  */
13643 #define UCPD_SR_TXMSGSENT_Pos               (2U)
13644 #define UCPD_SR_TXMSGSENT_Msk               (0x1UL << UCPD_SR_TXMSGSENT_Pos)     /*!< 0x00000004 */
13645 #define UCPD_SR_TXMSGSENT                   UCPD_SR_TXMSGSENT_Msk                /*!< Transmit message sent interrupt  */
13646 #define UCPD_SR_TXMSGABT_Pos                (3U)
13647 #define UCPD_SR_TXMSGABT_Msk                (0x1UL << UCPD_SR_TXMSGABT_Pos)      /*!< 0x00000008 */
13648 #define UCPD_SR_TXMSGABT                    UCPD_SR_TXMSGABT_Msk                 /*!< Transmit message abort interrupt  */
13649 #define UCPD_SR_HRSTDISC_Pos                (4U)
13650 #define UCPD_SR_HRSTDISC_Msk                (0x1UL << UCPD_SR_HRSTDISC_Pos)      /*!< 0x00000010 */
13651 #define UCPD_SR_HRSTDISC                    UCPD_SR_HRSTDISC_Msk                 /*!< HRST discarded interrupt  */
13652 #define UCPD_SR_HRSTSENT_Pos                (5U)
13653 #define UCPD_SR_HRSTSENT_Msk                (0x1UL << UCPD_SR_HRSTSENT_Pos)      /*!< 0x00000020 */
13654 #define UCPD_SR_HRSTSENT                    UCPD_SR_HRSTSENT_Msk                 /*!< HRST sent interrupt  */
13655 #define UCPD_SR_TXUND_Pos                   (6U)
13656 #define UCPD_SR_TXUND_Msk                   (0x1UL << UCPD_SR_TXUND_Pos)         /*!< 0x00000040 */
13657 #define UCPD_SR_TXUND                       UCPD_SR_TXUND_Msk                    /*!< Tx data underrun condition interrupt  */
13658 #define UCPD_SR_RXNE_Pos                    (8U)
13659 #define UCPD_SR_RXNE_Msk                    (0x1UL << UCPD_SR_RXNE_Pos)          /*!< 0x00000100 */
13660 #define UCPD_SR_RXNE                        UCPD_SR_RXNE_Msk                     /*!< Receive data register not empty interrupt  */
13661 #define UCPD_SR_RXORDDET_Pos                (9U)
13662 #define UCPD_SR_RXORDDET_Msk                (0x1UL << UCPD_SR_RXORDDET_Pos)      /*!< 0x00000200 */
13663 #define UCPD_SR_RXORDDET                    UCPD_SR_RXORDDET_Msk                 /*!< Rx ordered set (4 K-codes) detected interrupt  */
13664 #define UCPD_SR_RXHRSTDET_Pos               (10U)
13665 #define UCPD_SR_RXHRSTDET_Msk               (0x1UL << UCPD_SR_RXHRSTDET_Pos)     /*!< 0x00000400 */
13666 #define UCPD_SR_RXHRSTDET                   UCPD_SR_RXHRSTDET_Msk                /*!< Rx Hard Reset detect interrupt  */
13667 #define UCPD_SR_RXOVR_Pos                   (11U)
13668 #define UCPD_SR_RXOVR_Msk                   (0x1UL << UCPD_SR_RXOVR_Pos)         /*!< 0x00000800 */
13669 #define UCPD_SR_RXOVR                       UCPD_SR_RXOVR_Msk                    /*!< Rx data overflow interrupt  */
13670 #define UCPD_SR_RXMSGEND_Pos                (12U)
13671 #define UCPD_SR_RXMSGEND_Msk                (0x1UL << UCPD_SR_RXMSGEND_Pos)      /*!< 0x00001000 */
13672 #define UCPD_SR_RXMSGEND                    UCPD_SR_RXMSGEND_Msk                 /*!< Rx message received  */
13673 #define UCPD_SR_RXERR_Pos                   (13U)
13674 #define UCPD_SR_RXERR_Msk                   (0x1UL << UCPD_SR_RXERR_Pos)         /*!< 0x00002000 */
13675 #define UCPD_SR_RXERR                       UCPD_SR_RXERR_Msk                    /*!< RX Error */
13676 #define UCPD_SR_TYPECEVT1_Pos               (14U)
13677 #define UCPD_SR_TYPECEVT1_Msk               (0x1UL << UCPD_SR_TYPECEVT1_Pos)     /*!< 0x00004000 */
13678 #define UCPD_SR_TYPECEVT1                   UCPD_SR_TYPECEVT1_Msk                /*!< Type C voltage level event on CC1  */
13679 #define UCPD_SR_TYPECEVT2_Pos               (15U)
13680 #define UCPD_SR_TYPECEVT2_Msk               (0x1UL << UCPD_SR_TYPECEVT2_Pos)     /*!< 0x00008000 */
13681 #define UCPD_SR_TYPECEVT2                   UCPD_SR_TYPECEVT2_Msk                /*!< Type C voltage level event on CC2  */
13682 #define UCPD_SR_TYPEC_VSTATE_CC1_Pos        (16U)
13683 #define UCPD_SR_TYPEC_VSTATE_CC1_Msk        (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00030000 */
13684 #define UCPD_SR_TYPEC_VSTATE_CC1            UCPD_SR_TYPEC_VSTATE_CC1_Msk           /*!< Status of DC level on CC1 pin  */
13685 #define UCPD_SR_TYPEC_VSTATE_CC1_0          (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00010000 */
13686 #define UCPD_SR_TYPEC_VSTATE_CC1_1          (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00020000 */
13687 #define UCPD_SR_TYPEC_VSTATE_CC2_Pos        (18U)
13688 #define UCPD_SR_TYPEC_VSTATE_CC2_Msk        (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x000C0000 */
13689 #define UCPD_SR_TYPEC_VSTATE_CC2            UCPD_SR_TYPEC_VSTATE_CC2_Msk           /*!<Status of DC level on CC2 pin  */
13690 #define UCPD_SR_TYPEC_VSTATE_CC2_0          (0x1UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00040000 */
13691 #define UCPD_SR_TYPEC_VSTATE_CC2_1          (0x2UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00080000 */
13692 #define UCPD_SR_FRSEVT_Pos                  (20U)
13693 #define UCPD_SR_FRSEVT_Msk                  (0x1UL << UCPD_SR_FRSEVT_Pos)        /*!< 0x00100000 */
13694 #define UCPD_SR_FRSEVT                      UCPD_SR_FRSEVT_Msk                   /*!< Fast Role Swap detection event  */
13695 
13696 /********************  Bits definition for UCPD_ICR register  *******************/
13697 #define UCPD_ICR_TXMSGDISCCF_Pos            (1U)
13698 #define UCPD_ICR_TXMSGDISCCF_Msk            (0x1UL << UCPD_ICR_TXMSGDISCCF_Pos)  /*!< 0x00000002 */
13699 #define UCPD_ICR_TXMSGDISCCF                UCPD_ICR_TXMSGDISCCF_Msk             /*!< Tx message discarded flag (TXMSGDISC) clear  */
13700 #define UCPD_ICR_TXMSGSENTCF_Pos            (2U)
13701 #define UCPD_ICR_TXMSGSENTCF_Msk            (0x1UL << UCPD_ICR_TXMSGSENTCF_Pos)  /*!< 0x00000004 */
13702 #define UCPD_ICR_TXMSGSENTCF                UCPD_ICR_TXMSGSENTCF_Msk             /*!< Tx message sent flag (TXMSGSENT) clear  */
13703 #define UCPD_ICR_TXMSGABTCF_Pos             (3U)
13704 #define UCPD_ICR_TXMSGABTCF_Msk             (0x1UL << UCPD_ICR_TXMSGABTCF_Pos)   /*!< 0x00000008 */
13705 #define UCPD_ICR_TXMSGABTCF                 UCPD_ICR_TXMSGABTCF_Msk              /*!< Tx message abort flag (TXMSGABT) clear  */
13706 #define UCPD_ICR_HRSTDISCCF_Pos             (4U)
13707 #define UCPD_ICR_HRSTDISCCF_Msk             (0x1UL << UCPD_ICR_HRSTDISCCF_Pos)   /*!< 0x00000010 */
13708 #define UCPD_ICR_HRSTDISCCF                 UCPD_ICR_HRSTDISCCF_Msk              /*!< Hard reset discarded flag (HRSTDISC) clear  */
13709 #define UCPD_ICR_HRSTSENTCF_Pos             (5U)
13710 #define UCPD_ICR_HRSTSENTCF_Msk             (0x1UL << UCPD_ICR_HRSTSENTCF_Pos)   /*!< 0x00000020 */
13711 #define UCPD_ICR_HRSTSENTCF                 UCPD_ICR_HRSTSENTCF_Msk              /*!< Hard reset sent flag (HRSTSENT) clear  */
13712 #define UCPD_ICR_TXUNDCF_Pos                (6U)
13713 #define UCPD_ICR_TXUNDCF_Msk                (0x1UL << UCPD_ICR_TXUNDCF_Pos)      /*!< 0x00000040 */
13714 #define UCPD_ICR_TXUNDCF                    UCPD_ICR_TXUNDCF_Msk                 /*!< Tx underflow flag (TXUND) clear  */
13715 #define UCPD_ICR_RXORDDETCF_Pos             (9U)
13716 #define UCPD_ICR_RXORDDETCF_Msk             (0x1UL << UCPD_ICR_RXORDDETCF_Pos)   /*!< 0x00000200 */
13717 #define UCPD_ICR_RXORDDETCF                 UCPD_ICR_RXORDDETCF_Msk              /*!< Rx ordered set detect flag (RXORDDET) clear  */
13718 #define UCPD_ICR_RXHRSTDETCF_Pos            (10U)
13719 #define UCPD_ICR_RXHRSTDETCF_Msk            (0x1UL << UCPD_ICR_RXHRSTDETCF_Pos)  /*!< 0x00000400 */
13720 #define UCPD_ICR_RXHRSTDETCF                UCPD_ICR_RXHRSTDETCF_Msk             /*!< Rx Hard Reset detected flag (RXHRSTDET) clear  */
13721 #define UCPD_ICR_RXOVRCF_Pos                (11U)
13722 #define UCPD_ICR_RXOVRCF_Msk                (0x1UL << UCPD_ICR_RXOVRCF_Pos)      /*!< 0x00000800 */
13723 #define UCPD_ICR_RXOVRCF                    UCPD_ICR_RXOVRCF_Msk                 /*!< Rx overflow flag (RXOVR) clear  */
13724 #define UCPD_ICR_RXMSGENDCF_Pos             (12U)
13725 #define UCPD_ICR_RXMSGENDCF_Msk             (0x1UL << UCPD_ICR_RXMSGENDCF_Pos)   /*!< 0x00001000 */
13726 #define UCPD_ICR_RXMSGENDCF                 UCPD_ICR_RXMSGENDCF_Msk              /*!< Rx message received flag (RXMSGEND) clear  */
13727 #define UCPD_ICR_TYPECEVT1CF_Pos            (14U)
13728 #define UCPD_ICR_TYPECEVT1CF_Msk            (0x1UL << UCPD_ICR_TYPECEVT1CF_Pos)  /*!< 0x00004000 */
13729 #define UCPD_ICR_TYPECEVT1CF                UCPD_ICR_TYPECEVT1CF_Msk             /*!< TypeC event (CC1) flag (TYPECEVT1) clear  */
13730 #define UCPD_ICR_TYPECEVT2CF_Pos            (15U)
13731 #define UCPD_ICR_TYPECEVT2CF_Msk            (0x1UL << UCPD_ICR_TYPECEVT2CF_Pos)  /*!< 0x00008000 */
13732 #define UCPD_ICR_TYPECEVT2CF                UCPD_ICR_TYPECEVT2CF_Msk             /*!< TypeC event (CC2) flag (TYPECEVT2) clear  */
13733 #define UCPD_ICR_FRSEVTCF_Pos               (20U)
13734 #define UCPD_ICR_FRSEVTCF_Msk               (0x1UL << UCPD_ICR_FRSEVTCF_Pos)     /*!< 0x00100000 */
13735 #define UCPD_ICR_FRSEVTCF                   UCPD_ICR_FRSEVTCF_Msk                /*!< Fast Role Swap event flag clear  */
13736 
13737 /********************  Bits definition for UCPD_TXORDSET register  **************/
13738 #define UCPD_TX_ORDSET_TXORDSET_Pos         (0U)
13739 #define UCPD_TX_ORDSET_TXORDSET_Msk         (0xFFFFFUL << UCPD_TX_ORDSET_TXORDSET_Pos)/*!< 0x000FFFFF */
13740 #define UCPD_TX_ORDSET_TXORDSET             UCPD_TX_ORDSET_TXORDSET_Msk               /*!< Tx Ordered Set */
13741 
13742 /********************  Bits definition for UCPD_TXPAYSZ register  ****************/
13743 #define UCPD_TX_PAYSZ_TXPAYSZ_Pos           (0U)
13744 #define UCPD_TX_PAYSZ_TXPAYSZ_Msk           (0x3FFUL << UCPD_TX_PAYSZ_TXPAYSZ_Pos)/*!< 0x000003FF */
13745 #define UCPD_TX_PAYSZ_TXPAYSZ               UCPD_TX_PAYSZ_TXPAYSZ_Msk             /*!< Tx payload size in bytes  */
13746 
13747 /********************  Bits definition for UCPD_TXDR register  *******************/
13748 #define UCPD_TXDR_TXDATA_Pos                (0U)
13749 #define UCPD_TXDR_TXDATA_Msk                 (0xFFUL << UCPD_TXDR_TXDATA_Pos)     /*!< 0x000000FF */
13750 #define UCPD_TXDR_TXDATA                    UCPD_TXDR_TXDATA_Msk                  /*!< Tx Data Register */
13751 
13752 /********************  Bits definition for UCPD_RXORDSET register  **************/
13753 #define UCPD_RX_ORDSET_RXORDSET_Pos         (0U)
13754 #define UCPD_RX_ORDSET_RXORDSET_Msk         (0x7UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000007 */
13755 #define UCPD_RX_ORDSET_RXORDSET             UCPD_RX_ORDSET_RXORDSET_Msk            /*!< Rx Ordered Set Code detected  */
13756 #define UCPD_RX_ORDSET_RXORDSET_0           (0x1UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000001 */
13757 #define UCPD_RX_ORDSET_RXORDSET_1           (0x2UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000002 */
13758 #define UCPD_RX_ORDSET_RXORDSET_2           (0x4UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000004 */
13759 #define UCPD_RX_ORDSET_RXSOP3OF4_Pos        (3U)
13760 #define UCPD_RX_ORDSET_RXSOP3OF4_Msk        (0x1UL << UCPD_RX_ORDSET_RXSOP3OF4_Pos)/*!< 0x00000008 */
13761 #define UCPD_RX_ORDSET_RXSOP3OF4            UCPD_RX_ORDSET_RXSOP3OF4_Msk           /*!< Rx Ordered Set Debug indication */
13762 #define UCPD_RX_ORDSET_RXSOPKINVALID_Pos    (4U)
13763 #define UCPD_RX_ORDSET_RXSOPKINVALID_Msk    (0x7UL << UCPD_RX_ORDSET_RXSOPKINVALID_Pos)/*!< 0x00000070 */
13764 #define UCPD_RX_ORDSET_RXSOPKINVALID        UCPD_RX_ORDSET_RXSOPKINVALID_Msk           /*!< Rx Ordered Set corrupted K-Codes (Debug) */
13765 
13766 /********************  Bits definition for UCPD_RXPAYSZ register  ****************/
13767 #define UCPD_RX_PAYSZ_RXPAYSZ_Pos           (0U)
13768 #define UCPD_RX_PAYSZ_RXPAYSZ_Msk           (0x3FFUL << UCPD_RX_PAYSZ_RXPAYSZ_Pos)/*!< 0x000003FF */
13769 #define UCPD_RX_PAYSZ_RXPAYSZ               UCPD_RX_PAYSZ_RXPAYSZ_Msk             /*!< Rx payload size in bytes  */
13770 
13771 /********************  Bits definition for UCPD_RXDR register  *******************/
13772 #define UCPD_RXDR_RXDATA_Pos                (0U)
13773 #define UCPD_RXDR_RXDATA_Msk                (0xFFUL << UCPD_RXDR_RXDATA_Pos)     /*!< 0x000000FF */
13774 #define UCPD_RXDR_RXDATA                    UCPD_RXDR_RXDATA_Msk                 /*!< 8-bit receive data  */
13775 
13776 /********************  Bits definition for UCPD_RXORDEXT1 register  **************/
13777 #define UCPD_RX_ORDEXT1_RXSOPX1_Pos         (0U)
13778 #define UCPD_RX_ORDEXT1_RXSOPX1_Msk         (0xFFFFFUL << UCPD_RX_ORDEXT1_RXSOPX1_Pos)/*!< 0x000FFFFF */
13779 #define UCPD_RX_ORDEXT1_RXSOPX1             UCPD_RX_ORDEXT1_RXSOPX1_Msk               /*!< RX Ordered Set Extension Register 1 */
13780 
13781 /********************  Bits definition for UCPD_RXORDEXT2 register  **************/
13782 #define UCPD_RX_ORDEXT2_RXSOPX2_Pos         (0U)
13783 #define UCPD_RX_ORDEXT2_RXSOPX2_Msk         (0xFFFFFUL << UCPD_RX_ORDEXT2_RXSOPX2_Pos)/*!< 0x000FFFFF */
13784 #define UCPD_RX_ORDEXT2_RXSOPX2             UCPD_RX_ORDEXT2_RXSOPX2_Msk               /*!< RX Ordered Set Extension Register 1 */
13785 
13786 /******************************************************************************/
13787 /*                                                                            */
13788 /*                            Window WATCHDOG                                 */
13789 /*                                                                            */
13790 /******************************************************************************/
13791 /*******************  Bit definition for WWDG_CR register  ********************/
13792 #define WWDG_CR_T_Pos           (0U)
13793 #define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */
13794 #define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
13795 #define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                      /*!< 0x00000001 */
13796 #define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                      /*!< 0x00000002 */
13797 #define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                      /*!< 0x00000004 */
13798 #define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                      /*!< 0x00000008 */
13799 #define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                      /*!< 0x00000010 */
13800 #define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                      /*!< 0x00000020 */
13801 #define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                      /*!< 0x00000040 */
13802 
13803 #define WWDG_CR_WDGA_Pos        (7U)
13804 #define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */
13805 #define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
13806 
13807 /*******************  Bit definition for WWDG_CFR register  *******************/
13808 #define WWDG_CFR_W_Pos          (0U)
13809 #define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */
13810 #define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
13811 #define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                     /*!< 0x00000001 */
13812 #define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                     /*!< 0x00000002 */
13813 #define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                     /*!< 0x00000004 */
13814 #define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                     /*!< 0x00000008 */
13815 #define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                     /*!< 0x00000010 */
13816 #define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                     /*!< 0x00000020 */
13817 #define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                     /*!< 0x00000040 */
13818 
13819 #define WWDG_CFR_WDGTB_Pos      (11U)
13820 #define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */
13821 #define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */
13822 #define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00000800 */
13823 #define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00001000 */
13824 #define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00002000 */
13825 
13826 #define WWDG_CFR_EWI_Pos        (9U)
13827 #define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */
13828 #define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
13829 
13830 /*******************  Bit definition for WWDG_SR register  ********************/
13831 #define WWDG_SR_EWIF_Pos        (0U)
13832 #define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */
13833 #define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
13834 
13835 /**
13836   * @}
13837   */
13838 
13839 /**
13840   * @}
13841   */
13842 
13843 /** @addtogroup Exported_macros
13844   * @{
13845   */
13846 
13847 /******************************* ADC Instances ********************************/
13848 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
13849                                        ((INSTANCE) == ADC2) || \
13850                                        ((INSTANCE) == ADC3) || \
13851                                        ((INSTANCE) == ADC4) || \
13852                                        ((INSTANCE) == ADC5))
13853 
13854 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
13855                                                     ((INSTANCE) == ADC3))
13856 
13857 #define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) || \
13858                                           ((INSTANCE) == ADC345_COMMON) )
13859 
13860 
13861 /******************************** FDCAN Instances ******************************/
13862 #define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1) || \
13863                                          ((INSTANCE) == FDCAN2) || \
13864                                          ((INSTANCE) == FDCAN3))
13865 
13866 #define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN_CONFIG)
13867 /******************************** COMP Instances ******************************/
13868 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
13869                                         ((INSTANCE) == COMP2) || \
13870                                         ((INSTANCE) == COMP3) || \
13871                                         ((INSTANCE) == COMP4) || \
13872                                         ((INSTANCE) == COMP5) || \
13873                                         ((INSTANCE) == COMP6) || \
13874                                         ((INSTANCE) == COMP7))
13875 
13876 /******************************* CORDIC Instances *****************************/
13877 #define IS_CORDIC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CORDIC)
13878 
13879 /******************************* CRC Instances ********************************/
13880 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
13881 
13882 /******************************* DAC Instances ********************************/
13883 #define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1) || \
13884                                        ((INSTANCE) == DAC2) || \
13885                                        ((INSTANCE) == DAC3) || \
13886                                        ((INSTANCE) == DAC4))
13887 
13888 
13889 /******************************** DMA Instances *******************************/
13890 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
13891                                        ((INSTANCE) == DMA1_Channel2) || \
13892                                        ((INSTANCE) == DMA1_Channel3) || \
13893                                        ((INSTANCE) == DMA1_Channel4) || \
13894                                        ((INSTANCE) == DMA1_Channel5) || \
13895                                        ((INSTANCE) == DMA1_Channel6) || \
13896                                        ((INSTANCE) == DMA1_Channel7) || \
13897                                        ((INSTANCE) == DMA1_Channel8) || \
13898                                        ((INSTANCE) == DMA2_Channel1) || \
13899                                        ((INSTANCE) == DMA2_Channel2) || \
13900                                        ((INSTANCE) == DMA2_Channel3) || \
13901                                        ((INSTANCE) == DMA2_Channel4) || \
13902                                        ((INSTANCE) == DMA2_Channel5) || \
13903                                        ((INSTANCE) == DMA2_Channel6) || \
13904                                        ((INSTANCE) == DMA2_Channel7) || \
13905                                        ((INSTANCE) == DMA2_Channel8))
13906 
13907 #define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
13908                                                    ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
13909                                                    ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
13910                                                    ((INSTANCE) == DMAMUX1_RequestGenerator3))
13911 
13912 /******************************* FMAC Instances *******************************/
13913 #define IS_FMAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FMAC)
13914 
13915 /******************************* GPIO Instances *******************************/
13916 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
13917                                         ((INSTANCE) == GPIOB) || \
13918                                         ((INSTANCE) == GPIOC) || \
13919                                         ((INSTANCE) == GPIOD) || \
13920                                         ((INSTANCE) == GPIOE) || \
13921                                         ((INSTANCE) == GPIOF) || \
13922                                         ((INSTANCE) == GPIOG))
13923 
13924 /******************************* GPIO AF Instances ****************************/
13925 #define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
13926 
13927 /**************************** GPIO Lock Instances *****************************/
13928 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
13929 
13930 /******************************** I2C Instances *******************************/
13931 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
13932                                        ((INSTANCE) == I2C2) || \
13933                                        ((INSTANCE) == I2C3) || \
13934                                        ((INSTANCE) == I2C4))
13935 
13936 /****************** I2C Instances : wakeup capability from stop modes *********/
13937 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
13938 
13939 /****************************** OPAMP Instances *******************************/
13940 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
13941                                          ((INSTANCE) == OPAMP2) || \
13942                                          ((INSTANCE) == OPAMP3) || \
13943                                          ((INSTANCE) == OPAMP4) || \
13944                                          ((INSTANCE) == OPAMP5) || \
13945                                          ((INSTANCE) == OPAMP6))
13946 
13947 /******************************** PCD Instances *******************************/
13948 #define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
13949 
13950 /******************************* QSPI Instances *******************************/
13951 #define IS_QSPI_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == QUADSPI)
13952 
13953 /******************************* RNG Instances ********************************/
13954 #define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
13955 
13956 /****************************** RTC Instances *********************************/
13957 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
13958 
13959 #define IS_TAMP_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == TAMP)
13960 
13961 /****************************** SMBUS Instances *******************************/
13962 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
13963                                          ((INSTANCE) == I2C2) || \
13964                                          ((INSTANCE) == I2C3) || \
13965                                          ((INSTANCE) == I2C4))
13966 
13967 /******************************** SAI Instances *******************************/
13968 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || ((INSTANCE) == SAI1_Block_B))
13969 
13970 /******************************** SPI Instances *******************************/
13971 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
13972                                        ((INSTANCE) == SPI2) || \
13973                                        ((INSTANCE) == SPI3) || \
13974                                        ((INSTANCE) == SPI4))
13975 
13976 /******************************** I2S Instances *******************************/
13977 #define IS_I2S_ALL_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == SPI2) || \
13978                                             ((__INSTANCE__) == SPI3))
13979 
13980 /****************** LPTIM Instances : All supported instances *****************/
13981 #define IS_LPTIM_INSTANCE(INSTANCE)     ((INSTANCE) == LPTIM1)
13982 
13983 /****************** LPTIM Instances : supporting encoder interface **************/
13984 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)     ((INSTANCE) == LPTIM1)
13985 
13986 /****************** LPTIM Instances : All supported instances *****************/
13987 #define IS_LPTIM_ENCODER_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
13988 
13989 /****************** TIM Instances : All supported instances *******************/
13990 #define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
13991                                          ((INSTANCE) == TIM2)   || \
13992                                          ((INSTANCE) == TIM3)   || \
13993                                          ((INSTANCE) == TIM4)   || \
13994                                          ((INSTANCE) == TIM5)   || \
13995                                          ((INSTANCE) == TIM6)   || \
13996                                          ((INSTANCE) == TIM7)   || \
13997                                          ((INSTANCE) == TIM8)   || \
13998                                          ((INSTANCE) == TIM15)  || \
13999                                          ((INSTANCE) == TIM16)  || \
14000                                          ((INSTANCE) == TIM17)  || \
14001                                          ((INSTANCE) == TIM20))
14002 
14003 /****************** TIM Instances : supporting 32 bits counter ****************/
14004 
14005 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
14006                                                ((INSTANCE) == TIM5))
14007 
14008 /****************** TIM Instances : supporting the break function *************/
14009 #define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
14010                                             ((INSTANCE) == TIM8)    || \
14011                                             ((INSTANCE) == TIM15)   || \
14012                                             ((INSTANCE) == TIM16)   || \
14013                                             ((INSTANCE) == TIM17)   || \
14014                                             ((INSTANCE) == TIM20))
14015 
14016 /************** TIM Instances : supporting Break source selection *************/
14017 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
14018                                                ((INSTANCE) == TIM8)   || \
14019                                                ((INSTANCE) == TIM15)  || \
14020                                                ((INSTANCE) == TIM16)  || \
14021                                                ((INSTANCE) == TIM17)  || \
14022                                                ((INSTANCE) == TIM20))
14023 
14024 /****************** TIM Instances : supporting 2 break inputs *****************/
14025 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
14026                                             ((INSTANCE) == TIM8)    || \
14027                                             ((INSTANCE) == TIM20))
14028 
14029 /************* TIM Instances : at least 1 capture/compare channel *************/
14030 #define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
14031                                          ((INSTANCE) == TIM2)   || \
14032                                          ((INSTANCE) == TIM3)   || \
14033                                          ((INSTANCE) == TIM4)   || \
14034                                          ((INSTANCE) == TIM5)   || \
14035                                          ((INSTANCE) == TIM8)   || \
14036                                          ((INSTANCE) == TIM15)  || \
14037                                          ((INSTANCE) == TIM16)  || \
14038                                          ((INSTANCE) == TIM17)  || \
14039                                          ((INSTANCE) == TIM20))
14040 
14041 /************ TIM Instances : at least 2 capture/compare channels *************/
14042 #define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
14043                                          ((INSTANCE) == TIM2)   || \
14044                                          ((INSTANCE) == TIM3)   || \
14045                                          ((INSTANCE) == TIM4)   || \
14046                                          ((INSTANCE) == TIM5)   || \
14047                                          ((INSTANCE) == TIM8)   || \
14048                                          ((INSTANCE) == TIM15)  || \
14049                                          ((INSTANCE) == TIM20))
14050 
14051 /************ TIM Instances : at least 3 capture/compare channels *************/
14052 #define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
14053                                          ((INSTANCE) == TIM2)   || \
14054                                          ((INSTANCE) == TIM3)   || \
14055                                          ((INSTANCE) == TIM4)   || \
14056                                          ((INSTANCE) == TIM5)   || \
14057                                          ((INSTANCE) == TIM8)   || \
14058                                          ((INSTANCE) == TIM20))
14059 
14060 /************ TIM Instances : at least 4 capture/compare channels *************/
14061 #define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
14062                                          ((INSTANCE) == TIM2)   || \
14063                                          ((INSTANCE) == TIM3)   || \
14064                                          ((INSTANCE) == TIM4)   || \
14065                                          ((INSTANCE) == TIM5)   || \
14066                                          ((INSTANCE) == TIM8)   || \
14067                                          ((INSTANCE) == TIM20))
14068 
14069 /****************** TIM Instances : at least 5 capture/compare channels *******/
14070 #define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
14071                                          ((INSTANCE) == TIM8)   || \
14072                                          ((INSTANCE) == TIM20))
14073 
14074 /****************** TIM Instances : at least 6 capture/compare channels *******/
14075 #define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
14076                                          ((INSTANCE) == TIM8)   || \
14077                                          ((INSTANCE) == TIM20))
14078 
14079 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
14080 #define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
14081                                             ((INSTANCE) == TIM8)   || \
14082                                             ((INSTANCE) == TIM15)  || \
14083                                             ((INSTANCE) == TIM16)  || \
14084                                             ((INSTANCE) == TIM17)  || \
14085                                             ((INSTANCE) == TIM20))
14086 
14087 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
14088 #define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
14089                                             ((INSTANCE) == TIM2)   || \
14090                                             ((INSTANCE) == TIM3)   || \
14091                                             ((INSTANCE) == TIM4)   || \
14092                                             ((INSTANCE) == TIM5)   || \
14093                                             ((INSTANCE) == TIM6)   || \
14094                                             ((INSTANCE) == TIM7)   || \
14095                                             ((INSTANCE) == TIM8)   || \
14096                                             ((INSTANCE) == TIM15)  || \
14097                                             ((INSTANCE) == TIM16)  || \
14098                                             ((INSTANCE) == TIM17)  || \
14099                                             ((INSTANCE) == TIM20))
14100 
14101 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
14102 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
14103                                             ((INSTANCE) == TIM2)   || \
14104                                             ((INSTANCE) == TIM3)   || \
14105                                             ((INSTANCE) == TIM4)   || \
14106                                             ((INSTANCE) == TIM5)   || \
14107                                             ((INSTANCE) == TIM8)   || \
14108                                             ((INSTANCE) == TIM15)  || \
14109                                             ((INSTANCE) == TIM16)  || \
14110                                             ((INSTANCE) == TIM17)  || \
14111                                             ((INSTANCE) == TIM20))
14112 
14113 /******************** TIM Instances : DMA burst feature ***********************/
14114 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
14115                                             ((INSTANCE) == TIM2)   || \
14116                                             ((INSTANCE) == TIM3)   || \
14117                                             ((INSTANCE) == TIM4)   || \
14118                                             ((INSTANCE) == TIM5)   || \
14119                                             ((INSTANCE) == TIM8)   || \
14120                                             ((INSTANCE) == TIM15)  || \
14121                                             ((INSTANCE) == TIM16)  || \
14122                                             ((INSTANCE) == TIM17)  || \
14123                                             ((INSTANCE) == TIM20))
14124 
14125 /******************* TIM Instances : output(s) available **********************/
14126 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
14127     ((((INSTANCE) == TIM1) &&                  \
14128      (((CHANNEL) == TIM_CHANNEL_1) ||          \
14129       ((CHANNEL) == TIM_CHANNEL_2) ||          \
14130       ((CHANNEL) == TIM_CHANNEL_3) ||          \
14131       ((CHANNEL) == TIM_CHANNEL_4) ||          \
14132       ((CHANNEL) == TIM_CHANNEL_5) ||          \
14133       ((CHANNEL) == TIM_CHANNEL_6)))           \
14134      ||                                        \
14135      (((INSTANCE) == TIM2) &&                  \
14136      (((CHANNEL) == TIM_CHANNEL_1) ||          \
14137       ((CHANNEL) == TIM_CHANNEL_2) ||          \
14138       ((CHANNEL) == TIM_CHANNEL_3) ||          \
14139       ((CHANNEL) == TIM_CHANNEL_4)))           \
14140      ||                                        \
14141      (((INSTANCE) == TIM3) &&                  \
14142      (((CHANNEL) == TIM_CHANNEL_1) ||          \
14143       ((CHANNEL) == TIM_CHANNEL_2) ||          \
14144       ((CHANNEL) == TIM_CHANNEL_3) ||          \
14145       ((CHANNEL) == TIM_CHANNEL_4)))           \
14146      ||                                        \
14147      (((INSTANCE) == TIM4) &&                  \
14148      (((CHANNEL) == TIM_CHANNEL_1) ||          \
14149       ((CHANNEL) == TIM_CHANNEL_2) ||          \
14150       ((CHANNEL) == TIM_CHANNEL_3) ||          \
14151       ((CHANNEL) == TIM_CHANNEL_4)))           \
14152      ||                                        \
14153      (((INSTANCE) == TIM5) &&                  \
14154      (((CHANNEL) == TIM_CHANNEL_1) ||          \
14155       ((CHANNEL) == TIM_CHANNEL_2) ||          \
14156       ((CHANNEL) == TIM_CHANNEL_3) ||          \
14157       ((CHANNEL) == TIM_CHANNEL_4)))           \
14158      ||                                        \
14159      (((INSTANCE) == TIM8) &&                  \
14160      (((CHANNEL) == TIM_CHANNEL_1) ||          \
14161       ((CHANNEL) == TIM_CHANNEL_2) ||          \
14162       ((CHANNEL) == TIM_CHANNEL_3) ||          \
14163       ((CHANNEL) == TIM_CHANNEL_4) ||          \
14164       ((CHANNEL) == TIM_CHANNEL_5) ||          \
14165       ((CHANNEL) == TIM_CHANNEL_6)))           \
14166      ||                                        \
14167      (((INSTANCE) == TIM15) &&                 \
14168      (((CHANNEL) == TIM_CHANNEL_1) ||          \
14169       ((CHANNEL) == TIM_CHANNEL_2)))           \
14170      ||                                        \
14171      (((INSTANCE) == TIM16) &&                 \
14172      (((CHANNEL) == TIM_CHANNEL_1)))           \
14173      ||                                        \
14174      (((INSTANCE) == TIM17) &&                 \
14175       (((CHANNEL) == TIM_CHANNEL_1)))          \
14176      ||                                        \
14177      (((INSTANCE) == TIM20) &&                 \
14178      (((CHANNEL) == TIM_CHANNEL_1) ||          \
14179       ((CHANNEL) == TIM_CHANNEL_2) ||          \
14180       ((CHANNEL) == TIM_CHANNEL_3) ||          \
14181       ((CHANNEL) == TIM_CHANNEL_4) ||          \
14182       ((CHANNEL) == TIM_CHANNEL_5) ||          \
14183       ((CHANNEL) == TIM_CHANNEL_6))))
14184 
14185 /****************** TIM Instances : supporting complementary output(s) ********/
14186 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
14187    ((((INSTANCE) == TIM1) &&                    \
14188      (((CHANNEL) == TIM_CHANNEL_1) ||           \
14189       ((CHANNEL) == TIM_CHANNEL_2) ||           \
14190       ((CHANNEL) == TIM_CHANNEL_3) ||           \
14191       ((CHANNEL) == TIM_CHANNEL_4)))            \
14192     ||                                          \
14193     (((INSTANCE) == TIM8) &&                    \
14194      (((CHANNEL) == TIM_CHANNEL_1) ||           \
14195       ((CHANNEL) == TIM_CHANNEL_2) ||           \
14196       ((CHANNEL) == TIM_CHANNEL_3) ||           \
14197       ((CHANNEL) == TIM_CHANNEL_4)))            \
14198     ||                                          \
14199     (((INSTANCE) == TIM15) &&                   \
14200      ((CHANNEL) == TIM_CHANNEL_1))              \
14201     ||                                          \
14202     (((INSTANCE) == TIM16) &&                   \
14203      ((CHANNEL) == TIM_CHANNEL_1))              \
14204     ||                                          \
14205     (((INSTANCE) == TIM17) &&                   \
14206      ((CHANNEL) == TIM_CHANNEL_1))              \
14207     ||                                          \
14208     (((INSTANCE) == TIM20) &&                   \
14209      (((CHANNEL) == TIM_CHANNEL_1) ||           \
14210       ((CHANNEL) == TIM_CHANNEL_2) ||           \
14211       ((CHANNEL) == TIM_CHANNEL_3) ||           \
14212       ((CHANNEL) == TIM_CHANNEL_4))))
14213 
14214 /****************** TIM Instances : supporting clock division *****************/
14215 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)    || \
14216                                                     ((INSTANCE) == TIM2)    || \
14217                                                     ((INSTANCE) == TIM3)    || \
14218                                                     ((INSTANCE) == TIM4)    || \
14219                                                     ((INSTANCE) == TIM5)    || \
14220                                                     ((INSTANCE) == TIM8)    || \
14221                                                     ((INSTANCE) == TIM15)   || \
14222                                                     ((INSTANCE) == TIM16)   || \
14223                                                     ((INSTANCE) == TIM17)   || \
14224                                                     ((INSTANCE) == TIM20))
14225 
14226 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
14227 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14228                                                         ((INSTANCE) == TIM2) || \
14229                                                         ((INSTANCE) == TIM3) || \
14230                                                         ((INSTANCE) == TIM4) || \
14231                                                         ((INSTANCE) == TIM5) || \
14232                                                         ((INSTANCE) == TIM8) || \
14233                                                         ((INSTANCE) == TIM20))
14234 
14235 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
14236 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14237                                                         ((INSTANCE) == TIM2) || \
14238                                                         ((INSTANCE) == TIM3) || \
14239                                                         ((INSTANCE) == TIM4) || \
14240                                                         ((INSTANCE) == TIM5) || \
14241                                                         ((INSTANCE) == TIM8) || \
14242                                                         ((INSTANCE) == TIM20))
14243 
14244 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
14245 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
14246                                                         ((INSTANCE) == TIM2) || \
14247                                                         ((INSTANCE) == TIM3) || \
14248                                                         ((INSTANCE) == TIM4) || \
14249                                                         ((INSTANCE) == TIM5) || \
14250                                                         ((INSTANCE) == TIM8) || \
14251                                                         ((INSTANCE) == TIM15)|| \
14252                                                         ((INSTANCE) == TIM20))
14253 
14254 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
14255 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
14256                                                         ((INSTANCE) == TIM2) || \
14257                                                         ((INSTANCE) == TIM3) || \
14258                                                         ((INSTANCE) == TIM4) || \
14259                                                         ((INSTANCE) == TIM5) || \
14260                                                         ((INSTANCE) == TIM8) || \
14261                                                         ((INSTANCE) == TIM15)|| \
14262                                                         ((INSTANCE) == TIM20))
14263 
14264 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
14265 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
14266                                                      ((INSTANCE) == TIM8)   || \
14267                                                      ((INSTANCE) == TIM20))
14268 
14269 /****************** TIM Instances : supporting commutation event generation ***/
14270 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
14271                                                      ((INSTANCE) == TIM8)   || \
14272                                                      ((INSTANCE) == TIM15)  || \
14273                                                      ((INSTANCE) == TIM16)  || \
14274                                                      ((INSTANCE) == TIM17)  || \
14275                                                      ((INSTANCE) == TIM20))
14276 
14277 /****************** TIM Instances : supporting counting mode selection ********/
14278 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
14279                                                         ((INSTANCE) == TIM2) || \
14280                                                         ((INSTANCE) == TIM3) || \
14281                                                         ((INSTANCE) == TIM4) || \
14282                                                         ((INSTANCE) == TIM5) || \
14283                                                         ((INSTANCE) == TIM8) || \
14284                                                         ((INSTANCE) == TIM20))
14285 
14286 /****************** TIM Instances : supporting encoder interface **************/
14287 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
14288                                                       ((INSTANCE) == TIM2)  || \
14289                                                       ((INSTANCE) == TIM3)  || \
14290                                                       ((INSTANCE) == TIM4)  || \
14291                                                       ((INSTANCE) == TIM5)  || \
14292                                                       ((INSTANCE) == TIM8)  || \
14293                                                       ((INSTANCE) == TIM20))
14294 
14295 /****************** TIM Instances : supporting Hall sensor interface **********/
14296 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
14297                                                          ((INSTANCE) == TIM2)   || \
14298                                                          ((INSTANCE) == TIM3)   || \
14299                                                          ((INSTANCE) == TIM4)   || \
14300                                                          ((INSTANCE) == TIM5)   || \
14301                                                          ((INSTANCE) == TIM8)   || \
14302                                                          ((INSTANCE) == TIM15)  || \
14303                                                          ((INSTANCE) == TIM20))
14304 
14305 /**************** TIM Instances : external trigger input available ************/
14306 #define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
14307                                             ((INSTANCE) == TIM2)  || \
14308                                             ((INSTANCE) == TIM3)  || \
14309                                             ((INSTANCE) == TIM4)  || \
14310                                             ((INSTANCE) == TIM5)  || \
14311                                             ((INSTANCE) == TIM8)  || \
14312                                             ((INSTANCE) == TIM20))
14313 
14314 /************* TIM Instances : supporting ETR source selection ***************/
14315 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
14316                                              ((INSTANCE) == TIM2)  || \
14317                                              ((INSTANCE) == TIM3)  || \
14318                                              ((INSTANCE) == TIM4)  || \
14319                                              ((INSTANCE) == TIM5)  || \
14320                                              ((INSTANCE) == TIM8)  || \
14321                                              ((INSTANCE) == TIM20))
14322 
14323 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
14324 #define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
14325                                             ((INSTANCE) == TIM2)  || \
14326                                             ((INSTANCE) == TIM3)  || \
14327                                             ((INSTANCE) == TIM4)  || \
14328                                             ((INSTANCE) == TIM5)  || \
14329                                             ((INSTANCE) == TIM6)  || \
14330                                             ((INSTANCE) == TIM7)  || \
14331                                             ((INSTANCE) == TIM8)  || \
14332                                             ((INSTANCE) == TIM15) || \
14333                                             ((INSTANCE) == TIM20))
14334 
14335 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
14336 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
14337                                             ((INSTANCE) == TIM2)  || \
14338                                             ((INSTANCE) == TIM3)  || \
14339                                             ((INSTANCE) == TIM4)  || \
14340                                             ((INSTANCE) == TIM5)  || \
14341                                             ((INSTANCE) == TIM8)  || \
14342                                             ((INSTANCE) == TIM15) || \
14343                                             ((INSTANCE) == TIM20))
14344 
14345 /****************** TIM Instances : supporting OCxREF clear *******************/
14346 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1)  || \
14347                                                        ((INSTANCE) == TIM2)  || \
14348                                                        ((INSTANCE) == TIM3)  || \
14349                                                        ((INSTANCE) == TIM4)  || \
14350                                                        ((INSTANCE) == TIM5)  || \
14351                                                        ((INSTANCE) == TIM8)  || \
14352                                                        ((INSTANCE) == TIM15) || \
14353                                                        ((INSTANCE) == TIM16) || \
14354                                                        ((INSTANCE) == TIM17) || \
14355                                                        ((INSTANCE) == TIM20))
14356 
14357 /****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
14358 #define IS_TIM_OCCS_INSTANCE(INSTANCE)                (((INSTANCE) == TIM1)  || \
14359                                                        ((INSTANCE) == TIM2)  || \
14360                                                        ((INSTANCE) == TIM3)  || \
14361                                                        ((INSTANCE) == TIM8)  || \
14362                                                        ((INSTANCE) == TIM15) || \
14363                                                        ((INSTANCE) == TIM16) || \
14364                                                        ((INSTANCE) == TIM17) || \
14365                                                        ((INSTANCE) == TIM20))
14366 
14367 /****************** TIM Instances : remapping capability **********************/
14368 #define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
14369                                             ((INSTANCE) == TIM2)  || \
14370                                             ((INSTANCE) == TIM3)  || \
14371                                             ((INSTANCE) == TIM4)  || \
14372                                             ((INSTANCE) == TIM5)  || \
14373                                             ((INSTANCE) == TIM8)  || \
14374                                             ((INSTANCE) == TIM20))
14375 
14376 /****************** TIM Instances : supporting repetition counter *************/
14377 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
14378                                                        ((INSTANCE) == TIM8)  || \
14379                                                        ((INSTANCE) == TIM15) || \
14380                                                        ((INSTANCE) == TIM16) || \
14381                                                        ((INSTANCE) == TIM17) || \
14382                                                        ((INSTANCE) == TIM20))
14383 
14384 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
14385 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
14386                                             ((INSTANCE) == TIM8)    || \
14387                                             ((INSTANCE) == TIM20))
14388 
14389 /******************* TIM Instances : Timer input XOR function *****************/
14390 #define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
14391                                             ((INSTANCE) == TIM2)   || \
14392                                             ((INSTANCE) == TIM3)   || \
14393                                             ((INSTANCE) == TIM4)   || \
14394                                             ((INSTANCE) == TIM5)   || \
14395                                             ((INSTANCE) == TIM8)   || \
14396                                             ((INSTANCE) == TIM15)  || \
14397                                             ((INSTANCE) == TIM20))
14398 
14399 /******************* TIM Instances : Timer input selection ********************/
14400 #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
14401                                          ((INSTANCE) == TIM2)   || \
14402                                          ((INSTANCE) == TIM3)   || \
14403                                          ((INSTANCE) == TIM4)   || \
14404                                          ((INSTANCE) == TIM5)   || \
14405                                          ((INSTANCE) == TIM8)   || \
14406                                          ((INSTANCE) == TIM15)  || \
14407                                          ((INSTANCE) == TIM16)  || \
14408                                          ((INSTANCE) == TIM17)  || \
14409                                          ((INSTANCE) == TIM20))
14410 
14411 /****************** TIM Instances : Advanced timer instances *******************/
14412 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
14413                                                   ((INSTANCE) == TIM8)   || \
14414                                                   ((INSTANCE) == TIM20))
14415 
14416 /****************** TIM Instances : supporting HSE/32 request instances *******************/
14417 #define IS_TIM_HSE32_INSTANCE(INSTANCE)         (((INSTANCE) == TIM16)   || \
14418                                                  ((INSTANCE) == TIM17))
14419 
14420 
14421 /******************** USART Instances : Synchronous mode **********************/
14422 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14423                                      ((INSTANCE) == USART2) || \
14424                                      ((INSTANCE) == USART3))
14425 
14426 /******************** UART Instances : Asynchronous mode **********************/
14427 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14428                                     ((INSTANCE) == USART2) || \
14429                                     ((INSTANCE) == USART3) || \
14430                                     ((INSTANCE) == UART4) || \
14431                                     ((INSTANCE) == UART5))
14432 
14433 /*********************** UART Instances : FIFO mode ***************************/
14434 #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14435                                          ((INSTANCE) == USART2) || \
14436                                          ((INSTANCE) == USART3) || \
14437                                          ((INSTANCE) == UART4) || \
14438                                          ((INSTANCE) == UART5) || \
14439                                          ((INSTANCE) == LPUART1))
14440 
14441 /*********************** UART Instances : SPI Slave mode **********************/
14442 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14443                                               ((INSTANCE) == USART2) || \
14444                                               ((INSTANCE) == USART3))
14445 
14446 /****************** UART Instances : Auto Baud Rate detection ****************/
14447 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14448                                                             ((INSTANCE) == USART2) || \
14449                                                             ((INSTANCE) == USART3) || \
14450                                                             ((INSTANCE) == UART4)  || \
14451                                                             ((INSTANCE) == UART5))
14452 
14453 /****************** UART Instances : Driver Enable *****************/
14454 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \
14455                                                       ((INSTANCE) == USART2) || \
14456                                                       ((INSTANCE) == USART3) || \
14457                                                       ((INSTANCE) == UART4)  || \
14458                                                       ((INSTANCE) == UART5)  || \
14459                                                       ((INSTANCE) == LPUART1))
14460 
14461 /******************** UART Instances : Half-Duplex mode **********************/
14462 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
14463                                                  ((INSTANCE) == USART2) || \
14464                                                  ((INSTANCE) == USART3) || \
14465                                                  ((INSTANCE) == UART4)  || \
14466                                                  ((INSTANCE) == UART5)  || \
14467                                                  ((INSTANCE) == LPUART1))
14468 
14469 /****************** UART Instances : Hardware Flow control ********************/
14470 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14471                                            ((INSTANCE) == USART2) || \
14472                                            ((INSTANCE) == USART3) || \
14473                                            ((INSTANCE) == UART4)  || \
14474                                            ((INSTANCE) == UART5)  || \
14475                                            ((INSTANCE) == LPUART1))
14476 
14477 /******************** UART Instances : LIN mode **********************/
14478 #define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
14479                                           ((INSTANCE) == USART2) || \
14480                                           ((INSTANCE) == USART3) || \
14481                                           ((INSTANCE) == UART4)  || \
14482                                           ((INSTANCE) == UART5))
14483 
14484 /******************** UART Instances : Wake-up from Stop mode **********************/
14485 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
14486                                                       ((INSTANCE) == USART2) || \
14487                                                       ((INSTANCE) == USART3) || \
14488                                                       ((INSTANCE) == UART4)  || \
14489                                                       ((INSTANCE) == UART5)  || \
14490                                                       ((INSTANCE) == LPUART1))
14491 
14492 /*********************** UART Instances : IRDA mode ***************************/
14493 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14494                                     ((INSTANCE) == USART2) || \
14495                                     ((INSTANCE) == USART3) || \
14496                                     ((INSTANCE) == UART4)  || \
14497                                     ((INSTANCE) == UART5))
14498 
14499 /********************* USART Instances : Smard card mode ***********************/
14500 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14501                                          ((INSTANCE) == USART2) || \
14502                                          ((INSTANCE) == USART3))
14503 
14504 /******************** LPUART Instance *****************************************/
14505 #define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
14506 
14507 /****************************** IWDG Instances ********************************/
14508 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
14509 
14510 /****************************** WWDG Instances ********************************/
14511 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
14512 
14513 /****************************** UCPD Instances ********************************/
14514 #define IS_UCPD_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == UCPD1)
14515 
14516 /******************************* USB Instances *******************************/
14517 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
14518 
14519 /**
14520   * @}
14521   */
14522 
14523 
14524 /******************************************************************************/
14525 /*  For a painless codes migration between the STM32G4xx device product       */
14526 /*  lines, the aliases defined below are put in place to overcome the         */
14527 /*  differences in the interrupt handlers and IRQn definitions.               */
14528 /*  No need to update developed interrupt code when moving across             */
14529 /*  product lines within the same STM32G4 Family                              */
14530 /******************************************************************************/
14531 
14532 /* Aliases for __IRQn */
14533 
14534 /* Aliases for __IRQHandler */
14535 
14536 #ifdef __cplusplus
14537 }
14538 #endif /* __cplusplus */
14539 
14540 #endif /* __STM32G473xx_H */
14541 
14542 /**
14543   * @}
14544   */
14545 
14546   /**
14547   * @}
14548   */
14549 
14550