1 /**
2 ******************************************************************************
3 * @file stm32g4xx_hal_tim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer (TIM) peripheral:
8 * + TIM Time Base Initialization
9 * + TIM Time Base Start
10 * + TIM Time Base Start Interruption
11 * + TIM Time Base Start DMA
12 * + TIM Output Compare/PWM Initialization
13 * + TIM Output Compare/PWM Channel Configuration
14 * + TIM Output Compare/PWM Start
15 * + TIM Output Compare/PWM Start Interruption
16 * + TIM Output Compare/PWM Start DMA
17 * + TIM Input Capture Initialization
18 * + TIM Input Capture Channel Configuration
19 * + TIM Input Capture Start
20 * + TIM Input Capture Start Interruption
21 * + TIM Input Capture Start DMA
22 * + TIM One Pulse Initialization
23 * + TIM One Pulse Channel Configuration
24 * + TIM One Pulse Start
25 * + TIM Encoder Interface Initialization
26 * + TIM Encoder Interface Start
27 * + TIM Encoder Interface Start Interruption
28 * + TIM Encoder Interface Start DMA
29 * + Commutation Event configuration with Interruption and DMA
30 * + TIM OCRef clear configuration
31 * + TIM External Clock configuration
32 ******************************************************************************
33 * @attention
34 *
35 * Copyright (c) 2019 STMicroelectronics.
36 * All rights reserved.
37 *
38 * This software is licensed under terms that can be found in the LICENSE file
39 * in the root directory of this software component.
40 * If no LICENSE file comes with this software, it is provided AS-IS.
41 *
42 ******************************************************************************
43 @verbatim
44 ==============================================================================
45 ##### TIMER Generic features #####
46 ==============================================================================
47 [..] The Timer features include:
48 (#) 16-bit up, down, up/down auto-reload counter.
49 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
50 counter clock frequency either by any factor between 1 and 65536.
51 (#) Up to 4 independent channels for:
52 (++) Input Capture
53 (++) Output Compare
54 (++) PWM generation (Edge and Center-aligned Mode)
55 (++) One-pulse mode output
56 (#) Synchronization circuit to control the timer with external signals and to interconnect
57 several timers together.
58 (#) Supports incremental encoder for positioning purposes
59
60 ##### How to use this driver #####
61 ==============================================================================
62 [..]
63 (#) Initialize the TIM low level resources by implementing the following functions
64 depending on the selected feature:
65 (++) Time Base : HAL_TIM_Base_MspInit()
66 (++) Input Capture : HAL_TIM_IC_MspInit()
67 (++) Output Compare : HAL_TIM_OC_MspInit()
68 (++) PWM generation : HAL_TIM_PWM_MspInit()
69 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
70 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
71
72 (#) Initialize the TIM low level resources :
73 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
74 (##) TIM pins configuration
75 (+++) Enable the clock for the TIM GPIOs using the following function:
76 __HAL_RCC_GPIOx_CLK_ENABLE();
77 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
78
79 (#) The external Clock can be configured, if needed (the default clock is the
80 internal clock from the APBx), using the following function:
81 HAL_TIM_ConfigClockSource, the clock configuration should be done before
82 any start function.
83
84 (#) Configure the TIM in the desired functioning mode using one of the
85 Initialization function of this driver:
86 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
87 (++) HAL_TIM_OC_Init, HAL_TIM_OC_ConfigChannel and optionally HAL_TIMEx_OC_ConfigPulseOnCompare:
88 to use the Timer to generate an Output Compare signal.
89 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
90 PWM signal.
91 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
92 external signal.
93 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
94 in One Pulse Mode.
95 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
96
97 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
98 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
99 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
100 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
101 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
102 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
103 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
104
105 (#) The DMA Burst is managed with the two following functions:
106 HAL_TIM_DMABurst_WriteStart()
107 HAL_TIM_DMABurst_ReadStart()
108
109 *** Callback registration ***
110 =============================================
111
112 [..]
113 The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
114 allows the user to configure dynamically the driver callbacks.
115
116 [..]
117 Use Function HAL_TIM_RegisterCallback() to register a callback.
118 HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
119 the Callback ID and a pointer to the user callback function.
120
121 [..]
122 Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
123 weak function.
124 HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
125 and the Callback ID.
126
127 [..]
128 These functions allow to register/unregister following callbacks:
129 (+) Base_MspInitCallback : TIM Base Msp Init Callback.
130 (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
131 (+) IC_MspInitCallback : TIM IC Msp Init Callback.
132 (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
133 (+) OC_MspInitCallback : TIM OC Msp Init Callback.
134 (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
135 (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
136 (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
137 (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
138 (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
139 (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
140 (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
141 (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.
142 (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.
143 (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
144 (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.
145 (+) TriggerCallback : TIM Trigger Callback.
146 (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
147 (+) IC_CaptureCallback : TIM Input Capture Callback.
148 (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.
149 (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
150 (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
151 (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
152 (+) ErrorCallback : TIM Error Callback.
153 (+) CommutationCallback : TIM Commutation Callback.
154 (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.
155 (+) BreakCallback : TIM Break Callback.
156 (+) Break2Callback : TIM Break2 Callback.
157 (+) EncoderIndexCallback : TIM Encoder Index Callback.
158 (+) DirectionChangeCallback : TIM Direction Change Callback
159 (+) IndexErrorCallback : TIM Index Error Callback.
160 (+) TransitionErrorCallback : TIM Transition Error Callback
161
162 [..]
163 By default, after the Init and when the state is HAL_TIM_STATE_RESET
164 all interrupt callbacks are set to the corresponding weak functions:
165 examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
166
167 [..]
168 Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
169 functionalities in the Init / DeInit only when these callbacks are null
170 (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
171 keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
172
173 [..]
174 Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
175 Exception done MspInit / MspDeInit that can be registered / unregistered
176 in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
177 thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
178 In that case first register the MspInit/MspDeInit user callbacks
179 using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
180
181 [..]
182 When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
183 not defined, the callback registration feature is not available and all callbacks
184 are set to the corresponding weak functions.
185
186 @endverbatim
187 ******************************************************************************
188 */
189
190 /* Includes ------------------------------------------------------------------*/
191 #include "stm32g4xx_hal.h"
192
193 /** @addtogroup STM32G4xx_HAL_Driver
194 * @{
195 */
196
197 /** @defgroup TIM TIM
198 * @brief TIM HAL module driver
199 * @{
200 */
201
202 #ifdef HAL_TIM_MODULE_ENABLED
203
204 /* Private typedef -----------------------------------------------------------*/
205 /* Private define ------------------------------------------------------------*/
206 /** @addtogroup TIM_Private_Constants
207 * @{
208 */
209 #define TIMx_AF2_OCRSEL TIM1_AF2_OCRSEL
210
211 /**
212 * @}
213 */
214 /* Private macros ------------------------------------------------------------*/
215 /* Private variables ---------------------------------------------------------*/
216 /* Private function prototypes -----------------------------------------------*/
217 /** @addtogroup TIM_Private_Functions
218 * @{
219 */
220 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
221 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
222 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
223 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
224 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
225 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
226 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
227 uint32_t TIM_ICFilter);
228 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
229 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
230 uint32_t TIM_ICFilter);
231 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
232 uint32_t TIM_ICFilter);
233 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
234 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
235 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
236 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
237 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
238 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
239 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
240 TIM_SlaveConfigTypeDef *sSlaveConfig);
241 /**
242 * @}
243 */
244 /* Exported functions --------------------------------------------------------*/
245
246 /** @defgroup TIM_Exported_Functions TIM Exported Functions
247 * @{
248 */
249
250 /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
251 * @brief Time Base functions
252 *
253 @verbatim
254 ==============================================================================
255 ##### Time Base functions #####
256 ==============================================================================
257 [..]
258 This section provides functions allowing to:
259 (+) Initialize and configure the TIM base.
260 (+) De-initialize the TIM base.
261 (+) Start the Time Base.
262 (+) Stop the Time Base.
263 (+) Start the Time Base and enable interrupt.
264 (+) Stop the Time Base and disable interrupt.
265 (+) Start the Time Base and enable DMA transfer.
266 (+) Stop the Time Base and disable DMA transfer.
267
268 @endverbatim
269 * @{
270 */
271 /**
272 * @brief Initializes the TIM Time base Unit according to the specified
273 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
274 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
275 * requires a timer reset to avoid unexpected direction
276 * due to DIR bit readonly in center aligned mode.
277 * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
278 * @param htim TIM Base handle
279 * @retval HAL status
280 */
HAL_TIM_Base_Init(TIM_HandleTypeDef * htim)281 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
282 {
283 /* Check the TIM handle allocation */
284 if (htim == NULL)
285 {
286 return HAL_ERROR;
287 }
288
289 /* Check the parameters */
290 assert_param(IS_TIM_INSTANCE(htim->Instance));
291 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
292 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
293 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
294
295 if (htim->State == HAL_TIM_STATE_RESET)
296 {
297 /* Allocate lock resource and initialize it */
298 htim->Lock = HAL_UNLOCKED;
299
300 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
301 /* Reset interrupt callbacks to legacy weak callbacks */
302 TIM_ResetCallback(htim);
303
304 if (htim->Base_MspInitCallback == NULL)
305 {
306 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
307 }
308 /* Init the low level hardware : GPIO, CLOCK, NVIC */
309 htim->Base_MspInitCallback(htim);
310 #else
311 /* Init the low level hardware : GPIO, CLOCK, NVIC */
312 HAL_TIM_Base_MspInit(htim);
313 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
314 }
315
316 /* Set the TIM state */
317 htim->State = HAL_TIM_STATE_BUSY;
318
319 /* Set the Time Base configuration */
320 TIM_Base_SetConfig(htim->Instance, &htim->Init);
321
322 /* Initialize the DMA burst operation state */
323 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
324
325 /* Initialize the TIM channels state */
326 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
327 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
328
329 /* Initialize the TIM state*/
330 htim->State = HAL_TIM_STATE_READY;
331
332 return HAL_OK;
333 }
334
335 /**
336 * @brief DeInitializes the TIM Base peripheral
337 * @param htim TIM Base handle
338 * @retval HAL status
339 */
HAL_TIM_Base_DeInit(TIM_HandleTypeDef * htim)340 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
341 {
342 /* Check the parameters */
343 assert_param(IS_TIM_INSTANCE(htim->Instance));
344
345 htim->State = HAL_TIM_STATE_BUSY;
346
347 /* Disable the TIM Peripheral Clock */
348 __HAL_TIM_DISABLE(htim);
349
350 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
351 if (htim->Base_MspDeInitCallback == NULL)
352 {
353 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
354 }
355 /* DeInit the low level hardware */
356 htim->Base_MspDeInitCallback(htim);
357 #else
358 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
359 HAL_TIM_Base_MspDeInit(htim);
360 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
361
362 /* Change the DMA burst operation state */
363 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
364
365 /* Change the TIM channels state */
366 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
367 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
368
369 /* Change TIM state */
370 htim->State = HAL_TIM_STATE_RESET;
371
372 /* Release Lock */
373 __HAL_UNLOCK(htim);
374
375 return HAL_OK;
376 }
377
378 /**
379 * @brief Initializes the TIM Base MSP.
380 * @param htim TIM Base handle
381 * @retval None
382 */
HAL_TIM_Base_MspInit(TIM_HandleTypeDef * htim)383 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
384 {
385 /* Prevent unused argument(s) compilation warning */
386 UNUSED(htim);
387
388 /* NOTE : This function should not be modified, when the callback is needed,
389 the HAL_TIM_Base_MspInit could be implemented in the user file
390 */
391 }
392
393 /**
394 * @brief DeInitializes TIM Base MSP.
395 * @param htim TIM Base handle
396 * @retval None
397 */
HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef * htim)398 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
399 {
400 /* Prevent unused argument(s) compilation warning */
401 UNUSED(htim);
402
403 /* NOTE : This function should not be modified, when the callback is needed,
404 the HAL_TIM_Base_MspDeInit could be implemented in the user file
405 */
406 }
407
408
409 /**
410 * @brief Starts the TIM Base generation.
411 * @param htim TIM Base handle
412 * @retval HAL status
413 */
HAL_TIM_Base_Start(TIM_HandleTypeDef * htim)414 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
415 {
416 uint32_t tmpsmcr;
417
418 /* Check the parameters */
419 assert_param(IS_TIM_INSTANCE(htim->Instance));
420
421 /* Check the TIM state */
422 if (htim->State != HAL_TIM_STATE_READY)
423 {
424 return HAL_ERROR;
425 }
426
427 /* Set the TIM state */
428 htim->State = HAL_TIM_STATE_BUSY;
429
430 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
431 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
432 {
433 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
434 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
435 {
436 __HAL_TIM_ENABLE(htim);
437 }
438 }
439 else
440 {
441 __HAL_TIM_ENABLE(htim);
442 }
443
444 /* Return function status */
445 return HAL_OK;
446 }
447
448 /**
449 * @brief Stops the TIM Base generation.
450 * @param htim TIM Base handle
451 * @retval HAL status
452 */
HAL_TIM_Base_Stop(TIM_HandleTypeDef * htim)453 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
454 {
455 /* Check the parameters */
456 assert_param(IS_TIM_INSTANCE(htim->Instance));
457
458 /* Disable the Peripheral */
459 __HAL_TIM_DISABLE(htim);
460
461 /* Set the TIM state */
462 htim->State = HAL_TIM_STATE_READY;
463
464 /* Return function status */
465 return HAL_OK;
466 }
467
468 /**
469 * @brief Starts the TIM Base generation in interrupt mode.
470 * @param htim TIM Base handle
471 * @retval HAL status
472 */
HAL_TIM_Base_Start_IT(TIM_HandleTypeDef * htim)473 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
474 {
475 uint32_t tmpsmcr;
476
477 /* Check the parameters */
478 assert_param(IS_TIM_INSTANCE(htim->Instance));
479
480 /* Check the TIM state */
481 if (htim->State != HAL_TIM_STATE_READY)
482 {
483 return HAL_ERROR;
484 }
485
486 /* Set the TIM state */
487 htim->State = HAL_TIM_STATE_BUSY;
488
489 /* Enable the TIM Update interrupt */
490 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
491
492 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
493 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
494 {
495 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
496 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
497 {
498 __HAL_TIM_ENABLE(htim);
499 }
500 }
501 else
502 {
503 __HAL_TIM_ENABLE(htim);
504 }
505
506 /* Return function status */
507 return HAL_OK;
508 }
509
510 /**
511 * @brief Stops the TIM Base generation in interrupt mode.
512 * @param htim TIM Base handle
513 * @retval HAL status
514 */
HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef * htim)515 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
516 {
517 /* Check the parameters */
518 assert_param(IS_TIM_INSTANCE(htim->Instance));
519
520 /* Disable the TIM Update interrupt */
521 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
522
523 /* Disable the Peripheral */
524 __HAL_TIM_DISABLE(htim);
525
526 /* Set the TIM state */
527 htim->State = HAL_TIM_STATE_READY;
528
529 /* Return function status */
530 return HAL_OK;
531 }
532
533 /**
534 * @brief Starts the TIM Base generation in DMA mode.
535 * @param htim TIM Base handle
536 * @param pData The source Buffer address.
537 * @param Length The length of data to be transferred from memory to peripheral.
538 * @retval HAL status
539 */
HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef * htim,uint32_t * pData,uint16_t Length)540 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
541 {
542 uint32_t tmpsmcr;
543
544 /* Check the parameters */
545 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
546
547 /* Set the TIM state */
548 if (htim->State == HAL_TIM_STATE_BUSY)
549 {
550 return HAL_BUSY;
551 }
552 else if (htim->State == HAL_TIM_STATE_READY)
553 {
554 if ((pData == NULL) && (Length > 0U))
555 {
556 return HAL_ERROR;
557 }
558 else
559 {
560 htim->State = HAL_TIM_STATE_BUSY;
561 }
562 }
563 else
564 {
565 return HAL_ERROR;
566 }
567
568 /* Set the DMA Period elapsed callbacks */
569 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
570 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
571
572 /* Set the DMA error callback */
573 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
574
575 /* Enable the DMA channel */
576 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
577 Length) != HAL_OK)
578 {
579 /* Return error status */
580 return HAL_ERROR;
581 }
582
583 /* Enable the TIM Update DMA request */
584 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
585
586 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
587 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
588 {
589 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
590 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
591 {
592 __HAL_TIM_ENABLE(htim);
593 }
594 }
595 else
596 {
597 __HAL_TIM_ENABLE(htim);
598 }
599
600 /* Return function status */
601 return HAL_OK;
602 }
603
604 /**
605 * @brief Stops the TIM Base generation in DMA mode.
606 * @param htim TIM Base handle
607 * @retval HAL status
608 */
HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef * htim)609 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
610 {
611 /* Check the parameters */
612 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
613
614 /* Disable the TIM Update DMA request */
615 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
616
617 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
618
619 /* Disable the Peripheral */
620 __HAL_TIM_DISABLE(htim);
621
622 /* Set the TIM state */
623 htim->State = HAL_TIM_STATE_READY;
624
625 /* Return function status */
626 return HAL_OK;
627 }
628
629 /**
630 * @}
631 */
632
633 /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
634 * @brief TIM Output Compare functions
635 *
636 @verbatim
637 ==============================================================================
638 ##### TIM Output Compare functions #####
639 ==============================================================================
640 [..]
641 This section provides functions allowing to:
642 (+) Initialize and configure the TIM Output Compare.
643 (+) De-initialize the TIM Output Compare.
644 (+) Start the TIM Output Compare.
645 (+) Stop the TIM Output Compare.
646 (+) Start the TIM Output Compare and enable interrupt.
647 (+) Stop the TIM Output Compare and disable interrupt.
648 (+) Start the TIM Output Compare and enable DMA transfer.
649 (+) Stop the TIM Output Compare and disable DMA transfer.
650
651 @endverbatim
652 * @{
653 */
654 /**
655 * @brief Initializes the TIM Output Compare according to the specified
656 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
657 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
658 * requires a timer reset to avoid unexpected direction
659 * due to DIR bit readonly in center aligned mode.
660 * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
661 * @param htim TIM Output Compare handle
662 * @retval HAL status
663 */
HAL_TIM_OC_Init(TIM_HandleTypeDef * htim)664 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
665 {
666 /* Check the TIM handle allocation */
667 if (htim == NULL)
668 {
669 return HAL_ERROR;
670 }
671
672 /* Check the parameters */
673 assert_param(IS_TIM_INSTANCE(htim->Instance));
674 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
675 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
676 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
677
678 if (htim->State == HAL_TIM_STATE_RESET)
679 {
680 /* Allocate lock resource and initialize it */
681 htim->Lock = HAL_UNLOCKED;
682
683 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
684 /* Reset interrupt callbacks to legacy weak callbacks */
685 TIM_ResetCallback(htim);
686
687 if (htim->OC_MspInitCallback == NULL)
688 {
689 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
690 }
691 /* Init the low level hardware : GPIO, CLOCK, NVIC */
692 htim->OC_MspInitCallback(htim);
693 #else
694 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
695 HAL_TIM_OC_MspInit(htim);
696 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
697 }
698
699 /* Set the TIM state */
700 htim->State = HAL_TIM_STATE_BUSY;
701
702 /* Init the base time for the Output Compare */
703 TIM_Base_SetConfig(htim->Instance, &htim->Init);
704
705 /* Initialize the DMA burst operation state */
706 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
707
708 /* Initialize the TIM channels state */
709 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
710 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
711
712 /* Initialize the TIM state*/
713 htim->State = HAL_TIM_STATE_READY;
714
715 return HAL_OK;
716 }
717
718 /**
719 * @brief DeInitializes the TIM peripheral
720 * @param htim TIM Output Compare handle
721 * @retval HAL status
722 */
HAL_TIM_OC_DeInit(TIM_HandleTypeDef * htim)723 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
724 {
725 /* Check the parameters */
726 assert_param(IS_TIM_INSTANCE(htim->Instance));
727
728 htim->State = HAL_TIM_STATE_BUSY;
729
730 /* Disable the TIM Peripheral Clock */
731 __HAL_TIM_DISABLE(htim);
732
733 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
734 if (htim->OC_MspDeInitCallback == NULL)
735 {
736 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
737 }
738 /* DeInit the low level hardware */
739 htim->OC_MspDeInitCallback(htim);
740 #else
741 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
742 HAL_TIM_OC_MspDeInit(htim);
743 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
744
745 /* Change the DMA burst operation state */
746 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
747
748 /* Change the TIM channels state */
749 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
750 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
751
752 /* Change TIM state */
753 htim->State = HAL_TIM_STATE_RESET;
754
755 /* Release Lock */
756 __HAL_UNLOCK(htim);
757
758 return HAL_OK;
759 }
760
761 /**
762 * @brief Initializes the TIM Output Compare MSP.
763 * @param htim TIM Output Compare handle
764 * @retval None
765 */
HAL_TIM_OC_MspInit(TIM_HandleTypeDef * htim)766 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
767 {
768 /* Prevent unused argument(s) compilation warning */
769 UNUSED(htim);
770
771 /* NOTE : This function should not be modified, when the callback is needed,
772 the HAL_TIM_OC_MspInit could be implemented in the user file
773 */
774 }
775
776 /**
777 * @brief DeInitializes TIM Output Compare MSP.
778 * @param htim TIM Output Compare handle
779 * @retval None
780 */
HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef * htim)781 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
782 {
783 /* Prevent unused argument(s) compilation warning */
784 UNUSED(htim);
785
786 /* NOTE : This function should not be modified, when the callback is needed,
787 the HAL_TIM_OC_MspDeInit could be implemented in the user file
788 */
789 }
790
791 /**
792 * @brief Starts the TIM Output Compare signal generation.
793 * @param htim TIM Output Compare handle
794 * @param Channel TIM Channel to be enabled
795 * This parameter can be one of the following values:
796 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
797 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
798 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
799 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
800 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
801 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
802 * @retval HAL status
803 */
HAL_TIM_OC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)804 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
805 {
806 uint32_t tmpsmcr;
807
808 /* Check the parameters */
809 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
810
811 /* Check the TIM channel state */
812 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
813 {
814 return HAL_ERROR;
815 }
816
817 /* Set the TIM channel state */
818 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
819
820 /* Enable the Output compare channel */
821 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
822
823 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
824 {
825 /* Enable the main output */
826 __HAL_TIM_MOE_ENABLE(htim);
827 }
828
829 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
830 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
831 {
832 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
833 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
834 {
835 __HAL_TIM_ENABLE(htim);
836 }
837 }
838 else
839 {
840 __HAL_TIM_ENABLE(htim);
841 }
842
843 /* Return function status */
844 return HAL_OK;
845 }
846
847 /**
848 * @brief Stops the TIM Output Compare signal generation.
849 * @param htim TIM Output Compare handle
850 * @param Channel TIM Channel to be disabled
851 * This parameter can be one of the following values:
852 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
853 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
854 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
855 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
856 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
857 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
858 * @retval HAL status
859 */
HAL_TIM_OC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)860 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
861 {
862 /* Check the parameters */
863 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
864
865 /* Disable the Output compare channel */
866 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
867
868 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
869 {
870 /* Disable the Main Output */
871 __HAL_TIM_MOE_DISABLE(htim);
872 }
873
874 /* Disable the Peripheral */
875 __HAL_TIM_DISABLE(htim);
876
877 /* Set the TIM channel state */
878 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
879
880 /* Return function status */
881 return HAL_OK;
882 }
883
884 /**
885 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
886 * @param htim TIM Output Compare handle
887 * @param Channel TIM Channel to be enabled
888 * This parameter can be one of the following values:
889 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
890 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
891 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
892 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
893 * @retval HAL status
894 */
HAL_TIM_OC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)895 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
896 {
897 HAL_StatusTypeDef status = HAL_OK;
898 uint32_t tmpsmcr;
899
900 /* Check the parameters */
901 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
902
903 /* Check the TIM channel state */
904 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
905 {
906 return HAL_ERROR;
907 }
908
909 /* Set the TIM channel state */
910 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
911
912 switch (Channel)
913 {
914 case TIM_CHANNEL_1:
915 {
916 /* Enable the TIM Capture/Compare 1 interrupt */
917 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
918 break;
919 }
920
921 case TIM_CHANNEL_2:
922 {
923 /* Enable the TIM Capture/Compare 2 interrupt */
924 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
925 break;
926 }
927
928 case TIM_CHANNEL_3:
929 {
930 /* Enable the TIM Capture/Compare 3 interrupt */
931 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
932 break;
933 }
934
935 case TIM_CHANNEL_4:
936 {
937 /* Enable the TIM Capture/Compare 4 interrupt */
938 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
939 break;
940 }
941
942 default:
943 status = HAL_ERROR;
944 break;
945 }
946
947 if (status == HAL_OK)
948 {
949 /* Enable the Output compare channel */
950 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
951
952 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
953 {
954 /* Enable the main output */
955 __HAL_TIM_MOE_ENABLE(htim);
956 }
957
958 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
959 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
960 {
961 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
962 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
963 {
964 __HAL_TIM_ENABLE(htim);
965 }
966 }
967 else
968 {
969 __HAL_TIM_ENABLE(htim);
970 }
971 }
972
973 /* Return function status */
974 return status;
975 }
976
977 /**
978 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
979 * @param htim TIM Output Compare handle
980 * @param Channel TIM Channel to be disabled
981 * This parameter can be one of the following values:
982 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
983 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
984 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
985 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
986 * @retval HAL status
987 */
HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)988 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
989 {
990 HAL_StatusTypeDef status = HAL_OK;
991
992 /* Check the parameters */
993 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
994
995 switch (Channel)
996 {
997 case TIM_CHANNEL_1:
998 {
999 /* Disable the TIM Capture/Compare 1 interrupt */
1000 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1001 break;
1002 }
1003
1004 case TIM_CHANNEL_2:
1005 {
1006 /* Disable the TIM Capture/Compare 2 interrupt */
1007 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1008 break;
1009 }
1010
1011 case TIM_CHANNEL_3:
1012 {
1013 /* Disable the TIM Capture/Compare 3 interrupt */
1014 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1015 break;
1016 }
1017
1018 case TIM_CHANNEL_4:
1019 {
1020 /* Disable the TIM Capture/Compare 4 interrupt */
1021 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1022 break;
1023 }
1024
1025 default:
1026 status = HAL_ERROR;
1027 break;
1028 }
1029
1030 if (status == HAL_OK)
1031 {
1032 /* Disable the Output compare channel */
1033 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1034
1035 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1036 {
1037 /* Disable the Main Output */
1038 __HAL_TIM_MOE_DISABLE(htim);
1039 }
1040
1041 /* Disable the Peripheral */
1042 __HAL_TIM_DISABLE(htim);
1043
1044 /* Set the TIM channel state */
1045 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1046 }
1047
1048 /* Return function status */
1049 return status;
1050 }
1051
1052 /**
1053 * @brief Starts the TIM Output Compare signal generation in DMA mode.
1054 * @param htim TIM Output Compare handle
1055 * @param Channel TIM Channel to be enabled
1056 * This parameter can be one of the following values:
1057 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1058 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1059 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1060 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1061 * @param pData The source Buffer address.
1062 * @param Length The length of data to be transferred from memory to TIM peripheral
1063 * @retval HAL status
1064 */
HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)1065 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1066 {
1067 HAL_StatusTypeDef status = HAL_OK;
1068 uint32_t tmpsmcr;
1069
1070 /* Check the parameters */
1071 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1072
1073 /* Set the TIM channel state */
1074 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1075 {
1076 return HAL_BUSY;
1077 }
1078 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1079 {
1080 if ((pData == NULL) && (Length > 0U))
1081 {
1082 return HAL_ERROR;
1083 }
1084 else
1085 {
1086 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1087 }
1088 }
1089 else
1090 {
1091 return HAL_ERROR;
1092 }
1093
1094 switch (Channel)
1095 {
1096 case TIM_CHANNEL_1:
1097 {
1098 /* Set the DMA compare callbacks */
1099 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1100 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1101
1102 /* Set the DMA error callback */
1103 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1104
1105 /* Enable the DMA channel */
1106 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1107 Length) != HAL_OK)
1108 {
1109 /* Return error status */
1110 return HAL_ERROR;
1111 }
1112
1113 /* Enable the TIM Capture/Compare 1 DMA request */
1114 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1115 break;
1116 }
1117
1118 case TIM_CHANNEL_2:
1119 {
1120 /* Set the DMA compare callbacks */
1121 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1122 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1123
1124 /* Set the DMA error callback */
1125 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1126
1127 /* Enable the DMA channel */
1128 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1129 Length) != HAL_OK)
1130 {
1131 /* Return error status */
1132 return HAL_ERROR;
1133 }
1134
1135 /* Enable the TIM Capture/Compare 2 DMA request */
1136 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1137 break;
1138 }
1139
1140 case TIM_CHANNEL_3:
1141 {
1142 /* Set the DMA compare callbacks */
1143 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1144 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1145
1146 /* Set the DMA error callback */
1147 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1148
1149 /* Enable the DMA channel */
1150 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1151 Length) != HAL_OK)
1152 {
1153 /* Return error status */
1154 return HAL_ERROR;
1155 }
1156 /* Enable the TIM Capture/Compare 3 DMA request */
1157 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1158 break;
1159 }
1160
1161 case TIM_CHANNEL_4:
1162 {
1163 /* Set the DMA compare callbacks */
1164 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1165 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1166
1167 /* Set the DMA error callback */
1168 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1169
1170 /* Enable the DMA channel */
1171 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1172 Length) != HAL_OK)
1173 {
1174 /* Return error status */
1175 return HAL_ERROR;
1176 }
1177 /* Enable the TIM Capture/Compare 4 DMA request */
1178 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1179 break;
1180 }
1181
1182 default:
1183 status = HAL_ERROR;
1184 break;
1185 }
1186
1187 if (status == HAL_OK)
1188 {
1189 /* Enable the Output compare channel */
1190 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1191
1192 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1193 {
1194 /* Enable the main output */
1195 __HAL_TIM_MOE_ENABLE(htim);
1196 }
1197
1198 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1199 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1200 {
1201 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1202 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1203 {
1204 __HAL_TIM_ENABLE(htim);
1205 }
1206 }
1207 else
1208 {
1209 __HAL_TIM_ENABLE(htim);
1210 }
1211 }
1212
1213 /* Return function status */
1214 return status;
1215 }
1216
1217 /**
1218 * @brief Stops the TIM Output Compare signal generation in DMA mode.
1219 * @param htim TIM Output Compare handle
1220 * @param Channel TIM Channel to be disabled
1221 * This parameter can be one of the following values:
1222 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1223 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1224 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1225 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1226 * @retval HAL status
1227 */
HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1228 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1229 {
1230 HAL_StatusTypeDef status = HAL_OK;
1231
1232 /* Check the parameters */
1233 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1234
1235 switch (Channel)
1236 {
1237 case TIM_CHANNEL_1:
1238 {
1239 /* Disable the TIM Capture/Compare 1 DMA request */
1240 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1241 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1242 break;
1243 }
1244
1245 case TIM_CHANNEL_2:
1246 {
1247 /* Disable the TIM Capture/Compare 2 DMA request */
1248 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1249 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1250 break;
1251 }
1252
1253 case TIM_CHANNEL_3:
1254 {
1255 /* Disable the TIM Capture/Compare 3 DMA request */
1256 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1257 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1258 break;
1259 }
1260
1261 case TIM_CHANNEL_4:
1262 {
1263 /* Disable the TIM Capture/Compare 4 interrupt */
1264 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1265 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1266 break;
1267 }
1268
1269 default:
1270 status = HAL_ERROR;
1271 break;
1272 }
1273
1274 if (status == HAL_OK)
1275 {
1276 /* Disable the Output compare channel */
1277 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1278
1279 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1280 {
1281 /* Disable the Main Output */
1282 __HAL_TIM_MOE_DISABLE(htim);
1283 }
1284
1285 /* Disable the Peripheral */
1286 __HAL_TIM_DISABLE(htim);
1287
1288 /* Set the TIM channel state */
1289 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1290 }
1291
1292 /* Return function status */
1293 return status;
1294 }
1295
1296 /**
1297 * @}
1298 */
1299
1300 /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
1301 * @brief TIM PWM functions
1302 *
1303 @verbatim
1304 ==============================================================================
1305 ##### TIM PWM functions #####
1306 ==============================================================================
1307 [..]
1308 This section provides functions allowing to:
1309 (+) Initialize and configure the TIM PWM.
1310 (+) De-initialize the TIM PWM.
1311 (+) Start the TIM PWM.
1312 (+) Stop the TIM PWM.
1313 (+) Start the TIM PWM and enable interrupt.
1314 (+) Stop the TIM PWM and disable interrupt.
1315 (+) Start the TIM PWM and enable DMA transfer.
1316 (+) Stop the TIM PWM and disable DMA transfer.
1317
1318 @endverbatim
1319 * @{
1320 */
1321 /**
1322 * @brief Initializes the TIM PWM Time Base according to the specified
1323 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1324 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1325 * requires a timer reset to avoid unexpected direction
1326 * due to DIR bit readonly in center aligned mode.
1327 * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
1328 * @param htim TIM PWM handle
1329 * @retval HAL status
1330 */
HAL_TIM_PWM_Init(TIM_HandleTypeDef * htim)1331 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
1332 {
1333 /* Check the TIM handle allocation */
1334 if (htim == NULL)
1335 {
1336 return HAL_ERROR;
1337 }
1338
1339 /* Check the parameters */
1340 assert_param(IS_TIM_INSTANCE(htim->Instance));
1341 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1342 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1343 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1344
1345 if (htim->State == HAL_TIM_STATE_RESET)
1346 {
1347 /* Allocate lock resource and initialize it */
1348 htim->Lock = HAL_UNLOCKED;
1349
1350 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1351 /* Reset interrupt callbacks to legacy weak callbacks */
1352 TIM_ResetCallback(htim);
1353
1354 if (htim->PWM_MspInitCallback == NULL)
1355 {
1356 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
1357 }
1358 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1359 htim->PWM_MspInitCallback(htim);
1360 #else
1361 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1362 HAL_TIM_PWM_MspInit(htim);
1363 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1364 }
1365
1366 /* Set the TIM state */
1367 htim->State = HAL_TIM_STATE_BUSY;
1368
1369 /* Init the base time for the PWM */
1370 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1371
1372 /* Initialize the DMA burst operation state */
1373 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
1374
1375 /* Initialize the TIM channels state */
1376 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1377 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1378
1379 /* Initialize the TIM state*/
1380 htim->State = HAL_TIM_STATE_READY;
1381
1382 return HAL_OK;
1383 }
1384
1385 /**
1386 * @brief DeInitializes the TIM peripheral
1387 * @param htim TIM PWM handle
1388 * @retval HAL status
1389 */
HAL_TIM_PWM_DeInit(TIM_HandleTypeDef * htim)1390 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
1391 {
1392 /* Check the parameters */
1393 assert_param(IS_TIM_INSTANCE(htim->Instance));
1394
1395 htim->State = HAL_TIM_STATE_BUSY;
1396
1397 /* Disable the TIM Peripheral Clock */
1398 __HAL_TIM_DISABLE(htim);
1399
1400 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1401 if (htim->PWM_MspDeInitCallback == NULL)
1402 {
1403 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
1404 }
1405 /* DeInit the low level hardware */
1406 htim->PWM_MspDeInitCallback(htim);
1407 #else
1408 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1409 HAL_TIM_PWM_MspDeInit(htim);
1410 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1411
1412 /* Change the DMA burst operation state */
1413 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
1414
1415 /* Change the TIM channels state */
1416 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1417 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1418
1419 /* Change TIM state */
1420 htim->State = HAL_TIM_STATE_RESET;
1421
1422 /* Release Lock */
1423 __HAL_UNLOCK(htim);
1424
1425 return HAL_OK;
1426 }
1427
1428 /**
1429 * @brief Initializes the TIM PWM MSP.
1430 * @param htim TIM PWM handle
1431 * @retval None
1432 */
HAL_TIM_PWM_MspInit(TIM_HandleTypeDef * htim)1433 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1434 {
1435 /* Prevent unused argument(s) compilation warning */
1436 UNUSED(htim);
1437
1438 /* NOTE : This function should not be modified, when the callback is needed,
1439 the HAL_TIM_PWM_MspInit could be implemented in the user file
1440 */
1441 }
1442
1443 /**
1444 * @brief DeInitializes TIM PWM MSP.
1445 * @param htim TIM PWM handle
1446 * @retval None
1447 */
HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef * htim)1448 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1449 {
1450 /* Prevent unused argument(s) compilation warning */
1451 UNUSED(htim);
1452
1453 /* NOTE : This function should not be modified, when the callback is needed,
1454 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1455 */
1456 }
1457
1458 /**
1459 * @brief Starts the PWM signal generation.
1460 * @param htim TIM handle
1461 * @param Channel TIM Channels to be enabled
1462 * This parameter can be one of the following values:
1463 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1464 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1465 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1466 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1467 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1468 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1469 * @retval HAL status
1470 */
HAL_TIM_PWM_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1471 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1472 {
1473 uint32_t tmpsmcr;
1474
1475 /* Check the parameters */
1476 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1477
1478 /* Check the TIM channel state */
1479 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1480 {
1481 return HAL_ERROR;
1482 }
1483
1484 /* Set the TIM channel state */
1485 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1486
1487 /* Enable the Capture compare channel */
1488 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1489
1490 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1491 {
1492 /* Enable the main output */
1493 __HAL_TIM_MOE_ENABLE(htim);
1494 }
1495
1496 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1497 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1498 {
1499 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1500 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1501 {
1502 __HAL_TIM_ENABLE(htim);
1503 }
1504 }
1505 else
1506 {
1507 __HAL_TIM_ENABLE(htim);
1508 }
1509
1510 /* Return function status */
1511 return HAL_OK;
1512 }
1513
1514 /**
1515 * @brief Stops the PWM signal generation.
1516 * @param htim TIM PWM handle
1517 * @param Channel TIM Channels to be disabled
1518 * This parameter can be one of the following values:
1519 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1520 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1521 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1522 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1523 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1524 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1525 * @retval HAL status
1526 */
HAL_TIM_PWM_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1527 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1528 {
1529 /* Check the parameters */
1530 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1531
1532 /* Disable the Capture compare channel */
1533 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1534
1535 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1536 {
1537 /* Disable the Main Output */
1538 __HAL_TIM_MOE_DISABLE(htim);
1539 }
1540
1541 /* Disable the Peripheral */
1542 __HAL_TIM_DISABLE(htim);
1543
1544 /* Set the TIM channel state */
1545 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1546
1547 /* Return function status */
1548 return HAL_OK;
1549 }
1550
1551 /**
1552 * @brief Starts the PWM signal generation in interrupt mode.
1553 * @param htim TIM PWM handle
1554 * @param Channel TIM Channel to be enabled
1555 * This parameter can be one of the following values:
1556 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1557 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1558 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1559 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1560 * @retval HAL status
1561 */
HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1562 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1563 {
1564 HAL_StatusTypeDef status = HAL_OK;
1565 uint32_t tmpsmcr;
1566
1567 /* Check the parameters */
1568 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1569
1570 /* Check the TIM channel state */
1571 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1572 {
1573 return HAL_ERROR;
1574 }
1575
1576 /* Set the TIM channel state */
1577 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1578
1579 switch (Channel)
1580 {
1581 case TIM_CHANNEL_1:
1582 {
1583 /* Enable the TIM Capture/Compare 1 interrupt */
1584 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1585 break;
1586 }
1587
1588 case TIM_CHANNEL_2:
1589 {
1590 /* Enable the TIM Capture/Compare 2 interrupt */
1591 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1592 break;
1593 }
1594
1595 case TIM_CHANNEL_3:
1596 {
1597 /* Enable the TIM Capture/Compare 3 interrupt */
1598 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1599 break;
1600 }
1601
1602 case TIM_CHANNEL_4:
1603 {
1604 /* Enable the TIM Capture/Compare 4 interrupt */
1605 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1606 break;
1607 }
1608
1609 default:
1610 status = HAL_ERROR;
1611 break;
1612 }
1613
1614 if (status == HAL_OK)
1615 {
1616 /* Enable the Capture compare channel */
1617 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1618
1619 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1620 {
1621 /* Enable the main output */
1622 __HAL_TIM_MOE_ENABLE(htim);
1623 }
1624
1625 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1626 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1627 {
1628 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1629 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1630 {
1631 __HAL_TIM_ENABLE(htim);
1632 }
1633 }
1634 else
1635 {
1636 __HAL_TIM_ENABLE(htim);
1637 }
1638 }
1639
1640 /* Return function status */
1641 return status;
1642 }
1643
1644 /**
1645 * @brief Stops the PWM signal generation in interrupt mode.
1646 * @param htim TIM PWM handle
1647 * @param Channel TIM Channels to be disabled
1648 * This parameter can be one of the following values:
1649 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1650 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1651 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1652 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1653 * @retval HAL status
1654 */
HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1655 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1656 {
1657 HAL_StatusTypeDef status = HAL_OK;
1658
1659 /* Check the parameters */
1660 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1661
1662 switch (Channel)
1663 {
1664 case TIM_CHANNEL_1:
1665 {
1666 /* Disable the TIM Capture/Compare 1 interrupt */
1667 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1668 break;
1669 }
1670
1671 case TIM_CHANNEL_2:
1672 {
1673 /* Disable the TIM Capture/Compare 2 interrupt */
1674 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1675 break;
1676 }
1677
1678 case TIM_CHANNEL_3:
1679 {
1680 /* Disable the TIM Capture/Compare 3 interrupt */
1681 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1682 break;
1683 }
1684
1685 case TIM_CHANNEL_4:
1686 {
1687 /* Disable the TIM Capture/Compare 4 interrupt */
1688 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1689 break;
1690 }
1691
1692 default:
1693 status = HAL_ERROR;
1694 break;
1695 }
1696
1697 if (status == HAL_OK)
1698 {
1699 /* Disable the Capture compare channel */
1700 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1701
1702 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1703 {
1704 /* Disable the Main Output */
1705 __HAL_TIM_MOE_DISABLE(htim);
1706 }
1707
1708 /* Disable the Peripheral */
1709 __HAL_TIM_DISABLE(htim);
1710
1711 /* Set the TIM channel state */
1712 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1713 }
1714
1715 /* Return function status */
1716 return status;
1717 }
1718
1719 /**
1720 * @brief Starts the TIM PWM signal generation in DMA mode.
1721 * @param htim TIM PWM handle
1722 * @param Channel TIM Channels to be enabled
1723 * This parameter can be one of the following values:
1724 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1725 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1726 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1727 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1728 * @param pData The source Buffer address.
1729 * @param Length The length of data to be transferred from memory to TIM peripheral
1730 * @retval HAL status
1731 */
HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)1732 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1733 {
1734 HAL_StatusTypeDef status = HAL_OK;
1735 uint32_t tmpsmcr;
1736
1737 /* Check the parameters */
1738 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1739
1740 /* Set the TIM channel state */
1741 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1742 {
1743 return HAL_BUSY;
1744 }
1745 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1746 {
1747 if ((pData == NULL) && (Length > 0U))
1748 {
1749 return HAL_ERROR;
1750 }
1751 else
1752 {
1753 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1754 }
1755 }
1756 else
1757 {
1758 return HAL_ERROR;
1759 }
1760
1761 switch (Channel)
1762 {
1763 case TIM_CHANNEL_1:
1764 {
1765 /* Set the DMA compare callbacks */
1766 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1767 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1768
1769 /* Set the DMA error callback */
1770 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1771
1772 /* Enable the DMA channel */
1773 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1774 Length) != HAL_OK)
1775 {
1776 /* Return error status */
1777 return HAL_ERROR;
1778 }
1779
1780 /* Enable the TIM Capture/Compare 1 DMA request */
1781 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1782 break;
1783 }
1784
1785 case TIM_CHANNEL_2:
1786 {
1787 /* Set the DMA compare callbacks */
1788 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1789 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1790
1791 /* Set the DMA error callback */
1792 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1793
1794 /* Enable the DMA channel */
1795 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1796 Length) != HAL_OK)
1797 {
1798 /* Return error status */
1799 return HAL_ERROR;
1800 }
1801 /* Enable the TIM Capture/Compare 2 DMA request */
1802 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1803 break;
1804 }
1805
1806 case TIM_CHANNEL_3:
1807 {
1808 /* Set the DMA compare callbacks */
1809 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1810 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1811
1812 /* Set the DMA error callback */
1813 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1814
1815 /* Enable the DMA channel */
1816 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1817 Length) != HAL_OK)
1818 {
1819 /* Return error status */
1820 return HAL_ERROR;
1821 }
1822 /* Enable the TIM Output Capture/Compare 3 request */
1823 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1824 break;
1825 }
1826
1827 case TIM_CHANNEL_4:
1828 {
1829 /* Set the DMA compare callbacks */
1830 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1831 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1832
1833 /* Set the DMA error callback */
1834 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1835
1836 /* Enable the DMA channel */
1837 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1838 Length) != HAL_OK)
1839 {
1840 /* Return error status */
1841 return HAL_ERROR;
1842 }
1843 /* Enable the TIM Capture/Compare 4 DMA request */
1844 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1845 break;
1846 }
1847
1848 default:
1849 status = HAL_ERROR;
1850 break;
1851 }
1852
1853 if (status == HAL_OK)
1854 {
1855 /* Enable the Capture compare channel */
1856 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1857
1858 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1859 {
1860 /* Enable the main output */
1861 __HAL_TIM_MOE_ENABLE(htim);
1862 }
1863
1864 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1865 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1866 {
1867 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1868 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1869 {
1870 __HAL_TIM_ENABLE(htim);
1871 }
1872 }
1873 else
1874 {
1875 __HAL_TIM_ENABLE(htim);
1876 }
1877 }
1878
1879 /* Return function status */
1880 return status;
1881 }
1882
1883 /**
1884 * @brief Stops the TIM PWM signal generation in DMA mode.
1885 * @param htim TIM PWM handle
1886 * @param Channel TIM Channels to be disabled
1887 * This parameter can be one of the following values:
1888 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1889 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1890 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1891 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1892 * @retval HAL status
1893 */
HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1894 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1895 {
1896 HAL_StatusTypeDef status = HAL_OK;
1897
1898 /* Check the parameters */
1899 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1900
1901 switch (Channel)
1902 {
1903 case TIM_CHANNEL_1:
1904 {
1905 /* Disable the TIM Capture/Compare 1 DMA request */
1906 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1907 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1908 break;
1909 }
1910
1911 case TIM_CHANNEL_2:
1912 {
1913 /* Disable the TIM Capture/Compare 2 DMA request */
1914 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1915 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1916 break;
1917 }
1918
1919 case TIM_CHANNEL_3:
1920 {
1921 /* Disable the TIM Capture/Compare 3 DMA request */
1922 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1923 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1924 break;
1925 }
1926
1927 case TIM_CHANNEL_4:
1928 {
1929 /* Disable the TIM Capture/Compare 4 interrupt */
1930 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1931 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1932 break;
1933 }
1934
1935 default:
1936 status = HAL_ERROR;
1937 break;
1938 }
1939
1940 if (status == HAL_OK)
1941 {
1942 /* Disable the Capture compare channel */
1943 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1944
1945 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1946 {
1947 /* Disable the Main Output */
1948 __HAL_TIM_MOE_DISABLE(htim);
1949 }
1950
1951 /* Disable the Peripheral */
1952 __HAL_TIM_DISABLE(htim);
1953
1954 /* Set the TIM channel state */
1955 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1956 }
1957
1958 /* Return function status */
1959 return status;
1960 }
1961
1962 /**
1963 * @}
1964 */
1965
1966 /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
1967 * @brief TIM Input Capture functions
1968 *
1969 @verbatim
1970 ==============================================================================
1971 ##### TIM Input Capture functions #####
1972 ==============================================================================
1973 [..]
1974 This section provides functions allowing to:
1975 (+) Initialize and configure the TIM Input Capture.
1976 (+) De-initialize the TIM Input Capture.
1977 (+) Start the TIM Input Capture.
1978 (+) Stop the TIM Input Capture.
1979 (+) Start the TIM Input Capture and enable interrupt.
1980 (+) Stop the TIM Input Capture and disable interrupt.
1981 (+) Start the TIM Input Capture and enable DMA transfer.
1982 (+) Stop the TIM Input Capture and disable DMA transfer.
1983
1984 @endverbatim
1985 * @{
1986 */
1987 /**
1988 * @brief Initializes the TIM Input Capture Time base according to the specified
1989 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1990 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1991 * requires a timer reset to avoid unexpected direction
1992 * due to DIR bit readonly in center aligned mode.
1993 * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
1994 * @param htim TIM Input Capture handle
1995 * @retval HAL status
1996 */
HAL_TIM_IC_Init(TIM_HandleTypeDef * htim)1997 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
1998 {
1999 /* Check the TIM handle allocation */
2000 if (htim == NULL)
2001 {
2002 return HAL_ERROR;
2003 }
2004
2005 /* Check the parameters */
2006 assert_param(IS_TIM_INSTANCE(htim->Instance));
2007 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2008 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2009 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2010
2011 if (htim->State == HAL_TIM_STATE_RESET)
2012 {
2013 /* Allocate lock resource and initialize it */
2014 htim->Lock = HAL_UNLOCKED;
2015
2016 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2017 /* Reset interrupt callbacks to legacy weak callbacks */
2018 TIM_ResetCallback(htim);
2019
2020 if (htim->IC_MspInitCallback == NULL)
2021 {
2022 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
2023 }
2024 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2025 htim->IC_MspInitCallback(htim);
2026 #else
2027 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2028 HAL_TIM_IC_MspInit(htim);
2029 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2030 }
2031
2032 /* Set the TIM state */
2033 htim->State = HAL_TIM_STATE_BUSY;
2034
2035 /* Init the base time for the input capture */
2036 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2037
2038 /* Initialize the DMA burst operation state */
2039 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2040
2041 /* Initialize the TIM channels state */
2042 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
2043 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
2044
2045 /* Initialize the TIM state*/
2046 htim->State = HAL_TIM_STATE_READY;
2047
2048 return HAL_OK;
2049 }
2050
2051 /**
2052 * @brief DeInitializes the TIM peripheral
2053 * @param htim TIM Input Capture handle
2054 * @retval HAL status
2055 */
HAL_TIM_IC_DeInit(TIM_HandleTypeDef * htim)2056 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
2057 {
2058 /* Check the parameters */
2059 assert_param(IS_TIM_INSTANCE(htim->Instance));
2060
2061 htim->State = HAL_TIM_STATE_BUSY;
2062
2063 /* Disable the TIM Peripheral Clock */
2064 __HAL_TIM_DISABLE(htim);
2065
2066 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2067 if (htim->IC_MspDeInitCallback == NULL)
2068 {
2069 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
2070 }
2071 /* DeInit the low level hardware */
2072 htim->IC_MspDeInitCallback(htim);
2073 #else
2074 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
2075 HAL_TIM_IC_MspDeInit(htim);
2076 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2077
2078 /* Change the DMA burst operation state */
2079 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2080
2081 /* Change the TIM channels state */
2082 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2083 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2084
2085 /* Change TIM state */
2086 htim->State = HAL_TIM_STATE_RESET;
2087
2088 /* Release Lock */
2089 __HAL_UNLOCK(htim);
2090
2091 return HAL_OK;
2092 }
2093
2094 /**
2095 * @brief Initializes the TIM Input Capture MSP.
2096 * @param htim TIM Input Capture handle
2097 * @retval None
2098 */
HAL_TIM_IC_MspInit(TIM_HandleTypeDef * htim)2099 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
2100 {
2101 /* Prevent unused argument(s) compilation warning */
2102 UNUSED(htim);
2103
2104 /* NOTE : This function should not be modified, when the callback is needed,
2105 the HAL_TIM_IC_MspInit could be implemented in the user file
2106 */
2107 }
2108
2109 /**
2110 * @brief DeInitializes TIM Input Capture MSP.
2111 * @param htim TIM handle
2112 * @retval None
2113 */
HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef * htim)2114 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
2115 {
2116 /* Prevent unused argument(s) compilation warning */
2117 UNUSED(htim);
2118
2119 /* NOTE : This function should not be modified, when the callback is needed,
2120 the HAL_TIM_IC_MspDeInit could be implemented in the user file
2121 */
2122 }
2123
2124 /**
2125 * @brief Starts the TIM Input Capture measurement.
2126 * @param htim TIM Input Capture handle
2127 * @param Channel TIM Channels to be enabled
2128 * This parameter can be one of the following values:
2129 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2130 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2131 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2132 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2133 * @retval HAL status
2134 */
HAL_TIM_IC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)2135 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2136 {
2137 uint32_t tmpsmcr;
2138 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2139 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2140
2141 /* Check the parameters */
2142 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2143
2144 /* Check the TIM channel state */
2145 if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2146 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2147 {
2148 return HAL_ERROR;
2149 }
2150
2151 /* Set the TIM channel state */
2152 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2153 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2154
2155 /* Enable the Input Capture channel */
2156 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2157
2158 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2159 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2160 {
2161 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2162 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2163 {
2164 __HAL_TIM_ENABLE(htim);
2165 }
2166 }
2167 else
2168 {
2169 __HAL_TIM_ENABLE(htim);
2170 }
2171
2172 /* Return function status */
2173 return HAL_OK;
2174 }
2175
2176 /**
2177 * @brief Stops the TIM Input Capture measurement.
2178 * @param htim TIM Input Capture handle
2179 * @param Channel TIM Channels to be disabled
2180 * This parameter can be one of the following values:
2181 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2182 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2183 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2184 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2185 * @retval HAL status
2186 */
HAL_TIM_IC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)2187 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2188 {
2189 /* Check the parameters */
2190 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2191
2192 /* Disable the Input Capture channel */
2193 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2194
2195 /* Disable the Peripheral */
2196 __HAL_TIM_DISABLE(htim);
2197
2198 /* Set the TIM channel state */
2199 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2200 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2201
2202 /* Return function status */
2203 return HAL_OK;
2204 }
2205
2206 /**
2207 * @brief Starts the TIM Input Capture measurement in interrupt mode.
2208 * @param htim TIM Input Capture handle
2209 * @param Channel TIM Channels to be enabled
2210 * This parameter can be one of the following values:
2211 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2212 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2213 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2214 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2215 * @retval HAL status
2216 */
HAL_TIM_IC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2217 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2218 {
2219 HAL_StatusTypeDef status = HAL_OK;
2220 uint32_t tmpsmcr;
2221
2222 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2223 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2224
2225 /* Check the parameters */
2226 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2227
2228 /* Check the TIM channel state */
2229 if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2230 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2231 {
2232 return HAL_ERROR;
2233 }
2234
2235 /* Set the TIM channel state */
2236 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2237 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2238
2239 switch (Channel)
2240 {
2241 case TIM_CHANNEL_1:
2242 {
2243 /* Enable the TIM Capture/Compare 1 interrupt */
2244 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2245 break;
2246 }
2247
2248 case TIM_CHANNEL_2:
2249 {
2250 /* Enable the TIM Capture/Compare 2 interrupt */
2251 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2252 break;
2253 }
2254
2255 case TIM_CHANNEL_3:
2256 {
2257 /* Enable the TIM Capture/Compare 3 interrupt */
2258 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
2259 break;
2260 }
2261
2262 case TIM_CHANNEL_4:
2263 {
2264 /* Enable the TIM Capture/Compare 4 interrupt */
2265 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
2266 break;
2267 }
2268
2269 default:
2270 status = HAL_ERROR;
2271 break;
2272 }
2273
2274 if (status == HAL_OK)
2275 {
2276 /* Enable the Input Capture channel */
2277 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2278
2279 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2280 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2281 {
2282 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2283 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2284 {
2285 __HAL_TIM_ENABLE(htim);
2286 }
2287 }
2288 else
2289 {
2290 __HAL_TIM_ENABLE(htim);
2291 }
2292 }
2293
2294 /* Return function status */
2295 return status;
2296 }
2297
2298 /**
2299 * @brief Stops the TIM Input Capture measurement in interrupt mode.
2300 * @param htim TIM Input Capture handle
2301 * @param Channel TIM Channels to be disabled
2302 * This parameter can be one of the following values:
2303 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2304 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2305 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2306 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2307 * @retval HAL status
2308 */
HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2309 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2310 {
2311 HAL_StatusTypeDef status = HAL_OK;
2312
2313 /* Check the parameters */
2314 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2315
2316 switch (Channel)
2317 {
2318 case TIM_CHANNEL_1:
2319 {
2320 /* Disable the TIM Capture/Compare 1 interrupt */
2321 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2322 break;
2323 }
2324
2325 case TIM_CHANNEL_2:
2326 {
2327 /* Disable the TIM Capture/Compare 2 interrupt */
2328 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2329 break;
2330 }
2331
2332 case TIM_CHANNEL_3:
2333 {
2334 /* Disable the TIM Capture/Compare 3 interrupt */
2335 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
2336 break;
2337 }
2338
2339 case TIM_CHANNEL_4:
2340 {
2341 /* Disable the TIM Capture/Compare 4 interrupt */
2342 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
2343 break;
2344 }
2345
2346 default:
2347 status = HAL_ERROR;
2348 break;
2349 }
2350
2351 if (status == HAL_OK)
2352 {
2353 /* Disable the Input Capture channel */
2354 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2355
2356 /* Disable the Peripheral */
2357 __HAL_TIM_DISABLE(htim);
2358
2359 /* Set the TIM channel state */
2360 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2361 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2362 }
2363
2364 /* Return function status */
2365 return status;
2366 }
2367
2368 /**
2369 * @brief Starts the TIM Input Capture measurement in DMA mode.
2370 * @param htim TIM Input Capture handle
2371 * @param Channel TIM Channels to be enabled
2372 * This parameter can be one of the following values:
2373 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2374 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2375 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2376 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2377 * @param pData The destination Buffer address.
2378 * @param Length The length of data to be transferred from TIM peripheral to memory.
2379 * @retval HAL status
2380 */
HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)2381 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
2382 {
2383 HAL_StatusTypeDef status = HAL_OK;
2384 uint32_t tmpsmcr;
2385
2386 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2387 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2388
2389 /* Check the parameters */
2390 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2391 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2392
2393 /* Set the TIM channel state */
2394 if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
2395 || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
2396 {
2397 return HAL_BUSY;
2398 }
2399 else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
2400 && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
2401 {
2402 if ((pData == NULL) && (Length > 0U))
2403 {
2404 return HAL_ERROR;
2405 }
2406 else
2407 {
2408 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2409 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2410 }
2411 }
2412 else
2413 {
2414 return HAL_ERROR;
2415 }
2416
2417 /* Enable the Input Capture channel */
2418 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2419
2420 switch (Channel)
2421 {
2422 case TIM_CHANNEL_1:
2423 {
2424 /* Set the DMA capture callbacks */
2425 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2426 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2427
2428 /* Set the DMA error callback */
2429 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2430
2431 /* Enable the DMA channel */
2432 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
2433 Length) != HAL_OK)
2434 {
2435 /* Return error status */
2436 return HAL_ERROR;
2437 }
2438 /* Enable the TIM Capture/Compare 1 DMA request */
2439 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2440 break;
2441 }
2442
2443 case TIM_CHANNEL_2:
2444 {
2445 /* Set the DMA capture callbacks */
2446 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2447 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2448
2449 /* Set the DMA error callback */
2450 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
2451
2452 /* Enable the DMA channel */
2453 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
2454 Length) != HAL_OK)
2455 {
2456 /* Return error status */
2457 return HAL_ERROR;
2458 }
2459 /* Enable the TIM Capture/Compare 2 DMA request */
2460 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2461 break;
2462 }
2463
2464 case TIM_CHANNEL_3:
2465 {
2466 /* Set the DMA capture callbacks */
2467 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
2468 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2469
2470 /* Set the DMA error callback */
2471 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
2472
2473 /* Enable the DMA channel */
2474 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
2475 Length) != HAL_OK)
2476 {
2477 /* Return error status */
2478 return HAL_ERROR;
2479 }
2480 /* Enable the TIM Capture/Compare 3 DMA request */
2481 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
2482 break;
2483 }
2484
2485 case TIM_CHANNEL_4:
2486 {
2487 /* Set the DMA capture callbacks */
2488 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
2489 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2490
2491 /* Set the DMA error callback */
2492 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
2493
2494 /* Enable the DMA channel */
2495 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
2496 Length) != HAL_OK)
2497 {
2498 /* Return error status */
2499 return HAL_ERROR;
2500 }
2501 /* Enable the TIM Capture/Compare 4 DMA request */
2502 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
2503 break;
2504 }
2505
2506 default:
2507 status = HAL_ERROR;
2508 break;
2509 }
2510
2511 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2512 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2513 {
2514 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2515 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2516 {
2517 __HAL_TIM_ENABLE(htim);
2518 }
2519 }
2520 else
2521 {
2522 __HAL_TIM_ENABLE(htim);
2523 }
2524
2525 /* Return function status */
2526 return status;
2527 }
2528
2529 /**
2530 * @brief Stops the TIM Input Capture measurement in DMA mode.
2531 * @param htim TIM Input Capture handle
2532 * @param Channel TIM Channels to be disabled
2533 * This parameter can be one of the following values:
2534 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2535 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2536 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2537 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2538 * @retval HAL status
2539 */
HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)2540 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2541 {
2542 HAL_StatusTypeDef status = HAL_OK;
2543
2544 /* Check the parameters */
2545 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2546 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2547
2548 /* Disable the Input Capture channel */
2549 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2550
2551 switch (Channel)
2552 {
2553 case TIM_CHANNEL_1:
2554 {
2555 /* Disable the TIM Capture/Compare 1 DMA request */
2556 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2557 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
2558 break;
2559 }
2560
2561 case TIM_CHANNEL_2:
2562 {
2563 /* Disable the TIM Capture/Compare 2 DMA request */
2564 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2565 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
2566 break;
2567 }
2568
2569 case TIM_CHANNEL_3:
2570 {
2571 /* Disable the TIM Capture/Compare 3 DMA request */
2572 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
2573 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
2574 break;
2575 }
2576
2577 case TIM_CHANNEL_4:
2578 {
2579 /* Disable the TIM Capture/Compare 4 DMA request */
2580 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
2581 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
2582 break;
2583 }
2584
2585 default:
2586 status = HAL_ERROR;
2587 break;
2588 }
2589
2590 if (status == HAL_OK)
2591 {
2592 /* Disable the Peripheral */
2593 __HAL_TIM_DISABLE(htim);
2594
2595 /* Set the TIM channel state */
2596 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2597 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2598 }
2599
2600 /* Return function status */
2601 return status;
2602 }
2603 /**
2604 * @}
2605 */
2606
2607 /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
2608 * @brief TIM One Pulse functions
2609 *
2610 @verbatim
2611 ==============================================================================
2612 ##### TIM One Pulse functions #####
2613 ==============================================================================
2614 [..]
2615 This section provides functions allowing to:
2616 (+) Initialize and configure the TIM One Pulse.
2617 (+) De-initialize the TIM One Pulse.
2618 (+) Start the TIM One Pulse.
2619 (+) Stop the TIM One Pulse.
2620 (+) Start the TIM One Pulse and enable interrupt.
2621 (+) Stop the TIM One Pulse and disable interrupt.
2622 (+) Start the TIM One Pulse and enable DMA transfer.
2623 (+) Stop the TIM One Pulse and disable DMA transfer.
2624
2625 @endverbatim
2626 * @{
2627 */
2628 /**
2629 * @brief Initializes the TIM One Pulse Time Base according to the specified
2630 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
2631 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2632 * requires a timer reset to avoid unexpected direction
2633 * due to DIR bit readonly in center aligned mode.
2634 * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
2635 * @note When the timer instance is initialized in One Pulse mode, timer
2636 * channels 1 and channel 2 are reserved and cannot be used for other
2637 * purpose.
2638 * @param htim TIM One Pulse handle
2639 * @param OnePulseMode Select the One pulse mode.
2640 * This parameter can be one of the following values:
2641 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
2642 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
2643 * @retval HAL status
2644 */
HAL_TIM_OnePulse_Init(TIM_HandleTypeDef * htim,uint32_t OnePulseMode)2645 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
2646 {
2647 /* Check the TIM handle allocation */
2648 if (htim == NULL)
2649 {
2650 return HAL_ERROR;
2651 }
2652
2653 /* Check the parameters */
2654 assert_param(IS_TIM_INSTANCE(htim->Instance));
2655 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2656 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2657 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
2658 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2659
2660 if (htim->State == HAL_TIM_STATE_RESET)
2661 {
2662 /* Allocate lock resource and initialize it */
2663 htim->Lock = HAL_UNLOCKED;
2664
2665 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2666 /* Reset interrupt callbacks to legacy weak callbacks */
2667 TIM_ResetCallback(htim);
2668
2669 if (htim->OnePulse_MspInitCallback == NULL)
2670 {
2671 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
2672 }
2673 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2674 htim->OnePulse_MspInitCallback(htim);
2675 #else
2676 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2677 HAL_TIM_OnePulse_MspInit(htim);
2678 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2679 }
2680
2681 /* Set the TIM state */
2682 htim->State = HAL_TIM_STATE_BUSY;
2683
2684 /* Configure the Time base in the One Pulse Mode */
2685 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2686
2687 /* Reset the OPM Bit */
2688 htim->Instance->CR1 &= ~TIM_CR1_OPM;
2689
2690 /* Configure the OPM Mode */
2691 htim->Instance->CR1 |= OnePulseMode;
2692
2693 /* Initialize the DMA burst operation state */
2694 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2695
2696 /* Initialize the TIM channels state */
2697 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2698 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2699 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2700 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2701
2702 /* Initialize the TIM state*/
2703 htim->State = HAL_TIM_STATE_READY;
2704
2705 return HAL_OK;
2706 }
2707
2708 /**
2709 * @brief DeInitializes the TIM One Pulse
2710 * @param htim TIM One Pulse handle
2711 * @retval HAL status
2712 */
HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef * htim)2713 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
2714 {
2715 /* Check the parameters */
2716 assert_param(IS_TIM_INSTANCE(htim->Instance));
2717
2718 htim->State = HAL_TIM_STATE_BUSY;
2719
2720 /* Disable the TIM Peripheral Clock */
2721 __HAL_TIM_DISABLE(htim);
2722
2723 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2724 if (htim->OnePulse_MspDeInitCallback == NULL)
2725 {
2726 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
2727 }
2728 /* DeInit the low level hardware */
2729 htim->OnePulse_MspDeInitCallback(htim);
2730 #else
2731 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2732 HAL_TIM_OnePulse_MspDeInit(htim);
2733 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2734
2735 /* Change the DMA burst operation state */
2736 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2737
2738 /* Set the TIM channel state */
2739 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2740 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2741 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2742 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2743
2744 /* Change TIM state */
2745 htim->State = HAL_TIM_STATE_RESET;
2746
2747 /* Release Lock */
2748 __HAL_UNLOCK(htim);
2749
2750 return HAL_OK;
2751 }
2752
2753 /**
2754 * @brief Initializes the TIM One Pulse MSP.
2755 * @param htim TIM One Pulse handle
2756 * @retval None
2757 */
HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef * htim)2758 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
2759 {
2760 /* Prevent unused argument(s) compilation warning */
2761 UNUSED(htim);
2762
2763 /* NOTE : This function should not be modified, when the callback is needed,
2764 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
2765 */
2766 }
2767
2768 /**
2769 * @brief DeInitializes TIM One Pulse MSP.
2770 * @param htim TIM One Pulse handle
2771 * @retval None
2772 */
HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef * htim)2773 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
2774 {
2775 /* Prevent unused argument(s) compilation warning */
2776 UNUSED(htim);
2777
2778 /* NOTE : This function should not be modified, when the callback is needed,
2779 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2780 */
2781 }
2782
2783 /**
2784 * @brief Starts the TIM One Pulse signal generation.
2785 * @note Though OutputChannel parameter is deprecated and ignored by the function
2786 * it has been kept to avoid HAL_TIM API compatibility break.
2787 * @note The pulse output channel is determined when calling
2788 * @ref HAL_TIM_OnePulse_ConfigChannel().
2789 * @param htim TIM One Pulse handle
2790 * @param OutputChannel See note above
2791 * @retval HAL status
2792 */
HAL_TIM_OnePulse_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2793 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2794 {
2795 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2796 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2797 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2798 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2799
2800 /* Prevent unused argument(s) compilation warning */
2801 UNUSED(OutputChannel);
2802
2803 /* Check the TIM channels state */
2804 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2805 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2806 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2807 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2808 {
2809 return HAL_ERROR;
2810 }
2811
2812 /* Set the TIM channels state */
2813 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2814 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2815 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2816 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2817
2818 /* Enable the Capture compare and the Input Capture channels
2819 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2820 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2821 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2822 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2823
2824 No need to enable the counter, it's enabled automatically by hardware
2825 (the counter starts in response to a stimulus and generate a pulse */
2826
2827 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2828 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2829
2830 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2831 {
2832 /* Enable the main output */
2833 __HAL_TIM_MOE_ENABLE(htim);
2834 }
2835
2836 /* Return function status */
2837 return HAL_OK;
2838 }
2839
2840 /**
2841 * @brief Stops the TIM One Pulse signal generation.
2842 * @note Though OutputChannel parameter is deprecated and ignored by the function
2843 * it has been kept to avoid HAL_TIM API compatibility break.
2844 * @note The pulse output channel is determined when calling
2845 * @ref HAL_TIM_OnePulse_ConfigChannel().
2846 * @param htim TIM One Pulse handle
2847 * @param OutputChannel See note above
2848 * @retval HAL status
2849 */
HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2850 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2851 {
2852 /* Prevent unused argument(s) compilation warning */
2853 UNUSED(OutputChannel);
2854
2855 /* Disable the Capture compare and the Input Capture channels
2856 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2857 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2858 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2859 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2860
2861 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2862 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2863
2864 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2865 {
2866 /* Disable the Main Output */
2867 __HAL_TIM_MOE_DISABLE(htim);
2868 }
2869
2870 /* Disable the Peripheral */
2871 __HAL_TIM_DISABLE(htim);
2872
2873 /* Set the TIM channels state */
2874 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2875 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2876 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2877 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2878
2879 /* Return function status */
2880 return HAL_OK;
2881 }
2882
2883 /**
2884 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2885 * @note Though OutputChannel parameter is deprecated and ignored by the function
2886 * it has been kept to avoid HAL_TIM API compatibility break.
2887 * @note The pulse output channel is determined when calling
2888 * @ref HAL_TIM_OnePulse_ConfigChannel().
2889 * @param htim TIM One Pulse handle
2890 * @param OutputChannel See note above
2891 * @retval HAL status
2892 */
HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2893 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2894 {
2895 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2896 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2897 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2898 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2899
2900 /* Prevent unused argument(s) compilation warning */
2901 UNUSED(OutputChannel);
2902
2903 /* Check the TIM channels state */
2904 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2905 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2906 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2907 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2908 {
2909 return HAL_ERROR;
2910 }
2911
2912 /* Set the TIM channels state */
2913 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2914 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2915 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2916 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2917
2918 /* Enable the Capture compare and the Input Capture channels
2919 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2920 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2921 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2922 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2923
2924 No need to enable the counter, it's enabled automatically by hardware
2925 (the counter starts in response to a stimulus and generate a pulse */
2926
2927 /* Enable the TIM Capture/Compare 1 interrupt */
2928 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2929
2930 /* Enable the TIM Capture/Compare 2 interrupt */
2931 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2932
2933 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2934 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2935
2936 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2937 {
2938 /* Enable the main output */
2939 __HAL_TIM_MOE_ENABLE(htim);
2940 }
2941
2942 /* Return function status */
2943 return HAL_OK;
2944 }
2945
2946 /**
2947 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2948 * @note Though OutputChannel parameter is deprecated and ignored by the function
2949 * it has been kept to avoid HAL_TIM API compatibility break.
2950 * @note The pulse output channel is determined when calling
2951 * @ref HAL_TIM_OnePulse_ConfigChannel().
2952 * @param htim TIM One Pulse handle
2953 * @param OutputChannel See note above
2954 * @retval HAL status
2955 */
HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2956 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2957 {
2958 /* Prevent unused argument(s) compilation warning */
2959 UNUSED(OutputChannel);
2960
2961 /* Disable the TIM Capture/Compare 1 interrupt */
2962 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2963
2964 /* Disable the TIM Capture/Compare 2 interrupt */
2965 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2966
2967 /* Disable the Capture compare and the Input Capture channels
2968 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2969 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2970 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2971 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2972 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2973 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2974
2975 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2976 {
2977 /* Disable the Main Output */
2978 __HAL_TIM_MOE_DISABLE(htim);
2979 }
2980
2981 /* Disable the Peripheral */
2982 __HAL_TIM_DISABLE(htim);
2983
2984 /* Set the TIM channels state */
2985 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2986 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2987 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2988 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2989
2990 /* Return function status */
2991 return HAL_OK;
2992 }
2993
2994 /**
2995 * @}
2996 */
2997
2998 /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
2999 * @brief TIM Encoder functions
3000 *
3001 @verbatim
3002 ==============================================================================
3003 ##### TIM Encoder functions #####
3004 ==============================================================================
3005 [..]
3006 This section provides functions allowing to:
3007 (+) Initialize and configure the TIM Encoder.
3008 (+) De-initialize the TIM Encoder.
3009 (+) Start the TIM Encoder.
3010 (+) Stop the TIM Encoder.
3011 (+) Start the TIM Encoder and enable interrupt.
3012 (+) Stop the TIM Encoder and disable interrupt.
3013 (+) Start the TIM Encoder and enable DMA transfer.
3014 (+) Stop the TIM Encoder and disable DMA transfer.
3015
3016 @endverbatim
3017 * @{
3018 */
3019 /**
3020 * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
3021 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
3022 * requires a timer reset to avoid unexpected direction
3023 * due to DIR bit readonly in center aligned mode.
3024 * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
3025 * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
3026 * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
3027 * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
3028 * @note When the timer instance is initialized in Encoder mode, timer
3029 * channels 1 and channel 2 are reserved and cannot be used for other
3030 * purpose.
3031 * @param htim TIM Encoder Interface handle
3032 * @param sConfig TIM Encoder Interface configuration structure
3033 * @retval HAL status
3034 */
HAL_TIM_Encoder_Init(TIM_HandleTypeDef * htim,TIM_Encoder_InitTypeDef * sConfig)3035 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
3036 {
3037 uint32_t tmpsmcr;
3038 uint32_t tmpccmr1;
3039 uint32_t tmpccer;
3040
3041 /* Check the TIM handle allocation */
3042 if (htim == NULL)
3043 {
3044 return HAL_ERROR;
3045 }
3046
3047 /* Check the parameters */
3048 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3049 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
3050 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
3051 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
3052 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
3053 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
3054 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
3055 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
3056 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
3057 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
3058 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
3059 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
3060 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
3061
3062 if (htim->State == HAL_TIM_STATE_RESET)
3063 {
3064 /* Allocate lock resource and initialize it */
3065 htim->Lock = HAL_UNLOCKED;
3066
3067 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3068 /* Reset interrupt callbacks to legacy weak callbacks */
3069 TIM_ResetCallback(htim);
3070
3071 if (htim->Encoder_MspInitCallback == NULL)
3072 {
3073 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
3074 }
3075 /* Init the low level hardware : GPIO, CLOCK, NVIC */
3076 htim->Encoder_MspInitCallback(htim);
3077 #else
3078 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
3079 HAL_TIM_Encoder_MspInit(htim);
3080 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3081 }
3082
3083 /* Set the TIM state */
3084 htim->State = HAL_TIM_STATE_BUSY;
3085
3086 /* Reset the SMS and ECE bits */
3087 htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
3088
3089 /* Configure the Time base in the Encoder Mode */
3090 TIM_Base_SetConfig(htim->Instance, &htim->Init);
3091
3092 /* Get the TIMx SMCR register value */
3093 tmpsmcr = htim->Instance->SMCR;
3094
3095 /* Get the TIMx CCMR1 register value */
3096 tmpccmr1 = htim->Instance->CCMR1;
3097
3098 /* Get the TIMx CCER register value */
3099 tmpccer = htim->Instance->CCER;
3100
3101 /* Set the encoder Mode */
3102 tmpsmcr |= sConfig->EncoderMode;
3103
3104 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
3105 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
3106 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
3107
3108 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
3109 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
3110 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
3111 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
3112 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
3113
3114 /* Set the TI1 and the TI2 Polarities */
3115 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
3116 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
3117 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
3118
3119 /* Write to TIMx SMCR */
3120 htim->Instance->SMCR = tmpsmcr;
3121
3122 /* Write to TIMx CCMR1 */
3123 htim->Instance->CCMR1 = tmpccmr1;
3124
3125 /* Write to TIMx CCER */
3126 htim->Instance->CCER = tmpccer;
3127
3128 /* Initialize the DMA burst operation state */
3129 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
3130
3131 /* Set the TIM channels state */
3132 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3133 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3134 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3135 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3136
3137 /* Initialize the TIM state*/
3138 htim->State = HAL_TIM_STATE_READY;
3139
3140 return HAL_OK;
3141 }
3142
3143
3144 /**
3145 * @brief DeInitializes the TIM Encoder interface
3146 * @param htim TIM Encoder Interface handle
3147 * @retval HAL status
3148 */
HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef * htim)3149 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
3150 {
3151 /* Check the parameters */
3152 assert_param(IS_TIM_INSTANCE(htim->Instance));
3153
3154 htim->State = HAL_TIM_STATE_BUSY;
3155
3156 /* Disable the TIM Peripheral Clock */
3157 __HAL_TIM_DISABLE(htim);
3158
3159 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3160 if (htim->Encoder_MspDeInitCallback == NULL)
3161 {
3162 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
3163 }
3164 /* DeInit the low level hardware */
3165 htim->Encoder_MspDeInitCallback(htim);
3166 #else
3167 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
3168 HAL_TIM_Encoder_MspDeInit(htim);
3169 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3170
3171 /* Change the DMA burst operation state */
3172 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
3173
3174 /* Set the TIM channels state */
3175 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3176 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3177 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3178 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3179
3180 /* Change TIM state */
3181 htim->State = HAL_TIM_STATE_RESET;
3182
3183 /* Release Lock */
3184 __HAL_UNLOCK(htim);
3185
3186 return HAL_OK;
3187 }
3188
3189 /**
3190 * @brief Initializes the TIM Encoder Interface MSP.
3191 * @param htim TIM Encoder Interface handle
3192 * @retval None
3193 */
HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef * htim)3194 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
3195 {
3196 /* Prevent unused argument(s) compilation warning */
3197 UNUSED(htim);
3198
3199 /* NOTE : This function should not be modified, when the callback is needed,
3200 the HAL_TIM_Encoder_MspInit could be implemented in the user file
3201 */
3202 }
3203
3204 /**
3205 * @brief DeInitializes TIM Encoder Interface MSP.
3206 * @param htim TIM Encoder Interface handle
3207 * @retval None
3208 */
HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef * htim)3209 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
3210 {
3211 /* Prevent unused argument(s) compilation warning */
3212 UNUSED(htim);
3213
3214 /* NOTE : This function should not be modified, when the callback is needed,
3215 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
3216 */
3217 }
3218
3219 /**
3220 * @brief Starts the TIM Encoder Interface.
3221 * @param htim TIM Encoder Interface handle
3222 * @param Channel TIM Channels to be enabled
3223 * This parameter can be one of the following values:
3224 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3225 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3226 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3227 * @retval HAL status
3228 */
HAL_TIM_Encoder_Start(TIM_HandleTypeDef * htim,uint32_t Channel)3229 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
3230 {
3231 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3232 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3233 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3234 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3235
3236 /* Check the parameters */
3237 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3238
3239 /* Set the TIM channel(s) state */
3240 if (Channel == TIM_CHANNEL_1)
3241 {
3242 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3243 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3244 {
3245 return HAL_ERROR;
3246 }
3247 else
3248 {
3249 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3250 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3251 }
3252 }
3253 else if (Channel == TIM_CHANNEL_2)
3254 {
3255 if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3256 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3257 {
3258 return HAL_ERROR;
3259 }
3260 else
3261 {
3262 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3263 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3264 }
3265 }
3266 else
3267 {
3268 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3269 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3270 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3271 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3272 {
3273 return HAL_ERROR;
3274 }
3275 else
3276 {
3277 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3278 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3279 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3280 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3281 }
3282 }
3283
3284 /* Enable the encoder interface channels */
3285 switch (Channel)
3286 {
3287 case TIM_CHANNEL_1:
3288 {
3289 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3290 break;
3291 }
3292
3293 case TIM_CHANNEL_2:
3294 {
3295 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3296 break;
3297 }
3298
3299 default :
3300 {
3301 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3302 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3303 break;
3304 }
3305 }
3306 /* Enable the Peripheral */
3307 __HAL_TIM_ENABLE(htim);
3308
3309 /* Return function status */
3310 return HAL_OK;
3311 }
3312
3313 /**
3314 * @brief Stops the TIM Encoder Interface.
3315 * @param htim TIM Encoder Interface handle
3316 * @param Channel TIM Channels to be disabled
3317 * This parameter can be one of the following values:
3318 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3319 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3320 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3321 * @retval HAL status
3322 */
HAL_TIM_Encoder_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)3323 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
3324 {
3325 /* Check the parameters */
3326 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3327
3328 /* Disable the Input Capture channels 1 and 2
3329 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3330 switch (Channel)
3331 {
3332 case TIM_CHANNEL_1:
3333 {
3334 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3335 break;
3336 }
3337
3338 case TIM_CHANNEL_2:
3339 {
3340 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3341 break;
3342 }
3343
3344 default :
3345 {
3346 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3347 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3348 break;
3349 }
3350 }
3351
3352 /* Disable the Peripheral */
3353 __HAL_TIM_DISABLE(htim);
3354
3355 /* Set the TIM channel(s) state */
3356 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3357 {
3358 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3359 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3360 }
3361 else
3362 {
3363 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3364 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3365 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3366 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3367 }
3368
3369 /* Return function status */
3370 return HAL_OK;
3371 }
3372
3373 /**
3374 * @brief Starts the TIM Encoder Interface in interrupt mode.
3375 * @param htim TIM Encoder Interface handle
3376 * @param Channel TIM Channels to be enabled
3377 * This parameter can be one of the following values:
3378 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3379 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3380 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3381 * @retval HAL status
3382 */
HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3383 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3384 {
3385 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3386 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3387 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3388 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3389
3390 /* Check the parameters */
3391 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3392
3393 /* Set the TIM channel(s) state */
3394 if (Channel == TIM_CHANNEL_1)
3395 {
3396 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3397 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3398 {
3399 return HAL_ERROR;
3400 }
3401 else
3402 {
3403 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3404 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3405 }
3406 }
3407 else if (Channel == TIM_CHANNEL_2)
3408 {
3409 if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3410 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3411 {
3412 return HAL_ERROR;
3413 }
3414 else
3415 {
3416 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3417 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3418 }
3419 }
3420 else
3421 {
3422 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3423 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3424 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3425 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3426 {
3427 return HAL_ERROR;
3428 }
3429 else
3430 {
3431 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3432 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3433 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3434 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3435 }
3436 }
3437
3438 /* Enable the encoder interface channels */
3439 /* Enable the capture compare Interrupts 1 and/or 2 */
3440 switch (Channel)
3441 {
3442 case TIM_CHANNEL_1:
3443 {
3444 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3445 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3446 break;
3447 }
3448
3449 case TIM_CHANNEL_2:
3450 {
3451 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3452 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3453 break;
3454 }
3455
3456 default :
3457 {
3458 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3459 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3460 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3461 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3462 break;
3463 }
3464 }
3465
3466 /* Enable the Peripheral */
3467 __HAL_TIM_ENABLE(htim);
3468
3469 /* Return function status */
3470 return HAL_OK;
3471 }
3472
3473 /**
3474 * @brief Stops the TIM Encoder Interface in interrupt mode.
3475 * @param htim TIM Encoder Interface handle
3476 * @param Channel TIM Channels to be disabled
3477 * This parameter can be one of the following values:
3478 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3479 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3480 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3481 * @retval HAL status
3482 */
HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3483 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3484 {
3485 /* Check the parameters */
3486 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3487
3488 /* Disable the Input Capture channels 1 and 2
3489 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3490 if (Channel == TIM_CHANNEL_1)
3491 {
3492 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3493
3494 /* Disable the capture compare Interrupts 1 */
3495 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3496 }
3497 else if (Channel == TIM_CHANNEL_2)
3498 {
3499 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3500
3501 /* Disable the capture compare Interrupts 2 */
3502 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3503 }
3504 else
3505 {
3506 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3507 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3508
3509 /* Disable the capture compare Interrupts 1 and 2 */
3510 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3511 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3512 }
3513
3514 /* Disable the Peripheral */
3515 __HAL_TIM_DISABLE(htim);
3516
3517 /* Set the TIM channel(s) state */
3518 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3519 {
3520 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3521 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3522 }
3523 else
3524 {
3525 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3526 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3527 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3528 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3529 }
3530
3531 /* Return function status */
3532 return HAL_OK;
3533 }
3534
3535 /**
3536 * @brief Starts the TIM Encoder Interface in DMA mode.
3537 * @param htim TIM Encoder Interface handle
3538 * @param Channel TIM Channels to be enabled
3539 * This parameter can be one of the following values:
3540 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3541 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3542 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3543 * @param pData1 The destination Buffer address for IC1.
3544 * @param pData2 The destination Buffer address for IC2.
3545 * @param Length The length of data to be transferred from TIM peripheral to memory.
3546 * @retval HAL status
3547 */
HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData1,uint32_t * pData2,uint16_t Length)3548 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
3549 uint32_t *pData2, uint16_t Length)
3550 {
3551 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3552 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3553 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3554 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3555
3556 /* Check the parameters */
3557 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3558
3559 /* Set the TIM channel(s) state */
3560 if (Channel == TIM_CHANNEL_1)
3561 {
3562 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3563 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
3564 {
3565 return HAL_BUSY;
3566 }
3567 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3568 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
3569 {
3570 if ((pData1 == NULL) && (Length > 0U))
3571 {
3572 return HAL_ERROR;
3573 }
3574 else
3575 {
3576 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3577 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3578 }
3579 }
3580 else
3581 {
3582 return HAL_ERROR;
3583 }
3584 }
3585 else if (Channel == TIM_CHANNEL_2)
3586 {
3587 if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3588 || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3589 {
3590 return HAL_BUSY;
3591 }
3592 else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3593 && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3594 {
3595 if ((pData2 == NULL) && (Length > 0U))
3596 {
3597 return HAL_ERROR;
3598 }
3599 else
3600 {
3601 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3602 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3603 }
3604 }
3605 else
3606 {
3607 return HAL_ERROR;
3608 }
3609 }
3610 else
3611 {
3612 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3613 || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3614 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3615 || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3616 {
3617 return HAL_BUSY;
3618 }
3619 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3620 && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3621 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3622 && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3623 {
3624 if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
3625 {
3626 return HAL_ERROR;
3627 }
3628 else
3629 {
3630 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3631 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3632 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3633 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3634 }
3635 }
3636 else
3637 {
3638 return HAL_ERROR;
3639 }
3640 }
3641
3642 switch (Channel)
3643 {
3644 case TIM_CHANNEL_1:
3645 {
3646 /* Set the DMA capture callbacks */
3647 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3648 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3649
3650 /* Set the DMA error callback */
3651 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3652
3653 /* Enable the DMA channel */
3654 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3655 Length) != HAL_OK)
3656 {
3657 /* Return error status */
3658 return HAL_ERROR;
3659 }
3660 /* Enable the TIM Input Capture DMA request */
3661 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3662
3663 /* Enable the Capture compare channel */
3664 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3665
3666 /* Enable the Peripheral */
3667 __HAL_TIM_ENABLE(htim);
3668
3669 break;
3670 }
3671
3672 case TIM_CHANNEL_2:
3673 {
3674 /* Set the DMA capture callbacks */
3675 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3676 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3677
3678 /* Set the DMA error callback */
3679 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
3680 /* Enable the DMA channel */
3681 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3682 Length) != HAL_OK)
3683 {
3684 /* Return error status */
3685 return HAL_ERROR;
3686 }
3687 /* Enable the TIM Input Capture DMA request */
3688 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3689
3690 /* Enable the Capture compare channel */
3691 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3692
3693 /* Enable the Peripheral */
3694 __HAL_TIM_ENABLE(htim);
3695
3696 break;
3697 }
3698
3699 default:
3700 {
3701 /* Set the DMA capture callbacks */
3702 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3703 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3704
3705 /* Set the DMA error callback */
3706 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3707
3708 /* Enable the DMA channel */
3709 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3710 Length) != HAL_OK)
3711 {
3712 /* Return error status */
3713 return HAL_ERROR;
3714 }
3715
3716 /* Set the DMA capture callbacks */
3717 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3718 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3719
3720 /* Set the DMA error callback */
3721 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3722
3723 /* Enable the DMA channel */
3724 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3725 Length) != HAL_OK)
3726 {
3727 /* Return error status */
3728 return HAL_ERROR;
3729 }
3730
3731 /* Enable the TIM Input Capture DMA request */
3732 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3733 /* Enable the TIM Input Capture DMA request */
3734 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3735
3736 /* Enable the Capture compare channel */
3737 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3738 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3739
3740 /* Enable the Peripheral */
3741 __HAL_TIM_ENABLE(htim);
3742
3743 break;
3744 }
3745 }
3746
3747 /* Return function status */
3748 return HAL_OK;
3749 }
3750
3751 /**
3752 * @brief Stops the TIM Encoder Interface in DMA mode.
3753 * @param htim TIM Encoder Interface handle
3754 * @param Channel TIM Channels to be enabled
3755 * This parameter can be one of the following values:
3756 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3757 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3758 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3759 * @retval HAL status
3760 */
HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)3761 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
3762 {
3763 /* Check the parameters */
3764 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3765
3766 /* Disable the Input Capture channels 1 and 2
3767 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3768 if (Channel == TIM_CHANNEL_1)
3769 {
3770 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3771
3772 /* Disable the capture compare DMA Request 1 */
3773 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3774 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3775 }
3776 else if (Channel == TIM_CHANNEL_2)
3777 {
3778 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3779
3780 /* Disable the capture compare DMA Request 2 */
3781 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3782 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3783 }
3784 else
3785 {
3786 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3787 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3788
3789 /* Disable the capture compare DMA Request 1 and 2 */
3790 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3791 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3792 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3793 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3794 }
3795
3796 /* Disable the Peripheral */
3797 __HAL_TIM_DISABLE(htim);
3798
3799 /* Set the TIM channel(s) state */
3800 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3801 {
3802 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3803 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3804 }
3805 else
3806 {
3807 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3808 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3809 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3810 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3811 }
3812
3813 /* Return function status */
3814 return HAL_OK;
3815 }
3816
3817 /**
3818 * @}
3819 */
3820 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
3821 * @brief TIM IRQ handler management
3822 *
3823 @verbatim
3824 ==============================================================================
3825 ##### IRQ handler management #####
3826 ==============================================================================
3827 [..]
3828 This section provides Timer IRQ handler function.
3829
3830 @endverbatim
3831 * @{
3832 */
3833 /**
3834 * @brief This function handles TIM interrupts requests.
3835 * @param htim TIM handle
3836 * @retval None
3837 */
HAL_TIM_IRQHandler(TIM_HandleTypeDef * htim)3838 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
3839 {
3840 /* Capture compare 1 event */
3841 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
3842 {
3843 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
3844 {
3845 {
3846 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
3847 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3848
3849 /* Input capture event */
3850 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
3851 {
3852 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3853 htim->IC_CaptureCallback(htim);
3854 #else
3855 HAL_TIM_IC_CaptureCallback(htim);
3856 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3857 }
3858 /* Output compare event */
3859 else
3860 {
3861 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3862 htim->OC_DelayElapsedCallback(htim);
3863 htim->PWM_PulseFinishedCallback(htim);
3864 #else
3865 HAL_TIM_OC_DelayElapsedCallback(htim);
3866 HAL_TIM_PWM_PulseFinishedCallback(htim);
3867 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3868 }
3869 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3870 }
3871 }
3872 }
3873 /* Capture compare 2 event */
3874 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
3875 {
3876 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
3877 {
3878 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
3879 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3880 /* Input capture event */
3881 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
3882 {
3883 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3884 htim->IC_CaptureCallback(htim);
3885 #else
3886 HAL_TIM_IC_CaptureCallback(htim);
3887 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3888 }
3889 /* Output compare event */
3890 else
3891 {
3892 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3893 htim->OC_DelayElapsedCallback(htim);
3894 htim->PWM_PulseFinishedCallback(htim);
3895 #else
3896 HAL_TIM_OC_DelayElapsedCallback(htim);
3897 HAL_TIM_PWM_PulseFinishedCallback(htim);
3898 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3899 }
3900 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3901 }
3902 }
3903 /* Capture compare 3 event */
3904 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
3905 {
3906 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
3907 {
3908 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
3909 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3910 /* Input capture event */
3911 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
3912 {
3913 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3914 htim->IC_CaptureCallback(htim);
3915 #else
3916 HAL_TIM_IC_CaptureCallback(htim);
3917 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3918 }
3919 /* Output compare event */
3920 else
3921 {
3922 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3923 htim->OC_DelayElapsedCallback(htim);
3924 htim->PWM_PulseFinishedCallback(htim);
3925 #else
3926 HAL_TIM_OC_DelayElapsedCallback(htim);
3927 HAL_TIM_PWM_PulseFinishedCallback(htim);
3928 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3929 }
3930 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3931 }
3932 }
3933 /* Capture compare 4 event */
3934 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
3935 {
3936 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
3937 {
3938 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
3939 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3940 /* Input capture event */
3941 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
3942 {
3943 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3944 htim->IC_CaptureCallback(htim);
3945 #else
3946 HAL_TIM_IC_CaptureCallback(htim);
3947 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3948 }
3949 /* Output compare event */
3950 else
3951 {
3952 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3953 htim->OC_DelayElapsedCallback(htim);
3954 htim->PWM_PulseFinishedCallback(htim);
3955 #else
3956 HAL_TIM_OC_DelayElapsedCallback(htim);
3957 HAL_TIM_PWM_PulseFinishedCallback(htim);
3958 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3959 }
3960 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3961 }
3962 }
3963 /* TIM Update event */
3964 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
3965 {
3966 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
3967 {
3968 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
3969 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3970 htim->PeriodElapsedCallback(htim);
3971 #else
3972 HAL_TIM_PeriodElapsedCallback(htim);
3973 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3974 }
3975 }
3976 /* TIM Break input event */
3977 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
3978 {
3979 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
3980 {
3981 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
3982 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3983 htim->BreakCallback(htim);
3984 #else
3985 HAL_TIMEx_BreakCallback(htim);
3986 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3987 }
3988 }
3989 /* TIM Break2 input event */
3990 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
3991 {
3992 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
3993 {
3994 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
3995 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3996 htim->Break2Callback(htim);
3997 #else
3998 HAL_TIMEx_Break2Callback(htim);
3999 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4000 }
4001 }
4002 /* TIM Trigger detection event */
4003 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
4004 {
4005 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
4006 {
4007 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
4008 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4009 htim->TriggerCallback(htim);
4010 #else
4011 HAL_TIM_TriggerCallback(htim);
4012 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4013 }
4014 }
4015 /* TIM commutation event */
4016 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
4017 {
4018 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
4019 {
4020 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
4021 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4022 htim->CommutationCallback(htim);
4023 #else
4024 HAL_TIMEx_CommutCallback(htim);
4025 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4026 }
4027 }
4028 /* TIM Encoder index event */
4029 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_IDX) != RESET)
4030 {
4031 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_IDX) != RESET)
4032 {
4033 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_IDX);
4034 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4035 htim->EncoderIndexCallback(htim);
4036 #else
4037 HAL_TIMEx_EncoderIndexCallback(htim);
4038 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4039 }
4040 }
4041 /* TIM Direction change event */
4042 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_DIR) != RESET)
4043 {
4044 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_DIR) != RESET)
4045 {
4046 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_DIR);
4047 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4048 htim->DirectionChangeCallback(htim);
4049 #else
4050 HAL_TIMEx_DirectionChangeCallback(htim);
4051 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4052 }
4053 }
4054 /* TIM Index error event */
4055 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_IERR) != RESET)
4056 {
4057 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_IERR) != RESET)
4058 {
4059 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_IERR);
4060 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4061 htim->IndexErrorCallback(htim);
4062 #else
4063 HAL_TIMEx_IndexErrorCallback(htim);
4064 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4065 }
4066 }
4067 /* TIM Transition error event */
4068 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TERR) != RESET)
4069 {
4070 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TERR) != RESET)
4071 {
4072 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_TERR);
4073 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4074 htim->TransitionErrorCallback(htim);
4075 #else
4076 HAL_TIMEx_TransitionErrorCallback(htim);
4077 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4078 }
4079 }
4080 }
4081
4082 /**
4083 * @}
4084 */
4085
4086 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
4087 * @brief TIM Peripheral Control functions
4088 *
4089 @verbatim
4090 ==============================================================================
4091 ##### Peripheral Control functions #####
4092 ==============================================================================
4093 [..]
4094 This section provides functions allowing to:
4095 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
4096 (+) Configure External Clock source.
4097 (+) Configure Complementary channels, break features and dead time.
4098 (+) Configure Master and the Slave synchronization.
4099 (+) Configure the DMA Burst Mode.
4100
4101 @endverbatim
4102 * @{
4103 */
4104
4105 /**
4106 * @brief Initializes the TIM Output Compare Channels according to the specified
4107 * parameters in the TIM_OC_InitTypeDef.
4108 * @param htim TIM Output Compare handle
4109 * @param sConfig TIM Output Compare configuration structure
4110 * @param Channel TIM Channels to configure
4111 * This parameter can be one of the following values:
4112 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4113 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4114 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4115 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4116 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
4117 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
4118 * @retval HAL status
4119 */
HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OC_InitTypeDef * sConfig,uint32_t Channel)4120 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
4121 TIM_OC_InitTypeDef *sConfig,
4122 uint32_t Channel)
4123 {
4124 HAL_StatusTypeDef status = HAL_OK;
4125
4126 /* Check the parameters */
4127 assert_param(IS_TIM_CHANNELS(Channel));
4128 assert_param(IS_TIM_OC_CHANNEL_MODE(sConfig->OCMode, Channel));
4129 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4130
4131 /* Process Locked */
4132 __HAL_LOCK(htim);
4133
4134 switch (Channel)
4135 {
4136 case TIM_CHANNEL_1:
4137 {
4138 /* Check the parameters */
4139 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4140
4141 /* Configure the TIM Channel 1 in Output Compare */
4142 TIM_OC1_SetConfig(htim->Instance, sConfig);
4143 break;
4144 }
4145
4146 case TIM_CHANNEL_2:
4147 {
4148 /* Check the parameters */
4149 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4150
4151 /* Configure the TIM Channel 2 in Output Compare */
4152 TIM_OC2_SetConfig(htim->Instance, sConfig);
4153 break;
4154 }
4155
4156 case TIM_CHANNEL_3:
4157 {
4158 /* Check the parameters */
4159 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4160
4161 /* Configure the TIM Channel 3 in Output Compare */
4162 TIM_OC3_SetConfig(htim->Instance, sConfig);
4163 break;
4164 }
4165
4166 case TIM_CHANNEL_4:
4167 {
4168 /* Check the parameters */
4169 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4170
4171 /* Configure the TIM Channel 4 in Output Compare */
4172 TIM_OC4_SetConfig(htim->Instance, sConfig);
4173 break;
4174 }
4175
4176 case TIM_CHANNEL_5:
4177 {
4178 /* Check the parameters */
4179 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
4180
4181 /* Configure the TIM Channel 5 in Output Compare */
4182 TIM_OC5_SetConfig(htim->Instance, sConfig);
4183 break;
4184 }
4185
4186 case TIM_CHANNEL_6:
4187 {
4188 /* Check the parameters */
4189 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
4190
4191 /* Configure the TIM Channel 6 in Output Compare */
4192 TIM_OC6_SetConfig(htim->Instance, sConfig);
4193 break;
4194 }
4195
4196 default:
4197 status = HAL_ERROR;
4198 break;
4199 }
4200
4201 __HAL_UNLOCK(htim);
4202
4203 return status;
4204 }
4205
4206 /**
4207 * @brief Initializes the TIM Input Capture Channels according to the specified
4208 * parameters in the TIM_IC_InitTypeDef.
4209 * @param htim TIM IC handle
4210 * @param sConfig TIM Input Capture configuration structure
4211 * @param Channel TIM Channel to configure
4212 * This parameter can be one of the following values:
4213 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4214 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4215 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4216 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4217 * @retval HAL status
4218 */
HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef * htim,TIM_IC_InitTypeDef * sConfig,uint32_t Channel)4219 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
4220 {
4221 HAL_StatusTypeDef status = HAL_OK;
4222
4223 /* Check the parameters */
4224 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4225 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
4226 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
4227 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
4228 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
4229
4230 /* Process Locked */
4231 __HAL_LOCK(htim);
4232
4233 if (Channel == TIM_CHANNEL_1)
4234 {
4235 /* TI1 Configuration */
4236 TIM_TI1_SetConfig(htim->Instance,
4237 sConfig->ICPolarity,
4238 sConfig->ICSelection,
4239 sConfig->ICFilter);
4240
4241 /* Reset the IC1PSC Bits */
4242 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4243
4244 /* Set the IC1PSC value */
4245 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
4246 }
4247 else if (Channel == TIM_CHANNEL_2)
4248 {
4249 /* TI2 Configuration */
4250 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4251
4252 TIM_TI2_SetConfig(htim->Instance,
4253 sConfig->ICPolarity,
4254 sConfig->ICSelection,
4255 sConfig->ICFilter);
4256
4257 /* Reset the IC2PSC Bits */
4258 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4259
4260 /* Set the IC2PSC value */
4261 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
4262 }
4263 else if (Channel == TIM_CHANNEL_3)
4264 {
4265 /* TI3 Configuration */
4266 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4267
4268 TIM_TI3_SetConfig(htim->Instance,
4269 sConfig->ICPolarity,
4270 sConfig->ICSelection,
4271 sConfig->ICFilter);
4272
4273 /* Reset the IC3PSC Bits */
4274 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
4275
4276 /* Set the IC3PSC value */
4277 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
4278 }
4279 else if (Channel == TIM_CHANNEL_4)
4280 {
4281 /* TI4 Configuration */
4282 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4283
4284 TIM_TI4_SetConfig(htim->Instance,
4285 sConfig->ICPolarity,
4286 sConfig->ICSelection,
4287 sConfig->ICFilter);
4288
4289 /* Reset the IC4PSC Bits */
4290 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
4291
4292 /* Set the IC4PSC value */
4293 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
4294 }
4295 else
4296 {
4297 status = HAL_ERROR;
4298 }
4299
4300 __HAL_UNLOCK(htim);
4301
4302 return status;
4303 }
4304
4305 /**
4306 * @brief Initializes the TIM PWM channels according to the specified
4307 * parameters in the TIM_OC_InitTypeDef.
4308 * @param htim TIM PWM handle
4309 * @param sConfig TIM PWM configuration structure
4310 * @param Channel TIM Channels to be configured
4311 * This parameter can be one of the following values:
4312 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4313 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4314 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4315 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4316 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
4317 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
4318 * @retval HAL status
4319 */
HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OC_InitTypeDef * sConfig,uint32_t Channel)4320 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
4321 TIM_OC_InitTypeDef *sConfig,
4322 uint32_t Channel)
4323 {
4324 HAL_StatusTypeDef status = HAL_OK;
4325
4326 /* Check the parameters */
4327 assert_param(IS_TIM_CHANNELS(Channel));
4328 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
4329 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4330 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
4331
4332 /* Process Locked */
4333 __HAL_LOCK(htim);
4334
4335 switch (Channel)
4336 {
4337 case TIM_CHANNEL_1:
4338 {
4339 /* Check the parameters */
4340 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4341
4342 /* Configure the Channel 1 in PWM mode */
4343 TIM_OC1_SetConfig(htim->Instance, sConfig);
4344
4345 /* Set the Preload enable bit for channel1 */
4346 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
4347
4348 /* Configure the Output Fast mode */
4349 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
4350 htim->Instance->CCMR1 |= sConfig->OCFastMode;
4351 break;
4352 }
4353
4354 case TIM_CHANNEL_2:
4355 {
4356 /* Check the parameters */
4357 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4358
4359 /* Configure the Channel 2 in PWM mode */
4360 TIM_OC2_SetConfig(htim->Instance, sConfig);
4361
4362 /* Set the Preload enable bit for channel2 */
4363 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
4364
4365 /* Configure the Output Fast mode */
4366 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
4367 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
4368 break;
4369 }
4370
4371 case TIM_CHANNEL_3:
4372 {
4373 /* Check the parameters */
4374 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4375
4376 /* Configure the Channel 3 in PWM mode */
4377 TIM_OC3_SetConfig(htim->Instance, sConfig);
4378
4379 /* Set the Preload enable bit for channel3 */
4380 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
4381
4382 /* Configure the Output Fast mode */
4383 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
4384 htim->Instance->CCMR2 |= sConfig->OCFastMode;
4385 break;
4386 }
4387
4388 case TIM_CHANNEL_4:
4389 {
4390 /* Check the parameters */
4391 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4392
4393 /* Configure the Channel 4 in PWM mode */
4394 TIM_OC4_SetConfig(htim->Instance, sConfig);
4395
4396 /* Set the Preload enable bit for channel4 */
4397 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
4398
4399 /* Configure the Output Fast mode */
4400 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
4401 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
4402 break;
4403 }
4404
4405 case TIM_CHANNEL_5:
4406 {
4407 /* Check the parameters */
4408 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
4409
4410 /* Configure the Channel 5 in PWM mode */
4411 TIM_OC5_SetConfig(htim->Instance, sConfig);
4412
4413 /* Set the Preload enable bit for channel5*/
4414 htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
4415
4416 /* Configure the Output Fast mode */
4417 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
4418 htim->Instance->CCMR3 |= sConfig->OCFastMode;
4419 break;
4420 }
4421
4422 case TIM_CHANNEL_6:
4423 {
4424 /* Check the parameters */
4425 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
4426
4427 /* Configure the Channel 6 in PWM mode */
4428 TIM_OC6_SetConfig(htim->Instance, sConfig);
4429
4430 /* Set the Preload enable bit for channel6 */
4431 htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
4432
4433 /* Configure the Output Fast mode */
4434 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
4435 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
4436 break;
4437 }
4438
4439 default:
4440 status = HAL_ERROR;
4441 break;
4442 }
4443
4444 __HAL_UNLOCK(htim);
4445
4446 return status;
4447 }
4448
4449 /**
4450 * @brief Initializes the TIM One Pulse Channels according to the specified
4451 * parameters in the TIM_OnePulse_InitTypeDef.
4452 * @param htim TIM One Pulse handle
4453 * @param sConfig TIM One Pulse configuration structure
4454 * @param OutputChannel TIM output channel to configure
4455 * This parameter can be one of the following values:
4456 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4457 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4458 * @param InputChannel TIM input Channel to configure
4459 * This parameter can be one of the following values:
4460 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4461 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4462 * @note To output a waveform with a minimum delay user can enable the fast
4463 * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
4464 * output is forced in response to the edge detection on TIx input,
4465 * without taking in account the comparison.
4466 * @retval HAL status
4467 */
HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OnePulse_InitTypeDef * sConfig,uint32_t OutputChannel,uint32_t InputChannel)4468 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
4469 uint32_t OutputChannel, uint32_t InputChannel)
4470 {
4471 HAL_StatusTypeDef status = HAL_OK;
4472 TIM_OC_InitTypeDef temp1;
4473
4474 /* Check the parameters */
4475 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
4476 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
4477
4478 if (OutputChannel != InputChannel)
4479 {
4480 /* Process Locked */
4481 __HAL_LOCK(htim);
4482
4483 htim->State = HAL_TIM_STATE_BUSY;
4484
4485 /* Extract the Output compare configuration from sConfig structure */
4486 temp1.OCMode = sConfig->OCMode;
4487 temp1.Pulse = sConfig->Pulse;
4488 temp1.OCPolarity = sConfig->OCPolarity;
4489 temp1.OCNPolarity = sConfig->OCNPolarity;
4490 temp1.OCIdleState = sConfig->OCIdleState;
4491 temp1.OCNIdleState = sConfig->OCNIdleState;
4492
4493 switch (OutputChannel)
4494 {
4495 case TIM_CHANNEL_1:
4496 {
4497 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4498
4499 TIM_OC1_SetConfig(htim->Instance, &temp1);
4500 break;
4501 }
4502
4503 case TIM_CHANNEL_2:
4504 {
4505 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4506
4507 TIM_OC2_SetConfig(htim->Instance, &temp1);
4508 break;
4509 }
4510
4511 default:
4512 status = HAL_ERROR;
4513 break;
4514 }
4515
4516 if (status == HAL_OK)
4517 {
4518 switch (InputChannel)
4519 {
4520 case TIM_CHANNEL_1:
4521 {
4522 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4523
4524 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
4525 sConfig->ICSelection, sConfig->ICFilter);
4526
4527 /* Reset the IC1PSC Bits */
4528 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4529
4530 /* Select the Trigger source */
4531 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4532 htim->Instance->SMCR |= TIM_TS_TI1FP1;
4533
4534 /* Select the Slave Mode */
4535 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4536 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4537 break;
4538 }
4539
4540 case TIM_CHANNEL_2:
4541 {
4542 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4543
4544 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
4545 sConfig->ICSelection, sConfig->ICFilter);
4546
4547 /* Reset the IC2PSC Bits */
4548 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4549
4550 /* Select the Trigger source */
4551 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4552 htim->Instance->SMCR |= TIM_TS_TI2FP2;
4553
4554 /* Select the Slave Mode */
4555 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4556 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4557 break;
4558 }
4559
4560 default:
4561 status = HAL_ERROR;
4562 break;
4563 }
4564 }
4565
4566 htim->State = HAL_TIM_STATE_READY;
4567
4568 __HAL_UNLOCK(htim);
4569
4570 return status;
4571 }
4572 else
4573 {
4574 return HAL_ERROR;
4575 }
4576 }
4577
4578 /**
4579 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
4580 * @param htim TIM handle
4581 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4582 * This parameter can be one of the following values:
4583 * @arg TIM_DMABASE_CR1
4584 * @arg TIM_DMABASE_CR2
4585 * @arg TIM_DMABASE_SMCR
4586 * @arg TIM_DMABASE_DIER
4587 * @arg TIM_DMABASE_SR
4588 * @arg TIM_DMABASE_EGR
4589 * @arg TIM_DMABASE_CCMR1
4590 * @arg TIM_DMABASE_CCMR2
4591 * @arg TIM_DMABASE_CCER
4592 * @arg TIM_DMABASE_CNT
4593 * @arg TIM_DMABASE_PSC
4594 * @arg TIM_DMABASE_ARR
4595 * @arg TIM_DMABASE_RCR
4596 * @arg TIM_DMABASE_CCR1
4597 * @arg TIM_DMABASE_CCR2
4598 * @arg TIM_DMABASE_CCR3
4599 * @arg TIM_DMABASE_CCR4
4600 * @arg TIM_DMABASE_BDTR
4601 * @arg TIM_DMABASE_CCMR3
4602 * @arg TIM_DMABASE_CCR5
4603 * @arg TIM_DMABASE_CCR6
4604 * @arg TIM_DMABASE_DTR2
4605 * @arg TIM_DMABASE_ECR
4606 * @arg TIM_DMABASE_TISEL
4607 * @arg TIM_DMABASE_AF1
4608 * @arg TIM_DMABASE_AF2
4609 * @arg TIM_DMABASE_OR
4610 * @param BurstRequestSrc TIM DMA Request sources
4611 * This parameter can be one of the following values:
4612 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4613 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4614 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4615 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4616 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4617 * @arg TIM_DMA_COM: TIM Commutation DMA source
4618 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4619 * @param BurstBuffer The Buffer address.
4620 * @param BurstLength DMA Burst length. This parameter can be one value
4621 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
4622 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4623 * @retval HAL status
4624 */
HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)4625 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4626 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
4627 {
4628 HAL_StatusTypeDef status;
4629
4630 status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4631 ((BurstLength) >> 8U) + 1U);
4632
4633
4634
4635 return status;
4636 }
4637
4638 /**
4639 * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
4640 * @param htim TIM handle
4641 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4642 * This parameter can be one of the following values:
4643 * @arg TIM_DMABASE_CR1
4644 * @arg TIM_DMABASE_CR2
4645 * @arg TIM_DMABASE_SMCR
4646 * @arg TIM_DMABASE_DIER
4647 * @arg TIM_DMABASE_SR
4648 * @arg TIM_DMABASE_EGR
4649 * @arg TIM_DMABASE_CCMR1
4650 * @arg TIM_DMABASE_CCMR2
4651 * @arg TIM_DMABASE_CCER
4652 * @arg TIM_DMABASE_CNT
4653 * @arg TIM_DMABASE_PSC
4654 * @arg TIM_DMABASE_ARR
4655 * @arg TIM_DMABASE_RCR
4656 * @arg TIM_DMABASE_CCR1
4657 * @arg TIM_DMABASE_CCR2
4658 * @arg TIM_DMABASE_CCR3
4659 * @arg TIM_DMABASE_CCR4
4660 * @arg TIM_DMABASE_BDTR
4661 * @arg TIM_DMABASE_CCMR3
4662 * @arg TIM_DMABASE_CCR5
4663 * @arg TIM_DMABASE_CCR6
4664 * @arg TIM_DMABASE_DTR2
4665 * @arg TIM_DMABASE_ECR
4666 * @arg TIM_DMABASE_TISEL
4667 * @arg TIM_DMABASE_AF1
4668 * @arg TIM_DMABASE_AF2
4669 * @arg TIM_DMABASE_OR
4670 * @param BurstRequestSrc TIM DMA Request sources
4671 * This parameter can be one of the following values:
4672 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4673 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4674 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4675 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4676 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4677 * @arg TIM_DMA_COM: TIM Commutation DMA source
4678 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4679 * @param BurstBuffer The Buffer address.
4680 * @param BurstLength DMA Burst length. This parameter can be one value
4681 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
4682 * @param DataLength Data length. This parameter can be one value
4683 * between 1 and 0xFFFF.
4684 * @retval HAL status
4685 */
HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)4686 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4687 uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
4688 uint32_t BurstLength, uint32_t DataLength)
4689 {
4690 HAL_StatusTypeDef status = HAL_OK;
4691
4692 /* Check the parameters */
4693 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4694 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4695 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4696 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4697 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4698
4699 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
4700 {
4701 return HAL_BUSY;
4702 }
4703 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
4704 {
4705 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4706 {
4707 return HAL_ERROR;
4708 }
4709 else
4710 {
4711 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
4712 }
4713 }
4714 else
4715 {
4716 /* nothing to do */
4717 }
4718
4719 switch (BurstRequestSrc)
4720 {
4721 case TIM_DMA_UPDATE:
4722 {
4723 /* Set the DMA Period elapsed callbacks */
4724 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4725 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4726
4727 /* Set the DMA error callback */
4728 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4729
4730 /* Enable the DMA channel */
4731 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
4732 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4733 {
4734 /* Return error status */
4735 return HAL_ERROR;
4736 }
4737 break;
4738 }
4739 case TIM_DMA_CC1:
4740 {
4741 /* Set the DMA compare callbacks */
4742 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
4743 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4744
4745 /* Set the DMA error callback */
4746 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4747
4748 /* Enable the DMA channel */
4749 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
4750 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4751 {
4752 /* Return error status */
4753 return HAL_ERROR;
4754 }
4755 break;
4756 }
4757 case TIM_DMA_CC2:
4758 {
4759 /* Set the DMA compare callbacks */
4760 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
4761 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4762
4763 /* Set the DMA error callback */
4764 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4765
4766 /* Enable the DMA channel */
4767 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
4768 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4769 {
4770 /* Return error status */
4771 return HAL_ERROR;
4772 }
4773 break;
4774 }
4775 case TIM_DMA_CC3:
4776 {
4777 /* Set the DMA compare callbacks */
4778 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
4779 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4780
4781 /* Set the DMA error callback */
4782 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4783
4784 /* Enable the DMA channel */
4785 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
4786 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4787 {
4788 /* Return error status */
4789 return HAL_ERROR;
4790 }
4791 break;
4792 }
4793 case TIM_DMA_CC4:
4794 {
4795 /* Set the DMA compare callbacks */
4796 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
4797 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4798
4799 /* Set the DMA error callback */
4800 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4801
4802 /* Enable the DMA channel */
4803 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
4804 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4805 {
4806 /* Return error status */
4807 return HAL_ERROR;
4808 }
4809 break;
4810 }
4811 case TIM_DMA_COM:
4812 {
4813 /* Set the DMA commutation callbacks */
4814 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
4815 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
4816
4817 /* Set the DMA error callback */
4818 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
4819
4820 /* Enable the DMA channel */
4821 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
4822 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4823 {
4824 /* Return error status */
4825 return HAL_ERROR;
4826 }
4827 break;
4828 }
4829 case TIM_DMA_TRIGGER:
4830 {
4831 /* Set the DMA trigger callbacks */
4832 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4833 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
4834
4835 /* Set the DMA error callback */
4836 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4837
4838 /* Enable the DMA channel */
4839 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
4840 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4841 {
4842 /* Return error status */
4843 return HAL_ERROR;
4844 }
4845 break;
4846 }
4847 default:
4848 status = HAL_ERROR;
4849 break;
4850 }
4851
4852 if (status == HAL_OK)
4853 {
4854 /* Configure the DMA Burst Mode */
4855 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
4856 /* Enable the TIM DMA Request */
4857 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4858 }
4859
4860 /* Return function status */
4861 return status;
4862 }
4863
4864 /**
4865 * @brief Stops the TIM DMA Burst mode
4866 * @param htim TIM handle
4867 * @param BurstRequestSrc TIM DMA Request sources to disable
4868 * @retval HAL status
4869 */
HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)4870 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4871 {
4872 HAL_StatusTypeDef status = HAL_OK;
4873
4874 /* Check the parameters */
4875 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4876
4877 /* Abort the DMA transfer (at least disable the DMA channel) */
4878 switch (BurstRequestSrc)
4879 {
4880 case TIM_DMA_UPDATE:
4881 {
4882 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4883 break;
4884 }
4885 case TIM_DMA_CC1:
4886 {
4887 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
4888 break;
4889 }
4890 case TIM_DMA_CC2:
4891 {
4892 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
4893 break;
4894 }
4895 case TIM_DMA_CC3:
4896 {
4897 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
4898 break;
4899 }
4900 case TIM_DMA_CC4:
4901 {
4902 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
4903 break;
4904 }
4905 case TIM_DMA_COM:
4906 {
4907 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
4908 break;
4909 }
4910 case TIM_DMA_TRIGGER:
4911 {
4912 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
4913 break;
4914 }
4915 default:
4916 status = HAL_ERROR;
4917 break;
4918 }
4919
4920 if (status == HAL_OK)
4921 {
4922 /* Disable the TIM Update DMA request */
4923 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
4924
4925 /* Change the DMA burst operation state */
4926 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
4927 }
4928
4929 /* Return function status */
4930 return status;
4931 }
4932
4933 /**
4934 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4935 * @param htim TIM handle
4936 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4937 * This parameter can be one of the following values:
4938 * @arg TIM_DMABASE_CR1
4939 * @arg TIM_DMABASE_CR2
4940 * @arg TIM_DMABASE_SMCR
4941 * @arg TIM_DMABASE_DIER
4942 * @arg TIM_DMABASE_SR
4943 * @arg TIM_DMABASE_EGR
4944 * @arg TIM_DMABASE_CCMR1
4945 * @arg TIM_DMABASE_CCMR2
4946 * @arg TIM_DMABASE_CCER
4947 * @arg TIM_DMABASE_CNT
4948 * @arg TIM_DMABASE_PSC
4949 * @arg TIM_DMABASE_ARR
4950 * @arg TIM_DMABASE_RCR
4951 * @arg TIM_DMABASE_CCR1
4952 * @arg TIM_DMABASE_CCR2
4953 * @arg TIM_DMABASE_CCR3
4954 * @arg TIM_DMABASE_CCR4
4955 * @arg TIM_DMABASE_BDTR
4956 * @arg TIM_DMABASE_CCMR3
4957 * @arg TIM_DMABASE_CCR5
4958 * @arg TIM_DMABASE_CCR6
4959 * @arg TIM_DMABASE_DTR2
4960 * @arg TIM_DMABASE_ECR
4961 * @arg TIM_DMABASE_TISEL
4962 * @arg TIM_DMABASE_AF1
4963 * @arg TIM_DMABASE_AF2
4964 * @arg TIM_DMABASE_OR
4965 * @param BurstRequestSrc TIM DMA Request sources
4966 * This parameter can be one of the following values:
4967 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4968 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4969 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4970 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4971 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4972 * @arg TIM_DMA_COM: TIM Commutation DMA source
4973 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4974 * @param BurstBuffer The Buffer address.
4975 * @param BurstLength DMA Burst length. This parameter can be one value
4976 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
4977 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4978 * @retval HAL status
4979 */
HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)4980 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4981 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
4982 {
4983 HAL_StatusTypeDef status;
4984
4985 status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4986 ((BurstLength) >> 8U) + 1U);
4987
4988
4989 return status;
4990 }
4991
4992 /**
4993 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4994 * @param htim TIM handle
4995 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4996 * This parameter can be one of the following values:
4997 * @arg TIM_DMABASE_CR1
4998 * @arg TIM_DMABASE_CR2
4999 * @arg TIM_DMABASE_SMCR
5000 * @arg TIM_DMABASE_DIER
5001 * @arg TIM_DMABASE_SR
5002 * @arg TIM_DMABASE_EGR
5003 * @arg TIM_DMABASE_CCMR1
5004 * @arg TIM_DMABASE_CCMR2
5005 * @arg TIM_DMABASE_CCER
5006 * @arg TIM_DMABASE_CNT
5007 * @arg TIM_DMABASE_PSC
5008 * @arg TIM_DMABASE_ARR
5009 * @arg TIM_DMABASE_RCR
5010 * @arg TIM_DMABASE_CCR1
5011 * @arg TIM_DMABASE_CCR2
5012 * @arg TIM_DMABASE_CCR3
5013 * @arg TIM_DMABASE_CCR4
5014 * @arg TIM_DMABASE_BDTR
5015 * @arg TIM_DMABASE_CCMR3
5016 * @arg TIM_DMABASE_CCR5
5017 * @arg TIM_DMABASE_CCR6
5018 * @arg TIM_DMABASE_DTR2
5019 * @arg TIM_DMABASE_ECR
5020 * @arg TIM_DMABASE_TISEL
5021 * @arg TIM_DMABASE_AF1
5022 * @arg TIM_DMABASE_AF2
5023 * @arg TIM_DMABASE_OR
5024 * @param BurstRequestSrc TIM DMA Request sources
5025 * This parameter can be one of the following values:
5026 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
5027 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
5028 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
5029 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
5030 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
5031 * @arg TIM_DMA_COM: TIM Commutation DMA source
5032 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
5033 * @param BurstBuffer The Buffer address.
5034 * @param BurstLength DMA Burst length. This parameter can be one value
5035 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
5036 * @param DataLength Data length. This parameter can be one value
5037 * between 1 and 0xFFFF.
5038 * @retval HAL status
5039 */
HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)5040 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
5041 uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
5042 uint32_t BurstLength, uint32_t DataLength)
5043 {
5044 HAL_StatusTypeDef status = HAL_OK;
5045
5046 /* Check the parameters */
5047 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
5048 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
5049 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
5050 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
5051 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
5052
5053 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
5054 {
5055 return HAL_BUSY;
5056 }
5057 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
5058 {
5059 if ((BurstBuffer == NULL) && (BurstLength > 0U))
5060 {
5061 return HAL_ERROR;
5062 }
5063 else
5064 {
5065 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
5066 }
5067 }
5068 else
5069 {
5070 /* nothing to do */
5071 }
5072 switch (BurstRequestSrc)
5073 {
5074 case TIM_DMA_UPDATE:
5075 {
5076 /* Set the DMA Period elapsed callbacks */
5077 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
5078 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
5079
5080 /* Set the DMA error callback */
5081 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
5082
5083 /* Enable the DMA channel */
5084 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5085 DataLength) != HAL_OK)
5086 {
5087 /* Return error status */
5088 return HAL_ERROR;
5089 }
5090 break;
5091 }
5092 case TIM_DMA_CC1:
5093 {
5094 /* Set the DMA capture callbacks */
5095 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
5096 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5097
5098 /* Set the DMA error callback */
5099 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
5100
5101 /* Enable the DMA channel */
5102 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5103 DataLength) != HAL_OK)
5104 {
5105 /* Return error status */
5106 return HAL_ERROR;
5107 }
5108 break;
5109 }
5110 case TIM_DMA_CC2:
5111 {
5112 /* Set the DMA capture callbacks */
5113 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
5114 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5115
5116 /* Set the DMA error callback */
5117 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
5118
5119 /* Enable the DMA channel */
5120 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5121 DataLength) != HAL_OK)
5122 {
5123 /* Return error status */
5124 return HAL_ERROR;
5125 }
5126 break;
5127 }
5128 case TIM_DMA_CC3:
5129 {
5130 /* Set the DMA capture callbacks */
5131 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
5132 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5133
5134 /* Set the DMA error callback */
5135 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
5136
5137 /* Enable the DMA channel */
5138 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5139 DataLength) != HAL_OK)
5140 {
5141 /* Return error status */
5142 return HAL_ERROR;
5143 }
5144 break;
5145 }
5146 case TIM_DMA_CC4:
5147 {
5148 /* Set the DMA capture callbacks */
5149 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
5150 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5151
5152 /* Set the DMA error callback */
5153 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
5154
5155 /* Enable the DMA channel */
5156 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5157 DataLength) != HAL_OK)
5158 {
5159 /* Return error status */
5160 return HAL_ERROR;
5161 }
5162 break;
5163 }
5164 case TIM_DMA_COM:
5165 {
5166 /* Set the DMA commutation callbacks */
5167 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
5168 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
5169
5170 /* Set the DMA error callback */
5171 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
5172
5173 /* Enable the DMA channel */
5174 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5175 DataLength) != HAL_OK)
5176 {
5177 /* Return error status */
5178 return HAL_ERROR;
5179 }
5180 break;
5181 }
5182 case TIM_DMA_TRIGGER:
5183 {
5184 /* Set the DMA trigger callbacks */
5185 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
5186 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
5187
5188 /* Set the DMA error callback */
5189 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
5190
5191 /* Enable the DMA channel */
5192 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5193 DataLength) != HAL_OK)
5194 {
5195 /* Return error status */
5196 return HAL_ERROR;
5197 }
5198 break;
5199 }
5200 default:
5201 status = HAL_ERROR;
5202 break;
5203 }
5204
5205 if (status == HAL_OK)
5206 {
5207 /* Configure the DMA Burst Mode */
5208 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
5209
5210 /* Enable the TIM DMA Request */
5211 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
5212 }
5213
5214 /* Return function status */
5215 return status;
5216 }
5217
5218 /**
5219 * @brief Stop the DMA burst reading
5220 * @param htim TIM handle
5221 * @param BurstRequestSrc TIM DMA Request sources to disable.
5222 * @retval HAL status
5223 */
HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)5224 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
5225 {
5226 HAL_StatusTypeDef status = HAL_OK;
5227
5228 /* Check the parameters */
5229 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
5230
5231 /* Abort the DMA transfer (at least disable the DMA channel) */
5232 switch (BurstRequestSrc)
5233 {
5234 case TIM_DMA_UPDATE:
5235 {
5236 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
5237 break;
5238 }
5239 case TIM_DMA_CC1:
5240 {
5241 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
5242 break;
5243 }
5244 case TIM_DMA_CC2:
5245 {
5246 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
5247 break;
5248 }
5249 case TIM_DMA_CC3:
5250 {
5251 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
5252 break;
5253 }
5254 case TIM_DMA_CC4:
5255 {
5256 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
5257 break;
5258 }
5259 case TIM_DMA_COM:
5260 {
5261 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
5262 break;
5263 }
5264 case TIM_DMA_TRIGGER:
5265 {
5266 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
5267 break;
5268 }
5269 default:
5270 status = HAL_ERROR;
5271 break;
5272 }
5273
5274 if (status == HAL_OK)
5275 {
5276 /* Disable the TIM Update DMA request */
5277 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
5278
5279 /* Change the DMA burst operation state */
5280 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
5281 }
5282
5283 /* Return function status */
5284 return status;
5285 }
5286
5287 /**
5288 * @brief Generate a software event
5289 * @param htim TIM handle
5290 * @param EventSource specifies the event source.
5291 * This parameter can be one of the following values:
5292 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
5293 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
5294 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
5295 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
5296 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
5297 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
5298 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
5299 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
5300 * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
5301 * @note Basic timers can only generate an update event.
5302 * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
5303 * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
5304 * only for timer instances supporting break input(s).
5305 * @retval HAL status
5306 */
5307
HAL_TIM_GenerateEvent(TIM_HandleTypeDef * htim,uint32_t EventSource)5308 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
5309 {
5310 /* Check the parameters */
5311 assert_param(IS_TIM_INSTANCE(htim->Instance));
5312 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
5313
5314 /* Process Locked */
5315 __HAL_LOCK(htim);
5316
5317 /* Change the TIM state */
5318 htim->State = HAL_TIM_STATE_BUSY;
5319
5320 /* Set the event sources */
5321 htim->Instance->EGR = EventSource;
5322
5323 /* Change the TIM state */
5324 htim->State = HAL_TIM_STATE_READY;
5325
5326 __HAL_UNLOCK(htim);
5327
5328 /* Return function status */
5329 return HAL_OK;
5330 }
5331
5332 /**
5333 * @brief Configures the OCRef clear feature
5334 * @param htim TIM handle
5335 * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
5336 * contains the OCREF clear feature and parameters for the TIM peripheral.
5337 * @param Channel specifies the TIM Channel
5338 * This parameter can be one of the following values:
5339 * @arg TIM_CHANNEL_1: TIM Channel 1
5340 * @arg TIM_CHANNEL_2: TIM Channel 2
5341 * @arg TIM_CHANNEL_3: TIM Channel 3
5342 * @arg TIM_CHANNEL_4: TIM Channel 4
5343 * @arg TIM_CHANNEL_5: TIM Channel 5
5344 * @arg TIM_CHANNEL_6: TIM Channel 6
5345 * @retval HAL status
5346 */
HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef * htim,TIM_ClearInputConfigTypeDef * sClearInputConfig,uint32_t Channel)5347 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
5348 TIM_ClearInputConfigTypeDef *sClearInputConfig,
5349 uint32_t Channel)
5350 {
5351 HAL_StatusTypeDef status = HAL_OK;
5352
5353 /* Check the parameters */
5354 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
5355 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
5356
5357 /* Process Locked */
5358 __HAL_LOCK(htim);
5359
5360 htim->State = HAL_TIM_STATE_BUSY;
5361
5362 switch (sClearInputConfig->ClearInputSource)
5363 {
5364 case TIM_CLEARINPUTSOURCE_NONE:
5365 {
5366 /* Clear the OCREF clear selection bit and the the ETR Bits */
5367 if (IS_TIM_OCCS_INSTANCE(htim->Instance))
5368 {
5369 CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
5370
5371 /* Clear TIMx_AF2_OCRSEL (reset value) */
5372 CLEAR_BIT(htim->Instance->AF2, TIMx_AF2_OCRSEL);
5373 }
5374 else
5375 {
5376 CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
5377 }
5378 break;
5379 }
5380
5381 case TIM_CLEARINPUTSOURCE_COMP1:
5382 case TIM_CLEARINPUTSOURCE_COMP2:
5383 case TIM_CLEARINPUTSOURCE_COMP3:
5384 case TIM_CLEARINPUTSOURCE_COMP4:
5385 #if defined (COMP5)
5386 case TIM_CLEARINPUTSOURCE_COMP5:
5387 #endif /* COMP5 */
5388 #if defined (COMP6)
5389 case TIM_CLEARINPUTSOURCE_COMP6:
5390 #endif /* COMP6 */
5391 #if defined (COMP7)
5392 case TIM_CLEARINPUTSOURCE_COMP7:
5393 #endif /* COMP7 */
5394 {
5395 if (IS_TIM_OCCS_INSTANCE(htim->Instance))
5396 {
5397 /* Clear the OCREF clear selection bit */
5398 CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
5399
5400 /* Clear TIM1_AF2_OCRSEL (reset value) */
5401 MODIFY_REG(htim->Instance->AF2, TIMx_AF2_OCRSEL, sClearInputConfig->ClearInputSource);
5402 }
5403 break;
5404 }
5405
5406 case TIM_CLEARINPUTSOURCE_ETR:
5407 {
5408 /* Check the parameters */
5409 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
5410 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
5411 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
5412
5413 /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
5414 if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
5415 {
5416 htim->State = HAL_TIM_STATE_READY;
5417 __HAL_UNLOCK(htim);
5418 return HAL_ERROR;
5419 }
5420
5421 TIM_ETR_SetConfig(htim->Instance,
5422 sClearInputConfig->ClearInputPrescaler,
5423 sClearInputConfig->ClearInputPolarity,
5424 sClearInputConfig->ClearInputFilter);
5425
5426 if (IS_TIM_OCCS_INSTANCE(htim->Instance))
5427 {
5428 /* Set the OCREF clear selection bit */
5429 SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
5430
5431 /* Clear TIMx_AF2_OCRSEL (reset value) */
5432 CLEAR_BIT(htim->Instance->AF2, TIMx_AF2_OCRSEL);
5433 }
5434 break;
5435 }
5436
5437 default:
5438 status = HAL_ERROR;
5439 break;
5440 }
5441
5442 if (status == HAL_OK)
5443 {
5444 switch (Channel)
5445 {
5446 case TIM_CHANNEL_1:
5447 {
5448 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5449 {
5450 /* Enable the OCREF clear feature for Channel 1 */
5451 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5452 }
5453 else
5454 {
5455 /* Disable the OCREF clear feature for Channel 1 */
5456 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5457 }
5458 break;
5459 }
5460 case TIM_CHANNEL_2:
5461 {
5462 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5463 {
5464 /* Enable the OCREF clear feature for Channel 2 */
5465 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5466 }
5467 else
5468 {
5469 /* Disable the OCREF clear feature for Channel 2 */
5470 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5471 }
5472 break;
5473 }
5474 case TIM_CHANNEL_3:
5475 {
5476 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5477 {
5478 /* Enable the OCREF clear feature for Channel 3 */
5479 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5480 }
5481 else
5482 {
5483 /* Disable the OCREF clear feature for Channel 3 */
5484 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5485 }
5486 break;
5487 }
5488 case TIM_CHANNEL_4:
5489 {
5490 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5491 {
5492 /* Enable the OCREF clear feature for Channel 4 */
5493 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5494 }
5495 else
5496 {
5497 /* Disable the OCREF clear feature for Channel 4 */
5498 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5499 }
5500 break;
5501 }
5502 case TIM_CHANNEL_5:
5503 {
5504 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5505 {
5506 /* Enable the OCREF clear feature for Channel 5 */
5507 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
5508 }
5509 else
5510 {
5511 /* Disable the OCREF clear feature for Channel 5 */
5512 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
5513 }
5514 break;
5515 }
5516 case TIM_CHANNEL_6:
5517 {
5518 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5519 {
5520 /* Enable the OCREF clear feature for Channel 6 */
5521 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
5522 }
5523 else
5524 {
5525 /* Disable the OCREF clear feature for Channel 6 */
5526 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
5527 }
5528 break;
5529 }
5530 default:
5531 break;
5532 }
5533 }
5534
5535 htim->State = HAL_TIM_STATE_READY;
5536
5537 __HAL_UNLOCK(htim);
5538
5539 return status;
5540 }
5541
5542 /**
5543 * @brief Configures the clock source to be used
5544 * @param htim TIM handle
5545 * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
5546 * contains the clock source information for the TIM peripheral.
5547 * @retval HAL status
5548 */
HAL_TIM_ConfigClockSource(TIM_HandleTypeDef * htim,TIM_ClockConfigTypeDef * sClockSourceConfig)5549 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
5550 {
5551 HAL_StatusTypeDef status = HAL_OK;
5552 uint32_t tmpsmcr;
5553
5554 /* Process Locked */
5555 __HAL_LOCK(htim);
5556
5557 htim->State = HAL_TIM_STATE_BUSY;
5558
5559 /* Check the parameters */
5560 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
5561
5562 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
5563 tmpsmcr = htim->Instance->SMCR;
5564 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
5565 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
5566 htim->Instance->SMCR = tmpsmcr;
5567
5568 switch (sClockSourceConfig->ClockSource)
5569 {
5570 case TIM_CLOCKSOURCE_INTERNAL:
5571 {
5572 assert_param(IS_TIM_INSTANCE(htim->Instance));
5573 break;
5574 }
5575
5576 case TIM_CLOCKSOURCE_ETRMODE1:
5577 {
5578 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
5579 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
5580
5581 /* Check ETR input conditioning related parameters */
5582 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5583 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5584 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5585
5586 /* Configure the ETR Clock source */
5587 TIM_ETR_SetConfig(htim->Instance,
5588 sClockSourceConfig->ClockPrescaler,
5589 sClockSourceConfig->ClockPolarity,
5590 sClockSourceConfig->ClockFilter);
5591
5592 /* Select the External clock mode1 and the ETRF trigger */
5593 tmpsmcr = htim->Instance->SMCR;
5594 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
5595 /* Write to TIMx SMCR */
5596 htim->Instance->SMCR = tmpsmcr;
5597 break;
5598 }
5599
5600 case TIM_CLOCKSOURCE_ETRMODE2:
5601 {
5602 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
5603 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
5604
5605 /* Check ETR input conditioning related parameters */
5606 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5607 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5608 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5609
5610 /* Configure the ETR Clock source */
5611 TIM_ETR_SetConfig(htim->Instance,
5612 sClockSourceConfig->ClockPrescaler,
5613 sClockSourceConfig->ClockPolarity,
5614 sClockSourceConfig->ClockFilter);
5615 /* Enable the External clock mode2 */
5616 htim->Instance->SMCR |= TIM_SMCR_ECE;
5617 break;
5618 }
5619
5620 case TIM_CLOCKSOURCE_TI1:
5621 {
5622 /* Check whether or not the timer instance supports external clock mode 1 */
5623 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5624
5625 /* Check TI1 input conditioning related parameters */
5626 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5627 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5628
5629 TIM_TI1_ConfigInputStage(htim->Instance,
5630 sClockSourceConfig->ClockPolarity,
5631 sClockSourceConfig->ClockFilter);
5632 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
5633 break;
5634 }
5635
5636 case TIM_CLOCKSOURCE_TI2:
5637 {
5638 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
5639 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5640
5641 /* Check TI2 input conditioning related parameters */
5642 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5643 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5644
5645 TIM_TI2_ConfigInputStage(htim->Instance,
5646 sClockSourceConfig->ClockPolarity,
5647 sClockSourceConfig->ClockFilter);
5648 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
5649 break;
5650 }
5651
5652 case TIM_CLOCKSOURCE_TI1ED:
5653 {
5654 /* Check whether or not the timer instance supports external clock mode 1 */
5655 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5656
5657 /* Check TI1 input conditioning related parameters */
5658 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5659 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5660
5661 TIM_TI1_ConfigInputStage(htim->Instance,
5662 sClockSourceConfig->ClockPolarity,
5663 sClockSourceConfig->ClockFilter);
5664 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
5665 break;
5666 }
5667
5668 case TIM_CLOCKSOURCE_ITR0:
5669 case TIM_CLOCKSOURCE_ITR1:
5670 case TIM_CLOCKSOURCE_ITR2:
5671 case TIM_CLOCKSOURCE_ITR3:
5672 #if defined (TIM5)
5673 case TIM_CLOCKSOURCE_ITR4:
5674 #endif /* TIM5 */
5675 case TIM_CLOCKSOURCE_ITR5:
5676 case TIM_CLOCKSOURCE_ITR6:
5677 case TIM_CLOCKSOURCE_ITR7:
5678 case TIM_CLOCKSOURCE_ITR8:
5679 #if defined (TIM20)
5680 case TIM_CLOCKSOURCE_ITR9:
5681 #endif /* TIM20 */
5682 #if defined (HRTIM1)
5683 case TIM_CLOCKSOURCE_ITR10:
5684 #endif /* HRTIM1 */
5685 case TIM_CLOCKSOURCE_ITR11:
5686 {
5687 /* Check whether or not the timer instance supports internal trigger input */
5688 assert_param(IS_TIM_CLOCKSOURCE_INSTANCE((htim->Instance), sClockSourceConfig->ClockSource));
5689
5690 TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
5691 break;
5692 }
5693
5694 default:
5695 status = HAL_ERROR;
5696 break;
5697 }
5698 htim->State = HAL_TIM_STATE_READY;
5699
5700 __HAL_UNLOCK(htim);
5701
5702 return status;
5703 }
5704
5705 /**
5706 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
5707 * or a XOR combination between CH1_input, CH2_input & CH3_input
5708 * @param htim TIM handle.
5709 * @param TI1_Selection Indicate whether or not channel 1 is connected to the
5710 * output of a XOR gate.
5711 * This parameter can be one of the following values:
5712 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
5713 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
5714 * pins are connected to the TI1 input (XOR combination)
5715 * @retval HAL status
5716 */
HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef * htim,uint32_t TI1_Selection)5717 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
5718 {
5719 uint32_t tmpcr2;
5720
5721 /* Check the parameters */
5722 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
5723 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
5724
5725 /* Get the TIMx CR2 register value */
5726 tmpcr2 = htim->Instance->CR2;
5727
5728 /* Reset the TI1 selection */
5729 tmpcr2 &= ~TIM_CR2_TI1S;
5730
5731 /* Set the TI1 selection */
5732 tmpcr2 |= TI1_Selection;
5733
5734 /* Write to TIMxCR2 */
5735 htim->Instance->CR2 = tmpcr2;
5736
5737 return HAL_OK;
5738 }
5739
5740 /**
5741 * @brief Configures the TIM in Slave mode
5742 * @param htim TIM handle.
5743 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5744 * contains the selected trigger (internal trigger input, filtered
5745 * timer input or external trigger input) and the Slave mode
5746 * (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset).
5747 * @retval HAL status
5748 */
HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef * htim,TIM_SlaveConfigTypeDef * sSlaveConfig)5749 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
5750 {
5751 /* Check the parameters */
5752 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5753 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5754 assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger));
5755
5756 __HAL_LOCK(htim);
5757
5758 htim->State = HAL_TIM_STATE_BUSY;
5759
5760 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5761 {
5762 htim->State = HAL_TIM_STATE_READY;
5763 __HAL_UNLOCK(htim);
5764 return HAL_ERROR;
5765 }
5766
5767 /* Disable Trigger Interrupt */
5768 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
5769
5770 /* Disable Trigger DMA request */
5771 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5772
5773 htim->State = HAL_TIM_STATE_READY;
5774
5775 __HAL_UNLOCK(htim);
5776
5777 return HAL_OK;
5778 }
5779
5780 /**
5781 * @brief Configures the TIM in Slave mode in interrupt mode
5782 * @param htim TIM handle.
5783 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5784 * contains the selected trigger (internal trigger input, filtered
5785 * timer input or external trigger input) and the Slave mode
5786 * (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset).
5787 * @retval HAL status
5788 */
HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef * htim,TIM_SlaveConfigTypeDef * sSlaveConfig)5789 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
5790 TIM_SlaveConfigTypeDef *sSlaveConfig)
5791 {
5792 /* Check the parameters */
5793 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5794 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5795 assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger));
5796
5797 __HAL_LOCK(htim);
5798
5799 htim->State = HAL_TIM_STATE_BUSY;
5800
5801 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5802 {
5803 htim->State = HAL_TIM_STATE_READY;
5804 __HAL_UNLOCK(htim);
5805 return HAL_ERROR;
5806 }
5807
5808 /* Enable Trigger Interrupt */
5809 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
5810
5811 /* Disable Trigger DMA request */
5812 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5813
5814 htim->State = HAL_TIM_STATE_READY;
5815
5816 __HAL_UNLOCK(htim);
5817
5818 return HAL_OK;
5819 }
5820
5821 /**
5822 * @brief Read the captured value from Capture Compare unit
5823 * @param htim TIM handle.
5824 * @param Channel TIM Channels to be enabled
5825 * This parameter can be one of the following values:
5826 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
5827 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
5828 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
5829 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
5830 * @retval Captured value
5831 */
HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef * htim,uint32_t Channel)5832 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
5833 {
5834 uint32_t tmpreg = 0U;
5835
5836 switch (Channel)
5837 {
5838 case TIM_CHANNEL_1:
5839 {
5840 /* Check the parameters */
5841 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
5842
5843 /* Return the capture 1 value */
5844 tmpreg = htim->Instance->CCR1;
5845
5846 break;
5847 }
5848 case TIM_CHANNEL_2:
5849 {
5850 /* Check the parameters */
5851 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
5852
5853 /* Return the capture 2 value */
5854 tmpreg = htim->Instance->CCR2;
5855
5856 break;
5857 }
5858
5859 case TIM_CHANNEL_3:
5860 {
5861 /* Check the parameters */
5862 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
5863
5864 /* Return the capture 3 value */
5865 tmpreg = htim->Instance->CCR3;
5866
5867 break;
5868 }
5869
5870 case TIM_CHANNEL_4:
5871 {
5872 /* Check the parameters */
5873 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
5874
5875 /* Return the capture 4 value */
5876 tmpreg = htim->Instance->CCR4;
5877
5878 break;
5879 }
5880
5881 default:
5882 break;
5883 }
5884
5885 return tmpreg;
5886 }
5887
5888 /**
5889 * @}
5890 */
5891
5892 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
5893 * @brief TIM Callbacks functions
5894 *
5895 @verbatim
5896 ==============================================================================
5897 ##### TIM Callbacks functions #####
5898 ==============================================================================
5899 [..]
5900 This section provides TIM callback functions:
5901 (+) TIM Period elapsed callback
5902 (+) TIM Output Compare callback
5903 (+) TIM Input capture callback
5904 (+) TIM Trigger callback
5905 (+) TIM Error callback
5906 (+) TIM Index callback
5907 (+) TIM Direction change callback
5908 (+) TIM Index error callback
5909 (+) TIM Transition error callback
5910
5911 @endverbatim
5912 * @{
5913 */
5914
5915 /**
5916 * @brief Period elapsed callback in non-blocking mode
5917 * @param htim TIM handle
5918 * @retval None
5919 */
HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef * htim)5920 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
5921 {
5922 /* Prevent unused argument(s) compilation warning */
5923 UNUSED(htim);
5924
5925 /* NOTE : This function should not be modified, when the callback is needed,
5926 the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
5927 */
5928 }
5929
5930 /**
5931 * @brief Period elapsed half complete callback in non-blocking mode
5932 * @param htim TIM handle
5933 * @retval None
5934 */
HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef * htim)5935 __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
5936 {
5937 /* Prevent unused argument(s) compilation warning */
5938 UNUSED(htim);
5939
5940 /* NOTE : This function should not be modified, when the callback is needed,
5941 the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
5942 */
5943 }
5944
5945 /**
5946 * @brief Output Compare callback in non-blocking mode
5947 * @param htim TIM OC handle
5948 * @retval None
5949 */
HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef * htim)5950 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
5951 {
5952 /* Prevent unused argument(s) compilation warning */
5953 UNUSED(htim);
5954
5955 /* NOTE : This function should not be modified, when the callback is needed,
5956 the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
5957 */
5958 }
5959
5960 /**
5961 * @brief Input Capture callback in non-blocking mode
5962 * @param htim TIM IC handle
5963 * @retval None
5964 */
HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef * htim)5965 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
5966 {
5967 /* Prevent unused argument(s) compilation warning */
5968 UNUSED(htim);
5969
5970 /* NOTE : This function should not be modified, when the callback is needed,
5971 the HAL_TIM_IC_CaptureCallback could be implemented in the user file
5972 */
5973 }
5974
5975 /**
5976 * @brief Input Capture half complete callback in non-blocking mode
5977 * @param htim TIM IC handle
5978 * @retval None
5979 */
HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef * htim)5980 __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
5981 {
5982 /* Prevent unused argument(s) compilation warning */
5983 UNUSED(htim);
5984
5985 /* NOTE : This function should not be modified, when the callback is needed,
5986 the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
5987 */
5988 }
5989
5990 /**
5991 * @brief PWM Pulse finished callback in non-blocking mode
5992 * @param htim TIM handle
5993 * @retval None
5994 */
HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef * htim)5995 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
5996 {
5997 /* Prevent unused argument(s) compilation warning */
5998 UNUSED(htim);
5999
6000 /* NOTE : This function should not be modified, when the callback is needed,
6001 the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
6002 */
6003 }
6004
6005 /**
6006 * @brief PWM Pulse finished half complete callback in non-blocking mode
6007 * @param htim TIM handle
6008 * @retval None
6009 */
HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef * htim)6010 __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
6011 {
6012 /* Prevent unused argument(s) compilation warning */
6013 UNUSED(htim);
6014
6015 /* NOTE : This function should not be modified, when the callback is needed,
6016 the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
6017 */
6018 }
6019
6020 /**
6021 * @brief Hall Trigger detection callback in non-blocking mode
6022 * @param htim TIM handle
6023 * @retval None
6024 */
HAL_TIM_TriggerCallback(TIM_HandleTypeDef * htim)6025 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
6026 {
6027 /* Prevent unused argument(s) compilation warning */
6028 UNUSED(htim);
6029
6030 /* NOTE : This function should not be modified, when the callback is needed,
6031 the HAL_TIM_TriggerCallback could be implemented in the user file
6032 */
6033 }
6034
6035 /**
6036 * @brief Hall Trigger detection half complete callback in non-blocking mode
6037 * @param htim TIM handle
6038 * @retval None
6039 */
HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef * htim)6040 __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
6041 {
6042 /* Prevent unused argument(s) compilation warning */
6043 UNUSED(htim);
6044
6045 /* NOTE : This function should not be modified, when the callback is needed,
6046 the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
6047 */
6048 }
6049
6050 /**
6051 * @brief Timer error callback in non-blocking mode
6052 * @param htim TIM handle
6053 * @retval None
6054 */
HAL_TIM_ErrorCallback(TIM_HandleTypeDef * htim)6055 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
6056 {
6057 /* Prevent unused argument(s) compilation warning */
6058 UNUSED(htim);
6059
6060 /* NOTE : This function should not be modified, when the callback is needed,
6061 the HAL_TIM_ErrorCallback could be implemented in the user file
6062 */
6063 }
6064
6065 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6066 /**
6067 * @brief Register a User TIM callback to be used instead of the weak predefined callback
6068 * @param htim tim handle
6069 * @param CallbackID ID of the callback to be registered
6070 * This parameter can be one of the following values:
6071 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
6072 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
6073 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
6074 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
6075 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
6076 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
6077 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
6078 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
6079 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
6080 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
6081 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
6082 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
6083 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
6084 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
6085 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
6086 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
6087 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
6088 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
6089 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
6090 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
6091 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
6092 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
6093 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
6094 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
6095 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
6096 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
6097 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
6098 * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
6099 * @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID
6100 * @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID
6101 * @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID
6102 * @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID
6103 * @param pCallback pointer to the callback function
6104 * @retval status
6105 */
HAL_TIM_RegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID,pTIM_CallbackTypeDef pCallback)6106 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
6107 pTIM_CallbackTypeDef pCallback)
6108 {
6109 HAL_StatusTypeDef status = HAL_OK;
6110
6111 if (pCallback == NULL)
6112 {
6113 return HAL_ERROR;
6114 }
6115 /* Process locked */
6116 __HAL_LOCK(htim);
6117
6118 if (htim->State == HAL_TIM_STATE_READY)
6119 {
6120 switch (CallbackID)
6121 {
6122 case HAL_TIM_BASE_MSPINIT_CB_ID :
6123 htim->Base_MspInitCallback = pCallback;
6124 break;
6125
6126 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6127 htim->Base_MspDeInitCallback = pCallback;
6128 break;
6129
6130 case HAL_TIM_IC_MSPINIT_CB_ID :
6131 htim->IC_MspInitCallback = pCallback;
6132 break;
6133
6134 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6135 htim->IC_MspDeInitCallback = pCallback;
6136 break;
6137
6138 case HAL_TIM_OC_MSPINIT_CB_ID :
6139 htim->OC_MspInitCallback = pCallback;
6140 break;
6141
6142 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6143 htim->OC_MspDeInitCallback = pCallback;
6144 break;
6145
6146 case HAL_TIM_PWM_MSPINIT_CB_ID :
6147 htim->PWM_MspInitCallback = pCallback;
6148 break;
6149
6150 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6151 htim->PWM_MspDeInitCallback = pCallback;
6152 break;
6153
6154 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6155 htim->OnePulse_MspInitCallback = pCallback;
6156 break;
6157
6158 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6159 htim->OnePulse_MspDeInitCallback = pCallback;
6160 break;
6161
6162 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6163 htim->Encoder_MspInitCallback = pCallback;
6164 break;
6165
6166 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6167 htim->Encoder_MspDeInitCallback = pCallback;
6168 break;
6169
6170 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6171 htim->HallSensor_MspInitCallback = pCallback;
6172 break;
6173
6174 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6175 htim->HallSensor_MspDeInitCallback = pCallback;
6176 break;
6177
6178 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
6179 htim->PeriodElapsedCallback = pCallback;
6180 break;
6181
6182 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
6183 htim->PeriodElapsedHalfCpltCallback = pCallback;
6184 break;
6185
6186 case HAL_TIM_TRIGGER_CB_ID :
6187 htim->TriggerCallback = pCallback;
6188 break;
6189
6190 case HAL_TIM_TRIGGER_HALF_CB_ID :
6191 htim->TriggerHalfCpltCallback = pCallback;
6192 break;
6193
6194 case HAL_TIM_IC_CAPTURE_CB_ID :
6195 htim->IC_CaptureCallback = pCallback;
6196 break;
6197
6198 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
6199 htim->IC_CaptureHalfCpltCallback = pCallback;
6200 break;
6201
6202 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
6203 htim->OC_DelayElapsedCallback = pCallback;
6204 break;
6205
6206 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
6207 htim->PWM_PulseFinishedCallback = pCallback;
6208 break;
6209
6210 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
6211 htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
6212 break;
6213
6214 case HAL_TIM_ERROR_CB_ID :
6215 htim->ErrorCallback = pCallback;
6216 break;
6217
6218 case HAL_TIM_COMMUTATION_CB_ID :
6219 htim->CommutationCallback = pCallback;
6220 break;
6221
6222 case HAL_TIM_COMMUTATION_HALF_CB_ID :
6223 htim->CommutationHalfCpltCallback = pCallback;
6224 break;
6225
6226 case HAL_TIM_BREAK_CB_ID :
6227 htim->BreakCallback = pCallback;
6228 break;
6229
6230 case HAL_TIM_BREAK2_CB_ID :
6231 htim->Break2Callback = pCallback;
6232 break;
6233
6234 case HAL_TIM_ENCODER_INDEX_CB_ID :
6235 htim->EncoderIndexCallback = pCallback;
6236 break;
6237
6238 case HAL_TIM_DIRECTION_CHANGE_CB_ID :
6239 htim->DirectionChangeCallback = pCallback;
6240 break;
6241
6242 case HAL_TIM_INDEX_ERROR_CB_ID :
6243 htim->IndexErrorCallback = pCallback;
6244 break;
6245
6246 case HAL_TIM_TRANSITION_ERROR_CB_ID :
6247 htim->TransitionErrorCallback = pCallback;
6248 break;
6249
6250 default :
6251 /* Return error status */
6252 status = HAL_ERROR;
6253 break;
6254 }
6255 }
6256 else if (htim->State == HAL_TIM_STATE_RESET)
6257 {
6258 switch (CallbackID)
6259 {
6260 case HAL_TIM_BASE_MSPINIT_CB_ID :
6261 htim->Base_MspInitCallback = pCallback;
6262 break;
6263
6264 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6265 htim->Base_MspDeInitCallback = pCallback;
6266 break;
6267
6268 case HAL_TIM_IC_MSPINIT_CB_ID :
6269 htim->IC_MspInitCallback = pCallback;
6270 break;
6271
6272 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6273 htim->IC_MspDeInitCallback = pCallback;
6274 break;
6275
6276 case HAL_TIM_OC_MSPINIT_CB_ID :
6277 htim->OC_MspInitCallback = pCallback;
6278 break;
6279
6280 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6281 htim->OC_MspDeInitCallback = pCallback;
6282 break;
6283
6284 case HAL_TIM_PWM_MSPINIT_CB_ID :
6285 htim->PWM_MspInitCallback = pCallback;
6286 break;
6287
6288 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6289 htim->PWM_MspDeInitCallback = pCallback;
6290 break;
6291
6292 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6293 htim->OnePulse_MspInitCallback = pCallback;
6294 break;
6295
6296 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6297 htim->OnePulse_MspDeInitCallback = pCallback;
6298 break;
6299
6300 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6301 htim->Encoder_MspInitCallback = pCallback;
6302 break;
6303
6304 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6305 htim->Encoder_MspDeInitCallback = pCallback;
6306 break;
6307
6308 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6309 htim->HallSensor_MspInitCallback = pCallback;
6310 break;
6311
6312 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6313 htim->HallSensor_MspDeInitCallback = pCallback;
6314 break;
6315
6316 default :
6317 /* Return error status */
6318 status = HAL_ERROR;
6319 break;
6320 }
6321 }
6322 else
6323 {
6324 /* Return error status */
6325 status = HAL_ERROR;
6326 }
6327
6328 /* Release Lock */
6329 __HAL_UNLOCK(htim);
6330
6331 return status;
6332 }
6333
6334 /**
6335 * @brief Unregister a TIM callback
6336 * TIM callback is redirected to the weak predefined callback
6337 * @param htim tim handle
6338 * @param CallbackID ID of the callback to be unregistered
6339 * This parameter can be one of the following values:
6340 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
6341 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
6342 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
6343 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
6344 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
6345 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
6346 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
6347 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
6348 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
6349 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
6350 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
6351 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
6352 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
6353 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
6354 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
6355 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
6356 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
6357 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
6358 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
6359 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
6360 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
6361 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
6362 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
6363 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
6364 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
6365 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
6366 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
6367 * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
6368 * @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID
6369 * @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID
6370 * @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID
6371 * @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID
6372 * @retval status
6373 */
HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID)6374 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
6375 {
6376 HAL_StatusTypeDef status = HAL_OK;
6377
6378 /* Process locked */
6379 __HAL_LOCK(htim);
6380
6381 if (htim->State == HAL_TIM_STATE_READY)
6382 {
6383 switch (CallbackID)
6384 {
6385 case HAL_TIM_BASE_MSPINIT_CB_ID :
6386 /* Legacy weak Base MspInit Callback */
6387 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
6388 break;
6389
6390 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6391 /* Legacy weak Base Msp DeInit Callback */
6392 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
6393 break;
6394
6395 case HAL_TIM_IC_MSPINIT_CB_ID :
6396 /* Legacy weak IC Msp Init Callback */
6397 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
6398 break;
6399
6400 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6401 /* Legacy weak IC Msp DeInit Callback */
6402 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
6403 break;
6404
6405 case HAL_TIM_OC_MSPINIT_CB_ID :
6406 /* Legacy weak OC Msp Init Callback */
6407 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
6408 break;
6409
6410 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6411 /* Legacy weak OC Msp DeInit Callback */
6412 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
6413 break;
6414
6415 case HAL_TIM_PWM_MSPINIT_CB_ID :
6416 /* Legacy weak PWM Msp Init Callback */
6417 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
6418 break;
6419
6420 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6421 /* Legacy weak PWM Msp DeInit Callback */
6422 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
6423 break;
6424
6425 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6426 /* Legacy weak One Pulse Msp Init Callback */
6427 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
6428 break;
6429
6430 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6431 /* Legacy weak One Pulse Msp DeInit Callback */
6432 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
6433 break;
6434
6435 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6436 /* Legacy weak Encoder Msp Init Callback */
6437 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
6438 break;
6439
6440 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6441 /* Legacy weak Encoder Msp DeInit Callback */
6442 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
6443 break;
6444
6445 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6446 /* Legacy weak Hall Sensor Msp Init Callback */
6447 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
6448 break;
6449
6450 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6451 /* Legacy weak Hall Sensor Msp DeInit Callback */
6452 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
6453 break;
6454
6455 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
6456 /* Legacy weak Period Elapsed Callback */
6457 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
6458 break;
6459
6460 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
6461 /* Legacy weak Period Elapsed half complete Callback */
6462 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
6463 break;
6464
6465 case HAL_TIM_TRIGGER_CB_ID :
6466 /* Legacy weak Trigger Callback */
6467 htim->TriggerCallback = HAL_TIM_TriggerCallback;
6468 break;
6469
6470 case HAL_TIM_TRIGGER_HALF_CB_ID :
6471 /* Legacy weak Trigger half complete Callback */
6472 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
6473 break;
6474
6475 case HAL_TIM_IC_CAPTURE_CB_ID :
6476 /* Legacy weak IC Capture Callback */
6477 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
6478 break;
6479
6480 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
6481 /* Legacy weak IC Capture half complete Callback */
6482 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
6483 break;
6484
6485 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
6486 /* Legacy weak OC Delay Elapsed Callback */
6487 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
6488 break;
6489
6490 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
6491 /* Legacy weak PWM Pulse Finished Callback */
6492 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
6493 break;
6494
6495 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
6496 /* Legacy weak PWM Pulse Finished half complete Callback */
6497 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
6498 break;
6499
6500 case HAL_TIM_ERROR_CB_ID :
6501 /* Legacy weak Error Callback */
6502 htim->ErrorCallback = HAL_TIM_ErrorCallback;
6503 break;
6504
6505 case HAL_TIM_COMMUTATION_CB_ID :
6506 /* Legacy weak Commutation Callback */
6507 htim->CommutationCallback = HAL_TIMEx_CommutCallback;
6508 break;
6509
6510 case HAL_TIM_COMMUTATION_HALF_CB_ID :
6511 /* Legacy weak Commutation half complete Callback */
6512 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
6513 break;
6514
6515 case HAL_TIM_BREAK_CB_ID :
6516 /* Legacy weak Break Callback */
6517 htim->BreakCallback = HAL_TIMEx_BreakCallback;
6518 break;
6519
6520 case HAL_TIM_BREAK2_CB_ID :
6521 /* Legacy weak Break2 Callback */
6522 htim->Break2Callback = HAL_TIMEx_Break2Callback;
6523 break;
6524
6525 case HAL_TIM_ENCODER_INDEX_CB_ID :
6526 /* Legacy weak Encoder Index Callback */
6527 htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback;
6528 break;
6529
6530 case HAL_TIM_DIRECTION_CHANGE_CB_ID :
6531 /* Legacy weak Direction Change Callback */
6532 htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback;
6533 break;
6534
6535 case HAL_TIM_INDEX_ERROR_CB_ID :
6536 /* Legacy weak Index Error Callback */
6537 htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback;
6538 break;
6539
6540 case HAL_TIM_TRANSITION_ERROR_CB_ID :
6541 /* Legacy weak Transition Error Callback */
6542 htim->TransitionErrorCallback = HAL_TIMEx_TransitionErrorCallback;
6543 break;
6544
6545 default :
6546 /* Return error status */
6547 status = HAL_ERROR;
6548 break;
6549 }
6550 }
6551 else if (htim->State == HAL_TIM_STATE_RESET)
6552 {
6553 switch (CallbackID)
6554 {
6555 case HAL_TIM_BASE_MSPINIT_CB_ID :
6556 /* Legacy weak Base MspInit Callback */
6557 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
6558 break;
6559
6560 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6561 /* Legacy weak Base Msp DeInit Callback */
6562 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
6563 break;
6564
6565 case HAL_TIM_IC_MSPINIT_CB_ID :
6566 /* Legacy weak IC Msp Init Callback */
6567 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
6568 break;
6569
6570 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6571 /* Legacy weak IC Msp DeInit Callback */
6572 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
6573 break;
6574
6575 case HAL_TIM_OC_MSPINIT_CB_ID :
6576 /* Legacy weak OC Msp Init Callback */
6577 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
6578 break;
6579
6580 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6581 /* Legacy weak OC Msp DeInit Callback */
6582 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
6583 break;
6584
6585 case HAL_TIM_PWM_MSPINIT_CB_ID :
6586 /* Legacy weak PWM Msp Init Callback */
6587 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
6588 break;
6589
6590 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6591 /* Legacy weak PWM Msp DeInit Callback */
6592 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
6593 break;
6594
6595 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6596 /* Legacy weak One Pulse Msp Init Callback */
6597 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
6598 break;
6599
6600 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6601 /* Legacy weak One Pulse Msp DeInit Callback */
6602 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
6603 break;
6604
6605 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6606 /* Legacy weak Encoder Msp Init Callback */
6607 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
6608 break;
6609
6610 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6611 /* Legacy weak Encoder Msp DeInit Callback */
6612 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
6613 break;
6614
6615 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6616 /* Legacy weak Hall Sensor Msp Init Callback */
6617 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
6618 break;
6619
6620 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6621 /* Legacy weak Hall Sensor Msp DeInit Callback */
6622 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
6623 break;
6624
6625 default :
6626 /* Return error status */
6627 status = HAL_ERROR;
6628 break;
6629 }
6630 }
6631 else
6632 {
6633 /* Return error status */
6634 status = HAL_ERROR;
6635 }
6636
6637 /* Release Lock */
6638 __HAL_UNLOCK(htim);
6639
6640 return status;
6641 }
6642 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6643
6644 /**
6645 * @}
6646 */
6647
6648 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
6649 * @brief TIM Peripheral State functions
6650 *
6651 @verbatim
6652 ==============================================================================
6653 ##### Peripheral State functions #####
6654 ==============================================================================
6655 [..]
6656 This subsection permits to get in run-time the status of the peripheral
6657 and the data flow.
6658
6659 @endverbatim
6660 * @{
6661 */
6662
6663 /**
6664 * @brief Return the TIM Base handle state.
6665 * @param htim TIM Base handle
6666 * @retval HAL state
6667 */
HAL_TIM_Base_GetState(TIM_HandleTypeDef * htim)6668 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
6669 {
6670 return htim->State;
6671 }
6672
6673 /**
6674 * @brief Return the TIM OC handle state.
6675 * @param htim TIM Output Compare handle
6676 * @retval HAL state
6677 */
HAL_TIM_OC_GetState(TIM_HandleTypeDef * htim)6678 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
6679 {
6680 return htim->State;
6681 }
6682
6683 /**
6684 * @brief Return the TIM PWM handle state.
6685 * @param htim TIM handle
6686 * @retval HAL state
6687 */
HAL_TIM_PWM_GetState(TIM_HandleTypeDef * htim)6688 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
6689 {
6690 return htim->State;
6691 }
6692
6693 /**
6694 * @brief Return the TIM Input Capture handle state.
6695 * @param htim TIM IC handle
6696 * @retval HAL state
6697 */
HAL_TIM_IC_GetState(TIM_HandleTypeDef * htim)6698 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
6699 {
6700 return htim->State;
6701 }
6702
6703 /**
6704 * @brief Return the TIM One Pulse Mode handle state.
6705 * @param htim TIM OPM handle
6706 * @retval HAL state
6707 */
HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef * htim)6708 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
6709 {
6710 return htim->State;
6711 }
6712
6713 /**
6714 * @brief Return the TIM Encoder Mode handle state.
6715 * @param htim TIM Encoder Interface handle
6716 * @retval HAL state
6717 */
HAL_TIM_Encoder_GetState(TIM_HandleTypeDef * htim)6718 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
6719 {
6720 return htim->State;
6721 }
6722
6723 /**
6724 * @brief Return the TIM Encoder Mode handle state.
6725 * @param htim TIM handle
6726 * @retval Active channel
6727 */
HAL_TIM_GetActiveChannel(TIM_HandleTypeDef * htim)6728 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim)
6729 {
6730 return htim->Channel;
6731 }
6732
6733 /**
6734 * @brief Return actual state of the TIM channel.
6735 * @param htim TIM handle
6736 * @param Channel TIM Channel
6737 * This parameter can be one of the following values:
6738 * @arg TIM_CHANNEL_1: TIM Channel 1
6739 * @arg TIM_CHANNEL_2: TIM Channel 2
6740 * @arg TIM_CHANNEL_3: TIM Channel 3
6741 * @arg TIM_CHANNEL_4: TIM Channel 4
6742 * @arg TIM_CHANNEL_5: TIM Channel 5
6743 * @arg TIM_CHANNEL_6: TIM Channel 6
6744 * @retval TIM Channel state
6745 */
HAL_TIM_GetChannelState(TIM_HandleTypeDef * htim,uint32_t Channel)6746 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel)
6747 {
6748 HAL_TIM_ChannelStateTypeDef channel_state;
6749
6750 /* Check the parameters */
6751 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
6752
6753 channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
6754
6755 return channel_state;
6756 }
6757
6758 /**
6759 * @brief Return actual state of a DMA burst operation.
6760 * @param htim TIM handle
6761 * @retval DMA burst state
6762 */
HAL_TIM_DMABurstState(TIM_HandleTypeDef * htim)6763 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim)
6764 {
6765 /* Check the parameters */
6766 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
6767
6768 return htim->DMABurstState;
6769 }
6770
6771 /**
6772 * @}
6773 */
6774
6775 /**
6776 * @}
6777 */
6778
6779 /** @defgroup TIM_Private_Functions TIM Private Functions
6780 * @{
6781 */
6782
6783 /**
6784 * @brief TIM DMA error callback
6785 * @param hdma pointer to DMA handle.
6786 * @retval None
6787 */
TIM_DMAError(DMA_HandleTypeDef * hdma)6788 void TIM_DMAError(DMA_HandleTypeDef *hdma)
6789 {
6790 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6791
6792 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6793 {
6794 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6795 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6796 }
6797 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6798 {
6799 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6800 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6801 }
6802 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6803 {
6804 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6805 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6806 }
6807 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6808 {
6809 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6810 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6811 }
6812 else
6813 {
6814 htim->State = HAL_TIM_STATE_READY;
6815 }
6816
6817 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6818 htim->ErrorCallback(htim);
6819 #else
6820 HAL_TIM_ErrorCallback(htim);
6821 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6822
6823 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6824 }
6825
6826 /**
6827 * @brief TIM DMA Delay Pulse complete callback.
6828 * @param hdma pointer to DMA handle.
6829 * @retval None
6830 */
TIM_DMADelayPulseCplt(DMA_HandleTypeDef * hdma)6831 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
6832 {
6833 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6834
6835 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6836 {
6837 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6838
6839 if (hdma->Init.Mode == DMA_NORMAL)
6840 {
6841 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6842 }
6843 }
6844 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6845 {
6846 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6847
6848 if (hdma->Init.Mode == DMA_NORMAL)
6849 {
6850 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6851 }
6852 }
6853 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6854 {
6855 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6856
6857 if (hdma->Init.Mode == DMA_NORMAL)
6858 {
6859 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6860 }
6861 }
6862 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6863 {
6864 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6865
6866 if (hdma->Init.Mode == DMA_NORMAL)
6867 {
6868 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6869 }
6870 }
6871 else
6872 {
6873 /* nothing to do */
6874 }
6875
6876 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6877 htim->PWM_PulseFinishedCallback(htim);
6878 #else
6879 HAL_TIM_PWM_PulseFinishedCallback(htim);
6880 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6881
6882 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6883 }
6884
6885 /**
6886 * @brief TIM DMA Delay Pulse half complete callback.
6887 * @param hdma pointer to DMA handle.
6888 * @retval None
6889 */
TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef * hdma)6890 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
6891 {
6892 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6893
6894 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6895 {
6896 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6897 }
6898 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6899 {
6900 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6901 }
6902 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6903 {
6904 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6905 }
6906 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6907 {
6908 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6909 }
6910 else
6911 {
6912 /* nothing to do */
6913 }
6914
6915 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6916 htim->PWM_PulseFinishedHalfCpltCallback(htim);
6917 #else
6918 HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
6919 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6920
6921 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6922 }
6923
6924 /**
6925 * @brief TIM DMA Capture complete callback.
6926 * @param hdma pointer to DMA handle.
6927 * @retval None
6928 */
TIM_DMACaptureCplt(DMA_HandleTypeDef * hdma)6929 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
6930 {
6931 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6932
6933 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6934 {
6935 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6936
6937 if (hdma->Init.Mode == DMA_NORMAL)
6938 {
6939 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6940 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6941 }
6942 }
6943 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6944 {
6945 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6946
6947 if (hdma->Init.Mode == DMA_NORMAL)
6948 {
6949 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6950 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6951 }
6952 }
6953 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6954 {
6955 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6956
6957 if (hdma->Init.Mode == DMA_NORMAL)
6958 {
6959 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6960 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6961 }
6962 }
6963 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6964 {
6965 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6966
6967 if (hdma->Init.Mode == DMA_NORMAL)
6968 {
6969 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6970 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6971 }
6972 }
6973 else
6974 {
6975 /* nothing to do */
6976 }
6977
6978 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6979 htim->IC_CaptureCallback(htim);
6980 #else
6981 HAL_TIM_IC_CaptureCallback(htim);
6982 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6983
6984 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6985 }
6986
6987 /**
6988 * @brief TIM DMA Capture half complete callback.
6989 * @param hdma pointer to DMA handle.
6990 * @retval None
6991 */
TIM_DMACaptureHalfCplt(DMA_HandleTypeDef * hdma)6992 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
6993 {
6994 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6995
6996 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6997 {
6998 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6999 }
7000 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
7001 {
7002 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
7003 }
7004 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
7005 {
7006 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
7007 }
7008 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
7009 {
7010 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
7011 }
7012 else
7013 {
7014 /* nothing to do */
7015 }
7016
7017 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7018 htim->IC_CaptureHalfCpltCallback(htim);
7019 #else
7020 HAL_TIM_IC_CaptureHalfCpltCallback(htim);
7021 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7022
7023 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
7024 }
7025
7026 /**
7027 * @brief TIM DMA Period Elapse complete callback.
7028 * @param hdma pointer to DMA handle.
7029 * @retval None
7030 */
TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef * hdma)7031 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
7032 {
7033 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7034
7035 if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
7036 {
7037 htim->State = HAL_TIM_STATE_READY;
7038 }
7039
7040 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7041 htim->PeriodElapsedCallback(htim);
7042 #else
7043 HAL_TIM_PeriodElapsedCallback(htim);
7044 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7045 }
7046
7047 /**
7048 * @brief TIM DMA Period Elapse half complete callback.
7049 * @param hdma pointer to DMA handle.
7050 * @retval None
7051 */
TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef * hdma)7052 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
7053 {
7054 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7055
7056 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7057 htim->PeriodElapsedHalfCpltCallback(htim);
7058 #else
7059 HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
7060 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7061 }
7062
7063 /**
7064 * @brief TIM DMA Trigger callback.
7065 * @param hdma pointer to DMA handle.
7066 * @retval None
7067 */
TIM_DMATriggerCplt(DMA_HandleTypeDef * hdma)7068 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
7069 {
7070 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7071
7072 if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
7073 {
7074 htim->State = HAL_TIM_STATE_READY;
7075 }
7076
7077 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7078 htim->TriggerCallback(htim);
7079 #else
7080 HAL_TIM_TriggerCallback(htim);
7081 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7082 }
7083
7084 /**
7085 * @brief TIM DMA Trigger half complete callback.
7086 * @param hdma pointer to DMA handle.
7087 * @retval None
7088 */
TIM_DMATriggerHalfCplt(DMA_HandleTypeDef * hdma)7089 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
7090 {
7091 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7092
7093 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7094 htim->TriggerHalfCpltCallback(htim);
7095 #else
7096 HAL_TIM_TriggerHalfCpltCallback(htim);
7097 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7098 }
7099
7100 /**
7101 * @brief Time Base configuration
7102 * @param TIMx TIM peripheral
7103 * @param Structure TIM Base configuration structure
7104 * @retval None
7105 */
TIM_Base_SetConfig(TIM_TypeDef * TIMx,TIM_Base_InitTypeDef * Structure)7106 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
7107 {
7108 uint32_t tmpcr1;
7109 tmpcr1 = TIMx->CR1;
7110
7111 /* Set TIM Time Base Unit parameters ---------------------------------------*/
7112 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
7113 {
7114 /* Select the Counter Mode */
7115 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
7116 tmpcr1 |= Structure->CounterMode;
7117 }
7118
7119 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
7120 {
7121 /* Set the clock division */
7122 tmpcr1 &= ~TIM_CR1_CKD;
7123 tmpcr1 |= (uint32_t)Structure->ClockDivision;
7124 }
7125
7126 /* Set the auto-reload preload */
7127 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
7128
7129 TIMx->CR1 = tmpcr1;
7130
7131 /* Set the Autoreload value */
7132 TIMx->ARR = (uint32_t)Structure->Period ;
7133
7134 /* Set the Prescaler value */
7135 TIMx->PSC = Structure->Prescaler;
7136
7137 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
7138 {
7139 /* Set the Repetition Counter value */
7140 TIMx->RCR = Structure->RepetitionCounter;
7141 }
7142
7143 /* Generate an update event to reload the Prescaler
7144 and the repetition counter (only for advanced timer) value immediately */
7145 TIMx->EGR = TIM_EGR_UG;
7146 }
7147
7148 /**
7149 * @brief Timer Output Compare 1 configuration
7150 * @param TIMx to select the TIM peripheral
7151 * @param OC_Config The output configuration structure
7152 * @retval None
7153 */
TIM_OC1_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)7154 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
7155 {
7156 uint32_t tmpccmrx;
7157 uint32_t tmpccer;
7158 uint32_t tmpcr2;
7159
7160 /* Disable the Channel 1: Reset the CC1E Bit */
7161 TIMx->CCER &= ~TIM_CCER_CC1E;
7162
7163 /* Get the TIMx CCER register value */
7164 tmpccer = TIMx->CCER;
7165 /* Get the TIMx CR2 register value */
7166 tmpcr2 = TIMx->CR2;
7167
7168 /* Get the TIMx CCMR1 register value */
7169 tmpccmrx = TIMx->CCMR1;
7170
7171 /* Reset the Output Compare Mode Bits */
7172 tmpccmrx &= ~TIM_CCMR1_OC1M;
7173 tmpccmrx &= ~TIM_CCMR1_CC1S;
7174 /* Select the Output Compare Mode */
7175 tmpccmrx |= OC_Config->OCMode;
7176
7177 /* Reset the Output Polarity level */
7178 tmpccer &= ~TIM_CCER_CC1P;
7179 /* Set the Output Compare Polarity */
7180 tmpccer |= OC_Config->OCPolarity;
7181
7182 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
7183 {
7184 /* Check parameters */
7185 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7186
7187 /* Reset the Output N Polarity level */
7188 tmpccer &= ~TIM_CCER_CC1NP;
7189 /* Set the Output N Polarity */
7190 tmpccer |= OC_Config->OCNPolarity;
7191 /* Reset the Output N State */
7192 tmpccer &= ~TIM_CCER_CC1NE;
7193 }
7194
7195 if (IS_TIM_BREAK_INSTANCE(TIMx))
7196 {
7197 /* Check parameters */
7198 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7199 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7200
7201 /* Reset the Output Compare and Output Compare N IDLE State */
7202 tmpcr2 &= ~TIM_CR2_OIS1;
7203 tmpcr2 &= ~TIM_CR2_OIS1N;
7204 /* Set the Output Idle state */
7205 tmpcr2 |= OC_Config->OCIdleState;
7206 /* Set the Output N Idle state */
7207 tmpcr2 |= OC_Config->OCNIdleState;
7208 }
7209
7210 /* Write to TIMx CR2 */
7211 TIMx->CR2 = tmpcr2;
7212
7213 /* Write to TIMx CCMR1 */
7214 TIMx->CCMR1 = tmpccmrx;
7215
7216 /* Set the Capture Compare Register value */
7217 TIMx->CCR1 = OC_Config->Pulse;
7218
7219 /* Write to TIMx CCER */
7220 TIMx->CCER = tmpccer;
7221 }
7222
7223 /**
7224 * @brief Timer Output Compare 2 configuration
7225 * @param TIMx to select the TIM peripheral
7226 * @param OC_Config The output configuration structure
7227 * @retval None
7228 */
TIM_OC2_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)7229 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
7230 {
7231 uint32_t tmpccmrx;
7232 uint32_t tmpccer;
7233 uint32_t tmpcr2;
7234
7235 /* Disable the Channel 2: Reset the CC2E Bit */
7236 TIMx->CCER &= ~TIM_CCER_CC2E;
7237
7238 /* Get the TIMx CCER register value */
7239 tmpccer = TIMx->CCER;
7240 /* Get the TIMx CR2 register value */
7241 tmpcr2 = TIMx->CR2;
7242
7243 /* Get the TIMx CCMR1 register value */
7244 tmpccmrx = TIMx->CCMR1;
7245
7246 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7247 tmpccmrx &= ~TIM_CCMR1_OC2M;
7248 tmpccmrx &= ~TIM_CCMR1_CC2S;
7249
7250 /* Select the Output Compare Mode */
7251 tmpccmrx |= (OC_Config->OCMode << 8U);
7252
7253 /* Reset the Output Polarity level */
7254 tmpccer &= ~TIM_CCER_CC2P;
7255 /* Set the Output Compare Polarity */
7256 tmpccer |= (OC_Config->OCPolarity << 4U);
7257
7258 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
7259 {
7260 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7261
7262 /* Reset the Output N Polarity level */
7263 tmpccer &= ~TIM_CCER_CC2NP;
7264 /* Set the Output N Polarity */
7265 tmpccer |= (OC_Config->OCNPolarity << 4U);
7266 /* Reset the Output N State */
7267 tmpccer &= ~TIM_CCER_CC2NE;
7268
7269 }
7270
7271 if (IS_TIM_BREAK_INSTANCE(TIMx))
7272 {
7273 /* Check parameters */
7274 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7275 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7276
7277 /* Reset the Output Compare and Output Compare N IDLE State */
7278 tmpcr2 &= ~TIM_CR2_OIS2;
7279 tmpcr2 &= ~TIM_CR2_OIS2N;
7280 /* Set the Output Idle state */
7281 tmpcr2 |= (OC_Config->OCIdleState << 2U);
7282 /* Set the Output N Idle state */
7283 tmpcr2 |= (OC_Config->OCNIdleState << 2U);
7284 }
7285
7286 /* Write to TIMx CR2 */
7287 TIMx->CR2 = tmpcr2;
7288
7289 /* Write to TIMx CCMR1 */
7290 TIMx->CCMR1 = tmpccmrx;
7291
7292 /* Set the Capture Compare Register value */
7293 TIMx->CCR2 = OC_Config->Pulse;
7294
7295 /* Write to TIMx CCER */
7296 TIMx->CCER = tmpccer;
7297 }
7298
7299 /**
7300 * @brief Timer Output Compare 3 configuration
7301 * @param TIMx to select the TIM peripheral
7302 * @param OC_Config The output configuration structure
7303 * @retval None
7304 */
TIM_OC3_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)7305 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
7306 {
7307 uint32_t tmpccmrx;
7308 uint32_t tmpccer;
7309 uint32_t tmpcr2;
7310
7311 /* Disable the Channel 3: Reset the CC2E Bit */
7312 TIMx->CCER &= ~TIM_CCER_CC3E;
7313
7314 /* Get the TIMx CCER register value */
7315 tmpccer = TIMx->CCER;
7316 /* Get the TIMx CR2 register value */
7317 tmpcr2 = TIMx->CR2;
7318
7319 /* Get the TIMx CCMR2 register value */
7320 tmpccmrx = TIMx->CCMR2;
7321
7322 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7323 tmpccmrx &= ~TIM_CCMR2_OC3M;
7324 tmpccmrx &= ~TIM_CCMR2_CC3S;
7325 /* Select the Output Compare Mode */
7326 tmpccmrx |= OC_Config->OCMode;
7327
7328 /* Reset the Output Polarity level */
7329 tmpccer &= ~TIM_CCER_CC3P;
7330 /* Set the Output Compare Polarity */
7331 tmpccer |= (OC_Config->OCPolarity << 8U);
7332
7333 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
7334 {
7335 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7336
7337 /* Reset the Output N Polarity level */
7338 tmpccer &= ~TIM_CCER_CC3NP;
7339 /* Set the Output N Polarity */
7340 tmpccer |= (OC_Config->OCNPolarity << 8U);
7341 /* Reset the Output N State */
7342 tmpccer &= ~TIM_CCER_CC3NE;
7343 }
7344
7345 if (IS_TIM_BREAK_INSTANCE(TIMx))
7346 {
7347 /* Check parameters */
7348 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7349 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7350
7351 /* Reset the Output Compare and Output Compare N IDLE State */
7352 tmpcr2 &= ~TIM_CR2_OIS3;
7353 tmpcr2 &= ~TIM_CR2_OIS3N;
7354 /* Set the Output Idle state */
7355 tmpcr2 |= (OC_Config->OCIdleState << 4U);
7356 /* Set the Output N Idle state */
7357 tmpcr2 |= (OC_Config->OCNIdleState << 4U);
7358 }
7359
7360 /* Write to TIMx CR2 */
7361 TIMx->CR2 = tmpcr2;
7362
7363 /* Write to TIMx CCMR2 */
7364 TIMx->CCMR2 = tmpccmrx;
7365
7366 /* Set the Capture Compare Register value */
7367 TIMx->CCR3 = OC_Config->Pulse;
7368
7369 /* Write to TIMx CCER */
7370 TIMx->CCER = tmpccer;
7371 }
7372
7373 /**
7374 * @brief Timer Output Compare 4 configuration
7375 * @param TIMx to select the TIM peripheral
7376 * @param OC_Config The output configuration structure
7377 * @retval None
7378 */
TIM_OC4_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)7379 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
7380 {
7381 uint32_t tmpccmrx;
7382 uint32_t tmpccer;
7383 uint32_t tmpcr2;
7384
7385 /* Disable the Channel 4: Reset the CC4E Bit */
7386 TIMx->CCER &= ~TIM_CCER_CC4E;
7387
7388 /* Get the TIMx CCER register value */
7389 tmpccer = TIMx->CCER;
7390 /* Get the TIMx CR2 register value */
7391 tmpcr2 = TIMx->CR2;
7392
7393 /* Get the TIMx CCMR2 register value */
7394 tmpccmrx = TIMx->CCMR2;
7395
7396 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7397 tmpccmrx &= ~TIM_CCMR2_OC4M;
7398 tmpccmrx &= ~TIM_CCMR2_CC4S;
7399
7400 /* Select the Output Compare Mode */
7401 tmpccmrx |= (OC_Config->OCMode << 8U);
7402
7403 /* Reset the Output Polarity level */
7404 tmpccer &= ~TIM_CCER_CC4P;
7405 /* Set the Output Compare Polarity */
7406 tmpccer |= (OC_Config->OCPolarity << 12U);
7407
7408 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_4))
7409 {
7410 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7411
7412 /* Reset the Output N Polarity level */
7413 tmpccer &= ~TIM_CCER_CC4NP;
7414 /* Set the Output N Polarity */
7415 tmpccer |= (OC_Config->OCNPolarity << 12U);
7416 /* Reset the Output N State */
7417 tmpccer &= ~TIM_CCER_CC4NE;
7418 }
7419
7420 if (IS_TIM_BREAK_INSTANCE(TIMx))
7421 {
7422 /* Check parameters */
7423 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7424 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7425
7426 /* Reset the Output Compare IDLE State */
7427 tmpcr2 &= ~TIM_CR2_OIS4;
7428 /* Reset the Output Compare N IDLE State */
7429 tmpcr2 &= ~TIM_CR2_OIS4N;
7430
7431 /* Set the Output Idle state */
7432 tmpcr2 |= (OC_Config->OCIdleState << 6U);
7433 /* Set the Output N Idle state */
7434 tmpcr2 |= (OC_Config->OCNIdleState << 6U);
7435 }
7436
7437 /* Write to TIMx CR2 */
7438 TIMx->CR2 = tmpcr2;
7439
7440 /* Write to TIMx CCMR2 */
7441 TIMx->CCMR2 = tmpccmrx;
7442
7443 /* Set the Capture Compare Register value */
7444 TIMx->CCR4 = OC_Config->Pulse;
7445
7446 /* Write to TIMx CCER */
7447 TIMx->CCER = tmpccer;
7448 }
7449
7450 /**
7451 * @brief Timer Output Compare 5 configuration
7452 * @param TIMx to select the TIM peripheral
7453 * @param OC_Config The output configuration structure
7454 * @retval None
7455 */
TIM_OC5_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)7456 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
7457 TIM_OC_InitTypeDef *OC_Config)
7458 {
7459 uint32_t tmpccmrx;
7460 uint32_t tmpccer;
7461 uint32_t tmpcr2;
7462
7463 /* Disable the output: Reset the CCxE Bit */
7464 TIMx->CCER &= ~TIM_CCER_CC5E;
7465
7466 /* Get the TIMx CCER register value */
7467 tmpccer = TIMx->CCER;
7468 /* Get the TIMx CR2 register value */
7469 tmpcr2 = TIMx->CR2;
7470 /* Get the TIMx CCMR1 register value */
7471 tmpccmrx = TIMx->CCMR3;
7472
7473 /* Reset the Output Compare Mode Bits */
7474 tmpccmrx &= ~(TIM_CCMR3_OC5M);
7475 /* Select the Output Compare Mode */
7476 tmpccmrx |= OC_Config->OCMode;
7477
7478 /* Reset the Output Polarity level */
7479 tmpccer &= ~TIM_CCER_CC5P;
7480 /* Set the Output Compare Polarity */
7481 tmpccer |= (OC_Config->OCPolarity << 16U);
7482
7483 if (IS_TIM_BREAK_INSTANCE(TIMx))
7484 {
7485 /* Reset the Output Compare IDLE State */
7486 tmpcr2 &= ~TIM_CR2_OIS5;
7487 /* Set the Output Idle state */
7488 tmpcr2 |= (OC_Config->OCIdleState << 8U);
7489 }
7490 /* Write to TIMx CR2 */
7491 TIMx->CR2 = tmpcr2;
7492
7493 /* Write to TIMx CCMR3 */
7494 TIMx->CCMR3 = tmpccmrx;
7495
7496 /* Set the Capture Compare Register value */
7497 TIMx->CCR5 = OC_Config->Pulse;
7498
7499 /* Write to TIMx CCER */
7500 TIMx->CCER = tmpccer;
7501 }
7502
7503 /**
7504 * @brief Timer Output Compare 6 configuration
7505 * @param TIMx to select the TIM peripheral
7506 * @param OC_Config The output configuration structure
7507 * @retval None
7508 */
TIM_OC6_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)7509 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
7510 TIM_OC_InitTypeDef *OC_Config)
7511 {
7512 uint32_t tmpccmrx;
7513 uint32_t tmpccer;
7514 uint32_t tmpcr2;
7515
7516 /* Disable the output: Reset the CCxE Bit */
7517 TIMx->CCER &= ~TIM_CCER_CC6E;
7518
7519 /* Get the TIMx CCER register value */
7520 tmpccer = TIMx->CCER;
7521 /* Get the TIMx CR2 register value */
7522 tmpcr2 = TIMx->CR2;
7523 /* Get the TIMx CCMR1 register value */
7524 tmpccmrx = TIMx->CCMR3;
7525
7526 /* Reset the Output Compare Mode Bits */
7527 tmpccmrx &= ~(TIM_CCMR3_OC6M);
7528 /* Select the Output Compare Mode */
7529 tmpccmrx |= (OC_Config->OCMode << 8U);
7530
7531 /* Reset the Output Polarity level */
7532 tmpccer &= (uint32_t)~TIM_CCER_CC6P;
7533 /* Set the Output Compare Polarity */
7534 tmpccer |= (OC_Config->OCPolarity << 20U);
7535
7536 if (IS_TIM_BREAK_INSTANCE(TIMx))
7537 {
7538 /* Reset the Output Compare IDLE State */
7539 tmpcr2 &= ~TIM_CR2_OIS6;
7540 /* Set the Output Idle state */
7541 tmpcr2 |= (OC_Config->OCIdleState << 10U);
7542 }
7543
7544 /* Write to TIMx CR2 */
7545 TIMx->CR2 = tmpcr2;
7546
7547 /* Write to TIMx CCMR3 */
7548 TIMx->CCMR3 = tmpccmrx;
7549
7550 /* Set the Capture Compare Register value */
7551 TIMx->CCR6 = OC_Config->Pulse;
7552
7553 /* Write to TIMx CCER */
7554 TIMx->CCER = tmpccer;
7555 }
7556
7557 /**
7558 * @brief Slave Timer configuration function
7559 * @param htim TIM handle
7560 * @param sSlaveConfig Slave timer configuration
7561 * @retval None
7562 */
TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef * htim,TIM_SlaveConfigTypeDef * sSlaveConfig)7563 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
7564 TIM_SlaveConfigTypeDef *sSlaveConfig)
7565 {
7566 HAL_StatusTypeDef status = HAL_OK;
7567 uint32_t tmpsmcr;
7568 uint32_t tmpccmr1;
7569 uint32_t tmpccer;
7570
7571 /* Get the TIMx SMCR register value */
7572 tmpsmcr = htim->Instance->SMCR;
7573
7574 /* Reset the Trigger Selection Bits */
7575 tmpsmcr &= ~TIM_SMCR_TS;
7576 /* Set the Input Trigger source */
7577 tmpsmcr |= sSlaveConfig->InputTrigger;
7578
7579 /* Reset the slave mode Bits */
7580 tmpsmcr &= ~TIM_SMCR_SMS;
7581 /* Set the slave mode */
7582 tmpsmcr |= sSlaveConfig->SlaveMode;
7583
7584 /* Write to TIMx SMCR */
7585 htim->Instance->SMCR = tmpsmcr;
7586
7587 /* Configure the trigger prescaler, filter, and polarity */
7588 switch (sSlaveConfig->InputTrigger)
7589 {
7590 case TIM_TS_ETRF:
7591 {
7592 /* Check the parameters */
7593 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
7594 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
7595 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7596 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7597 /* Configure the ETR Trigger source */
7598 TIM_ETR_SetConfig(htim->Instance,
7599 sSlaveConfig->TriggerPrescaler,
7600 sSlaveConfig->TriggerPolarity,
7601 sSlaveConfig->TriggerFilter);
7602 break;
7603 }
7604
7605 case TIM_TS_TI1F_ED:
7606 {
7607 /* Check the parameters */
7608 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7609 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7610
7611 if ((sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) || \
7612 (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_COMBINED_GATEDRESET))
7613 {
7614 return HAL_ERROR;
7615 }
7616
7617 /* Disable the Channel 1: Reset the CC1E Bit */
7618 tmpccer = htim->Instance->CCER;
7619 htim->Instance->CCER &= ~TIM_CCER_CC1E;
7620 tmpccmr1 = htim->Instance->CCMR1;
7621
7622 /* Set the filter */
7623 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7624 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
7625
7626 /* Write to TIMx CCMR1 and CCER registers */
7627 htim->Instance->CCMR1 = tmpccmr1;
7628 htim->Instance->CCER = tmpccer;
7629 break;
7630 }
7631
7632 case TIM_TS_TI1FP1:
7633 {
7634 /* Check the parameters */
7635 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7636 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7637 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7638
7639 /* Configure TI1 Filter and Polarity */
7640 TIM_TI1_ConfigInputStage(htim->Instance,
7641 sSlaveConfig->TriggerPolarity,
7642 sSlaveConfig->TriggerFilter);
7643 break;
7644 }
7645
7646 case TIM_TS_TI2FP2:
7647 {
7648 /* Check the parameters */
7649 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
7650 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7651 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7652
7653 /* Configure TI2 Filter and Polarity */
7654 TIM_TI2_ConfigInputStage(htim->Instance,
7655 sSlaveConfig->TriggerPolarity,
7656 sSlaveConfig->TriggerFilter);
7657 break;
7658 }
7659
7660 case TIM_TS_ITR0:
7661 case TIM_TS_ITR1:
7662 case TIM_TS_ITR2:
7663 case TIM_TS_ITR3:
7664 #if defined (TIM5)
7665 case TIM_TS_ITR4:
7666 #endif /* TIM5 */
7667 case TIM_TS_ITR5:
7668 case TIM_TS_ITR6:
7669 case TIM_TS_ITR7:
7670 case TIM_TS_ITR8:
7671 #if defined (TIM20)
7672 case TIM_TS_ITR9:
7673 #endif /* TIM20 */
7674 #if defined (HRTIM1)
7675 case TIM_TS_ITR10:
7676 #endif /* HRTIM1 */
7677 case TIM_TS_ITR11:
7678 {
7679 /* Check the parameter */
7680 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE((htim->Instance), sSlaveConfig->InputTrigger));
7681 break;
7682 }
7683
7684 default:
7685 status = HAL_ERROR;
7686 break;
7687 }
7688
7689 return status;
7690 }
7691
7692 /**
7693 * @brief Configure the TI1 as Input.
7694 * @param TIMx to select the TIM peripheral.
7695 * @param TIM_ICPolarity The Input Polarity.
7696 * This parameter can be one of the following values:
7697 * @arg TIM_ICPOLARITY_RISING
7698 * @arg TIM_ICPOLARITY_FALLING
7699 * @arg TIM_ICPOLARITY_BOTHEDGE
7700 * @param TIM_ICSelection specifies the input to be used.
7701 * This parameter can be one of the following values:
7702 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
7703 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
7704 * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
7705 * @param TIM_ICFilter Specifies the Input Capture Filter.
7706 * This parameter must be a value between 0x00 and 0x0F.
7707 * @retval None
7708 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
7709 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
7710 * protected against un-initialized filter and polarity values.
7711 */
TIM_TI1_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7712 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7713 uint32_t TIM_ICFilter)
7714 {
7715 uint32_t tmpccmr1;
7716 uint32_t tmpccer;
7717
7718 /* Disable the Channel 1: Reset the CC1E Bit */
7719 TIMx->CCER &= ~TIM_CCER_CC1E;
7720 tmpccmr1 = TIMx->CCMR1;
7721 tmpccer = TIMx->CCER;
7722
7723 /* Select the Input */
7724 if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
7725 {
7726 tmpccmr1 &= ~TIM_CCMR1_CC1S;
7727 tmpccmr1 |= TIM_ICSelection;
7728 }
7729 else
7730 {
7731 tmpccmr1 |= TIM_CCMR1_CC1S_0;
7732 }
7733
7734 /* Set the filter */
7735 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7736 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
7737
7738 /* Select the Polarity and set the CC1E Bit */
7739 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7740 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
7741
7742 /* Write to TIMx CCMR1 and CCER registers */
7743 TIMx->CCMR1 = tmpccmr1;
7744 TIMx->CCER = tmpccer;
7745 }
7746
7747 /**
7748 * @brief Configure the Polarity and Filter for TI1.
7749 * @param TIMx to select the TIM peripheral.
7750 * @param TIM_ICPolarity The Input Polarity.
7751 * This parameter can be one of the following values:
7752 * @arg TIM_ICPOLARITY_RISING
7753 * @arg TIM_ICPOLARITY_FALLING
7754 * @arg TIM_ICPOLARITY_BOTHEDGE
7755 * @param TIM_ICFilter Specifies the Input Capture Filter.
7756 * This parameter must be a value between 0x00 and 0x0F.
7757 * @retval None
7758 */
TIM_TI1_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)7759 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7760 {
7761 uint32_t tmpccmr1;
7762 uint32_t tmpccer;
7763
7764 /* Disable the Channel 1: Reset the CC1E Bit */
7765 tmpccer = TIMx->CCER;
7766 TIMx->CCER &= ~TIM_CCER_CC1E;
7767 tmpccmr1 = TIMx->CCMR1;
7768
7769 /* Set the filter */
7770 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7771 tmpccmr1 |= (TIM_ICFilter << 4U);
7772
7773 /* Select the Polarity and set the CC1E Bit */
7774 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7775 tmpccer |= TIM_ICPolarity;
7776
7777 /* Write to TIMx CCMR1 and CCER registers */
7778 TIMx->CCMR1 = tmpccmr1;
7779 TIMx->CCER = tmpccer;
7780 }
7781
7782 /**
7783 * @brief Configure the TI2 as Input.
7784 * @param TIMx to select the TIM peripheral
7785 * @param TIM_ICPolarity The Input Polarity.
7786 * This parameter can be one of the following values:
7787 * @arg TIM_ICPOLARITY_RISING
7788 * @arg TIM_ICPOLARITY_FALLING
7789 * @arg TIM_ICPOLARITY_BOTHEDGE
7790 * @param TIM_ICSelection specifies the input to be used.
7791 * This parameter can be one of the following values:
7792 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
7793 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
7794 * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
7795 * @param TIM_ICFilter Specifies the Input Capture Filter.
7796 * This parameter must be a value between 0x00 and 0x0F.
7797 * @retval None
7798 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
7799 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
7800 * protected against un-initialized filter and polarity values.
7801 */
TIM_TI2_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7802 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7803 uint32_t TIM_ICFilter)
7804 {
7805 uint32_t tmpccmr1;
7806 uint32_t tmpccer;
7807
7808 /* Disable the Channel 2: Reset the CC2E Bit */
7809 TIMx->CCER &= ~TIM_CCER_CC2E;
7810 tmpccmr1 = TIMx->CCMR1;
7811 tmpccer = TIMx->CCER;
7812
7813 /* Select the Input */
7814 tmpccmr1 &= ~TIM_CCMR1_CC2S;
7815 tmpccmr1 |= (TIM_ICSelection << 8U);
7816
7817 /* Set the filter */
7818 tmpccmr1 &= ~TIM_CCMR1_IC2F;
7819 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
7820
7821 /* Select the Polarity and set the CC2E Bit */
7822 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7823 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
7824
7825 /* Write to TIMx CCMR1 and CCER registers */
7826 TIMx->CCMR1 = tmpccmr1 ;
7827 TIMx->CCER = tmpccer;
7828 }
7829
7830 /**
7831 * @brief Configure the Polarity and Filter for TI2.
7832 * @param TIMx to select the TIM peripheral.
7833 * @param TIM_ICPolarity The Input Polarity.
7834 * This parameter can be one of the following values:
7835 * @arg TIM_ICPOLARITY_RISING
7836 * @arg TIM_ICPOLARITY_FALLING
7837 * @arg TIM_ICPOLARITY_BOTHEDGE
7838 * @param TIM_ICFilter Specifies the Input Capture Filter.
7839 * This parameter must be a value between 0x00 and 0x0F.
7840 * @retval None
7841 */
TIM_TI2_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)7842 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7843 {
7844 uint32_t tmpccmr1;
7845 uint32_t tmpccer;
7846
7847 /* Disable the Channel 2: Reset the CC2E Bit */
7848 TIMx->CCER &= ~TIM_CCER_CC2E;
7849 tmpccmr1 = TIMx->CCMR1;
7850 tmpccer = TIMx->CCER;
7851
7852 /* Set the filter */
7853 tmpccmr1 &= ~TIM_CCMR1_IC2F;
7854 tmpccmr1 |= (TIM_ICFilter << 12U);
7855
7856 /* Select the Polarity and set the CC2E Bit */
7857 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7858 tmpccer |= (TIM_ICPolarity << 4U);
7859
7860 /* Write to TIMx CCMR1 and CCER registers */
7861 TIMx->CCMR1 = tmpccmr1 ;
7862 TIMx->CCER = tmpccer;
7863 }
7864
7865 /**
7866 * @brief Configure the TI3 as Input.
7867 * @param TIMx to select the TIM peripheral
7868 * @param TIM_ICPolarity The Input Polarity.
7869 * This parameter can be one of the following values:
7870 * @arg TIM_ICPOLARITY_RISING
7871 * @arg TIM_ICPOLARITY_FALLING
7872 * @arg TIM_ICPOLARITY_BOTHEDGE
7873 * @param TIM_ICSelection specifies the input to be used.
7874 * This parameter can be one of the following values:
7875 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
7876 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
7877 * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
7878 * @param TIM_ICFilter Specifies the Input Capture Filter.
7879 * This parameter must be a value between 0x00 and 0x0F.
7880 * @retval None
7881 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
7882 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
7883 * protected against un-initialized filter and polarity values.
7884 */
TIM_TI3_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7885 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7886 uint32_t TIM_ICFilter)
7887 {
7888 uint32_t tmpccmr2;
7889 uint32_t tmpccer;
7890
7891 /* Disable the Channel 3: Reset the CC3E Bit */
7892 TIMx->CCER &= ~TIM_CCER_CC3E;
7893 tmpccmr2 = TIMx->CCMR2;
7894 tmpccer = TIMx->CCER;
7895
7896 /* Select the Input */
7897 tmpccmr2 &= ~TIM_CCMR2_CC3S;
7898 tmpccmr2 |= TIM_ICSelection;
7899
7900 /* Set the filter */
7901 tmpccmr2 &= ~TIM_CCMR2_IC3F;
7902 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
7903
7904 /* Select the Polarity and set the CC3E Bit */
7905 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
7906 tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
7907
7908 /* Write to TIMx CCMR2 and CCER registers */
7909 TIMx->CCMR2 = tmpccmr2;
7910 TIMx->CCER = tmpccer;
7911 }
7912
7913 /**
7914 * @brief Configure the TI4 as Input.
7915 * @param TIMx to select the TIM peripheral
7916 * @param TIM_ICPolarity The Input Polarity.
7917 * This parameter can be one of the following values:
7918 * @arg TIM_ICPOLARITY_RISING
7919 * @arg TIM_ICPOLARITY_FALLING
7920 * @arg TIM_ICPOLARITY_BOTHEDGE
7921 * @param TIM_ICSelection specifies the input to be used.
7922 * This parameter can be one of the following values:
7923 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
7924 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
7925 * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
7926 * @param TIM_ICFilter Specifies the Input Capture Filter.
7927 * This parameter must be a value between 0x00 and 0x0F.
7928 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
7929 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
7930 * protected against un-initialized filter and polarity values.
7931 * @retval None
7932 */
TIM_TI4_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7933 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7934 uint32_t TIM_ICFilter)
7935 {
7936 uint32_t tmpccmr2;
7937 uint32_t tmpccer;
7938
7939 /* Disable the Channel 4: Reset the CC4E Bit */
7940 TIMx->CCER &= ~TIM_CCER_CC4E;
7941 tmpccmr2 = TIMx->CCMR2;
7942 tmpccer = TIMx->CCER;
7943
7944 /* Select the Input */
7945 tmpccmr2 &= ~TIM_CCMR2_CC4S;
7946 tmpccmr2 |= (TIM_ICSelection << 8U);
7947
7948 /* Set the filter */
7949 tmpccmr2 &= ~TIM_CCMR2_IC4F;
7950 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
7951
7952 /* Select the Polarity and set the CC4E Bit */
7953 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
7954 tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
7955
7956 /* Write to TIMx CCMR2 and CCER registers */
7957 TIMx->CCMR2 = tmpccmr2;
7958 TIMx->CCER = tmpccer ;
7959 }
7960
7961 /**
7962 * @brief Selects the Input Trigger source
7963 * @param TIMx to select the TIM peripheral
7964 * @param InputTriggerSource The Input Trigger source.
7965 * This parameter can be one of the following values:
7966 * @arg TIM_TS_ITR0: Internal Trigger 0
7967 * @arg TIM_TS_ITR1: Internal Trigger 1
7968 * @arg TIM_TS_ITR2: Internal Trigger 2
7969 * @arg TIM_TS_ITR3: Internal Trigger 3
7970 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
7971 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
7972 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
7973 * @arg TIM_TS_ETRF: External Trigger input
7974 * @arg TIM_TS_ITR4: Internal Trigger 4 (*)
7975 * @arg TIM_TS_ITR5: Internal Trigger 5
7976 * @arg TIM_TS_ITR6: Internal Trigger 6
7977 * @arg TIM_TS_ITR7: Internal Trigger 7
7978 * @arg TIM_TS_ITR8: Internal Trigger 8
7979 * @arg TIM_TS_ITR9: Internal Trigger 9 (*)
7980 * @arg TIM_TS_ITR10: Internal Trigger 10
7981 * @arg TIM_TS_ITR11: Internal Trigger 11
7982 *
7983 * (*) Value not defined in all devices.
7984 *
7985 * @retval None
7986 */
TIM_ITRx_SetConfig(TIM_TypeDef * TIMx,uint32_t InputTriggerSource)7987 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
7988 {
7989 uint32_t tmpsmcr;
7990
7991 /* Get the TIMx SMCR register value */
7992 tmpsmcr = TIMx->SMCR;
7993 /* Reset the TS Bits */
7994 tmpsmcr &= ~TIM_SMCR_TS;
7995 /* Set the Input Trigger source and the slave mode*/
7996 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
7997 /* Write to TIMx SMCR */
7998 TIMx->SMCR = tmpsmcr;
7999 }
8000 /**
8001 * @brief Configures the TIMx External Trigger (ETR).
8002 * @param TIMx to select the TIM peripheral
8003 * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
8004 * This parameter can be one of the following values:
8005 * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
8006 * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
8007 * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
8008 * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
8009 * @param TIM_ExtTRGPolarity The external Trigger Polarity.
8010 * This parameter can be one of the following values:
8011 * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
8012 * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
8013 * @param ExtTRGFilter External Trigger Filter.
8014 * This parameter must be a value between 0x00 and 0x0F
8015 * @retval None
8016 */
TIM_ETR_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ExtTRGPrescaler,uint32_t TIM_ExtTRGPolarity,uint32_t ExtTRGFilter)8017 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
8018 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
8019 {
8020 uint32_t tmpsmcr;
8021
8022 tmpsmcr = TIMx->SMCR;
8023
8024 /* Reset the ETR Bits */
8025 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8026
8027 /* Set the Prescaler, the Filter value and the Polarity */
8028 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
8029
8030 /* Write to TIMx SMCR */
8031 TIMx->SMCR = tmpsmcr;
8032 }
8033
8034 /**
8035 * @brief Enables or disables the TIM Capture Compare Channel x.
8036 * @param TIMx to select the TIM peripheral
8037 * @param Channel specifies the TIM Channel
8038 * This parameter can be one of the following values:
8039 * @arg TIM_CHANNEL_1: TIM Channel 1
8040 * @arg TIM_CHANNEL_2: TIM Channel 2
8041 * @arg TIM_CHANNEL_3: TIM Channel 3
8042 * @arg TIM_CHANNEL_4: TIM Channel 4
8043 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
8044 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
8045 * @param ChannelState specifies the TIM Channel CCxE bit new state.
8046 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
8047 * @retval None
8048 */
TIM_CCxChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelState)8049 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
8050 {
8051 uint32_t tmp;
8052
8053 /* Check the parameters */
8054 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
8055 assert_param(IS_TIM_CHANNELS(Channel));
8056
8057 tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
8058
8059 /* Reset the CCxE Bit */
8060 TIMx->CCER &= ~tmp;
8061
8062 /* Set or reset the CCxE Bit */
8063 TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
8064 }
8065
8066 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
8067 /**
8068 * @brief Reset interrupt callbacks to the legacy weak callbacks.
8069 * @param htim pointer to a TIM_HandleTypeDef structure that contains
8070 * the configuration information for TIM module.
8071 * @retval None
8072 */
TIM_ResetCallback(TIM_HandleTypeDef * htim)8073 void TIM_ResetCallback(TIM_HandleTypeDef *htim)
8074 {
8075 /* Reset the TIM callback to the legacy weak callbacks */
8076 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
8077 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
8078 htim->TriggerCallback = HAL_TIM_TriggerCallback;
8079 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
8080 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
8081 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
8082 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
8083 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
8084 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
8085 htim->ErrorCallback = HAL_TIM_ErrorCallback;
8086 htim->CommutationCallback = HAL_TIMEx_CommutCallback;
8087 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
8088 htim->BreakCallback = HAL_TIMEx_BreakCallback;
8089 htim->Break2Callback = HAL_TIMEx_Break2Callback;
8090 htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback;
8091 htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback;
8092 htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback;
8093 htim->TransitionErrorCallback = HAL_TIMEx_TransitionErrorCallback;
8094 }
8095 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
8096
8097 /**
8098 * @}
8099 */
8100
8101 #endif /* HAL_TIM_MODULE_ENABLED */
8102 /**
8103 * @}
8104 */
8105
8106 /**
8107 * @}
8108 */
8109
