1 /** 2 ****************************************************************************** 3 * @file stm32g4xx_hal_adc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of ADC HAL extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32G4xx_HAL_ADC_EX_H 21 #define STM32G4xx_HAL_ADC_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32g4xx_hal_def.h" 29 30 /** @addtogroup STM32G4xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup ADCEx 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup ADCEx_Exported_Types ADC Extended Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief ADC Injected Conversion Oversampling structure definition 45 */ 46 typedef struct 47 { 48 uint32_t Ratio; /*!< Configures the oversampling ratio. 49 This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ 50 51 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 52 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 53 } ADC_InjOversamplingTypeDef; 54 55 /** 56 * @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected 57 * @note Parameters of this structure are shared within 2 scopes: 58 * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset, InjectedOffsetSign, InjectedOffsetSaturation 59 * - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, 60 * AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling. 61 * @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. 62 * ADC state can be either: 63 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff') 64 * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group. 65 * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'InjectedOffsetSign', 'InjectedOffsetSaturation', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups. 66 * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going 67 * on ADC groups regular and injected. 68 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 69 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). 70 */ 71 typedef struct 72 { 73 uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected. 74 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 75 Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ 76 77 uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer. 78 This parameter must be a value of @ref ADC_INJ_SEQ_RANKS. 79 Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by 80 the new channel setting (or parameter number of conversions adjusted) */ 81 82 uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. 83 Unit: ADC clock cycles. 84 Conversion time is the addition of sampling time and processing time 85 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 86 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME. 87 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 88 It overwrites the last setting. 89 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 90 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 91 Refer to device datasheet for timings values. */ 92 93 uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input. 94 In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input). 95 Only channel 'i' has to be configured, channel 'i+1' is configured automatically. 96 This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING. 97 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 98 It overwrites the last setting. 99 Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. 100 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. 101 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 102 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case 103 of another parameter update on the fly) */ 104 105 uint32_t InjectedOffsetNumber; /*!< Selects the offset number. 106 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB. 107 Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ 108 109 uint32_t InjectedOffset; /*!< Defines the offset to be applied on the raw converted data. 110 Offset value must be a positive number. 111 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number 112 between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. 113 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 114 without continuous mode or external trigger that could launch a conversion). */ 115 116 uint32_t InjectedOffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data. 117 This parameter can be a value of @ref ADCEx_OffsetSign. 118 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ 119 FunctionalState InjectedOffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow. 120 This parameter value can be ENABLE or DISABLE. 121 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ 122 123 uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer. 124 To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 125 This parameter must be a number between Min_Data = 1 and Max_Data = 4. 126 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 127 configure a channel on injected group can impact the configuration of other channels previously set. */ 128 129 FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence 130 (main sequence subdivided in successive parts). 131 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 132 Discontinuous mode can be enabled only if continuous mode is disabled. 133 This parameter can be set to ENABLE or DISABLE. 134 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 135 Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank). 136 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 137 configure a channel on injected group can impact the configuration of other channels previously set. */ 138 139 FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one 140 This parameter can be set to ENABLE or DISABLE. 141 Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) 142 Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START) 143 Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. 144 To maintain JAUTO always enabled, DMA must be configured in circular mode. 145 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 146 configure a channel on injected group can impact the configuration of other channels previously set. */ 147 148 FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled. 149 This parameter can be set to ENABLE or DISABLE. 150 If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a 151 new injected context is set when queue is full, error is triggered by interruption and through function 152 'HAL_ADCEx_InjectedQueueOverflowCallback'. 153 Caution: This feature request that the sequence is fully configured before injected conversion start. 154 Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter. 155 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 156 configure a channel on injected group can impact the configuration of other channels previously set. 157 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */ 158 159 uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. 160 If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead. 161 This parameter can be a value of @ref ADC_injected_external_trigger_source. 162 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 163 configure a channel on injected group can impact the configuration of other channels previously set. */ 164 165 uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. 166 This parameter can be a value of @ref ADC_injected_external_trigger_edge. 167 If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. 168 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 169 configure a channel on injected group can impact the configuration of other channels previously set. */ 170 171 FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. 172 This parameter can be set to ENABLE or DISABLE. 173 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ 174 175 ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters. 176 Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. 177 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ 178 } ADC_InjectionConfTypeDef; 179 180 #if defined(ADC_MULTIMODE_SUPPORT) 181 /** 182 * @brief Structure definition of ADC multimode 183 * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs). 184 * Both Master and Slave ADCs must be disabled. 185 */ 186 typedef struct 187 { 188 uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode. 189 This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */ 190 191 uint32_t DMAAccessMode; /*!< Configures the DMA mode for multimode ADC: 192 selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master) 193 This parameter can be a value of @ref ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION. */ 194 195 uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. 196 This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY. 197 Delay range depends on selected resolution: 198 from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits, 199 from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits. */ 200 } ADC_MultiModeTypeDef; 201 #endif /* ADC_MULTIMODE_SUPPORT */ 202 203 /** 204 * @} 205 */ 206 207 /* Exported constants --------------------------------------------------------*/ 208 209 /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants 210 * @{ 211 */ 212 213 /** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source 214 * @{ 215 */ 216 /* ADC group regular trigger sources for all ADC instances */ 217 #define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< Software triggers injected group conversion start */ 218 #define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ 219 #define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ 220 #define ADC_EXTERNALTRIGINJEC_T1_CC3 (LL_ADC_INJ_TRIG_EXT_TIM1_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 221 #define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 222 #define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ 223 #define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 224 #define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ 225 #define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 226 #define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 227 #define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 228 #define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ 229 #define ADC_EXTERNALTRIGINJEC_T4_CC3 (LL_ADC_INJ_TRIG_EXT_TIM4_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 230 #define ADC_EXTERNALTRIGINJEC_T4_CC4 (LL_ADC_INJ_TRIG_EXT_TIM4_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 231 #define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ 232 #define ADC_EXTERNALTRIGINJEC_T7_TRGO (LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM7 TRGO. Trigger edge set to rising edge (default setting). */ 233 #define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ 234 #define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ 235 #define ADC_EXTERNALTRIGINJEC_T8_CC2 (LL_ADC_INJ_TRIG_EXT_TIM8_CH2) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 236 #define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 237 #define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ 238 #define ADC_EXTERNALTRIGINJEC_T16_CC1 (LL_ADC_INJ_TRIG_EXT_TIM16_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 239 #define ADC_EXTERNALTRIGINJEC_T20_TRGO (LL_ADC_INJ_TRIG_EXT_TIM20_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting). */ 240 #define ADC_EXTERNALTRIGINJEC_T20_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting). */ 241 #define ADC_EXTERNALTRIGINJEC_T20_CC2 (LL_ADC_INJ_TRIG_EXT_TIM20_CH2) /*!< ADC group injected conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 242 #define ADC_EXTERNALTRIGINJEC_T20_CC4 (LL_ADC_INJ_TRIG_EXT_TIM20_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM20 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 243 #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG1 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting). */ 244 #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG2 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting). */ 245 #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG3 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting). */ 246 #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG4 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting). */ 247 #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG5 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting). */ 248 #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG6 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting). */ 249 #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG7 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting). */ 250 #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG8 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting). */ 251 #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG9 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting). */ 252 #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG10 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting). */ 253 #define ADC_EXTERNALTRIGINJEC_EXT_IT3 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE3) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 3. Trigger edge set to rising edge (default setting). */ 254 #define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */ 255 #define ADC_EXTERNALTRIGINJEC_LPTIM_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */ 256 /** 257 * @} 258 */ 259 260 /** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected) 261 * @{ 262 */ 263 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions hardware trigger detection disabled */ 264 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */ 265 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */ 266 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */ 267 /** 268 * @} 269 */ 270 271 /** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending 272 * @{ 273 */ 274 #define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */ 275 #define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */ 276 /** 277 * @} 278 */ 279 280 /** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number 281 * @{ 282 */ 283 #define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */ 284 #define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 285 #define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 286 #define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 287 #define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 288 /** 289 * @} 290 */ 291 292 /** @defgroup ADCEx_OffsetSign ADC Extended Offset Sign 293 * @{ 294 */ 295 #define ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< Offset sign negative, offset is subtracted */ 296 #define ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS) /*!< Offset sign positive, offset is added */ 297 /** 298 * @} 299 */ 300 301 /** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks 302 * @{ 303 */ 304 #define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */ 305 #define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */ 306 #define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */ 307 #define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */ 308 /** 309 * @} 310 */ 311 312 #if defined(ADC_MULTIMODE_SUPPORT) 313 /** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode 314 * @{ 315 */ 316 #define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled (ADC independent mode) */ 317 #define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular simultaneous */ 318 #define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined group regular interleaved */ 319 #define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group injected simultaneous */ 320 #define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ 321 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ 322 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ 323 #define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */ 324 325 /** @defgroup ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION Multimode - DMA transfer mode depending on ADC resolution 326 * @{ 327 */ 328 #define ADC_DMAACCESSMODE_DISABLED (0x00000000UL) /*!< DMA multimode disabled: each ADC uses its own DMA channel */ 329 #define ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */ 330 #define ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */ 331 /** 332 * @} 333 */ 334 335 /** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases 336 * @{ 337 */ 338 #define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ 339 #define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */ 340 #define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */ 341 #define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */ 342 #define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */ 343 #define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ 344 #define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ 345 #define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ 346 #define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */ 347 #define ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */ 348 #define ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */ 349 #define ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */ 350 /** 351 * @} 352 */ 353 354 /** 355 * @} 356 */ 357 #endif /* ADC_MULTIMODE_SUPPORT */ 358 359 /** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups 360 * @{ 361 */ 362 #define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */ 363 #define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices)*/ 364 #define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */ 365 /** 366 * @} 367 */ 368 369 /** @defgroup ADC_CFGR_fields ADCx CFGR fields 370 * @{ 371 */ 372 #define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\ 373 ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\ 374 ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\ 375 ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ 376 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\ 377 ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN ) 378 /** 379 * @} 380 */ 381 382 /** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields 383 * @{ 384 */ 385 #if defined(ADC_SMPR1_SMPPLUS) 386 #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ 387 ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ 388 ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ 389 ADC_SMPR1_SMP0 | ADC_SMPR1_SMPPLUS) 390 #else 391 #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ 392 ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ 393 ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ 394 ADC_SMPR1_SMP0) 395 #endif /* ADC_SMPR1_SMPPLUS */ 396 /** 397 * @} 398 */ 399 400 /** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields 401 * @{ 402 */ 403 /* ADC_CFGR fields of parameters that can be updated when no conversion 404 (neither regular nor injected) is on-going */ 405 #define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY)) 406 /** 407 * @} 408 */ 409 410 /** 411 * @} 412 */ 413 414 /* Exported macros -----------------------------------------------------------*/ 415 416 #if defined(ADC_MULTIMODE_SUPPORT) 417 /** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros 418 * @{ 419 */ 420 421 /** @brief Force ADC instance in multimode mode independent (multimode disable). 422 * @note This macro must be used only in case of transition from multimode 423 * to mode independent and in case of unknown previous state, 424 * to ensure ADC configuration is in mode independent. 425 * @note Standard way of multimode configuration change is done from 426 * HAL ADC handle of ADC master using function 427 * "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )". 428 * Usage of this macro is not the Standard way of multimode 429 * configuration and can lead to have HAL ADC handles status 430 * misaligned. Usage of this macro must be limited to cases 431 * mentioned above. 432 * @param __HANDLE__ ADC handle. 433 * @retval None 434 */ 435 #define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \ 436 LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT) 437 438 /** 439 * @} 440 */ 441 #endif /* ADC_MULTIMODE_SUPPORT */ 442 443 /* Private macros ------------------------------------------------------------*/ 444 445 /** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros 446 * @{ 447 */ 448 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 449 /* code of final user. */ 450 451 /** 452 * @brief Test if conversion trigger of injected group is software start 453 * or external trigger. 454 * @param __HANDLE__ ADC handle. 455 * @retval SET (software start) or RESET (external trigger). 456 */ 457 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ 458 (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL) 459 460 /** 461 * @brief Check whether or not ADC is independent. 462 * @param __HANDLE__ ADC handle. 463 * @note When multimode feature is not available, the macro always returns SET. 464 * @retval SET (ADC is independent) or RESET (ADC is not). 465 */ 466 #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) 467 #define ADC_IS_INDEPENDENT(__HANDLE__) \ 468 ( ( ( ((__HANDLE__)->Instance) == ADC5) \ 469 )? \ 470 SET \ 471 : \ 472 RESET \ 473 ) 474 #elif defined(STM32G491xx) || defined(STM32G4A1xx) 475 #define ADC_IS_INDEPENDENT(__HANDLE__) \ 476 ( ( ( ((__HANDLE__)->Instance) == ADC3) \ 477 )? \ 478 SET \ 479 : \ 480 RESET \ 481 ) 482 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) 483 #define ADC_IS_INDEPENDENT(__HANDLE__) (RESET) 484 #endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */ 485 486 /** 487 * @brief Set the selected injected Channel rank. 488 * @param __CHANNELNB__ Channel number. 489 * @param __RANKNB__ Rank number. 490 * @retval None 491 */ 492 #define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__)\ 493 & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK)) 494 495 /** 496 * @brief Configure ADC injected context queue 497 * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode. 498 * @retval None 499 */ 500 #define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos) 501 502 /** 503 * @brief Configure ADC discontinuous conversion mode for injected group 504 * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode. 505 * @retval None 506 */ 507 #define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos) 508 509 /** 510 * @brief Configure ADC discontinuous conversion mode for regular group 511 * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode. 512 * @retval None 513 */ 514 #define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos) 515 516 /** 517 * @brief Configure the number of discontinuous conversions for regular group. 518 * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions. 519 * @retval None 520 */ 521 #define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos) 522 523 /** 524 * @brief Configure the ADC auto delay mode. 525 * @param __AUTOWAIT__ Auto delay bit enable or disable. 526 * @retval None 527 */ 528 #define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos) 529 530 /** 531 * @brief Configure ADC continuous conversion mode. 532 * @param __CONTINUOUS_MODE__ Continuous mode. 533 * @retval None 534 */ 535 #define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos) 536 537 /** 538 * @brief Configure the ADC DMA continuous request. 539 * @param __DMACONTREQ_MODE__ DMA continuous request mode. 540 * @retval None 541 */ 542 #define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CFGR_DMACFG_Pos) 543 544 #if defined(ADC_MULTIMODE_SUPPORT) 545 /** 546 * @brief Configure the ADC DMA continuous request for ADC multimode. 547 * @param __DMACONTREQ_MODE__ DMA continuous request mode. 548 * @retval None 549 */ 550 #define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos) 551 #endif /* ADC_MULTIMODE_SUPPORT */ 552 553 /** 554 * @brief Shift the offset with respect to the selected ADC resolution. 555 * @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0. 556 * If resolution 12 bits, no shift. 557 * If resolution 10 bits, shift of 2 ranks on the left. 558 * If resolution 8 bits, shift of 4 ranks on the left. 559 * If resolution 6 bits, shift of 6 ranks on the left. 560 * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)). 561 * @param __HANDLE__ ADC handle 562 * @param __OFFSET__ Value to be shifted 563 * @retval None 564 */ 565 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ 566 ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) 567 568 /** 569 * @brief Shift the AWD1 threshold with respect to the selected ADC resolution. 570 * @note Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. 571 * If resolution 12 bits, no shift. 572 * If resolution 10 bits, shift of 2 ranks on the left. 573 * If resolution 8 bits, shift of 4 ranks on the left. 574 * If resolution 6 bits, shift of 6 ranks on the left. 575 * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)). 576 * @param __HANDLE__ ADC handle 577 * @param __THRESHOLD__ Value to be shifted 578 * @retval None 579 */ 580 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 581 ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) 582 583 /** 584 * @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution. 585 * @note Thresholds have to be left-aligned on bit 7. 586 * If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded). 587 * If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded). 588 * If resolution 8 bits, no shift. 589 * If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0). 590 * @param __HANDLE__ ADC handle 591 * @param __THRESHOLD__ Value to be shifted 592 * @retval None 593 */ 594 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 595 ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) ? \ 596 ((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \ 597 ((__THRESHOLD__) << 2UL) \ 598 ) 599 600 /** 601 * @brief Clear Common Control Register. 602 * @param __HANDLE__ ADC handle. 603 * @retval None 604 */ 605 #if defined(ADC_MULTIMODE_SUPPORT) 606 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \ 607 ADC_CCR_CKMODE | \ 608 ADC_CCR_PRESC | \ 609 ADC_CCR_VBATSEL | \ 610 ADC_CCR_VSENSESEL | \ 611 ADC_CCR_VREFEN | \ 612 ADC_CCR_MDMA | \ 613 ADC_CCR_DMACFG | \ 614 ADC_CCR_DELAY | \ 615 ADC_CCR_DUAL) 616 #endif /* ADC_MULTIMODE_SUPPORT */ 617 618 #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) 619 /** 620 * @brief Set handle instance of the ADC slave associated to the ADC master. 621 * @param __HANDLE_MASTER__ ADC master handle. 622 * @param __HANDLE_SLAVE__ ADC slave handle. 623 * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL. 624 * @retval None 625 */ 626 #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ 627 ( ((__HANDLE_MASTER__)->Instance == ADC1) ? \ 628 ((__HANDLE_SLAVE__)->Instance = ADC2) \ 629 : \ 630 ((__HANDLE_MASTER__)->Instance == ADC3) ? \ 631 ((__HANDLE_SLAVE__)->Instance = ADC4) \ 632 : \ 633 ((__HANDLE_SLAVE__)->Instance = NULL) \ 634 ) 635 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) 636 /** 637 * @brief Set handle instance of the ADC slave associated to the ADC master. 638 * @param __HANDLE_MASTER__ ADC master handle. 639 * @param __HANDLE_SLAVE__ ADC slave handle. 640 * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL. 641 * @retval None 642 */ 643 #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ 644 ( ((__HANDLE_MASTER__)->Instance == ADC1) ? \ 645 ((__HANDLE_SLAVE__)->Instance = ADC2) \ 646 : \ 647 ((__HANDLE_SLAVE__)->Instance = NULL) \ 648 ) 649 #endif 650 651 652 /** 653 * @brief Verify the ADC instance connected to the temperature sensor. 654 * @param __HANDLE__ ADC handle. 655 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 656 */ 657 #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) 658 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC5)) 659 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) 660 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) 661 #endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */ 662 663 /** 664 * @brief Verify the ADC instance connected to the battery voltage VBAT. 665 * @param __HANDLE__ ADC handle. 666 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 667 */ 668 #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) 669 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) != ADC2) || (((__HANDLE__)->Instance) != ADC4)) 670 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) 671 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) != ADC2) 672 #elif defined(STM32G491xx) || defined(STM32G4A1xx) 673 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) 674 #endif 675 676 /** 677 * @brief Verify the ADC instance connected to the internal voltage reference VREFINT. 678 * @param __HANDLE__ ADC handle. 679 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 680 */ 681 #define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) != ADC2) 682 683 /** 684 * @brief Verify the length of scheduled injected conversions group. 685 * @param __LENGTH__ number of programmed conversions. 686 * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large) 687 */ 688 #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U))) 689 690 /** 691 * @brief Calibration factor size verification (7 bits maximum). 692 * @param __CALIBRATION_FACTOR__ Calibration factor value. 693 * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large) 694 */ 695 #define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU)) 696 697 698 /** 699 * @brief Verify the ADC channel setting. 700 * @param __HANDLE__ ADC handle. 701 * @param __CHANNEL__ programmed ADC channel. 702 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 703 */ 704 #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) 705 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ 706 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 707 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 708 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 709 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 710 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 711 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 712 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 713 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 714 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 715 ((__CHANNEL__) == ADC_CHANNEL_15)) || \ 716 ((((__HANDLE__)->Instance) == ADC1) && \ 717 (((__CHANNEL__) == ADC_CHANNEL_3) || \ 718 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 719 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 720 ((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \ 721 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \ 722 ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ 723 ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \ 724 ((((__HANDLE__)->Instance) == ADC2) && \ 725 (((__CHANNEL__) == ADC_CHANNEL_3) || \ 726 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 727 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 728 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 729 ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \ 730 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 731 ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))) || \ 732 ((((__HANDLE__)->Instance) == ADC3) && \ 733 (((__CHANNEL__) == ADC_CHANNEL_3) || \ 734 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 735 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 736 ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3) || \ 737 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 738 ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ 739 ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \ 740 ((((__HANDLE__)->Instance) == ADC4) && \ 741 (((__CHANNEL__) == ADC_CHANNEL_3) || \ 742 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 743 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 744 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 745 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 746 ((__CHANNEL__) == ADC_CHANNEL_VOPAMP6) || \ 747 ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \ 748 ((((__HANDLE__)->Instance) == ADC5) && \ 749 (((__CHANNEL__) == ADC_CHANNEL_VOPAMP5) || \ 750 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC5) || \ 751 ((__CHANNEL__) == ADC_CHANNEL_VOPAMP4) || \ 752 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 753 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 754 ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ 755 ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))) 756 #elif defined(STM32G471xx) 757 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ 758 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 759 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 760 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 761 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 762 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 763 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 764 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 765 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 766 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 767 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 768 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 769 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 770 ((__CHANNEL__) == ADC_CHANNEL_15)) || \ 771 ((((__HANDLE__)->Instance) == ADC1) && \ 772 (((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \ 773 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \ 774 ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ 775 ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \ 776 ((((__HANDLE__)->Instance) == ADC2) && \ 777 (((__CHANNEL__) == ADC_CHANNEL_13) || \ 778 ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \ 779 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 780 ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))) || \ 781 ((((__HANDLE__)->Instance) == ADC3) && \ 782 (((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3) || \ 783 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 784 ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ 785 ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))) 786 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) 787 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ 788 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 789 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 790 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 791 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 792 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 793 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 794 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 795 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 796 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 797 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 798 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 799 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 800 ((__CHANNEL__) == ADC_CHANNEL_15)) || \ 801 ((((__HANDLE__)->Instance) == ADC1) && \ 802 (((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \ 803 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \ 804 ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ 805 ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \ 806 ((((__HANDLE__)->Instance) == ADC2) && \ 807 (((__CHANNEL__) == ADC_CHANNEL_13) || \ 808 ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \ 809 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 810 ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2)))) 811 #elif defined(STM32G491xx) || defined(STM32G4A1xx) 812 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ 813 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 814 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 815 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 816 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 817 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 818 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 819 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 820 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 821 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 822 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 823 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 824 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 825 ((__CHANNEL__) == ADC_CHANNEL_15)) || \ 826 ((((__HANDLE__)->Instance) == ADC1) && \ 827 (((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \ 828 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \ 829 ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ 830 ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \ 831 ((((__HANDLE__)->Instance) == ADC2) && \ 832 (((__CHANNEL__) == ADC_CHANNEL_13) || \ 833 ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \ 834 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 835 ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))) || \ 836 ((((__HANDLE__)->Instance) == ADC3) && \ 837 (((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3) || \ 838 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 839 ((__CHANNEL__) == ADC_CHANNEL_VOPAMP6) || \ 840 ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))) 841 #endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */ 842 843 /** 844 * @brief Verify the ADC channel setting in differential mode. 845 * @param __HANDLE__ ADC handle. 846 * @param __CHANNEL__ programmed ADC channel. 847 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 848 */ 849 #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) 850 #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ 851 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 852 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 853 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 854 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 855 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 856 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 857 ((__CHANNEL__) == ADC_CHANNEL_14)) || \ 858 ((((__HANDLE__)->Instance) == ADC1) && \ 859 (((__CHANNEL__) == ADC_CHANNEL_2) || \ 860 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 861 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 862 ((__CHANNEL__) == ADC_CHANNEL_5))) || \ 863 ((((__HANDLE__)->Instance) == ADC2) && \ 864 (((__CHANNEL__) == ADC_CHANNEL_2) || \ 865 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 866 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 867 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 868 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 869 ((__CHANNEL__) == ADC_CHANNEL_13))) || \ 870 ((((__HANDLE__)->Instance) == ADC3) && \ 871 (((__CHANNEL__) == ADC_CHANNEL_2) || \ 872 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 873 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 874 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 875 ((__CHANNEL__) == ADC_CHANNEL_15))) || \ 876 ((((__HANDLE__)->Instance) == ADC4) && \ 877 (((__CHANNEL__) == ADC_CHANNEL_2) || \ 878 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 879 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 880 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 881 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 882 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 883 ((__CHANNEL__) == ADC_CHANNEL_15))) || \ 884 ((((__HANDLE__)->Instance) == ADC5) && \ 885 (((__CHANNEL__) == ADC_CHANNEL_12) || \ 886 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 887 ((__CHANNEL__) == ADC_CHANNEL_15))) ) 888 #elif defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) 889 #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ 890 (((__CHANNEL__) == ADC_CHANNEL_2) || \ 891 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 892 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 893 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 894 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 895 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 896 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 897 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 898 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 899 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 900 ((__CHANNEL__) == ADC_CHANNEL_14)) || \ 901 ((((__HANDLE__)->Instance) == ADC2) && \ 902 (((__CHANNEL__) == ADC_CHANNEL_12) || \ 903 ((__CHANNEL__) == ADC_CHANNEL_13))) || \ 904 ((((__HANDLE__)->Instance) == ADC3) && \ 905 ((__CHANNEL__) == ADC_CHANNEL_15))) ) 906 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) 907 #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ 908 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 909 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 910 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 911 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 912 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 913 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 914 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 915 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 916 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 917 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 918 ((__CHANNEL__) == ADC_CHANNEL_14)) || \ 919 ((((__HANDLE__)->Instance) == ADC2) && \ 920 (((__CHANNEL__) == ADC_CHANNEL_12) || \ 921 ((__CHANNEL__) == ADC_CHANNEL_13))) ) 922 #endif 923 924 /** 925 * @brief Verify the ADC single-ended input or differential mode setting. 926 * @param __SING_DIFF__ programmed channel setting. 927 * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid) 928 */ 929 #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \ 930 ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) ) 931 932 /** 933 * @brief Verify the ADC offset management setting. 934 * @param __OFFSET_NUMBER__ ADC offset management. 935 * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid) 936 */ 937 #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \ 938 ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \ 939 ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \ 940 ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \ 941 ((__OFFSET_NUMBER__) == ADC_OFFSET_4) ) 942 943 /** 944 * @brief Verify the ADC offset sign setting. 945 * @param __OFFSET_SIGN__ ADC offset sign. 946 * @retval SET (__OFFSET_SIGN__ is valid) or RESET (__OFFSET_SIGN__ is invalid) 947 */ 948 #define IS_ADC_OFFSET_SIGN(__OFFSET_SIGN__) (((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_NEGATIVE) || \ 949 ((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_POSITIVE) ) 950 951 /** 952 * @brief Verify the ADC injected channel setting. 953 * @param __CHANNEL__ programmed ADC injected channel. 954 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 955 */ 956 #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \ 957 ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \ 958 ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \ 959 ((__CHANNEL__) == ADC_INJECTED_RANK_4) ) 960 961 /** 962 * @brief Verify the ADC injected conversions external trigger. 963 * @param __HANDLE__ ADC handle. 964 * @param __INJTRIG__ programmed ADC injected conversions external trigger. 965 * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid) 966 */ 967 #if defined(STM32G474xx) || defined(STM32G484xx) 968 #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ 969 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ 970 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ 971 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ 972 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ 973 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ 974 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ 975 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \ 976 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ 977 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ 978 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ 979 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ 980 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO) || \ 981 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2) || \ 982 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG2) || \ 983 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG4) || \ 984 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG5) || \ 985 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG6) || \ 986 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG7) || \ 987 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG8) || \ 988 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG9) || \ 989 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG10) || \ 990 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ 991 ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ 992 (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ 993 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ 994 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ 995 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ 996 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ 997 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \ 998 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \ 999 ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \ 1000 (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \ 1001 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \ 1002 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \ 1003 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \ 1004 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \ 1005 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG1) || \ 1006 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG3) || \ 1007 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \ 1008 ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) 1009 #elif defined(STM32G473xx) || defined(STM32G483xx) 1010 #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ 1011 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ 1012 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ 1013 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ 1014 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ 1015 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ 1016 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ 1017 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \ 1018 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ 1019 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ 1020 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ 1021 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ 1022 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO) || \ 1023 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2) || \ 1024 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ 1025 ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ 1026 (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ 1027 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ 1028 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ 1029 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ 1030 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ 1031 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \ 1032 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \ 1033 ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \ 1034 (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \ 1035 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \ 1036 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \ 1037 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \ 1038 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \ 1039 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \ 1040 ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) 1041 #elif defined(STM32G471xx) 1042 #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ 1043 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ 1044 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ 1045 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ 1046 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ 1047 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ 1048 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ 1049 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \ 1050 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ 1051 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ 1052 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ 1053 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ 1054 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ 1055 ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ 1056 (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ 1057 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ 1058 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ 1059 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ 1060 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ 1061 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \ 1062 ((((__HANDLE__)->Instance == ADC3)) && \ 1063 (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \ 1064 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \ 1065 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \ 1066 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \ 1067 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \ 1068 ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) 1069 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) 1070 #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ 1071 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ 1072 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ 1073 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ 1074 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ 1075 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ 1076 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ 1077 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ 1078 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ 1079 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ 1080 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ 1081 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \ 1082 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ 1083 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ 1084 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ 1085 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ 1086 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ 1087 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \ 1088 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ 1089 ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) 1090 #elif defined(STM32G491xx) || defined(STM32G4A1xx) 1091 #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ 1092 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ 1093 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ 1094 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ 1095 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ 1096 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ 1097 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ 1098 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \ 1099 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ 1100 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ 1101 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ 1102 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ 1103 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO) || \ 1104 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2) || \ 1105 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ 1106 ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ 1107 (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ 1108 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ 1109 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ 1110 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ 1111 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ 1112 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \ 1113 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \ 1114 (((__HANDLE__)->Instance == ADC3) && \ 1115 (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \ 1116 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \ 1117 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \ 1118 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \ 1119 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \ 1120 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \ 1121 ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) 1122 #endif 1123 1124 /** 1125 * @brief Verify the ADC edge trigger setting for injected group. 1126 * @param __EDGE__ programmed ADC edge trigger setting. 1127 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 1128 */ 1129 #define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ 1130 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ 1131 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ 1132 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) 1133 1134 #if defined(ADC_MULTIMODE_SUPPORT) 1135 /** 1136 * @brief Verify the ADC multimode setting. 1137 * @param __MODE__ programmed ADC multimode setting. 1138 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 1139 */ 1140 #define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \ 1141 ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ 1142 ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ 1143 ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \ 1144 ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \ 1145 ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \ 1146 ((__MODE__) == ADC_DUALMODE_INTERL) || \ 1147 ((__MODE__) == ADC_DUALMODE_ALTERTRIG) ) 1148 1149 /** 1150 * @brief Verify the ADC multimode DMA access setting. 1151 * @param __MODE__ programmed ADC multimode DMA access setting. 1152 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 1153 */ 1154 #define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \ 1155 ((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) || \ 1156 ((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS) ) 1157 1158 /** 1159 * @brief Verify the ADC multimode delay setting. 1160 * @param __DELAY__ programmed ADC multimode delay setting. 1161 * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid) 1162 */ 1163 #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \ 1164 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \ 1165 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \ 1166 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \ 1167 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ 1168 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ 1169 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ 1170 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ 1171 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ 1172 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ 1173 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ 1174 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) ) 1175 #endif /* ADC_MULTIMODE_SUPPORT */ 1176 1177 /** 1178 * @brief Verify the ADC analog watchdog setting. 1179 * @param __WATCHDOG__ programmed ADC analog watchdog setting. 1180 * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid) 1181 */ 1182 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \ 1183 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \ 1184 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) ) 1185 1186 /** 1187 * @brief Verify the ADC analog watchdog mode setting. 1188 * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting. 1189 * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid) 1190 */ 1191 #define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \ 1192 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 1193 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ 1194 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ 1195 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \ 1196 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ 1197 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) 1198 1199 /** 1200 * @brief Verify the ADC analog watchdog filtering setting. 1201 * @param __FILTERING_MODE__ programmed ADC analog watchdog mode setting. 1202 * @retval SET (__FILTERING_MODE__ is valid) or RESET (__FILTERING_MODE__ is invalid) 1203 */ 1204 #define IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(__FILTERING_MODE__) (((__FILTERING_MODE__) == ADC_AWD_FILTERING_NONE) || \ 1205 ((__FILTERING_MODE__) == ADC_AWD_FILTERING_2SAMPLES) || \ 1206 ((__FILTERING_MODE__) == ADC_AWD_FILTERING_3SAMPLES) || \ 1207 ((__FILTERING_MODE__) == ADC_AWD_FILTERING_4SAMPLES) || \ 1208 ((__FILTERING_MODE__) == ADC_AWD_FILTERING_5SAMPLES) || \ 1209 ((__FILTERING_MODE__) == ADC_AWD_FILTERING_6SAMPLES) || \ 1210 ((__FILTERING_MODE__) == ADC_AWD_FILTERING_7SAMPLES) || \ 1211 ((__FILTERING_MODE__) == ADC_AWD_FILTERING_8SAMPLES) ) 1212 1213 1214 /** 1215 * @brief Verify the ADC conversion (regular or injected or both). 1216 * @param __CONVERSION__ ADC conversion group. 1217 * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid) 1218 */ 1219 #define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \ 1220 ((__CONVERSION__) == ADC_INJECTED_GROUP) || \ 1221 ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) ) 1222 1223 /** 1224 * @brief Verify the ADC event type. 1225 * @param __EVENT__ ADC event. 1226 * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid) 1227 */ 1228 #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ 1229 ((__EVENT__) == ADC_AWD_EVENT) || \ 1230 ((__EVENT__) == ADC_AWD2_EVENT) || \ 1231 ((__EVENT__) == ADC_AWD3_EVENT) || \ 1232 ((__EVENT__) == ADC_OVR_EVENT) || \ 1233 ((__EVENT__) == ADC_JQOVF_EVENT) ) 1234 1235 /** 1236 * @brief Verify the ADC oversampling ratio. 1237 * @param __RATIO__ programmed ADC oversampling ratio. 1238 * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid) 1239 */ 1240 #define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \ 1241 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \ 1242 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \ 1243 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \ 1244 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \ 1245 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \ 1246 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \ 1247 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 )) 1248 1249 /** 1250 * @brief Verify the ADC oversampling shift. 1251 * @param __SHIFT__ programmed ADC oversampling shift. 1252 * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) 1253 */ 1254 #define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \ 1255 ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \ 1256 ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \ 1257 ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \ 1258 ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \ 1259 ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \ 1260 ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \ 1261 ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \ 1262 ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 )) 1263 1264 /** 1265 * @brief Verify the ADC oversampling triggered mode. 1266 * @param __MODE__ programmed ADC oversampling triggered mode. 1267 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 1268 */ 1269 #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ 1270 ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) 1271 1272 /** 1273 * @brief Verify the ADC oversampling regular conversion resumed or continued mode. 1274 * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode. 1275 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 1276 */ 1277 #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \ 1278 ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) ) 1279 1280 /** 1281 * @brief Verify the DFSDM mode configuration. 1282 * @param __HANDLE__ ADC handle. 1283 * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For 1284 * this reason, the input parameter is the ADC handle and not the configuration parameter 1285 * directly. 1286 * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid) 1287 */ 1288 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET) 1289 1290 /** 1291 * @brief Return the DFSDM configuration mode. 1292 * @param __HANDLE__ ADC handle. 1293 * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). 1294 * For this reason, the input parameter is the ADC handle and not the configuration parameter 1295 * directly. 1296 * @retval DFSDM configuration mode 1297 */ 1298 #define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL) 1299 1300 /** 1301 * @} 1302 */ 1303 1304 1305 /* Exported functions --------------------------------------------------------*/ 1306 /** @addtogroup ADCEx_Exported_Functions 1307 * @{ 1308 */ 1309 1310 /** @addtogroup ADCEx_Exported_Functions_Group1 1311 * @{ 1312 */ 1313 /* IO operation functions *****************************************************/ 1314 1315 /* ADC calibration */ 1316 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); 1317 uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); 1318 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, 1319 uint32_t CalibrationFactor); 1320 1321 /* Blocking mode: Polling */ 1322 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc); 1323 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc); 1324 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); 1325 1326 /* Non-blocking mode: Interruption */ 1327 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc); 1328 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); 1329 1330 #if defined(ADC_MULTIMODE_SUPPORT) 1331 /* ADC multimode */ 1332 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); 1333 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); 1334 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); 1335 #endif /* ADC_MULTIMODE_SUPPORT */ 1336 1337 /* ADC retrieve conversion value intended to be used with polling or interruption */ 1338 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank); 1339 1340 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ 1341 void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); 1342 void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc); 1343 void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc); 1344 void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc); 1345 void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc); 1346 1347 /* ADC group regular conversions stop */ 1348 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc); 1349 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc); 1350 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc); 1351 #if defined(ADC_MULTIMODE_SUPPORT) 1352 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc); 1353 #endif /* ADC_MULTIMODE_SUPPORT */ 1354 1355 /** 1356 * @} 1357 */ 1358 1359 /** @addtogroup ADCEx_Exported_Functions_Group2 1360 * @{ 1361 */ 1362 /* Peripheral Control functions ***********************************************/ 1363 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, 1364 ADC_InjectionConfTypeDef *sConfigInjected); 1365 #if defined(ADC_MULTIMODE_SUPPORT) 1366 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); 1367 #endif /* ADC_MULTIMODE_SUPPORT */ 1368 HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc); 1369 HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc); 1370 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc); 1371 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc); 1372 1373 /** 1374 * @} 1375 */ 1376 1377 /** 1378 * @} 1379 */ 1380 1381 /** 1382 * @} 1383 */ 1384 1385 /** 1386 * @} 1387 */ 1388 1389 #ifdef __cplusplus 1390 } 1391 #endif 1392 1393 #endif /* STM32G4xx_HAL_ADC_EX_H */ 1394
