1 /**
2 ******************************************************************************
3 * @file stm32g0xx_hal_hcd.h
4 * @author MCD Application Team
5 * @brief Header file of HCD HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2018 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32G0xx_HAL_HCD_H
21 #define STM32G0xx_HAL_HCD_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32g0xx_ll_usb.h"
29
30 #if defined (USB_DRD_FS)
31 /** @addtogroup STM32G0xx_HAL_Driver
32 * @{
33 */
34
35 /** @addtogroup HCD HCD
36 * @{
37 */
38
39 /* Exported types ------------------------------------------------------------*/
40 /** @defgroup HCD_Exported_Types HCD Exported Types
41 * @{
42 */
43
44 /** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition
45 * @{
46 */
47 typedef enum
48 {
49 HAL_HCD_STATE_RESET = 0x00,
50 HAL_HCD_STATE_READY = 0x01,
51 HAL_HCD_STATE_ERROR = 0x02,
52 HAL_HCD_STATE_BUSY = 0x03,
53 HAL_HCD_STATE_TIMEOUT = 0x04
54 } HCD_StateTypeDef;
55
56 typedef USB_DRD_TypeDef HCD_TypeDef;
57 typedef USB_DRD_CfgTypeDef HCD_InitTypeDef;
58 typedef USB_DRD_HCTypeDef HCD_HCTypeDef;
59 typedef USB_DRD_URBStateTypeDef HCD_URBStateTypeDef;
60 typedef USB_DRD_HCStateTypeDef HCD_HCStateTypeDef;
61
62 typedef enum
63 {
64 HCD_HCD_STATE_DISCONNECTED = 0x00U,
65 HCD_HCD_STATE_CONNECTED = 0x01U,
66 HCD_HCD_STATE_RESETED = 0x02U,
67 HCD_HCD_STATE_RUN = 0x03U,
68 HCD_HCD_STATE_SUSPEND = 0x04U,
69 HCD_HCD_STATE_RESUME = 0x05U,
70 } HCD_HostStateTypeDef;
71
72 /* PMA lookup Table size depending on PMA Size
73 * 8Bytes each Block 32Bit in each word
74 */
75 #define PMA_BLOCKS ((USB_DRD_PMA_SIZE) / (8U * 32U))
76 /**
77 * @}
78 */
79
80 /** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
81 * @{
82 */
83 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
84 typedef struct __HCD_HandleTypeDef
85 #else
86 typedef struct
87 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
88 {
89 HCD_TypeDef *Instance; /*!< Register base address */
90 HCD_InitTypeDef Init; /*!< HCD required parameters */
91 HCD_HCTypeDef hc[16]; /*!< Host channels parameters */
92 uint32_t ep0_PmaAllocState; /*!< EP0 PMA allocation State (allocated, virtual Ch, EP0 direction) */
93 uint16_t phy_chin_state[8]; /*!< Physical Channel in State (Used/Free) */
94 uint16_t phy_chout_state[8]; /*!< Physical Channel out State (Used/Free)*/
95 uint32_t PMALookupTable[PMA_BLOCKS]; /*PMA LookUp Table */
96 HCD_HostStateTypeDef HostState; /*!< USB current state DICONNECT/CONNECT/RUN/SUSPEND/RESUME */
97 HAL_LockTypeDef Lock; /*!< HCD peripheral status */
98 __IO HCD_StateTypeDef State; /*!< HCD communication state */
99 __IO uint32_t ErrorCode; /*!< HCD Error code */
100 void *pData; /*!< Pointer Stack Handler */
101 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
102 void (* SOFCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD SOF callback */
103 void (* ConnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Connect callback */
104 void (* DisconnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Disconnect callback */
105 void (* PortEnabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Enable callback */
106 void (* PortDisabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Disable callback */
107 void (* HC_NotifyURBChangeCallback)(struct __HCD_HandleTypeDef *hhcd, uint8_t chnum,
108 HCD_URBStateTypeDef urb_state); /*!< USB OTG HCD Host Channel Notify URB Change callback */
109
110 void (* MspInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp Init callback */
111 void (* MspDeInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp DeInit callback */
112 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
113 } HCD_HandleTypeDef;
114 /**
115 * @}
116 */
117
118 /**
119 * @}
120 */
121
122 /* Exported constants --------------------------------------------------------*/
123 /** @defgroup HCD_Exported_Constants HCD Exported Constants
124 * @{
125 */
126
127 /** @defgroup HCD_Speed HCD Speed
128 * @{
129 */
130 #define HCD_SPEED_FULL USBH_FSLS_SPEED
131 #define HCD_SPEED_LOW USBH_FSLS_SPEED
132 /**
133 * @}
134 */
135
136 /** @defgroup HCD_Device_Speed HCD Device Speed
137 * @{
138 */
139 #define HCD_DEVICE_SPEED_HIGH 0U
140 #define HCD_DEVICE_SPEED_FULL 1U
141 #define HCD_DEVICE_SPEED_LOW 2U
142 /**
143 * @}
144 */
145
146 /** @defgroup HCD_PHY_Module HCD PHY Module
147 * @{
148 */
149 #define HCD_PHY_ULPI 1U
150 #define HCD_PHY_EMBEDDED 2U
151 /**
152 * @}
153 */
154
155 /** @defgroup HCD_Error_Code_definition HCD Error Code definition
156 * @brief HCD Error Code definition
157 * @{
158 */
159 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
160 #define HAL_HCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */
161 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
162
163 /**
164 * @}
165 */
166
167 /**
168 * @}
169 */
170
171 /* Exported macro ------------------------------------------------------------*/
172 /** @defgroup HCD_Exported_Macros HCD Exported Macros
173 * @brief macros to handle interrupts and specific clock configurations
174 * @{
175 */
176 #define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
177 #define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
178
179 #define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\
180 & (__INTERRUPT__)) == (__INTERRUPT__))
181 #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
182 #define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
183
184 #define __HAL_HCD_GET_CHNUM(__HANDLE__) (((__HANDLE__)->Instance->ISTR) & USB_ISTR_IDN)
185 #define __HAL_HCD_GET_CHDIR(__HANDLE__) (((__HANDLE__)->Instance->ISTR) & USB_ISTR_DIR)
186 /**
187 * @}
188 */
189
190 /* Exported functions --------------------------------------------------------*/
191 /** @addtogroup HCD_Exported_Functions HCD Exported Functions
192 * @{
193 */
194
195 /** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
196 * @{
197 */
198 HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
199 HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
200 HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
201 uint8_t epnum, uint8_t dev_address,
202 uint8_t speed, uint8_t ep_type, uint16_t mps);
203
204 HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
205 HAL_StatusTypeDef HAL_HCD_HC_Close(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
206 void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
207 void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
208
209 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
210 /** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition
211 * @brief HAL USB OTG HCD Callback ID enumeration definition
212 * @{
213 */
214 typedef enum
215 {
216 HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */
217 HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */
218 HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */
219 HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */
220 HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */
221
222 HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */
223 HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */
224
225 } HAL_HCD_CallbackIDTypeDef;
226 /**
227 * @}
228 */
229
230 /** @defgroup HAL_HCD_Callback_pointer_definition HAL USB OTG HCD Callback pointer definition
231 * @brief HAL USB OTG HCD Callback pointer definition
232 * @{
233 */
234
235 typedef void (*pHCD_CallbackTypeDef)(HCD_HandleTypeDef *hhcd); /*!< pointer to a common USB OTG HCD callback function */
236 typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd,
237 uint8_t epnum,
238 HCD_URBStateTypeDef urb_state); /*!< pointer to USB OTG HCD host channel callback */
239 /**
240 * @}
241 */
242
243 HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd,
244 HAL_HCD_CallbackIDTypeDef CallbackID,
245 pHCD_CallbackTypeDef pCallback);
246
247 HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd,
248 HAL_HCD_CallbackIDTypeDef CallbackID);
249
250 HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd,
251 pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback);
252
253 HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd);
254 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
255 /**
256 * @}
257 */
258
259 /* I/O operation functions ***************************************************/
260 /** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
261 * @{
262 */
263 HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
264 uint8_t direction, uint8_t ep_type,
265 uint8_t token, uint8_t *pbuff,
266 uint16_t length, uint8_t do_ping);
267
268 /* Non-Blocking mode: Interrupt */
269 void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
270 void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
271 void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
272 void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
273 void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
274 void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
275 void HAL_HCD_SuspendCallback(HCD_HandleTypeDef *hhcd);
276 void HAL_HCD_ResumeCallback(HCD_HandleTypeDef *hhcd);
277 void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum,
278 HCD_URBStateTypeDef urb_state);
279 /**
280 * @}
281 */
282
283 /* Peripheral Control functions **********************************************/
284 /** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
285 * @{
286 */
287 HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
288 HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
289 HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
290 HAL_StatusTypeDef HAL_HCD_Suspend(HCD_HandleTypeDef *hhcd);
291 HAL_StatusTypeDef HAL_HCD_Resume(HCD_HandleTypeDef *hhcd);
292 HAL_StatusTypeDef HAL_HCD_ResumePort(HCD_HandleTypeDef *hhcd);
293 /**
294 * @}
295 */
296
297 /* Peripheral State functions ************************************************/
298 /** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
299 * @{
300 */
301 HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
302 HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
303 HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
304 uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
305 uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
306 uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
307
308 /* PMA Allocation functions **********************************************/
309 /** @addtogroup PMA Allocation
310 * @{
311 */
312 HAL_StatusTypeDef HAL_HCD_PMAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
313 uint16_t ch_kind, uint16_t mps);
314
315 HAL_StatusTypeDef HAL_HCD_PMADeAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
316 HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd);
317
318 /**
319 * @}
320 */
321 /**
322 * @}
323 */
324
325 /**
326 * @}
327 */
328
329 /* Private macros ------------------------------------------------------------*/
330 /** @defgroup HCD_Private_Macros HCD Private Macros
331 * @{
332 */
333 /** @defgroup HCD_LOGICAL_CHANNEL HCD Logical Channel
334 * @{
335 */
336 #define HCD_LOGICAL_CH_NOT_OPENED 0xFFU
337 #define HCD_FREE_CH_NOT_FOUND 0xFFU
338 /**
339 * @}
340 */
341
342 /** @defgroup HCD_ENDP_Kind HCD Endpoint Kind
343 * @{
344 */
345 #define HCD_SNG_BUF 0U
346 #define HCD_DBL_BUF 1U
347 /**
348 * @}
349 */
350
351 /* Set Channel */
352 #define HCD_SET_CHANNEL USB_DRD_SET_CHEP
353
354 /* Get Channel Register */
355 #define HCD_GET_CHANNEL USB_DRD_GET_CHEP
356
357
358 /**
359 * @brief free buffer used from the application realizing it to the line
360 * toggles bit SW_BUF in the double buffered endpoint register
361 * @param USBx USB device.
362 * @param bChNum, bDir
363 * @retval None
364 */
365 #define HCD_FREE_USER_BUFFER USB_DRD_FREE_USER_BUFFER
366
367 /**
368 * @brief Set the Setup bit in the corresponding channel, when a Setup
369 transaction is needed.
370 * @param USBx USB device.
371 * @param bChNum
372 * @retval None
373 */
374 #define HAC_SET_CH_TX_SETUP USB_DRD_CHEP_TX_SETUP
375
376 /**
377 * @brief sets the status for tx transfer (bits STAT_TX[1:0]).
378 * @param USBx USB peripheral instance register address.
379 * @param bChNum Endpoint Number.
380 * @param wState new state
381 * @retval None
382 */
383 #define HCD_SET_CH_TX_STATUS USB_DRD_SET_CHEP_TX_STATUS
384
385 /**
386 * @brief sets the status for rx transfer (bits STAT_TX[1:0])
387 * @param USBx USB peripheral instance register address.
388 * @param bChNum Endpoint Number.
389 * @param wState new state
390 * @retval None
391 */
392 #define HCD_SET_CH_RX_STATUS USB_DRD_SET_CHEP_RX_STATUS
393 /**
394 * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0]
395 * /STAT_RX[1:0])
396 * @param USBx USB peripheral instance register address.
397 * @param bChNum Endpoint Number.
398 * @retval status
399 */
400 #define HCD_GET_CH_TX_STATUS USB_DRD_GET_CHEP_TX_STATUS
401 #define HCD_GET_CH_RX_STATUS USB_DRD_GET_CHEP_RX_STATUS
402 /**
403 * @brief Sets/clears CH_KIND bit in the Channel register.
404 * @param USBx USB peripheral instance register address.
405 * @param bChNum Endpoint Number.
406 * @retval None
407 */
408 #define HCD_SET_CH_KIND USB_DRD_SET_CH_KIND
409 #define HCD_CLEAR_CH_KIND USB_DRD_CLEAR_CH_KIND
410 #define HCD_SET_BULK_CH_DBUF HCD_SET_CH_KIND
411 #define HCD_CLEAR_BULK_CH_DBUF HCD_CLEAR_CH_KIND
412
413 /**
414 * @brief Clears bit ERR_RX in the Channel register
415 * @param USBx USB peripheral instance register address.
416 * @param bChNum Endpoint Number.
417 * @retval None
418 */
419 #define HCD_CLEAR_RX_CH_ERR USB_DRD_CLEAR_CHEP_RX_ERR
420
421 /**
422 * @brief Clears bit ERR_TX in the Channel register
423 * @param USBx USB peripheral instance register address.
424 * @param bChNum Endpoint Number.
425 * @retval None
426 */
427 #define HCD_CLEAR_TX_CH_ERR USB_DRD_CLEAR_CHEP_TX_ERR
428 /**
429 * @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
430 * @param USBx USB peripheral instance register address.
431 * @param bChNum Endpoint Number.
432 * @retval None
433 */
434 #define HCD_CLEAR_RX_CH_CTR USB_DRD_CLEAR_RX_CHEP_CTR
435 #define HCD_CLEAR_TX_CH_CTR USB_DRD_CLEAR_TX_CHEP_CTR
436
437 /**
438 * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
439 * @param USBx USB peripheral instance register address.
440 * @param bChNum Endpoint Number.
441 * @retval None
442 */
443 #define HCD_RX_DTOG USB_DRD_RX_DTOG
444 #define HCD_TX_DTOG USB_DRD_TX_DTOG
445 /**
446 * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
447 * @param USBx USB peripheral instance register address.
448 * @param bChNum Endpoint Number.
449 * @retval None
450 */
451 #define HCD_CLEAR_RX_DTOG USB_DRD_CLEAR_RX_DTOG
452 #define HCD_CLEAR_TX_DTOG USB_DRD_CLEAR_TX_DTOG
453
454 /**
455 * @brief sets counter for the tx/rx buffer.
456 * @param USBx USB peripheral instance register address.
457 * @param bChNum Endpoint Number.
458 * @param wCount Counter value.
459 * @retval None
460 */
461 #define HCD_SET_CH_TX_CNT USB_DRD_SET_CHEP_TX_CNT
462 #define HCD_SET_CH_RX_CNT USB_DRD_SET_CHEP_RX_CNT
463
464 /**
465 * @brief gets counter of the tx buffer.
466 * @param USBx USB peripheral instance register address.
467 * @param bChNum channel Number.
468 * @retval Counter value
469 */
470 #define HCD_GET_CH_TX_CNT USB_DRD_GET_CHEP_TX_CNT
471
472 /**
473 * @brief gets counter of the rx buffer.
474 * @param Instance USB peripheral instance register address.
475 * @param bChNum channel Number.
476 * @retval Counter value
477 */
HCD_GET_CH_RX_CNT(const HCD_TypeDef * Instance,uint16_t bChNum)478 __STATIC_INLINE uint16_t HCD_GET_CH_RX_CNT(const HCD_TypeDef *Instance, uint16_t bChNum)
479 {
480 UNUSED(Instance);
481 __IO uint32_t count = 10U;
482
483 /* WA: few cycles for RX PMA descriptor to update */
484 while (count > 0U)
485 {
486 count--;
487 }
488
489 return (uint16_t)USB_DRD_GET_CHEP_RX_CNT((Instance), (bChNum));
490 }
491
492 /**
493 * @brief Gets buffer 0/1 address of a double buffer endpoint.
494 * @param USBx USB peripheral instance register address.
495 * @param bChNum Endpoint Number.
496 * @param bDir endpoint dir EP_DBUF_OUT = OUT
497 * EP_DBUF_IN = IN
498 * @param wCount: Counter value
499 * @retval None
500 */
501 #define HCD_SET_CH_DBUF0_CNT USB_DRD_SET_CHEP_DBUF0_CNT
502 #define HCD_SET_CH_DBUF1_CNT USB_DRD_SET_CHEP_DBUF1_CNT
503 #define HCD_SET_CH_DBUF_CNT USB_DRD_SET_CHEP_DBUF_CNT
504
505
506 /**
507 * @brief gets counter of the rx buffer0.
508 * @param Instance USB peripheral instance register address.
509 * @param bChNum channel Number.
510 * @retval Counter value
511 */
HCD_GET_CH_DBUF0_CNT(const HCD_TypeDef * Instance,uint16_t bChNum)512 __STATIC_INLINE uint16_t HCD_GET_CH_DBUF0_CNT(const HCD_TypeDef *Instance, uint16_t bChNum)
513 {
514 UNUSED(Instance);
515 __IO uint32_t count = 10U;
516
517 /* WA: few cycles for RX PMA descriptor to update */
518 while (count > 0U)
519 {
520 count--;
521 }
522
523 return (uint16_t)USB_DRD_GET_CHEP_DBUF0_CNT((Instance), (bChNum));
524 }
525
526 /**
527 * @brief gets counter of the rx buffer1.
528 * @param Instance USB peripheral instance register address.
529 * @param bChNum channel Number.
530 * @retval Counter value
531 */
HCD_GET_CH_DBUF1_CNT(const HCD_TypeDef * Instance,uint16_t bChNum)532 __STATIC_INLINE uint16_t HCD_GET_CH_DBUF1_CNT(const HCD_TypeDef *Instance, uint16_t bChNum)
533 {
534 UNUSED(Instance);
535 __IO uint32_t count = 10U;
536
537 /* WA: few cycles for RX PMA descriptor to update */
538 while (count > 0U)
539 {
540 count--;
541 }
542
543 return (uint16_t)USB_DRD_GET_CHEP_DBUF1_CNT((Instance), (bChNum));
544 }
545
546 /**
547 * @}
548 */
549 /* Private functions prototypes ----------------------------------------------*/
550
551 /**
552 * @}
553 */
554 /**
555 * @}
556 */
557 #endif /* defined (USB_DRD_FS) */
558
559 #ifdef __cplusplus
560 }
561 #endif
562
563 #endif /* STM32G0xx_HAL_HCD_H */
564
