1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_dma.c
4 * @author MCD Application Team
5 * @brief DMA LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32f7xx_ll_dma.h"
22 #include "stm32f7xx_ll_bus.h"
23 #ifdef USE_FULL_ASSERT
24 #include "stm32_assert.h"
25 #else
26 #define assert_param(expr) ((void)0U)
27 #endif
28
29 /** @addtogroup STM32F7xx_LL_Driver
30 * @{
31 */
32
33 #if defined (DMA1) || defined (DMA2)
34
35 /** @defgroup DMA_LL DMA
36 * @{
37 */
38
39 /* Private types -------------------------------------------------------------*/
40 /* Private variables ---------------------------------------------------------*/
41 /* Private constants ---------------------------------------------------------*/
42 /* Private macros ------------------------------------------------------------*/
43 /** @addtogroup DMA_LL_Private_Macros
44 * @{
45 */
46 #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
47 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
48 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
49
50 #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
51 ((__VALUE__) == LL_DMA_MODE_CIRCULAR) || \
52 ((__VALUE__) == LL_DMA_MODE_PFCTRL))
53
54 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
55 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
56
57 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
58 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
59
60 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
61 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
62 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
63
64 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
65 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
66 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
67
68 #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
69
70 #if defined(DMA_CHANNEL_SELECTION_8_15)
71 #define IS_LL_DMA_CHANNEL(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_0) || \
72 ((__VALUE__) == LL_DMA_CHANNEL_1) || \
73 ((__VALUE__) == LL_DMA_CHANNEL_2) || \
74 ((__VALUE__) == LL_DMA_CHANNEL_3) || \
75 ((__VALUE__) == LL_DMA_CHANNEL_4) || \
76 ((__VALUE__) == LL_DMA_CHANNEL_5) || \
77 ((__VALUE__) == LL_DMA_CHANNEL_6) || \
78 ((__VALUE__) == LL_DMA_CHANNEL_7) || \
79 ((__VALUE__) == LL_DMA_CHANNEL_8) || \
80 ((__VALUE__) == LL_DMA_CHANNEL_9) || \
81 ((__VALUE__) == LL_DMA_CHANNEL_10) || \
82 ((__VALUE__) == LL_DMA_CHANNEL_11) || \
83 ((__VALUE__) == LL_DMA_CHANNEL_12) || \
84 ((__VALUE__) == LL_DMA_CHANNEL_13) || \
85 ((__VALUE__) == LL_DMA_CHANNEL_14) || \
86 ((__VALUE__) == LL_DMA_CHANNEL_15))
87
88 #else
89 #define IS_LL_DMA_CHANNEL(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_0) || \
90 ((__VALUE__) == LL_DMA_CHANNEL_1) || \
91 ((__VALUE__) == LL_DMA_CHANNEL_2) || \
92 ((__VALUE__) == LL_DMA_CHANNEL_3) || \
93 ((__VALUE__) == LL_DMA_CHANNEL_4) || \
94 ((__VALUE__) == LL_DMA_CHANNEL_5) || \
95 ((__VALUE__) == LL_DMA_CHANNEL_6) || \
96 ((__VALUE__) == LL_DMA_CHANNEL_7))
97
98 #endif /* DMA_CHANNEL_SELECTION_8_15 */
99
100 #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
101 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
102 ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
103 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
104
105 #define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM) ((((INSTANCE) == DMA1) && \
106 (((STREAM) == LL_DMA_STREAM_0) || \
107 ((STREAM) == LL_DMA_STREAM_1) || \
108 ((STREAM) == LL_DMA_STREAM_2) || \
109 ((STREAM) == LL_DMA_STREAM_3) || \
110 ((STREAM) == LL_DMA_STREAM_4) || \
111 ((STREAM) == LL_DMA_STREAM_5) || \
112 ((STREAM) == LL_DMA_STREAM_6) || \
113 ((STREAM) == LL_DMA_STREAM_7) || \
114 ((STREAM) == LL_DMA_STREAM_ALL))) ||\
115 (((INSTANCE) == DMA2) && \
116 (((STREAM) == LL_DMA_STREAM_0) || \
117 ((STREAM) == LL_DMA_STREAM_1) || \
118 ((STREAM) == LL_DMA_STREAM_2) || \
119 ((STREAM) == LL_DMA_STREAM_3) || \
120 ((STREAM) == LL_DMA_STREAM_4) || \
121 ((STREAM) == LL_DMA_STREAM_5) || \
122 ((STREAM) == LL_DMA_STREAM_6) || \
123 ((STREAM) == LL_DMA_STREAM_7) || \
124 ((STREAM) == LL_DMA_STREAM_ALL))))
125
126 #define IS_LL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \
127 ((STATE) == LL_DMA_FIFOMODE_ENABLE))
128
129 #define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4) || \
130 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2) || \
131 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4) || \
132 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL))
133
134 #define IS_LL_DMA_MEMORY_BURST(BURST) (((BURST) == LL_DMA_MBURST_SINGLE) || \
135 ((BURST) == LL_DMA_MBURST_INC4) || \
136 ((BURST) == LL_DMA_MBURST_INC8) || \
137 ((BURST) == LL_DMA_MBURST_INC16))
138
139 #define IS_LL_DMA_PERIPHERAL_BURST(BURST) (((BURST) == LL_DMA_PBURST_SINGLE) || \
140 ((BURST) == LL_DMA_PBURST_INC4) || \
141 ((BURST) == LL_DMA_PBURST_INC8) || \
142 ((BURST) == LL_DMA_PBURST_INC16))
143
144 /**
145 * @}
146 */
147
148 /* Private function prototypes -----------------------------------------------*/
149
150 /* Exported functions --------------------------------------------------------*/
151 /** @addtogroup DMA_LL_Exported_Functions
152 * @{
153 */
154
155 /** @addtogroup DMA_LL_EF_Init
156 * @{
157 */
158
159 /**
160 * @brief De-initialize the DMA registers to their default reset values.
161 * @param DMAx DMAx Instance
162 * @param Stream This parameter can be one of the following values:
163 * @arg @ref LL_DMA_STREAM_0
164 * @arg @ref LL_DMA_STREAM_1
165 * @arg @ref LL_DMA_STREAM_2
166 * @arg @ref LL_DMA_STREAM_3
167 * @arg @ref LL_DMA_STREAM_4
168 * @arg @ref LL_DMA_STREAM_5
169 * @arg @ref LL_DMA_STREAM_6
170 * @arg @ref LL_DMA_STREAM_7
171 * @arg @ref LL_DMA_STREAM_ALL
172 * @retval An ErrorStatus enumeration value:
173 * - SUCCESS: DMA registers are de-initialized
174 * - ERROR: DMA registers are not de-initialized
175 */
LL_DMA_DeInit(DMA_TypeDef * DMAx,uint32_t Stream)176 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream)
177 {
178 DMA_Stream_TypeDef *tmp = (DMA_Stream_TypeDef *)DMA1_Stream0;
179 ErrorStatus status = SUCCESS;
180
181 /* Check the DMA Instance DMAx and Stream parameters*/
182 assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
183
184 if (Stream == LL_DMA_STREAM_ALL)
185 {
186 if (DMAx == DMA1)
187 {
188 /* Force reset of DMA clock */
189 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
190
191 /* Release reset of DMA clock */
192 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
193 }
194 else if (DMAx == DMA2)
195 {
196 /* Force reset of DMA clock */
197 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
198
199 /* Release reset of DMA clock */
200 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
201 }
202 else
203 {
204 status = ERROR;
205 }
206 }
207 else
208 {
209 /* Disable the selected Stream */
210 LL_DMA_DisableStream(DMAx,Stream);
211
212 /* Get the DMA Stream Instance */
213 tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream));
214
215 /* Reset DMAx_Streamy configuration register */
216 LL_DMA_WriteReg(tmp, CR, 0U);
217
218 /* Reset DMAx_Streamy remaining bytes register */
219 LL_DMA_WriteReg(tmp, NDTR, 0U);
220
221 /* Reset DMAx_Streamy peripheral address register */
222 LL_DMA_WriteReg(tmp, PAR, 0U);
223
224 /* Reset DMAx_Streamy memory address register */
225 LL_DMA_WriteReg(tmp, M0AR, 0U);
226
227 /* Reset DMAx_Streamy memory address register */
228 LL_DMA_WriteReg(tmp, M1AR, 0U);
229
230 /* Reset DMAx_Streamy FIFO control register */
231 LL_DMA_WriteReg(tmp, FCR, 0x00000021U);
232
233 /* Reset Channel register field for DMAx Stream*/
234 LL_DMA_SetChannelSelection(DMAx, Stream, LL_DMA_CHANNEL_0);
235
236 if(Stream == LL_DMA_STREAM_0)
237 {
238 /* Reset the Stream0 pending flags */
239 DMAx->LIFCR = 0x0000003FU;
240 }
241 else if(Stream == LL_DMA_STREAM_1)
242 {
243 /* Reset the Stream1 pending flags */
244 DMAx->LIFCR = 0x00000F40U;
245 }
246 else if(Stream == LL_DMA_STREAM_2)
247 {
248 /* Reset the Stream2 pending flags */
249 DMAx->LIFCR = 0x003F0000U;
250 }
251 else if(Stream == LL_DMA_STREAM_3)
252 {
253 /* Reset the Stream3 pending flags */
254 DMAx->LIFCR = 0x0F400000U;
255 }
256 else if(Stream == LL_DMA_STREAM_4)
257 {
258 /* Reset the Stream4 pending flags */
259 DMAx->HIFCR = 0x0000003FU;
260 }
261 else if(Stream == LL_DMA_STREAM_5)
262 {
263 /* Reset the Stream5 pending flags */
264 DMAx->HIFCR = 0x00000F40U;
265 }
266 else if(Stream == LL_DMA_STREAM_6)
267 {
268 /* Reset the Stream6 pending flags */
269 DMAx->HIFCR = 0x003F0000U;
270 }
271 else if(Stream == LL_DMA_STREAM_7)
272 {
273 /* Reset the Stream7 pending flags */
274 DMAx->HIFCR = 0x0F400000U;
275 }
276 else
277 {
278 status = ERROR;
279 }
280 }
281
282 return status;
283 }
284
285 /**
286 * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
287 * @note To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros :
288 * @arg @ref __LL_DMA_GET_INSTANCE
289 * @arg @ref __LL_DMA_GET_STREAM
290 * @param DMAx DMAx Instance
291 * @param Stream This parameter can be one of the following values:
292 * @arg @ref LL_DMA_STREAM_0
293 * @arg @ref LL_DMA_STREAM_1
294 * @arg @ref LL_DMA_STREAM_2
295 * @arg @ref LL_DMA_STREAM_3
296 * @arg @ref LL_DMA_STREAM_4
297 * @arg @ref LL_DMA_STREAM_5
298 * @arg @ref LL_DMA_STREAM_6
299 * @arg @ref LL_DMA_STREAM_7
300 * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
301 * @retval An ErrorStatus enumeration value:
302 * - SUCCESS: DMA registers are initialized
303 * - ERROR: Not applicable
304 */
LL_DMA_Init(DMA_TypeDef * DMAx,uint32_t Stream,LL_DMA_InitTypeDef * DMA_InitStruct)305 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct)
306 {
307 /* Check the DMA Instance DMAx and Stream parameters*/
308 assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
309
310 /* Check the DMA parameters from DMA_InitStruct */
311 assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
312 assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
313 assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
314 assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
315 assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
316 assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
317 assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
318 assert_param(IS_LL_DMA_CHANNEL(DMA_InitStruct->Channel));
319 assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
320 assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode));
321 /* Check the memory burst, peripheral burst and FIFO threshold parameters only
322 when FIFO mode is enabled */
323 if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
324 {
325 assert_param(IS_LL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold));
326 assert_param(IS_LL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst));
327 assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst));
328 }
329
330 /*---------------------------- DMAx SxCR Configuration ------------------------
331 * Configure DMAx_Streamy: data transfer direction, data transfer mode,
332 * peripheral and memory increment mode,
333 * data size alignment and priority level with parameters :
334 * - Direction: DMA_SxCR_DIR[1:0] bits
335 * - Mode: DMA_SxCR_CIRC bit
336 * - PeriphOrM2MSrcIncMode: DMA_SxCR_PINC bit
337 * - MemoryOrM2MDstIncMode: DMA_SxCR_MINC bit
338 * - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits
339 * - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits
340 * - Priority: DMA_SxCR_PL[1:0] bits
341 */
342 LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \
343 DMA_InitStruct->Mode | \
344 DMA_InitStruct->PeriphOrM2MSrcIncMode | \
345 DMA_InitStruct->MemoryOrM2MDstIncMode | \
346 DMA_InitStruct->PeriphOrM2MSrcDataSize | \
347 DMA_InitStruct->MemoryOrM2MDstDataSize | \
348 DMA_InitStruct->Priority
349 );
350
351 if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
352 {
353 /*---------------------------- DMAx SxFCR Configuration ------------------------
354 * Configure DMAx_Streamy: fifo mode and fifo threshold with parameters :
355 * - FIFOMode: DMA_SxFCR_DMDIS bit
356 * - FIFOThreshold: DMA_SxFCR_FTH[1:0] bits
357 */
358 LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold);
359
360 /*---------------------------- DMAx SxCR Configuration --------------------------
361 * Configure DMAx_Streamy: memory burst transfer with parameters :
362 * - MemBurst: DMA_SxCR_MBURST[1:0] bits
363 */
364 LL_DMA_SetMemoryBurstxfer(DMAx,Stream,DMA_InitStruct->MemBurst);
365
366 /*---------------------------- DMAx SxCR Configuration --------------------------
367 * Configure DMAx_Streamy: peripheral burst transfer with parameters :
368 * - PeriphBurst: DMA_SxCR_PBURST[1:0] bits
369 */
370 LL_DMA_SetPeriphBurstxfer(DMAx,Stream,DMA_InitStruct->PeriphBurst);
371 }
372
373 /*-------------------------- DMAx SxM0AR Configuration --------------------------
374 * Configure the memory or destination base address with parameter :
375 * - MemoryOrM2MDstAddress: DMA_SxM0AR_M0A[31:0] bits
376 */
377 LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress);
378
379 /*-------------------------- DMAx SxPAR Configuration ---------------------------
380 * Configure the peripheral or source base address with parameter :
381 * - PeriphOrM2MSrcAddress: DMA_SxPAR_PA[31:0] bits
382 */
383 LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress);
384
385 /*--------------------------- DMAx SxNDTR Configuration -------------------------
386 * Configure the peripheral base address with parameter :
387 * - NbData: DMA_SxNDT[15:0] bits
388 */
389 LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData);
390
391 /*--------------------------- DMA SxCR_CHSEL Configuration ----------------------
392 * Configure the peripheral base address with parameter :
393 * - PeriphRequest: DMA_SxCR_CHSEL[3:0] bits
394 */
395 LL_DMA_SetChannelSelection(DMAx, Stream, DMA_InitStruct->Channel);
396
397 return SUCCESS;
398 }
399
400 /**
401 * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
402 * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
403 * @retval None
404 */
LL_DMA_StructInit(LL_DMA_InitTypeDef * DMA_InitStruct)405 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
406 {
407 /* Set DMA_InitStruct fields to default values */
408 DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
409 DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
410 DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
411 DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
412 DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
413 DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
414 DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
415 DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
416 DMA_InitStruct->NbData = 0x00000000U;
417 DMA_InitStruct->Channel = LL_DMA_CHANNEL_0;
418 DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
419 DMA_InitStruct->FIFOMode = LL_DMA_FIFOMODE_DISABLE;
420 DMA_InitStruct->FIFOThreshold = LL_DMA_FIFOTHRESHOLD_1_4;
421 DMA_InitStruct->MemBurst = LL_DMA_MBURST_SINGLE;
422 DMA_InitStruct->PeriphBurst = LL_DMA_PBURST_SINGLE;
423 }
424
425 /**
426 * @}
427 */
428
429 /**
430 * @}
431 */
432
433 /**
434 * @}
435 */
436
437 #endif /* DMA1 || DMA2 */
438
439 /**
440 * @}
441 */
442
443 #endif /* USE_FULL_LL_DRIVER */
444
445
