1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 ******************************************************************************
16 */
17
18 /* Define to prevent recursive inclusion -------------------------------------*/
19 #ifndef __STM32F7xx_LL_RCC_H
20 #define __STM32F7xx_LL_RCC_H
21
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25
26 /* Includes ------------------------------------------------------------------*/
27 #include "stm32f7xx.h"
28
29 /** @addtogroup STM32F7xx_LL_Driver
30 * @{
31 */
32
33 #if defined(RCC)
34
35 /** @defgroup RCC_LL RCC
36 * @{
37 */
38
39 /* Private types -------------------------------------------------------------*/
40 /* Private variables ---------------------------------------------------------*/
41 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
42 * @{
43 */
44
45 #if defined(RCC_DCKCFGR1_PLLSAIDIVR)
46 static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16};
47 #endif /* RCC_DCKCFGR1_PLLSAIDIVR */
48
49 /**
50 * @}
51 */
52 /* Private constants ---------------------------------------------------------*/
53 /* Private macros ------------------------------------------------------------*/
54 #if defined(USE_FULL_LL_DRIVER)
55 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
56 * @{
57 */
58 /**
59 * @}
60 */
61 #endif /*USE_FULL_LL_DRIVER*/
62 /* Exported types ------------------------------------------------------------*/
63 #if defined(USE_FULL_LL_DRIVER)
64 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
65 * @{
66 */
67
68 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
69 * @{
70 */
71
72 /**
73 * @brief RCC Clocks Frequency Structure
74 */
75 typedef struct
76 {
77 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
78 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
79 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
80 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
81 } LL_RCC_ClocksTypeDef;
82
83 /**
84 * @}
85 */
86
87 /**
88 * @}
89 */
90 #endif /* USE_FULL_LL_DRIVER */
91
92 /* Exported constants --------------------------------------------------------*/
93 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
94 * @{
95 */
96
97 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
98 * @brief Defines used to adapt values of different oscillators
99 * @note These values could be modified in the user environment according to
100 * HW set-up.
101 * @{
102 */
103 #if !defined (HSE_VALUE)
104 #define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */
105 #endif /* HSE_VALUE */
106
107 #if !defined (HSI_VALUE)
108 #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
109 #endif /* HSI_VALUE */
110
111 #if !defined (LSE_VALUE)
112 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
113 #endif /* LSE_VALUE */
114
115 #if !defined (LSI_VALUE)
116 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
117 #endif /* LSI_VALUE */
118
119 #if !defined (EXTERNAL_CLOCK_VALUE)
120 #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
121 #endif /* EXTERNAL_CLOCK_VALUE */
122
123 #if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
124 #define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1_EXTCLK external oscillator in Hz */
125 #endif /* EXTERNAL_SAI1_CLOCK_VALUE */
126
127 #if !defined (EXTERNAL_SAI2_CLOCK_VALUE)
128 #define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2_EXTCLK external oscillator in Hz */
129 #endif /* EXTERNAL_SAI2_CLOCK_VALUE */
130 /**
131 * @}
132 */
133
134 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
135 * @brief Flags defines which can be used with LL_RCC_WriteReg function
136 * @{
137 */
138 #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */
139 #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */
140 #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */
141 #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */
142 #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */
143 #define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC /*!< PLLI2S Ready Interrupt Clear */
144 #define LL_RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC /*!< PLLSAI Ready Interrupt Clear */
145 #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */
146 /**
147 * @}
148 */
149
150 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
151 * @brief Flags defines which can be used with LL_RCC_ReadReg function
152 * @{
153 */
154 #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */
155 #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */
156 #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */
157 #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */
158 #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */
159 #define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF /*!< PLLI2S Ready Interrupt flag */
160 #define LL_RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF /*!< PLLSAI Ready Interrupt flag */
161 #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */
162 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
163 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
164 #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */
165 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
166 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
167 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
168 #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */
169 /**
170 * @}
171 */
172
173 /** @defgroup RCC_LL_EC_IT IT Defines
174 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
175 * @{
176 */
177 #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */
178 #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */
179 #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */
180 #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */
181 #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */
182 #define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE /*!< PLLI2S Ready Interrupt Enable */
183 #define LL_RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE /*!< PLLSAI Ready Interrupt Enable */
184 /**
185 * @}
186 */
187
188 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
189 * @{
190 */
191 #define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */
192 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */
193 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */
194 #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
195 /**
196 * @}
197 */
198
199 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
200 * @{
201 */
202 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
203 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
204 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
205 /**
206 * @}
207 */
208
209 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
210 * @{
211 */
212 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
213 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
214 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
215 /**
216 * @}
217 */
218
219 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
220 * @{
221 */
222 #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
223 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
224 #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
225 #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
226 #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
227 #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
228 #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
229 #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
230 #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
231 /**
232 * @}
233 */
234
235 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
236 * @{
237 */
238 #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
239 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
240 #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
241 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
242 #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
243 /**
244 * @}
245 */
246 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
247 * @{
248 */
249 #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
250 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
251 #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
252 #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
253 #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
254 /**
255 * @}
256 */
257
258 /** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection
259 * @{
260 */
261 #define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1|0x00000000U) /*!< HSI selection as MCO1 source */
262 #define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U)) /*!< LSE selection as MCO1 source */
263 #define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U)) /*!< HSE selection as MCO1 source */
264 #define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) >> 16U)) /*!< PLLCLK selection as MCO1 source */
265 #define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2|0x00000000U) /*!< SYSCLK selection as MCO2 source */
266 #define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U)) /*!< PLLI2S selection as MCO2 source */
267 #define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U)) /*!< HSE selection as MCO2 source */
268 #define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) >> 16U)) /*!< PLLCLK selection as MCO2 source */
269 /**
270 * @}
271 */
272
273 /** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler
274 * @{
275 */
276 #define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U) /*!< MCO1 not divided */
277 #define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U)) /*!< MCO1 divided by 2 */
278 #define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_0) >> 16U)) /*!< MCO1 divided by 3 */
279 #define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_1) >> 16U)) /*!< MCO1 divided by 4 */
280 #define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U)) /*!< MCO1 divided by 5 */
281 #define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U) /*!< MCO2 not divided */
282 #define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U)) /*!< MCO2 divided by 2 */
283 #define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_0) >> 16U)) /*!< MCO2 divided by 3 */
284 #define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_1) >> 16U)) /*!< MCO2 divided by 4 */
285 #define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U)) /*!< MCO2 divided by 5 */
286 /**
287 * @}
288 */
289
290 /** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock
291 * @{
292 */
293 #define LL_RCC_RTC_NOCLOCK 0x00000000U /*!< HSE not divided */
294 #define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 /*!< HSE clock divided by 2 */
295 #define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 3 */
296 #define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 /*!< HSE clock divided by 4 */
297 #define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 5 */
298 #define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 6 */
299 #define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 7 */
300 #define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 /*!< HSE clock divided by 8 */
301 #define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 9 */
302 #define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 10 */
303 #define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 11 */
304 #define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 12 */
305 #define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 13 */
306 #define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 14 */
307 #define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 15 */
308 #define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 /*!< HSE clock divided by 16 */
309 #define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 17 */
310 #define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 18 */
311 #define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 19 */
312 #define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 20 */
313 #define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 21 */
314 #define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 22 */
315 #define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 23 */
316 #define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) /*!< HSE clock divided by 24 */
317 #define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 25 */
318 #define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 26 */
319 #define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 27 */
320 #define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 28 */
321 #define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 29 */
322 #define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 30 */
323 #define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 31 */
324 /**
325 * @}
326 */
327
328 #if defined(USE_FULL_LL_DRIVER)
329 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
330 * @{
331 */
332 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
333 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
334 /**
335 * @}
336 */
337 #endif /* USE_FULL_LL_DRIVER */
338
339 /** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection
340 * @{
341 */
342 #define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | 0x00000000U) /*!< PCLK2 clock used as USART1 clock source */
343 #define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR2_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */
344 #define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR2_USART1SEL_1) /*!< HSI clock used as USART1 clock source */
345 #define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR2_USART1SEL) /*!< LSE clock used as USART1 clock source */
346 #define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as USART2 clock source */
347 #define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR2_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */
348 #define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR2_USART2SEL_1) /*!< HSI clock used as USART2 clock source */
349 #define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR2_USART2SEL) /*!< LSE clock used as USART2 clock source */
350 #define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as USART3 clock source */
351 #define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR2_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */
352 #define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR2_USART3SEL_1) /*!< HSI clock used as USART3 clock source */
353 #define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR2_USART3SEL) /*!< LSE clock used as USART3 clock source */
354 #define LL_RCC_USART6_CLKSOURCE_PCLK2 (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | 0x00000000U) /*!< PCLK2 clock used as USART6 clock source */
355 #define LL_RCC_USART6_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR2_USART6SEL_0) /*!< SYSCLK clock used as USART6 clock source */
356 #define LL_RCC_USART6_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR2_USART6SEL_1) /*!< HSI clock used as USART6 clock source */
357 #define LL_RCC_USART6_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR2_USART6SEL) /*!< LSE clock used as USART6 clock source */
358 /**
359 * @}
360 */
361
362 /** @defgroup RCC_LL_EC_UARTx_CLKSOURCE Peripheral UART clock source selection
363 * @{
364 */
365 #define LL_RCC_UART4_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as UART4 clock source */
366 #define LL_RCC_UART4_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_UART4SEL_0) /*!< SYSCLK clock used as UART4 clock source */
367 #define LL_RCC_UART4_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_UART4SEL_1) /*!< HSI clock used as UART4 clock source */
368 #define LL_RCC_UART4_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_UART4SEL) /*!< LSE clock used as UART4 clock source */
369 #define LL_RCC_UART5_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as UART5 clock source */
370 #define LL_RCC_UART5_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_UART5SEL_0) /*!< SYSCLK clock used as UART5 clock source */
371 #define LL_RCC_UART5_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_UART5SEL_1) /*!< HSI clock used as UART5 clock source */
372 #define LL_RCC_UART5_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_UART5SEL) /*!< LSE clock used as UART5 clock source */
373 #define LL_RCC_UART7_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as UART7 clock source */
374 #define LL_RCC_UART7_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_UART7SEL_0) /*!< SYSCLK clock used as UART7 clock source */
375 #define LL_RCC_UART7_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_UART7SEL_1) /*!< HSI clock used as UART7 clock source */
376 #define LL_RCC_UART7_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_UART7SEL) /*!< LSE clock used as UART7 clock source */
377 #define LL_RCC_UART8_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as UART8 clock source */
378 #define LL_RCC_UART8_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_UART8SEL_0) /*!< SYSCLK clock used as UART8 clock source */
379 #define LL_RCC_UART8_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_UART8SEL_1) /*!< HSI clock used as UART8 clock source */
380 #define LL_RCC_UART8_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_UART8SEL) /*!< LSE clock used as UART8 clock source */
381 /**
382 * @}
383 */
384
385 /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection
386 * @{
387 */
388 #define LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C1SEL|0x00000000U) /*!< PCLK1 clock used as I2C1 clock source */
389 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C1SEL|(RCC_DCKCFGR2_I2C1SEL_0 >> 16U)) /*!< SYSCLK clock used as I2C1 clock source */
390 #define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C1SEL|(RCC_DCKCFGR2_I2C1SEL_1 >> 16U)) /*!< HSI clock used as I2C1 clock source */
391 #define LL_RCC_I2C2_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C2SEL|0x00000000U) /*!< PCLK1 clock used as I2C2 clock source */
392 #define LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C2SEL|(RCC_DCKCFGR2_I2C2SEL_0 >> 16U)) /*!< SYSCLK clock used as I2C2 clock source */
393 #define LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C2SEL|(RCC_DCKCFGR2_I2C2SEL_1 >> 16U)) /*!< HSI clock used as I2C2 clock source */
394 #define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C3SEL|0x00000000U) /*!< PCLK1 clock used as I2C3 clock source */
395 #define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C3SEL|(RCC_DCKCFGR2_I2C3SEL_0 >> 16U)) /*!< SYSCLK clock used as I2C3 clock source */
396 #define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C3SEL|(RCC_DCKCFGR2_I2C3SEL_1 >> 16U)) /*!< HSI clock used as I2C3 clock source */
397 #if defined(I2C4)
398 #define LL_RCC_I2C4_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C4SEL|0x00000000U) /*!< PCLK1 clock used as I2C4 clock source */
399 #define LL_RCC_I2C4_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C4SEL|(RCC_DCKCFGR2_I2C4SEL_0 >> 16U)) /*!< SYSCLK clock used as I2C4 clock source */
400 #define LL_RCC_I2C4_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C4SEL|(RCC_DCKCFGR2_I2C4SEL_1 >> 16U)) /*!< HSI clock used as I2C4 clock source */
401 #endif /* I2C4 */
402 /**
403 * @}
404 */
405
406 /** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection
407 * @{
408 */
409 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPTIM1 clock */
410 #define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0 /*!< LSI oscillator clock used as LPTIM1 clock */
411 #define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1 /*!< HSI oscillator clock used as LPTIM1 clock */
412 #define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTIM1SEL_0) /*!< LSE oscillator clock used as LPTIM1 clock */
413 /**
414 * @}
415 */
416
417 /** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection
418 * @{
419 */
420 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR1_SAI1SEL | 0x00000000U) /*!< PLLSAI clock used as SAI1 clock source */
421 #define LL_RCC_SAI1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL_0 >> 16U)) /*!< PLLI2S clock used as SAI1 clock source */
422 #define LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL_1 >> 16U)) /*!< External pin clock used as SAI1 clock source */
423 #if defined(RCC_SAI1SEL_PLLSRC_SUPPORT)
424 #define LL_RCC_SAI1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL >> 16U)) /*!< Main source clock used as SAI1 clock source */
425 #endif /* RCC_SAI1SEL_PLLSRC_SUPPORT */
426 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR1_SAI2SEL | 0x00000000U) /*!< PLLSAI clock used as SAI2 clock source */
427 #define LL_RCC_SAI2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL_0 >> 16U)) /*!< PLLI2S clock used as SAI2 clock source */
428 #define LL_RCC_SAI2_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL_1 >> 16U)) /*!< External pin clock used as SAI2 clock source */
429 #if defined(RCC_SAI2SEL_PLLSRC_SUPPORT)
430 #define LL_RCC_SAI2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL >> 16U)) /*!< Main source clock used as SAI2 clock source */
431 #endif /* RCC_SAI2SEL_PLLSRC_SUPPORT */
432 /**
433 * @}
434 */
435
436 /** @defgroup RCC_LL_EC_SDMMCx_CLKSOURCE Peripheral SDMMC clock source selection
437 * @{
438 */
439 #define LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK (uint32_t)(RCC_DCKCFGR2_SDMMC1SEL | 0x00000000U) /*!< PLL 48M domain clock used as SDMMC1 clock */
440 #define LL_RCC_SDMMC1_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_SDMMC1SEL | (RCC_DCKCFGR2_SDMMC1SEL >> 16U)) /*!< System clock clock used as SDMMC1 clock */
441 #if defined(SDMMC2)
442 #define LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (uint32_t)(RCC_DCKCFGR2_SDMMC2SEL | 0x00000000U) /*!< PLL 48M domain clock used as SDMMC2 clock */
443 #define LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_SDMMC2SEL | (RCC_DCKCFGR2_SDMMC2SEL >> 16U)) /*!< System clock clock used as SDMMC2 clock */
444 #endif /* SDMMC2 */
445 /**
446 * @}
447 */
448
449 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
450 * @{
451 */
452 #define LL_RCC_RNG_CLKSOURCE_PLL 0x00000000U /*!< PLL clock used as RNG clock source */
453 #define LL_RCC_RNG_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI clock used as RNG clock source */
454 /**
455 * @}
456 */
457
458 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
459 * @{
460 */
461 #define LL_RCC_USB_CLKSOURCE_PLL 0x00000000U /*!< PLL clock used as USB clock source */
462 #define LL_RCC_USB_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI1 clock used as USB clock source */
463 /**
464 * @}
465 */
466
467 #if defined(DSI)
468 /** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection
469 * @{
470 */
471 #define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /*!< DSI-PHY clock used as DSI byte lane clock source */
472 #define LL_RCC_DSI_CLKSOURCE_PLL RCC_DCKCFGR2_DSISEL /*!< PLL clock used as DSI byte lane clock source */
473 /**
474 * @}
475 */
476 #endif /* DSI */
477
478 #if defined(CEC)
479 /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
480 * @{
481 */
482 #define LL_RCC_CEC_CLKSOURCE_LSE 0x00000000U /*!< LSE oscillator clock used as CEC clock */
483 #define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 RCC_DCKCFGR2_CECSEL /*!< HSI oscillator clock divided by 488 used as CEC clock */
484 /**
485 * @}
486 */
487 #endif /* CEC */
488
489 /** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection
490 * @{
491 */
492 #define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U /*!< I2S oscillator clock used as I2S1 clock */
493 #define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC /*!< External pin clock used as I2S1 clock */
494 /**
495 * @}
496 */
497
498 /** @defgroup RCC_LL_EC_CK48M_CLKSOURCE Peripheral 48Mhz domain clock source selection
499 * @{
500 */
501 #define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /*!< PLL oscillator clock used as 48Mhz domain clock */
502 #define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI oscillator clock used as 48Mhz domain clock */
503 /**
504 * @}
505 */
506
507 #if defined(DFSDM1_Channel0)
508 /** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM Audio clock source selection
509 * @{
510 */
511 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 0x00000000U /*!< SAI1 clock used as DFSDM1 Audio clock */
512 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2 RCC_DCKCFGR1_ADFSDM1SEL /*!< SAI2 clock used as DFSDM1 Audio clock */
513 /**
514 * @}
515 */
516
517 /** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM clock source selection
518 * @{
519 */
520 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as DFSDM1 clock */
521 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_DCKCFGR1_DFSDM1SEL /*!< System clock used as DFSDM1 clock */
522 /**
523 * @}
524 */
525 #endif /* DFSDM1_Channel0 */
526
527 /** @defgroup RCC_LL_EC_USARTx Peripheral USART get clock source
528 * @{
529 */
530 #define LL_RCC_USART1_CLKSOURCE RCC_DCKCFGR2_USART1SEL /*!< USART1 Clock source selection */
531 #define LL_RCC_USART2_CLKSOURCE RCC_DCKCFGR2_USART2SEL /*!< USART2 Clock source selection */
532 #define LL_RCC_USART3_CLKSOURCE RCC_DCKCFGR2_USART3SEL /*!< USART3 Clock source selection */
533 #define LL_RCC_USART6_CLKSOURCE RCC_DCKCFGR2_USART6SEL /*!< USART6 Clock source selection */
534 /**
535 * @}
536 */
537
538 /** @defgroup RCC_LL_EC_UARTx Peripheral UART get clock source
539 * @{
540 */
541 #define LL_RCC_UART4_CLKSOURCE RCC_DCKCFGR2_UART4SEL /*!< UART4 Clock source selection */
542 #define LL_RCC_UART5_CLKSOURCE RCC_DCKCFGR2_UART5SEL /*!< UART5 Clock source selection */
543 #define LL_RCC_UART7_CLKSOURCE RCC_DCKCFGR2_UART7SEL /*!< UART7 Clock source selection */
544 #define LL_RCC_UART8_CLKSOURCE RCC_DCKCFGR2_UART8SEL /*!< UART8 Clock source selection */
545 /**
546 * @}
547 */
548
549 /** @defgroup RCC_LL_EC_I2Cx Peripheral I2C get clock source
550 * @{
551 */
552 #define LL_RCC_I2C1_CLKSOURCE RCC_DCKCFGR2_I2C1SEL /*!< I2C1 Clock source selection */
553 #define LL_RCC_I2C2_CLKSOURCE RCC_DCKCFGR2_I2C2SEL /*!< I2C2 Clock source selection */
554 #define LL_RCC_I2C3_CLKSOURCE RCC_DCKCFGR2_I2C3SEL /*!< I2C3 Clock source selection */
555 #if defined(I2C4)
556 #define LL_RCC_I2C4_CLKSOURCE RCC_DCKCFGR2_I2C4SEL /*!< I2C4 Clock source selection */
557 #endif /* I2C4 */
558 /**
559 * @}
560 */
561
562 /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
563 * @{
564 */
565 #define LL_RCC_LPTIM1_CLKSOURCE RCC_DCKCFGR2_LPTIM1SEL /*!< LPTIM1 Clock source selection */
566 /**
567 * @}
568 */
569
570 /** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source
571 * @{
572 */
573 #define LL_RCC_SAI1_CLKSOURCE RCC_DCKCFGR1_SAI1SEL /*!< SAI1 Clock source selection */
574 #define LL_RCC_SAI2_CLKSOURCE RCC_DCKCFGR1_SAI2SEL /*!< SAI2 Clock source selection */
575 /**
576 * @}
577 */
578
579 /** @defgroup RCC_LL_EC_SDMMCx Peripheral SDMMC get clock source
580 * @{
581 */
582 #define LL_RCC_SDMMC1_CLKSOURCE RCC_DCKCFGR2_SDMMC1SEL /*!< SDMMC1 Clock source selection */
583 #if defined(SDMMC2)
584 #define LL_RCC_SDMMC2_CLKSOURCE RCC_DCKCFGR2_SDMMC2SEL /*!< SDMMC2 Clock source selection */
585 #endif /* SDMMC2 */
586 /**
587 * @}
588 */
589
590 /** @defgroup RCC_LL_EC_CK48M Peripheral CK48M get clock source
591 * @{
592 */
593 #define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< CK48M Domain clock source selection */
594 /**
595 * @}
596 */
597
598 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
599 * @{
600 */
601 #define LL_RCC_RNG_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< RNG Clock source selection */
602 /**
603 * @}
604 */
605
606 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
607 * @{
608 */
609 #define LL_RCC_USB_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< USB Clock source selection */
610 /**
611 * @}
612 */
613
614 #if defined(CEC)
615 /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
616 * @{
617 */
618 #define LL_RCC_CEC_CLKSOURCE RCC_DCKCFGR2_CECSEL /*!< CEC Clock source selection */
619 /**
620 * @}
621 */
622 #endif /* CEC */
623
624 /** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source
625 * @{
626 */
627 #define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S Clock source selection */
628 /**
629 * @}
630 */
631 #if defined(DFSDM1_Channel0)
632 /** @defgroup RCC_LL_EC_DFSDM_AUDIO Peripheral DFSDM Audio get clock source
633 * @{
634 */
635 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_DCKCFGR1_ADFSDM1SEL /*!< DFSDM Audio Clock source selection */
636 /**
637 * @}
638 */
639
640 /** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source
641 * @{
642 */
643 #define LL_RCC_DFSDM1_CLKSOURCE RCC_DCKCFGR1_DFSDM1SEL /*!< DFSDM Clock source selection */
644 /**
645 * @}
646 */
647 #endif /* DFSDM1_Channel0 */
648
649 #if defined(DSI)
650 /** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source
651 * @{
652 */
653 #define LL_RCC_DSI_CLKSOURCE RCC_DCKCFGR2_DSISEL /*!< DSI Clock source selection */
654 /**
655 * @}
656 */
657 #endif /* DSI */
658
659 #if defined(LTDC)
660 /** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source
661 * @{
662 */
663 #define LL_RCC_LTDC_CLKSOURCE RCC_DCKCFGR1_PLLSAIDIVR /*!< LTDC Clock source selection */
664 /**
665 * @}
666 */
667 #endif /* LTDC */
668
669 #if defined(SPDIFRX)
670 /** @defgroup RCC_LL_EC_SPDIFRX Peripheral SPDIFRX get clock source
671 * @{
672 */
673 #define LL_RCC_SPDIFRX1_CLKSOURCE RCC_PLLI2SCFGR_PLLI2SP /*!< SPDIFRX Clock source selection */
674 /**
675 * @}
676 */
677 #endif /* SPDIFRX */
678
679 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
680 * @{
681 */
682 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
683 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
684 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
685 #define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by HSE prescaler used as RTC clock */
686 /**
687 * @}
688 */
689
690 /** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection
691 * @{
692 */
693 #define LL_RCC_TIM_PRESCALER_TWICE 0x00000000U /*!< Timers clock to twice PCLK */
694 #define LL_RCC_TIM_PRESCALER_FOUR_TIMES RCC_DCKCFGR1_TIMPRE /*!< Timers clock to four time PCLK */
695 /**
696 * @}
697 */
698
699 /** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLI2S and PLLSAI entry clock source
700 * @{
701 */
702 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */
703 #define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
704 /**
705 * @}
706 */
707
708 /** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLI2S and PLLSAI division factor
709 * @{
710 */
711 #define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 2 */
712 #define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 3 */
713 #define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 4 */
714 #define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 5 */
715 #define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 6 */
716 #define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 7 */
717 #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 8 */
718 #define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 9 */
719 #define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 10 */
720 #define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 11 */
721 #define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 12 */
722 #define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 13 */
723 #define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 14 */
724 #define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 15 */
725 #define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 16 */
726 #define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 17 */
727 #define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 18 */
728 #define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 19 */
729 #define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 20 */
730 #define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 21 */
731 #define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 22 */
732 #define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 23 */
733 #define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 24 */
734 #define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 25 */
735 #define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 26 */
736 #define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 27 */
737 #define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 28 */
738 #define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 29 */
739 #define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 30 */
740 #define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 31 */
741 #define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) /*!< PLL, PLLI2S and PLLSAI division factor by 32 */
742 #define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 33 */
743 #define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 34 */
744 #define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 35 */
745 #define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 36 */
746 #define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 37 */
747 #define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 38 */
748 #define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 39 */
749 #define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 40 */
750 #define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 41 */
751 #define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 42 */
752 #define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 43 */
753 #define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 44 */
754 #define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 45 */
755 #define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 46 */
756 #define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 47 */
757 #define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 48 */
758 #define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 49 */
759 #define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 50 */
760 #define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 51 */
761 #define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 52 */
762 #define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 53 */
763 #define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 54 */
764 #define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 55 */
765 #define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 56 */
766 #define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 57 */
767 #define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 58 */
768 #define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 59 */
769 #define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 60 */
770 #define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 61 */
771 #define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 62 */
772 #define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 63 */
773 /**
774 * @}
775 */
776
777 #if defined(RCC_PLLCFGR_PLLR)
778 /** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
779 * @{
780 */
781 #define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
782 #define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 3 */
783 #define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_2) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
784 #define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 5 */
785 #define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
786 #define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 7 */
787 /**
788 * @}
789 */
790 #endif /* RCC_PLLCFGR_PLLR */
791
792 /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
793 * @{
794 */
795 #define LL_RCC_PLLP_DIV_2 0x00000000U /*!< Main PLL division factor for PLLP output by 2 */
796 #define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 /*!< Main PLL division factor for PLLP output by 4 */
797 #define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 /*!< Main PLL division factor for PLLP output by 6 */
798 #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 8 */
799 /**
800 * @}
801 */
802
803 /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
804 * @{
805 */
806 #define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 /*!< Main PLL division factor for PLLQ output by 2 */
807 #define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 3 */
808 #define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 /*!< Main PLL division factor for PLLQ output by 4 */
809 #define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 5 */
810 #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */
811 #define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 7 */
812 #define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 /*!< Main PLL division factor for PLLQ output by 8 */
813 #define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 9 */
814 #define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 10 */
815 #define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 11 */
816 #define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 12 */
817 #define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 13 */
818 #define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 14 */
819 #define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 15 */
820 /**
821 * @}
822 */
823
824 /** @defgroup RCC_LL_EC_PLL_SPRE_SEL PLL Spread Spectrum Selection
825 * @{
826 */
827 #define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U /*!< PLL center spread spectrum selection */
828 #define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL /*!< PLL down spread spectrum selection */
829 /**
830 * @}
831 */
832
833 /** @defgroup RCC_LL_EC_PLLI2SQ PLLI2SQ division factor (PLLI2SQ)
834 * @{
835 */
836 #define LL_RCC_PLLI2SQ_DIV_2 RCC_PLLI2SCFGR_PLLI2SQ_1 /*!< PLLI2S division factor for PLLI2SQ output by 2 */
837 #define LL_RCC_PLLI2SQ_DIV_3 (RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 3 */
838 #define LL_RCC_PLLI2SQ_DIV_4 RCC_PLLI2SCFGR_PLLI2SQ_2 /*!< PLLI2S division factor for PLLI2SQ output by 4 */
839 #define LL_RCC_PLLI2SQ_DIV_5 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 5 */
840 #define LL_RCC_PLLI2SQ_DIV_6 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 6 */
841 #define LL_RCC_PLLI2SQ_DIV_7 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 7 */
842 #define LL_RCC_PLLI2SQ_DIV_8 RCC_PLLI2SCFGR_PLLI2SQ_3 /*!< PLLI2S division factor for PLLI2SQ output by 8 */
843 #define LL_RCC_PLLI2SQ_DIV_9 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 9 */
844 #define LL_RCC_PLLI2SQ_DIV_10 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 10 */
845 #define LL_RCC_PLLI2SQ_DIV_11 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 11 */
846 #define LL_RCC_PLLI2SQ_DIV_12 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2) /*!< PLLI2S division factor for PLLI2SQ output by 12 */
847 #define LL_RCC_PLLI2SQ_DIV_13 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 13 */
848 #define LL_RCC_PLLI2SQ_DIV_14 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 14 */
849 #define LL_RCC_PLLI2SQ_DIV_15 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 15 */
850 /**
851 * @}
852 */
853
854 /** @defgroup RCC_LL_EC_PLLI2SDIVQ PLLI2SDIVQ division factor (PLLI2SDIVQ)
855 * @{
856 */
857 #define LL_RCC_PLLI2SDIVQ_DIV_1 0x00000000U /*!< PLLI2S division factor for PLLI2SDIVQ output by 1 */
858 #define LL_RCC_PLLI2SDIVQ_DIV_2 RCC_DCKCFGR1_PLLI2SDIVQ_0 /*!< PLLI2S division factor for PLLI2SDIVQ output by 2 */
859 #define LL_RCC_PLLI2SDIVQ_DIV_3 RCC_DCKCFGR1_PLLI2SDIVQ_1 /*!< PLLI2S division factor for PLLI2SDIVQ output by 3 */
860 #define LL_RCC_PLLI2SDIVQ_DIV_4 (RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 4 */
861 #define LL_RCC_PLLI2SDIVQ_DIV_5 RCC_DCKCFGR1_PLLI2SDIVQ_2 /*!< PLLI2S division factor for PLLI2SDIVQ output by 5 */
862 #define LL_RCC_PLLI2SDIVQ_DIV_6 (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 6 */
863 #define LL_RCC_PLLI2SDIVQ_DIV_7 (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 7 */
864 #define LL_RCC_PLLI2SDIVQ_DIV_8 (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 8 */
865 #define LL_RCC_PLLI2SDIVQ_DIV_9 RCC_DCKCFGR1_PLLI2SDIVQ_3 /*!< PLLI2S division factor for PLLI2SDIVQ output by 9 */
866 #define LL_RCC_PLLI2SDIVQ_DIV_10 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 10 */
867 #define LL_RCC_PLLI2SDIVQ_DIV_11 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 11 */
868 #define LL_RCC_PLLI2SDIVQ_DIV_12 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 12 */
869 #define LL_RCC_PLLI2SDIVQ_DIV_13 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 13 */
870 #define LL_RCC_PLLI2SDIVQ_DIV_14 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 14 */
871 #define LL_RCC_PLLI2SDIVQ_DIV_15 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 15 */
872 #define LL_RCC_PLLI2SDIVQ_DIV_16 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 16 */
873 #define LL_RCC_PLLI2SDIVQ_DIV_17 RCC_DCKCFGR1_PLLI2SDIVQ_4 /*!< PLLI2S division factor for PLLI2SDIVQ output by 17 */
874 #define LL_RCC_PLLI2SDIVQ_DIV_18 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 18 */
875 #define LL_RCC_PLLI2SDIVQ_DIV_19 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 19 */
876 #define LL_RCC_PLLI2SDIVQ_DIV_20 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 20 */
877 #define LL_RCC_PLLI2SDIVQ_DIV_21 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 21 */
878 #define LL_RCC_PLLI2SDIVQ_DIV_22 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 22 */
879 #define LL_RCC_PLLI2SDIVQ_DIV_23 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 23 */
880 #define LL_RCC_PLLI2SDIVQ_DIV_24 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 24 */
881 #define LL_RCC_PLLI2SDIVQ_DIV_25 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3) /*!< PLLI2S division factor for PLLI2SDIVQ output by 25 */
882 #define LL_RCC_PLLI2SDIVQ_DIV_26 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 26 */
883 #define LL_RCC_PLLI2SDIVQ_DIV_27 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 27 */
884 #define LL_RCC_PLLI2SDIVQ_DIV_28 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 28 */
885 #define LL_RCC_PLLI2SDIVQ_DIV_29 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 29 */
886 #define LL_RCC_PLLI2SDIVQ_DIV_30 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 30 */
887 #define LL_RCC_PLLI2SDIVQ_DIV_31 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 31 */
888 #define LL_RCC_PLLI2SDIVQ_DIV_32 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 32 */
889 /**
890 * @}
891 */
892
893 /** @defgroup RCC_LL_EC_PLLI2SR PLLI2SR division factor (PLLI2SR)
894 * @{
895 */
896 #define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 /*!< PLLI2S division factor for PLLI2SR output by 2 */
897 #define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 3 */
898 #define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 /*!< PLLI2S division factor for PLLI2SR output by 4 */
899 #define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 5 */
900 #define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1) /*!< PLLI2S division factor for PLLI2SR output by 6 */
901 #define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 7 */
902 /**
903 * @}
904 */
905
906 #if defined(RCC_PLLI2SCFGR_PLLI2SP)
907 /** @defgroup RCC_LL_EC_PLLI2SP PLLI2SP division factor (PLLI2SP)
908 * @{
909 */
910 #define LL_RCC_PLLI2SP_DIV_2 0x00000000U /*!< PLLI2S division factor for PLLI2SP output by 2 */
911 #define LL_RCC_PLLI2SP_DIV_4 RCC_PLLI2SCFGR_PLLI2SP_0 /*!< PLLI2S division factor for PLLI2SP output by 4 */
912 #define LL_RCC_PLLI2SP_DIV_6 RCC_PLLI2SCFGR_PLLI2SP_1 /*!< PLLI2S division factor for PLLI2SP output by 6 */
913 #define LL_RCC_PLLI2SP_DIV_8 (RCC_PLLI2SCFGR_PLLI2SP_1 | RCC_PLLI2SCFGR_PLLI2SP_0) /*!< PLLI2S division factor for PLLI2SP output by 8 */
914 /**
915 * @}
916 */
917 #endif /* RCC_PLLI2SCFGR_PLLI2SP */
918
919 /** @defgroup RCC_LL_EC_PLLSAIQ PLLSAIQ division factor (PLLSAIQ)
920 * @{
921 */
922 #define LL_RCC_PLLSAIQ_DIV_2 RCC_PLLSAICFGR_PLLSAIQ_1 /*!< PLLSAI division factor for PLLSAIQ output by 2 */
923 #define LL_RCC_PLLSAIQ_DIV_3 (RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 3 */
924 #define LL_RCC_PLLSAIQ_DIV_4 RCC_PLLSAICFGR_PLLSAIQ_2 /*!< PLLSAI division factor for PLLSAIQ output by 4 */
925 #define LL_RCC_PLLSAIQ_DIV_5 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 5 */
926 #define LL_RCC_PLLSAIQ_DIV_6 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 6 */
927 #define LL_RCC_PLLSAIQ_DIV_7 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 7 */
928 #define LL_RCC_PLLSAIQ_DIV_8 RCC_PLLSAICFGR_PLLSAIQ_3 /*!< PLLSAI division factor for PLLSAIQ output by 8 */
929 #define LL_RCC_PLLSAIQ_DIV_9 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 9 */
930 #define LL_RCC_PLLSAIQ_DIV_10 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 10 */
931 #define LL_RCC_PLLSAIQ_DIV_11 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 11 */
932 #define LL_RCC_PLLSAIQ_DIV_12 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2) /*!< PLLSAI division factor for PLLSAIQ output by 12 */
933 #define LL_RCC_PLLSAIQ_DIV_13 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 13 */
934 #define LL_RCC_PLLSAIQ_DIV_14 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 14 */
935 #define LL_RCC_PLLSAIQ_DIV_15 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 15 */
936 /**
937 * @}
938 */
939
940 /** @defgroup RCC_LL_EC_PLLSAIDIVQ PLLSAIDIVQ division factor (PLLSAIDIVQ)
941 * @{
942 */
943 #define LL_RCC_PLLSAIDIVQ_DIV_1 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVQ output by 1 */
944 #define LL_RCC_PLLSAIDIVQ_DIV_2 RCC_DCKCFGR1_PLLSAIDIVQ_0 /*!< PLLSAI division factor for PLLSAIDIVQ output by 2 */
945 #define LL_RCC_PLLSAIDIVQ_DIV_3 RCC_DCKCFGR1_PLLSAIDIVQ_1 /*!< PLLSAI division factor for PLLSAIDIVQ output by 3 */
946 #define LL_RCC_PLLSAIDIVQ_DIV_4 (RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 4 */
947 #define LL_RCC_PLLSAIDIVQ_DIV_5 RCC_DCKCFGR1_PLLSAIDIVQ_2 /*!< PLLSAI division factor for PLLSAIDIVQ output by 5 */
948 #define LL_RCC_PLLSAIDIVQ_DIV_6 (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 6 */
949 #define LL_RCC_PLLSAIDIVQ_DIV_7 (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 7 */
950 #define LL_RCC_PLLSAIDIVQ_DIV_8 (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 8 */
951 #define LL_RCC_PLLSAIDIVQ_DIV_9 RCC_DCKCFGR1_PLLSAIDIVQ_3 /*!< PLLSAI division factor for PLLSAIDIVQ output by 9 */
952 #define LL_RCC_PLLSAIDIVQ_DIV_10 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 10 */
953 #define LL_RCC_PLLSAIDIVQ_DIV_11 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 11 */
954 #define LL_RCC_PLLSAIDIVQ_DIV_12 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 12 */
955 #define LL_RCC_PLLSAIDIVQ_DIV_13 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 13 */
956 #define LL_RCC_PLLSAIDIVQ_DIV_14 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 14 */
957 #define LL_RCC_PLLSAIDIVQ_DIV_15 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 15 */
958 #define LL_RCC_PLLSAIDIVQ_DIV_16 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 16 */
959 #define LL_RCC_PLLSAIDIVQ_DIV_17 RCC_DCKCFGR1_PLLSAIDIVQ_4 /*!< PLLSAI division factor for PLLSAIDIVQ output by 17 */
960 #define LL_RCC_PLLSAIDIVQ_DIV_18 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 18 */
961 #define LL_RCC_PLLSAIDIVQ_DIV_19 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 19 */
962 #define LL_RCC_PLLSAIDIVQ_DIV_20 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 20 */
963 #define LL_RCC_PLLSAIDIVQ_DIV_21 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 21 */
964 #define LL_RCC_PLLSAIDIVQ_DIV_22 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 22 */
965 #define LL_RCC_PLLSAIDIVQ_DIV_23 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 23 */
966 #define LL_RCC_PLLSAIDIVQ_DIV_24 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 24 */
967 #define LL_RCC_PLLSAIDIVQ_DIV_25 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3) /*!< PLLSAI division factor for PLLSAIDIVQ output by 25 */
968 #define LL_RCC_PLLSAIDIVQ_DIV_26 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 26 */
969 #define LL_RCC_PLLSAIDIVQ_DIV_27 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 27 */
970 #define LL_RCC_PLLSAIDIVQ_DIV_28 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 28 */
971 #define LL_RCC_PLLSAIDIVQ_DIV_29 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 29 */
972 #define LL_RCC_PLLSAIDIVQ_DIV_30 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 30 */
973 #define LL_RCC_PLLSAIDIVQ_DIV_31 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 31 */
974 #define LL_RCC_PLLSAIDIVQ_DIV_32 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 32 */
975 /**
976 * @}
977 */
978
979 #if defined(RCC_PLLSAICFGR_PLLSAIR)
980 /** @defgroup RCC_LL_EC_PLLSAIR PLLSAIR division factor (PLLSAIR)
981 * @{
982 */
983 #define LL_RCC_PLLSAIR_DIV_2 RCC_PLLSAICFGR_PLLSAIR_1 /*!< PLLSAI division factor for PLLSAIR output by 2 */
984 #define LL_RCC_PLLSAIR_DIV_3 (RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 3 */
985 #define LL_RCC_PLLSAIR_DIV_4 RCC_PLLSAICFGR_PLLSAIR_2 /*!< PLLSAI division factor for PLLSAIR output by 4 */
986 #define LL_RCC_PLLSAIR_DIV_5 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 5 */
987 #define LL_RCC_PLLSAIR_DIV_6 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1) /*!< PLLSAI division factor for PLLSAIR output by 6 */
988 #define LL_RCC_PLLSAIR_DIV_7 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 7 */
989 /**
990 * @}
991 */
992 #endif /* RCC_PLLSAICFGR_PLLSAIR */
993
994 #if defined(RCC_DCKCFGR1_PLLSAIDIVR)
995 /** @defgroup RCC_LL_EC_PLLSAIDIVR PLLSAIDIVR division factor (PLLSAIDIVR)
996 * @{
997 */
998 #define LL_RCC_PLLSAIDIVR_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVR output by 2 */
999 #define LL_RCC_PLLSAIDIVR_DIV_4 RCC_DCKCFGR1_PLLSAIDIVR_0 /*!< PLLSAI division factor for PLLSAIDIVR output by 4 */
1000 #define LL_RCC_PLLSAIDIVR_DIV_8 RCC_DCKCFGR1_PLLSAIDIVR_1 /*!< PLLSAI division factor for PLLSAIDIVR output by 8 */
1001 #define LL_RCC_PLLSAIDIVR_DIV_16 (RCC_DCKCFGR1_PLLSAIDIVR_1 | RCC_DCKCFGR1_PLLSAIDIVR_0) /*!< PLLSAI division factor for PLLSAIDIVR output by 16 */
1002 /**
1003 * @}
1004 */
1005 #endif /* RCC_DCKCFGR1_PLLSAIDIVR */
1006
1007 /** @defgroup RCC_LL_EC_PLLSAIP PLLSAIP division factor (PLLSAIP)
1008 * @{
1009 */
1010 #define LL_RCC_PLLSAIP_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIP output by 2 */
1011 #define LL_RCC_PLLSAIP_DIV_4 RCC_PLLSAICFGR_PLLSAIP_0 /*!< PLLSAI division factor for PLLSAIP output by 4 */
1012 #define LL_RCC_PLLSAIP_DIV_6 RCC_PLLSAICFGR_PLLSAIP_1 /*!< PLLSAI division factor for PLLSAIP output by 6 */
1013 #define LL_RCC_PLLSAIP_DIV_8 (RCC_PLLSAICFGR_PLLSAIP_1 | RCC_PLLSAICFGR_PLLSAIP_0) /*!< PLLSAI division factor for PLLSAIP output by 8 */
1014 /**
1015 * @}
1016 */
1017
1018 /**
1019 * @}
1020 */
1021
1022 /* Exported macro ------------------------------------------------------------*/
1023 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
1024 * @{
1025 */
1026
1027 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
1028 * @{
1029 */
1030
1031 /**
1032 * @brief Write a value in RCC register
1033 * @param __REG__ Register to be written
1034 * @param __VALUE__ Value to be written in the register
1035 * @retval None
1036 */
1037 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
1038
1039 /**
1040 * @brief Read a value in RCC register
1041 * @param __REG__ Register to be read
1042 * @retval Register value
1043 */
1044 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
1045 /**
1046 * @}
1047 */
1048
1049 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
1050 * @{
1051 */
1052
1053 /**
1054 * @brief Helper macro to calculate the PLLCLK frequency on system domain
1055 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1056 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
1057 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1058 * @param __PLLM__ This parameter can be one of the following values:
1059 * @arg @ref LL_RCC_PLLM_DIV_2
1060 * @arg @ref LL_RCC_PLLM_DIV_3
1061 * @arg @ref LL_RCC_PLLM_DIV_4
1062 * @arg @ref LL_RCC_PLLM_DIV_5
1063 * @arg @ref LL_RCC_PLLM_DIV_6
1064 * @arg @ref LL_RCC_PLLM_DIV_7
1065 * @arg @ref LL_RCC_PLLM_DIV_8
1066 * @arg @ref LL_RCC_PLLM_DIV_9
1067 * @arg @ref LL_RCC_PLLM_DIV_10
1068 * @arg @ref LL_RCC_PLLM_DIV_11
1069 * @arg @ref LL_RCC_PLLM_DIV_12
1070 * @arg @ref LL_RCC_PLLM_DIV_13
1071 * @arg @ref LL_RCC_PLLM_DIV_14
1072 * @arg @ref LL_RCC_PLLM_DIV_15
1073 * @arg @ref LL_RCC_PLLM_DIV_16
1074 * @arg @ref LL_RCC_PLLM_DIV_17
1075 * @arg @ref LL_RCC_PLLM_DIV_18
1076 * @arg @ref LL_RCC_PLLM_DIV_19
1077 * @arg @ref LL_RCC_PLLM_DIV_20
1078 * @arg @ref LL_RCC_PLLM_DIV_21
1079 * @arg @ref LL_RCC_PLLM_DIV_22
1080 * @arg @ref LL_RCC_PLLM_DIV_23
1081 * @arg @ref LL_RCC_PLLM_DIV_24
1082 * @arg @ref LL_RCC_PLLM_DIV_25
1083 * @arg @ref LL_RCC_PLLM_DIV_26
1084 * @arg @ref LL_RCC_PLLM_DIV_27
1085 * @arg @ref LL_RCC_PLLM_DIV_28
1086 * @arg @ref LL_RCC_PLLM_DIV_29
1087 * @arg @ref LL_RCC_PLLM_DIV_30
1088 * @arg @ref LL_RCC_PLLM_DIV_31
1089 * @arg @ref LL_RCC_PLLM_DIV_32
1090 * @arg @ref LL_RCC_PLLM_DIV_33
1091 * @arg @ref LL_RCC_PLLM_DIV_34
1092 * @arg @ref LL_RCC_PLLM_DIV_35
1093 * @arg @ref LL_RCC_PLLM_DIV_36
1094 * @arg @ref LL_RCC_PLLM_DIV_37
1095 * @arg @ref LL_RCC_PLLM_DIV_38
1096 * @arg @ref LL_RCC_PLLM_DIV_39
1097 * @arg @ref LL_RCC_PLLM_DIV_40
1098 * @arg @ref LL_RCC_PLLM_DIV_41
1099 * @arg @ref LL_RCC_PLLM_DIV_42
1100 * @arg @ref LL_RCC_PLLM_DIV_43
1101 * @arg @ref LL_RCC_PLLM_DIV_44
1102 * @arg @ref LL_RCC_PLLM_DIV_45
1103 * @arg @ref LL_RCC_PLLM_DIV_46
1104 * @arg @ref LL_RCC_PLLM_DIV_47
1105 * @arg @ref LL_RCC_PLLM_DIV_48
1106 * @arg @ref LL_RCC_PLLM_DIV_49
1107 * @arg @ref LL_RCC_PLLM_DIV_50
1108 * @arg @ref LL_RCC_PLLM_DIV_51
1109 * @arg @ref LL_RCC_PLLM_DIV_52
1110 * @arg @ref LL_RCC_PLLM_DIV_53
1111 * @arg @ref LL_RCC_PLLM_DIV_54
1112 * @arg @ref LL_RCC_PLLM_DIV_55
1113 * @arg @ref LL_RCC_PLLM_DIV_56
1114 * @arg @ref LL_RCC_PLLM_DIV_57
1115 * @arg @ref LL_RCC_PLLM_DIV_58
1116 * @arg @ref LL_RCC_PLLM_DIV_59
1117 * @arg @ref LL_RCC_PLLM_DIV_60
1118 * @arg @ref LL_RCC_PLLM_DIV_61
1119 * @arg @ref LL_RCC_PLLM_DIV_62
1120 * @arg @ref LL_RCC_PLLM_DIV_63
1121 * @param __PLLN__ Between 50 and 432
1122 * @param __PLLP__ This parameter can be one of the following values:
1123 * @arg @ref LL_RCC_PLLP_DIV_2
1124 * @arg @ref LL_RCC_PLLP_DIV_4
1125 * @arg @ref LL_RCC_PLLP_DIV_6
1126 * @arg @ref LL_RCC_PLLP_DIV_8
1127 * @retval PLL clock frequency (in Hz)
1128 */
1129 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1130 ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U))
1131
1132 /**
1133 * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
1134 * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1135 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
1136 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1137 * @param __PLLM__ This parameter can be one of the following values:
1138 * @arg @ref LL_RCC_PLLM_DIV_2
1139 * @arg @ref LL_RCC_PLLM_DIV_3
1140 * @arg @ref LL_RCC_PLLM_DIV_4
1141 * @arg @ref LL_RCC_PLLM_DIV_5
1142 * @arg @ref LL_RCC_PLLM_DIV_6
1143 * @arg @ref LL_RCC_PLLM_DIV_7
1144 * @arg @ref LL_RCC_PLLM_DIV_8
1145 * @arg @ref LL_RCC_PLLM_DIV_9
1146 * @arg @ref LL_RCC_PLLM_DIV_10
1147 * @arg @ref LL_RCC_PLLM_DIV_11
1148 * @arg @ref LL_RCC_PLLM_DIV_12
1149 * @arg @ref LL_RCC_PLLM_DIV_13
1150 * @arg @ref LL_RCC_PLLM_DIV_14
1151 * @arg @ref LL_RCC_PLLM_DIV_15
1152 * @arg @ref LL_RCC_PLLM_DIV_16
1153 * @arg @ref LL_RCC_PLLM_DIV_17
1154 * @arg @ref LL_RCC_PLLM_DIV_18
1155 * @arg @ref LL_RCC_PLLM_DIV_19
1156 * @arg @ref LL_RCC_PLLM_DIV_20
1157 * @arg @ref LL_RCC_PLLM_DIV_21
1158 * @arg @ref LL_RCC_PLLM_DIV_22
1159 * @arg @ref LL_RCC_PLLM_DIV_23
1160 * @arg @ref LL_RCC_PLLM_DIV_24
1161 * @arg @ref LL_RCC_PLLM_DIV_25
1162 * @arg @ref LL_RCC_PLLM_DIV_26
1163 * @arg @ref LL_RCC_PLLM_DIV_27
1164 * @arg @ref LL_RCC_PLLM_DIV_28
1165 * @arg @ref LL_RCC_PLLM_DIV_29
1166 * @arg @ref LL_RCC_PLLM_DIV_30
1167 * @arg @ref LL_RCC_PLLM_DIV_31
1168 * @arg @ref LL_RCC_PLLM_DIV_32
1169 * @arg @ref LL_RCC_PLLM_DIV_33
1170 * @arg @ref LL_RCC_PLLM_DIV_34
1171 * @arg @ref LL_RCC_PLLM_DIV_35
1172 * @arg @ref LL_RCC_PLLM_DIV_36
1173 * @arg @ref LL_RCC_PLLM_DIV_37
1174 * @arg @ref LL_RCC_PLLM_DIV_38
1175 * @arg @ref LL_RCC_PLLM_DIV_39
1176 * @arg @ref LL_RCC_PLLM_DIV_40
1177 * @arg @ref LL_RCC_PLLM_DIV_41
1178 * @arg @ref LL_RCC_PLLM_DIV_42
1179 * @arg @ref LL_RCC_PLLM_DIV_43
1180 * @arg @ref LL_RCC_PLLM_DIV_44
1181 * @arg @ref LL_RCC_PLLM_DIV_45
1182 * @arg @ref LL_RCC_PLLM_DIV_46
1183 * @arg @ref LL_RCC_PLLM_DIV_47
1184 * @arg @ref LL_RCC_PLLM_DIV_48
1185 * @arg @ref LL_RCC_PLLM_DIV_49
1186 * @arg @ref LL_RCC_PLLM_DIV_50
1187 * @arg @ref LL_RCC_PLLM_DIV_51
1188 * @arg @ref LL_RCC_PLLM_DIV_52
1189 * @arg @ref LL_RCC_PLLM_DIV_53
1190 * @arg @ref LL_RCC_PLLM_DIV_54
1191 * @arg @ref LL_RCC_PLLM_DIV_55
1192 * @arg @ref LL_RCC_PLLM_DIV_56
1193 * @arg @ref LL_RCC_PLLM_DIV_57
1194 * @arg @ref LL_RCC_PLLM_DIV_58
1195 * @arg @ref LL_RCC_PLLM_DIV_59
1196 * @arg @ref LL_RCC_PLLM_DIV_60
1197 * @arg @ref LL_RCC_PLLM_DIV_61
1198 * @arg @ref LL_RCC_PLLM_DIV_62
1199 * @arg @ref LL_RCC_PLLM_DIV_63
1200 * @param __PLLN__ Between 50 and 432
1201 * @param __PLLQ__ This parameter can be one of the following values:
1202 * @arg @ref LL_RCC_PLLQ_DIV_2
1203 * @arg @ref LL_RCC_PLLQ_DIV_3
1204 * @arg @ref LL_RCC_PLLQ_DIV_4
1205 * @arg @ref LL_RCC_PLLQ_DIV_5
1206 * @arg @ref LL_RCC_PLLQ_DIV_6
1207 * @arg @ref LL_RCC_PLLQ_DIV_7
1208 * @arg @ref LL_RCC_PLLQ_DIV_8
1209 * @arg @ref LL_RCC_PLLQ_DIV_9
1210 * @arg @ref LL_RCC_PLLQ_DIV_10
1211 * @arg @ref LL_RCC_PLLQ_DIV_11
1212 * @arg @ref LL_RCC_PLLQ_DIV_12
1213 * @arg @ref LL_RCC_PLLQ_DIV_13
1214 * @arg @ref LL_RCC_PLLQ_DIV_14
1215 * @arg @ref LL_RCC_PLLQ_DIV_15
1216 * @retval PLL clock frequency (in Hz)
1217 */
1218 #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1219 ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos ))
1220
1221 #if defined(DSI)
1222 /**
1223 * @brief Helper macro to calculate the PLLCLK frequency used on DSI
1224 * @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
1225 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
1226 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1227 * @param __PLLM__ This parameter can be one of the following values:
1228 * @arg @ref LL_RCC_PLLM_DIV_2
1229 * @arg @ref LL_RCC_PLLM_DIV_3
1230 * @arg @ref LL_RCC_PLLM_DIV_4
1231 * @arg @ref LL_RCC_PLLM_DIV_5
1232 * @arg @ref LL_RCC_PLLM_DIV_6
1233 * @arg @ref LL_RCC_PLLM_DIV_7
1234 * @arg @ref LL_RCC_PLLM_DIV_8
1235 * @arg @ref LL_RCC_PLLM_DIV_9
1236 * @arg @ref LL_RCC_PLLM_DIV_10
1237 * @arg @ref LL_RCC_PLLM_DIV_11
1238 * @arg @ref LL_RCC_PLLM_DIV_12
1239 * @arg @ref LL_RCC_PLLM_DIV_13
1240 * @arg @ref LL_RCC_PLLM_DIV_14
1241 * @arg @ref LL_RCC_PLLM_DIV_15
1242 * @arg @ref LL_RCC_PLLM_DIV_16
1243 * @arg @ref LL_RCC_PLLM_DIV_17
1244 * @arg @ref LL_RCC_PLLM_DIV_18
1245 * @arg @ref LL_RCC_PLLM_DIV_19
1246 * @arg @ref LL_RCC_PLLM_DIV_20
1247 * @arg @ref LL_RCC_PLLM_DIV_21
1248 * @arg @ref LL_RCC_PLLM_DIV_22
1249 * @arg @ref LL_RCC_PLLM_DIV_23
1250 * @arg @ref LL_RCC_PLLM_DIV_24
1251 * @arg @ref LL_RCC_PLLM_DIV_25
1252 * @arg @ref LL_RCC_PLLM_DIV_26
1253 * @arg @ref LL_RCC_PLLM_DIV_27
1254 * @arg @ref LL_RCC_PLLM_DIV_28
1255 * @arg @ref LL_RCC_PLLM_DIV_29
1256 * @arg @ref LL_RCC_PLLM_DIV_30
1257 * @arg @ref LL_RCC_PLLM_DIV_31
1258 * @arg @ref LL_RCC_PLLM_DIV_32
1259 * @arg @ref LL_RCC_PLLM_DIV_33
1260 * @arg @ref LL_RCC_PLLM_DIV_34
1261 * @arg @ref LL_RCC_PLLM_DIV_35
1262 * @arg @ref LL_RCC_PLLM_DIV_36
1263 * @arg @ref LL_RCC_PLLM_DIV_37
1264 * @arg @ref LL_RCC_PLLM_DIV_38
1265 * @arg @ref LL_RCC_PLLM_DIV_39
1266 * @arg @ref LL_RCC_PLLM_DIV_40
1267 * @arg @ref LL_RCC_PLLM_DIV_41
1268 * @arg @ref LL_RCC_PLLM_DIV_42
1269 * @arg @ref LL_RCC_PLLM_DIV_43
1270 * @arg @ref LL_RCC_PLLM_DIV_44
1271 * @arg @ref LL_RCC_PLLM_DIV_45
1272 * @arg @ref LL_RCC_PLLM_DIV_46
1273 * @arg @ref LL_RCC_PLLM_DIV_47
1274 * @arg @ref LL_RCC_PLLM_DIV_48
1275 * @arg @ref LL_RCC_PLLM_DIV_49
1276 * @arg @ref LL_RCC_PLLM_DIV_50
1277 * @arg @ref LL_RCC_PLLM_DIV_51
1278 * @arg @ref LL_RCC_PLLM_DIV_52
1279 * @arg @ref LL_RCC_PLLM_DIV_53
1280 * @arg @ref LL_RCC_PLLM_DIV_54
1281 * @arg @ref LL_RCC_PLLM_DIV_55
1282 * @arg @ref LL_RCC_PLLM_DIV_56
1283 * @arg @ref LL_RCC_PLLM_DIV_57
1284 * @arg @ref LL_RCC_PLLM_DIV_58
1285 * @arg @ref LL_RCC_PLLM_DIV_59
1286 * @arg @ref LL_RCC_PLLM_DIV_60
1287 * @arg @ref LL_RCC_PLLM_DIV_61
1288 * @arg @ref LL_RCC_PLLM_DIV_62
1289 * @arg @ref LL_RCC_PLLM_DIV_63
1290 * @param __PLLN__ Between 50 and 432
1291 * @param __PLLR__ This parameter can be one of the following values:
1292 * @arg @ref LL_RCC_PLLR_DIV_2
1293 * @arg @ref LL_RCC_PLLR_DIV_3
1294 * @arg @ref LL_RCC_PLLR_DIV_4
1295 * @arg @ref LL_RCC_PLLR_DIV_5
1296 * @arg @ref LL_RCC_PLLR_DIV_6
1297 * @arg @ref LL_RCC_PLLR_DIV_7
1298 * @retval PLL clock frequency (in Hz)
1299 */
1300 #define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1301 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
1302 #endif /* DSI */
1303
1304 /**
1305 * @brief Helper macro to calculate the PLLSAI frequency used for SAI1 and SAI2 domains
1306 * @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1307 * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ ());
1308 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1309 * @param __PLLM__ This parameter can be one of the following values:
1310 * @arg @ref LL_RCC_PLLM_DIV_2
1311 * @arg @ref LL_RCC_PLLM_DIV_3
1312 * @arg @ref LL_RCC_PLLM_DIV_4
1313 * @arg @ref LL_RCC_PLLM_DIV_5
1314 * @arg @ref LL_RCC_PLLM_DIV_6
1315 * @arg @ref LL_RCC_PLLM_DIV_7
1316 * @arg @ref LL_RCC_PLLM_DIV_8
1317 * @arg @ref LL_RCC_PLLM_DIV_9
1318 * @arg @ref LL_RCC_PLLM_DIV_10
1319 * @arg @ref LL_RCC_PLLM_DIV_11
1320 * @arg @ref LL_RCC_PLLM_DIV_12
1321 * @arg @ref LL_RCC_PLLM_DIV_13
1322 * @arg @ref LL_RCC_PLLM_DIV_14
1323 * @arg @ref LL_RCC_PLLM_DIV_15
1324 * @arg @ref LL_RCC_PLLM_DIV_16
1325 * @arg @ref LL_RCC_PLLM_DIV_17
1326 * @arg @ref LL_RCC_PLLM_DIV_18
1327 * @arg @ref LL_RCC_PLLM_DIV_19
1328 * @arg @ref LL_RCC_PLLM_DIV_20
1329 * @arg @ref LL_RCC_PLLM_DIV_21
1330 * @arg @ref LL_RCC_PLLM_DIV_22
1331 * @arg @ref LL_RCC_PLLM_DIV_23
1332 * @arg @ref LL_RCC_PLLM_DIV_24
1333 * @arg @ref LL_RCC_PLLM_DIV_25
1334 * @arg @ref LL_RCC_PLLM_DIV_26
1335 * @arg @ref LL_RCC_PLLM_DIV_27
1336 * @arg @ref LL_RCC_PLLM_DIV_28
1337 * @arg @ref LL_RCC_PLLM_DIV_29
1338 * @arg @ref LL_RCC_PLLM_DIV_30
1339 * @arg @ref LL_RCC_PLLM_DIV_31
1340 * @arg @ref LL_RCC_PLLM_DIV_32
1341 * @arg @ref LL_RCC_PLLM_DIV_33
1342 * @arg @ref LL_RCC_PLLM_DIV_34
1343 * @arg @ref LL_RCC_PLLM_DIV_35
1344 * @arg @ref LL_RCC_PLLM_DIV_36
1345 * @arg @ref LL_RCC_PLLM_DIV_37
1346 * @arg @ref LL_RCC_PLLM_DIV_38
1347 * @arg @ref LL_RCC_PLLM_DIV_39
1348 * @arg @ref LL_RCC_PLLM_DIV_40
1349 * @arg @ref LL_RCC_PLLM_DIV_41
1350 * @arg @ref LL_RCC_PLLM_DIV_42
1351 * @arg @ref LL_RCC_PLLM_DIV_43
1352 * @arg @ref LL_RCC_PLLM_DIV_44
1353 * @arg @ref LL_RCC_PLLM_DIV_45
1354 * @arg @ref LL_RCC_PLLM_DIV_46
1355 * @arg @ref LL_RCC_PLLM_DIV_47
1356 * @arg @ref LL_RCC_PLLM_DIV_48
1357 * @arg @ref LL_RCC_PLLM_DIV_49
1358 * @arg @ref LL_RCC_PLLM_DIV_50
1359 * @arg @ref LL_RCC_PLLM_DIV_51
1360 * @arg @ref LL_RCC_PLLM_DIV_52
1361 * @arg @ref LL_RCC_PLLM_DIV_53
1362 * @arg @ref LL_RCC_PLLM_DIV_54
1363 * @arg @ref LL_RCC_PLLM_DIV_55
1364 * @arg @ref LL_RCC_PLLM_DIV_56
1365 * @arg @ref LL_RCC_PLLM_DIV_57
1366 * @arg @ref LL_RCC_PLLM_DIV_58
1367 * @arg @ref LL_RCC_PLLM_DIV_59
1368 * @arg @ref LL_RCC_PLLM_DIV_60
1369 * @arg @ref LL_RCC_PLLM_DIV_61
1370 * @arg @ref LL_RCC_PLLM_DIV_62
1371 * @arg @ref LL_RCC_PLLM_DIV_63
1372 * @param __PLLSAIN__ Between 50 and 432
1373 * @param __PLLSAIQ__ This parameter can be one of the following values:
1374 * @arg @ref LL_RCC_PLLSAIQ_DIV_2
1375 * @arg @ref LL_RCC_PLLSAIQ_DIV_3
1376 * @arg @ref LL_RCC_PLLSAIQ_DIV_4
1377 * @arg @ref LL_RCC_PLLSAIQ_DIV_5
1378 * @arg @ref LL_RCC_PLLSAIQ_DIV_6
1379 * @arg @ref LL_RCC_PLLSAIQ_DIV_7
1380 * @arg @ref LL_RCC_PLLSAIQ_DIV_8
1381 * @arg @ref LL_RCC_PLLSAIQ_DIV_9
1382 * @arg @ref LL_RCC_PLLSAIQ_DIV_10
1383 * @arg @ref LL_RCC_PLLSAIQ_DIV_11
1384 * @arg @ref LL_RCC_PLLSAIQ_DIV_12
1385 * @arg @ref LL_RCC_PLLSAIQ_DIV_13
1386 * @arg @ref LL_RCC_PLLSAIQ_DIV_14
1387 * @arg @ref LL_RCC_PLLSAIQ_DIV_15
1388 * @param __PLLSAIDIVQ__ This parameter can be one of the following values:
1389 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
1390 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
1391 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
1392 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
1393 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
1394 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
1395 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
1396 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
1397 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
1398 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
1399 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
1400 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
1401 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
1402 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
1403 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
1404 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
1405 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
1406 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
1407 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
1408 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
1409 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
1410 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
1411 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
1412 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
1413 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
1414 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
1415 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
1416 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
1417 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
1418 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
1419 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
1420 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
1421 * @retval PLLSAI clock frequency (in Hz)
1422 */
1423 #define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
1424 (((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCFGR1_PLLSAIDIVQ_Pos) + 1U)))
1425
1426 /**
1427 * @brief Helper macro to calculate the PLLSAI frequency used on 48Mhz domain
1428 * @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1429 * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ());
1430 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1431 * @param __PLLM__ This parameter can be one of the following values:
1432 * @arg @ref LL_RCC_PLLM_DIV_2
1433 * @arg @ref LL_RCC_PLLM_DIV_3
1434 * @arg @ref LL_RCC_PLLM_DIV_4
1435 * @arg @ref LL_RCC_PLLM_DIV_5
1436 * @arg @ref LL_RCC_PLLM_DIV_6
1437 * @arg @ref LL_RCC_PLLM_DIV_7
1438 * @arg @ref LL_RCC_PLLM_DIV_8
1439 * @arg @ref LL_RCC_PLLM_DIV_9
1440 * @arg @ref LL_RCC_PLLM_DIV_10
1441 * @arg @ref LL_RCC_PLLM_DIV_11
1442 * @arg @ref LL_RCC_PLLM_DIV_12
1443 * @arg @ref LL_RCC_PLLM_DIV_13
1444 * @arg @ref LL_RCC_PLLM_DIV_14
1445 * @arg @ref LL_RCC_PLLM_DIV_15
1446 * @arg @ref LL_RCC_PLLM_DIV_16
1447 * @arg @ref LL_RCC_PLLM_DIV_17
1448 * @arg @ref LL_RCC_PLLM_DIV_18
1449 * @arg @ref LL_RCC_PLLM_DIV_19
1450 * @arg @ref LL_RCC_PLLM_DIV_20
1451 * @arg @ref LL_RCC_PLLM_DIV_21
1452 * @arg @ref LL_RCC_PLLM_DIV_22
1453 * @arg @ref LL_RCC_PLLM_DIV_23
1454 * @arg @ref LL_RCC_PLLM_DIV_24
1455 * @arg @ref LL_RCC_PLLM_DIV_25
1456 * @arg @ref LL_RCC_PLLM_DIV_26
1457 * @arg @ref LL_RCC_PLLM_DIV_27
1458 * @arg @ref LL_RCC_PLLM_DIV_28
1459 * @arg @ref LL_RCC_PLLM_DIV_29
1460 * @arg @ref LL_RCC_PLLM_DIV_30
1461 * @arg @ref LL_RCC_PLLM_DIV_31
1462 * @arg @ref LL_RCC_PLLM_DIV_32
1463 * @arg @ref LL_RCC_PLLM_DIV_33
1464 * @arg @ref LL_RCC_PLLM_DIV_34
1465 * @arg @ref LL_RCC_PLLM_DIV_35
1466 * @arg @ref LL_RCC_PLLM_DIV_36
1467 * @arg @ref LL_RCC_PLLM_DIV_37
1468 * @arg @ref LL_RCC_PLLM_DIV_38
1469 * @arg @ref LL_RCC_PLLM_DIV_39
1470 * @arg @ref LL_RCC_PLLM_DIV_40
1471 * @arg @ref LL_RCC_PLLM_DIV_41
1472 * @arg @ref LL_RCC_PLLM_DIV_42
1473 * @arg @ref LL_RCC_PLLM_DIV_43
1474 * @arg @ref LL_RCC_PLLM_DIV_44
1475 * @arg @ref LL_RCC_PLLM_DIV_45
1476 * @arg @ref LL_RCC_PLLM_DIV_46
1477 * @arg @ref LL_RCC_PLLM_DIV_47
1478 * @arg @ref LL_RCC_PLLM_DIV_48
1479 * @arg @ref LL_RCC_PLLM_DIV_49
1480 * @arg @ref LL_RCC_PLLM_DIV_50
1481 * @arg @ref LL_RCC_PLLM_DIV_51
1482 * @arg @ref LL_RCC_PLLM_DIV_52
1483 * @arg @ref LL_RCC_PLLM_DIV_53
1484 * @arg @ref LL_RCC_PLLM_DIV_54
1485 * @arg @ref LL_RCC_PLLM_DIV_55
1486 * @arg @ref LL_RCC_PLLM_DIV_56
1487 * @arg @ref LL_RCC_PLLM_DIV_57
1488 * @arg @ref LL_RCC_PLLM_DIV_58
1489 * @arg @ref LL_RCC_PLLM_DIV_59
1490 * @arg @ref LL_RCC_PLLM_DIV_60
1491 * @arg @ref LL_RCC_PLLM_DIV_61
1492 * @arg @ref LL_RCC_PLLM_DIV_62
1493 * @arg @ref LL_RCC_PLLM_DIV_63
1494 * @param __PLLSAIN__ Between 50 and 432
1495 * @param __PLLSAIP__ This parameter can be one of the following values:
1496 * @arg @ref LL_RCC_PLLSAIP_DIV_2
1497 * @arg @ref LL_RCC_PLLSAIP_DIV_4
1498 * @arg @ref LL_RCC_PLLSAIP_DIV_6
1499 * @arg @ref LL_RCC_PLLSAIP_DIV_8
1500 * @retval PLLSAI clock frequency (in Hz)
1501 */
1502 #define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
1503 ((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U ) * 2U))
1504
1505 #if defined(LTDC)
1506 /**
1507 * @brief Helper macro to calculate the PLLSAI frequency used for LTDC domain
1508 * @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1509 * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR ());
1510 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1511 * @param __PLLM__ This parameter can be one of the following values:
1512 * @arg @ref LL_RCC_PLLM_DIV_2
1513 * @arg @ref LL_RCC_PLLM_DIV_3
1514 * @arg @ref LL_RCC_PLLM_DIV_4
1515 * @arg @ref LL_RCC_PLLM_DIV_5
1516 * @arg @ref LL_RCC_PLLM_DIV_6
1517 * @arg @ref LL_RCC_PLLM_DIV_7
1518 * @arg @ref LL_RCC_PLLM_DIV_8
1519 * @arg @ref LL_RCC_PLLM_DIV_9
1520 * @arg @ref LL_RCC_PLLM_DIV_10
1521 * @arg @ref LL_RCC_PLLM_DIV_11
1522 * @arg @ref LL_RCC_PLLM_DIV_12
1523 * @arg @ref LL_RCC_PLLM_DIV_13
1524 * @arg @ref LL_RCC_PLLM_DIV_14
1525 * @arg @ref LL_RCC_PLLM_DIV_15
1526 * @arg @ref LL_RCC_PLLM_DIV_16
1527 * @arg @ref LL_RCC_PLLM_DIV_17
1528 * @arg @ref LL_RCC_PLLM_DIV_18
1529 * @arg @ref LL_RCC_PLLM_DIV_19
1530 * @arg @ref LL_RCC_PLLM_DIV_20
1531 * @arg @ref LL_RCC_PLLM_DIV_21
1532 * @arg @ref LL_RCC_PLLM_DIV_22
1533 * @arg @ref LL_RCC_PLLM_DIV_23
1534 * @arg @ref LL_RCC_PLLM_DIV_24
1535 * @arg @ref LL_RCC_PLLM_DIV_25
1536 * @arg @ref LL_RCC_PLLM_DIV_26
1537 * @arg @ref LL_RCC_PLLM_DIV_27
1538 * @arg @ref LL_RCC_PLLM_DIV_28
1539 * @arg @ref LL_RCC_PLLM_DIV_29
1540 * @arg @ref LL_RCC_PLLM_DIV_30
1541 * @arg @ref LL_RCC_PLLM_DIV_31
1542 * @arg @ref LL_RCC_PLLM_DIV_32
1543 * @arg @ref LL_RCC_PLLM_DIV_33
1544 * @arg @ref LL_RCC_PLLM_DIV_34
1545 * @arg @ref LL_RCC_PLLM_DIV_35
1546 * @arg @ref LL_RCC_PLLM_DIV_36
1547 * @arg @ref LL_RCC_PLLM_DIV_37
1548 * @arg @ref LL_RCC_PLLM_DIV_38
1549 * @arg @ref LL_RCC_PLLM_DIV_39
1550 * @arg @ref LL_RCC_PLLM_DIV_40
1551 * @arg @ref LL_RCC_PLLM_DIV_41
1552 * @arg @ref LL_RCC_PLLM_DIV_42
1553 * @arg @ref LL_RCC_PLLM_DIV_43
1554 * @arg @ref LL_RCC_PLLM_DIV_44
1555 * @arg @ref LL_RCC_PLLM_DIV_45
1556 * @arg @ref LL_RCC_PLLM_DIV_46
1557 * @arg @ref LL_RCC_PLLM_DIV_47
1558 * @arg @ref LL_RCC_PLLM_DIV_48
1559 * @arg @ref LL_RCC_PLLM_DIV_49
1560 * @arg @ref LL_RCC_PLLM_DIV_50
1561 * @arg @ref LL_RCC_PLLM_DIV_51
1562 * @arg @ref LL_RCC_PLLM_DIV_52
1563 * @arg @ref LL_RCC_PLLM_DIV_53
1564 * @arg @ref LL_RCC_PLLM_DIV_54
1565 * @arg @ref LL_RCC_PLLM_DIV_55
1566 * @arg @ref LL_RCC_PLLM_DIV_56
1567 * @arg @ref LL_RCC_PLLM_DIV_57
1568 * @arg @ref LL_RCC_PLLM_DIV_58
1569 * @arg @ref LL_RCC_PLLM_DIV_59
1570 * @arg @ref LL_RCC_PLLM_DIV_60
1571 * @arg @ref LL_RCC_PLLM_DIV_61
1572 * @arg @ref LL_RCC_PLLM_DIV_62
1573 * @arg @ref LL_RCC_PLLM_DIV_63
1574 * @param __PLLSAIN__ Between 50 and 432
1575 * @param __PLLSAIR__ This parameter can be one of the following values:
1576 * @arg @ref LL_RCC_PLLSAIR_DIV_2
1577 * @arg @ref LL_RCC_PLLSAIR_DIV_3
1578 * @arg @ref LL_RCC_PLLSAIR_DIV_4
1579 * @arg @ref LL_RCC_PLLSAIR_DIV_5
1580 * @arg @ref LL_RCC_PLLSAIR_DIV_6
1581 * @arg @ref LL_RCC_PLLSAIR_DIV_7
1582 * @param __PLLSAIDIVR__ This parameter can be one of the following values:
1583 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
1584 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
1585 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
1586 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
1587 * @retval PLLSAI clock frequency (in Hz)
1588 */
1589 #define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
1590 (((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR1_PLLSAIDIVR_Pos])))
1591 #endif /* LTDC */
1592
1593 /**
1594 * @brief Helper macro to calculate the PLLI2S frequency used for SAI1 and SAI2 domains
1595 * @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1596 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ ());
1597 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1598 * @param __PLLM__ This parameter can be one of the following values:
1599 * @arg @ref LL_RCC_PLLM_DIV_2
1600 * @arg @ref LL_RCC_PLLM_DIV_3
1601 * @arg @ref LL_RCC_PLLM_DIV_4
1602 * @arg @ref LL_RCC_PLLM_DIV_5
1603 * @arg @ref LL_RCC_PLLM_DIV_6
1604 * @arg @ref LL_RCC_PLLM_DIV_7
1605 * @arg @ref LL_RCC_PLLM_DIV_8
1606 * @arg @ref LL_RCC_PLLM_DIV_9
1607 * @arg @ref LL_RCC_PLLM_DIV_10
1608 * @arg @ref LL_RCC_PLLM_DIV_11
1609 * @arg @ref LL_RCC_PLLM_DIV_12
1610 * @arg @ref LL_RCC_PLLM_DIV_13
1611 * @arg @ref LL_RCC_PLLM_DIV_14
1612 * @arg @ref LL_RCC_PLLM_DIV_15
1613 * @arg @ref LL_RCC_PLLM_DIV_16
1614 * @arg @ref LL_RCC_PLLM_DIV_17
1615 * @arg @ref LL_RCC_PLLM_DIV_18
1616 * @arg @ref LL_RCC_PLLM_DIV_19
1617 * @arg @ref LL_RCC_PLLM_DIV_20
1618 * @arg @ref LL_RCC_PLLM_DIV_21
1619 * @arg @ref LL_RCC_PLLM_DIV_22
1620 * @arg @ref LL_RCC_PLLM_DIV_23
1621 * @arg @ref LL_RCC_PLLM_DIV_24
1622 * @arg @ref LL_RCC_PLLM_DIV_25
1623 * @arg @ref LL_RCC_PLLM_DIV_26
1624 * @arg @ref LL_RCC_PLLM_DIV_27
1625 * @arg @ref LL_RCC_PLLM_DIV_28
1626 * @arg @ref LL_RCC_PLLM_DIV_29
1627 * @arg @ref LL_RCC_PLLM_DIV_30
1628 * @arg @ref LL_RCC_PLLM_DIV_31
1629 * @arg @ref LL_RCC_PLLM_DIV_32
1630 * @arg @ref LL_RCC_PLLM_DIV_33
1631 * @arg @ref LL_RCC_PLLM_DIV_34
1632 * @arg @ref LL_RCC_PLLM_DIV_35
1633 * @arg @ref LL_RCC_PLLM_DIV_36
1634 * @arg @ref LL_RCC_PLLM_DIV_37
1635 * @arg @ref LL_RCC_PLLM_DIV_38
1636 * @arg @ref LL_RCC_PLLM_DIV_39
1637 * @arg @ref LL_RCC_PLLM_DIV_40
1638 * @arg @ref LL_RCC_PLLM_DIV_41
1639 * @arg @ref LL_RCC_PLLM_DIV_42
1640 * @arg @ref LL_RCC_PLLM_DIV_43
1641 * @arg @ref LL_RCC_PLLM_DIV_44
1642 * @arg @ref LL_RCC_PLLM_DIV_45
1643 * @arg @ref LL_RCC_PLLM_DIV_46
1644 * @arg @ref LL_RCC_PLLM_DIV_47
1645 * @arg @ref LL_RCC_PLLM_DIV_48
1646 * @arg @ref LL_RCC_PLLM_DIV_49
1647 * @arg @ref LL_RCC_PLLM_DIV_50
1648 * @arg @ref LL_RCC_PLLM_DIV_51
1649 * @arg @ref LL_RCC_PLLM_DIV_52
1650 * @arg @ref LL_RCC_PLLM_DIV_53
1651 * @arg @ref LL_RCC_PLLM_DIV_54
1652 * @arg @ref LL_RCC_PLLM_DIV_55
1653 * @arg @ref LL_RCC_PLLM_DIV_56
1654 * @arg @ref LL_RCC_PLLM_DIV_57
1655 * @arg @ref LL_RCC_PLLM_DIV_58
1656 * @arg @ref LL_RCC_PLLM_DIV_59
1657 * @arg @ref LL_RCC_PLLM_DIV_60
1658 * @arg @ref LL_RCC_PLLM_DIV_61
1659 * @arg @ref LL_RCC_PLLM_DIV_62
1660 * @arg @ref LL_RCC_PLLM_DIV_63
1661 * @param __PLLI2SN__ Between 50 and 432
1662 * @param __PLLI2SQ__ This parameter can be one of the following values:
1663 * @arg @ref LL_RCC_PLLI2SQ_DIV_2
1664 * @arg @ref LL_RCC_PLLI2SQ_DIV_3
1665 * @arg @ref LL_RCC_PLLI2SQ_DIV_4
1666 * @arg @ref LL_RCC_PLLI2SQ_DIV_5
1667 * @arg @ref LL_RCC_PLLI2SQ_DIV_6
1668 * @arg @ref LL_RCC_PLLI2SQ_DIV_7
1669 * @arg @ref LL_RCC_PLLI2SQ_DIV_8
1670 * @arg @ref LL_RCC_PLLI2SQ_DIV_9
1671 * @arg @ref LL_RCC_PLLI2SQ_DIV_10
1672 * @arg @ref LL_RCC_PLLI2SQ_DIV_11
1673 * @arg @ref LL_RCC_PLLI2SQ_DIV_12
1674 * @arg @ref LL_RCC_PLLI2SQ_DIV_13
1675 * @arg @ref LL_RCC_PLLI2SQ_DIV_14
1676 * @arg @ref LL_RCC_PLLI2SQ_DIV_15
1677 * @param __PLLI2SDIVQ__ This parameter can be one of the following values:
1678 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
1679 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
1680 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
1681 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
1682 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
1683 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
1684 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
1685 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
1686 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
1687 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
1688 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
1689 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
1690 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
1691 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
1692 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
1693 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
1694 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
1695 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
1696 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
1697 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
1698 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
1699 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
1700 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
1701 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
1702 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
1703 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
1704 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
1705 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
1706 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
1707 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
1708 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
1709 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
1710 * @retval PLLI2S clock frequency (in Hz)
1711 */
1712 #define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
1713 (((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ__) >> RCC_DCKCFGR1_PLLI2SDIVQ_Pos) + 1U)))
1714
1715 #if defined(SPDIFRX)
1716 /**
1717 * @brief Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain
1718 * @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1719 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ());
1720 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1721 * @param __PLLM__ This parameter can be one of the following values:
1722 * @arg @ref LL_RCC_PLLM_DIV_2
1723 * @arg @ref LL_RCC_PLLM_DIV_3
1724 * @arg @ref LL_RCC_PLLM_DIV_4
1725 * @arg @ref LL_RCC_PLLM_DIV_5
1726 * @arg @ref LL_RCC_PLLM_DIV_6
1727 * @arg @ref LL_RCC_PLLM_DIV_7
1728 * @arg @ref LL_RCC_PLLM_DIV_8
1729 * @arg @ref LL_RCC_PLLM_DIV_9
1730 * @arg @ref LL_RCC_PLLM_DIV_10
1731 * @arg @ref LL_RCC_PLLM_DIV_11
1732 * @arg @ref LL_RCC_PLLM_DIV_12
1733 * @arg @ref LL_RCC_PLLM_DIV_13
1734 * @arg @ref LL_RCC_PLLM_DIV_14
1735 * @arg @ref LL_RCC_PLLM_DIV_15
1736 * @arg @ref LL_RCC_PLLM_DIV_16
1737 * @arg @ref LL_RCC_PLLM_DIV_17
1738 * @arg @ref LL_RCC_PLLM_DIV_18
1739 * @arg @ref LL_RCC_PLLM_DIV_19
1740 * @arg @ref LL_RCC_PLLM_DIV_20
1741 * @arg @ref LL_RCC_PLLM_DIV_21
1742 * @arg @ref LL_RCC_PLLM_DIV_22
1743 * @arg @ref LL_RCC_PLLM_DIV_23
1744 * @arg @ref LL_RCC_PLLM_DIV_24
1745 * @arg @ref LL_RCC_PLLM_DIV_25
1746 * @arg @ref LL_RCC_PLLM_DIV_26
1747 * @arg @ref LL_RCC_PLLM_DIV_27
1748 * @arg @ref LL_RCC_PLLM_DIV_28
1749 * @arg @ref LL_RCC_PLLM_DIV_29
1750 * @arg @ref LL_RCC_PLLM_DIV_30
1751 * @arg @ref LL_RCC_PLLM_DIV_31
1752 * @arg @ref LL_RCC_PLLM_DIV_32
1753 * @arg @ref LL_RCC_PLLM_DIV_33
1754 * @arg @ref LL_RCC_PLLM_DIV_34
1755 * @arg @ref LL_RCC_PLLM_DIV_35
1756 * @arg @ref LL_RCC_PLLM_DIV_36
1757 * @arg @ref LL_RCC_PLLM_DIV_37
1758 * @arg @ref LL_RCC_PLLM_DIV_38
1759 * @arg @ref LL_RCC_PLLM_DIV_39
1760 * @arg @ref LL_RCC_PLLM_DIV_40
1761 * @arg @ref LL_RCC_PLLM_DIV_41
1762 * @arg @ref LL_RCC_PLLM_DIV_42
1763 * @arg @ref LL_RCC_PLLM_DIV_43
1764 * @arg @ref LL_RCC_PLLM_DIV_44
1765 * @arg @ref LL_RCC_PLLM_DIV_45
1766 * @arg @ref LL_RCC_PLLM_DIV_46
1767 * @arg @ref LL_RCC_PLLM_DIV_47
1768 * @arg @ref LL_RCC_PLLM_DIV_48
1769 * @arg @ref LL_RCC_PLLM_DIV_49
1770 * @arg @ref LL_RCC_PLLM_DIV_50
1771 * @arg @ref LL_RCC_PLLM_DIV_51
1772 * @arg @ref LL_RCC_PLLM_DIV_52
1773 * @arg @ref LL_RCC_PLLM_DIV_53
1774 * @arg @ref LL_RCC_PLLM_DIV_54
1775 * @arg @ref LL_RCC_PLLM_DIV_55
1776 * @arg @ref LL_RCC_PLLM_DIV_56
1777 * @arg @ref LL_RCC_PLLM_DIV_57
1778 * @arg @ref LL_RCC_PLLM_DIV_58
1779 * @arg @ref LL_RCC_PLLM_DIV_59
1780 * @arg @ref LL_RCC_PLLM_DIV_60
1781 * @arg @ref LL_RCC_PLLM_DIV_61
1782 * @arg @ref LL_RCC_PLLM_DIV_62
1783 * @arg @ref LL_RCC_PLLM_DIV_63
1784 * @param __PLLI2SN__ Between 50 and 432
1785 * @param __PLLI2SP__ This parameter can be one of the following values:
1786 * @arg @ref LL_RCC_PLLI2SP_DIV_2
1787 * @arg @ref LL_RCC_PLLI2SP_DIV_4
1788 * @arg @ref LL_RCC_PLLI2SP_DIV_6
1789 * @arg @ref LL_RCC_PLLI2SP_DIV_8
1790 * @retval PLLI2S clock frequency (in Hz)
1791 */
1792 #define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
1793 ((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U))
1794 #endif /* SPDIFRX */
1795
1796 /**
1797 * @brief Helper macro to calculate the PLLI2S frequency used for I2S domain
1798 * @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1799 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ());
1800 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1801 * @param __PLLM__ This parameter can be one of the following values:
1802 * @arg @ref LL_RCC_PLLM_DIV_2
1803 * @arg @ref LL_RCC_PLLM_DIV_3
1804 * @arg @ref LL_RCC_PLLM_DIV_4
1805 * @arg @ref LL_RCC_PLLM_DIV_5
1806 * @arg @ref LL_RCC_PLLM_DIV_6
1807 * @arg @ref LL_RCC_PLLM_DIV_7
1808 * @arg @ref LL_RCC_PLLM_DIV_8
1809 * @arg @ref LL_RCC_PLLM_DIV_9
1810 * @arg @ref LL_RCC_PLLM_DIV_10
1811 * @arg @ref LL_RCC_PLLM_DIV_11
1812 * @arg @ref LL_RCC_PLLM_DIV_12
1813 * @arg @ref LL_RCC_PLLM_DIV_13
1814 * @arg @ref LL_RCC_PLLM_DIV_14
1815 * @arg @ref LL_RCC_PLLM_DIV_15
1816 * @arg @ref LL_RCC_PLLM_DIV_16
1817 * @arg @ref LL_RCC_PLLM_DIV_17
1818 * @arg @ref LL_RCC_PLLM_DIV_18
1819 * @arg @ref LL_RCC_PLLM_DIV_19
1820 * @arg @ref LL_RCC_PLLM_DIV_20
1821 * @arg @ref LL_RCC_PLLM_DIV_21
1822 * @arg @ref LL_RCC_PLLM_DIV_22
1823 * @arg @ref LL_RCC_PLLM_DIV_23
1824 * @arg @ref LL_RCC_PLLM_DIV_24
1825 * @arg @ref LL_RCC_PLLM_DIV_25
1826 * @arg @ref LL_RCC_PLLM_DIV_26
1827 * @arg @ref LL_RCC_PLLM_DIV_27
1828 * @arg @ref LL_RCC_PLLM_DIV_28
1829 * @arg @ref LL_RCC_PLLM_DIV_29
1830 * @arg @ref LL_RCC_PLLM_DIV_30
1831 * @arg @ref LL_RCC_PLLM_DIV_31
1832 * @arg @ref LL_RCC_PLLM_DIV_32
1833 * @arg @ref LL_RCC_PLLM_DIV_33
1834 * @arg @ref LL_RCC_PLLM_DIV_34
1835 * @arg @ref LL_RCC_PLLM_DIV_35
1836 * @arg @ref LL_RCC_PLLM_DIV_36
1837 * @arg @ref LL_RCC_PLLM_DIV_37
1838 * @arg @ref LL_RCC_PLLM_DIV_38
1839 * @arg @ref LL_RCC_PLLM_DIV_39
1840 * @arg @ref LL_RCC_PLLM_DIV_40
1841 * @arg @ref LL_RCC_PLLM_DIV_41
1842 * @arg @ref LL_RCC_PLLM_DIV_42
1843 * @arg @ref LL_RCC_PLLM_DIV_43
1844 * @arg @ref LL_RCC_PLLM_DIV_44
1845 * @arg @ref LL_RCC_PLLM_DIV_45
1846 * @arg @ref LL_RCC_PLLM_DIV_46
1847 * @arg @ref LL_RCC_PLLM_DIV_47
1848 * @arg @ref LL_RCC_PLLM_DIV_48
1849 * @arg @ref LL_RCC_PLLM_DIV_49
1850 * @arg @ref LL_RCC_PLLM_DIV_50
1851 * @arg @ref LL_RCC_PLLM_DIV_51
1852 * @arg @ref LL_RCC_PLLM_DIV_52
1853 * @arg @ref LL_RCC_PLLM_DIV_53
1854 * @arg @ref LL_RCC_PLLM_DIV_54
1855 * @arg @ref LL_RCC_PLLM_DIV_55
1856 * @arg @ref LL_RCC_PLLM_DIV_56
1857 * @arg @ref LL_RCC_PLLM_DIV_57
1858 * @arg @ref LL_RCC_PLLM_DIV_58
1859 * @arg @ref LL_RCC_PLLM_DIV_59
1860 * @arg @ref LL_RCC_PLLM_DIV_60
1861 * @arg @ref LL_RCC_PLLM_DIV_61
1862 * @arg @ref LL_RCC_PLLM_DIV_62
1863 * @arg @ref LL_RCC_PLLM_DIV_63
1864 * @param __PLLI2SN__ Between 50 and 432
1865 * @param __PLLI2SR__ This parameter can be one of the following values:
1866 * @arg @ref LL_RCC_PLLI2SR_DIV_2
1867 * @arg @ref LL_RCC_PLLI2SR_DIV_3
1868 * @arg @ref LL_RCC_PLLI2SR_DIV_4
1869 * @arg @ref LL_RCC_PLLI2SR_DIV_5
1870 * @arg @ref LL_RCC_PLLI2SR_DIV_6
1871 * @arg @ref LL_RCC_PLLI2SR_DIV_7
1872 * @retval PLLI2S clock frequency (in Hz)
1873 */
1874 #define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
1875 ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos))
1876
1877 /**
1878 * @brief Helper macro to calculate the HCLK frequency
1879 * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
1880 * @param __AHBPRESCALER__ This parameter can be one of the following values:
1881 * @arg @ref LL_RCC_SYSCLK_DIV_1
1882 * @arg @ref LL_RCC_SYSCLK_DIV_2
1883 * @arg @ref LL_RCC_SYSCLK_DIV_4
1884 * @arg @ref LL_RCC_SYSCLK_DIV_8
1885 * @arg @ref LL_RCC_SYSCLK_DIV_16
1886 * @arg @ref LL_RCC_SYSCLK_DIV_64
1887 * @arg @ref LL_RCC_SYSCLK_DIV_128
1888 * @arg @ref LL_RCC_SYSCLK_DIV_256
1889 * @arg @ref LL_RCC_SYSCLK_DIV_512
1890 * @retval HCLK clock frequency (in Hz)
1891 */
1892 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
1893
1894 /**
1895 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
1896 * @param __HCLKFREQ__ HCLK frequency
1897 * @param __APB1PRESCALER__ This parameter can be one of the following values:
1898 * @arg @ref LL_RCC_APB1_DIV_1
1899 * @arg @ref LL_RCC_APB1_DIV_2
1900 * @arg @ref LL_RCC_APB1_DIV_4
1901 * @arg @ref LL_RCC_APB1_DIV_8
1902 * @arg @ref LL_RCC_APB1_DIV_16
1903 * @retval PCLK1 clock frequency (in Hz)
1904 */
1905 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
1906
1907 /**
1908 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
1909 * @param __HCLKFREQ__ HCLK frequency
1910 * @param __APB2PRESCALER__ This parameter can be one of the following values:
1911 * @arg @ref LL_RCC_APB2_DIV_1
1912 * @arg @ref LL_RCC_APB2_DIV_2
1913 * @arg @ref LL_RCC_APB2_DIV_4
1914 * @arg @ref LL_RCC_APB2_DIV_8
1915 * @arg @ref LL_RCC_APB2_DIV_16
1916 * @retval PCLK2 clock frequency (in Hz)
1917 */
1918 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
1919
1920 /**
1921 * @}
1922 */
1923
1924 /**
1925 * @}
1926 */
1927
1928 /* Exported functions --------------------------------------------------------*/
1929 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
1930 * @{
1931 */
1932
1933 /** @defgroup RCC_LL_EF_HSE HSE
1934 * @{
1935 */
1936
1937 /**
1938 * @brief Enable the Clock Security System.
1939 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
1940 * @retval None
1941 */
LL_RCC_HSE_EnableCSS(void)1942 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
1943 {
1944 SET_BIT(RCC->CR, RCC_CR_CSSON);
1945 }
1946
1947 /**
1948 * @brief Enable HSE external oscillator (HSE Bypass)
1949 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
1950 * @retval None
1951 */
LL_RCC_HSE_EnableBypass(void)1952 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
1953 {
1954 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
1955 }
1956
1957 /**
1958 * @brief Disable HSE external oscillator (HSE Bypass)
1959 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
1960 * @retval None
1961 */
LL_RCC_HSE_DisableBypass(void)1962 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
1963 {
1964 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
1965 }
1966
1967 /**
1968 * @brief Enable HSE crystal oscillator (HSE ON)
1969 * @rmtoll CR HSEON LL_RCC_HSE_Enable
1970 * @retval None
1971 */
LL_RCC_HSE_Enable(void)1972 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
1973 {
1974 SET_BIT(RCC->CR, RCC_CR_HSEON);
1975 }
1976
1977 /**
1978 * @brief Disable HSE crystal oscillator (HSE ON)
1979 * @rmtoll CR HSEON LL_RCC_HSE_Disable
1980 * @retval None
1981 */
LL_RCC_HSE_Disable(void)1982 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
1983 {
1984 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
1985 }
1986
1987 /**
1988 * @brief Check if HSE oscillator Ready
1989 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
1990 * @retval State of bit (1 or 0).
1991 */
LL_RCC_HSE_IsReady(void)1992 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
1993 {
1994 return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
1995 }
1996
1997 /**
1998 * @}
1999 */
2000
2001 /** @defgroup RCC_LL_EF_HSI HSI
2002 * @{
2003 */
2004
2005 /**
2006 * @brief Enable HSI oscillator
2007 * @rmtoll CR HSION LL_RCC_HSI_Enable
2008 * @retval None
2009 */
LL_RCC_HSI_Enable(void)2010 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
2011 {
2012 SET_BIT(RCC->CR, RCC_CR_HSION);
2013 }
2014
2015 /**
2016 * @brief Disable HSI oscillator
2017 * @rmtoll CR HSION LL_RCC_HSI_Disable
2018 * @retval None
2019 */
LL_RCC_HSI_Disable(void)2020 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
2021 {
2022 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
2023 }
2024
2025 /**
2026 * @brief Check if HSI clock is ready
2027 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
2028 * @retval State of bit (1 or 0).
2029 */
LL_RCC_HSI_IsReady(void)2030 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
2031 {
2032 return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
2033 }
2034
2035 /**
2036 * @brief Get HSI Calibration value
2037 * @note When HSITRIM is written, HSICAL is updated with the sum of
2038 * HSITRIM and the factory trim value
2039 * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
2040 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
2041 */
LL_RCC_HSI_GetCalibration(void)2042 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
2043 {
2044 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
2045 }
2046
2047 /**
2048 * @brief Set HSI Calibration trimming
2049 * @note user-programmable trimming value that is added to the HSICAL
2050 * @note Default value is 16, which, when added to the HSICAL value,
2051 * should trim the HSI to 16 MHz +/- 1 %
2052 * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
2053 * @param Value Between Min_Data = 0 and Max_Data = 31
2054 * @retval None
2055 */
LL_RCC_HSI_SetCalibTrimming(uint32_t Value)2056 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
2057 {
2058 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
2059 }
2060
2061 /**
2062 * @brief Get HSI Calibration trimming
2063 * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
2064 * @retval Between Min_Data = 0 and Max_Data = 31
2065 */
LL_RCC_HSI_GetCalibTrimming(void)2066 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
2067 {
2068 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
2069 }
2070
2071 /**
2072 * @}
2073 */
2074
2075 /** @defgroup RCC_LL_EF_LSE LSE
2076 * @{
2077 */
2078
2079 /**
2080 * @brief Enable Low Speed External (LSE) crystal.
2081 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
2082 * @retval None
2083 */
LL_RCC_LSE_Enable(void)2084 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
2085 {
2086 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
2087 }
2088
2089 /**
2090 * @brief Disable Low Speed External (LSE) crystal.
2091 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
2092 * @retval None
2093 */
LL_RCC_LSE_Disable(void)2094 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
2095 {
2096 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
2097 }
2098
2099 /**
2100 * @brief Enable external clock source (LSE bypass).
2101 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
2102 * @retval None
2103 */
LL_RCC_LSE_EnableBypass(void)2104 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
2105 {
2106 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
2107 }
2108
2109 /**
2110 * @brief Disable external clock source (LSE bypass).
2111 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
2112 * @retval None
2113 */
LL_RCC_LSE_DisableBypass(void)2114 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
2115 {
2116 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
2117 }
2118
2119 /**
2120 * @brief Set LSE oscillator drive capability
2121 * @note The oscillator is in Xtal mode when it is not in bypass mode.
2122 * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
2123 * @param LSEDrive This parameter can be one of the following values:
2124 * @arg @ref LL_RCC_LSEDRIVE_LOW
2125 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
2126 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
2127 * @arg @ref LL_RCC_LSEDRIVE_HIGH
2128 * @retval None
2129 */
LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)2130 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
2131 {
2132 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
2133 }
2134
2135 /**
2136 * @brief Get LSE oscillator drive capability
2137 * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
2138 * @retval Returned value can be one of the following values:
2139 * @arg @ref LL_RCC_LSEDRIVE_LOW
2140 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
2141 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
2142 * @arg @ref LL_RCC_LSEDRIVE_HIGH
2143 */
LL_RCC_LSE_GetDriveCapability(void)2144 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
2145 {
2146 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
2147 }
2148
2149 /**
2150 * @brief Check if LSE oscillator Ready
2151 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
2152 * @retval State of bit (1 or 0).
2153 */
LL_RCC_LSE_IsReady(void)2154 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
2155 {
2156 return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
2157 }
2158
2159 /**
2160 * @}
2161 */
2162
2163 /** @defgroup RCC_LL_EF_LSI LSI
2164 * @{
2165 */
2166
2167 /**
2168 * @brief Enable LSI Oscillator
2169 * @rmtoll CSR LSION LL_RCC_LSI_Enable
2170 * @retval None
2171 */
LL_RCC_LSI_Enable(void)2172 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
2173 {
2174 SET_BIT(RCC->CSR, RCC_CSR_LSION);
2175 }
2176
2177 /**
2178 * @brief Disable LSI Oscillator
2179 * @rmtoll CSR LSION LL_RCC_LSI_Disable
2180 * @retval None
2181 */
LL_RCC_LSI_Disable(void)2182 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
2183 {
2184 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
2185 }
2186
2187 /**
2188 * @brief Check if LSI is Ready
2189 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
2190 * @retval State of bit (1 or 0).
2191 */
LL_RCC_LSI_IsReady(void)2192 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
2193 {
2194 return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
2195 }
2196
2197 /**
2198 * @}
2199 */
2200
2201 /** @defgroup RCC_LL_EF_System System
2202 * @{
2203 */
2204
2205 /**
2206 * @brief Configure the system clock source
2207 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
2208 * @param Source This parameter can be one of the following values:
2209 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
2210 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
2211 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
2212 * @retval None
2213 */
LL_RCC_SetSysClkSource(uint32_t Source)2214 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
2215 {
2216 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
2217 }
2218
2219 /**
2220 * @brief Get the system clock source
2221 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
2222 * @retval Returned value can be one of the following values:
2223 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
2224 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
2225 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
2226 */
LL_RCC_GetSysClkSource(void)2227 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
2228 {
2229 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
2230 }
2231
2232 /**
2233 * @brief Set AHB prescaler
2234 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
2235 * @param Prescaler This parameter can be one of the following values:
2236 * @arg @ref LL_RCC_SYSCLK_DIV_1
2237 * @arg @ref LL_RCC_SYSCLK_DIV_2
2238 * @arg @ref LL_RCC_SYSCLK_DIV_4
2239 * @arg @ref LL_RCC_SYSCLK_DIV_8
2240 * @arg @ref LL_RCC_SYSCLK_DIV_16
2241 * @arg @ref LL_RCC_SYSCLK_DIV_64
2242 * @arg @ref LL_RCC_SYSCLK_DIV_128
2243 * @arg @ref LL_RCC_SYSCLK_DIV_256
2244 * @arg @ref LL_RCC_SYSCLK_DIV_512
2245 * @retval None
2246 */
LL_RCC_SetAHBPrescaler(uint32_t Prescaler)2247 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
2248 {
2249 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
2250 }
2251
2252 /**
2253 * @brief Set APB1 prescaler
2254 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
2255 * @param Prescaler This parameter can be one of the following values:
2256 * @arg @ref LL_RCC_APB1_DIV_1
2257 * @arg @ref LL_RCC_APB1_DIV_2
2258 * @arg @ref LL_RCC_APB1_DIV_4
2259 * @arg @ref LL_RCC_APB1_DIV_8
2260 * @arg @ref LL_RCC_APB1_DIV_16
2261 * @retval None
2262 */
LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)2263 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
2264 {
2265 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
2266 }
2267
2268 /**
2269 * @brief Set APB2 prescaler
2270 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
2271 * @param Prescaler This parameter can be one of the following values:
2272 * @arg @ref LL_RCC_APB2_DIV_1
2273 * @arg @ref LL_RCC_APB2_DIV_2
2274 * @arg @ref LL_RCC_APB2_DIV_4
2275 * @arg @ref LL_RCC_APB2_DIV_8
2276 * @arg @ref LL_RCC_APB2_DIV_16
2277 * @retval None
2278 */
LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)2279 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
2280 {
2281 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
2282 }
2283
2284 /**
2285 * @brief Get AHB prescaler
2286 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
2287 * @retval Returned value can be one of the following values:
2288 * @arg @ref LL_RCC_SYSCLK_DIV_1
2289 * @arg @ref LL_RCC_SYSCLK_DIV_2
2290 * @arg @ref LL_RCC_SYSCLK_DIV_4
2291 * @arg @ref LL_RCC_SYSCLK_DIV_8
2292 * @arg @ref LL_RCC_SYSCLK_DIV_16
2293 * @arg @ref LL_RCC_SYSCLK_DIV_64
2294 * @arg @ref LL_RCC_SYSCLK_DIV_128
2295 * @arg @ref LL_RCC_SYSCLK_DIV_256
2296 * @arg @ref LL_RCC_SYSCLK_DIV_512
2297 */
LL_RCC_GetAHBPrescaler(void)2298 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
2299 {
2300 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
2301 }
2302
2303 /**
2304 * @brief Get APB1 prescaler
2305 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
2306 * @retval Returned value can be one of the following values:
2307 * @arg @ref LL_RCC_APB1_DIV_1
2308 * @arg @ref LL_RCC_APB1_DIV_2
2309 * @arg @ref LL_RCC_APB1_DIV_4
2310 * @arg @ref LL_RCC_APB1_DIV_8
2311 * @arg @ref LL_RCC_APB1_DIV_16
2312 */
LL_RCC_GetAPB1Prescaler(void)2313 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
2314 {
2315 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
2316 }
2317
2318 /**
2319 * @brief Get APB2 prescaler
2320 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
2321 * @retval Returned value can be one of the following values:
2322 * @arg @ref LL_RCC_APB2_DIV_1
2323 * @arg @ref LL_RCC_APB2_DIV_2
2324 * @arg @ref LL_RCC_APB2_DIV_4
2325 * @arg @ref LL_RCC_APB2_DIV_8
2326 * @arg @ref LL_RCC_APB2_DIV_16
2327 */
LL_RCC_GetAPB2Prescaler(void)2328 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
2329 {
2330 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
2331 }
2332
2333 /**
2334 * @}
2335 */
2336
2337 /** @defgroup RCC_LL_EF_MCO MCO
2338 * @{
2339 */
2340
2341 /**
2342 * @brief Configure MCOx
2343 * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n
2344 * CFGR MCO1PRE LL_RCC_ConfigMCO\n
2345 * CFGR MCO2 LL_RCC_ConfigMCO\n
2346 * CFGR MCO2PRE LL_RCC_ConfigMCO
2347 * @param MCOxSource This parameter can be one of the following values:
2348 * @arg @ref LL_RCC_MCO1SOURCE_HSI
2349 * @arg @ref LL_RCC_MCO1SOURCE_LSE
2350 * @arg @ref LL_RCC_MCO1SOURCE_HSE
2351 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
2352 * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
2353 * @arg @ref LL_RCC_MCO2SOURCE_PLLI2S
2354 * @arg @ref LL_RCC_MCO2SOURCE_HSE
2355 * @arg @ref LL_RCC_MCO2SOURCE_PLLCLK
2356 * @param MCOxPrescaler This parameter can be one of the following values:
2357 * @arg @ref LL_RCC_MCO1_DIV_1
2358 * @arg @ref LL_RCC_MCO1_DIV_2
2359 * @arg @ref LL_RCC_MCO1_DIV_3
2360 * @arg @ref LL_RCC_MCO1_DIV_4
2361 * @arg @ref LL_RCC_MCO1_DIV_5
2362 * @arg @ref LL_RCC_MCO2_DIV_1
2363 * @arg @ref LL_RCC_MCO2_DIV_2
2364 * @arg @ref LL_RCC_MCO2_DIV_3
2365 * @arg @ref LL_RCC_MCO2_DIV_4
2366 * @arg @ref LL_RCC_MCO2_DIV_5
2367 * @retval None
2368 */
LL_RCC_ConfigMCO(uint32_t MCOxSource,uint32_t MCOxPrescaler)2369 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
2370 {
2371 MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << 16U) | (MCOxPrescaler << 16U));
2372 }
2373
2374 /**
2375 * @}
2376 */
2377
2378 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
2379 * @{
2380 */
2381
2382 /**
2383 * @brief Configure USARTx clock source
2384 * @rmtoll DCKCFGR2 USART1SEL LL_RCC_SetUSARTClockSource\n
2385 * DCKCFGR2 USART2SEL LL_RCC_SetUSARTClockSource\n
2386 * DCKCFGR2 USART3SEL LL_RCC_SetUSARTClockSource\n
2387 * DCKCFGR2 USART6SEL LL_RCC_SetUSARTClockSource
2388 * @param USARTxSource This parameter can be one of the following values:
2389 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
2390 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
2391 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
2392 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
2393 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
2394 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
2395 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
2396 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
2397 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
2398 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
2399 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
2400 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
2401 * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2
2402 * @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK
2403 * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI
2404 * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE
2405 * @retval None
2406 */
LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)2407 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
2408 {
2409 MODIFY_REG(RCC->DCKCFGR2, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU));
2410 }
2411
2412 /**
2413 * @brief Configure UARTx clock source
2414 * @rmtoll DCKCFGR2 UART4SEL LL_RCC_SetUARTClockSource\n
2415 * DCKCFGR2 UART5SEL LL_RCC_SetUARTClockSource\n
2416 * DCKCFGR2 UART7SEL LL_RCC_SetUARTClockSource\n
2417 * DCKCFGR2 UART8SEL LL_RCC_SetUARTClockSource
2418 * @param UARTxSource This parameter can be one of the following values:
2419 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
2420 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
2421 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
2422 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
2423 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
2424 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
2425 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
2426 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
2427 * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1
2428 * @arg @ref LL_RCC_UART7_CLKSOURCE_SYSCLK
2429 * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI
2430 * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE
2431 * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1
2432 * @arg @ref LL_RCC_UART8_CLKSOURCE_SYSCLK
2433 * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI
2434 * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE
2435 * @retval None
2436 */
LL_RCC_SetUARTClockSource(uint32_t UARTxSource)2437 __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
2438 {
2439 MODIFY_REG(RCC->DCKCFGR2, (UARTxSource >> 16U), (UARTxSource & 0x0000FFFFU));
2440 }
2441
2442 /**
2443 * @brief Configure I2Cx clock source
2444 * @rmtoll DCKCFGR2 I2C1SEL LL_RCC_SetI2CClockSource\n
2445 * DCKCFGR2 I2C2SEL LL_RCC_SetI2CClockSource\n
2446 * DCKCFGR2 I2C3SEL LL_RCC_SetI2CClockSource\n
2447 * DCKCFGR2 I2C4SEL LL_RCC_SetI2CClockSource
2448 * @param I2CxSource This parameter can be one of the following values:
2449 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
2450 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
2451 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
2452 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
2453 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
2454 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
2455 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
2456 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
2457 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
2458 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
2459 * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
2460 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
2461 *
2462 * (*) value not defined in all devices.
2463 * @retval None
2464 */
LL_RCC_SetI2CClockSource(uint32_t I2CxSource)2465 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
2466 {
2467 MODIFY_REG(RCC->DCKCFGR2, (I2CxSource & 0xFFFF0000U), (I2CxSource << 16U));
2468 }
2469
2470 /**
2471 * @brief Configure LPTIMx clock source
2472 * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_SetLPTIMClockSource
2473 * @param LPTIMxSource This parameter can be one of the following values:
2474 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2475 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2476 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
2477 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2478 * @retval None
2479 */
LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)2480 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
2481 {
2482 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource);
2483 }
2484
2485 /**
2486 * @brief Configure SAIx clock source
2487 * @rmtoll DCKCFGR1 SAI1SEL LL_RCC_SetSAIClockSource\n
2488 * DCKCFGR1 SAI2SEL LL_RCC_SetSAIClockSource
2489 * @param SAIxSource This parameter can be one of the following values:
2490 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI
2491 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S
2492 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
2493 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSRC (*)
2494 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI
2495 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S
2496 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN
2497 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
2498 *
2499 * (*) value not defined in all devices.
2500 * @retval None
2501 */
LL_RCC_SetSAIClockSource(uint32_t SAIxSource)2502 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
2503 {
2504 MODIFY_REG(RCC->DCKCFGR1, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));
2505 }
2506
2507 /**
2508 * @brief Configure SDMMC clock source
2509 * @rmtoll DCKCFGR2 SDMMC1SEL LL_RCC_SetSDMMCClockSource\n
2510 * DCKCFGR2 SDMMC2SEL LL_RCC_SetSDMMCClockSource
2511 * @param SDMMCxSource This parameter can be one of the following values:
2512 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK
2513 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_SYSCLK
2514 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (*)
2515 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (*)
2516 *
2517 * (*) value not defined in all devices.
2518 * @retval None
2519 */
LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)2520 __STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)
2521 {
2522 MODIFY_REG(RCC->DCKCFGR2, (SDMMCxSource & 0xFFFF0000U), (SDMMCxSource << 16U));
2523 }
2524
2525 /**
2526 * @brief Configure 48Mhz domain clock source
2527 * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_SetCK48MClockSource
2528 * @param CK48MxSource This parameter can be one of the following values:
2529 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
2530 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI
2531 * @retval None
2532 */
LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource)2533 __STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource)
2534 {
2535 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource);
2536 }
2537
2538 /**
2539 * @brief Configure RNG clock source
2540 * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_SetRNGClockSource
2541 * @param RNGxSource This parameter can be one of the following values:
2542 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
2543 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI
2544 * @retval None
2545 */
LL_RCC_SetRNGClockSource(uint32_t RNGxSource)2546 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
2547 {
2548 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource);
2549 }
2550
2551 /**
2552 * @brief Configure USB clock source
2553 * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_SetUSBClockSource
2554 * @param USBxSource This parameter can be one of the following values:
2555 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
2556 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI
2557 * @retval None
2558 */
LL_RCC_SetUSBClockSource(uint32_t USBxSource)2559 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
2560 {
2561 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource);
2562 }
2563
2564 #if defined(CEC)
2565 /**
2566 * @brief Configure CEC clock source
2567 * @rmtoll DCKCFGR2 CECSEL LL_RCC_SetCECClockSource
2568 * @param Source This parameter can be one of the following values:
2569 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
2570 * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
2571 * @retval None
2572 */
LL_RCC_SetCECClockSource(uint32_t Source)2573 __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source)
2574 {
2575 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source);
2576 }
2577 #endif /* CEC */
2578
2579 /**
2580 * @brief Configure I2S clock source
2581 * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource
2582 * @param Source This parameter can be one of the following values:
2583 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S
2584 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
2585 * @retval None
2586 */
LL_RCC_SetI2SClockSource(uint32_t Source)2587 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source)
2588 {
2589 MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source);
2590 }
2591
2592 #if defined(DSI)
2593 /**
2594 * @brief Configure DSI clock source
2595 * @rmtoll DCKCFGR2 DSISEL LL_RCC_SetDSIClockSource
2596 * @param Source This parameter can be one of the following values:
2597 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
2598 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
2599 * @retval None
2600 */
LL_RCC_SetDSIClockSource(uint32_t Source)2601 __STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)
2602 {
2603 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, Source);
2604 }
2605 #endif /* DSI */
2606
2607 #if defined(DFSDM1_Channel0)
2608 /**
2609 * @brief Configure DFSDM Audio clock source
2610 * @rmtoll DCKCFGR1 ADFSDM1SEL LL_RCC_SetDFSDMAudioClockSource
2611 * @param Source This parameter can be one of the following values:
2612 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1
2613 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2
2614 * @retval None
2615 */
LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)2616 __STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)
2617 {
2618 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, Source);
2619 }
2620
2621 /**
2622 * @brief Configure DFSDM Kernel clock source
2623 * @rmtoll DCKCFGR1 DFSDM1SEL LL_RCC_SetDFSDMClockSource
2624 * @param Source This parameter can be one of the following values:
2625 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
2626 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
2627 * @retval None
2628 */
LL_RCC_SetDFSDMClockSource(uint32_t Source)2629 __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source)
2630 {
2631 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, Source);
2632 }
2633 #endif /* DFSDM1_Channel0 */
2634
2635 /**
2636 * @brief Get USARTx clock source
2637 * @rmtoll DCKCFGR2 USART1SEL LL_RCC_GetUSARTClockSource\n
2638 * DCKCFGR2 USART2SEL LL_RCC_GetUSARTClockSource\n
2639 * DCKCFGR2 USART3SEL LL_RCC_GetUSARTClockSource\n
2640 * DCKCFGR2 USART6SEL LL_RCC_GetUSARTClockSource
2641 * @param USARTx This parameter can be one of the following values:
2642 * @arg @ref LL_RCC_USART1_CLKSOURCE
2643 * @arg @ref LL_RCC_USART2_CLKSOURCE
2644 * @arg @ref LL_RCC_USART3_CLKSOURCE
2645 * @arg @ref LL_RCC_USART6_CLKSOURCE
2646 * @retval Returned value can be one of the following values:
2647 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
2648 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
2649 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
2650 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
2651 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
2652 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
2653 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
2654 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
2655 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
2656 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
2657 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
2658 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
2659 * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2
2660 * @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK
2661 * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI
2662 * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE
2663 */
LL_RCC_GetUSARTClockSource(uint32_t USARTx)2664 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
2665 {
2666 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USARTx) | (USARTx << 16U));
2667 }
2668
2669 /**
2670 * @brief Get UARTx clock source
2671 * @rmtoll DCKCFGR2 UART4SEL LL_RCC_GetUARTClockSource\n
2672 * DCKCFGR2 UART5SEL LL_RCC_GetUARTClockSource\n
2673 * DCKCFGR2 UART7SEL LL_RCC_GetUARTClockSource\n
2674 * DCKCFGR2 UART8SEL LL_RCC_GetUARTClockSource
2675 * @param UARTx This parameter can be one of the following values:
2676 * @arg @ref LL_RCC_UART4_CLKSOURCE
2677 * @arg @ref LL_RCC_UART5_CLKSOURCE
2678 * @arg @ref LL_RCC_UART7_CLKSOURCE
2679 * @arg @ref LL_RCC_UART8_CLKSOURCE
2680 * @retval Returned value can be one of the following values:
2681 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
2682 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
2683 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
2684 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
2685 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
2686 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
2687 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
2688 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
2689 * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1
2690 * @arg @ref LL_RCC_UART7_CLKSOURCE_SYSCLK
2691 * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI
2692 * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE
2693 * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1
2694 * @arg @ref LL_RCC_UART8_CLKSOURCE_SYSCLK
2695 * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI
2696 * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE
2697 */
LL_RCC_GetUARTClockSource(uint32_t UARTx)2698 __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
2699 {
2700 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, UARTx) | (UARTx << 16U));
2701 }
2702
2703 /**
2704 * @brief Get I2Cx clock source
2705 * @rmtoll DCKCFGR2 I2C1SEL LL_RCC_GetI2CClockSource\n
2706 * DCKCFGR2 I2C2SEL LL_RCC_GetI2CClockSource\n
2707 * DCKCFGR2 I2C3SEL LL_RCC_GetI2CClockSource\n
2708 * DCKCFGR2 I2C4SEL LL_RCC_GetI2CClockSource
2709 * @param I2Cx This parameter can be one of the following values:
2710 * @arg @ref LL_RCC_I2C1_CLKSOURCE
2711 * @arg @ref LL_RCC_I2C2_CLKSOURCE
2712 * @arg @ref LL_RCC_I2C3_CLKSOURCE
2713 * @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
2714 * @retval Returned value can be one of the following values:
2715 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
2716 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
2717 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
2718 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
2719 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
2720 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
2721 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
2722 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
2723 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
2724 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
2725 * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
2726 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
2727 *
2728 * (*) value not defined in all devices.
2729 */
LL_RCC_GetI2CClockSource(uint32_t I2Cx)2730 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
2731 {
2732 return (uint32_t)((READ_BIT(RCC->DCKCFGR2, I2Cx) >> 16U) | I2Cx);
2733 }
2734
2735 /**
2736 * @brief Get LPTIMx clock source
2737 * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_GetLPTIMClockSource
2738 * @param LPTIMx This parameter can be one of the following values:
2739 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
2740 * @retval Returned value can be one of the following values:
2741 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2742 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2743 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
2744 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2745 */
LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)2746 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
2747 {
2748 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL));
2749 }
2750
2751 /**
2752 * @brief Get SAIx clock source
2753 * @rmtoll DCKCFGR1 SAI1SEL LL_RCC_GetSAIClockSource\n
2754 * DCKCFGR1 SAI2SEL LL_RCC_GetSAIClockSource
2755 * @param SAIx This parameter can be one of the following values:
2756 * @arg @ref LL_RCC_SAI1_CLKSOURCE
2757 * @arg @ref LL_RCC_SAI2_CLKSOURCE
2758 * @retval Returned value can be one of the following values:
2759 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI
2760 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S
2761 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
2762 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSRC (*)
2763 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI
2764 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S
2765 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN
2766 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
2767 *
2768 * (*) value not defined in all devices.
2769 */
LL_RCC_GetSAIClockSource(uint32_t SAIx)2770 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
2771 {
2772 return (uint32_t)(READ_BIT(RCC->DCKCFGR1, SAIx) >> 16U | SAIx);
2773 }
2774
2775 /**
2776 * @brief Get SDMMCx clock source
2777 * @rmtoll DCKCFGR2 SDMMC1SEL LL_RCC_GetSDMMCClockSource\n
2778 * DCKCFGR2 SDMMC2SEL LL_RCC_GetSDMMCClockSource
2779 * @param SDMMCx This parameter can be one of the following values:
2780 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE
2781 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE (*)
2782 * @retval Returned value can be one of the following values:
2783 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK
2784 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_SYSCLK
2785 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (*)
2786 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (*)
2787 *
2788 * (*) value not defined in all devices.
2789 */
LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)2790 __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)
2791 {
2792 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDMMCx) >> 16U | SDMMCx);
2793 }
2794
2795 /**
2796 * @brief Get 48Mhz domain clock source
2797 * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_GetCK48MClockSource
2798 * @param CK48Mx This parameter can be one of the following values:
2799 * @arg @ref LL_RCC_CK48M_CLKSOURCE
2800 * @retval Returned value can be one of the following values:
2801 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
2802 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI
2803 */
LL_RCC_GetCK48MClockSource(uint32_t CK48Mx)2804 __STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx)
2805 {
2806 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx));
2807 }
2808
2809 /**
2810 * @brief Get RNGx clock source
2811 * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_GetRNGClockSource
2812 * @param RNGx This parameter can be one of the following values:
2813 * @arg @ref LL_RCC_RNG_CLKSOURCE
2814 * @retval Returned value can be one of the following values:
2815 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
2816 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI
2817 */
LL_RCC_GetRNGClockSource(uint32_t RNGx)2818 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
2819 {
2820 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx));
2821 }
2822
2823 /**
2824 * @brief Get USBx clock source
2825 * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_GetUSBClockSource
2826 * @param USBx This parameter can be one of the following values:
2827 * @arg @ref LL_RCC_USB_CLKSOURCE
2828 * @retval Returned value can be one of the following values:
2829 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
2830 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI
2831 */
LL_RCC_GetUSBClockSource(uint32_t USBx)2832 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
2833 {
2834 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx));
2835 }
2836
2837 #if defined(CEC)
2838 /**
2839 * @brief Get CEC Clock Source
2840 * @rmtoll DCKCFGR2 CECSEL LL_RCC_GetCECClockSource
2841 * @param CECx This parameter can be one of the following values:
2842 * @arg @ref LL_RCC_CEC_CLKSOURCE
2843 * @retval Returned value can be one of the following values:
2844 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
2845 * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
2846 */
LL_RCC_GetCECClockSource(uint32_t CECx)2847 __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
2848 {
2849 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx));
2850 }
2851 #endif /* CEC */
2852
2853 /**
2854 * @brief Get I2S Clock Source
2855 * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource
2856 * @param I2Sx This parameter can be one of the following values:
2857 * @arg @ref LL_RCC_I2S1_CLKSOURCE
2858 * @retval Returned value can be one of the following values:
2859 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S
2860 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
2861 */
LL_RCC_GetI2SClockSource(uint32_t I2Sx)2862 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
2863 {
2864 return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
2865 }
2866
2867 #if defined(DFSDM1_Channel0)
2868 /**
2869 * @brief Get DFSDM Audio Clock Source
2870 * @rmtoll DCKCFGR1 ADFSDM1SEL LL_RCC_GetDFSDMAudioClockSource
2871 * @param DFSDMx This parameter can be one of the following values:
2872 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
2873 * @retval Returned value can be one of the following values:
2874 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1
2875 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2
2876 */
LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)2877 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)
2878 {
2879 return (uint32_t)(READ_BIT(RCC->DCKCFGR1, DFSDMx));
2880 }
2881
2882 /**
2883 * @brief Get DFSDM Audio Clock Source
2884 * @rmtoll DCKCFGR1 DFSDM1SEL LL_RCC_GetDFSDMClockSource
2885 * @param DFSDMx This parameter can be one of the following values:
2886 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
2887 * @retval Returned value can be one of the following values:
2888 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
2889 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
2890 */
LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)2891 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
2892 {
2893 return (uint32_t)(READ_BIT(RCC->DCKCFGR1, DFSDMx));
2894 }
2895 #endif /* DFSDM1_Channel0 */
2896
2897 #if defined(DSI)
2898 /**
2899 * @brief Get DSI Clock Source
2900 * @rmtoll DCKCFGR2 DSISEL LL_RCC_GetDSIClockSource
2901 * @param DSIx This parameter can be one of the following values:
2902 * @arg @ref LL_RCC_DSI_CLKSOURCE
2903 * @retval Returned value can be one of the following values:
2904 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
2905 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
2906 */
LL_RCC_GetDSIClockSource(uint32_t DSIx)2907 __STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)
2908 {
2909 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, DSIx));
2910 }
2911 #endif /* DSI */
2912
2913 /**
2914 * @}
2915 */
2916
2917 /** @defgroup RCC_LL_EF_RTC RTC
2918 * @{
2919 */
2920
2921 /**
2922 * @brief Set RTC Clock Source
2923 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
2924 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
2925 * set). The BDRST bit can be used to reset them.
2926 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
2927 * @param Source This parameter can be one of the following values:
2928 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2929 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2930 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2931 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
2932 * @retval None
2933 */
LL_RCC_SetRTCClockSource(uint32_t Source)2934 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
2935 {
2936 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
2937 }
2938
2939 /**
2940 * @brief Get RTC Clock Source
2941 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
2942 * @retval Returned value can be one of the following values:
2943 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2944 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2945 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2946 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
2947 */
LL_RCC_GetRTCClockSource(void)2948 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
2949 {
2950 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
2951 }
2952
2953 /**
2954 * @brief Enable RTC
2955 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
2956 * @retval None
2957 */
LL_RCC_EnableRTC(void)2958 __STATIC_INLINE void LL_RCC_EnableRTC(void)
2959 {
2960 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
2961 }
2962
2963 /**
2964 * @brief Disable RTC
2965 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
2966 * @retval None
2967 */
LL_RCC_DisableRTC(void)2968 __STATIC_INLINE void LL_RCC_DisableRTC(void)
2969 {
2970 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
2971 }
2972
2973 /**
2974 * @brief Check if RTC has been enabled or not
2975 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
2976 * @retval State of bit (1 or 0).
2977 */
LL_RCC_IsEnabledRTC(void)2978 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
2979 {
2980 return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
2981 }
2982
2983 /**
2984 * @brief Force the Backup domain reset
2985 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
2986 * @retval None
2987 */
LL_RCC_ForceBackupDomainReset(void)2988 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
2989 {
2990 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
2991 }
2992
2993 /**
2994 * @brief Release the Backup domain reset
2995 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
2996 * @retval None
2997 */
LL_RCC_ReleaseBackupDomainReset(void)2998 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
2999 {
3000 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
3001 }
3002
3003 /**
3004 * @brief Set HSE Prescalers for RTC Clock
3005 * @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler
3006 * @param Prescaler This parameter can be one of the following values:
3007 * @arg @ref LL_RCC_RTC_NOCLOCK
3008 * @arg @ref LL_RCC_RTC_HSE_DIV_2
3009 * @arg @ref LL_RCC_RTC_HSE_DIV_3
3010 * @arg @ref LL_RCC_RTC_HSE_DIV_4
3011 * @arg @ref LL_RCC_RTC_HSE_DIV_5
3012 * @arg @ref LL_RCC_RTC_HSE_DIV_6
3013 * @arg @ref LL_RCC_RTC_HSE_DIV_7
3014 * @arg @ref LL_RCC_RTC_HSE_DIV_8
3015 * @arg @ref LL_RCC_RTC_HSE_DIV_9
3016 * @arg @ref LL_RCC_RTC_HSE_DIV_10
3017 * @arg @ref LL_RCC_RTC_HSE_DIV_11
3018 * @arg @ref LL_RCC_RTC_HSE_DIV_12
3019 * @arg @ref LL_RCC_RTC_HSE_DIV_13
3020 * @arg @ref LL_RCC_RTC_HSE_DIV_14
3021 * @arg @ref LL_RCC_RTC_HSE_DIV_15
3022 * @arg @ref LL_RCC_RTC_HSE_DIV_16
3023 * @arg @ref LL_RCC_RTC_HSE_DIV_17
3024 * @arg @ref LL_RCC_RTC_HSE_DIV_18
3025 * @arg @ref LL_RCC_RTC_HSE_DIV_19
3026 * @arg @ref LL_RCC_RTC_HSE_DIV_20
3027 * @arg @ref LL_RCC_RTC_HSE_DIV_21
3028 * @arg @ref LL_RCC_RTC_HSE_DIV_22
3029 * @arg @ref LL_RCC_RTC_HSE_DIV_23
3030 * @arg @ref LL_RCC_RTC_HSE_DIV_24
3031 * @arg @ref LL_RCC_RTC_HSE_DIV_25
3032 * @arg @ref LL_RCC_RTC_HSE_DIV_26
3033 * @arg @ref LL_RCC_RTC_HSE_DIV_27
3034 * @arg @ref LL_RCC_RTC_HSE_DIV_28
3035 * @arg @ref LL_RCC_RTC_HSE_DIV_29
3036 * @arg @ref LL_RCC_RTC_HSE_DIV_30
3037 * @arg @ref LL_RCC_RTC_HSE_DIV_31
3038 * @retval None
3039 */
LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)3040 __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
3041 {
3042 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
3043 }
3044
3045 /**
3046 * @brief Get HSE Prescalers for RTC Clock
3047 * @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler
3048 * @retval Returned value can be one of the following values:
3049 * @arg @ref LL_RCC_RTC_NOCLOCK
3050 * @arg @ref LL_RCC_RTC_HSE_DIV_2
3051 * @arg @ref LL_RCC_RTC_HSE_DIV_3
3052 * @arg @ref LL_RCC_RTC_HSE_DIV_4
3053 * @arg @ref LL_RCC_RTC_HSE_DIV_5
3054 * @arg @ref LL_RCC_RTC_HSE_DIV_6
3055 * @arg @ref LL_RCC_RTC_HSE_DIV_7
3056 * @arg @ref LL_RCC_RTC_HSE_DIV_8
3057 * @arg @ref LL_RCC_RTC_HSE_DIV_9
3058 * @arg @ref LL_RCC_RTC_HSE_DIV_10
3059 * @arg @ref LL_RCC_RTC_HSE_DIV_11
3060 * @arg @ref LL_RCC_RTC_HSE_DIV_12
3061 * @arg @ref LL_RCC_RTC_HSE_DIV_13
3062 * @arg @ref LL_RCC_RTC_HSE_DIV_14
3063 * @arg @ref LL_RCC_RTC_HSE_DIV_15
3064 * @arg @ref LL_RCC_RTC_HSE_DIV_16
3065 * @arg @ref LL_RCC_RTC_HSE_DIV_17
3066 * @arg @ref LL_RCC_RTC_HSE_DIV_18
3067 * @arg @ref LL_RCC_RTC_HSE_DIV_19
3068 * @arg @ref LL_RCC_RTC_HSE_DIV_20
3069 * @arg @ref LL_RCC_RTC_HSE_DIV_21
3070 * @arg @ref LL_RCC_RTC_HSE_DIV_22
3071 * @arg @ref LL_RCC_RTC_HSE_DIV_23
3072 * @arg @ref LL_RCC_RTC_HSE_DIV_24
3073 * @arg @ref LL_RCC_RTC_HSE_DIV_25
3074 * @arg @ref LL_RCC_RTC_HSE_DIV_26
3075 * @arg @ref LL_RCC_RTC_HSE_DIV_27
3076 * @arg @ref LL_RCC_RTC_HSE_DIV_28
3077 * @arg @ref LL_RCC_RTC_HSE_DIV_29
3078 * @arg @ref LL_RCC_RTC_HSE_DIV_30
3079 * @arg @ref LL_RCC_RTC_HSE_DIV_31
3080 */
LL_RCC_GetRTC_HSEPrescaler(void)3081 __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
3082 {
3083 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
3084 }
3085
3086 /**
3087 * @}
3088 */
3089
3090 /** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
3091 * @{
3092 */
3093
3094 /**
3095 * @brief Set Timers Clock Prescalers
3096 * @rmtoll DCKCFGR1 TIMPRE LL_RCC_SetTIMPrescaler
3097 * @param Prescaler This parameter can be one of the following values:
3098 * @arg @ref LL_RCC_TIM_PRESCALER_TWICE
3099 * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
3100 * @retval None
3101 */
LL_RCC_SetTIMPrescaler(uint32_t Prescaler)3102 __STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
3103 {
3104 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_TIMPRE, Prescaler);
3105 }
3106
3107 /**
3108 * @brief Get Timers Clock Prescalers
3109 * @rmtoll DCKCFGR1 TIMPRE LL_RCC_GetTIMPrescaler
3110 * @retval Returned value can be one of the following values:
3111 * @arg @ref LL_RCC_TIM_PRESCALER_TWICE
3112 * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
3113 */
LL_RCC_GetTIMPrescaler(void)3114 __STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
3115 {
3116 return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_TIMPRE));
3117 }
3118
3119 /**
3120 * @}
3121 */
3122
3123 /** @defgroup RCC_LL_EF_PLL PLL
3124 * @{
3125 */
3126
3127 /**
3128 * @brief Enable PLL
3129 * @rmtoll CR PLLON LL_RCC_PLL_Enable
3130 * @retval None
3131 */
LL_RCC_PLL_Enable(void)3132 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
3133 {
3134 SET_BIT(RCC->CR, RCC_CR_PLLON);
3135 }
3136
3137 /**
3138 * @brief Disable PLL
3139 * @note Cannot be disabled if the PLL clock is used as the system clock
3140 * @rmtoll CR PLLON LL_RCC_PLL_Disable
3141 * @retval None
3142 */
LL_RCC_PLL_Disable(void)3143 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
3144 {
3145 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
3146 }
3147
3148 /**
3149 * @brief Check if PLL Ready
3150 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
3151 * @retval State of bit (1 or 0).
3152 */
LL_RCC_PLL_IsReady(void)3153 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
3154 {
3155 return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
3156 }
3157
3158 /**
3159 * @brief Configure PLL used for SYSCLK Domain
3160 * @note PLL Source and PLLM Divider can be written only when PLL,
3161 * PLLI2S and PLLSAI are disabled
3162 * @note PLLN/PLLP can be written only when PLL is disabled
3163 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
3164 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
3165 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
3166 * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS
3167 * @param Source This parameter can be one of the following values:
3168 * @arg @ref LL_RCC_PLLSOURCE_HSI
3169 * @arg @ref LL_RCC_PLLSOURCE_HSE
3170 * @param PLLM This parameter can be one of the following values:
3171 * @arg @ref LL_RCC_PLLM_DIV_2
3172 * @arg @ref LL_RCC_PLLM_DIV_3
3173 * @arg @ref LL_RCC_PLLM_DIV_4
3174 * @arg @ref LL_RCC_PLLM_DIV_5
3175 * @arg @ref LL_RCC_PLLM_DIV_6
3176 * @arg @ref LL_RCC_PLLM_DIV_7
3177 * @arg @ref LL_RCC_PLLM_DIV_8
3178 * @arg @ref LL_RCC_PLLM_DIV_9
3179 * @arg @ref LL_RCC_PLLM_DIV_10
3180 * @arg @ref LL_RCC_PLLM_DIV_11
3181 * @arg @ref LL_RCC_PLLM_DIV_12
3182 * @arg @ref LL_RCC_PLLM_DIV_13
3183 * @arg @ref LL_RCC_PLLM_DIV_14
3184 * @arg @ref LL_RCC_PLLM_DIV_15
3185 * @arg @ref LL_RCC_PLLM_DIV_16
3186 * @arg @ref LL_RCC_PLLM_DIV_17
3187 * @arg @ref LL_RCC_PLLM_DIV_18
3188 * @arg @ref LL_RCC_PLLM_DIV_19
3189 * @arg @ref LL_RCC_PLLM_DIV_20
3190 * @arg @ref LL_RCC_PLLM_DIV_21
3191 * @arg @ref LL_RCC_PLLM_DIV_22
3192 * @arg @ref LL_RCC_PLLM_DIV_23
3193 * @arg @ref LL_RCC_PLLM_DIV_24
3194 * @arg @ref LL_RCC_PLLM_DIV_25
3195 * @arg @ref LL_RCC_PLLM_DIV_26
3196 * @arg @ref LL_RCC_PLLM_DIV_27
3197 * @arg @ref LL_RCC_PLLM_DIV_28
3198 * @arg @ref LL_RCC_PLLM_DIV_29
3199 * @arg @ref LL_RCC_PLLM_DIV_30
3200 * @arg @ref LL_RCC_PLLM_DIV_31
3201 * @arg @ref LL_RCC_PLLM_DIV_32
3202 * @arg @ref LL_RCC_PLLM_DIV_33
3203 * @arg @ref LL_RCC_PLLM_DIV_34
3204 * @arg @ref LL_RCC_PLLM_DIV_35
3205 * @arg @ref LL_RCC_PLLM_DIV_36
3206 * @arg @ref LL_RCC_PLLM_DIV_37
3207 * @arg @ref LL_RCC_PLLM_DIV_38
3208 * @arg @ref LL_RCC_PLLM_DIV_39
3209 * @arg @ref LL_RCC_PLLM_DIV_40
3210 * @arg @ref LL_RCC_PLLM_DIV_41
3211 * @arg @ref LL_RCC_PLLM_DIV_42
3212 * @arg @ref LL_RCC_PLLM_DIV_43
3213 * @arg @ref LL_RCC_PLLM_DIV_44
3214 * @arg @ref LL_RCC_PLLM_DIV_45
3215 * @arg @ref LL_RCC_PLLM_DIV_46
3216 * @arg @ref LL_RCC_PLLM_DIV_47
3217 * @arg @ref LL_RCC_PLLM_DIV_48
3218 * @arg @ref LL_RCC_PLLM_DIV_49
3219 * @arg @ref LL_RCC_PLLM_DIV_50
3220 * @arg @ref LL_RCC_PLLM_DIV_51
3221 * @arg @ref LL_RCC_PLLM_DIV_52
3222 * @arg @ref LL_RCC_PLLM_DIV_53
3223 * @arg @ref LL_RCC_PLLM_DIV_54
3224 * @arg @ref LL_RCC_PLLM_DIV_55
3225 * @arg @ref LL_RCC_PLLM_DIV_56
3226 * @arg @ref LL_RCC_PLLM_DIV_57
3227 * @arg @ref LL_RCC_PLLM_DIV_58
3228 * @arg @ref LL_RCC_PLLM_DIV_59
3229 * @arg @ref LL_RCC_PLLM_DIV_60
3230 * @arg @ref LL_RCC_PLLM_DIV_61
3231 * @arg @ref LL_RCC_PLLM_DIV_62
3232 * @arg @ref LL_RCC_PLLM_DIV_63
3233 * @param PLLN Between 50 and 432
3234 * @param PLLP This parameter can be one of the following values:
3235 * @arg @ref LL_RCC_PLLP_DIV_2
3236 * @arg @ref LL_RCC_PLLP_DIV_4
3237 * @arg @ref LL_RCC_PLLP_DIV_6
3238 * @arg @ref LL_RCC_PLLP_DIV_8
3239 * @retval None
3240 */
LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)3241 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
3242 {
3243 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
3244 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP);
3245 }
3246
3247 /**
3248 * @brief Configure PLL used for 48Mhz domain clock
3249 * @note PLL Source and PLLM Divider can be written only when PLL,
3250 * PLLI2S and PLLSAI are disabled
3251 * @note PLLN/PLLQ can be written only when PLL is disabled
3252 * @note This can be selected for USB, RNG, SDMMC1
3253 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
3254 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
3255 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
3256 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
3257 * @param Source This parameter can be one of the following values:
3258 * @arg @ref LL_RCC_PLLSOURCE_HSI
3259 * @arg @ref LL_RCC_PLLSOURCE_HSE
3260 * @param PLLM This parameter can be one of the following values:
3261 * @arg @ref LL_RCC_PLLM_DIV_2
3262 * @arg @ref LL_RCC_PLLM_DIV_3
3263 * @arg @ref LL_RCC_PLLM_DIV_4
3264 * @arg @ref LL_RCC_PLLM_DIV_5
3265 * @arg @ref LL_RCC_PLLM_DIV_6
3266 * @arg @ref LL_RCC_PLLM_DIV_7
3267 * @arg @ref LL_RCC_PLLM_DIV_8
3268 * @arg @ref LL_RCC_PLLM_DIV_9
3269 * @arg @ref LL_RCC_PLLM_DIV_10
3270 * @arg @ref LL_RCC_PLLM_DIV_11
3271 * @arg @ref LL_RCC_PLLM_DIV_12
3272 * @arg @ref LL_RCC_PLLM_DIV_13
3273 * @arg @ref LL_RCC_PLLM_DIV_14
3274 * @arg @ref LL_RCC_PLLM_DIV_15
3275 * @arg @ref LL_RCC_PLLM_DIV_16
3276 * @arg @ref LL_RCC_PLLM_DIV_17
3277 * @arg @ref LL_RCC_PLLM_DIV_18
3278 * @arg @ref LL_RCC_PLLM_DIV_19
3279 * @arg @ref LL_RCC_PLLM_DIV_20
3280 * @arg @ref LL_RCC_PLLM_DIV_21
3281 * @arg @ref LL_RCC_PLLM_DIV_22
3282 * @arg @ref LL_RCC_PLLM_DIV_23
3283 * @arg @ref LL_RCC_PLLM_DIV_24
3284 * @arg @ref LL_RCC_PLLM_DIV_25
3285 * @arg @ref LL_RCC_PLLM_DIV_26
3286 * @arg @ref LL_RCC_PLLM_DIV_27
3287 * @arg @ref LL_RCC_PLLM_DIV_28
3288 * @arg @ref LL_RCC_PLLM_DIV_29
3289 * @arg @ref LL_RCC_PLLM_DIV_30
3290 * @arg @ref LL_RCC_PLLM_DIV_31
3291 * @arg @ref LL_RCC_PLLM_DIV_32
3292 * @arg @ref LL_RCC_PLLM_DIV_33
3293 * @arg @ref LL_RCC_PLLM_DIV_34
3294 * @arg @ref LL_RCC_PLLM_DIV_35
3295 * @arg @ref LL_RCC_PLLM_DIV_36
3296 * @arg @ref LL_RCC_PLLM_DIV_37
3297 * @arg @ref LL_RCC_PLLM_DIV_38
3298 * @arg @ref LL_RCC_PLLM_DIV_39
3299 * @arg @ref LL_RCC_PLLM_DIV_40
3300 * @arg @ref LL_RCC_PLLM_DIV_41
3301 * @arg @ref LL_RCC_PLLM_DIV_42
3302 * @arg @ref LL_RCC_PLLM_DIV_43
3303 * @arg @ref LL_RCC_PLLM_DIV_44
3304 * @arg @ref LL_RCC_PLLM_DIV_45
3305 * @arg @ref LL_RCC_PLLM_DIV_46
3306 * @arg @ref LL_RCC_PLLM_DIV_47
3307 * @arg @ref LL_RCC_PLLM_DIV_48
3308 * @arg @ref LL_RCC_PLLM_DIV_49
3309 * @arg @ref LL_RCC_PLLM_DIV_50
3310 * @arg @ref LL_RCC_PLLM_DIV_51
3311 * @arg @ref LL_RCC_PLLM_DIV_52
3312 * @arg @ref LL_RCC_PLLM_DIV_53
3313 * @arg @ref LL_RCC_PLLM_DIV_54
3314 * @arg @ref LL_RCC_PLLM_DIV_55
3315 * @arg @ref LL_RCC_PLLM_DIV_56
3316 * @arg @ref LL_RCC_PLLM_DIV_57
3317 * @arg @ref LL_RCC_PLLM_DIV_58
3318 * @arg @ref LL_RCC_PLLM_DIV_59
3319 * @arg @ref LL_RCC_PLLM_DIV_60
3320 * @arg @ref LL_RCC_PLLM_DIV_61
3321 * @arg @ref LL_RCC_PLLM_DIV_62
3322 * @arg @ref LL_RCC_PLLM_DIV_63
3323 * @param PLLN Between 50 and 432
3324 * @param PLLQ This parameter can be one of the following values:
3325 * @arg @ref LL_RCC_PLLQ_DIV_2
3326 * @arg @ref LL_RCC_PLLQ_DIV_3
3327 * @arg @ref LL_RCC_PLLQ_DIV_4
3328 * @arg @ref LL_RCC_PLLQ_DIV_5
3329 * @arg @ref LL_RCC_PLLQ_DIV_6
3330 * @arg @ref LL_RCC_PLLQ_DIV_7
3331 * @arg @ref LL_RCC_PLLQ_DIV_8
3332 * @arg @ref LL_RCC_PLLQ_DIV_9
3333 * @arg @ref LL_RCC_PLLQ_DIV_10
3334 * @arg @ref LL_RCC_PLLQ_DIV_11
3335 * @arg @ref LL_RCC_PLLQ_DIV_12
3336 * @arg @ref LL_RCC_PLLQ_DIV_13
3337 * @arg @ref LL_RCC_PLLQ_DIV_14
3338 * @arg @ref LL_RCC_PLLQ_DIV_15
3339 * @retval None
3340 */
LL_RCC_PLL_ConfigDomain_48M(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)3341 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
3342 {
3343 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
3344 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ);
3345 }
3346
3347 #if defined(DSI)
3348 /**
3349 * @brief Configure PLL used for DSI clock
3350 * @note PLL Source and PLLM Divider can be written only when PLL,
3351 * PLLI2S and PLLSAI are disabled
3352 * @note PLLN/PLLR can be written only when PLL is disabled
3353 * @note This can be selected for DSI
3354 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_DSI\n
3355 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_DSI\n
3356 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_DSI\n
3357 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_DSI
3358 * @param Source This parameter can be one of the following values:
3359 * @arg @ref LL_RCC_PLLSOURCE_HSI
3360 * @arg @ref LL_RCC_PLLSOURCE_HSE
3361 * @param PLLM This parameter can be one of the following values:
3362 * @arg @ref LL_RCC_PLLM_DIV_2
3363 * @arg @ref LL_RCC_PLLM_DIV_3
3364 * @arg @ref LL_RCC_PLLM_DIV_4
3365 * @arg @ref LL_RCC_PLLM_DIV_5
3366 * @arg @ref LL_RCC_PLLM_DIV_6
3367 * @arg @ref LL_RCC_PLLM_DIV_7
3368 * @arg @ref LL_RCC_PLLM_DIV_8
3369 * @arg @ref LL_RCC_PLLM_DIV_9
3370 * @arg @ref LL_RCC_PLLM_DIV_10
3371 * @arg @ref LL_RCC_PLLM_DIV_11
3372 * @arg @ref LL_RCC_PLLM_DIV_12
3373 * @arg @ref LL_RCC_PLLM_DIV_13
3374 * @arg @ref LL_RCC_PLLM_DIV_14
3375 * @arg @ref LL_RCC_PLLM_DIV_15
3376 * @arg @ref LL_RCC_PLLM_DIV_16
3377 * @arg @ref LL_RCC_PLLM_DIV_17
3378 * @arg @ref LL_RCC_PLLM_DIV_18
3379 * @arg @ref LL_RCC_PLLM_DIV_19
3380 * @arg @ref LL_RCC_PLLM_DIV_20
3381 * @arg @ref LL_RCC_PLLM_DIV_21
3382 * @arg @ref LL_RCC_PLLM_DIV_22
3383 * @arg @ref LL_RCC_PLLM_DIV_23
3384 * @arg @ref LL_RCC_PLLM_DIV_24
3385 * @arg @ref LL_RCC_PLLM_DIV_25
3386 * @arg @ref LL_RCC_PLLM_DIV_26
3387 * @arg @ref LL_RCC_PLLM_DIV_27
3388 * @arg @ref LL_RCC_PLLM_DIV_28
3389 * @arg @ref LL_RCC_PLLM_DIV_29
3390 * @arg @ref LL_RCC_PLLM_DIV_30
3391 * @arg @ref LL_RCC_PLLM_DIV_31
3392 * @arg @ref LL_RCC_PLLM_DIV_32
3393 * @arg @ref LL_RCC_PLLM_DIV_33
3394 * @arg @ref LL_RCC_PLLM_DIV_34
3395 * @arg @ref LL_RCC_PLLM_DIV_35
3396 * @arg @ref LL_RCC_PLLM_DIV_36
3397 * @arg @ref LL_RCC_PLLM_DIV_37
3398 * @arg @ref LL_RCC_PLLM_DIV_38
3399 * @arg @ref LL_RCC_PLLM_DIV_39
3400 * @arg @ref LL_RCC_PLLM_DIV_40
3401 * @arg @ref LL_RCC_PLLM_DIV_41
3402 * @arg @ref LL_RCC_PLLM_DIV_42
3403 * @arg @ref LL_RCC_PLLM_DIV_43
3404 * @arg @ref LL_RCC_PLLM_DIV_44
3405 * @arg @ref LL_RCC_PLLM_DIV_45
3406 * @arg @ref LL_RCC_PLLM_DIV_46
3407 * @arg @ref LL_RCC_PLLM_DIV_47
3408 * @arg @ref LL_RCC_PLLM_DIV_48
3409 * @arg @ref LL_RCC_PLLM_DIV_49
3410 * @arg @ref LL_RCC_PLLM_DIV_50
3411 * @arg @ref LL_RCC_PLLM_DIV_51
3412 * @arg @ref LL_RCC_PLLM_DIV_52
3413 * @arg @ref LL_RCC_PLLM_DIV_53
3414 * @arg @ref LL_RCC_PLLM_DIV_54
3415 * @arg @ref LL_RCC_PLLM_DIV_55
3416 * @arg @ref LL_RCC_PLLM_DIV_56
3417 * @arg @ref LL_RCC_PLLM_DIV_57
3418 * @arg @ref LL_RCC_PLLM_DIV_58
3419 * @arg @ref LL_RCC_PLLM_DIV_59
3420 * @arg @ref LL_RCC_PLLM_DIV_60
3421 * @arg @ref LL_RCC_PLLM_DIV_61
3422 * @arg @ref LL_RCC_PLLM_DIV_62
3423 * @arg @ref LL_RCC_PLLM_DIV_63
3424 * @param PLLN Between 50 and 432
3425 * @param PLLR This parameter can be one of the following values:
3426 * @arg @ref LL_RCC_PLLR_DIV_2
3427 * @arg @ref LL_RCC_PLLR_DIV_3
3428 * @arg @ref LL_RCC_PLLR_DIV_4
3429 * @arg @ref LL_RCC_PLLR_DIV_5
3430 * @arg @ref LL_RCC_PLLR_DIV_6
3431 * @arg @ref LL_RCC_PLLR_DIV_7
3432 * @retval None
3433 */
LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)3434 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
3435 {
3436 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
3437 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
3438 }
3439 #endif /* DSI */
3440
3441 /**
3442 * @brief Configure PLL clock source
3443 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
3444 * @param PLLSource This parameter can be one of the following values:
3445 * @arg @ref LL_RCC_PLLSOURCE_HSI
3446 * @arg @ref LL_RCC_PLLSOURCE_HSE
3447 * @retval None
3448 */
LL_RCC_PLL_SetMainSource(uint32_t PLLSource)3449 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
3450 {
3451 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
3452 }
3453
3454 /**
3455 * @brief Get the oscillator used as PLL clock source.
3456 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
3457 * @retval Returned value can be one of the following values:
3458 * @arg @ref LL_RCC_PLLSOURCE_HSI
3459 * @arg @ref LL_RCC_PLLSOURCE_HSE
3460 */
LL_RCC_PLL_GetMainSource(void)3461 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
3462 {
3463 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
3464 }
3465
3466 /**
3467 * @brief Get Main PLL multiplication factor for VCO
3468 * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
3469 * @retval Between 50 and 432
3470 */
LL_RCC_PLL_GetN(void)3471 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
3472 {
3473 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
3474 }
3475
3476 /**
3477 * @brief Get Main PLL division factor for PLLP
3478 * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
3479 * @retval Returned value can be one of the following values:
3480 * @arg @ref LL_RCC_PLLP_DIV_2
3481 * @arg @ref LL_RCC_PLLP_DIV_4
3482 * @arg @ref LL_RCC_PLLP_DIV_6
3483 * @arg @ref LL_RCC_PLLP_DIV_8
3484 */
LL_RCC_PLL_GetP(void)3485 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
3486 {
3487 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
3488 }
3489
3490 /**
3491 * @brief Get Main PLL division factor for PLLQ
3492 * @note used for PLL48MCLK selected for USB, RNG, SDMMC (48 MHz clock)
3493 * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
3494 * @retval Returned value can be one of the following values:
3495 * @arg @ref LL_RCC_PLLQ_DIV_2
3496 * @arg @ref LL_RCC_PLLQ_DIV_3
3497 * @arg @ref LL_RCC_PLLQ_DIV_4
3498 * @arg @ref LL_RCC_PLLQ_DIV_5
3499 * @arg @ref LL_RCC_PLLQ_DIV_6
3500 * @arg @ref LL_RCC_PLLQ_DIV_7
3501 * @arg @ref LL_RCC_PLLQ_DIV_8
3502 * @arg @ref LL_RCC_PLLQ_DIV_9
3503 * @arg @ref LL_RCC_PLLQ_DIV_10
3504 * @arg @ref LL_RCC_PLLQ_DIV_11
3505 * @arg @ref LL_RCC_PLLQ_DIV_12
3506 * @arg @ref LL_RCC_PLLQ_DIV_13
3507 * @arg @ref LL_RCC_PLLQ_DIV_14
3508 * @arg @ref LL_RCC_PLLQ_DIV_15
3509 */
LL_RCC_PLL_GetQ(void)3510 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
3511 {
3512 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
3513 }
3514
3515 #if defined(RCC_PLLCFGR_PLLR)
3516 /**
3517 * @brief Get Main PLL division factor for PLLR
3518 * @note used for PLLCLK (system clock)
3519 * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
3520 * @retval Returned value can be one of the following values:
3521 * @arg @ref LL_RCC_PLLR_DIV_2
3522 * @arg @ref LL_RCC_PLLR_DIV_3
3523 * @arg @ref LL_RCC_PLLR_DIV_4
3524 * @arg @ref LL_RCC_PLLR_DIV_5
3525 * @arg @ref LL_RCC_PLLR_DIV_6
3526 * @arg @ref LL_RCC_PLLR_DIV_7
3527 */
LL_RCC_PLL_GetR(void)3528 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
3529 {
3530 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
3531 }
3532 #endif /* RCC_PLLCFGR_PLLR */
3533
3534 /**
3535 * @brief Get Division factor for the main PLL and other PLL
3536 * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
3537 * @retval Returned value can be one of the following values:
3538 * @arg @ref LL_RCC_PLLM_DIV_2
3539 * @arg @ref LL_RCC_PLLM_DIV_3
3540 * @arg @ref LL_RCC_PLLM_DIV_4
3541 * @arg @ref LL_RCC_PLLM_DIV_5
3542 * @arg @ref LL_RCC_PLLM_DIV_6
3543 * @arg @ref LL_RCC_PLLM_DIV_7
3544 * @arg @ref LL_RCC_PLLM_DIV_8
3545 * @arg @ref LL_RCC_PLLM_DIV_9
3546 * @arg @ref LL_RCC_PLLM_DIV_10
3547 * @arg @ref LL_RCC_PLLM_DIV_11
3548 * @arg @ref LL_RCC_PLLM_DIV_12
3549 * @arg @ref LL_RCC_PLLM_DIV_13
3550 * @arg @ref LL_RCC_PLLM_DIV_14
3551 * @arg @ref LL_RCC_PLLM_DIV_15
3552 * @arg @ref LL_RCC_PLLM_DIV_16
3553 * @arg @ref LL_RCC_PLLM_DIV_17
3554 * @arg @ref LL_RCC_PLLM_DIV_18
3555 * @arg @ref LL_RCC_PLLM_DIV_19
3556 * @arg @ref LL_RCC_PLLM_DIV_20
3557 * @arg @ref LL_RCC_PLLM_DIV_21
3558 * @arg @ref LL_RCC_PLLM_DIV_22
3559 * @arg @ref LL_RCC_PLLM_DIV_23
3560 * @arg @ref LL_RCC_PLLM_DIV_24
3561 * @arg @ref LL_RCC_PLLM_DIV_25
3562 * @arg @ref LL_RCC_PLLM_DIV_26
3563 * @arg @ref LL_RCC_PLLM_DIV_27
3564 * @arg @ref LL_RCC_PLLM_DIV_28
3565 * @arg @ref LL_RCC_PLLM_DIV_29
3566 * @arg @ref LL_RCC_PLLM_DIV_30
3567 * @arg @ref LL_RCC_PLLM_DIV_31
3568 * @arg @ref LL_RCC_PLLM_DIV_32
3569 * @arg @ref LL_RCC_PLLM_DIV_33
3570 * @arg @ref LL_RCC_PLLM_DIV_34
3571 * @arg @ref LL_RCC_PLLM_DIV_35
3572 * @arg @ref LL_RCC_PLLM_DIV_36
3573 * @arg @ref LL_RCC_PLLM_DIV_37
3574 * @arg @ref LL_RCC_PLLM_DIV_38
3575 * @arg @ref LL_RCC_PLLM_DIV_39
3576 * @arg @ref LL_RCC_PLLM_DIV_40
3577 * @arg @ref LL_RCC_PLLM_DIV_41
3578 * @arg @ref LL_RCC_PLLM_DIV_42
3579 * @arg @ref LL_RCC_PLLM_DIV_43
3580 * @arg @ref LL_RCC_PLLM_DIV_44
3581 * @arg @ref LL_RCC_PLLM_DIV_45
3582 * @arg @ref LL_RCC_PLLM_DIV_46
3583 * @arg @ref LL_RCC_PLLM_DIV_47
3584 * @arg @ref LL_RCC_PLLM_DIV_48
3585 * @arg @ref LL_RCC_PLLM_DIV_49
3586 * @arg @ref LL_RCC_PLLM_DIV_50
3587 * @arg @ref LL_RCC_PLLM_DIV_51
3588 * @arg @ref LL_RCC_PLLM_DIV_52
3589 * @arg @ref LL_RCC_PLLM_DIV_53
3590 * @arg @ref LL_RCC_PLLM_DIV_54
3591 * @arg @ref LL_RCC_PLLM_DIV_55
3592 * @arg @ref LL_RCC_PLLM_DIV_56
3593 * @arg @ref LL_RCC_PLLM_DIV_57
3594 * @arg @ref LL_RCC_PLLM_DIV_58
3595 * @arg @ref LL_RCC_PLLM_DIV_59
3596 * @arg @ref LL_RCC_PLLM_DIV_60
3597 * @arg @ref LL_RCC_PLLM_DIV_61
3598 * @arg @ref LL_RCC_PLLM_DIV_62
3599 * @arg @ref LL_RCC_PLLM_DIV_63
3600 */
LL_RCC_PLL_GetDivider(void)3601 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
3602 {
3603 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
3604 }
3605
3606 /**
3607 * @brief Configure Spread Spectrum used for PLL
3608 * @note These bits must be written before enabling PLL
3609 * @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum\n
3610 * SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum\n
3611 * SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum
3612 * @param Mod Between Min_Data=0 and Max_Data=8191
3613 * @param Inc Between Min_Data=0 and Max_Data=32767
3614 * @param Sel This parameter can be one of the following values:
3615 * @arg @ref LL_RCC_SPREAD_SELECT_CENTER
3616 * @arg @ref LL_RCC_SPREAD_SELECT_DOWN
3617 * @retval None
3618 */
LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod,uint32_t Inc,uint32_t Sel)3619 __STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel)
3620 {
3621 MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << RCC_SSCGR_INCSTEP_Pos) | Sel);
3622 }
3623
3624 /**
3625 * @brief Get Spread Spectrum Modulation Period for PLL
3626 * @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation
3627 * @retval Between Min_Data=0 and Max_Data=8191
3628 */
LL_RCC_PLL_GetPeriodModulation(void)3629 __STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void)
3630 {
3631 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER));
3632 }
3633
3634 /**
3635 * @brief Get Spread Spectrum Incrementation Step for PLL
3636 * @note Must be written before enabling PLL
3637 * @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation
3638 * @retval Between Min_Data=0 and Max_Data=32767
3639 */
LL_RCC_PLL_GetStepIncrementation(void)3640 __STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void)
3641 {
3642 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos);
3643 }
3644
3645 /**
3646 * @brief Get Spread Spectrum Selection for PLL
3647 * @note Must be written before enabling PLL
3648 * @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection
3649 * @retval Returned value can be one of the following values:
3650 * @arg @ref LL_RCC_SPREAD_SELECT_CENTER
3651 * @arg @ref LL_RCC_SPREAD_SELECT_DOWN
3652 */
LL_RCC_PLL_GetSpreadSelection(void)3653 __STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void)
3654 {
3655 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL));
3656 }
3657
3658 /**
3659 * @brief Enable Spread Spectrum for PLL.
3660 * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable
3661 * @retval None
3662 */
LL_RCC_PLL_SpreadSpectrum_Enable(void)3663 __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void)
3664 {
3665 SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
3666 }
3667
3668 /**
3669 * @brief Disable Spread Spectrum for PLL.
3670 * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable
3671 * @retval None
3672 */
LL_RCC_PLL_SpreadSpectrum_Disable(void)3673 __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void)
3674 {
3675 CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
3676 }
3677
3678 /**
3679 * @}
3680 */
3681
3682 /** @defgroup RCC_LL_EF_PLLI2S PLLI2S
3683 * @{
3684 */
3685
3686 /**
3687 * @brief Enable PLLI2S
3688 * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable
3689 * @retval None
3690 */
LL_RCC_PLLI2S_Enable(void)3691 __STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
3692 {
3693 SET_BIT(RCC->CR, RCC_CR_PLLI2SON);
3694 }
3695
3696 /**
3697 * @brief Disable PLLI2S
3698 * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable
3699 * @retval None
3700 */
LL_RCC_PLLI2S_Disable(void)3701 __STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
3702 {
3703 CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
3704 }
3705
3706 /**
3707 * @brief Check if PLLI2S Ready
3708 * @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady
3709 * @retval State of bit (1 or 0).
3710 */
LL_RCC_PLLI2S_IsReady(void)3711 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
3712 {
3713 return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY));
3714 }
3715
3716 /**
3717 * @brief Configure PLLI2S used for SAI1 and SAI2 domain clock
3718 * @note PLL Source and PLLM Divider can be written only when PLL,
3719 * PLLI2S and PLLSAI are disabled
3720 * @note PLLN/PLLQ can be written only when PLLI2S is disabled
3721 * @note This can be selected for SAI1 and SAI2
3722 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n
3723 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SAI\n
3724 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SAI\n
3725 * PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_SAI\n
3726 * DCKCFGR1 PLLI2SDIVQ LL_RCC_PLLI2S_ConfigDomain_SAI
3727 * @param Source This parameter can be one of the following values:
3728 * @arg @ref LL_RCC_PLLSOURCE_HSI
3729 * @arg @ref LL_RCC_PLLSOURCE_HSE
3730 * @param PLLM This parameter can be one of the following values:
3731 * @arg @ref LL_RCC_PLLM_DIV_2
3732 * @arg @ref LL_RCC_PLLM_DIV_3
3733 * @arg @ref LL_RCC_PLLM_DIV_4
3734 * @arg @ref LL_RCC_PLLM_DIV_5
3735 * @arg @ref LL_RCC_PLLM_DIV_6
3736 * @arg @ref LL_RCC_PLLM_DIV_7
3737 * @arg @ref LL_RCC_PLLM_DIV_8
3738 * @arg @ref LL_RCC_PLLM_DIV_9
3739 * @arg @ref LL_RCC_PLLM_DIV_10
3740 * @arg @ref LL_RCC_PLLM_DIV_11
3741 * @arg @ref LL_RCC_PLLM_DIV_12
3742 * @arg @ref LL_RCC_PLLM_DIV_13
3743 * @arg @ref LL_RCC_PLLM_DIV_14
3744 * @arg @ref LL_RCC_PLLM_DIV_15
3745 * @arg @ref LL_RCC_PLLM_DIV_16
3746 * @arg @ref LL_RCC_PLLM_DIV_17
3747 * @arg @ref LL_RCC_PLLM_DIV_18
3748 * @arg @ref LL_RCC_PLLM_DIV_19
3749 * @arg @ref LL_RCC_PLLM_DIV_20
3750 * @arg @ref LL_RCC_PLLM_DIV_21
3751 * @arg @ref LL_RCC_PLLM_DIV_22
3752 * @arg @ref LL_RCC_PLLM_DIV_23
3753 * @arg @ref LL_RCC_PLLM_DIV_24
3754 * @arg @ref LL_RCC_PLLM_DIV_25
3755 * @arg @ref LL_RCC_PLLM_DIV_26
3756 * @arg @ref LL_RCC_PLLM_DIV_27
3757 * @arg @ref LL_RCC_PLLM_DIV_28
3758 * @arg @ref LL_RCC_PLLM_DIV_29
3759 * @arg @ref LL_RCC_PLLM_DIV_30
3760 * @arg @ref LL_RCC_PLLM_DIV_31
3761 * @arg @ref LL_RCC_PLLM_DIV_32
3762 * @arg @ref LL_RCC_PLLM_DIV_33
3763 * @arg @ref LL_RCC_PLLM_DIV_34
3764 * @arg @ref LL_RCC_PLLM_DIV_35
3765 * @arg @ref LL_RCC_PLLM_DIV_36
3766 * @arg @ref LL_RCC_PLLM_DIV_37
3767 * @arg @ref LL_RCC_PLLM_DIV_38
3768 * @arg @ref LL_RCC_PLLM_DIV_39
3769 * @arg @ref LL_RCC_PLLM_DIV_40
3770 * @arg @ref LL_RCC_PLLM_DIV_41
3771 * @arg @ref LL_RCC_PLLM_DIV_42
3772 * @arg @ref LL_RCC_PLLM_DIV_43
3773 * @arg @ref LL_RCC_PLLM_DIV_44
3774 * @arg @ref LL_RCC_PLLM_DIV_45
3775 * @arg @ref LL_RCC_PLLM_DIV_46
3776 * @arg @ref LL_RCC_PLLM_DIV_47
3777 * @arg @ref LL_RCC_PLLM_DIV_48
3778 * @arg @ref LL_RCC_PLLM_DIV_49
3779 * @arg @ref LL_RCC_PLLM_DIV_50
3780 * @arg @ref LL_RCC_PLLM_DIV_51
3781 * @arg @ref LL_RCC_PLLM_DIV_52
3782 * @arg @ref LL_RCC_PLLM_DIV_53
3783 * @arg @ref LL_RCC_PLLM_DIV_54
3784 * @arg @ref LL_RCC_PLLM_DIV_55
3785 * @arg @ref LL_RCC_PLLM_DIV_56
3786 * @arg @ref LL_RCC_PLLM_DIV_57
3787 * @arg @ref LL_RCC_PLLM_DIV_58
3788 * @arg @ref LL_RCC_PLLM_DIV_59
3789 * @arg @ref LL_RCC_PLLM_DIV_60
3790 * @arg @ref LL_RCC_PLLM_DIV_61
3791 * @arg @ref LL_RCC_PLLM_DIV_62
3792 * @arg @ref LL_RCC_PLLM_DIV_63
3793 * @param PLLN Between 50 and 432
3794 * @param PLLQ This parameter can be one of the following values:
3795 * @arg @ref LL_RCC_PLLI2SQ_DIV_2
3796 * @arg @ref LL_RCC_PLLI2SQ_DIV_3
3797 * @arg @ref LL_RCC_PLLI2SQ_DIV_4
3798 * @arg @ref LL_RCC_PLLI2SQ_DIV_5
3799 * @arg @ref LL_RCC_PLLI2SQ_DIV_6
3800 * @arg @ref LL_RCC_PLLI2SQ_DIV_7
3801 * @arg @ref LL_RCC_PLLI2SQ_DIV_8
3802 * @arg @ref LL_RCC_PLLI2SQ_DIV_9
3803 * @arg @ref LL_RCC_PLLI2SQ_DIV_10
3804 * @arg @ref LL_RCC_PLLI2SQ_DIV_11
3805 * @arg @ref LL_RCC_PLLI2SQ_DIV_12
3806 * @arg @ref LL_RCC_PLLI2SQ_DIV_13
3807 * @arg @ref LL_RCC_PLLI2SQ_DIV_14
3808 * @arg @ref LL_RCC_PLLI2SQ_DIV_15
3809 * @param PLLDIVQ This parameter can be one of the following values:
3810 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
3811 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
3812 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
3813 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
3814 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
3815 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
3816 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
3817 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
3818 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
3819 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
3820 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
3821 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
3822 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
3823 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
3824 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
3825 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
3826 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
3827 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
3828 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
3829 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
3830 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
3831 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
3832 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
3833 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
3834 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
3835 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
3836 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
3837 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
3838 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
3839 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
3840 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
3841 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
3842 * @retval None
3843 */
LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ,uint32_t PLLDIVQ)3844 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ)
3845 {
3846 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
3847 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLQ);
3848 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, PLLDIVQ);
3849 }
3850
3851 #if defined(SPDIFRX)
3852 /**
3853 * @brief Configure PLLI2S used for SPDIFRX domain clock
3854 * @note PLL Source and PLLM Divider can be written only when PLL,
3855 * PLLI2S and PLLSAI are disabled
3856 * @note PLLN/PLLP can be written only when PLLI2S is disabled
3857 * @note This can be selected for SPDIFRX
3858 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
3859 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
3860 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
3861 * PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_ConfigDomain_SPDIFRX
3862 * @param Source This parameter can be one of the following values:
3863 * @arg @ref LL_RCC_PLLSOURCE_HSI
3864 * @arg @ref LL_RCC_PLLSOURCE_HSE
3865 * @param PLLM This parameter can be one of the following values:
3866 * @arg @ref LL_RCC_PLLM_DIV_2
3867 * @arg @ref LL_RCC_PLLM_DIV_3
3868 * @arg @ref LL_RCC_PLLM_DIV_4
3869 * @arg @ref LL_RCC_PLLM_DIV_5
3870 * @arg @ref LL_RCC_PLLM_DIV_6
3871 * @arg @ref LL_RCC_PLLM_DIV_7
3872 * @arg @ref LL_RCC_PLLM_DIV_8
3873 * @arg @ref LL_RCC_PLLM_DIV_9
3874 * @arg @ref LL_RCC_PLLM_DIV_10
3875 * @arg @ref LL_RCC_PLLM_DIV_11
3876 * @arg @ref LL_RCC_PLLM_DIV_12
3877 * @arg @ref LL_RCC_PLLM_DIV_13
3878 * @arg @ref LL_RCC_PLLM_DIV_14
3879 * @arg @ref LL_RCC_PLLM_DIV_15
3880 * @arg @ref LL_RCC_PLLM_DIV_16
3881 * @arg @ref LL_RCC_PLLM_DIV_17
3882 * @arg @ref LL_RCC_PLLM_DIV_18
3883 * @arg @ref LL_RCC_PLLM_DIV_19
3884 * @arg @ref LL_RCC_PLLM_DIV_20
3885 * @arg @ref LL_RCC_PLLM_DIV_21
3886 * @arg @ref LL_RCC_PLLM_DIV_22
3887 * @arg @ref LL_RCC_PLLM_DIV_23
3888 * @arg @ref LL_RCC_PLLM_DIV_24
3889 * @arg @ref LL_RCC_PLLM_DIV_25
3890 * @arg @ref LL_RCC_PLLM_DIV_26
3891 * @arg @ref LL_RCC_PLLM_DIV_27
3892 * @arg @ref LL_RCC_PLLM_DIV_28
3893 * @arg @ref LL_RCC_PLLM_DIV_29
3894 * @arg @ref LL_RCC_PLLM_DIV_30
3895 * @arg @ref LL_RCC_PLLM_DIV_31
3896 * @arg @ref LL_RCC_PLLM_DIV_32
3897 * @arg @ref LL_RCC_PLLM_DIV_33
3898 * @arg @ref LL_RCC_PLLM_DIV_34
3899 * @arg @ref LL_RCC_PLLM_DIV_35
3900 * @arg @ref LL_RCC_PLLM_DIV_36
3901 * @arg @ref LL_RCC_PLLM_DIV_37
3902 * @arg @ref LL_RCC_PLLM_DIV_38
3903 * @arg @ref LL_RCC_PLLM_DIV_39
3904 * @arg @ref LL_RCC_PLLM_DIV_40
3905 * @arg @ref LL_RCC_PLLM_DIV_41
3906 * @arg @ref LL_RCC_PLLM_DIV_42
3907 * @arg @ref LL_RCC_PLLM_DIV_43
3908 * @arg @ref LL_RCC_PLLM_DIV_44
3909 * @arg @ref LL_RCC_PLLM_DIV_45
3910 * @arg @ref LL_RCC_PLLM_DIV_46
3911 * @arg @ref LL_RCC_PLLM_DIV_47
3912 * @arg @ref LL_RCC_PLLM_DIV_48
3913 * @arg @ref LL_RCC_PLLM_DIV_49
3914 * @arg @ref LL_RCC_PLLM_DIV_50
3915 * @arg @ref LL_RCC_PLLM_DIV_51
3916 * @arg @ref LL_RCC_PLLM_DIV_52
3917 * @arg @ref LL_RCC_PLLM_DIV_53
3918 * @arg @ref LL_RCC_PLLM_DIV_54
3919 * @arg @ref LL_RCC_PLLM_DIV_55
3920 * @arg @ref LL_RCC_PLLM_DIV_56
3921 * @arg @ref LL_RCC_PLLM_DIV_57
3922 * @arg @ref LL_RCC_PLLM_DIV_58
3923 * @arg @ref LL_RCC_PLLM_DIV_59
3924 * @arg @ref LL_RCC_PLLM_DIV_60
3925 * @arg @ref LL_RCC_PLLM_DIV_61
3926 * @arg @ref LL_RCC_PLLM_DIV_62
3927 * @arg @ref LL_RCC_PLLM_DIV_63
3928 * @param PLLN Between 50 and 432
3929 * @param PLLP This parameter can be one of the following values:
3930 * @arg @ref LL_RCC_PLLI2SP_DIV_2
3931 * @arg @ref LL_RCC_PLLI2SP_DIV_4
3932 * @arg @ref LL_RCC_PLLI2SP_DIV_6
3933 * @arg @ref LL_RCC_PLLI2SP_DIV_8
3934 * @retval None
3935 */
LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)3936 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
3937 {
3938 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
3939 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLP);
3940 }
3941 #endif /* SPDIFRX */
3942
3943 /**
3944 * @brief Configure PLLI2S used for I2S1 domain clock
3945 * @note PLL Source and PLLM Divider can be written only when PLL,
3946 * PLLI2S and PLLSAI are disabled
3947 * @note PLLN/PLLR can be written only when PLLI2S is disabled
3948 * @note This can be selected for I2S
3949 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n
3950 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S\n
3951 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S\n
3952 * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S
3953 * @param Source This parameter can be one of the following values:
3954 * @arg @ref LL_RCC_PLLSOURCE_HSI
3955 * @arg @ref LL_RCC_PLLSOURCE_HSE
3956 * @param PLLM This parameter can be one of the following values:
3957 * @arg @ref LL_RCC_PLLM_DIV_2
3958 * @arg @ref LL_RCC_PLLM_DIV_3
3959 * @arg @ref LL_RCC_PLLM_DIV_4
3960 * @arg @ref LL_RCC_PLLM_DIV_5
3961 * @arg @ref LL_RCC_PLLM_DIV_6
3962 * @arg @ref LL_RCC_PLLM_DIV_7
3963 * @arg @ref LL_RCC_PLLM_DIV_8
3964 * @arg @ref LL_RCC_PLLM_DIV_9
3965 * @arg @ref LL_RCC_PLLM_DIV_10
3966 * @arg @ref LL_RCC_PLLM_DIV_11
3967 * @arg @ref LL_RCC_PLLM_DIV_12
3968 * @arg @ref LL_RCC_PLLM_DIV_13
3969 * @arg @ref LL_RCC_PLLM_DIV_14
3970 * @arg @ref LL_RCC_PLLM_DIV_15
3971 * @arg @ref LL_RCC_PLLM_DIV_16
3972 * @arg @ref LL_RCC_PLLM_DIV_17
3973 * @arg @ref LL_RCC_PLLM_DIV_18
3974 * @arg @ref LL_RCC_PLLM_DIV_19
3975 * @arg @ref LL_RCC_PLLM_DIV_20
3976 * @arg @ref LL_RCC_PLLM_DIV_21
3977 * @arg @ref LL_RCC_PLLM_DIV_22
3978 * @arg @ref LL_RCC_PLLM_DIV_23
3979 * @arg @ref LL_RCC_PLLM_DIV_24
3980 * @arg @ref LL_RCC_PLLM_DIV_25
3981 * @arg @ref LL_RCC_PLLM_DIV_26
3982 * @arg @ref LL_RCC_PLLM_DIV_27
3983 * @arg @ref LL_RCC_PLLM_DIV_28
3984 * @arg @ref LL_RCC_PLLM_DIV_29
3985 * @arg @ref LL_RCC_PLLM_DIV_30
3986 * @arg @ref LL_RCC_PLLM_DIV_31
3987 * @arg @ref LL_RCC_PLLM_DIV_32
3988 * @arg @ref LL_RCC_PLLM_DIV_33
3989 * @arg @ref LL_RCC_PLLM_DIV_34
3990 * @arg @ref LL_RCC_PLLM_DIV_35
3991 * @arg @ref LL_RCC_PLLM_DIV_36
3992 * @arg @ref LL_RCC_PLLM_DIV_37
3993 * @arg @ref LL_RCC_PLLM_DIV_38
3994 * @arg @ref LL_RCC_PLLM_DIV_39
3995 * @arg @ref LL_RCC_PLLM_DIV_40
3996 * @arg @ref LL_RCC_PLLM_DIV_41
3997 * @arg @ref LL_RCC_PLLM_DIV_42
3998 * @arg @ref LL_RCC_PLLM_DIV_43
3999 * @arg @ref LL_RCC_PLLM_DIV_44
4000 * @arg @ref LL_RCC_PLLM_DIV_45
4001 * @arg @ref LL_RCC_PLLM_DIV_46
4002 * @arg @ref LL_RCC_PLLM_DIV_47
4003 * @arg @ref LL_RCC_PLLM_DIV_48
4004 * @arg @ref LL_RCC_PLLM_DIV_49
4005 * @arg @ref LL_RCC_PLLM_DIV_50
4006 * @arg @ref LL_RCC_PLLM_DIV_51
4007 * @arg @ref LL_RCC_PLLM_DIV_52
4008 * @arg @ref LL_RCC_PLLM_DIV_53
4009 * @arg @ref LL_RCC_PLLM_DIV_54
4010 * @arg @ref LL_RCC_PLLM_DIV_55
4011 * @arg @ref LL_RCC_PLLM_DIV_56
4012 * @arg @ref LL_RCC_PLLM_DIV_57
4013 * @arg @ref LL_RCC_PLLM_DIV_58
4014 * @arg @ref LL_RCC_PLLM_DIV_59
4015 * @arg @ref LL_RCC_PLLM_DIV_60
4016 * @arg @ref LL_RCC_PLLM_DIV_61
4017 * @arg @ref LL_RCC_PLLM_DIV_62
4018 * @arg @ref LL_RCC_PLLM_DIV_63
4019 * @param PLLN Between 50 and 432
4020 * @param PLLR This parameter can be one of the following values:
4021 * @arg @ref LL_RCC_PLLI2SR_DIV_2
4022 * @arg @ref LL_RCC_PLLI2SR_DIV_3
4023 * @arg @ref LL_RCC_PLLI2SR_DIV_4
4024 * @arg @ref LL_RCC_PLLI2SR_DIV_5
4025 * @arg @ref LL_RCC_PLLI2SR_DIV_6
4026 * @arg @ref LL_RCC_PLLI2SR_DIV_7
4027 * @retval None
4028 */
LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)4029 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4030 {
4031 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
4032 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLR);
4033 }
4034
4035 /**
4036 * @brief Get I2SPLL multiplication factor for VCO
4037 * @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN
4038 * @retval Between 50 and 432
4039 */
LL_RCC_PLLI2S_GetN(void)4040 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void)
4041 {
4042 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
4043 }
4044
4045 /**
4046 * @brief Get I2SPLL division factor for PLLI2SQ
4047 * @rmtoll PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_GetQ
4048 * @retval Returned value can be one of the following values:
4049 * @arg @ref LL_RCC_PLLI2SQ_DIV_2
4050 * @arg @ref LL_RCC_PLLI2SQ_DIV_3
4051 * @arg @ref LL_RCC_PLLI2SQ_DIV_4
4052 * @arg @ref LL_RCC_PLLI2SQ_DIV_5
4053 * @arg @ref LL_RCC_PLLI2SQ_DIV_6
4054 * @arg @ref LL_RCC_PLLI2SQ_DIV_7
4055 * @arg @ref LL_RCC_PLLI2SQ_DIV_8
4056 * @arg @ref LL_RCC_PLLI2SQ_DIV_9
4057 * @arg @ref LL_RCC_PLLI2SQ_DIV_10
4058 * @arg @ref LL_RCC_PLLI2SQ_DIV_11
4059 * @arg @ref LL_RCC_PLLI2SQ_DIV_12
4060 * @arg @ref LL_RCC_PLLI2SQ_DIV_13
4061 * @arg @ref LL_RCC_PLLI2SQ_DIV_14
4062 * @arg @ref LL_RCC_PLLI2SQ_DIV_15
4063 */
LL_RCC_PLLI2S_GetQ(void)4064 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void)
4065 {
4066 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ));
4067 }
4068
4069 /**
4070 * @brief Get I2SPLL division factor for PLLI2SR
4071 * @note used for PLLI2SCLK (I2S clock)
4072 * @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR
4073 * @retval Returned value can be one of the following values:
4074 * @arg @ref LL_RCC_PLLI2SR_DIV_2
4075 * @arg @ref LL_RCC_PLLI2SR_DIV_3
4076 * @arg @ref LL_RCC_PLLI2SR_DIV_4
4077 * @arg @ref LL_RCC_PLLI2SR_DIV_5
4078 * @arg @ref LL_RCC_PLLI2SR_DIV_6
4079 * @arg @ref LL_RCC_PLLI2SR_DIV_7
4080 */
LL_RCC_PLLI2S_GetR(void)4081 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void)
4082 {
4083 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR));
4084 }
4085
4086 #if defined(RCC_PLLI2SCFGR_PLLI2SP)
4087 /**
4088 * @brief Get I2SPLL division factor for PLLI2SP
4089 * @note used for PLLSPDIFRXCLK (SPDIFRX clock)
4090 * @rmtoll PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_GetP
4091 * @retval Returned value can be one of the following values:
4092 * @arg @ref LL_RCC_PLLI2SP_DIV_2
4093 * @arg @ref LL_RCC_PLLI2SP_DIV_4
4094 * @arg @ref LL_RCC_PLLI2SP_DIV_6
4095 * @arg @ref LL_RCC_PLLI2SP_DIV_8
4096 */
LL_RCC_PLLI2S_GetP(void)4097 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void)
4098 {
4099 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP));
4100 }
4101 #endif /* RCC_PLLI2SCFGR_PLLI2SP */
4102
4103 /**
4104 * @brief Get I2SPLL division factor for PLLI2SDIVQ
4105 * @note used PLLSAI1CLK, PLLSAI2CLK selected (SAI1 and SAI2 clock)
4106 * @rmtoll DCKCFGR1 PLLI2SDIVQ LL_RCC_PLLI2S_GetDIVQ
4107 * @retval Returned value can be one of the following values:
4108 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
4109 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
4110 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
4111 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
4112 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
4113 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
4114 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
4115 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
4116 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
4117 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
4118 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
4119 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
4120 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
4121 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
4122 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
4123 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
4124 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
4125 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
4126 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
4127 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
4128 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
4129 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
4130 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
4131 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
4132 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
4133 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
4134 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
4135 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
4136 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
4137 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
4138 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
4139 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
4140 */
LL_RCC_PLLI2S_GetDIVQ(void)4141 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void)
4142 {
4143 return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ));
4144 }
4145
4146 /**
4147 * @}
4148 */
4149
4150 /** @defgroup RCC_LL_EF_PLLSAI PLLSAI
4151 * @{
4152 */
4153
4154 /**
4155 * @brief Enable PLLSAI
4156 * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Enable
4157 * @retval None
4158 */
LL_RCC_PLLSAI_Enable(void)4159 __STATIC_INLINE void LL_RCC_PLLSAI_Enable(void)
4160 {
4161 SET_BIT(RCC->CR, RCC_CR_PLLSAION);
4162 }
4163
4164 /**
4165 * @brief Disable PLLSAI
4166 * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Disable
4167 * @retval None
4168 */
LL_RCC_PLLSAI_Disable(void)4169 __STATIC_INLINE void LL_RCC_PLLSAI_Disable(void)
4170 {
4171 CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
4172 }
4173
4174 /**
4175 * @brief Check if PLLSAI Ready
4176 * @rmtoll CR PLLSAIRDY LL_RCC_PLLSAI_IsReady
4177 * @retval State of bit (1 or 0).
4178 */
LL_RCC_PLLSAI_IsReady(void)4179 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void)
4180 {
4181 return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY));
4182 }
4183
4184 /**
4185 * @brief Configure PLLSAI used for SAI1 and SAI2 domain clock
4186 * @note PLL Source and PLLM Divider can be written only when PLL,
4187 * PLLI2S and PLLSAI are disabled
4188 * @note PLLN/PLLQ can be written only when PLLSAI is disabled
4189 * @note This can be selected for SAI1 and SAI2
4190 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_SAI\n
4191 * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_SAI\n
4192 * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_SAI\n
4193 * PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_ConfigDomain_SAI\n
4194 * DCKCFGR1 PLLSAIDIVQ LL_RCC_PLLSAI_ConfigDomain_SAI
4195 * @param Source This parameter can be one of the following values:
4196 * @arg @ref LL_RCC_PLLSOURCE_HSI
4197 * @arg @ref LL_RCC_PLLSOURCE_HSE
4198 * @param PLLM This parameter can be one of the following values:
4199 * @arg @ref LL_RCC_PLLM_DIV_2
4200 * @arg @ref LL_RCC_PLLM_DIV_3
4201 * @arg @ref LL_RCC_PLLM_DIV_4
4202 * @arg @ref LL_RCC_PLLM_DIV_5
4203 * @arg @ref LL_RCC_PLLM_DIV_6
4204 * @arg @ref LL_RCC_PLLM_DIV_7
4205 * @arg @ref LL_RCC_PLLM_DIV_8
4206 * @arg @ref LL_RCC_PLLM_DIV_9
4207 * @arg @ref LL_RCC_PLLM_DIV_10
4208 * @arg @ref LL_RCC_PLLM_DIV_11
4209 * @arg @ref LL_RCC_PLLM_DIV_12
4210 * @arg @ref LL_RCC_PLLM_DIV_13
4211 * @arg @ref LL_RCC_PLLM_DIV_14
4212 * @arg @ref LL_RCC_PLLM_DIV_15
4213 * @arg @ref LL_RCC_PLLM_DIV_16
4214 * @arg @ref LL_RCC_PLLM_DIV_17
4215 * @arg @ref LL_RCC_PLLM_DIV_18
4216 * @arg @ref LL_RCC_PLLM_DIV_19
4217 * @arg @ref LL_RCC_PLLM_DIV_20
4218 * @arg @ref LL_RCC_PLLM_DIV_21
4219 * @arg @ref LL_RCC_PLLM_DIV_22
4220 * @arg @ref LL_RCC_PLLM_DIV_23
4221 * @arg @ref LL_RCC_PLLM_DIV_24
4222 * @arg @ref LL_RCC_PLLM_DIV_25
4223 * @arg @ref LL_RCC_PLLM_DIV_26
4224 * @arg @ref LL_RCC_PLLM_DIV_27
4225 * @arg @ref LL_RCC_PLLM_DIV_28
4226 * @arg @ref LL_RCC_PLLM_DIV_29
4227 * @arg @ref LL_RCC_PLLM_DIV_30
4228 * @arg @ref LL_RCC_PLLM_DIV_31
4229 * @arg @ref LL_RCC_PLLM_DIV_32
4230 * @arg @ref LL_RCC_PLLM_DIV_33
4231 * @arg @ref LL_RCC_PLLM_DIV_34
4232 * @arg @ref LL_RCC_PLLM_DIV_35
4233 * @arg @ref LL_RCC_PLLM_DIV_36
4234 * @arg @ref LL_RCC_PLLM_DIV_37
4235 * @arg @ref LL_RCC_PLLM_DIV_38
4236 * @arg @ref LL_RCC_PLLM_DIV_39
4237 * @arg @ref LL_RCC_PLLM_DIV_40
4238 * @arg @ref LL_RCC_PLLM_DIV_41
4239 * @arg @ref LL_RCC_PLLM_DIV_42
4240 * @arg @ref LL_RCC_PLLM_DIV_43
4241 * @arg @ref LL_RCC_PLLM_DIV_44
4242 * @arg @ref LL_RCC_PLLM_DIV_45
4243 * @arg @ref LL_RCC_PLLM_DIV_46
4244 * @arg @ref LL_RCC_PLLM_DIV_47
4245 * @arg @ref LL_RCC_PLLM_DIV_48
4246 * @arg @ref LL_RCC_PLLM_DIV_49
4247 * @arg @ref LL_RCC_PLLM_DIV_50
4248 * @arg @ref LL_RCC_PLLM_DIV_51
4249 * @arg @ref LL_RCC_PLLM_DIV_52
4250 * @arg @ref LL_RCC_PLLM_DIV_53
4251 * @arg @ref LL_RCC_PLLM_DIV_54
4252 * @arg @ref LL_RCC_PLLM_DIV_55
4253 * @arg @ref LL_RCC_PLLM_DIV_56
4254 * @arg @ref LL_RCC_PLLM_DIV_57
4255 * @arg @ref LL_RCC_PLLM_DIV_58
4256 * @arg @ref LL_RCC_PLLM_DIV_59
4257 * @arg @ref LL_RCC_PLLM_DIV_60
4258 * @arg @ref LL_RCC_PLLM_DIV_61
4259 * @arg @ref LL_RCC_PLLM_DIV_62
4260 * @arg @ref LL_RCC_PLLM_DIV_63
4261 * @param PLLN Between 50 and 432
4262 * @param PLLQ This parameter can be one of the following values:
4263 * @arg @ref LL_RCC_PLLSAIQ_DIV_2
4264 * @arg @ref LL_RCC_PLLSAIQ_DIV_3
4265 * @arg @ref LL_RCC_PLLSAIQ_DIV_4
4266 * @arg @ref LL_RCC_PLLSAIQ_DIV_5
4267 * @arg @ref LL_RCC_PLLSAIQ_DIV_6
4268 * @arg @ref LL_RCC_PLLSAIQ_DIV_7
4269 * @arg @ref LL_RCC_PLLSAIQ_DIV_8
4270 * @arg @ref LL_RCC_PLLSAIQ_DIV_9
4271 * @arg @ref LL_RCC_PLLSAIQ_DIV_10
4272 * @arg @ref LL_RCC_PLLSAIQ_DIV_11
4273 * @arg @ref LL_RCC_PLLSAIQ_DIV_12
4274 * @arg @ref LL_RCC_PLLSAIQ_DIV_13
4275 * @arg @ref LL_RCC_PLLSAIQ_DIV_14
4276 * @arg @ref LL_RCC_PLLSAIQ_DIV_15
4277 * @param PLLDIVQ This parameter can be one of the following values:
4278 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
4279 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
4280 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
4281 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
4282 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
4283 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
4284 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
4285 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
4286 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
4287 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
4288 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
4289 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
4290 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
4291 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
4292 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
4293 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
4294 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
4295 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
4296 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
4297 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
4298 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
4299 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
4300 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
4301 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
4302 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
4303 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
4304 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
4305 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
4306 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
4307 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
4308 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
4309 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
4310 * @retval None
4311 */
LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ,uint32_t PLLDIVQ)4312 __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ)
4313 {
4314 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
4315 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLQ);
4316 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, PLLDIVQ);
4317 }
4318
4319 /**
4320 * @brief Configure PLLSAI used for 48Mhz domain clock
4321 * @note PLL Source and PLLM Divider can be written only when PLL,
4322 * PLLI2S and PLLSAI are disabled
4323 * @note PLLN/PLLP can be written only when PLLSAI is disabled
4324 * @note This can be selected for USB, RNG, SDMMC1
4325 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_48M\n
4326 * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_48M\n
4327 * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_48M\n
4328 * PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_ConfigDomain_48M
4329 * @param Source This parameter can be one of the following values:
4330 * @arg @ref LL_RCC_PLLSOURCE_HSI
4331 * @arg @ref LL_RCC_PLLSOURCE_HSE
4332 * @param PLLM This parameter can be one of the following values:
4333 * @arg @ref LL_RCC_PLLM_DIV_2
4334 * @arg @ref LL_RCC_PLLM_DIV_3
4335 * @arg @ref LL_RCC_PLLM_DIV_4
4336 * @arg @ref LL_RCC_PLLM_DIV_5
4337 * @arg @ref LL_RCC_PLLM_DIV_6
4338 * @arg @ref LL_RCC_PLLM_DIV_7
4339 * @arg @ref LL_RCC_PLLM_DIV_8
4340 * @arg @ref LL_RCC_PLLM_DIV_9
4341 * @arg @ref LL_RCC_PLLM_DIV_10
4342 * @arg @ref LL_RCC_PLLM_DIV_11
4343 * @arg @ref LL_RCC_PLLM_DIV_12
4344 * @arg @ref LL_RCC_PLLM_DIV_13
4345 * @arg @ref LL_RCC_PLLM_DIV_14
4346 * @arg @ref LL_RCC_PLLM_DIV_15
4347 * @arg @ref LL_RCC_PLLM_DIV_16
4348 * @arg @ref LL_RCC_PLLM_DIV_17
4349 * @arg @ref LL_RCC_PLLM_DIV_18
4350 * @arg @ref LL_RCC_PLLM_DIV_19
4351 * @arg @ref LL_RCC_PLLM_DIV_20
4352 * @arg @ref LL_RCC_PLLM_DIV_21
4353 * @arg @ref LL_RCC_PLLM_DIV_22
4354 * @arg @ref LL_RCC_PLLM_DIV_23
4355 * @arg @ref LL_RCC_PLLM_DIV_24
4356 * @arg @ref LL_RCC_PLLM_DIV_25
4357 * @arg @ref LL_RCC_PLLM_DIV_26
4358 * @arg @ref LL_RCC_PLLM_DIV_27
4359 * @arg @ref LL_RCC_PLLM_DIV_28
4360 * @arg @ref LL_RCC_PLLM_DIV_29
4361 * @arg @ref LL_RCC_PLLM_DIV_30
4362 * @arg @ref LL_RCC_PLLM_DIV_31
4363 * @arg @ref LL_RCC_PLLM_DIV_32
4364 * @arg @ref LL_RCC_PLLM_DIV_33
4365 * @arg @ref LL_RCC_PLLM_DIV_34
4366 * @arg @ref LL_RCC_PLLM_DIV_35
4367 * @arg @ref LL_RCC_PLLM_DIV_36
4368 * @arg @ref LL_RCC_PLLM_DIV_37
4369 * @arg @ref LL_RCC_PLLM_DIV_38
4370 * @arg @ref LL_RCC_PLLM_DIV_39
4371 * @arg @ref LL_RCC_PLLM_DIV_40
4372 * @arg @ref LL_RCC_PLLM_DIV_41
4373 * @arg @ref LL_RCC_PLLM_DIV_42
4374 * @arg @ref LL_RCC_PLLM_DIV_43
4375 * @arg @ref LL_RCC_PLLM_DIV_44
4376 * @arg @ref LL_RCC_PLLM_DIV_45
4377 * @arg @ref LL_RCC_PLLM_DIV_46
4378 * @arg @ref LL_RCC_PLLM_DIV_47
4379 * @arg @ref LL_RCC_PLLM_DIV_48
4380 * @arg @ref LL_RCC_PLLM_DIV_49
4381 * @arg @ref LL_RCC_PLLM_DIV_50
4382 * @arg @ref LL_RCC_PLLM_DIV_51
4383 * @arg @ref LL_RCC_PLLM_DIV_52
4384 * @arg @ref LL_RCC_PLLM_DIV_53
4385 * @arg @ref LL_RCC_PLLM_DIV_54
4386 * @arg @ref LL_RCC_PLLM_DIV_55
4387 * @arg @ref LL_RCC_PLLM_DIV_56
4388 * @arg @ref LL_RCC_PLLM_DIV_57
4389 * @arg @ref LL_RCC_PLLM_DIV_58
4390 * @arg @ref LL_RCC_PLLM_DIV_59
4391 * @arg @ref LL_RCC_PLLM_DIV_60
4392 * @arg @ref LL_RCC_PLLM_DIV_61
4393 * @arg @ref LL_RCC_PLLM_DIV_62
4394 * @arg @ref LL_RCC_PLLM_DIV_63
4395 * @param PLLN Between 50 and 432
4396 * @param PLLP This parameter can be one of the following values:
4397 * @arg @ref LL_RCC_PLLSAIP_DIV_2
4398 * @arg @ref LL_RCC_PLLSAIP_DIV_4
4399 * @arg @ref LL_RCC_PLLSAIP_DIV_6
4400 * @arg @ref LL_RCC_PLLSAIP_DIV_8
4401 * @retval None
4402 */
LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)4403 __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
4404 {
4405 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
4406 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLP);
4407 }
4408
4409 #if defined(LTDC)
4410 /**
4411 * @brief Configure PLLSAI used for LTDC domain clock
4412 * @note PLL Source and PLLM Divider can be written only when PLL,
4413 * PLLI2S and PLLSAI are disabled
4414 * @note PLLN/PLLR can be written only when PLLSAI is disabled
4415 * @note This can be selected for LTDC
4416 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_LTDC\n
4417 * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_LTDC\n
4418 * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_LTDC\n
4419 * PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_ConfigDomain_LTDC\n
4420 * DCKCFGR1 PLLSAIDIVR LL_RCC_PLLSAI_ConfigDomain_LTDC
4421 * @param Source This parameter can be one of the following values:
4422 * @arg @ref LL_RCC_PLLSOURCE_HSI
4423 * @arg @ref LL_RCC_PLLSOURCE_HSE
4424 * @param PLLM This parameter can be one of the following values:
4425 * @arg @ref LL_RCC_PLLM_DIV_2
4426 * @arg @ref LL_RCC_PLLM_DIV_3
4427 * @arg @ref LL_RCC_PLLM_DIV_4
4428 * @arg @ref LL_RCC_PLLM_DIV_5
4429 * @arg @ref LL_RCC_PLLM_DIV_6
4430 * @arg @ref LL_RCC_PLLM_DIV_7
4431 * @arg @ref LL_RCC_PLLM_DIV_8
4432 * @arg @ref LL_RCC_PLLM_DIV_9
4433 * @arg @ref LL_RCC_PLLM_DIV_10
4434 * @arg @ref LL_RCC_PLLM_DIV_11
4435 * @arg @ref LL_RCC_PLLM_DIV_12
4436 * @arg @ref LL_RCC_PLLM_DIV_13
4437 * @arg @ref LL_RCC_PLLM_DIV_14
4438 * @arg @ref LL_RCC_PLLM_DIV_15
4439 * @arg @ref LL_RCC_PLLM_DIV_16
4440 * @arg @ref LL_RCC_PLLM_DIV_17
4441 * @arg @ref LL_RCC_PLLM_DIV_18
4442 * @arg @ref LL_RCC_PLLM_DIV_19
4443 * @arg @ref LL_RCC_PLLM_DIV_20
4444 * @arg @ref LL_RCC_PLLM_DIV_21
4445 * @arg @ref LL_RCC_PLLM_DIV_22
4446 * @arg @ref LL_RCC_PLLM_DIV_23
4447 * @arg @ref LL_RCC_PLLM_DIV_24
4448 * @arg @ref LL_RCC_PLLM_DIV_25
4449 * @arg @ref LL_RCC_PLLM_DIV_26
4450 * @arg @ref LL_RCC_PLLM_DIV_27
4451 * @arg @ref LL_RCC_PLLM_DIV_28
4452 * @arg @ref LL_RCC_PLLM_DIV_29
4453 * @arg @ref LL_RCC_PLLM_DIV_30
4454 * @arg @ref LL_RCC_PLLM_DIV_31
4455 * @arg @ref LL_RCC_PLLM_DIV_32
4456 * @arg @ref LL_RCC_PLLM_DIV_33
4457 * @arg @ref LL_RCC_PLLM_DIV_34
4458 * @arg @ref LL_RCC_PLLM_DIV_35
4459 * @arg @ref LL_RCC_PLLM_DIV_36
4460 * @arg @ref LL_RCC_PLLM_DIV_37
4461 * @arg @ref LL_RCC_PLLM_DIV_38
4462 * @arg @ref LL_RCC_PLLM_DIV_39
4463 * @arg @ref LL_RCC_PLLM_DIV_40
4464 * @arg @ref LL_RCC_PLLM_DIV_41
4465 * @arg @ref LL_RCC_PLLM_DIV_42
4466 * @arg @ref LL_RCC_PLLM_DIV_43
4467 * @arg @ref LL_RCC_PLLM_DIV_44
4468 * @arg @ref LL_RCC_PLLM_DIV_45
4469 * @arg @ref LL_RCC_PLLM_DIV_46
4470 * @arg @ref LL_RCC_PLLM_DIV_47
4471 * @arg @ref LL_RCC_PLLM_DIV_48
4472 * @arg @ref LL_RCC_PLLM_DIV_49
4473 * @arg @ref LL_RCC_PLLM_DIV_50
4474 * @arg @ref LL_RCC_PLLM_DIV_51
4475 * @arg @ref LL_RCC_PLLM_DIV_52
4476 * @arg @ref LL_RCC_PLLM_DIV_53
4477 * @arg @ref LL_RCC_PLLM_DIV_54
4478 * @arg @ref LL_RCC_PLLM_DIV_55
4479 * @arg @ref LL_RCC_PLLM_DIV_56
4480 * @arg @ref LL_RCC_PLLM_DIV_57
4481 * @arg @ref LL_RCC_PLLM_DIV_58
4482 * @arg @ref LL_RCC_PLLM_DIV_59
4483 * @arg @ref LL_RCC_PLLM_DIV_60
4484 * @arg @ref LL_RCC_PLLM_DIV_61
4485 * @arg @ref LL_RCC_PLLM_DIV_62
4486 * @arg @ref LL_RCC_PLLM_DIV_63
4487 * @param PLLN Between 50 and 432
4488 * @param PLLR This parameter can be one of the following values:
4489 * @arg @ref LL_RCC_PLLSAIR_DIV_2
4490 * @arg @ref LL_RCC_PLLSAIR_DIV_3
4491 * @arg @ref LL_RCC_PLLSAIR_DIV_4
4492 * @arg @ref LL_RCC_PLLSAIR_DIV_5
4493 * @arg @ref LL_RCC_PLLSAIR_DIV_6
4494 * @arg @ref LL_RCC_PLLSAIR_DIV_7
4495 * @param PLLDIVR This parameter can be one of the following values:
4496 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
4497 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
4498 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
4499 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
4500 * @retval None
4501 */
LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR,uint32_t PLLDIVR)4502 __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
4503 {
4504 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
4505 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLR);
4506 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, PLLDIVR);
4507 }
4508 #endif /* LTDC */
4509
4510 /**
4511 * @brief Get SAIPLL multiplication factor for VCO
4512 * @rmtoll PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_GetN
4513 * @retval Between 50 and 432
4514 */
LL_RCC_PLLSAI_GetN(void)4515 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void)
4516 {
4517 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
4518 }
4519
4520 /**
4521 * @brief Get SAIPLL division factor for PLLSAIQ
4522 * @rmtoll PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_GetQ
4523 * @retval Returned value can be one of the following values:
4524 * @arg @ref LL_RCC_PLLSAIQ_DIV_2
4525 * @arg @ref LL_RCC_PLLSAIQ_DIV_3
4526 * @arg @ref LL_RCC_PLLSAIQ_DIV_4
4527 * @arg @ref LL_RCC_PLLSAIQ_DIV_5
4528 * @arg @ref LL_RCC_PLLSAIQ_DIV_6
4529 * @arg @ref LL_RCC_PLLSAIQ_DIV_7
4530 * @arg @ref LL_RCC_PLLSAIQ_DIV_8
4531 * @arg @ref LL_RCC_PLLSAIQ_DIV_9
4532 * @arg @ref LL_RCC_PLLSAIQ_DIV_10
4533 * @arg @ref LL_RCC_PLLSAIQ_DIV_11
4534 * @arg @ref LL_RCC_PLLSAIQ_DIV_12
4535 * @arg @ref LL_RCC_PLLSAIQ_DIV_13
4536 * @arg @ref LL_RCC_PLLSAIQ_DIV_14
4537 * @arg @ref LL_RCC_PLLSAIQ_DIV_15
4538 */
LL_RCC_PLLSAI_GetQ(void)4539 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void)
4540 {
4541 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ));
4542 }
4543
4544 #if defined(RCC_PLLSAICFGR_PLLSAIR)
4545 /**
4546 * @brief Get SAIPLL division factor for PLLSAIR
4547 * @note used for PLLSAICLK (SAI clock)
4548 * @rmtoll PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_GetR
4549 * @retval Returned value can be one of the following values:
4550 * @arg @ref LL_RCC_PLLSAIR_DIV_2
4551 * @arg @ref LL_RCC_PLLSAIR_DIV_3
4552 * @arg @ref LL_RCC_PLLSAIR_DIV_4
4553 * @arg @ref LL_RCC_PLLSAIR_DIV_5
4554 * @arg @ref LL_RCC_PLLSAIR_DIV_6
4555 * @arg @ref LL_RCC_PLLSAIR_DIV_7
4556 */
LL_RCC_PLLSAI_GetR(void)4557 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void)
4558 {
4559 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR));
4560 }
4561 #endif /* RCC_PLLSAICFGR_PLLSAIR */
4562
4563 /**
4564 * @brief Get SAIPLL division factor for PLLSAIP
4565 * @note used for PLL48MCLK (48M domain clock)
4566 * @rmtoll PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_GetP
4567 * @retval Returned value can be one of the following values:
4568 * @arg @ref LL_RCC_PLLSAIP_DIV_2
4569 * @arg @ref LL_RCC_PLLSAIP_DIV_4
4570 * @arg @ref LL_RCC_PLLSAIP_DIV_6
4571 * @arg @ref LL_RCC_PLLSAIP_DIV_8
4572 */
LL_RCC_PLLSAI_GetP(void)4573 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void)
4574 {
4575 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP));
4576 }
4577
4578 /**
4579 * @brief Get SAIPLL division factor for PLLSAIDIVQ
4580 * @note used PLLSAI1CLK, PLLSAI2CLK selected (SAI1 and SAI2 clock)
4581 * @rmtoll DCKCFGR1 PLLSAIDIVQ LL_RCC_PLLSAI_GetDIVQ
4582 * @retval Returned value can be one of the following values:
4583 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
4584 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
4585 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
4586 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
4587 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
4588 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
4589 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
4590 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
4591 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
4592 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
4593 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
4594 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
4595 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
4596 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
4597 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
4598 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
4599 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
4600 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
4601 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
4602 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
4603 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
4604 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
4605 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
4606 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
4607 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
4608 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
4609 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
4610 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
4611 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
4612 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
4613 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
4614 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
4615 */
LL_RCC_PLLSAI_GetDIVQ(void)4616 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void)
4617 {
4618 return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ));
4619 }
4620
4621 #if defined(RCC_DCKCFGR1_PLLSAIDIVR)
4622 /**
4623 * @brief Get SAIPLL division factor for PLLSAIDIVR
4624 * @note used for LTDC domain clock
4625 * @rmtoll DCKCFGR1 PLLSAIDIVR LL_RCC_PLLSAI_GetDIVR
4626 * @retval Returned value can be one of the following values:
4627 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
4628 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
4629 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
4630 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
4631 */
LL_RCC_PLLSAI_GetDIVR(void)4632 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void)
4633 {
4634 return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR));
4635 }
4636 #endif /* RCC_DCKCFGR1_PLLSAIDIVR */
4637
4638 /**
4639 * @}
4640 */
4641
4642 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
4643 * @{
4644 */
4645
4646 /**
4647 * @brief Clear LSI ready interrupt flag
4648 * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
4649 * @retval None
4650 */
LL_RCC_ClearFlag_LSIRDY(void)4651 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
4652 {
4653 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
4654 }
4655
4656 /**
4657 * @brief Clear LSE ready interrupt flag
4658 * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
4659 * @retval None
4660 */
LL_RCC_ClearFlag_LSERDY(void)4661 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
4662 {
4663 SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
4664 }
4665
4666 /**
4667 * @brief Clear HSI ready interrupt flag
4668 * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
4669 * @retval None
4670 */
LL_RCC_ClearFlag_HSIRDY(void)4671 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
4672 {
4673 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
4674 }
4675
4676 /**
4677 * @brief Clear HSE ready interrupt flag
4678 * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
4679 * @retval None
4680 */
LL_RCC_ClearFlag_HSERDY(void)4681 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
4682 {
4683 SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
4684 }
4685
4686 /**
4687 * @brief Clear PLL ready interrupt flag
4688 * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
4689 * @retval None
4690 */
LL_RCC_ClearFlag_PLLRDY(void)4691 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
4692 {
4693 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
4694 }
4695
4696 /**
4697 * @brief Clear PLLI2S ready interrupt flag
4698 * @rmtoll CIR PLLI2SRDYC LL_RCC_ClearFlag_PLLI2SRDY
4699 * @retval None
4700 */
LL_RCC_ClearFlag_PLLI2SRDY(void)4701 __STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
4702 {
4703 SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
4704 }
4705
4706 /**
4707 * @brief Clear PLLSAI ready interrupt flag
4708 * @rmtoll CIR PLLSAIRDYC LL_RCC_ClearFlag_PLLSAIRDY
4709 * @retval None
4710 */
LL_RCC_ClearFlag_PLLSAIRDY(void)4711 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAIRDY(void)
4712 {
4713 SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
4714 }
4715
4716 /**
4717 * @brief Clear Clock security system interrupt flag
4718 * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
4719 * @retval None
4720 */
LL_RCC_ClearFlag_HSECSS(void)4721 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
4722 {
4723 SET_BIT(RCC->CIR, RCC_CIR_CSSC);
4724 }
4725
4726 /**
4727 * @brief Check if LSI ready interrupt occurred or not
4728 * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
4729 * @retval State of bit (1 or 0).
4730 */
LL_RCC_IsActiveFlag_LSIRDY(void)4731 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
4732 {
4733 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
4734 }
4735
4736 /**
4737 * @brief Check if LSE ready interrupt occurred or not
4738 * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
4739 * @retval State of bit (1 or 0).
4740 */
LL_RCC_IsActiveFlag_LSERDY(void)4741 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
4742 {
4743 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
4744 }
4745
4746 /**
4747 * @brief Check if HSI ready interrupt occurred or not
4748 * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
4749 * @retval State of bit (1 or 0).
4750 */
LL_RCC_IsActiveFlag_HSIRDY(void)4751 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
4752 {
4753 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
4754 }
4755
4756 /**
4757 * @brief Check if HSE ready interrupt occurred or not
4758 * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
4759 * @retval State of bit (1 or 0).
4760 */
LL_RCC_IsActiveFlag_HSERDY(void)4761 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
4762 {
4763 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
4764 }
4765
4766 /**
4767 * @brief Check if PLL ready interrupt occurred or not
4768 * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
4769 * @retval State of bit (1 or 0).
4770 */
LL_RCC_IsActiveFlag_PLLRDY(void)4771 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
4772 {
4773 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
4774 }
4775
4776 /**
4777 * @brief Check if PLLI2S ready interrupt occurred or not
4778 * @rmtoll CIR PLLI2SRDYF LL_RCC_IsActiveFlag_PLLI2SRDY
4779 * @retval State of bit (1 or 0).
4780 */
LL_RCC_IsActiveFlag_PLLI2SRDY(void)4781 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
4782 {
4783 return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF));
4784 }
4785
4786 /**
4787 * @brief Check if PLLSAI ready interrupt occurred or not
4788 * @rmtoll CIR PLLSAIRDYF LL_RCC_IsActiveFlag_PLLSAIRDY
4789 * @retval State of bit (1 or 0).
4790 */
LL_RCC_IsActiveFlag_PLLSAIRDY(void)4791 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAIRDY(void)
4792 {
4793 return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYF) == (RCC_CIR_PLLSAIRDYF));
4794 }
4795
4796 /**
4797 * @brief Check if Clock security system interrupt occurred or not
4798 * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
4799 * @retval State of bit (1 or 0).
4800 */
LL_RCC_IsActiveFlag_HSECSS(void)4801 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
4802 {
4803 return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
4804 }
4805
4806 /**
4807 * @brief Check if RCC flag Independent Watchdog reset is set or not.
4808 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
4809 * @retval State of bit (1 or 0).
4810 */
LL_RCC_IsActiveFlag_IWDGRST(void)4811 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
4812 {
4813 return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
4814 }
4815
4816 /**
4817 * @brief Check if RCC flag Low Power reset is set or not.
4818 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
4819 * @retval State of bit (1 or 0).
4820 */
LL_RCC_IsActiveFlag_LPWRRST(void)4821 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
4822 {
4823 return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
4824 }
4825
4826 /**
4827 * @brief Check if RCC flag Pin reset is set or not.
4828 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
4829 * @retval State of bit (1 or 0).
4830 */
LL_RCC_IsActiveFlag_PINRST(void)4831 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
4832 {
4833 return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
4834 }
4835
4836 /**
4837 * @brief Check if RCC flag POR/PDR reset is set or not.
4838 * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
4839 * @retval State of bit (1 or 0).
4840 */
LL_RCC_IsActiveFlag_PORRST(void)4841 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
4842 {
4843 return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
4844 }
4845
4846 /**
4847 * @brief Check if RCC flag Software reset is set or not.
4848 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
4849 * @retval State of bit (1 or 0).
4850 */
LL_RCC_IsActiveFlag_SFTRST(void)4851 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
4852 {
4853 return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
4854 }
4855
4856 /**
4857 * @brief Check if RCC flag Window Watchdog reset is set or not.
4858 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
4859 * @retval State of bit (1 or 0).
4860 */
LL_RCC_IsActiveFlag_WWDGRST(void)4861 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
4862 {
4863 return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
4864 }
4865
4866 /**
4867 * @brief Check if RCC flag BOR reset is set or not.
4868 * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
4869 * @retval State of bit (1 or 0).
4870 */
LL_RCC_IsActiveFlag_BORRST(void)4871 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
4872 {
4873 return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
4874 }
4875
4876 /**
4877 * @brief Set RMVF bit to clear the reset flags.
4878 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
4879 * @retval None
4880 */
LL_RCC_ClearResetFlags(void)4881 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
4882 {
4883 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
4884 }
4885
4886 /**
4887 * @}
4888 */
4889
4890 /** @defgroup RCC_LL_EF_IT_Management IT Management
4891 * @{
4892 */
4893
4894 /**
4895 * @brief Enable LSI ready interrupt
4896 * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
4897 * @retval None
4898 */
LL_RCC_EnableIT_LSIRDY(void)4899 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
4900 {
4901 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
4902 }
4903
4904 /**
4905 * @brief Enable LSE ready interrupt
4906 * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
4907 * @retval None
4908 */
LL_RCC_EnableIT_LSERDY(void)4909 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
4910 {
4911 SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
4912 }
4913
4914 /**
4915 * @brief Enable HSI ready interrupt
4916 * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
4917 * @retval None
4918 */
LL_RCC_EnableIT_HSIRDY(void)4919 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
4920 {
4921 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
4922 }
4923
4924 /**
4925 * @brief Enable HSE ready interrupt
4926 * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
4927 * @retval None
4928 */
LL_RCC_EnableIT_HSERDY(void)4929 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
4930 {
4931 SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
4932 }
4933
4934 /**
4935 * @brief Enable PLL ready interrupt
4936 * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
4937 * @retval None
4938 */
LL_RCC_EnableIT_PLLRDY(void)4939 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
4940 {
4941 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
4942 }
4943
4944 /**
4945 * @brief Enable PLLI2S ready interrupt
4946 * @rmtoll CIR PLLI2SRDYIE LL_RCC_EnableIT_PLLI2SRDY
4947 * @retval None
4948 */
LL_RCC_EnableIT_PLLI2SRDY(void)4949 __STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
4950 {
4951 SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
4952 }
4953
4954 /**
4955 * @brief Enable PLLSAI ready interrupt
4956 * @rmtoll CIR PLLSAIRDYIE LL_RCC_EnableIT_PLLSAIRDY
4957 * @retval None
4958 */
LL_RCC_EnableIT_PLLSAIRDY(void)4959 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAIRDY(void)
4960 {
4961 SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
4962 }
4963
4964 /**
4965 * @brief Disable LSI ready interrupt
4966 * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
4967 * @retval None
4968 */
LL_RCC_DisableIT_LSIRDY(void)4969 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
4970 {
4971 CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
4972 }
4973
4974 /**
4975 * @brief Disable LSE ready interrupt
4976 * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
4977 * @retval None
4978 */
LL_RCC_DisableIT_LSERDY(void)4979 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
4980 {
4981 CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
4982 }
4983
4984 /**
4985 * @brief Disable HSI ready interrupt
4986 * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
4987 * @retval None
4988 */
LL_RCC_DisableIT_HSIRDY(void)4989 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
4990 {
4991 CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
4992 }
4993
4994 /**
4995 * @brief Disable HSE ready interrupt
4996 * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
4997 * @retval None
4998 */
LL_RCC_DisableIT_HSERDY(void)4999 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
5000 {
5001 CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
5002 }
5003
5004 /**
5005 * @brief Disable PLL ready interrupt
5006 * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
5007 * @retval None
5008 */
LL_RCC_DisableIT_PLLRDY(void)5009 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
5010 {
5011 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
5012 }
5013
5014 /**
5015 * @brief Disable PLLI2S ready interrupt
5016 * @rmtoll CIR PLLI2SRDYIE LL_RCC_DisableIT_PLLI2SRDY
5017 * @retval None
5018 */
LL_RCC_DisableIT_PLLI2SRDY(void)5019 __STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
5020 {
5021 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
5022 }
5023
5024 /**
5025 * @brief Disable PLLSAI ready interrupt
5026 * @rmtoll CIR PLLSAIRDYIE LL_RCC_DisableIT_PLLSAIRDY
5027 * @retval None
5028 */
LL_RCC_DisableIT_PLLSAIRDY(void)5029 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAIRDY(void)
5030 {
5031 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
5032 }
5033
5034 /**
5035 * @brief Checks if LSI ready interrupt source is enabled or disabled.
5036 * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
5037 * @retval State of bit (1 or 0).
5038 */
LL_RCC_IsEnabledIT_LSIRDY(void)5039 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
5040 {
5041 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
5042 }
5043
5044 /**
5045 * @brief Checks if LSE ready interrupt source is enabled or disabled.
5046 * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
5047 * @retval State of bit (1 or 0).
5048 */
LL_RCC_IsEnabledIT_LSERDY(void)5049 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
5050 {
5051 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
5052 }
5053
5054 /**
5055 * @brief Checks if HSI ready interrupt source is enabled or disabled.
5056 * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
5057 * @retval State of bit (1 or 0).
5058 */
LL_RCC_IsEnabledIT_HSIRDY(void)5059 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
5060 {
5061 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
5062 }
5063
5064 /**
5065 * @brief Checks if HSE ready interrupt source is enabled or disabled.
5066 * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
5067 * @retval State of bit (1 or 0).
5068 */
LL_RCC_IsEnabledIT_HSERDY(void)5069 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
5070 {
5071 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
5072 }
5073
5074 /**
5075 * @brief Checks if PLL ready interrupt source is enabled or disabled.
5076 * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
5077 * @retval State of bit (1 or 0).
5078 */
LL_RCC_IsEnabledIT_PLLRDY(void)5079 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
5080 {
5081 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
5082 }
5083
5084 /**
5085 * @brief Checks if PLLI2S ready interrupt source is enabled or disabled.
5086 * @rmtoll CIR PLLI2SRDYIE LL_RCC_IsEnabledIT_PLLI2SRDY
5087 * @retval State of bit (1 or 0).
5088 */
LL_RCC_IsEnabledIT_PLLI2SRDY(void)5089 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
5090 {
5091 return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE));
5092 }
5093
5094 /**
5095 * @brief Checks if PLLSAI ready interrupt source is enabled or disabled.
5096 * @rmtoll CIR PLLSAIRDYIE LL_RCC_IsEnabledIT_PLLSAIRDY
5097 * @retval State of bit (1 or 0).
5098 */
LL_RCC_IsEnabledIT_PLLSAIRDY(void)5099 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAIRDY(void)
5100 {
5101 return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE) == (RCC_CIR_PLLSAIRDYIE));
5102 }
5103
5104 /**
5105 * @}
5106 */
5107
5108 #if defined(USE_FULL_LL_DRIVER)
5109 /** @defgroup RCC_LL_EF_Init De-initialization function
5110 * @{
5111 */
5112 ErrorStatus LL_RCC_DeInit(void);
5113 /**
5114 * @}
5115 */
5116
5117 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
5118 * @{
5119 */
5120 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
5121 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
5122 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
5123 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
5124 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
5125 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
5126 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
5127 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
5128 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
5129 #if defined(DFSDM1_Channel0)
5130 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
5131 uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource);
5132 #endif /* DFSDM1_Channel0 */
5133 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
5134 #if defined(CEC)
5135 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
5136 #endif /* CEC */
5137 #if defined(LTDC)
5138 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);
5139 #endif /* LTDC */
5140 #if defined(SPDIFRX)
5141 uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource);
5142 #endif /* SPDIFRX */
5143 #if defined(DSI)
5144 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
5145 #endif /* DSI */
5146 /**
5147 * @}
5148 */
5149 #endif /* USE_FULL_LL_DRIVER */
5150
5151 /**
5152 * @}
5153 */
5154
5155 /**
5156 * @}
5157 */
5158
5159 #endif /* defined(RCC) */
5160
5161 /**
5162 * @}
5163 */
5164
5165 #ifdef __cplusplus
5166 }
5167 #endif
5168
5169 #endif /* __STM32F7xx_LL_RCC_H */
5170
5171
