1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_fmc.c
4 * @author MCD Application Team
5 * @brief FMC Low Layer HAL module driver.
6 *
7 * This file provides firmware functions to manage the following
8 * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
9 * + Initialization/de-initialization functions
10 * + Peripheral Control functions
11 * + Peripheral State functions
12 *
13 ******************************************************************************
14 * @attention
15 *
16 * Copyright (c) 2016 STMicroelectronics.
17 * All rights reserved.
18 *
19 * This software is licensed under terms that can be found in the LICENSE file
20 * in the root directory of this software component.
21 * If no LICENSE file comes with this software, it is provided AS-IS.
22 *
23 ******************************************************************************
24 @verbatim
25 ==============================================================================
26 ##### FMC peripheral features #####
27 ==============================================================================
28 [..] The Flexible memory controller (FMC) includes following memory controllers:
29 (+) The NOR/PSRAM memory controller
30 (+) The NAND/PC Card memory controller
31 (+) The Synchronous DRAM (SDRAM) controller
32
33 [..] The FMC functional block makes the interface with synchronous and asynchronous static
34 memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
35 (+) to translate AHB transactions into the appropriate external device protocol
36 (+) to meet the access time requirements of the external memory devices
37
38 [..] All external memories share the addresses, data and control signals with the controller.
39 Each external device is accessed by means of a unique Chip Select. The FMC performs
40 only one access at a time to an external device.
41 The main features of the FMC controller are the following:
42 (+) Interface with static-memory mapped devices including:
43 (++) Static random access memory (SRAM)
44 (++) Read-only memory (ROM)
45 (++) NOR Flash memory/OneNAND Flash memory
46 (++) PSRAM (4 memory banks)
47 (++) 16-bit PC Card compatible devices
48 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
49 data
50 (+) Interface with synchronous DRAM (SDRAM) memories
51 (+) Independent Chip Select control for each memory bank
52 (+) Independent configuration for each memory bank
53
54 @endverbatim
55 ******************************************************************************
56 */
57
58 /* Includes ------------------------------------------------------------------*/
59 #include "stm32f4xx_hal.h"
60
61 /** @addtogroup STM32F4xx_HAL_Driver
62 * @{
63 */
64 #if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || (defined(HAL_NAND_MODULE_ENABLED)) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)
65
66 /** @defgroup FMC_LL FMC Low Layer
67 * @brief FMC driver modules
68 * @{
69 */
70
71 /* Private typedef -----------------------------------------------------------*/
72 /* Private define ------------------------------------------------------------*/
73
74 /** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants
75 * @{
76 */
77
78 /* ----------------------- FMC registers bit mask --------------------------- */
79
80 #if defined(FMC_Bank1)
81 /* --- BCR Register ---*/
82 /* BCR register clear mask */
83
84 /* --- BTR Register ---*/
85 /* BTR register clear mask */
86 #define BTR_CLEAR_MASK ((uint32_t)(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD |\
87 FMC_BTR1_DATAST | FMC_BTR1_BUSTURN |\
88 FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT |\
89 FMC_BTR1_ACCMOD))
90
91 /* --- BWTR Register ---*/
92 /* BWTR register clear mask */
93 #define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD |\
94 FMC_BWTR1_DATAST | FMC_BWTR1_BUSTURN |\
95 FMC_BWTR1_ACCMOD))
96 #endif /* FMC_Bank1 */
97 #if defined(FMC_Bank3) || defined(FMC_Bank2_3)
98
99 #if defined (FMC_PCR_PWAITEN)
100 /* --- PCR Register ---*/
101 /* PCR register clear mask */
102 #define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | \
103 FMC_PCR_PTYP | FMC_PCR_PWID | \
104 FMC_PCR_ECCEN | FMC_PCR_TCLR | \
105 FMC_PCR_TAR | FMC_PCR_ECCPS))
106 /* --- PMEM Register ---*/
107 /* PMEM register clear mask */
108 #define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM_MEMSET2 | FMC_PMEM_MEMWAIT2 |\
109 FMC_PMEM_MEMHOLD2 | FMC_PMEM_MEMHIZ2))
110
111 /* --- PATT Register ---*/
112 /* PATT register clear mask */
113 #define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT_ATTSET2 | FMC_PATT_ATTWAIT2 |\
114 FMC_PATT_ATTHOLD2 | FMC_PATT_ATTHIZ2))
115 #else
116 /* --- PCR Register ---*/
117 /* PCR register clear mask */
118 #define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR2_PWAITEN | FMC_PCR2_PBKEN | \
119 FMC_PCR2_PTYP | FMC_PCR2_PWID | \
120 FMC_PCR2_ECCEN | FMC_PCR2_TCLR | \
121 FMC_PCR2_TAR | FMC_PCR2_ECCPS))
122 /* --- PMEM Register ---*/
123 /* PMEM register clear mask */
124 #define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM2_MEMSET2 | FMC_PMEM2_MEMWAIT2 |\
125 FMC_PMEM2_MEMHOLD2 | FMC_PMEM2_MEMHIZ2))
126
127 /* --- PATT Register ---*/
128 /* PATT register clear mask */
129 #define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT2_ATTSET2 | FMC_PATT2_ATTWAIT2 |\
130 FMC_PATT2_ATTHOLD2 | FMC_PATT2_ATTHIZ2))
131
132 #endif /* FMC_PCR_PWAITEN */
133 #endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
134 #if defined(FMC_Bank4)
135 /* --- PCR Register ---*/
136 /* PCR register clear mask */
137 #define PCR4_CLEAR_MASK ((uint32_t)(FMC_PCR4_PWAITEN | FMC_PCR4_PBKEN | \
138 FMC_PCR4_PTYP | FMC_PCR4_PWID | \
139 FMC_PCR4_ECCEN | FMC_PCR4_TCLR | \
140 FMC_PCR4_TAR | FMC_PCR4_ECCPS))
141 /* --- PMEM Register ---*/
142 /* PMEM register clear mask */
143 #define PMEM4_CLEAR_MASK ((uint32_t)(FMC_PMEM4_MEMSET4 | FMC_PMEM4_MEMWAIT4 |\
144 FMC_PMEM4_MEMHOLD4 | FMC_PMEM4_MEMHIZ4))
145
146 /* --- PATT Register ---*/
147 /* PATT register clear mask */
148 #define PATT4_CLEAR_MASK ((uint32_t)(FMC_PATT4_ATTSET4 | FMC_PATT4_ATTWAIT4 |\
149 FMC_PATT4_ATTHOLD4 | FMC_PATT4_ATTHIZ4))
150
151 /* --- PIO4 Register ---*/
152 /* PIO4 register clear mask */
153 #define PIO4_CLEAR_MASK ((uint32_t)(FMC_PIO4_IOSET4 | FMC_PIO4_IOWAIT4 | \
154 FMC_PIO4_IOHOLD4 | FMC_PIO4_IOHIZ4))
155
156 #endif /* FMC_Bank4 */
157 #if defined(FMC_Bank5_6)
158
159 /* --- SDCR Register ---*/
160 /* SDCR register clear mask */
161 #define SDCR_CLEAR_MASK ((uint32_t)(FMC_SDCR1_NC | FMC_SDCR1_NR | \
162 FMC_SDCR1_MWID | FMC_SDCR1_NB | \
163 FMC_SDCR1_CAS | FMC_SDCR1_WP | \
164 FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | \
165 FMC_SDCR1_RPIPE))
166
167 /* --- SDTR Register ---*/
168 /* SDTR register clear mask */
169 #define SDTR_CLEAR_MASK ((uint32_t)(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | \
170 FMC_SDTR1_TRAS | FMC_SDTR1_TRC | \
171 FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
172 FMC_SDTR1_TRCD))
173 #endif /* FMC_Bank5_6 */
174
175 /**
176 * @}
177 */
178
179 /* Private macro -------------------------------------------------------------*/
180 /* Private variables ---------------------------------------------------------*/
181 /* Private function prototypes -----------------------------------------------*/
182 /* Exported functions --------------------------------------------------------*/
183
184 /** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
185 * @{
186 */
187
188 #if defined(FMC_Bank1)
189
190 /** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions
191 * @brief NORSRAM Controller functions
192 *
193 @verbatim
194 ==============================================================================
195 ##### How to use NORSRAM device driver #####
196 ==============================================================================
197
198 [..]
199 This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
200 to run the NORSRAM external devices.
201
202 (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
203 (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
204 (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
205 (+) FMC NORSRAM bank extended timing configuration using the function
206 FMC_NORSRAM_Extended_Timing_Init()
207 (+) FMC NORSRAM bank enable/disable write operation using the functions
208 FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
209
210 @endverbatim
211 * @{
212 */
213
214 /** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
215 * @brief Initialization and Configuration functions
216 *
217 @verbatim
218 ==============================================================================
219 ##### Initialization and de_initialization functions #####
220 ==============================================================================
221 [..]
222 This section provides functions allowing to:
223 (+) Initialize and configure the FMC NORSRAM interface
224 (+) De-initialize the FMC NORSRAM interface
225 (+) Configure the FMC clock and associated GPIOs
226
227 @endverbatim
228 * @{
229 */
230
231 /**
232 * @brief Initialize the FMC_NORSRAM device according to the specified
233 * control parameters in the FMC_NORSRAM_InitTypeDef
234 * @param Device Pointer to NORSRAM device instance
235 * @param Init Pointer to NORSRAM Initialization structure
236 * @retval HAL status
237 */
FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef * Device,FMC_NORSRAM_InitTypeDef * Init)238 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
239 FMC_NORSRAM_InitTypeDef *Init)
240 {
241 uint32_t flashaccess;
242 uint32_t btcr_reg;
243 uint32_t mask;
244
245 /* Check the parameters */
246 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
247 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
248 assert_param(IS_FMC_MUX(Init->DataAddressMux));
249 assert_param(IS_FMC_MEMORY(Init->MemoryType));
250 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
251 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
252 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
253 #if defined(FMC_BCR1_WRAPMOD)
254 assert_param(IS_FMC_WRAP_MODE(Init->WrapMode));
255 #endif /* FMC_BCR1_WRAPMOD */
256 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
257 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
258 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
259 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
260 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
261 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
262 #if defined(FMC_BCR1_CCLKEN)
263 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
264 #endif
265 #if defined(FMC_BCR1_WFDIS)
266 assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
267 #endif /* FMC_BCR1_WFDIS */
268 assert_param(IS_FMC_PAGESIZE(Init->PageSize));
269
270 /* Disable NORSRAM Device */
271 __FMC_NORSRAM_DISABLE(Device, Init->NSBank);
272
273 /* Set NORSRAM device control parameters */
274 if (Init->MemoryType == FMC_MEMORY_TYPE_NOR)
275 {
276 flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE;
277 }
278 else
279 {
280 flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE;
281 }
282
283 btcr_reg = (flashaccess | \
284 Init->DataAddressMux | \
285 Init->MemoryType | \
286 Init->MemoryDataWidth | \
287 Init->BurstAccessMode | \
288 Init->WaitSignalPolarity | \
289 Init->WaitSignalActive | \
290 Init->WriteOperation | \
291 Init->WaitSignal | \
292 Init->ExtendedMode | \
293 Init->AsynchronousWait | \
294 Init->WriteBurst);
295
296 #if defined(FMC_BCR1_WRAPMOD)
297 btcr_reg |= Init->WrapMode;
298 #endif /* FMC_BCR1_WRAPMOD */
299 #if defined(FMC_BCR1_CCLKEN)
300 btcr_reg |= Init->ContinuousClock;
301 #endif /* FMC_BCR1_CCLKEN */
302 #if defined(FMC_BCR1_WFDIS)
303 btcr_reg |= Init->WriteFifo;
304 #endif /* FMC_BCR1_WFDIS */
305 btcr_reg |= Init->PageSize;
306
307 mask = (FMC_BCR1_MBKEN |
308 FMC_BCR1_MUXEN |
309 FMC_BCR1_MTYP |
310 FMC_BCR1_MWID |
311 FMC_BCR1_FACCEN |
312 FMC_BCR1_BURSTEN |
313 FMC_BCR1_WAITPOL |
314 FMC_BCR1_WAITCFG |
315 FMC_BCR1_WREN |
316 FMC_BCR1_WAITEN |
317 FMC_BCR1_EXTMOD |
318 FMC_BCR1_ASYNCWAIT |
319 FMC_BCR1_CBURSTRW);
320
321 #if defined(FMC_BCR1_WRAPMOD)
322 mask |= FMC_BCR1_WRAPMOD;
323 #endif /* FMC_BCR1_WRAPMOD */
324 #if defined(FMC_BCR1_CCLKEN)
325 mask |= FMC_BCR1_CCLKEN;
326 #endif
327 #if defined(FMC_BCR1_WFDIS)
328 mask |= FMC_BCR1_WFDIS;
329 #endif /* FMC_BCR1_WFDIS */
330 mask |= FMC_BCR1_CPSIZE;
331
332 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
333
334 #if defined(FMC_BCR1_CCLKEN)
335 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
336 if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
337 {
338 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);
339 }
340 #endif
341 #if defined(FMC_BCR1_WFDIS)
342
343 if (Init->NSBank != FMC_NORSRAM_BANK1)
344 {
345 /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */
346 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));
347 }
348 #endif /* FMC_BCR1_WFDIS */
349
350 return HAL_OK;
351 }
352
353 /**
354 * @brief DeInitialize the FMC_NORSRAM peripheral
355 * @param Device Pointer to NORSRAM device instance
356 * @param ExDevice Pointer to NORSRAM extended mode device instance
357 * @param Bank NORSRAM bank number
358 * @retval HAL status
359 */
FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef * Device,FMC_NORSRAM_EXTENDED_TypeDef * ExDevice,uint32_t Bank)360 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
361 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
362 {
363 /* Check the parameters */
364 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
365 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
366 assert_param(IS_FMC_NORSRAM_BANK(Bank));
367
368 /* Disable the FMC_NORSRAM device */
369 __FMC_NORSRAM_DISABLE(Device, Bank);
370
371 /* De-initialize the FMC_NORSRAM device */
372 /* FMC_NORSRAM_BANK1 */
373 if (Bank == FMC_NORSRAM_BANK1)
374 {
375 Device->BTCR[Bank] = 0x000030DBU;
376 }
377 /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
378 else
379 {
380 Device->BTCR[Bank] = 0x000030D2U;
381 }
382
383 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
384 ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
385
386 return HAL_OK;
387 }
388
389 /**
390 * @brief Initialize the FMC_NORSRAM Timing according to the specified
391 * parameters in the FMC_NORSRAM_TimingTypeDef
392 * @param Device Pointer to NORSRAM device instance
393 * @param Timing Pointer to NORSRAM Timing structure
394 * @param Bank NORSRAM bank number
395 * @retval HAL status
396 */
FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef * Device,FMC_NORSRAM_TimingTypeDef * Timing,uint32_t Bank)397 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
398 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
399 {
400 #if defined(FMC_BCR1_CCLKEN)
401 uint32_t tmpr;
402 #endif
403
404 /* Check the parameters */
405 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
406 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
407 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
408 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
409 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
410 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
411 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
412 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
413 assert_param(IS_FMC_NORSRAM_BANK(Bank));
414
415 /* Set FMC_NORSRAM device timing parameters */
416 MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime |
417 ((Timing->AddressHoldTime) << FMC_BTR1_ADDHLD_Pos) |
418 ((Timing->DataSetupTime) << FMC_BTR1_DATAST_Pos) |
419 ((Timing->BusTurnAroundDuration) << FMC_BTR1_BUSTURN_Pos) |
420 (((Timing->CLKDivision) - 1U) << FMC_BTR1_CLKDIV_Pos) |
421 (((Timing->DataLatency) - 2U) << FMC_BTR1_DATLAT_Pos) |
422 (Timing->AccessMode)));
423
424 #if defined(FMC_BCR1_CCLKEN)
425 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
426 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
427 {
428 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTR1_CLKDIV_Pos));
429 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTR1_CLKDIV_Pos);
430 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTR1_CLKDIV, tmpr);
431 }
432
433 #endif
434 return HAL_OK;
435 }
436
437 /**
438 * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
439 * parameters in the FMC_NORSRAM_TimingTypeDef
440 * @param Device Pointer to NORSRAM device instance
441 * @param Timing Pointer to NORSRAM Timing structure
442 * @param Bank NORSRAM bank number
443 * @param ExtendedMode FMC Extended Mode
444 * This parameter can be one of the following values:
445 * @arg FMC_EXTENDED_MODE_DISABLE
446 * @arg FMC_EXTENDED_MODE_ENABLE
447 * @retval HAL status
448 */
FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef * Device,FMC_NORSRAM_TimingTypeDef * Timing,uint32_t Bank,uint32_t ExtendedMode)449 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
450 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
451 uint32_t ExtendedMode)
452 {
453 /* Check the parameters */
454 assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
455
456 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
457 if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
458 {
459 /* Check the parameters */
460 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
461 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
462 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
463 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
464 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
465 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
466 assert_param(IS_FMC_NORSRAM_BANK(Bank));
467
468 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
469 MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime |
470 ((Timing->AddressHoldTime) << FMC_BWTR1_ADDHLD_Pos) |
471 ((Timing->DataSetupTime) << FMC_BWTR1_DATAST_Pos) |
472 Timing->AccessMode |
473 ((Timing->BusTurnAroundDuration) << FMC_BWTR1_BUSTURN_Pos)));
474 }
475 else
476 {
477 Device->BWTR[Bank] = 0x0FFFFFFFU;
478 }
479
480 return HAL_OK;
481 }
482 /**
483 * @}
484 */
485
486 /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
487 * @brief management functions
488 *
489 @verbatim
490 ==============================================================================
491 ##### FMC_NORSRAM Control functions #####
492 ==============================================================================
493 [..]
494 This subsection provides a set of functions allowing to control dynamically
495 the FMC NORSRAM interface.
496
497 @endverbatim
498 * @{
499 */
500
501 /**
502 * @brief Enables dynamically FMC_NORSRAM write operation.
503 * @param Device Pointer to NORSRAM device instance
504 * @param Bank NORSRAM bank number
505 * @retval HAL status
506 */
FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef * Device,uint32_t Bank)507 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
508 {
509 /* Check the parameters */
510 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
511 assert_param(IS_FMC_NORSRAM_BANK(Bank));
512
513 /* Enable write operation */
514 SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
515
516 return HAL_OK;
517 }
518
519 /**
520 * @brief Disables dynamically FMC_NORSRAM write operation.
521 * @param Device Pointer to NORSRAM device instance
522 * @param Bank NORSRAM bank number
523 * @retval HAL status
524 */
FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef * Device,uint32_t Bank)525 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
526 {
527 /* Check the parameters */
528 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
529 assert_param(IS_FMC_NORSRAM_BANK(Bank));
530
531 /* Disable write operation */
532 CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
533
534 return HAL_OK;
535 }
536
537 /**
538 * @}
539 */
540
541 /**
542 * @}
543 */
544 #endif /* FMC_Bank1 */
545
546 #if defined(FMC_Bank3) || defined(FMC_Bank2_3)
547
548 /** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions
549 * @brief NAND Controller functions
550 *
551 @verbatim
552 ==============================================================================
553 ##### How to use NAND device driver #####
554 ==============================================================================
555 [..]
556 This driver contains a set of APIs to interface with the FMC NAND banks in order
557 to run the NAND external devices.
558
559 (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
560 (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
561 (+) FMC NAND bank common space timing configuration using the function
562 FMC_NAND_CommonSpace_Timing_Init()
563 (+) FMC NAND bank attribute space timing configuration using the function
564 FMC_NAND_AttributeSpace_Timing_Init()
565 (+) FMC NAND bank enable/disable ECC correction feature using the functions
566 FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
567 (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
568
569 @endverbatim
570 * @{
571 */
572
573 /** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
574 * @brief Initialization and Configuration functions
575 *
576 @verbatim
577 ==============================================================================
578 ##### Initialization and de_initialization functions #####
579 ==============================================================================
580 [..]
581 This section provides functions allowing to:
582 (+) Initialize and configure the FMC NAND interface
583 (+) De-initialize the FMC NAND interface
584 (+) Configure the FMC clock and associated GPIOs
585
586 @endverbatim
587 * @{
588 */
589
590 /**
591 * @brief Initializes the FMC_NAND device according to the specified
592 * control parameters in the FMC_NAND_HandleTypeDef
593 * @param Device Pointer to NAND device instance
594 * @param Init Pointer to NAND Initialization structure
595 * @retval HAL status
596 */
FMC_NAND_Init(FMC_NAND_TypeDef * Device,FMC_NAND_InitTypeDef * Init)597 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
598 {
599 /* Check the parameters */
600 assert_param(IS_FMC_NAND_DEVICE(Device));
601 assert_param(IS_FMC_NAND_BANK(Init->NandBank));
602 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
603 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
604 assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
605 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
606 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
607 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
608
609 #if defined(FMC_Bank2_3)
610 /* Set NAND device control parameters */
611 if (Init->NandBank == FMC_NAND_BANK2)
612 {
613 /* NAND bank 2 registers configuration */
614 MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature |
615 FMC_PCR_MEMORY_TYPE_NAND |
616 Init->MemoryDataWidth |
617 Init->EccComputation |
618 Init->ECCPageSize |
619 ((Init->TCLRSetupTime) << FMC_PCR2_TCLR_Pos) |
620 ((Init->TARSetupTime) << FMC_PCR2_TAR_Pos)));
621 }
622 else
623 {
624 /* NAND bank 3 registers configuration */
625 MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature |
626 FMC_PCR_MEMORY_TYPE_NAND |
627 Init->MemoryDataWidth |
628 Init->EccComputation |
629 Init->ECCPageSize |
630 ((Init->TCLRSetupTime) << FMC_PCR2_TCLR_Pos) |
631 ((Init->TARSetupTime) << FMC_PCR2_TAR_Pos)));
632 }
633 #else
634 /* NAND bank 3 registers configuration */
635 MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature |
636 FMC_PCR_MEMORY_TYPE_NAND |
637 Init->MemoryDataWidth |
638 Init->EccComputation |
639 Init->ECCPageSize |
640 ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos) |
641 ((Init->TARSetupTime) << FMC_PCR_TAR_Pos)));
642 #endif
643
644 return HAL_OK;
645 }
646
647 /**
648 * @brief Initializes the FMC_NAND Common space Timing according to the specified
649 * parameters in the FMC_NAND_PCC_TimingTypeDef
650 * @param Device Pointer to NAND device instance
651 * @param Timing Pointer to NAND timing structure
652 * @param Bank NAND bank number
653 * @retval HAL status
654 */
FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef * Device,FMC_NAND_PCC_TimingTypeDef * Timing,uint32_t Bank)655 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
656 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
657 {
658 /* Check the parameters */
659 assert_param(IS_FMC_NAND_DEVICE(Device));
660 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
661 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
662 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
663 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
664 assert_param(IS_FMC_NAND_BANK(Bank));
665
666 #if defined(FMC_Bank2_3)
667 /* Set FMC_NAND device timing parameters */
668 if (Bank == FMC_NAND_BANK2)
669 {
670 /* NAND bank 2 registers configuration */
671 MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime |
672 ((Timing->WaitSetupTime) << FMC_PMEM2_MEMWAIT2_Pos) |
673 ((Timing->HoldSetupTime) << FMC_PMEM2_MEMHOLD2_Pos) |
674 ((Timing->HiZSetupTime) << FMC_PMEM2_MEMHIZ2_Pos)));
675 }
676 else
677 {
678 /* NAND bank 3 registers configuration */
679 MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime |
680 ((Timing->WaitSetupTime) << FMC_PMEM2_MEMWAIT2_Pos) |
681 ((Timing->HoldSetupTime) << FMC_PMEM2_MEMHOLD2_Pos) |
682 ((Timing->HiZSetupTime) << FMC_PMEM2_MEMHIZ2_Pos)));
683 }
684 #else
685 /* Prevent unused argument(s) compilation warning if no assert_param check */
686 UNUSED(Bank);
687
688 /* NAND bank 3 registers configuration */
689 MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime |
690 ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT2_Pos) |
691 ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD2_Pos) |
692 ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ2_Pos)));
693 #endif
694
695 return HAL_OK;
696 }
697
698 /**
699 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
700 * parameters in the FMC_NAND_PCC_TimingTypeDef
701 * @param Device Pointer to NAND device instance
702 * @param Timing Pointer to NAND timing structure
703 * @param Bank NAND bank number
704 * @retval HAL status
705 */
FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef * Device,FMC_NAND_PCC_TimingTypeDef * Timing,uint32_t Bank)706 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
707 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
708 {
709 /* Check the parameters */
710 assert_param(IS_FMC_NAND_DEVICE(Device));
711 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
712 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
713 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
714 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
715 assert_param(IS_FMC_NAND_BANK(Bank));
716
717 #if defined(FMC_Bank2_3)
718 /* Set FMC_NAND device timing parameters */
719 if (Bank == FMC_NAND_BANK2)
720 {
721 /* NAND bank 2 registers configuration */
722 MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime |
723 ((Timing->WaitSetupTime) << FMC_PATT2_ATTWAIT2_Pos) |
724 ((Timing->HoldSetupTime) << FMC_PATT2_ATTHOLD2_Pos) |
725 ((Timing->HiZSetupTime) << FMC_PATT2_ATTHIZ2_Pos)));
726 }
727 else
728 {
729 /* NAND bank 3 registers configuration */
730 MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime |
731 ((Timing->WaitSetupTime) << FMC_PATT2_ATTWAIT2_Pos) |
732 ((Timing->HoldSetupTime) << FMC_PATT2_ATTHOLD2_Pos) |
733 ((Timing->HiZSetupTime) << FMC_PATT2_ATTHIZ2_Pos)));
734 }
735 #else
736 /* Prevent unused argument(s) compilation warning if no assert_param check */
737 UNUSED(Bank);
738
739 /* NAND bank 3 registers configuration */
740 MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime |
741 ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT2_Pos) |
742 ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD2_Pos) |
743 ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ2_Pos)));
744 #endif
745
746 return HAL_OK;
747 }
748
749 /**
750 * @brief DeInitializes the FMC_NAND device
751 * @param Device Pointer to NAND device instance
752 * @param Bank NAND bank number
753 * @retval HAL status
754 */
FMC_NAND_DeInit(FMC_NAND_TypeDef * Device,uint32_t Bank)755 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
756 {
757 /* Check the parameters */
758 assert_param(IS_FMC_NAND_DEVICE(Device));
759 assert_param(IS_FMC_NAND_BANK(Bank));
760
761 /* Disable the NAND Bank */
762 __FMC_NAND_DISABLE(Device, Bank);
763
764 /* De-initialize the NAND Bank */
765 #if defined(FMC_Bank2_3)
766 if (Bank == FMC_NAND_BANK2)
767 {
768 /* Set the FMC_NAND_BANK2 registers to their reset values */
769 WRITE_REG(Device->PCR2, 0x00000018U);
770 WRITE_REG(Device->SR2, 0x00000040U);
771 WRITE_REG(Device->PMEM2, 0xFCFCFCFCU);
772 WRITE_REG(Device->PATT2, 0xFCFCFCFCU);
773 }
774 /* FMC_Bank3_NAND */
775 else
776 {
777 /* Set the FMC_NAND_BANK3 registers to their reset values */
778 WRITE_REG(Device->PCR3, 0x00000018U);
779 WRITE_REG(Device->SR3, 0x00000040U);
780 WRITE_REG(Device->PMEM3, 0xFCFCFCFCU);
781 WRITE_REG(Device->PATT3, 0xFCFCFCFCU);
782 }
783 #else
784 /* Prevent unused argument(s) compilation warning if no assert_param check */
785 UNUSED(Bank);
786
787 /* Set the FMC_NAND_BANK3 registers to their reset values */
788 WRITE_REG(Device->PCR, 0x00000018U);
789 WRITE_REG(Device->SR, 0x00000040U);
790 WRITE_REG(Device->PMEM, 0xFCFCFCFCU);
791 WRITE_REG(Device->PATT, 0xFCFCFCFCU);
792 #endif
793
794 return HAL_OK;
795 }
796
797 /**
798 * @}
799 */
800
801 /** @defgroup HAL_FMC_NAND_Group2 Peripheral Control functions
802 * @brief management functions
803 *
804 @verbatim
805 ==============================================================================
806 ##### FMC_NAND Control functions #####
807 ==============================================================================
808 [..]
809 This subsection provides a set of functions allowing to control dynamically
810 the FMC NAND interface.
811
812 @endverbatim
813 * @{
814 */
815
816
817 /**
818 * @brief Enables dynamically FMC_NAND ECC feature.
819 * @param Device Pointer to NAND device instance
820 * @param Bank NAND bank number
821 * @retval HAL status
822 */
FMC_NAND_ECC_Enable(FMC_NAND_TypeDef * Device,uint32_t Bank)823 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
824 {
825 /* Check the parameters */
826 assert_param(IS_FMC_NAND_DEVICE(Device));
827 assert_param(IS_FMC_NAND_BANK(Bank));
828
829 /* Enable ECC feature */
830 #if defined(FMC_Bank2_3)
831 if (Bank == FMC_NAND_BANK2)
832 {
833 SET_BIT(Device->PCR2, FMC_PCR2_ECCEN);
834 }
835 else
836 {
837 SET_BIT(Device->PCR3, FMC_PCR2_ECCEN);
838 }
839 #else
840 /* Prevent unused argument(s) compilation warning if no assert_param check */
841 UNUSED(Bank);
842
843 SET_BIT(Device->PCR, FMC_PCR_ECCEN);
844 #endif
845
846 return HAL_OK;
847 }
848
849
850 /**
851 * @brief Disables dynamically FMC_NAND ECC feature.
852 * @param Device Pointer to NAND device instance
853 * @param Bank NAND bank number
854 * @retval HAL status
855 */
FMC_NAND_ECC_Disable(FMC_NAND_TypeDef * Device,uint32_t Bank)856 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
857 {
858 /* Check the parameters */
859 assert_param(IS_FMC_NAND_DEVICE(Device));
860 assert_param(IS_FMC_NAND_BANK(Bank));
861
862 /* Disable ECC feature */
863 #if defined(FMC_Bank2_3)
864 if (Bank == FMC_NAND_BANK2)
865 {
866 CLEAR_BIT(Device->PCR2, FMC_PCR2_ECCEN);
867 }
868 else
869 {
870 CLEAR_BIT(Device->PCR3, FMC_PCR2_ECCEN);
871 }
872 #else
873 /* Prevent unused argument(s) compilation warning if no assert_param check */
874 UNUSED(Bank);
875
876 CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN);
877 #endif
878
879 return HAL_OK;
880 }
881
882 /**
883 * @brief Disables dynamically FMC_NAND ECC feature.
884 * @param Device Pointer to NAND device instance
885 * @param ECCval Pointer to ECC value
886 * @param Bank NAND bank number
887 * @param Timeout Timeout wait value
888 * @retval HAL status
889 */
FMC_NAND_GetECC(FMC_NAND_TypeDef * Device,uint32_t * ECCval,uint32_t Bank,uint32_t Timeout)890 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
891 uint32_t Timeout)
892 {
893 uint32_t tickstart;
894
895 /* Check the parameters */
896 assert_param(IS_FMC_NAND_DEVICE(Device));
897 assert_param(IS_FMC_NAND_BANK(Bank));
898
899 /* Get tick */
900 tickstart = HAL_GetTick();
901
902 /* Wait until FIFO is empty */
903 while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
904 {
905 /* Check for the Timeout */
906 if (Timeout != HAL_MAX_DELAY)
907 {
908 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
909 {
910 return HAL_TIMEOUT;
911 }
912 }
913 }
914
915 #if defined(FMC_Bank2_3)
916 if (Bank == FMC_NAND_BANK2)
917 {
918 /* Get the ECCR2 register value */
919 *ECCval = (uint32_t)Device->ECCR2;
920 }
921 else
922 {
923 /* Get the ECCR3 register value */
924 *ECCval = (uint32_t)Device->ECCR3;
925 }
926 #else
927 /* Prevent unused argument(s) compilation warning if no assert_param check */
928 UNUSED(Bank);
929
930 /* Get the ECCR register value */
931 *ECCval = (uint32_t)Device->ECCR;
932 #endif
933
934 return HAL_OK;
935 }
936
937 /**
938 * @}
939 */
940 #endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
941
942 #if defined(FMC_Bank4)
943
944 /** @addtogroup FMC_LL_PCCARD
945 * @brief PCCARD Controller functions
946 *
947 @verbatim
948 ==============================================================================
949 ##### How to use PCCARD device driver #####
950 ==============================================================================
951 [..]
952 This driver contains a set of APIs to interface with the FMC PCCARD bank in order
953 to run the PCCARD/compact flash external devices.
954
955 (+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit()
956 (+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init()
957 (+) FMC PCCARD bank common space timing configuration using the function
958 FMC_PCCARD_CommonSpace_Timing_Init()
959 (+) FMC PCCARD bank attribute space timing configuration using the function
960 FMC_PCCARD_AttributeSpace_Timing_Init()
961 (+) FMC PCCARD bank IO space timing configuration using the function
962 FMC_PCCARD_IOSpace_Timing_Init()
963 @endverbatim
964 * @{
965 */
966
967 /** @addtogroup FMC_LL_PCCARD_Private_Functions_Group1
968 * @brief Initialization and Configuration functions
969 *
970 @verbatim
971 ==============================================================================
972 ##### Initialization and de_initialization functions #####
973 ==============================================================================
974 [..]
975 This section provides functions allowing to:
976 (+) Initialize and configure the FMC PCCARD interface
977 (+) De-initialize the FMC PCCARD interface
978 (+) Configure the FMC clock and associated GPIOs
979
980 @endverbatim
981 * @{
982 */
983
984 /**
985 * @brief Initializes the FMC_PCCARD device according to the specified
986 * control parameters in the FMC_PCCARD_HandleTypeDef
987 * @param Device Pointer to PCCARD device instance
988 * @param Init Pointer to PCCARD Initialization structure
989 * @retval HAL status
990 */
FMC_PCCARD_Init(FMC_PCCARD_TypeDef * Device,FMC_PCCARD_InitTypeDef * Init)991 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init)
992 {
993 /* Check the parameters */
994 assert_param(IS_FMC_PCCARD_DEVICE(Device));
995 #if defined(FMC_Bank3) || defined(FMC_Bank2_3)
996 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
997 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
998 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
999 #endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
1000
1001 /* Set FMC_PCCARD device control parameters */
1002 MODIFY_REG(Device->PCR4,
1003 (FMC_PCR4_PTYP |
1004 FMC_PCR4_PWAITEN |
1005 FMC_PCR4_PWID |
1006 FMC_PCR4_TCLR |
1007 FMC_PCR4_TAR),
1008 (FMC_PCR_MEMORY_TYPE_PCCARD |
1009 Init->Waitfeature |
1010 FMC_NAND_PCC_MEM_BUS_WIDTH_16 |
1011 (Init->TCLRSetupTime << FMC_PCR4_TCLR_Pos) |
1012 (Init->TARSetupTime << FMC_PCR4_TAR_Pos)));
1013
1014 return HAL_OK;
1015 }
1016
1017 /**
1018 * @brief Initializes the FMC_PCCARD Common space Timing according to the specified
1019 * parameters in the FMC_NAND_PCC_TimingTypeDef
1020 * @param Device Pointer to PCCARD device instance
1021 * @param Timing Pointer to PCCARD timing structure
1022 * @retval HAL status
1023 */
FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef * Device,FMC_NAND_PCC_TimingTypeDef * Timing)1024 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
1025 FMC_NAND_PCC_TimingTypeDef *Timing)
1026 {
1027 /* Check the parameters */
1028 assert_param(IS_FMC_PCCARD_DEVICE(Device));
1029 #if defined(FMC_Bank3) || defined(FMC_Bank2_3)
1030 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
1031 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
1032 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
1033 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
1034 #endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
1035
1036 /* Set PCCARD timing parameters */
1037 MODIFY_REG(Device->PMEM4, PMEM4_CLEAR_MASK,
1038 (Timing->SetupTime |
1039 ((Timing->WaitSetupTime) << FMC_PMEM4_MEMWAIT4_Pos) |
1040 ((Timing->HoldSetupTime) << FMC_PMEM4_MEMHOLD4_Pos) |
1041 ((Timing->HiZSetupTime) << FMC_PMEM4_MEMHIZ4_Pos)));
1042
1043 return HAL_OK;
1044 }
1045
1046 /**
1047 * @brief Initializes the FMC_PCCARD Attribute space Timing according to the specified
1048 * parameters in the FMC_NAND_PCC_TimingTypeDef
1049 * @param Device Pointer to PCCARD device instance
1050 * @param Timing Pointer to PCCARD timing structure
1051 * @retval HAL status
1052 */
FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef * Device,FMC_NAND_PCC_TimingTypeDef * Timing)1053 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
1054 FMC_NAND_PCC_TimingTypeDef *Timing)
1055 {
1056 /* Check the parameters */
1057 assert_param(IS_FMC_PCCARD_DEVICE(Device));
1058 #if defined(FMC_Bank3) || defined(FMC_Bank2_3)
1059 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
1060 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
1061 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
1062 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
1063 #endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
1064
1065 /* Set PCCARD timing parameters */
1066 MODIFY_REG(Device->PATT4, PATT4_CLEAR_MASK,
1067 (Timing->SetupTime |
1068 ((Timing->WaitSetupTime) << FMC_PATT4_ATTWAIT4_Pos) |
1069 ((Timing->HoldSetupTime) << FMC_PATT4_ATTHOLD4_Pos) |
1070 ((Timing->HiZSetupTime) << FMC_PATT4_ATTHIZ4_Pos)));
1071
1072 return HAL_OK;
1073 }
1074
1075 /**
1076 * @brief Initializes the FMC_PCCARD IO space Timing according to the specified
1077 * parameters in the FMC_NAND_PCC_TimingTypeDef
1078 * @param Device Pointer to PCCARD device instance
1079 * @param Timing Pointer to PCCARD timing structure
1080 * @retval HAL status
1081 */
FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef * Device,FMC_NAND_PCC_TimingTypeDef * Timing)1082 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
1083 FMC_NAND_PCC_TimingTypeDef *Timing)
1084 {
1085 /* Check the parameters */
1086 assert_param(IS_FMC_PCCARD_DEVICE(Device));
1087 #if defined(FMC_Bank3) || defined(FMC_Bank2_3)
1088 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
1089 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
1090 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
1091 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
1092 #endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
1093
1094 /* Set FMC_PCCARD device timing parameters */
1095 MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK,
1096 (Timing->SetupTime |
1097 (Timing->WaitSetupTime << FMC_PIO4_IOWAIT4_Pos) |
1098 (Timing->HoldSetupTime << FMC_PIO4_IOHOLD4_Pos) |
1099 (Timing->HiZSetupTime << FMC_PIO4_IOHIZ4_Pos)));
1100
1101 return HAL_OK;
1102 }
1103
1104 /**
1105 * @brief DeInitializes the FMC_PCCARD device
1106 * @param Device Pointer to PCCARD device instance
1107 * @retval HAL status
1108 */
FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef * Device)1109 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
1110 {
1111 /* Check the parameters */
1112 assert_param(IS_FMC_PCCARD_DEVICE(Device));
1113
1114 /* Disable the FMC_PCCARD device */
1115 __FMC_PCCARD_DISABLE(Device);
1116
1117 /* De-initialize the FMC_PCCARD device */
1118 Device->PCR4 = 0x00000018U;
1119 Device->SR4 = 0x00000040U;
1120 Device->PMEM4 = 0xFCFCFCFCU;
1121 Device->PATT4 = 0xFCFCFCFCU;
1122 Device->PIO4 = 0xFCFCFCFCU;
1123
1124 return HAL_OK;
1125 }
1126
1127 /**
1128 * @}
1129 */
1130 #endif /* FMC_Bank4 */
1131
1132 #if defined(FMC_Bank5_6)
1133
1134 /** @defgroup FMC_LL_SDRAM
1135 * @brief SDRAM Controller functions
1136 *
1137 @verbatim
1138 ==============================================================================
1139 ##### How to use SDRAM device driver #####
1140 ==============================================================================
1141 [..]
1142 This driver contains a set of APIs to interface with the FMC SDRAM banks in order
1143 to run the SDRAM external devices.
1144
1145 (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
1146 (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
1147 (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
1148 (+) FMC SDRAM bank enable/disable write operation using the functions
1149 FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
1150 (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
1151
1152 @endverbatim
1153 * @{
1154 */
1155
1156 /** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1
1157 * @brief Initialization and Configuration functions
1158 *
1159 @verbatim
1160 ==============================================================================
1161 ##### Initialization and de_initialization functions #####
1162 ==============================================================================
1163 [..]
1164 This section provides functions allowing to:
1165 (+) Initialize and configure the FMC SDRAM interface
1166 (+) De-initialize the FMC SDRAM interface
1167 (+) Configure the FMC clock and associated GPIOs
1168
1169 @endverbatim
1170 * @{
1171 */
1172
1173 /**
1174 * @brief Initializes the FMC_SDRAM device according to the specified
1175 * control parameters in the FMC_SDRAM_InitTypeDef
1176 * @param Device Pointer to SDRAM device instance
1177 * @param Init Pointer to SDRAM Initialization structure
1178 * @retval HAL status
1179 */
FMC_SDRAM_Init(FMC_SDRAM_TypeDef * Device,FMC_SDRAM_InitTypeDef * Init)1180 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
1181 {
1182 /* Check the parameters */
1183 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1184 assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
1185 assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
1186 assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
1187 assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
1188 assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
1189 assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
1190 assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
1191 assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
1192 assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
1193 assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
1194
1195 /* Set SDRAM bank configuration parameters */
1196 if (Init->SDBank == FMC_SDRAM_BANK1)
1197 {
1198 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
1199 SDCR_CLEAR_MASK,
1200 (Init->ColumnBitsNumber |
1201 Init->RowBitsNumber |
1202 Init->MemoryDataWidth |
1203 Init->InternalBankNumber |
1204 Init->CASLatency |
1205 Init->WriteProtection |
1206 Init->SDClockPeriod |
1207 Init->ReadBurst |
1208 Init->ReadPipeDelay));
1209 }
1210 else /* FMC_Bank2_SDRAM */
1211 {
1212 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
1213 FMC_SDCR1_SDCLK |
1214 FMC_SDCR1_RBURST |
1215 FMC_SDCR1_RPIPE,
1216 (Init->SDClockPeriod |
1217 Init->ReadBurst |
1218 Init->ReadPipeDelay));
1219
1220 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2],
1221 SDCR_CLEAR_MASK,
1222 (Init->ColumnBitsNumber |
1223 Init->RowBitsNumber |
1224 Init->MemoryDataWidth |
1225 Init->InternalBankNumber |
1226 Init->CASLatency |
1227 Init->WriteProtection));
1228 }
1229
1230 return HAL_OK;
1231 }
1232
1233
1234 /**
1235 * @brief Initializes the FMC_SDRAM device timing according to the specified
1236 * parameters in the FMC_SDRAM_TimingTypeDef
1237 * @param Device Pointer to SDRAM device instance
1238 * @param Timing Pointer to SDRAM Timing structure
1239 * @param Bank SDRAM bank number
1240 * @retval HAL status
1241 */
FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef * Device,FMC_SDRAM_TimingTypeDef * Timing,uint32_t Bank)1242 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device,
1243 FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
1244 {
1245 /* Check the parameters */
1246 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1247 assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
1248 assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
1249 assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
1250 assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
1251 assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
1252 assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
1253 assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
1254 assert_param(IS_FMC_SDRAM_BANK(Bank));
1255
1256 /* Set SDRAM device timing parameters */
1257 if (Bank == FMC_SDRAM_BANK1)
1258 {
1259 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],
1260 SDTR_CLEAR_MASK,
1261 (((Timing->LoadToActiveDelay) - 1U) |
1262 (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTR1_TXSR_Pos) |
1263 (((Timing->SelfRefreshTime) - 1U) << FMC_SDTR1_TRAS_Pos) |
1264 (((Timing->RowCycleDelay) - 1U) << FMC_SDTR1_TRC_Pos) |
1265 (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) |
1266 (((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos) |
1267 (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos)));
1268 }
1269 else /* FMC_Bank2_SDRAM */
1270 {
1271 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],
1272 FMC_SDTR1_TRC |
1273 FMC_SDTR1_TRP,
1274 (((Timing->RowCycleDelay) - 1U) << FMC_SDTR1_TRC_Pos) |
1275 (((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos));
1276
1277 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2],
1278 SDTR_CLEAR_MASK,
1279 (((Timing->LoadToActiveDelay) - 1U) |
1280 (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTR1_TXSR_Pos) |
1281 (((Timing->SelfRefreshTime) - 1U) << FMC_SDTR1_TRAS_Pos) |
1282 (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) |
1283 (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos)));
1284 }
1285
1286 return HAL_OK;
1287 }
1288
1289 /**
1290 * @brief DeInitializes the FMC_SDRAM peripheral
1291 * @param Device Pointer to SDRAM device instance
1292 * @retval HAL status
1293 */
FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef * Device,uint32_t Bank)1294 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1295 {
1296 /* Check the parameters */
1297 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1298 assert_param(IS_FMC_SDRAM_BANK(Bank));
1299
1300 /* De-initialize the SDRAM device */
1301 Device->SDCR[Bank] = 0x000002D0U;
1302 Device->SDTR[Bank] = 0x0FFFFFFFU;
1303 Device->SDCMR = 0x00000000U;
1304 Device->SDRTR = 0x00000000U;
1305 Device->SDSR = 0x00000000U;
1306
1307 return HAL_OK;
1308 }
1309
1310 /**
1311 * @}
1312 */
1313
1314 /** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2
1315 * @brief management functions
1316 *
1317 @verbatim
1318 ==============================================================================
1319 ##### FMC_SDRAM Control functions #####
1320 ==============================================================================
1321 [..]
1322 This subsection provides a set of functions allowing to control dynamically
1323 the FMC SDRAM interface.
1324
1325 @endverbatim
1326 * @{
1327 */
1328
1329 /**
1330 * @brief Enables dynamically FMC_SDRAM write protection.
1331 * @param Device Pointer to SDRAM device instance
1332 * @param Bank SDRAM bank number
1333 * @retval HAL status
1334 */
FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef * Device,uint32_t Bank)1335 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1336 {
1337 /* Check the parameters */
1338 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1339 assert_param(IS_FMC_SDRAM_BANK(Bank));
1340
1341 /* Enable write protection */
1342 SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);
1343
1344 return HAL_OK;
1345 }
1346
1347 /**
1348 * @brief Disables dynamically FMC_SDRAM write protection.
1349 * @param hsdram FMC_SDRAM handle
1350 * @retval HAL status
1351 */
FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef * Device,uint32_t Bank)1352 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1353 {
1354 /* Check the parameters */
1355 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1356 assert_param(IS_FMC_SDRAM_BANK(Bank));
1357
1358 /* Disable write protection */
1359 CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);
1360
1361 return HAL_OK;
1362 }
1363
1364 /**
1365 * @brief Send Command to the FMC SDRAM bank
1366 * @param Device Pointer to SDRAM device instance
1367 * @param Command Pointer to SDRAM command structure
1368 * @param Timing Pointer to SDRAM Timing structure
1369 * @param Timeout Timeout wait value
1370 * @retval HAL state
1371 */
FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef * Device,FMC_SDRAM_CommandTypeDef * Command,uint32_t Timeout)1372 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device,
1373 FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
1374 {
1375 uint32_t tickstart = 0U;
1376 /* Check the parameters */
1377 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1378 assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
1379 assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
1380 assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
1381 assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
1382
1383 /* Set command register */
1384 MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | FMC_SDCMR_NRFS | FMC_SDCMR_MRD),
1385 ((Command->CommandMode) | (Command->CommandTarget) |
1386 (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) |
1387 ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos)));
1388 /* Get tick */
1389 tickstart = HAL_GetTick();
1390
1391 /* wait until command is send */
1392 while (HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))
1393 {
1394 /* Check for the Timeout */
1395 if (Timeout != HAL_MAX_DELAY)
1396 {
1397 if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
1398 {
1399 return HAL_TIMEOUT;
1400 }
1401 }
1402 }
1403 return HAL_OK;
1404 }
1405
1406 /**
1407 * @brief Program the SDRAM Memory Refresh rate.
1408 * @param Device Pointer to SDRAM device instance
1409 * @param RefreshRate The SDRAM refresh rate value.
1410 * @retval HAL state
1411 */
FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef * Device,uint32_t RefreshRate)1412 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
1413 {
1414 /* Check the parameters */
1415 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1416 assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
1417
1418 /* Set the refresh rate in command register */
1419 MODIFY_REG(Device->SDRTR, FMC_SDRTR_COUNT, (RefreshRate << FMC_SDRTR_COUNT_Pos));
1420
1421 return HAL_OK;
1422 }
1423
1424 /**
1425 * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands.
1426 * @param Device Pointer to SDRAM device instance
1427 * @param AutoRefreshNumber Specifies the auto Refresh number.
1428 * @retval None
1429 */
FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef * Device,uint32_t AutoRefreshNumber)1430 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device,
1431 uint32_t AutoRefreshNumber)
1432 {
1433 /* Check the parameters */
1434 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1435 assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
1436
1437 /* Set the Auto-refresh number in command register */
1438 MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos));
1439
1440 return HAL_OK;
1441 }
1442
1443 /**
1444 * @brief Returns the indicated FMC SDRAM bank mode status.
1445 * @param Device Pointer to SDRAM device instance
1446 * @param Bank Defines the FMC SDRAM bank. This parameter can be
1447 * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
1448 * @retval The FMC SDRAM bank mode status, could be on of the following values:
1449 * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
1450 * FMC_SDRAM_POWER_DOWN_MODE.
1451 */
FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef * Device,uint32_t Bank)1452 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1453 {
1454 uint32_t tmpreg;
1455
1456 /* Check the parameters */
1457 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1458 assert_param(IS_FMC_SDRAM_BANK(Bank));
1459
1460 /* Get the corresponding bank mode */
1461 if (Bank == FMC_SDRAM_BANK1)
1462 {
1463 tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
1464 }
1465 else
1466 {
1467 tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U);
1468 }
1469
1470 /* Return the mode status */
1471 return tmpreg;
1472 }
1473
1474 /**
1475 * @}
1476 */
1477
1478 /**
1479 * @}
1480 */
1481
1482 #endif /* FMC_Bank5_6 */
1483
1484 /**
1485 * @}
1486 */
1487
1488 /**
1489 * @}
1490 */
1491
1492 #endif /* HAL_NOR_MODULE_ENABLED */
1493 /**
1494 * @}
1495 */
1496 /**
1497 * @}
1498 */
1499
