1 /**
2   ******************************************************************************
3   * @file    stm32f103xe.h
4   * @author  MCD Application Team
5   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
6   *          This file contains all the peripheral register's definitions, bits
7   *          definitions and memory mapping for STM32F1xx devices.
8   *
9   *          This file contains:
10   *           - Data structures and the address mapping for all peripherals
11   *           - Peripheral's registers declarations and bits definition
12   *           - Macros to access peripheral�s registers hardware
13   *
14   ******************************************************************************
15   * @attention
16   *
17   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
18   * All rights reserved.</center></h2>
19   *
20   * This software component is licensed by ST under BSD 3-Clause license,
21   * the "License"; You may not use this file except in compliance with the
22   * License. You may obtain a copy of the License at:
23   *                        opensource.org/licenses/BSD-3-Clause
24   *
25   ******************************************************************************
26   */
27 
28 
29 /** @addtogroup CMSIS
30   * @{
31   */
32 
33 /** @addtogroup stm32f103xe
34   * @{
35   */
36 
37 #ifndef __STM32F103xE_H
38 #define __STM32F103xE_H
39 
40 #ifdef __cplusplus
41  extern "C" {
42 #endif
43 
44 /** @addtogroup Configuration_section_for_CMSIS
45   * @{
46   */
47 /**
48   * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
49  */
50 #define __CM3_REV                  0x0200U  /*!< Core Revision r2p0                           */
51  #define __MPU_PRESENT             0U       /*!< Other STM32 devices does not provide an MPU  */
52 #define __NVIC_PRIO_BITS           4U       /*!< STM32 uses 4 Bits for the Priority Levels    */
53 #define __Vendor_SysTickConfig     0U       /*!< Set to 1 if different SysTick Config is used */
54 
55 /**
56   * @}
57   */
58 
59 /** @addtogroup Peripheral_interrupt_number_definition
60   * @{
61   */
62 
63 /**
64  * @brief STM32F10x Interrupt Number Definition, according to the selected device
65  *        in @ref Library_configuration_section
66  */
67 
68  /*!< Interrupt Number Definition */
69 typedef enum
70 {
71 /******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
72   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                             */
73   HardFault_IRQn              = -13,    /*!< 3 Cortex-M3 Hard Fault Interrupt                     */
74   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt              */
75   BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                      */
76   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                    */
77   SVCall_IRQn                 = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                       */
78   DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                 */
79   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                       */
80   SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                   */
81 
82 /******  STM32 specific Interrupt Numbers *********************************************************/
83   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                            */
84   PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt            */
85   TAMPER_IRQn                 = 2,      /*!< Tamper Interrupt                                     */
86   RTC_IRQn                    = 3,      /*!< RTC global Interrupt                                 */
87   FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                               */
88   RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                 */
89   EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                 */
90   EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                 */
91   EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                 */
92   EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                 */
93   EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                 */
94   DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                      */
95   DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                      */
96   DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                      */
97   DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                      */
98   DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                      */
99   DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                      */
100   DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                      */
101   ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
102   USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
103   USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
104   CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
105   CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
106   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
107   TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
108   TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
109   TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
110   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
111   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
112   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
113   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
114   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
115   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
116   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
117   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
118   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
119   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
120   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
121   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
122   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
123   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
124   RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
125   USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
126   TIM8_BRK_IRQn               = 43,     /*!< TIM8 Break Interrupt                                 */
127   TIM8_UP_IRQn                = 44,     /*!< TIM8 Update Interrupt                                */
128   TIM8_TRG_COM_IRQn           = 45,     /*!< TIM8 Trigger and Commutation Interrupt               */
129   TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                       */
130   ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
131   FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                */
132   SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                */
133   TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */
134   SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
135   UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
136   UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
137   TIM6_IRQn                   = 54,     /*!< TIM6 global Interrupt                                */
138   TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                */
139   DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
140   DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
141   DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
142   DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
143 } IRQn_Type;
144 
145 /**
146   * @}
147   */
148 
149 #include "core_cm3.h"
150 #include "system_stm32f1xx.h"
151 #include <stdint.h>
152 
153 /** @addtogroup Peripheral_registers_structures
154   * @{
155   */
156 
157 /**
158   * @brief Analog to Digital Converter
159   */
160 
161 typedef struct
162 {
163   __IO uint32_t SR;
164   __IO uint32_t CR1;
165   __IO uint32_t CR2;
166   __IO uint32_t SMPR1;
167   __IO uint32_t SMPR2;
168   __IO uint32_t JOFR1;
169   __IO uint32_t JOFR2;
170   __IO uint32_t JOFR3;
171   __IO uint32_t JOFR4;
172   __IO uint32_t HTR;
173   __IO uint32_t LTR;
174   __IO uint32_t SQR1;
175   __IO uint32_t SQR2;
176   __IO uint32_t SQR3;
177   __IO uint32_t JSQR;
178   __IO uint32_t JDR1;
179   __IO uint32_t JDR2;
180   __IO uint32_t JDR3;
181   __IO uint32_t JDR4;
182   __IO uint32_t DR;
183 } ADC_TypeDef;
184 
185 typedef struct
186 {
187   __IO uint32_t SR;               /*!< ADC status register,    used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address         */
188   __IO uint32_t CR1;              /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04  */
189   __IO uint32_t CR2;              /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08  */
190   uint32_t  RESERVED[16];
191   __IO uint32_t DR;               /*!< ADC data register,      used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C  */
192 } ADC_Common_TypeDef;
193 
194 /**
195   * @brief Backup Registers
196   */
197 
198 typedef struct
199 {
200   uint32_t  RESERVED0;
201   __IO uint32_t DR1;
202   __IO uint32_t DR2;
203   __IO uint32_t DR3;
204   __IO uint32_t DR4;
205   __IO uint32_t DR5;
206   __IO uint32_t DR6;
207   __IO uint32_t DR7;
208   __IO uint32_t DR8;
209   __IO uint32_t DR9;
210   __IO uint32_t DR10;
211   __IO uint32_t RTCCR;
212   __IO uint32_t CR;
213   __IO uint32_t CSR;
214   uint32_t  RESERVED13[2];
215   __IO uint32_t DR11;
216   __IO uint32_t DR12;
217   __IO uint32_t DR13;
218   __IO uint32_t DR14;
219   __IO uint32_t DR15;
220   __IO uint32_t DR16;
221   __IO uint32_t DR17;
222   __IO uint32_t DR18;
223   __IO uint32_t DR19;
224   __IO uint32_t DR20;
225   __IO uint32_t DR21;
226   __IO uint32_t DR22;
227   __IO uint32_t DR23;
228   __IO uint32_t DR24;
229   __IO uint32_t DR25;
230   __IO uint32_t DR26;
231   __IO uint32_t DR27;
232   __IO uint32_t DR28;
233   __IO uint32_t DR29;
234   __IO uint32_t DR30;
235   __IO uint32_t DR31;
236   __IO uint32_t DR32;
237   __IO uint32_t DR33;
238   __IO uint32_t DR34;
239   __IO uint32_t DR35;
240   __IO uint32_t DR36;
241   __IO uint32_t DR37;
242   __IO uint32_t DR38;
243   __IO uint32_t DR39;
244   __IO uint32_t DR40;
245   __IO uint32_t DR41;
246   __IO uint32_t DR42;
247 } BKP_TypeDef;
248 
249 /**
250   * @brief Controller Area Network TxMailBox
251   */
252 
253 typedef struct
254 {
255   __IO uint32_t TIR;
256   __IO uint32_t TDTR;
257   __IO uint32_t TDLR;
258   __IO uint32_t TDHR;
259 } CAN_TxMailBox_TypeDef;
260 
261 /**
262   * @brief Controller Area Network FIFOMailBox
263   */
264 
265 typedef struct
266 {
267   __IO uint32_t RIR;
268   __IO uint32_t RDTR;
269   __IO uint32_t RDLR;
270   __IO uint32_t RDHR;
271 } CAN_FIFOMailBox_TypeDef;
272 
273 /**
274   * @brief Controller Area Network FilterRegister
275   */
276 
277 typedef struct
278 {
279   __IO uint32_t FR1;
280   __IO uint32_t FR2;
281 } CAN_FilterRegister_TypeDef;
282 
283 /**
284   * @brief Controller Area Network
285   */
286 
287 typedef struct
288 {
289   __IO uint32_t MCR;
290   __IO uint32_t MSR;
291   __IO uint32_t TSR;
292   __IO uint32_t RF0R;
293   __IO uint32_t RF1R;
294   __IO uint32_t IER;
295   __IO uint32_t ESR;
296   __IO uint32_t BTR;
297   uint32_t  RESERVED0[88];
298   CAN_TxMailBox_TypeDef sTxMailBox[3];
299   CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
300   uint32_t  RESERVED1[12];
301   __IO uint32_t FMR;
302   __IO uint32_t FM1R;
303   uint32_t  RESERVED2;
304   __IO uint32_t FS1R;
305   uint32_t  RESERVED3;
306   __IO uint32_t FFA1R;
307   uint32_t  RESERVED4;
308   __IO uint32_t FA1R;
309   uint32_t  RESERVED5[8];
310   CAN_FilterRegister_TypeDef sFilterRegister[14];
311 } CAN_TypeDef;
312 
313 /**
314   * @brief CRC calculation unit
315   */
316 
317 typedef struct
318 {
319   __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
320   __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
321   uint8_t       RESERVED0;    /*!< Reserved,                                    Address offset: 0x05 */
322   uint16_t      RESERVED1;    /*!< Reserved,                                    Address offset: 0x06 */
323   __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */
324 } CRC_TypeDef;
325 
326 /**
327   * @brief Digital to Analog Converter
328   */
329 
330 typedef struct
331 {
332   __IO uint32_t CR;
333   __IO uint32_t SWTRIGR;
334   __IO uint32_t DHR12R1;
335   __IO uint32_t DHR12L1;
336   __IO uint32_t DHR8R1;
337   __IO uint32_t DHR12R2;
338   __IO uint32_t DHR12L2;
339   __IO uint32_t DHR8R2;
340   __IO uint32_t DHR12RD;
341   __IO uint32_t DHR12LD;
342   __IO uint32_t DHR8RD;
343   __IO uint32_t DOR1;
344   __IO uint32_t DOR2;
345 } DAC_TypeDef;
346 
347 /**
348   * @brief Debug MCU
349   */
350 
351 typedef struct
352 {
353   __IO uint32_t IDCODE;
354   __IO uint32_t CR;
355 }DBGMCU_TypeDef;
356 
357 /**
358   * @brief DMA Controller
359   */
360 
361 typedef struct
362 {
363   __IO uint32_t CCR;
364   __IO uint32_t CNDTR;
365   __IO uint32_t CPAR;
366   __IO uint32_t CMAR;
367 } DMA_Channel_TypeDef;
368 
369 typedef struct
370 {
371   __IO uint32_t ISR;
372   __IO uint32_t IFCR;
373 } DMA_TypeDef;
374 
375 
376 
377 /**
378   * @brief External Interrupt/Event Controller
379   */
380 
381 typedef struct
382 {
383   __IO uint32_t IMR;
384   __IO uint32_t EMR;
385   __IO uint32_t RTSR;
386   __IO uint32_t FTSR;
387   __IO uint32_t SWIER;
388   __IO uint32_t PR;
389 } EXTI_TypeDef;
390 
391 /**
392   * @brief FLASH Registers
393   */
394 
395 typedef struct
396 {
397   __IO uint32_t ACR;
398   __IO uint32_t KEYR;
399   __IO uint32_t OPTKEYR;
400   __IO uint32_t SR;
401   __IO uint32_t CR;
402   __IO uint32_t AR;
403   __IO uint32_t RESERVED;
404   __IO uint32_t OBR;
405   __IO uint32_t WRPR;
406 } FLASH_TypeDef;
407 
408 /**
409   * @brief Option Bytes Registers
410   */
411 
412 typedef struct
413 {
414   __IO uint16_t RDP;
415   __IO uint16_t USER;
416   __IO uint16_t Data0;
417   __IO uint16_t Data1;
418   __IO uint16_t WRP0;
419   __IO uint16_t WRP1;
420   __IO uint16_t WRP2;
421   __IO uint16_t WRP3;
422 } OB_TypeDef;
423 
424 /**
425   * @brief Flexible Static Memory Controller
426   */
427 
428 typedef struct
429 {
430   __IO uint32_t BTCR[8];
431 } FSMC_Bank1_TypeDef;
432 
433 /**
434   * @brief Flexible Static Memory Controller Bank1E
435   */
436 
437 typedef struct
438 {
439   __IO uint32_t BWTR[7];
440 } FSMC_Bank1E_TypeDef;
441 
442 /**
443   * @brief Flexible Static Memory Controller Bank2
444   */
445 
446 typedef struct
447 {
448   __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
449   __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
450   __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
451   __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
452   uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
453   __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
454   uint32_t      RESERVED1;  /*!< Reserved, 0x78                                                            */
455   uint32_t      RESERVED2;  /*!< Reserved, 0x7C                                                            */
456   __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
457   __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
458   __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
459   __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
460   uint32_t      RESERVED3;  /*!< Reserved, 0x90                                                            */
461   __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
462 } FSMC_Bank2_3_TypeDef;
463 
464 /**
465   * @brief Flexible Static Memory Controller Bank4
466   */
467 
468 typedef struct
469 {
470   __IO uint32_t PCR4;
471   __IO uint32_t SR4;
472   __IO uint32_t PMEM4;
473   __IO uint32_t PATT4;
474   __IO uint32_t PIO4;
475 } FSMC_Bank4_TypeDef;
476 
477 /**
478   * @brief General Purpose I/O
479   */
480 
481 typedef struct
482 {
483   __IO uint32_t CRL;
484   __IO uint32_t CRH;
485   __IO uint32_t IDR;
486   __IO uint32_t ODR;
487   __IO uint32_t BSRR;
488   __IO uint32_t BRR;
489   __IO uint32_t LCKR;
490 } GPIO_TypeDef;
491 
492 /**
493   * @brief Alternate Function I/O
494   */
495 
496 typedef struct
497 {
498   __IO uint32_t EVCR;
499   __IO uint32_t MAPR;
500   __IO uint32_t EXTICR[4];
501   uint32_t RESERVED0;
502   __IO uint32_t MAPR2;
503 } AFIO_TypeDef;
504 /**
505   * @brief Inter Integrated Circuit Interface
506   */
507 
508 typedef struct
509 {
510   __IO uint32_t CR1;
511   __IO uint32_t CR2;
512   __IO uint32_t OAR1;
513   __IO uint32_t OAR2;
514   __IO uint32_t DR;
515   __IO uint32_t SR1;
516   __IO uint32_t SR2;
517   __IO uint32_t CCR;
518   __IO uint32_t TRISE;
519 } I2C_TypeDef;
520 
521 /**
522   * @brief Independent WATCHDOG
523   */
524 
525 typedef struct
526 {
527   __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
528   __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
529   __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
530   __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
531 } IWDG_TypeDef;
532 
533 /**
534   * @brief Power Control
535   */
536 
537 typedef struct
538 {
539   __IO uint32_t CR;
540   __IO uint32_t CSR;
541 } PWR_TypeDef;
542 
543 /**
544   * @brief Reset and Clock Control
545   */
546 
547 typedef struct
548 {
549   __IO uint32_t CR;
550   __IO uint32_t CFGR;
551   __IO uint32_t CIR;
552   __IO uint32_t APB2RSTR;
553   __IO uint32_t APB1RSTR;
554   __IO uint32_t AHBENR;
555   __IO uint32_t APB2ENR;
556   __IO uint32_t APB1ENR;
557   __IO uint32_t BDCR;
558   __IO uint32_t CSR;
559 
560 
561 } RCC_TypeDef;
562 
563 /**
564   * @brief Real-Time Clock
565   */
566 
567 typedef struct
568 {
569   __IO uint32_t CRH;
570   __IO uint32_t CRL;
571   __IO uint32_t PRLH;
572   __IO uint32_t PRLL;
573   __IO uint32_t DIVH;
574   __IO uint32_t DIVL;
575   __IO uint32_t CNTH;
576   __IO uint32_t CNTL;
577   __IO uint32_t ALRH;
578   __IO uint32_t ALRL;
579 } RTC_TypeDef;
580 
581 /**
582   * @brief SD host Interface
583   */
584 
585 typedef struct
586 {
587   __IO uint32_t POWER;
588   __IO uint32_t CLKCR;
589   __IO uint32_t ARG;
590   __IO uint32_t CMD;
591   __I uint32_t RESPCMD;
592   __I uint32_t RESP1;
593   __I uint32_t RESP2;
594   __I uint32_t RESP3;
595   __I uint32_t RESP4;
596   __IO uint32_t DTIMER;
597   __IO uint32_t DLEN;
598   __IO uint32_t DCTRL;
599   __I uint32_t DCOUNT;
600   __I uint32_t STA;
601   __IO uint32_t ICR;
602   __IO uint32_t MASK;
603   uint32_t  RESERVED0[2];
604   __I uint32_t FIFOCNT;
605   uint32_t  RESERVED1[13];
606   __IO uint32_t FIFO;
607 } SDIO_TypeDef;
608 
609 /**
610   * @brief Serial Peripheral Interface
611   */
612 
613 typedef struct
614 {
615   __IO uint32_t CR1;
616   __IO uint32_t CR2;
617   __IO uint32_t SR;
618   __IO uint32_t DR;
619   __IO uint32_t CRCPR;
620   __IO uint32_t RXCRCR;
621   __IO uint32_t TXCRCR;
622   __IO uint32_t I2SCFGR;
623   __IO uint32_t I2SPR;
624 } SPI_TypeDef;
625 
626 /**
627   * @brief TIM Timers
628   */
629 typedef struct
630 {
631   __IO uint32_t CR1;             /*!< TIM control register 1,                      Address offset: 0x00 */
632   __IO uint32_t CR2;             /*!< TIM control register 2,                      Address offset: 0x04 */
633   __IO uint32_t SMCR;            /*!< TIM slave Mode Control register,             Address offset: 0x08 */
634   __IO uint32_t DIER;            /*!< TIM DMA/interrupt enable register,           Address offset: 0x0C */
635   __IO uint32_t SR;              /*!< TIM status register,                         Address offset: 0x10 */
636   __IO uint32_t EGR;             /*!< TIM event generation register,               Address offset: 0x14 */
637   __IO uint32_t CCMR1;           /*!< TIM  capture/compare mode register 1,        Address offset: 0x18 */
638   __IO uint32_t CCMR2;           /*!< TIM  capture/compare mode register 2,        Address offset: 0x1C */
639   __IO uint32_t CCER;            /*!< TIM capture/compare enable register,         Address offset: 0x20 */
640   __IO uint32_t CNT;             /*!< TIM counter register,                        Address offset: 0x24 */
641   __IO uint32_t PSC;             /*!< TIM prescaler register,                      Address offset: 0x28 */
642   __IO uint32_t ARR;             /*!< TIM auto-reload register,                    Address offset: 0x2C */
643   __IO uint32_t RCR;             /*!< TIM  repetition counter register,            Address offset: 0x30 */
644   __IO uint32_t CCR1;            /*!< TIM capture/compare register 1,              Address offset: 0x34 */
645   __IO uint32_t CCR2;            /*!< TIM capture/compare register 2,              Address offset: 0x38 */
646   __IO uint32_t CCR3;            /*!< TIM capture/compare register 3,              Address offset: 0x3C */
647   __IO uint32_t CCR4;            /*!< TIM capture/compare register 4,              Address offset: 0x40 */
648   __IO uint32_t BDTR;            /*!< TIM break and dead-time register,            Address offset: 0x44 */
649   __IO uint32_t DCR;             /*!< TIM DMA control register,                    Address offset: 0x48 */
650   __IO uint32_t DMAR;            /*!< TIM DMA address for full transfer register,  Address offset: 0x4C */
651   __IO uint32_t OR;              /*!< TIM option register,                         Address offset: 0x50 */
652 }TIM_TypeDef;
653 
654 
655 /**
656   * @brief Universal Synchronous Asynchronous Receiver Transmitter
657   */
658 
659 typedef struct
660 {
661   __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
662   __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
663   __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
664   __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
665   __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
666   __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
667   __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
668 } USART_TypeDef;
669 
670 /**
671   * @brief Universal Serial Bus Full Speed Device
672   */
673 
674 typedef struct
675 {
676   __IO uint16_t EP0R;                 /*!< USB Endpoint 0 register,                   Address offset: 0x00 */
677   __IO uint16_t RESERVED0;            /*!< Reserved */
678   __IO uint16_t EP1R;                 /*!< USB Endpoint 1 register,                   Address offset: 0x04 */
679   __IO uint16_t RESERVED1;            /*!< Reserved */
680   __IO uint16_t EP2R;                 /*!< USB Endpoint 2 register,                   Address offset: 0x08 */
681   __IO uint16_t RESERVED2;            /*!< Reserved */
682   __IO uint16_t EP3R;                 /*!< USB Endpoint 3 register,                   Address offset: 0x0C */
683   __IO uint16_t RESERVED3;            /*!< Reserved */
684   __IO uint16_t EP4R;                 /*!< USB Endpoint 4 register,                   Address offset: 0x10 */
685   __IO uint16_t RESERVED4;            /*!< Reserved */
686   __IO uint16_t EP5R;                 /*!< USB Endpoint 5 register,                   Address offset: 0x14 */
687   __IO uint16_t RESERVED5;            /*!< Reserved */
688   __IO uint16_t EP6R;                 /*!< USB Endpoint 6 register,                   Address offset: 0x18 */
689   __IO uint16_t RESERVED6;            /*!< Reserved */
690   __IO uint16_t EP7R;                 /*!< USB Endpoint 7 register,                   Address offset: 0x1C */
691   __IO uint16_t RESERVED7[17];        /*!< Reserved */
692   __IO uint16_t CNTR;                 /*!< Control register,                          Address offset: 0x40 */
693   __IO uint16_t RESERVED8;            /*!< Reserved */
694   __IO uint16_t ISTR;                 /*!< Interrupt status register,                 Address offset: 0x44 */
695   __IO uint16_t RESERVED9;            /*!< Reserved */
696   __IO uint16_t FNR;                  /*!< Frame number register,                     Address offset: 0x48 */
697   __IO uint16_t RESERVEDA;            /*!< Reserved */
698   __IO uint16_t DADDR;                /*!< Device address register,                   Address offset: 0x4C */
699   __IO uint16_t RESERVEDB;            /*!< Reserved */
700   __IO uint16_t BTABLE;               /*!< Buffer Table address register,             Address offset: 0x50 */
701   __IO uint16_t RESERVEDC;            /*!< Reserved */
702 } USB_TypeDef;
703 
704 
705 /**
706   * @brief Window WATCHDOG
707   */
708 
709 typedef struct
710 {
711   __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
712   __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
713   __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
714 } WWDG_TypeDef;
715 
716 /**
717   * @}
718   */
719 
720 /** @addtogroup Peripheral_memory_map
721   * @{
722   */
723 
724 
725 #define FLASH_BASE            0x08000000UL /*!< FLASH base address in the alias region */
726 #define FLASH_BANK1_END       0x0807FFFFUL /*!< FLASH END address of bank1 */
727 #define SRAM_BASE             0x20000000UL /*!< SRAM base address in the alias region */
728 #define PERIPH_BASE           0x40000000UL /*!< Peripheral base address in the alias region */
729 
730 #define SRAM_BB_BASE          0x22000000UL /*!< SRAM base address in the bit-band region */
731 #define PERIPH_BB_BASE        0x42000000UL /*!< Peripheral base address in the bit-band region */
732 
733 #define FSMC_BASE             0x60000000UL /*!< FSMC base address */
734 #define FSMC_R_BASE           0xA0000000UL /*!< FSMC registers base address */
735 
736 /*!< Peripheral memory map */
737 #define APB1PERIPH_BASE       PERIPH_BASE
738 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
739 #define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
740 
741 #define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000UL)
742 #define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400UL)
743 #define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800UL)
744 #define TIM5_BASE             (APB1PERIPH_BASE + 0x00000C00UL)
745 #define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000UL)
746 #define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400UL)
747 #define RTC_BASE              (APB1PERIPH_BASE + 0x00002800UL)
748 #define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00UL)
749 #define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000UL)
750 #define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800UL)
751 #define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00UL)
752 #define USART2_BASE           (APB1PERIPH_BASE + 0x00004400UL)
753 #define USART3_BASE           (APB1PERIPH_BASE + 0x00004800UL)
754 #define UART4_BASE            (APB1PERIPH_BASE + 0x00004C00UL)
755 #define UART5_BASE            (APB1PERIPH_BASE + 0x00005000UL)
756 #define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400UL)
757 #define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800UL)
758 #define CAN1_BASE             (APB1PERIPH_BASE + 0x00006400UL)
759 #define BKP_BASE              (APB1PERIPH_BASE + 0x00006C00UL)
760 #define PWR_BASE              (APB1PERIPH_BASE + 0x00007000UL)
761 #define DAC_BASE              (APB1PERIPH_BASE + 0x00007400UL)
762 #define AFIO_BASE             (APB2PERIPH_BASE + 0x00000000UL)
763 #define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400UL)
764 #define GPIOA_BASE            (APB2PERIPH_BASE + 0x00000800UL)
765 #define GPIOB_BASE            (APB2PERIPH_BASE + 0x00000C00UL)
766 #define GPIOC_BASE            (APB2PERIPH_BASE + 0x00001000UL)
767 #define GPIOD_BASE            (APB2PERIPH_BASE + 0x00001400UL)
768 #define GPIOE_BASE            (APB2PERIPH_BASE + 0x00001800UL)
769 #define GPIOF_BASE            (APB2PERIPH_BASE + 0x00001C00UL)
770 #define GPIOG_BASE            (APB2PERIPH_BASE + 0x00002000UL)
771 #define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400UL)
772 #define ADC2_BASE             (APB2PERIPH_BASE + 0x00002800UL)
773 #define TIM1_BASE             (APB2PERIPH_BASE + 0x00002C00UL)
774 #define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000UL)
775 #define TIM8_BASE             (APB2PERIPH_BASE + 0x00003400UL)
776 #define USART1_BASE           (APB2PERIPH_BASE + 0x00003800UL)
777 #define ADC3_BASE             (APB2PERIPH_BASE + 0x00003C00UL)
778 
779 #define SDIO_BASE             (PERIPH_BASE + 0x00018000UL)
780 
781 #define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000UL)
782 #define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x00000008UL)
783 #define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x0000001CUL)
784 #define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x00000030UL)
785 #define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x00000044UL)
786 #define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x00000058UL)
787 #define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x0000006CUL)
788 #define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x00000080UL)
789 #define DMA2_BASE             (AHBPERIPH_BASE + 0x00000400UL)
790 #define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x00000408UL)
791 #define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x0000041CUL)
792 #define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x00000430UL)
793 #define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x00000444UL)
794 #define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x00000458UL)
795 #define RCC_BASE              (AHBPERIPH_BASE + 0x00001000UL)
796 #define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
797 
798 #define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000UL) /*!< Flash registers base address */
799 #define FLASHSIZE_BASE        0x1FFFF7E0UL    /*!< FLASH Size register base address */
800 #define UID_BASE              0x1FFFF7E8UL    /*!< Unique device ID register base address */
801 #define OB_BASE               0x1FFFF800UL    /*!< Flash Option Bytes base address */
802 
803 
804 #define FSMC_BANK1            (FSMC_BASE)               /*!< FSMC Bank1 base address */
805 #define FSMC_BANK1_1          (FSMC_BANK1)              /*!< FSMC Bank1_1 base address */
806 #define FSMC_BANK1_2          (FSMC_BANK1 + 0x04000000UL) /*!< FSMC Bank1_2 base address */
807 #define FSMC_BANK1_3          (FSMC_BANK1 + 0x08000000UL) /*!< FSMC Bank1_3 base address */
808 #define FSMC_BANK1_4          (FSMC_BANK1 + 0x0C000000UL) /*!< FSMC Bank1_4 base address */
809 
810 #define FSMC_BANK2            (FSMC_BASE + 0x10000000UL)  /*!< FSMC Bank2 base address */
811 #define FSMC_BANK3            (FSMC_BASE + 0x20000000UL)  /*!< FSMC Bank3 base address */
812 #define FSMC_BANK4            (FSMC_BASE + 0x30000000UL)  /*!< FSMC Bank4 base address */
813 
814 #define FSMC_BANK1_R_BASE     (FSMC_R_BASE + 0x00000000UL)    /*!< FSMC Bank1 registers base address */
815 #define FSMC_BANK1E_R_BASE    (FSMC_R_BASE + 0x00000104UL)    /*!< FSMC Bank1E registers base address */
816 #define FSMC_BANK2_3_R_BASE   (FSMC_R_BASE + 0x00000060UL)    /*!< FSMC Bank2/Bank3 registers base address */
817 #define FSMC_BANK4_R_BASE     (FSMC_R_BASE + 0x000000A0UL)    /*!< FSMC Bank4 registers base address */
818 
819 #define DBGMCU_BASE          0xE0042000UL /*!< Debug MCU registers base address */
820 
821 /* USB device FS */
822 #define USB_BASE              (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */
823 #define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */
824 
825 
826 /**
827   * @}
828   */
829 
830 /** @addtogroup Peripheral_declaration
831   * @{
832   */
833 
834 #define TIM2                ((TIM_TypeDef *)TIM2_BASE)
835 #define TIM3                ((TIM_TypeDef *)TIM3_BASE)
836 #define TIM4                ((TIM_TypeDef *)TIM4_BASE)
837 #define TIM5                ((TIM_TypeDef *)TIM5_BASE)
838 #define TIM6                ((TIM_TypeDef *)TIM6_BASE)
839 #define TIM7                ((TIM_TypeDef *)TIM7_BASE)
840 #define RTC                 ((RTC_TypeDef *)RTC_BASE)
841 #define WWDG                ((WWDG_TypeDef *)WWDG_BASE)
842 #define IWDG                ((IWDG_TypeDef *)IWDG_BASE)
843 #define SPI2                ((SPI_TypeDef *)SPI2_BASE)
844 #define SPI3                ((SPI_TypeDef *)SPI3_BASE)
845 #define USART2              ((USART_TypeDef *)USART2_BASE)
846 #define USART3              ((USART_TypeDef *)USART3_BASE)
847 #define UART4               ((USART_TypeDef *)UART4_BASE)
848 #define UART5               ((USART_TypeDef *)UART5_BASE)
849 #define I2C1                ((I2C_TypeDef *)I2C1_BASE)
850 #define I2C2                ((I2C_TypeDef *)I2C2_BASE)
851 #define USB                 ((USB_TypeDef *)USB_BASE)
852 #define CAN1                ((CAN_TypeDef *)CAN1_BASE)
853 #define BKP                 ((BKP_TypeDef *)BKP_BASE)
854 #define PWR                 ((PWR_TypeDef *)PWR_BASE)
855 #define DAC1                ((DAC_TypeDef *)DAC_BASE)
856 #define DAC                 ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */
857 #define AFIO                ((AFIO_TypeDef *)AFIO_BASE)
858 #define EXTI                ((EXTI_TypeDef *)EXTI_BASE)
859 #define GPIOA               ((GPIO_TypeDef *)GPIOA_BASE)
860 #define GPIOB               ((GPIO_TypeDef *)GPIOB_BASE)
861 #define GPIOC               ((GPIO_TypeDef *)GPIOC_BASE)
862 #define GPIOD               ((GPIO_TypeDef *)GPIOD_BASE)
863 #define GPIOE               ((GPIO_TypeDef *)GPIOE_BASE)
864 #define GPIOF               ((GPIO_TypeDef *)GPIOF_BASE)
865 #define GPIOG               ((GPIO_TypeDef *)GPIOG_BASE)
866 #define ADC1                ((ADC_TypeDef *)ADC1_BASE)
867 #define ADC2                ((ADC_TypeDef *)ADC2_BASE)
868 #define ADC3                ((ADC_TypeDef *)ADC3_BASE)
869 #define ADC12_COMMON        ((ADC_Common_TypeDef *)ADC1_BASE)
870 #define TIM1                ((TIM_TypeDef *)TIM1_BASE)
871 #define SPI1                ((SPI_TypeDef *)SPI1_BASE)
872 #define TIM8                ((TIM_TypeDef *)TIM8_BASE)
873 #define USART1              ((USART_TypeDef *)USART1_BASE)
874 #define SDIO                ((SDIO_TypeDef *)SDIO_BASE)
875 #define DMA1                ((DMA_TypeDef *)DMA1_BASE)
876 #define DMA2                ((DMA_TypeDef *)DMA2_BASE)
877 #define DMA1_Channel1       ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
878 #define DMA1_Channel2       ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
879 #define DMA1_Channel3       ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
880 #define DMA1_Channel4       ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
881 #define DMA1_Channel5       ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
882 #define DMA1_Channel6       ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
883 #define DMA1_Channel7       ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
884 #define DMA2_Channel1       ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE)
885 #define DMA2_Channel2       ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE)
886 #define DMA2_Channel3       ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE)
887 #define DMA2_Channel4       ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE)
888 #define DMA2_Channel5       ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE)
889 #define RCC                 ((RCC_TypeDef *)RCC_BASE)
890 #define CRC                 ((CRC_TypeDef *)CRC_BASE)
891 #define FLASH               ((FLASH_TypeDef *)FLASH_R_BASE)
892 #define OB                  ((OB_TypeDef *)OB_BASE)
893 #define FSMC_Bank1          ((FSMC_Bank1_TypeDef *)FSMC_BANK1_R_BASE)
894 #define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *)FSMC_BANK1E_R_BASE)
895 #define FSMC_Bank2_3        ((FSMC_Bank2_3_TypeDef *)FSMC_BANK2_3_R_BASE)
896 #define FSMC_Bank4          ((FSMC_Bank4_TypeDef *)FSMC_BANK4_R_BASE)
897 #define DBGMCU              ((DBGMCU_TypeDef *)DBGMCU_BASE)
898 
899 
900 /**
901   * @}
902   */
903 
904 /** @addtogroup Exported_constants
905   * @{
906   */
907 
908   /** @addtogroup Hardware_Constant_Definition
909     * @{
910     */
911 #define LSI_STARTUP_TIME                85U /*!< LSI Maximum startup time in us */
912   /**
913     * @}
914     */
915 
916   /** @addtogroup Peripheral_Registers_Bits_Definition
917   * @{
918   */
919 
920 /******************************************************************************/
921 /*                         Peripheral Registers_Bits_Definition               */
922 /******************************************************************************/
923 
924 /******************************************************************************/
925 /*                                                                            */
926 /*                       CRC calculation unit (CRC)                           */
927 /*                                                                            */
928 /******************************************************************************/
929 
930 /*******************  Bit definition for CRC_DR register  *********************/
931 #define CRC_DR_DR_Pos                       (0U)
932 #define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)     /*!< 0xFFFFFFFF */
933 #define CRC_DR_DR                           CRC_DR_DR_Msk                      /*!< Data register bits */
934 
935 /*******************  Bit definition for CRC_IDR register  ********************/
936 #define CRC_IDR_IDR_Pos                     (0U)
937 #define CRC_IDR_IDR_Msk                     (0xFFUL << CRC_IDR_IDR_Pos)         /*!< 0x000000FF */
938 #define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                    /*!< General-purpose 8-bit data register bits */
939 
940 /********************  Bit definition for CRC_CR register  ********************/
941 #define CRC_CR_RESET_Pos                    (0U)
942 #define CRC_CR_RESET_Msk                    (0x1UL << CRC_CR_RESET_Pos)         /*!< 0x00000001 */
943 #define CRC_CR_RESET                        CRC_CR_RESET_Msk                   /*!< RESET bit */
944 
945 /******************************************************************************/
946 /*                                                                            */
947 /*                             Power Control                                  */
948 /*                                                                            */
949 /******************************************************************************/
950 
951 /********************  Bit definition for PWR_CR register  ********************/
952 #define PWR_CR_LPDS_Pos                     (0U)
953 #define PWR_CR_LPDS_Msk                     (0x1UL << PWR_CR_LPDS_Pos)          /*!< 0x00000001 */
954 #define PWR_CR_LPDS                         PWR_CR_LPDS_Msk                    /*!< Low-Power Deepsleep */
955 #define PWR_CR_PDDS_Pos                     (1U)
956 #define PWR_CR_PDDS_Msk                     (0x1UL << PWR_CR_PDDS_Pos)          /*!< 0x00000002 */
957 #define PWR_CR_PDDS                         PWR_CR_PDDS_Msk                    /*!< Power Down Deepsleep */
958 #define PWR_CR_CWUF_Pos                     (2U)
959 #define PWR_CR_CWUF_Msk                     (0x1UL << PWR_CR_CWUF_Pos)          /*!< 0x00000004 */
960 #define PWR_CR_CWUF                         PWR_CR_CWUF_Msk                    /*!< Clear Wakeup Flag */
961 #define PWR_CR_CSBF_Pos                     (3U)
962 #define PWR_CR_CSBF_Msk                     (0x1UL << PWR_CR_CSBF_Pos)          /*!< 0x00000008 */
963 #define PWR_CR_CSBF                         PWR_CR_CSBF_Msk                    /*!< Clear Standby Flag */
964 #define PWR_CR_PVDE_Pos                     (4U)
965 #define PWR_CR_PVDE_Msk                     (0x1UL << PWR_CR_PVDE_Pos)          /*!< 0x00000010 */
966 #define PWR_CR_PVDE                         PWR_CR_PVDE_Msk                    /*!< Power Voltage Detector Enable */
967 
968 #define PWR_CR_PLS_Pos                      (5U)
969 #define PWR_CR_PLS_Msk                      (0x7UL << PWR_CR_PLS_Pos)           /*!< 0x000000E0 */
970 #define PWR_CR_PLS                          PWR_CR_PLS_Msk                     /*!< PLS[2:0] bits (PVD Level Selection) */
971 #define PWR_CR_PLS_0                        (0x1UL << PWR_CR_PLS_Pos)           /*!< 0x00000020 */
972 #define PWR_CR_PLS_1                        (0x2UL << PWR_CR_PLS_Pos)           /*!< 0x00000040 */
973 #define PWR_CR_PLS_2                        (0x4UL << PWR_CR_PLS_Pos)           /*!< 0x00000080 */
974 
975 /*!< PVD level configuration */
976 #define PWR_CR_PLS_LEV0                      0x00000000U                           /*!< PVD level 2.2V */
977 #define PWR_CR_PLS_LEV1                      0x00000020U                           /*!< PVD level 2.3V */
978 #define PWR_CR_PLS_LEV2                      0x00000040U                           /*!< PVD level 2.4V */
979 #define PWR_CR_PLS_LEV3                      0x00000060U                           /*!< PVD level 2.5V */
980 #define PWR_CR_PLS_LEV4                      0x00000080U                           /*!< PVD level 2.6V */
981 #define PWR_CR_PLS_LEV5                      0x000000A0U                           /*!< PVD level 2.7V */
982 #define PWR_CR_PLS_LEV6                      0x000000C0U                           /*!< PVD level 2.8V */
983 #define PWR_CR_PLS_LEV7                      0x000000E0U                           /*!< PVD level 2.9V */
984 
985 /* Legacy defines */
986 #define PWR_CR_PLS_2V2                       PWR_CR_PLS_LEV0
987 #define PWR_CR_PLS_2V3                       PWR_CR_PLS_LEV1
988 #define PWR_CR_PLS_2V4                       PWR_CR_PLS_LEV2
989 #define PWR_CR_PLS_2V5                       PWR_CR_PLS_LEV3
990 #define PWR_CR_PLS_2V6                       PWR_CR_PLS_LEV4
991 #define PWR_CR_PLS_2V7                       PWR_CR_PLS_LEV5
992 #define PWR_CR_PLS_2V8                       PWR_CR_PLS_LEV6
993 #define PWR_CR_PLS_2V9                       PWR_CR_PLS_LEV7
994 
995 #define PWR_CR_DBP_Pos                      (8U)
996 #define PWR_CR_DBP_Msk                      (0x1UL << PWR_CR_DBP_Pos)           /*!< 0x00000100 */
997 #define PWR_CR_DBP                          PWR_CR_DBP_Msk                     /*!< Disable Backup Domain write protection */
998 
999 
1000 /*******************  Bit definition for PWR_CSR register  ********************/
1001 #define PWR_CSR_WUF_Pos                     (0U)
1002 #define PWR_CSR_WUF_Msk                     (0x1UL << PWR_CSR_WUF_Pos)          /*!< 0x00000001 */
1003 #define PWR_CSR_WUF                         PWR_CSR_WUF_Msk                    /*!< Wakeup Flag */
1004 #define PWR_CSR_SBF_Pos                     (1U)
1005 #define PWR_CSR_SBF_Msk                     (0x1UL << PWR_CSR_SBF_Pos)          /*!< 0x00000002 */
1006 #define PWR_CSR_SBF                         PWR_CSR_SBF_Msk                    /*!< Standby Flag */
1007 #define PWR_CSR_PVDO_Pos                    (2U)
1008 #define PWR_CSR_PVDO_Msk                    (0x1UL << PWR_CSR_PVDO_Pos)         /*!< 0x00000004 */
1009 #define PWR_CSR_PVDO                        PWR_CSR_PVDO_Msk                   /*!< PVD Output */
1010 #define PWR_CSR_EWUP_Pos                    (8U)
1011 #define PWR_CSR_EWUP_Msk                    (0x1UL << PWR_CSR_EWUP_Pos)         /*!< 0x00000100 */
1012 #define PWR_CSR_EWUP                        PWR_CSR_EWUP_Msk                   /*!< Enable WKUP pin */
1013 
1014 /******************************************************************************/
1015 /*                                                                            */
1016 /*                            Backup registers                                */
1017 /*                                                                            */
1018 /******************************************************************************/
1019 
1020 /*******************  Bit definition for BKP_DR1 register  ********************/
1021 #define BKP_DR1_D_Pos                       (0U)
1022 #define BKP_DR1_D_Msk                       (0xFFFFUL << BKP_DR1_D_Pos)         /*!< 0x0000FFFF */
1023 #define BKP_DR1_D                           BKP_DR1_D_Msk                      /*!< Backup data */
1024 
1025 /*******************  Bit definition for BKP_DR2 register  ********************/
1026 #define BKP_DR2_D_Pos                       (0U)
1027 #define BKP_DR2_D_Msk                       (0xFFFFUL << BKP_DR2_D_Pos)         /*!< 0x0000FFFF */
1028 #define BKP_DR2_D                           BKP_DR2_D_Msk                      /*!< Backup data */
1029 
1030 /*******************  Bit definition for BKP_DR3 register  ********************/
1031 #define BKP_DR3_D_Pos                       (0U)
1032 #define BKP_DR3_D_Msk                       (0xFFFFUL << BKP_DR3_D_Pos)         /*!< 0x0000FFFF */
1033 #define BKP_DR3_D                           BKP_DR3_D_Msk                      /*!< Backup data */
1034 
1035 /*******************  Bit definition for BKP_DR4 register  ********************/
1036 #define BKP_DR4_D_Pos                       (0U)
1037 #define BKP_DR4_D_Msk                       (0xFFFFUL << BKP_DR4_D_Pos)         /*!< 0x0000FFFF */
1038 #define BKP_DR4_D                           BKP_DR4_D_Msk                      /*!< Backup data */
1039 
1040 /*******************  Bit definition for BKP_DR5 register  ********************/
1041 #define BKP_DR5_D_Pos                       (0U)
1042 #define BKP_DR5_D_Msk                       (0xFFFFUL << BKP_DR5_D_Pos)         /*!< 0x0000FFFF */
1043 #define BKP_DR5_D                           BKP_DR5_D_Msk                      /*!< Backup data */
1044 
1045 /*******************  Bit definition for BKP_DR6 register  ********************/
1046 #define BKP_DR6_D_Pos                       (0U)
1047 #define BKP_DR6_D_Msk                       (0xFFFFUL << BKP_DR6_D_Pos)         /*!< 0x0000FFFF */
1048 #define BKP_DR6_D                           BKP_DR6_D_Msk                      /*!< Backup data */
1049 
1050 /*******************  Bit definition for BKP_DR7 register  ********************/
1051 #define BKP_DR7_D_Pos                       (0U)
1052 #define BKP_DR7_D_Msk                       (0xFFFFUL << BKP_DR7_D_Pos)         /*!< 0x0000FFFF */
1053 #define BKP_DR7_D                           BKP_DR7_D_Msk                      /*!< Backup data */
1054 
1055 /*******************  Bit definition for BKP_DR8 register  ********************/
1056 #define BKP_DR8_D_Pos                       (0U)
1057 #define BKP_DR8_D_Msk                       (0xFFFFUL << BKP_DR8_D_Pos)         /*!< 0x0000FFFF */
1058 #define BKP_DR8_D                           BKP_DR8_D_Msk                      /*!< Backup data */
1059 
1060 /*******************  Bit definition for BKP_DR9 register  ********************/
1061 #define BKP_DR9_D_Pos                       (0U)
1062 #define BKP_DR9_D_Msk                       (0xFFFFUL << BKP_DR9_D_Pos)         /*!< 0x0000FFFF */
1063 #define BKP_DR9_D                           BKP_DR9_D_Msk                      /*!< Backup data */
1064 
1065 /*******************  Bit definition for BKP_DR10 register  *******************/
1066 #define BKP_DR10_D_Pos                      (0U)
1067 #define BKP_DR10_D_Msk                      (0xFFFFUL << BKP_DR10_D_Pos)        /*!< 0x0000FFFF */
1068 #define BKP_DR10_D                          BKP_DR10_D_Msk                     /*!< Backup data */
1069 
1070 /*******************  Bit definition for BKP_DR11 register  *******************/
1071 #define BKP_DR11_D_Pos                      (0U)
1072 #define BKP_DR11_D_Msk                      (0xFFFFUL << BKP_DR11_D_Pos)        /*!< 0x0000FFFF */
1073 #define BKP_DR11_D                          BKP_DR11_D_Msk                     /*!< Backup data */
1074 
1075 /*******************  Bit definition for BKP_DR12 register  *******************/
1076 #define BKP_DR12_D_Pos                      (0U)
1077 #define BKP_DR12_D_Msk                      (0xFFFFUL << BKP_DR12_D_Pos)        /*!< 0x0000FFFF */
1078 #define BKP_DR12_D                          BKP_DR12_D_Msk                     /*!< Backup data */
1079 
1080 /*******************  Bit definition for BKP_DR13 register  *******************/
1081 #define BKP_DR13_D_Pos                      (0U)
1082 #define BKP_DR13_D_Msk                      (0xFFFFUL << BKP_DR13_D_Pos)        /*!< 0x0000FFFF */
1083 #define BKP_DR13_D                          BKP_DR13_D_Msk                     /*!< Backup data */
1084 
1085 /*******************  Bit definition for BKP_DR14 register  *******************/
1086 #define BKP_DR14_D_Pos                      (0U)
1087 #define BKP_DR14_D_Msk                      (0xFFFFUL << BKP_DR14_D_Pos)        /*!< 0x0000FFFF */
1088 #define BKP_DR14_D                          BKP_DR14_D_Msk                     /*!< Backup data */
1089 
1090 /*******************  Bit definition for BKP_DR15 register  *******************/
1091 #define BKP_DR15_D_Pos                      (0U)
1092 #define BKP_DR15_D_Msk                      (0xFFFFUL << BKP_DR15_D_Pos)        /*!< 0x0000FFFF */
1093 #define BKP_DR15_D                          BKP_DR15_D_Msk                     /*!< Backup data */
1094 
1095 /*******************  Bit definition for BKP_DR16 register  *******************/
1096 #define BKP_DR16_D_Pos                      (0U)
1097 #define BKP_DR16_D_Msk                      (0xFFFFUL << BKP_DR16_D_Pos)        /*!< 0x0000FFFF */
1098 #define BKP_DR16_D                          BKP_DR16_D_Msk                     /*!< Backup data */
1099 
1100 /*******************  Bit definition for BKP_DR17 register  *******************/
1101 #define BKP_DR17_D_Pos                      (0U)
1102 #define BKP_DR17_D_Msk                      (0xFFFFUL << BKP_DR17_D_Pos)        /*!< 0x0000FFFF */
1103 #define BKP_DR17_D                          BKP_DR17_D_Msk                     /*!< Backup data */
1104 
1105 /******************  Bit definition for BKP_DR18 register  ********************/
1106 #define BKP_DR18_D_Pos                      (0U)
1107 #define BKP_DR18_D_Msk                      (0xFFFFUL << BKP_DR18_D_Pos)        /*!< 0x0000FFFF */
1108 #define BKP_DR18_D                          BKP_DR18_D_Msk                     /*!< Backup data */
1109 
1110 /*******************  Bit definition for BKP_DR19 register  *******************/
1111 #define BKP_DR19_D_Pos                      (0U)
1112 #define BKP_DR19_D_Msk                      (0xFFFFUL << BKP_DR19_D_Pos)        /*!< 0x0000FFFF */
1113 #define BKP_DR19_D                          BKP_DR19_D_Msk                     /*!< Backup data */
1114 
1115 /*******************  Bit definition for BKP_DR20 register  *******************/
1116 #define BKP_DR20_D_Pos                      (0U)
1117 #define BKP_DR20_D_Msk                      (0xFFFFUL << BKP_DR20_D_Pos)        /*!< 0x0000FFFF */
1118 #define BKP_DR20_D                          BKP_DR20_D_Msk                     /*!< Backup data */
1119 
1120 /*******************  Bit definition for BKP_DR21 register  *******************/
1121 #define BKP_DR21_D_Pos                      (0U)
1122 #define BKP_DR21_D_Msk                      (0xFFFFUL << BKP_DR21_D_Pos)        /*!< 0x0000FFFF */
1123 #define BKP_DR21_D                          BKP_DR21_D_Msk                     /*!< Backup data */
1124 
1125 /*******************  Bit definition for BKP_DR22 register  *******************/
1126 #define BKP_DR22_D_Pos                      (0U)
1127 #define BKP_DR22_D_Msk                      (0xFFFFUL << BKP_DR22_D_Pos)        /*!< 0x0000FFFF */
1128 #define BKP_DR22_D                          BKP_DR22_D_Msk                     /*!< Backup data */
1129 
1130 /*******************  Bit definition for BKP_DR23 register  *******************/
1131 #define BKP_DR23_D_Pos                      (0U)
1132 #define BKP_DR23_D_Msk                      (0xFFFFUL << BKP_DR23_D_Pos)        /*!< 0x0000FFFF */
1133 #define BKP_DR23_D                          BKP_DR23_D_Msk                     /*!< Backup data */
1134 
1135 /*******************  Bit definition for BKP_DR24 register  *******************/
1136 #define BKP_DR24_D_Pos                      (0U)
1137 #define BKP_DR24_D_Msk                      (0xFFFFUL << BKP_DR24_D_Pos)        /*!< 0x0000FFFF */
1138 #define BKP_DR24_D                          BKP_DR24_D_Msk                     /*!< Backup data */
1139 
1140 /*******************  Bit definition for BKP_DR25 register  *******************/
1141 #define BKP_DR25_D_Pos                      (0U)
1142 #define BKP_DR25_D_Msk                      (0xFFFFUL << BKP_DR25_D_Pos)        /*!< 0x0000FFFF */
1143 #define BKP_DR25_D                          BKP_DR25_D_Msk                     /*!< Backup data */
1144 
1145 /*******************  Bit definition for BKP_DR26 register  *******************/
1146 #define BKP_DR26_D_Pos                      (0U)
1147 #define BKP_DR26_D_Msk                      (0xFFFFUL << BKP_DR26_D_Pos)        /*!< 0x0000FFFF */
1148 #define BKP_DR26_D                          BKP_DR26_D_Msk                     /*!< Backup data */
1149 
1150 /*******************  Bit definition for BKP_DR27 register  *******************/
1151 #define BKP_DR27_D_Pos                      (0U)
1152 #define BKP_DR27_D_Msk                      (0xFFFFUL << BKP_DR27_D_Pos)        /*!< 0x0000FFFF */
1153 #define BKP_DR27_D                          BKP_DR27_D_Msk                     /*!< Backup data */
1154 
1155 /*******************  Bit definition for BKP_DR28 register  *******************/
1156 #define BKP_DR28_D_Pos                      (0U)
1157 #define BKP_DR28_D_Msk                      (0xFFFFUL << BKP_DR28_D_Pos)        /*!< 0x0000FFFF */
1158 #define BKP_DR28_D                          BKP_DR28_D_Msk                     /*!< Backup data */
1159 
1160 /*******************  Bit definition for BKP_DR29 register  *******************/
1161 #define BKP_DR29_D_Pos                      (0U)
1162 #define BKP_DR29_D_Msk                      (0xFFFFUL << BKP_DR29_D_Pos)        /*!< 0x0000FFFF */
1163 #define BKP_DR29_D                          BKP_DR29_D_Msk                     /*!< Backup data */
1164 
1165 /*******************  Bit definition for BKP_DR30 register  *******************/
1166 #define BKP_DR30_D_Pos                      (0U)
1167 #define BKP_DR30_D_Msk                      (0xFFFFUL << BKP_DR30_D_Pos)        /*!< 0x0000FFFF */
1168 #define BKP_DR30_D                          BKP_DR30_D_Msk                     /*!< Backup data */
1169 
1170 /*******************  Bit definition for BKP_DR31 register  *******************/
1171 #define BKP_DR31_D_Pos                      (0U)
1172 #define BKP_DR31_D_Msk                      (0xFFFFUL << BKP_DR31_D_Pos)        /*!< 0x0000FFFF */
1173 #define BKP_DR31_D                          BKP_DR31_D_Msk                     /*!< Backup data */
1174 
1175 /*******************  Bit definition for BKP_DR32 register  *******************/
1176 #define BKP_DR32_D_Pos                      (0U)
1177 #define BKP_DR32_D_Msk                      (0xFFFFUL << BKP_DR32_D_Pos)        /*!< 0x0000FFFF */
1178 #define BKP_DR32_D                          BKP_DR32_D_Msk                     /*!< Backup data */
1179 
1180 /*******************  Bit definition for BKP_DR33 register  *******************/
1181 #define BKP_DR33_D_Pos                      (0U)
1182 #define BKP_DR33_D_Msk                      (0xFFFFUL << BKP_DR33_D_Pos)        /*!< 0x0000FFFF */
1183 #define BKP_DR33_D                          BKP_DR33_D_Msk                     /*!< Backup data */
1184 
1185 /*******************  Bit definition for BKP_DR34 register  *******************/
1186 #define BKP_DR34_D_Pos                      (0U)
1187 #define BKP_DR34_D_Msk                      (0xFFFFUL << BKP_DR34_D_Pos)        /*!< 0x0000FFFF */
1188 #define BKP_DR34_D                          BKP_DR34_D_Msk                     /*!< Backup data */
1189 
1190 /*******************  Bit definition for BKP_DR35 register  *******************/
1191 #define BKP_DR35_D_Pos                      (0U)
1192 #define BKP_DR35_D_Msk                      (0xFFFFUL << BKP_DR35_D_Pos)        /*!< 0x0000FFFF */
1193 #define BKP_DR35_D                          BKP_DR35_D_Msk                     /*!< Backup data */
1194 
1195 /*******************  Bit definition for BKP_DR36 register  *******************/
1196 #define BKP_DR36_D_Pos                      (0U)
1197 #define BKP_DR36_D_Msk                      (0xFFFFUL << BKP_DR36_D_Pos)        /*!< 0x0000FFFF */
1198 #define BKP_DR36_D                          BKP_DR36_D_Msk                     /*!< Backup data */
1199 
1200 /*******************  Bit definition for BKP_DR37 register  *******************/
1201 #define BKP_DR37_D_Pos                      (0U)
1202 #define BKP_DR37_D_Msk                      (0xFFFFUL << BKP_DR37_D_Pos)        /*!< 0x0000FFFF */
1203 #define BKP_DR37_D                          BKP_DR37_D_Msk                     /*!< Backup data */
1204 
1205 /*******************  Bit definition for BKP_DR38 register  *******************/
1206 #define BKP_DR38_D_Pos                      (0U)
1207 #define BKP_DR38_D_Msk                      (0xFFFFUL << BKP_DR38_D_Pos)        /*!< 0x0000FFFF */
1208 #define BKP_DR38_D                          BKP_DR38_D_Msk                     /*!< Backup data */
1209 
1210 /*******************  Bit definition for BKP_DR39 register  *******************/
1211 #define BKP_DR39_D_Pos                      (0U)
1212 #define BKP_DR39_D_Msk                      (0xFFFFUL << BKP_DR39_D_Pos)        /*!< 0x0000FFFF */
1213 #define BKP_DR39_D                          BKP_DR39_D_Msk                     /*!< Backup data */
1214 
1215 /*******************  Bit definition for BKP_DR40 register  *******************/
1216 #define BKP_DR40_D_Pos                      (0U)
1217 #define BKP_DR40_D_Msk                      (0xFFFFUL << BKP_DR40_D_Pos)        /*!< 0x0000FFFF */
1218 #define BKP_DR40_D                          BKP_DR40_D_Msk                     /*!< Backup data */
1219 
1220 /*******************  Bit definition for BKP_DR41 register  *******************/
1221 #define BKP_DR41_D_Pos                      (0U)
1222 #define BKP_DR41_D_Msk                      (0xFFFFUL << BKP_DR41_D_Pos)        /*!< 0x0000FFFF */
1223 #define BKP_DR41_D                          BKP_DR41_D_Msk                     /*!< Backup data */
1224 
1225 /*******************  Bit definition for BKP_DR42 register  *******************/
1226 #define BKP_DR42_D_Pos                      (0U)
1227 #define BKP_DR42_D_Msk                      (0xFFFFUL << BKP_DR42_D_Pos)        /*!< 0x0000FFFF */
1228 #define BKP_DR42_D                          BKP_DR42_D_Msk                     /*!< Backup data */
1229 
1230 #define RTC_BKP_NUMBER 42
1231 
1232 /******************  Bit definition for BKP_RTCCR register  *******************/
1233 #define BKP_RTCCR_CAL_Pos                   (0U)
1234 #define BKP_RTCCR_CAL_Msk                   (0x7FUL << BKP_RTCCR_CAL_Pos)       /*!< 0x0000007F */
1235 #define BKP_RTCCR_CAL                       BKP_RTCCR_CAL_Msk                  /*!< Calibration value */
1236 #define BKP_RTCCR_CCO_Pos                   (7U)
1237 #define BKP_RTCCR_CCO_Msk                   (0x1UL << BKP_RTCCR_CCO_Pos)        /*!< 0x00000080 */
1238 #define BKP_RTCCR_CCO                       BKP_RTCCR_CCO_Msk                  /*!< Calibration Clock Output */
1239 #define BKP_RTCCR_ASOE_Pos                  (8U)
1240 #define BKP_RTCCR_ASOE_Msk                  (0x1UL << BKP_RTCCR_ASOE_Pos)       /*!< 0x00000100 */
1241 #define BKP_RTCCR_ASOE                      BKP_RTCCR_ASOE_Msk                 /*!< Alarm or Second Output Enable */
1242 #define BKP_RTCCR_ASOS_Pos                  (9U)
1243 #define BKP_RTCCR_ASOS_Msk                  (0x1UL << BKP_RTCCR_ASOS_Pos)       /*!< 0x00000200 */
1244 #define BKP_RTCCR_ASOS                      BKP_RTCCR_ASOS_Msk                 /*!< Alarm or Second Output Selection */
1245 
1246 /********************  Bit definition for BKP_CR register  ********************/
1247 #define BKP_CR_TPE_Pos                      (0U)
1248 #define BKP_CR_TPE_Msk                      (0x1UL << BKP_CR_TPE_Pos)           /*!< 0x00000001 */
1249 #define BKP_CR_TPE                          BKP_CR_TPE_Msk                     /*!< TAMPER pin enable */
1250 #define BKP_CR_TPAL_Pos                     (1U)
1251 #define BKP_CR_TPAL_Msk                     (0x1UL << BKP_CR_TPAL_Pos)          /*!< 0x00000002 */
1252 #define BKP_CR_TPAL                         BKP_CR_TPAL_Msk                    /*!< TAMPER pin active level */
1253 
1254 /*******************  Bit definition for BKP_CSR register  ********************/
1255 #define BKP_CSR_CTE_Pos                     (0U)
1256 #define BKP_CSR_CTE_Msk                     (0x1UL << BKP_CSR_CTE_Pos)          /*!< 0x00000001 */
1257 #define BKP_CSR_CTE                         BKP_CSR_CTE_Msk                    /*!< Clear Tamper event */
1258 #define BKP_CSR_CTI_Pos                     (1U)
1259 #define BKP_CSR_CTI_Msk                     (0x1UL << BKP_CSR_CTI_Pos)          /*!< 0x00000002 */
1260 #define BKP_CSR_CTI                         BKP_CSR_CTI_Msk                    /*!< Clear Tamper Interrupt */
1261 #define BKP_CSR_TPIE_Pos                    (2U)
1262 #define BKP_CSR_TPIE_Msk                    (0x1UL << BKP_CSR_TPIE_Pos)         /*!< 0x00000004 */
1263 #define BKP_CSR_TPIE                        BKP_CSR_TPIE_Msk                   /*!< TAMPER Pin interrupt enable */
1264 #define BKP_CSR_TEF_Pos                     (8U)
1265 #define BKP_CSR_TEF_Msk                     (0x1UL << BKP_CSR_TEF_Pos)          /*!< 0x00000100 */
1266 #define BKP_CSR_TEF                         BKP_CSR_TEF_Msk                    /*!< Tamper Event Flag */
1267 #define BKP_CSR_TIF_Pos                     (9U)
1268 #define BKP_CSR_TIF_Msk                     (0x1UL << BKP_CSR_TIF_Pos)          /*!< 0x00000200 */
1269 #define BKP_CSR_TIF                         BKP_CSR_TIF_Msk                    /*!< Tamper Interrupt Flag */
1270 
1271 /******************************************************************************/
1272 /*                                                                            */
1273 /*                         Reset and Clock Control                            */
1274 /*                                                                            */
1275 /******************************************************************************/
1276 
1277 /********************  Bit definition for RCC_CR register  ********************/
1278 #define RCC_CR_HSION_Pos                     (0U)
1279 #define RCC_CR_HSION_Msk                     (0x1UL << RCC_CR_HSION_Pos)        /*!< 0x00000001 */
1280 #define RCC_CR_HSION                         RCC_CR_HSION_Msk                  /*!< Internal High Speed clock enable */
1281 #define RCC_CR_HSIRDY_Pos                    (1U)
1282 #define RCC_CR_HSIRDY_Msk                    (0x1UL << RCC_CR_HSIRDY_Pos)       /*!< 0x00000002 */
1283 #define RCC_CR_HSIRDY                        RCC_CR_HSIRDY_Msk                 /*!< Internal High Speed clock ready flag */
1284 #define RCC_CR_HSITRIM_Pos                   (3U)
1285 #define RCC_CR_HSITRIM_Msk                   (0x1FUL << RCC_CR_HSITRIM_Pos)     /*!< 0x000000F8 */
1286 #define RCC_CR_HSITRIM                       RCC_CR_HSITRIM_Msk                /*!< Internal High Speed clock trimming */
1287 #define RCC_CR_HSICAL_Pos                    (8U)
1288 #define RCC_CR_HSICAL_Msk                    (0xFFUL << RCC_CR_HSICAL_Pos)      /*!< 0x0000FF00 */
1289 #define RCC_CR_HSICAL                        RCC_CR_HSICAL_Msk                 /*!< Internal High Speed clock Calibration */
1290 #define RCC_CR_HSEON_Pos                     (16U)
1291 #define RCC_CR_HSEON_Msk                     (0x1UL << RCC_CR_HSEON_Pos)        /*!< 0x00010000 */
1292 #define RCC_CR_HSEON                         RCC_CR_HSEON_Msk                  /*!< External High Speed clock enable */
1293 #define RCC_CR_HSERDY_Pos                    (17U)
1294 #define RCC_CR_HSERDY_Msk                    (0x1UL << RCC_CR_HSERDY_Pos)       /*!< 0x00020000 */
1295 #define RCC_CR_HSERDY                        RCC_CR_HSERDY_Msk                 /*!< External High Speed clock ready flag */
1296 #define RCC_CR_HSEBYP_Pos                    (18U)
1297 #define RCC_CR_HSEBYP_Msk                    (0x1UL << RCC_CR_HSEBYP_Pos)       /*!< 0x00040000 */
1298 #define RCC_CR_HSEBYP                        RCC_CR_HSEBYP_Msk                 /*!< External High Speed clock Bypass */
1299 #define RCC_CR_CSSON_Pos                     (19U)
1300 #define RCC_CR_CSSON_Msk                     (0x1UL << RCC_CR_CSSON_Pos)        /*!< 0x00080000 */
1301 #define RCC_CR_CSSON                         RCC_CR_CSSON_Msk                  /*!< Clock Security System enable */
1302 #define RCC_CR_PLLON_Pos                     (24U)
1303 #define RCC_CR_PLLON_Msk                     (0x1UL << RCC_CR_PLLON_Pos)        /*!< 0x01000000 */
1304 #define RCC_CR_PLLON                         RCC_CR_PLLON_Msk                  /*!< PLL enable */
1305 #define RCC_CR_PLLRDY_Pos                    (25U)
1306 #define RCC_CR_PLLRDY_Msk                    (0x1UL << RCC_CR_PLLRDY_Pos)       /*!< 0x02000000 */
1307 #define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< PLL clock ready flag */
1308 
1309 
1310 /*******************  Bit definition for RCC_CFGR register  *******************/
1311 /*!< SW configuration */
1312 #define RCC_CFGR_SW_Pos                      (0U)
1313 #define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
1314 #define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
1315 #define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
1316 #define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
1317 
1318 #define RCC_CFGR_SW_HSI                      0x00000000U                       /*!< HSI selected as system clock */
1319 #define RCC_CFGR_SW_HSE                      0x00000001U                       /*!< HSE selected as system clock */
1320 #define RCC_CFGR_SW_PLL                      0x00000002U                       /*!< PLL selected as system clock */
1321 
1322 /*!< SWS configuration */
1323 #define RCC_CFGR_SWS_Pos                     (2U)
1324 #define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
1325 #define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
1326 #define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
1327 #define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
1328 
1329 #define RCC_CFGR_SWS_HSI                     0x00000000U                       /*!< HSI oscillator used as system clock */
1330 #define RCC_CFGR_SWS_HSE                     0x00000004U                       /*!< HSE oscillator used as system clock */
1331 #define RCC_CFGR_SWS_PLL                     0x00000008U                       /*!< PLL used as system clock */
1332 
1333 /*!< HPRE configuration */
1334 #define RCC_CFGR_HPRE_Pos                    (4U)
1335 #define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
1336 #define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
1337 #define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
1338 #define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
1339 #define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
1340 #define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
1341 
1342 #define RCC_CFGR_HPRE_DIV1                   0x00000000U                       /*!< SYSCLK not divided */
1343 #define RCC_CFGR_HPRE_DIV2                   0x00000080U                       /*!< SYSCLK divided by 2 */
1344 #define RCC_CFGR_HPRE_DIV4                   0x00000090U                       /*!< SYSCLK divided by 4 */
1345 #define RCC_CFGR_HPRE_DIV8                   0x000000A0U                       /*!< SYSCLK divided by 8 */
1346 #define RCC_CFGR_HPRE_DIV16                  0x000000B0U                       /*!< SYSCLK divided by 16 */
1347 #define RCC_CFGR_HPRE_DIV64                  0x000000C0U                       /*!< SYSCLK divided by 64 */
1348 #define RCC_CFGR_HPRE_DIV128                 0x000000D0U                       /*!< SYSCLK divided by 128 */
1349 #define RCC_CFGR_HPRE_DIV256                 0x000000E0U                       /*!< SYSCLK divided by 256 */
1350 #define RCC_CFGR_HPRE_DIV512                 0x000000F0U                       /*!< SYSCLK divided by 512 */
1351 
1352 /*!< PPRE1 configuration */
1353 #define RCC_CFGR_PPRE1_Pos                   (8U)
1354 #define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
1355 #define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */
1356 #define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
1357 #define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
1358 #define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
1359 
1360 #define RCC_CFGR_PPRE1_DIV1                  0x00000000U                       /*!< HCLK not divided */
1361 #define RCC_CFGR_PPRE1_DIV2                  0x00000400U                       /*!< HCLK divided by 2 */
1362 #define RCC_CFGR_PPRE1_DIV4                  0x00000500U                       /*!< HCLK divided by 4 */
1363 #define RCC_CFGR_PPRE1_DIV8                  0x00000600U                       /*!< HCLK divided by 8 */
1364 #define RCC_CFGR_PPRE1_DIV16                 0x00000700U                       /*!< HCLK divided by 16 */
1365 
1366 /*!< PPRE2 configuration */
1367 #define RCC_CFGR_PPRE2_Pos                   (11U)
1368 #define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
1369 #define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
1370 #define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
1371 #define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
1372 #define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
1373 
1374 #define RCC_CFGR_PPRE2_DIV1                  0x00000000U                       /*!< HCLK not divided */
1375 #define RCC_CFGR_PPRE2_DIV2                  0x00002000U                       /*!< HCLK divided by 2 */
1376 #define RCC_CFGR_PPRE2_DIV4                  0x00002800U                       /*!< HCLK divided by 4 */
1377 #define RCC_CFGR_PPRE2_DIV8                  0x00003000U                       /*!< HCLK divided by 8 */
1378 #define RCC_CFGR_PPRE2_DIV16                 0x00003800U                       /*!< HCLK divided by 16 */
1379 
1380 /*!< ADCPPRE configuration */
1381 #define RCC_CFGR_ADCPRE_Pos                  (14U)
1382 #define RCC_CFGR_ADCPRE_Msk                  (0x3UL << RCC_CFGR_ADCPRE_Pos)     /*!< 0x0000C000 */
1383 #define RCC_CFGR_ADCPRE                      RCC_CFGR_ADCPRE_Msk               /*!< ADCPRE[1:0] bits (ADC prescaler) */
1384 #define RCC_CFGR_ADCPRE_0                    (0x1UL << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00004000 */
1385 #define RCC_CFGR_ADCPRE_1                    (0x2UL << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00008000 */
1386 
1387 #define RCC_CFGR_ADCPRE_DIV2                 0x00000000U                       /*!< PCLK2 divided by 2 */
1388 #define RCC_CFGR_ADCPRE_DIV4                 0x00004000U                       /*!< PCLK2 divided by 4 */
1389 #define RCC_CFGR_ADCPRE_DIV6                 0x00008000U                       /*!< PCLK2 divided by 6 */
1390 #define RCC_CFGR_ADCPRE_DIV8                 0x0000C000U                       /*!< PCLK2 divided by 8 */
1391 
1392 #define RCC_CFGR_PLLSRC_Pos                  (16U)
1393 #define RCC_CFGR_PLLSRC_Msk                  (0x1UL << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */
1394 #define RCC_CFGR_PLLSRC                      RCC_CFGR_PLLSRC_Msk               /*!< PLL entry clock source */
1395 
1396 #define RCC_CFGR_PLLXTPRE_Pos                (17U)
1397 #define RCC_CFGR_PLLXTPRE_Msk                (0x1UL << RCC_CFGR_PLLXTPRE_Pos)   /*!< 0x00020000 */
1398 #define RCC_CFGR_PLLXTPRE                    RCC_CFGR_PLLXTPRE_Msk             /*!< HSE divider for PLL entry */
1399 
1400 /*!< PLLMUL configuration */
1401 #define RCC_CFGR_PLLMULL_Pos                 (18U)
1402 #define RCC_CFGR_PLLMULL_Msk                 (0xFUL << RCC_CFGR_PLLMULL_Pos)    /*!< 0x003C0000 */
1403 #define RCC_CFGR_PLLMULL                     RCC_CFGR_PLLMULL_Msk              /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
1404 #define RCC_CFGR_PLLMULL_0                   (0x1UL << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00040000 */
1405 #define RCC_CFGR_PLLMULL_1                   (0x2UL << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00080000 */
1406 #define RCC_CFGR_PLLMULL_2                   (0x4UL << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00100000 */
1407 #define RCC_CFGR_PLLMULL_3                   (0x8UL << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00200000 */
1408 
1409 #define RCC_CFGR_PLLXTPRE_HSE                0x00000000U                      /*!< HSE clock not divided for PLL entry */
1410 #define RCC_CFGR_PLLXTPRE_HSE_DIV2           0x00020000U                      /*!< HSE clock divided by 2 for PLL entry */
1411 
1412 #define RCC_CFGR_PLLMULL2                    0x00000000U                       /*!< PLL input clock*2 */
1413 #define RCC_CFGR_PLLMULL3_Pos                (18U)
1414 #define RCC_CFGR_PLLMULL3_Msk                (0x1UL << RCC_CFGR_PLLMULL3_Pos)   /*!< 0x00040000 */
1415 #define RCC_CFGR_PLLMULL3                    RCC_CFGR_PLLMULL3_Msk             /*!< PLL input clock*3 */
1416 #define RCC_CFGR_PLLMULL4_Pos                (19U)
1417 #define RCC_CFGR_PLLMULL4_Msk                (0x1UL << RCC_CFGR_PLLMULL4_Pos)   /*!< 0x00080000 */
1418 #define RCC_CFGR_PLLMULL4                    RCC_CFGR_PLLMULL4_Msk             /*!< PLL input clock*4 */
1419 #define RCC_CFGR_PLLMULL5_Pos                (18U)
1420 #define RCC_CFGR_PLLMULL5_Msk                (0x3UL << RCC_CFGR_PLLMULL5_Pos)   /*!< 0x000C0000 */
1421 #define RCC_CFGR_PLLMULL5                    RCC_CFGR_PLLMULL5_Msk             /*!< PLL input clock*5 */
1422 #define RCC_CFGR_PLLMULL6_Pos                (20U)
1423 #define RCC_CFGR_PLLMULL6_Msk                (0x1UL << RCC_CFGR_PLLMULL6_Pos)   /*!< 0x00100000 */
1424 #define RCC_CFGR_PLLMULL6                    RCC_CFGR_PLLMULL6_Msk             /*!< PLL input clock*6 */
1425 #define RCC_CFGR_PLLMULL7_Pos                (18U)
1426 #define RCC_CFGR_PLLMULL7_Msk                (0x5UL << RCC_CFGR_PLLMULL7_Pos)   /*!< 0x00140000 */
1427 #define RCC_CFGR_PLLMULL7                    RCC_CFGR_PLLMULL7_Msk             /*!< PLL input clock*7 */
1428 #define RCC_CFGR_PLLMULL8_Pos                (19U)
1429 #define RCC_CFGR_PLLMULL8_Msk                (0x3UL << RCC_CFGR_PLLMULL8_Pos)   /*!< 0x00180000 */
1430 #define RCC_CFGR_PLLMULL8                    RCC_CFGR_PLLMULL8_Msk             /*!< PLL input clock*8 */
1431 #define RCC_CFGR_PLLMULL9_Pos                (18U)
1432 #define RCC_CFGR_PLLMULL9_Msk                (0x7UL << RCC_CFGR_PLLMULL9_Pos)   /*!< 0x001C0000 */
1433 #define RCC_CFGR_PLLMULL9                    RCC_CFGR_PLLMULL9_Msk             /*!< PLL input clock*9 */
1434 #define RCC_CFGR_PLLMULL10_Pos               (21U)
1435 #define RCC_CFGR_PLLMULL10_Msk               (0x1UL << RCC_CFGR_PLLMULL10_Pos)  /*!< 0x00200000 */
1436 #define RCC_CFGR_PLLMULL10                   RCC_CFGR_PLLMULL10_Msk            /*!< PLL input clock10 */
1437 #define RCC_CFGR_PLLMULL11_Pos               (18U)
1438 #define RCC_CFGR_PLLMULL11_Msk               (0x9UL << RCC_CFGR_PLLMULL11_Pos)  /*!< 0x00240000 */
1439 #define RCC_CFGR_PLLMULL11                   RCC_CFGR_PLLMULL11_Msk            /*!< PLL input clock*11 */
1440 #define RCC_CFGR_PLLMULL12_Pos               (19U)
1441 #define RCC_CFGR_PLLMULL12_Msk               (0x5UL << RCC_CFGR_PLLMULL12_Pos)  /*!< 0x00280000 */
1442 #define RCC_CFGR_PLLMULL12                   RCC_CFGR_PLLMULL12_Msk            /*!< PLL input clock*12 */
1443 #define RCC_CFGR_PLLMULL13_Pos               (18U)
1444 #define RCC_CFGR_PLLMULL13_Msk               (0xBUL << RCC_CFGR_PLLMULL13_Pos)  /*!< 0x002C0000 */
1445 #define RCC_CFGR_PLLMULL13                   RCC_CFGR_PLLMULL13_Msk            /*!< PLL input clock*13 */
1446 #define RCC_CFGR_PLLMULL14_Pos               (20U)
1447 #define RCC_CFGR_PLLMULL14_Msk               (0x3UL << RCC_CFGR_PLLMULL14_Pos)  /*!< 0x00300000 */
1448 #define RCC_CFGR_PLLMULL14                   RCC_CFGR_PLLMULL14_Msk            /*!< PLL input clock*14 */
1449 #define RCC_CFGR_PLLMULL15_Pos               (18U)
1450 #define RCC_CFGR_PLLMULL15_Msk               (0xDUL << RCC_CFGR_PLLMULL15_Pos)  /*!< 0x00340000 */
1451 #define RCC_CFGR_PLLMULL15                   RCC_CFGR_PLLMULL15_Msk            /*!< PLL input clock*15 */
1452 #define RCC_CFGR_PLLMULL16_Pos               (19U)
1453 #define RCC_CFGR_PLLMULL16_Msk               (0x7UL << RCC_CFGR_PLLMULL16_Pos)  /*!< 0x00380000 */
1454 #define RCC_CFGR_PLLMULL16                   RCC_CFGR_PLLMULL16_Msk            /*!< PLL input clock*16 */
1455 #define RCC_CFGR_USBPRE_Pos                  (22U)
1456 #define RCC_CFGR_USBPRE_Msk                  (0x1UL << RCC_CFGR_USBPRE_Pos)     /*!< 0x00400000 */
1457 #define RCC_CFGR_USBPRE                      RCC_CFGR_USBPRE_Msk               /*!< USB Device prescaler */
1458 
1459 /*!< MCO configuration */
1460 #define RCC_CFGR_MCO_Pos                     (24U)
1461 #define RCC_CFGR_MCO_Msk                     (0x7UL << RCC_CFGR_MCO_Pos)        /*!< 0x07000000 */
1462 #define RCC_CFGR_MCO                         RCC_CFGR_MCO_Msk                  /*!< MCO[2:0] bits (Microcontroller Clock Output) */
1463 #define RCC_CFGR_MCO_0                       (0x1UL << RCC_CFGR_MCO_Pos)        /*!< 0x01000000 */
1464 #define RCC_CFGR_MCO_1                       (0x2UL << RCC_CFGR_MCO_Pos)        /*!< 0x02000000 */
1465 #define RCC_CFGR_MCO_2                       (0x4UL << RCC_CFGR_MCO_Pos)        /*!< 0x04000000 */
1466 
1467 #define RCC_CFGR_MCO_NOCLOCK                 0x00000000U                        /*!< No clock */
1468 #define RCC_CFGR_MCO_SYSCLK                  0x04000000U                        /*!< System clock selected as MCO source */
1469 #define RCC_CFGR_MCO_HSI                     0x05000000U                        /*!< HSI clock selected as MCO source */
1470 #define RCC_CFGR_MCO_HSE                     0x06000000U                        /*!< HSE clock selected as MCO source  */
1471 #define RCC_CFGR_MCO_PLLCLK_DIV2             0x07000000U                        /*!< PLL clock divided by 2 selected as MCO source */
1472 
1473  /* Reference defines */
1474  #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCO
1475  #define RCC_CFGR_MCOSEL_0                    RCC_CFGR_MCO_0
1476  #define RCC_CFGR_MCOSEL_1                    RCC_CFGR_MCO_1
1477  #define RCC_CFGR_MCOSEL_2                    RCC_CFGR_MCO_2
1478  #define RCC_CFGR_MCOSEL_NOCLOCK              RCC_CFGR_MCO_NOCLOCK
1479  #define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCO_SYSCLK
1480  #define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCO_HSI
1481  #define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCO_HSE
1482  #define RCC_CFGR_MCOSEL_PLL_DIV2             RCC_CFGR_MCO_PLLCLK_DIV2
1483 
1484 /*!<******************  Bit definition for RCC_CIR register  ********************/
1485 #define RCC_CIR_LSIRDYF_Pos                  (0U)
1486 #define RCC_CIR_LSIRDYF_Msk                  (0x1UL << RCC_CIR_LSIRDYF_Pos)     /*!< 0x00000001 */
1487 #define RCC_CIR_LSIRDYF                      RCC_CIR_LSIRDYF_Msk               /*!< LSI Ready Interrupt flag */
1488 #define RCC_CIR_LSERDYF_Pos                  (1U)
1489 #define RCC_CIR_LSERDYF_Msk                  (0x1UL << RCC_CIR_LSERDYF_Pos)     /*!< 0x00000002 */
1490 #define RCC_CIR_LSERDYF                      RCC_CIR_LSERDYF_Msk               /*!< LSE Ready Interrupt flag */
1491 #define RCC_CIR_HSIRDYF_Pos                  (2U)
1492 #define RCC_CIR_HSIRDYF_Msk                  (0x1UL << RCC_CIR_HSIRDYF_Pos)     /*!< 0x00000004 */
1493 #define RCC_CIR_HSIRDYF                      RCC_CIR_HSIRDYF_Msk               /*!< HSI Ready Interrupt flag */
1494 #define RCC_CIR_HSERDYF_Pos                  (3U)
1495 #define RCC_CIR_HSERDYF_Msk                  (0x1UL << RCC_CIR_HSERDYF_Pos)     /*!< 0x00000008 */
1496 #define RCC_CIR_HSERDYF                      RCC_CIR_HSERDYF_Msk               /*!< HSE Ready Interrupt flag */
1497 #define RCC_CIR_PLLRDYF_Pos                  (4U)
1498 #define RCC_CIR_PLLRDYF_Msk                  (0x1UL << RCC_CIR_PLLRDYF_Pos)     /*!< 0x00000010 */
1499 #define RCC_CIR_PLLRDYF                      RCC_CIR_PLLRDYF_Msk               /*!< PLL Ready Interrupt flag */
1500 #define RCC_CIR_CSSF_Pos                     (7U)
1501 #define RCC_CIR_CSSF_Msk                     (0x1UL << RCC_CIR_CSSF_Pos)        /*!< 0x00000080 */
1502 #define RCC_CIR_CSSF                         RCC_CIR_CSSF_Msk                  /*!< Clock Security System Interrupt flag */
1503 #define RCC_CIR_LSIRDYIE_Pos                 (8U)
1504 #define RCC_CIR_LSIRDYIE_Msk                 (0x1UL << RCC_CIR_LSIRDYIE_Pos)    /*!< 0x00000100 */
1505 #define RCC_CIR_LSIRDYIE                     RCC_CIR_LSIRDYIE_Msk              /*!< LSI Ready Interrupt Enable */
1506 #define RCC_CIR_LSERDYIE_Pos                 (9U)
1507 #define RCC_CIR_LSERDYIE_Msk                 (0x1UL << RCC_CIR_LSERDYIE_Pos)    /*!< 0x00000200 */
1508 #define RCC_CIR_LSERDYIE                     RCC_CIR_LSERDYIE_Msk              /*!< LSE Ready Interrupt Enable */
1509 #define RCC_CIR_HSIRDYIE_Pos                 (10U)
1510 #define RCC_CIR_HSIRDYIE_Msk                 (0x1UL << RCC_CIR_HSIRDYIE_Pos)    /*!< 0x00000400 */
1511 #define RCC_CIR_HSIRDYIE                     RCC_CIR_HSIRDYIE_Msk              /*!< HSI Ready Interrupt Enable */
1512 #define RCC_CIR_HSERDYIE_Pos                 (11U)
1513 #define RCC_CIR_HSERDYIE_Msk                 (0x1UL << RCC_CIR_HSERDYIE_Pos)    /*!< 0x00000800 */
1514 #define RCC_CIR_HSERDYIE                     RCC_CIR_HSERDYIE_Msk              /*!< HSE Ready Interrupt Enable */
1515 #define RCC_CIR_PLLRDYIE_Pos                 (12U)
1516 #define RCC_CIR_PLLRDYIE_Msk                 (0x1UL << RCC_CIR_PLLRDYIE_Pos)    /*!< 0x00001000 */
1517 #define RCC_CIR_PLLRDYIE                     RCC_CIR_PLLRDYIE_Msk              /*!< PLL Ready Interrupt Enable */
1518 #define RCC_CIR_LSIRDYC_Pos                  (16U)
1519 #define RCC_CIR_LSIRDYC_Msk                  (0x1UL << RCC_CIR_LSIRDYC_Pos)     /*!< 0x00010000 */
1520 #define RCC_CIR_LSIRDYC                      RCC_CIR_LSIRDYC_Msk               /*!< LSI Ready Interrupt Clear */
1521 #define RCC_CIR_LSERDYC_Pos                  (17U)
1522 #define RCC_CIR_LSERDYC_Msk                  (0x1UL << RCC_CIR_LSERDYC_Pos)     /*!< 0x00020000 */
1523 #define RCC_CIR_LSERDYC                      RCC_CIR_LSERDYC_Msk               /*!< LSE Ready Interrupt Clear */
1524 #define RCC_CIR_HSIRDYC_Pos                  (18U)
1525 #define RCC_CIR_HSIRDYC_Msk                  (0x1UL << RCC_CIR_HSIRDYC_Pos)     /*!< 0x00040000 */
1526 #define RCC_CIR_HSIRDYC                      RCC_CIR_HSIRDYC_Msk               /*!< HSI Ready Interrupt Clear */
1527 #define RCC_CIR_HSERDYC_Pos                  (19U)
1528 #define RCC_CIR_HSERDYC_Msk                  (0x1UL << RCC_CIR_HSERDYC_Pos)     /*!< 0x00080000 */
1529 #define RCC_CIR_HSERDYC                      RCC_CIR_HSERDYC_Msk               /*!< HSE Ready Interrupt Clear */
1530 #define RCC_CIR_PLLRDYC_Pos                  (20U)
1531 #define RCC_CIR_PLLRDYC_Msk                  (0x1UL << RCC_CIR_PLLRDYC_Pos)     /*!< 0x00100000 */
1532 #define RCC_CIR_PLLRDYC                      RCC_CIR_PLLRDYC_Msk               /*!< PLL Ready Interrupt Clear */
1533 #define RCC_CIR_CSSC_Pos                     (23U)
1534 #define RCC_CIR_CSSC_Msk                     (0x1UL << RCC_CIR_CSSC_Pos)        /*!< 0x00800000 */
1535 #define RCC_CIR_CSSC                         RCC_CIR_CSSC_Msk                  /*!< Clock Security System Interrupt Clear */
1536 
1537 
1538 /*****************  Bit definition for RCC_APB2RSTR register  *****************/
1539 #define RCC_APB2RSTR_AFIORST_Pos             (0U)
1540 #define RCC_APB2RSTR_AFIORST_Msk             (0x1UL << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */
1541 #define RCC_APB2RSTR_AFIORST                 RCC_APB2RSTR_AFIORST_Msk          /*!< Alternate Function I/O reset */
1542 #define RCC_APB2RSTR_IOPARST_Pos             (2U)
1543 #define RCC_APB2RSTR_IOPARST_Msk             (0x1UL << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */
1544 #define RCC_APB2RSTR_IOPARST                 RCC_APB2RSTR_IOPARST_Msk          /*!< I/O port A reset */
1545 #define RCC_APB2RSTR_IOPBRST_Pos             (3U)
1546 #define RCC_APB2RSTR_IOPBRST_Msk             (0x1UL << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */
1547 #define RCC_APB2RSTR_IOPBRST                 RCC_APB2RSTR_IOPBRST_Msk          /*!< I/O port B reset */
1548 #define RCC_APB2RSTR_IOPCRST_Pos             (4U)
1549 #define RCC_APB2RSTR_IOPCRST_Msk             (0x1UL << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */
1550 #define RCC_APB2RSTR_IOPCRST                 RCC_APB2RSTR_IOPCRST_Msk          /*!< I/O port C reset */
1551 #define RCC_APB2RSTR_IOPDRST_Pos             (5U)
1552 #define RCC_APB2RSTR_IOPDRST_Msk             (0x1UL << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */
1553 #define RCC_APB2RSTR_IOPDRST                 RCC_APB2RSTR_IOPDRST_Msk          /*!< I/O port D reset */
1554 #define RCC_APB2RSTR_ADC1RST_Pos             (9U)
1555 #define RCC_APB2RSTR_ADC1RST_Msk             (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
1556 #define RCC_APB2RSTR_ADC1RST                 RCC_APB2RSTR_ADC1RST_Msk          /*!< ADC 1 interface reset */
1557 
1558 #define RCC_APB2RSTR_ADC2RST_Pos             (10U)
1559 #define RCC_APB2RSTR_ADC2RST_Msk             (0x1UL << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */
1560 #define RCC_APB2RSTR_ADC2RST                 RCC_APB2RSTR_ADC2RST_Msk          /*!< ADC 2 interface reset */
1561 
1562 #define RCC_APB2RSTR_TIM1RST_Pos             (11U)
1563 #define RCC_APB2RSTR_TIM1RST_Msk             (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
1564 #define RCC_APB2RSTR_TIM1RST                 RCC_APB2RSTR_TIM1RST_Msk          /*!< TIM1 Timer reset */
1565 #define RCC_APB2RSTR_SPI1RST_Pos             (12U)
1566 #define RCC_APB2RSTR_SPI1RST_Msk             (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
1567 #define RCC_APB2RSTR_SPI1RST                 RCC_APB2RSTR_SPI1RST_Msk          /*!< SPI 1 reset */
1568 #define RCC_APB2RSTR_USART1RST_Pos           (14U)
1569 #define RCC_APB2RSTR_USART1RST_Msk           (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
1570 #define RCC_APB2RSTR_USART1RST               RCC_APB2RSTR_USART1RST_Msk        /*!< USART1 reset */
1571 
1572 
1573 #define RCC_APB2RSTR_IOPERST_Pos             (6U)
1574 #define RCC_APB2RSTR_IOPERST_Msk             (0x1UL << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */
1575 #define RCC_APB2RSTR_IOPERST                 RCC_APB2RSTR_IOPERST_Msk          /*!< I/O port E reset */
1576 
1577 #define RCC_APB2RSTR_IOPFRST_Pos             (7U)
1578 #define RCC_APB2RSTR_IOPFRST_Msk             (0x1UL << RCC_APB2RSTR_IOPFRST_Pos) /*!< 0x00000080 */
1579 #define RCC_APB2RSTR_IOPFRST                 RCC_APB2RSTR_IOPFRST_Msk          /*!< I/O port F reset */
1580 #define RCC_APB2RSTR_IOPGRST_Pos             (8U)
1581 #define RCC_APB2RSTR_IOPGRST_Msk             (0x1UL << RCC_APB2RSTR_IOPGRST_Pos) /*!< 0x00000100 */
1582 #define RCC_APB2RSTR_IOPGRST                 RCC_APB2RSTR_IOPGRST_Msk          /*!< I/O port G reset */
1583 #define RCC_APB2RSTR_TIM8RST_Pos             (13U)
1584 #define RCC_APB2RSTR_TIM8RST_Msk             (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */
1585 #define RCC_APB2RSTR_TIM8RST                 RCC_APB2RSTR_TIM8RST_Msk          /*!< TIM8 Timer reset */
1586 #define RCC_APB2RSTR_ADC3RST_Pos             (15U)
1587 #define RCC_APB2RSTR_ADC3RST_Msk             (0x1UL << RCC_APB2RSTR_ADC3RST_Pos) /*!< 0x00008000 */
1588 #define RCC_APB2RSTR_ADC3RST                 RCC_APB2RSTR_ADC3RST_Msk          /*!< ADC3 interface reset */
1589 
1590 
1591 
1592 /*****************  Bit definition for RCC_APB1RSTR register  *****************/
1593 #define RCC_APB1RSTR_TIM2RST_Pos             (0U)
1594 #define RCC_APB1RSTR_TIM2RST_Msk             (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
1595 #define RCC_APB1RSTR_TIM2RST                 RCC_APB1RSTR_TIM2RST_Msk          /*!< Timer 2 reset */
1596 #define RCC_APB1RSTR_TIM3RST_Pos             (1U)
1597 #define RCC_APB1RSTR_TIM3RST_Msk             (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
1598 #define RCC_APB1RSTR_TIM3RST                 RCC_APB1RSTR_TIM3RST_Msk          /*!< Timer 3 reset */
1599 #define RCC_APB1RSTR_WWDGRST_Pos             (11U)
1600 #define RCC_APB1RSTR_WWDGRST_Msk             (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
1601 #define RCC_APB1RSTR_WWDGRST                 RCC_APB1RSTR_WWDGRST_Msk          /*!< Window Watchdog reset */
1602 #define RCC_APB1RSTR_USART2RST_Pos           (17U)
1603 #define RCC_APB1RSTR_USART2RST_Msk           (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
1604 #define RCC_APB1RSTR_USART2RST               RCC_APB1RSTR_USART2RST_Msk        /*!< USART 2 reset */
1605 #define RCC_APB1RSTR_I2C1RST_Pos             (21U)
1606 #define RCC_APB1RSTR_I2C1RST_Msk             (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
1607 #define RCC_APB1RSTR_I2C1RST                 RCC_APB1RSTR_I2C1RST_Msk          /*!< I2C 1 reset */
1608 
1609 #define RCC_APB1RSTR_CAN1RST_Pos             (25U)
1610 #define RCC_APB1RSTR_CAN1RST_Msk             (0x1UL << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
1611 #define RCC_APB1RSTR_CAN1RST                 RCC_APB1RSTR_CAN1RST_Msk          /*!< CAN1 reset */
1612 
1613 #define RCC_APB1RSTR_BKPRST_Pos              (27U)
1614 #define RCC_APB1RSTR_BKPRST_Msk              (0x1UL << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */
1615 #define RCC_APB1RSTR_BKPRST                  RCC_APB1RSTR_BKPRST_Msk           /*!< Backup interface reset */
1616 #define RCC_APB1RSTR_PWRRST_Pos              (28U)
1617 #define RCC_APB1RSTR_PWRRST_Msk              (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
1618 #define RCC_APB1RSTR_PWRRST                  RCC_APB1RSTR_PWRRST_Msk           /*!< Power interface reset */
1619 
1620 #define RCC_APB1RSTR_TIM4RST_Pos             (2U)
1621 #define RCC_APB1RSTR_TIM4RST_Msk             (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
1622 #define RCC_APB1RSTR_TIM4RST                 RCC_APB1RSTR_TIM4RST_Msk          /*!< Timer 4 reset */
1623 #define RCC_APB1RSTR_SPI2RST_Pos             (14U)
1624 #define RCC_APB1RSTR_SPI2RST_Msk             (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
1625 #define RCC_APB1RSTR_SPI2RST                 RCC_APB1RSTR_SPI2RST_Msk          /*!< SPI 2 reset */
1626 #define RCC_APB1RSTR_USART3RST_Pos           (18U)
1627 #define RCC_APB1RSTR_USART3RST_Msk           (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
1628 #define RCC_APB1RSTR_USART3RST               RCC_APB1RSTR_USART3RST_Msk        /*!< USART 3 reset */
1629 #define RCC_APB1RSTR_I2C2RST_Pos             (22U)
1630 #define RCC_APB1RSTR_I2C2RST_Msk             (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
1631 #define RCC_APB1RSTR_I2C2RST                 RCC_APB1RSTR_I2C2RST_Msk          /*!< I2C 2 reset */
1632 
1633 #define RCC_APB1RSTR_USBRST_Pos              (23U)
1634 #define RCC_APB1RSTR_USBRST_Msk              (0x1UL << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
1635 #define RCC_APB1RSTR_USBRST                  RCC_APB1RSTR_USBRST_Msk           /*!< USB Device reset */
1636 
1637 #define RCC_APB1RSTR_TIM5RST_Pos             (3U)
1638 #define RCC_APB1RSTR_TIM5RST_Msk             (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
1639 #define RCC_APB1RSTR_TIM5RST                 RCC_APB1RSTR_TIM5RST_Msk          /*!< Timer 5 reset */
1640 #define RCC_APB1RSTR_TIM6RST_Pos             (4U)
1641 #define RCC_APB1RSTR_TIM6RST_Msk             (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
1642 #define RCC_APB1RSTR_TIM6RST                 RCC_APB1RSTR_TIM6RST_Msk          /*!< Timer 6 reset */
1643 #define RCC_APB1RSTR_TIM7RST_Pos             (5U)
1644 #define RCC_APB1RSTR_TIM7RST_Msk             (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
1645 #define RCC_APB1RSTR_TIM7RST                 RCC_APB1RSTR_TIM7RST_Msk          /*!< Timer 7 reset */
1646 #define RCC_APB1RSTR_SPI3RST_Pos             (15U)
1647 #define RCC_APB1RSTR_SPI3RST_Msk             (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
1648 #define RCC_APB1RSTR_SPI3RST                 RCC_APB1RSTR_SPI3RST_Msk          /*!< SPI 3 reset */
1649 #define RCC_APB1RSTR_UART4RST_Pos            (19U)
1650 #define RCC_APB1RSTR_UART4RST_Msk            (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
1651 #define RCC_APB1RSTR_UART4RST                RCC_APB1RSTR_UART4RST_Msk         /*!< UART 4 reset */
1652 #define RCC_APB1RSTR_UART5RST_Pos            (20U)
1653 #define RCC_APB1RSTR_UART5RST_Msk            (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
1654 #define RCC_APB1RSTR_UART5RST                RCC_APB1RSTR_UART5RST_Msk         /*!< UART 5 reset */
1655 
1656 
1657 
1658 
1659 #define RCC_APB1RSTR_DACRST_Pos              (29U)
1660 #define RCC_APB1RSTR_DACRST_Msk              (0x1UL << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
1661 #define RCC_APB1RSTR_DACRST                  RCC_APB1RSTR_DACRST_Msk           /*!< DAC interface reset */
1662 
1663 /******************  Bit definition for RCC_AHBENR register  ******************/
1664 #define RCC_AHBENR_DMA1EN_Pos                (0U)
1665 #define RCC_AHBENR_DMA1EN_Msk                (0x1UL << RCC_AHBENR_DMA1EN_Pos)   /*!< 0x00000001 */
1666 #define RCC_AHBENR_DMA1EN                    RCC_AHBENR_DMA1EN_Msk             /*!< DMA1 clock enable */
1667 #define RCC_AHBENR_SRAMEN_Pos                (2U)
1668 #define RCC_AHBENR_SRAMEN_Msk                (0x1UL << RCC_AHBENR_SRAMEN_Pos)   /*!< 0x00000004 */
1669 #define RCC_AHBENR_SRAMEN                    RCC_AHBENR_SRAMEN_Msk             /*!< SRAM interface clock enable */
1670 #define RCC_AHBENR_FLITFEN_Pos               (4U)
1671 #define RCC_AHBENR_FLITFEN_Msk               (0x1UL << RCC_AHBENR_FLITFEN_Pos)  /*!< 0x00000010 */
1672 #define RCC_AHBENR_FLITFEN                   RCC_AHBENR_FLITFEN_Msk            /*!< FLITF clock enable */
1673 #define RCC_AHBENR_CRCEN_Pos                 (6U)
1674 #define RCC_AHBENR_CRCEN_Msk                 (0x1UL << RCC_AHBENR_CRCEN_Pos)    /*!< 0x00000040 */
1675 #define RCC_AHBENR_CRCEN                     RCC_AHBENR_CRCEN_Msk              /*!< CRC clock enable */
1676 
1677 #define RCC_AHBENR_DMA2EN_Pos                (1U)
1678 #define RCC_AHBENR_DMA2EN_Msk                (0x1UL << RCC_AHBENR_DMA2EN_Pos)   /*!< 0x00000002 */
1679 #define RCC_AHBENR_DMA2EN                    RCC_AHBENR_DMA2EN_Msk             /*!< DMA2 clock enable */
1680 
1681 #define RCC_AHBENR_FSMCEN_Pos                (8U)
1682 #define RCC_AHBENR_FSMCEN_Msk                (0x1UL << RCC_AHBENR_FSMCEN_Pos)   /*!< 0x00000100 */
1683 #define RCC_AHBENR_FSMCEN                    RCC_AHBENR_FSMCEN_Msk             /*!< FSMC clock enable */
1684 #define RCC_AHBENR_SDIOEN_Pos                (10U)
1685 #define RCC_AHBENR_SDIOEN_Msk                (0x1UL << RCC_AHBENR_SDIOEN_Pos)   /*!< 0x00000400 */
1686 #define RCC_AHBENR_SDIOEN                    RCC_AHBENR_SDIOEN_Msk             /*!< SDIO clock enable */
1687 
1688 
1689 /******************  Bit definition for RCC_APB2ENR register  *****************/
1690 #define RCC_APB2ENR_AFIOEN_Pos               (0U)
1691 #define RCC_APB2ENR_AFIOEN_Msk               (0x1UL << RCC_APB2ENR_AFIOEN_Pos)  /*!< 0x00000001 */
1692 #define RCC_APB2ENR_AFIOEN                   RCC_APB2ENR_AFIOEN_Msk            /*!< Alternate Function I/O clock enable */
1693 #define RCC_APB2ENR_IOPAEN_Pos               (2U)
1694 #define RCC_APB2ENR_IOPAEN_Msk               (0x1UL << RCC_APB2ENR_IOPAEN_Pos)  /*!< 0x00000004 */
1695 #define RCC_APB2ENR_IOPAEN                   RCC_APB2ENR_IOPAEN_Msk            /*!< I/O port A clock enable */
1696 #define RCC_APB2ENR_IOPBEN_Pos               (3U)
1697 #define RCC_APB2ENR_IOPBEN_Msk               (0x1UL << RCC_APB2ENR_IOPBEN_Pos)  /*!< 0x00000008 */
1698 #define RCC_APB2ENR_IOPBEN                   RCC_APB2ENR_IOPBEN_Msk            /*!< I/O port B clock enable */
1699 #define RCC_APB2ENR_IOPCEN_Pos               (4U)
1700 #define RCC_APB2ENR_IOPCEN_Msk               (0x1UL << RCC_APB2ENR_IOPCEN_Pos)  /*!< 0x00000010 */
1701 #define RCC_APB2ENR_IOPCEN                   RCC_APB2ENR_IOPCEN_Msk            /*!< I/O port C clock enable */
1702 #define RCC_APB2ENR_IOPDEN_Pos               (5U)
1703 #define RCC_APB2ENR_IOPDEN_Msk               (0x1UL << RCC_APB2ENR_IOPDEN_Pos)  /*!< 0x00000020 */
1704 #define RCC_APB2ENR_IOPDEN                   RCC_APB2ENR_IOPDEN_Msk            /*!< I/O port D clock enable */
1705 #define RCC_APB2ENR_ADC1EN_Pos               (9U)
1706 #define RCC_APB2ENR_ADC1EN_Msk               (0x1UL << RCC_APB2ENR_ADC1EN_Pos)  /*!< 0x00000200 */
1707 #define RCC_APB2ENR_ADC1EN                   RCC_APB2ENR_ADC1EN_Msk            /*!< ADC 1 interface clock enable */
1708 
1709 #define RCC_APB2ENR_ADC2EN_Pos               (10U)
1710 #define RCC_APB2ENR_ADC2EN_Msk               (0x1UL << RCC_APB2ENR_ADC2EN_Pos)  /*!< 0x00000400 */
1711 #define RCC_APB2ENR_ADC2EN                   RCC_APB2ENR_ADC2EN_Msk            /*!< ADC 2 interface clock enable */
1712 
1713 #define RCC_APB2ENR_TIM1EN_Pos               (11U)
1714 #define RCC_APB2ENR_TIM1EN_Msk               (0x1UL << RCC_APB2ENR_TIM1EN_Pos)  /*!< 0x00000800 */
1715 #define RCC_APB2ENR_TIM1EN                   RCC_APB2ENR_TIM1EN_Msk            /*!< TIM1 Timer clock enable */
1716 #define RCC_APB2ENR_SPI1EN_Pos               (12U)
1717 #define RCC_APB2ENR_SPI1EN_Msk               (0x1UL << RCC_APB2ENR_SPI1EN_Pos)  /*!< 0x00001000 */
1718 #define RCC_APB2ENR_SPI1EN                   RCC_APB2ENR_SPI1EN_Msk            /*!< SPI 1 clock enable */
1719 #define RCC_APB2ENR_USART1EN_Pos             (14U)
1720 #define RCC_APB2ENR_USART1EN_Msk             (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
1721 #define RCC_APB2ENR_USART1EN                 RCC_APB2ENR_USART1EN_Msk          /*!< USART1 clock enable */
1722 
1723 
1724 #define RCC_APB2ENR_IOPEEN_Pos               (6U)
1725 #define RCC_APB2ENR_IOPEEN_Msk               (0x1UL << RCC_APB2ENR_IOPEEN_Pos)  /*!< 0x00000040 */
1726 #define RCC_APB2ENR_IOPEEN                   RCC_APB2ENR_IOPEEN_Msk            /*!< I/O port E clock enable */
1727 
1728 #define RCC_APB2ENR_IOPFEN_Pos               (7U)
1729 #define RCC_APB2ENR_IOPFEN_Msk               (0x1UL << RCC_APB2ENR_IOPFEN_Pos)  /*!< 0x00000080 */
1730 #define RCC_APB2ENR_IOPFEN                   RCC_APB2ENR_IOPFEN_Msk            /*!< I/O port F clock enable */
1731 #define RCC_APB2ENR_IOPGEN_Pos               (8U)
1732 #define RCC_APB2ENR_IOPGEN_Msk               (0x1UL << RCC_APB2ENR_IOPGEN_Pos)  /*!< 0x00000100 */
1733 #define RCC_APB2ENR_IOPGEN                   RCC_APB2ENR_IOPGEN_Msk            /*!< I/O port G clock enable */
1734 #define RCC_APB2ENR_TIM8EN_Pos               (13U)
1735 #define RCC_APB2ENR_TIM8EN_Msk               (0x1UL << RCC_APB2ENR_TIM8EN_Pos)  /*!< 0x00002000 */
1736 #define RCC_APB2ENR_TIM8EN                   RCC_APB2ENR_TIM8EN_Msk            /*!< TIM8 Timer clock enable */
1737 #define RCC_APB2ENR_ADC3EN_Pos               (15U)
1738 #define RCC_APB2ENR_ADC3EN_Msk               (0x1UL << RCC_APB2ENR_ADC3EN_Pos)  /*!< 0x00008000 */
1739 #define RCC_APB2ENR_ADC3EN                   RCC_APB2ENR_ADC3EN_Msk            /*!< DMA1 clock enable */
1740 
1741 
1742 
1743 /*****************  Bit definition for RCC_APB1ENR register  ******************/
1744 #define RCC_APB1ENR_TIM2EN_Pos               (0U)
1745 #define RCC_APB1ENR_TIM2EN_Msk               (0x1UL << RCC_APB1ENR_TIM2EN_Pos)  /*!< 0x00000001 */
1746 #define RCC_APB1ENR_TIM2EN                   RCC_APB1ENR_TIM2EN_Msk            /*!< Timer 2 clock enabled*/
1747 #define RCC_APB1ENR_TIM3EN_Pos               (1U)
1748 #define RCC_APB1ENR_TIM3EN_Msk               (0x1UL << RCC_APB1ENR_TIM3EN_Pos)  /*!< 0x00000002 */
1749 #define RCC_APB1ENR_TIM3EN                   RCC_APB1ENR_TIM3EN_Msk            /*!< Timer 3 clock enable */
1750 #define RCC_APB1ENR_WWDGEN_Pos               (11U)
1751 #define RCC_APB1ENR_WWDGEN_Msk               (0x1UL << RCC_APB1ENR_WWDGEN_Pos)  /*!< 0x00000800 */
1752 #define RCC_APB1ENR_WWDGEN                   RCC_APB1ENR_WWDGEN_Msk            /*!< Window Watchdog clock enable */
1753 #define RCC_APB1ENR_USART2EN_Pos             (17U)
1754 #define RCC_APB1ENR_USART2EN_Msk             (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
1755 #define RCC_APB1ENR_USART2EN                 RCC_APB1ENR_USART2EN_Msk          /*!< USART 2 clock enable */
1756 #define RCC_APB1ENR_I2C1EN_Pos               (21U)
1757 #define RCC_APB1ENR_I2C1EN_Msk               (0x1UL << RCC_APB1ENR_I2C1EN_Pos)  /*!< 0x00200000 */
1758 #define RCC_APB1ENR_I2C1EN                   RCC_APB1ENR_I2C1EN_Msk            /*!< I2C 1 clock enable */
1759 
1760 #define RCC_APB1ENR_CAN1EN_Pos               (25U)
1761 #define RCC_APB1ENR_CAN1EN_Msk               (0x1UL << RCC_APB1ENR_CAN1EN_Pos)  /*!< 0x02000000 */
1762 #define RCC_APB1ENR_CAN1EN                   RCC_APB1ENR_CAN1EN_Msk            /*!< CAN1 clock enable */
1763 
1764 #define RCC_APB1ENR_BKPEN_Pos                (27U)
1765 #define RCC_APB1ENR_BKPEN_Msk                (0x1UL << RCC_APB1ENR_BKPEN_Pos)   /*!< 0x08000000 */
1766 #define RCC_APB1ENR_BKPEN                    RCC_APB1ENR_BKPEN_Msk             /*!< Backup interface clock enable */
1767 #define RCC_APB1ENR_PWREN_Pos                (28U)
1768 #define RCC_APB1ENR_PWREN_Msk                (0x1UL << RCC_APB1ENR_PWREN_Pos)   /*!< 0x10000000 */
1769 #define RCC_APB1ENR_PWREN                    RCC_APB1ENR_PWREN_Msk             /*!< Power interface clock enable */
1770 
1771 #define RCC_APB1ENR_TIM4EN_Pos               (2U)
1772 #define RCC_APB1ENR_TIM4EN_Msk               (0x1UL << RCC_APB1ENR_TIM4EN_Pos)  /*!< 0x00000004 */
1773 #define RCC_APB1ENR_TIM4EN                   RCC_APB1ENR_TIM4EN_Msk            /*!< Timer 4 clock enable */
1774 #define RCC_APB1ENR_SPI2EN_Pos               (14U)
1775 #define RCC_APB1ENR_SPI2EN_Msk               (0x1UL << RCC_APB1ENR_SPI2EN_Pos)  /*!< 0x00004000 */
1776 #define RCC_APB1ENR_SPI2EN                   RCC_APB1ENR_SPI2EN_Msk            /*!< SPI 2 clock enable */
1777 #define RCC_APB1ENR_USART3EN_Pos             (18U)
1778 #define RCC_APB1ENR_USART3EN_Msk             (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
1779 #define RCC_APB1ENR_USART3EN                 RCC_APB1ENR_USART3EN_Msk          /*!< USART 3 clock enable */
1780 #define RCC_APB1ENR_I2C2EN_Pos               (22U)
1781 #define RCC_APB1ENR_I2C2EN_Msk               (0x1UL << RCC_APB1ENR_I2C2EN_Pos)  /*!< 0x00400000 */
1782 #define RCC_APB1ENR_I2C2EN                   RCC_APB1ENR_I2C2EN_Msk            /*!< I2C 2 clock enable */
1783 
1784 #define RCC_APB1ENR_USBEN_Pos                (23U)
1785 #define RCC_APB1ENR_USBEN_Msk                (0x1UL << RCC_APB1ENR_USBEN_Pos)   /*!< 0x00800000 */
1786 #define RCC_APB1ENR_USBEN                    RCC_APB1ENR_USBEN_Msk             /*!< USB Device clock enable */
1787 
1788 #define RCC_APB1ENR_TIM5EN_Pos               (3U)
1789 #define RCC_APB1ENR_TIM5EN_Msk               (0x1UL << RCC_APB1ENR_TIM5EN_Pos)  /*!< 0x00000008 */
1790 #define RCC_APB1ENR_TIM5EN                   RCC_APB1ENR_TIM5EN_Msk            /*!< Timer 5 clock enable */
1791 #define RCC_APB1ENR_TIM6EN_Pos               (4U)
1792 #define RCC_APB1ENR_TIM6EN_Msk               (0x1UL << RCC_APB1ENR_TIM6EN_Pos)  /*!< 0x00000010 */
1793 #define RCC_APB1ENR_TIM6EN                   RCC_APB1ENR_TIM6EN_Msk            /*!< Timer 6 clock enable */
1794 #define RCC_APB1ENR_TIM7EN_Pos               (5U)
1795 #define RCC_APB1ENR_TIM7EN_Msk               (0x1UL << RCC_APB1ENR_TIM7EN_Pos)  /*!< 0x00000020 */
1796 #define RCC_APB1ENR_TIM7EN                   RCC_APB1ENR_TIM7EN_Msk            /*!< Timer 7 clock enable */
1797 #define RCC_APB1ENR_SPI3EN_Pos               (15U)
1798 #define RCC_APB1ENR_SPI3EN_Msk               (0x1UL << RCC_APB1ENR_SPI3EN_Pos)  /*!< 0x00008000 */
1799 #define RCC_APB1ENR_SPI3EN                   RCC_APB1ENR_SPI3EN_Msk            /*!< SPI 3 clock enable */
1800 #define RCC_APB1ENR_UART4EN_Pos              (19U)
1801 #define RCC_APB1ENR_UART4EN_Msk              (0x1UL << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
1802 #define RCC_APB1ENR_UART4EN                  RCC_APB1ENR_UART4EN_Msk           /*!< UART 4 clock enable */
1803 #define RCC_APB1ENR_UART5EN_Pos              (20U)
1804 #define RCC_APB1ENR_UART5EN_Msk              (0x1UL << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
1805 #define RCC_APB1ENR_UART5EN                  RCC_APB1ENR_UART5EN_Msk           /*!< UART 5 clock enable */
1806 
1807 
1808 
1809 
1810 #define RCC_APB1ENR_DACEN_Pos                (29U)
1811 #define RCC_APB1ENR_DACEN_Msk                (0x1UL << RCC_APB1ENR_DACEN_Pos)   /*!< 0x20000000 */
1812 #define RCC_APB1ENR_DACEN                    RCC_APB1ENR_DACEN_Msk             /*!< DAC interface clock enable */
1813 
1814 /*******************  Bit definition for RCC_BDCR register  *******************/
1815 #define RCC_BDCR_LSEON_Pos                   (0U)
1816 #define RCC_BDCR_LSEON_Msk                   (0x1UL << RCC_BDCR_LSEON_Pos)      /*!< 0x00000001 */
1817 #define RCC_BDCR_LSEON                       RCC_BDCR_LSEON_Msk                /*!< External Low Speed oscillator enable */
1818 #define RCC_BDCR_LSERDY_Pos                  (1U)
1819 #define RCC_BDCR_LSERDY_Msk                  (0x1UL << RCC_BDCR_LSERDY_Pos)     /*!< 0x00000002 */
1820 #define RCC_BDCR_LSERDY                      RCC_BDCR_LSERDY_Msk               /*!< External Low Speed oscillator Ready */
1821 #define RCC_BDCR_LSEBYP_Pos                  (2U)
1822 #define RCC_BDCR_LSEBYP_Msk                  (0x1UL << RCC_BDCR_LSEBYP_Pos)     /*!< 0x00000004 */
1823 #define RCC_BDCR_LSEBYP                      RCC_BDCR_LSEBYP_Msk               /*!< External Low Speed oscillator Bypass */
1824 
1825 #define RCC_BDCR_RTCSEL_Pos                  (8U)
1826 #define RCC_BDCR_RTCSEL_Msk                  (0x3UL << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000300 */
1827 #define RCC_BDCR_RTCSEL                      RCC_BDCR_RTCSEL_Msk               /*!< RTCSEL[1:0] bits (RTC clock source selection) */
1828 #define RCC_BDCR_RTCSEL_0                    (0x1UL << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000100 */
1829 #define RCC_BDCR_RTCSEL_1                    (0x2UL << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000200 */
1830 
1831 /*!< RTC congiguration */
1832 #define RCC_BDCR_RTCSEL_NOCLOCK              0x00000000U                       /*!< No clock */
1833 #define RCC_BDCR_RTCSEL_LSE                  0x00000100U                       /*!< LSE oscillator clock used as RTC clock */
1834 #define RCC_BDCR_RTCSEL_LSI                  0x00000200U                       /*!< LSI oscillator clock used as RTC clock */
1835 #define RCC_BDCR_RTCSEL_HSE                  0x00000300U                       /*!< HSE oscillator clock divided by 128 used as RTC clock */
1836 
1837 #define RCC_BDCR_RTCEN_Pos                   (15U)
1838 #define RCC_BDCR_RTCEN_Msk                   (0x1UL << RCC_BDCR_RTCEN_Pos)      /*!< 0x00008000 */
1839 #define RCC_BDCR_RTCEN                       RCC_BDCR_RTCEN_Msk                /*!< RTC clock enable */
1840 #define RCC_BDCR_BDRST_Pos                   (16U)
1841 #define RCC_BDCR_BDRST_Msk                   (0x1UL << RCC_BDCR_BDRST_Pos)      /*!< 0x00010000 */
1842 #define RCC_BDCR_BDRST                       RCC_BDCR_BDRST_Msk                /*!< Backup domain software reset  */
1843 
1844 /*******************  Bit definition for RCC_CSR register  ********************/
1845 #define RCC_CSR_LSION_Pos                    (0U)
1846 #define RCC_CSR_LSION_Msk                    (0x1UL << RCC_CSR_LSION_Pos)       /*!< 0x00000001 */
1847 #define RCC_CSR_LSION                        RCC_CSR_LSION_Msk                 /*!< Internal Low Speed oscillator enable */
1848 #define RCC_CSR_LSIRDY_Pos                   (1U)
1849 #define RCC_CSR_LSIRDY_Msk                   (0x1UL << RCC_CSR_LSIRDY_Pos)      /*!< 0x00000002 */
1850 #define RCC_CSR_LSIRDY                       RCC_CSR_LSIRDY_Msk                /*!< Internal Low Speed oscillator Ready */
1851 #define RCC_CSR_RMVF_Pos                     (24U)
1852 #define RCC_CSR_RMVF_Msk                     (0x1UL << RCC_CSR_RMVF_Pos)        /*!< 0x01000000 */
1853 #define RCC_CSR_RMVF                         RCC_CSR_RMVF_Msk                  /*!< Remove reset flag */
1854 #define RCC_CSR_PINRSTF_Pos                  (26U)
1855 #define RCC_CSR_PINRSTF_Msk                  (0x1UL << RCC_CSR_PINRSTF_Pos)     /*!< 0x04000000 */
1856 #define RCC_CSR_PINRSTF                      RCC_CSR_PINRSTF_Msk               /*!< PIN reset flag */
1857 #define RCC_CSR_PORRSTF_Pos                  (27U)
1858 #define RCC_CSR_PORRSTF_Msk                  (0x1UL << RCC_CSR_PORRSTF_Pos)     /*!< 0x08000000 */
1859 #define RCC_CSR_PORRSTF                      RCC_CSR_PORRSTF_Msk               /*!< POR/PDR reset flag */
1860 #define RCC_CSR_SFTRSTF_Pos                  (28U)
1861 #define RCC_CSR_SFTRSTF_Msk                  (0x1UL << RCC_CSR_SFTRSTF_Pos)     /*!< 0x10000000 */
1862 #define RCC_CSR_SFTRSTF                      RCC_CSR_SFTRSTF_Msk               /*!< Software Reset flag */
1863 #define RCC_CSR_IWDGRSTF_Pos                 (29U)
1864 #define RCC_CSR_IWDGRSTF_Msk                 (0x1UL << RCC_CSR_IWDGRSTF_Pos)    /*!< 0x20000000 */
1865 #define RCC_CSR_IWDGRSTF                     RCC_CSR_IWDGRSTF_Msk              /*!< Independent Watchdog reset flag */
1866 #define RCC_CSR_WWDGRSTF_Pos                 (30U)
1867 #define RCC_CSR_WWDGRSTF_Msk                 (0x1UL << RCC_CSR_WWDGRSTF_Pos)    /*!< 0x40000000 */
1868 #define RCC_CSR_WWDGRSTF                     RCC_CSR_WWDGRSTF_Msk              /*!< Window watchdog reset flag */
1869 #define RCC_CSR_LPWRRSTF_Pos                 (31U)
1870 #define RCC_CSR_LPWRRSTF_Msk                 (0x1UL << RCC_CSR_LPWRRSTF_Pos)    /*!< 0x80000000 */
1871 #define RCC_CSR_LPWRRSTF                     RCC_CSR_LPWRRSTF_Msk              /*!< Low-Power reset flag */
1872 
1873 
1874 
1875 /******************************************************************************/
1876 /*                                                                            */
1877 /*                General Purpose and Alternate Function I/O                  */
1878 /*                                                                            */
1879 /******************************************************************************/
1880 
1881 /*******************  Bit definition for GPIO_CRL register  *******************/
1882 #define GPIO_CRL_MODE_Pos                    (0U)
1883 #define GPIO_CRL_MODE_Msk                    (0x33333333UL << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */
1884 #define GPIO_CRL_MODE                        GPIO_CRL_MODE_Msk                 /*!< Port x mode bits */
1885 
1886 #define GPIO_CRL_MODE0_Pos                   (0U)
1887 #define GPIO_CRL_MODE0_Msk                   (0x3UL << GPIO_CRL_MODE0_Pos)      /*!< 0x00000003 */
1888 #define GPIO_CRL_MODE0                       GPIO_CRL_MODE0_Msk                /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
1889 #define GPIO_CRL_MODE0_0                     (0x1UL << GPIO_CRL_MODE0_Pos)      /*!< 0x00000001 */
1890 #define GPIO_CRL_MODE0_1                     (0x2UL << GPIO_CRL_MODE0_Pos)      /*!< 0x00000002 */
1891 
1892 #define GPIO_CRL_MODE1_Pos                   (4U)
1893 #define GPIO_CRL_MODE1_Msk                   (0x3UL << GPIO_CRL_MODE1_Pos)      /*!< 0x00000030 */
1894 #define GPIO_CRL_MODE1                       GPIO_CRL_MODE1_Msk                /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
1895 #define GPIO_CRL_MODE1_0                     (0x1UL << GPIO_CRL_MODE1_Pos)      /*!< 0x00000010 */
1896 #define GPIO_CRL_MODE1_1                     (0x2UL << GPIO_CRL_MODE1_Pos)      /*!< 0x00000020 */
1897 
1898 #define GPIO_CRL_MODE2_Pos                   (8U)
1899 #define GPIO_CRL_MODE2_Msk                   (0x3UL << GPIO_CRL_MODE2_Pos)      /*!< 0x00000300 */
1900 #define GPIO_CRL_MODE2                       GPIO_CRL_MODE2_Msk                /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
1901 #define GPIO_CRL_MODE2_0                     (0x1UL << GPIO_CRL_MODE2_Pos)      /*!< 0x00000100 */
1902 #define GPIO_CRL_MODE2_1                     (0x2UL << GPIO_CRL_MODE2_Pos)      /*!< 0x00000200 */
1903 
1904 #define GPIO_CRL_MODE3_Pos                   (12U)
1905 #define GPIO_CRL_MODE3_Msk                   (0x3UL << GPIO_CRL_MODE3_Pos)      /*!< 0x00003000 */
1906 #define GPIO_CRL_MODE3                       GPIO_CRL_MODE3_Msk                /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
1907 #define GPIO_CRL_MODE3_0                     (0x1UL << GPIO_CRL_MODE3_Pos)      /*!< 0x00001000 */
1908 #define GPIO_CRL_MODE3_1                     (0x2UL << GPIO_CRL_MODE3_Pos)      /*!< 0x00002000 */
1909 
1910 #define GPIO_CRL_MODE4_Pos                   (16U)
1911 #define GPIO_CRL_MODE4_Msk                   (0x3UL << GPIO_CRL_MODE4_Pos)      /*!< 0x00030000 */
1912 #define GPIO_CRL_MODE4                       GPIO_CRL_MODE4_Msk                /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
1913 #define GPIO_CRL_MODE4_0                     (0x1UL << GPIO_CRL_MODE4_Pos)      /*!< 0x00010000 */
1914 #define GPIO_CRL_MODE4_1                     (0x2UL << GPIO_CRL_MODE4_Pos)      /*!< 0x00020000 */
1915 
1916 #define GPIO_CRL_MODE5_Pos                   (20U)
1917 #define GPIO_CRL_MODE5_Msk                   (0x3UL << GPIO_CRL_MODE5_Pos)      /*!< 0x00300000 */
1918 #define GPIO_CRL_MODE5                       GPIO_CRL_MODE5_Msk                /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
1919 #define GPIO_CRL_MODE5_0                     (0x1UL << GPIO_CRL_MODE5_Pos)      /*!< 0x00100000 */
1920 #define GPIO_CRL_MODE5_1                     (0x2UL << GPIO_CRL_MODE5_Pos)      /*!< 0x00200000 */
1921 
1922 #define GPIO_CRL_MODE6_Pos                   (24U)
1923 #define GPIO_CRL_MODE6_Msk                   (0x3UL << GPIO_CRL_MODE6_Pos)      /*!< 0x03000000 */
1924 #define GPIO_CRL_MODE6                       GPIO_CRL_MODE6_Msk                /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
1925 #define GPIO_CRL_MODE6_0                     (0x1UL << GPIO_CRL_MODE6_Pos)      /*!< 0x01000000 */
1926 #define GPIO_CRL_MODE6_1                     (0x2UL << GPIO_CRL_MODE6_Pos)      /*!< 0x02000000 */
1927 
1928 #define GPIO_CRL_MODE7_Pos                   (28U)
1929 #define GPIO_CRL_MODE7_Msk                   (0x3UL << GPIO_CRL_MODE7_Pos)      /*!< 0x30000000 */
1930 #define GPIO_CRL_MODE7                       GPIO_CRL_MODE7_Msk                /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
1931 #define GPIO_CRL_MODE7_0                     (0x1UL << GPIO_CRL_MODE7_Pos)      /*!< 0x10000000 */
1932 #define GPIO_CRL_MODE7_1                     (0x2UL << GPIO_CRL_MODE7_Pos)      /*!< 0x20000000 */
1933 
1934 #define GPIO_CRL_CNF_Pos                     (2U)
1935 #define GPIO_CRL_CNF_Msk                     (0x33333333UL << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */
1936 #define GPIO_CRL_CNF                         GPIO_CRL_CNF_Msk                  /*!< Port x configuration bits */
1937 
1938 #define GPIO_CRL_CNF0_Pos                    (2U)
1939 #define GPIO_CRL_CNF0_Msk                    (0x3UL << GPIO_CRL_CNF0_Pos)       /*!< 0x0000000C */
1940 #define GPIO_CRL_CNF0                        GPIO_CRL_CNF0_Msk                 /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
1941 #define GPIO_CRL_CNF0_0                      (0x1UL << GPIO_CRL_CNF0_Pos)       /*!< 0x00000004 */
1942 #define GPIO_CRL_CNF0_1                      (0x2UL << GPIO_CRL_CNF0_Pos)       /*!< 0x00000008 */
1943 
1944 #define GPIO_CRL_CNF1_Pos                    (6U)
1945 #define GPIO_CRL_CNF1_Msk                    (0x3UL << GPIO_CRL_CNF1_Pos)       /*!< 0x000000C0 */
1946 #define GPIO_CRL_CNF1                        GPIO_CRL_CNF1_Msk                 /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
1947 #define GPIO_CRL_CNF1_0                      (0x1UL << GPIO_CRL_CNF1_Pos)       /*!< 0x00000040 */
1948 #define GPIO_CRL_CNF1_1                      (0x2UL << GPIO_CRL_CNF1_Pos)       /*!< 0x00000080 */
1949 
1950 #define GPIO_CRL_CNF2_Pos                    (10U)
1951 #define GPIO_CRL_CNF2_Msk                    (0x3UL << GPIO_CRL_CNF2_Pos)       /*!< 0x00000C00 */
1952 #define GPIO_CRL_CNF2                        GPIO_CRL_CNF2_Msk                 /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
1953 #define GPIO_CRL_CNF2_0                      (0x1UL << GPIO_CRL_CNF2_Pos)       /*!< 0x00000400 */
1954 #define GPIO_CRL_CNF2_1                      (0x2UL << GPIO_CRL_CNF2_Pos)       /*!< 0x00000800 */
1955 
1956 #define GPIO_CRL_CNF3_Pos                    (14U)
1957 #define GPIO_CRL_CNF3_Msk                    (0x3UL << GPIO_CRL_CNF3_Pos)       /*!< 0x0000C000 */
1958 #define GPIO_CRL_CNF3                        GPIO_CRL_CNF3_Msk                 /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
1959 #define GPIO_CRL_CNF3_0                      (0x1UL << GPIO_CRL_CNF3_Pos)       /*!< 0x00004000 */
1960 #define GPIO_CRL_CNF3_1                      (0x2UL << GPIO_CRL_CNF3_Pos)       /*!< 0x00008000 */
1961 
1962 #define GPIO_CRL_CNF4_Pos                    (18U)
1963 #define GPIO_CRL_CNF4_Msk                    (0x3UL << GPIO_CRL_CNF4_Pos)       /*!< 0x000C0000 */
1964 #define GPIO_CRL_CNF4                        GPIO_CRL_CNF4_Msk                 /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
1965 #define GPIO_CRL_CNF4_0                      (0x1UL << GPIO_CRL_CNF4_Pos)       /*!< 0x00040000 */
1966 #define GPIO_CRL_CNF4_1                      (0x2UL << GPIO_CRL_CNF4_Pos)       /*!< 0x00080000 */
1967 
1968 #define GPIO_CRL_CNF5_Pos                    (22U)
1969 #define GPIO_CRL_CNF5_Msk                    (0x3UL << GPIO_CRL_CNF5_Pos)       /*!< 0x00C00000 */
1970 #define GPIO_CRL_CNF5                        GPIO_CRL_CNF5_Msk                 /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
1971 #define GPIO_CRL_CNF5_0                      (0x1UL << GPIO_CRL_CNF5_Pos)       /*!< 0x00400000 */
1972 #define GPIO_CRL_CNF5_1                      (0x2UL << GPIO_CRL_CNF5_Pos)       /*!< 0x00800000 */
1973 
1974 #define GPIO_CRL_CNF6_Pos                    (26U)
1975 #define GPIO_CRL_CNF6_Msk                    (0x3UL << GPIO_CRL_CNF6_Pos)       /*!< 0x0C000000 */
1976 #define GPIO_CRL_CNF6                        GPIO_CRL_CNF6_Msk                 /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
1977 #define GPIO_CRL_CNF6_0                      (0x1UL << GPIO_CRL_CNF6_Pos)       /*!< 0x04000000 */
1978 #define GPIO_CRL_CNF6_1                      (0x2UL << GPIO_CRL_CNF6_Pos)       /*!< 0x08000000 */
1979 
1980 #define GPIO_CRL_CNF7_Pos                    (30U)
1981 #define GPIO_CRL_CNF7_Msk                    (0x3UL << GPIO_CRL_CNF7_Pos)       /*!< 0xC0000000 */
1982 #define GPIO_CRL_CNF7                        GPIO_CRL_CNF7_Msk                 /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
1983 #define GPIO_CRL_CNF7_0                      (0x1UL << GPIO_CRL_CNF7_Pos)       /*!< 0x40000000 */
1984 #define GPIO_CRL_CNF7_1                      (0x2UL << GPIO_CRL_CNF7_Pos)       /*!< 0x80000000 */
1985 
1986 /*******************  Bit definition for GPIO_CRH register  *******************/
1987 #define GPIO_CRH_MODE_Pos                    (0U)
1988 #define GPIO_CRH_MODE_Msk                    (0x33333333UL << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */
1989 #define GPIO_CRH_MODE                        GPIO_CRH_MODE_Msk                 /*!< Port x mode bits */
1990 
1991 #define GPIO_CRH_MODE8_Pos                   (0U)
1992 #define GPIO_CRH_MODE8_Msk                   (0x3UL << GPIO_CRH_MODE8_Pos)      /*!< 0x00000003 */
1993 #define GPIO_CRH_MODE8                       GPIO_CRH_MODE8_Msk                /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
1994 #define GPIO_CRH_MODE8_0                     (0x1UL << GPIO_CRH_MODE8_Pos)      /*!< 0x00000001 */
1995 #define GPIO_CRH_MODE8_1                     (0x2UL << GPIO_CRH_MODE8_Pos)      /*!< 0x00000002 */
1996 
1997 #define GPIO_CRH_MODE9_Pos                   (4U)
1998 #define GPIO_CRH_MODE9_Msk                   (0x3UL << GPIO_CRH_MODE9_Pos)      /*!< 0x00000030 */
1999 #define GPIO_CRH_MODE9                       GPIO_CRH_MODE9_Msk                /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
2000 #define GPIO_CRH_MODE9_0                     (0x1UL << GPIO_CRH_MODE9_Pos)      /*!< 0x00000010 */
2001 #define GPIO_CRH_MODE9_1                     (0x2UL << GPIO_CRH_MODE9_Pos)      /*!< 0x00000020 */
2002 
2003 #define GPIO_CRH_MODE10_Pos                  (8U)
2004 #define GPIO_CRH_MODE10_Msk                  (0x3UL << GPIO_CRH_MODE10_Pos)     /*!< 0x00000300 */
2005 #define GPIO_CRH_MODE10                      GPIO_CRH_MODE10_Msk               /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
2006 #define GPIO_CRH_MODE10_0                    (0x1UL << GPIO_CRH_MODE10_Pos)     /*!< 0x00000100 */
2007 #define GPIO_CRH_MODE10_1                    (0x2UL << GPIO_CRH_MODE10_Pos)     /*!< 0x00000200 */
2008 
2009 #define GPIO_CRH_MODE11_Pos                  (12U)
2010 #define GPIO_CRH_MODE11_Msk                  (0x3UL << GPIO_CRH_MODE11_Pos)     /*!< 0x00003000 */
2011 #define GPIO_CRH_MODE11                      GPIO_CRH_MODE11_Msk               /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
2012 #define GPIO_CRH_MODE11_0                    (0x1UL << GPIO_CRH_MODE11_Pos)     /*!< 0x00001000 */
2013 #define GPIO_CRH_MODE11_1                    (0x2UL << GPIO_CRH_MODE11_Pos)     /*!< 0x00002000 */
2014 
2015 #define GPIO_CRH_MODE12_Pos                  (16U)
2016 #define GPIO_CRH_MODE12_Msk                  (0x3UL << GPIO_CRH_MODE12_Pos)     /*!< 0x00030000 */
2017 #define GPIO_CRH_MODE12                      GPIO_CRH_MODE12_Msk               /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
2018 #define GPIO_CRH_MODE12_0                    (0x1UL << GPIO_CRH_MODE12_Pos)     /*!< 0x00010000 */
2019 #define GPIO_CRH_MODE12_1                    (0x2UL << GPIO_CRH_MODE12_Pos)     /*!< 0x00020000 */
2020 
2021 #define GPIO_CRH_MODE13_Pos                  (20U)
2022 #define GPIO_CRH_MODE13_Msk                  (0x3UL << GPIO_CRH_MODE13_Pos)     /*!< 0x00300000 */
2023 #define GPIO_CRH_MODE13                      GPIO_CRH_MODE13_Msk               /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
2024 #define GPIO_CRH_MODE13_0                    (0x1UL << GPIO_CRH_MODE13_Pos)     /*!< 0x00100000 */
2025 #define GPIO_CRH_MODE13_1                    (0x2UL << GPIO_CRH_MODE13_Pos)     /*!< 0x00200000 */
2026 
2027 #define GPIO_CRH_MODE14_Pos                  (24U)
2028 #define GPIO_CRH_MODE14_Msk                  (0x3UL << GPIO_CRH_MODE14_Pos)     /*!< 0x03000000 */
2029 #define GPIO_CRH_MODE14                      GPIO_CRH_MODE14_Msk               /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
2030 #define GPIO_CRH_MODE14_0                    (0x1UL << GPIO_CRH_MODE14_Pos)     /*!< 0x01000000 */
2031 #define GPIO_CRH_MODE14_1                    (0x2UL << GPIO_CRH_MODE14_Pos)     /*!< 0x02000000 */
2032 
2033 #define GPIO_CRH_MODE15_Pos                  (28U)
2034 #define GPIO_CRH_MODE15_Msk                  (0x3UL << GPIO_CRH_MODE15_Pos)     /*!< 0x30000000 */
2035 #define GPIO_CRH_MODE15                      GPIO_CRH_MODE15_Msk               /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
2036 #define GPIO_CRH_MODE15_0                    (0x1UL << GPIO_CRH_MODE15_Pos)     /*!< 0x10000000 */
2037 #define GPIO_CRH_MODE15_1                    (0x2UL << GPIO_CRH_MODE15_Pos)     /*!< 0x20000000 */
2038 
2039 #define GPIO_CRH_CNF_Pos                     (2U)
2040 #define GPIO_CRH_CNF_Msk                     (0x33333333UL << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */
2041 #define GPIO_CRH_CNF                         GPIO_CRH_CNF_Msk                  /*!< Port x configuration bits */
2042 
2043 #define GPIO_CRH_CNF8_Pos                    (2U)
2044 #define GPIO_CRH_CNF8_Msk                    (0x3UL << GPIO_CRH_CNF8_Pos)       /*!< 0x0000000C */
2045 #define GPIO_CRH_CNF8                        GPIO_CRH_CNF8_Msk                 /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
2046 #define GPIO_CRH_CNF8_0                      (0x1UL << GPIO_CRH_CNF8_Pos)       /*!< 0x00000004 */
2047 #define GPIO_CRH_CNF8_1                      (0x2UL << GPIO_CRH_CNF8_Pos)       /*!< 0x00000008 */
2048 
2049 #define GPIO_CRH_CNF9_Pos                    (6U)
2050 #define GPIO_CRH_CNF9_Msk                    (0x3UL << GPIO_CRH_CNF9_Pos)       /*!< 0x000000C0 */
2051 #define GPIO_CRH_CNF9                        GPIO_CRH_CNF9_Msk                 /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
2052 #define GPIO_CRH_CNF9_0                      (0x1UL << GPIO_CRH_CNF9_Pos)       /*!< 0x00000040 */
2053 #define GPIO_CRH_CNF9_1                      (0x2UL << GPIO_CRH_CNF9_Pos)       /*!< 0x00000080 */
2054 
2055 #define GPIO_CRH_CNF10_Pos                   (10U)
2056 #define GPIO_CRH_CNF10_Msk                   (0x3UL << GPIO_CRH_CNF10_Pos)      /*!< 0x00000C00 */
2057 #define GPIO_CRH_CNF10                       GPIO_CRH_CNF10_Msk                /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
2058 #define GPIO_CRH_CNF10_0                     (0x1UL << GPIO_CRH_CNF10_Pos)      /*!< 0x00000400 */
2059 #define GPIO_CRH_CNF10_1                     (0x2UL << GPIO_CRH_CNF10_Pos)      /*!< 0x00000800 */
2060 
2061 #define GPIO_CRH_CNF11_Pos                   (14U)
2062 #define GPIO_CRH_CNF11_Msk                   (0x3UL << GPIO_CRH_CNF11_Pos)      /*!< 0x0000C000 */
2063 #define GPIO_CRH_CNF11                       GPIO_CRH_CNF11_Msk                /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
2064 #define GPIO_CRH_CNF11_0                     (0x1UL << GPIO_CRH_CNF11_Pos)      /*!< 0x00004000 */
2065 #define GPIO_CRH_CNF11_1                     (0x2UL << GPIO_CRH_CNF11_Pos)      /*!< 0x00008000 */
2066 
2067 #define GPIO_CRH_CNF12_Pos                   (18U)
2068 #define GPIO_CRH_CNF12_Msk                   (0x3UL << GPIO_CRH_CNF12_Pos)      /*!< 0x000C0000 */
2069 #define GPIO_CRH_CNF12                       GPIO_CRH_CNF12_Msk                /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
2070 #define GPIO_CRH_CNF12_0                     (0x1UL << GPIO_CRH_CNF12_Pos)      /*!< 0x00040000 */
2071 #define GPIO_CRH_CNF12_1                     (0x2UL << GPIO_CRH_CNF12_Pos)      /*!< 0x00080000 */
2072 
2073 #define GPIO_CRH_CNF13_Pos                   (22U)
2074 #define GPIO_CRH_CNF13_Msk                   (0x3UL << GPIO_CRH_CNF13_Pos)      /*!< 0x00C00000 */
2075 #define GPIO_CRH_CNF13                       GPIO_CRH_CNF13_Msk                /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
2076 #define GPIO_CRH_CNF13_0                     (0x1UL << GPIO_CRH_CNF13_Pos)      /*!< 0x00400000 */
2077 #define GPIO_CRH_CNF13_1                     (0x2UL << GPIO_CRH_CNF13_Pos)      /*!< 0x00800000 */
2078 
2079 #define GPIO_CRH_CNF14_Pos                   (26U)
2080 #define GPIO_CRH_CNF14_Msk                   (0x3UL << GPIO_CRH_CNF14_Pos)      /*!< 0x0C000000 */
2081 #define GPIO_CRH_CNF14                       GPIO_CRH_CNF14_Msk                /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
2082 #define GPIO_CRH_CNF14_0                     (0x1UL << GPIO_CRH_CNF14_Pos)      /*!< 0x04000000 */
2083 #define GPIO_CRH_CNF14_1                     (0x2UL << GPIO_CRH_CNF14_Pos)      /*!< 0x08000000 */
2084 
2085 #define GPIO_CRH_CNF15_Pos                   (30U)
2086 #define GPIO_CRH_CNF15_Msk                   (0x3UL << GPIO_CRH_CNF15_Pos)      /*!< 0xC0000000 */
2087 #define GPIO_CRH_CNF15                       GPIO_CRH_CNF15_Msk                /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
2088 #define GPIO_CRH_CNF15_0                     (0x1UL << GPIO_CRH_CNF15_Pos)      /*!< 0x40000000 */
2089 #define GPIO_CRH_CNF15_1                     (0x2UL << GPIO_CRH_CNF15_Pos)      /*!< 0x80000000 */
2090 
2091 /*!<******************  Bit definition for GPIO_IDR register  *******************/
2092 #define GPIO_IDR_IDR0_Pos                    (0U)
2093 #define GPIO_IDR_IDR0_Msk                    (0x1UL << GPIO_IDR_IDR0_Pos)       /*!< 0x00000001 */
2094 #define GPIO_IDR_IDR0                        GPIO_IDR_IDR0_Msk                 /*!< Port input data, bit 0 */
2095 #define GPIO_IDR_IDR1_Pos                    (1U)
2096 #define GPIO_IDR_IDR1_Msk                    (0x1UL << GPIO_IDR_IDR1_Pos)       /*!< 0x00000002 */
2097 #define GPIO_IDR_IDR1                        GPIO_IDR_IDR1_Msk                 /*!< Port input data, bit 1 */
2098 #define GPIO_IDR_IDR2_Pos                    (2U)
2099 #define GPIO_IDR_IDR2_Msk                    (0x1UL << GPIO_IDR_IDR2_Pos)       /*!< 0x00000004 */
2100 #define GPIO_IDR_IDR2                        GPIO_IDR_IDR2_Msk                 /*!< Port input data, bit 2 */
2101 #define GPIO_IDR_IDR3_Pos                    (3U)
2102 #define GPIO_IDR_IDR3_Msk                    (0x1UL << GPIO_IDR_IDR3_Pos)       /*!< 0x00000008 */
2103 #define GPIO_IDR_IDR3                        GPIO_IDR_IDR3_Msk                 /*!< Port input data, bit 3 */
2104 #define GPIO_IDR_IDR4_Pos                    (4U)
2105 #define GPIO_IDR_IDR4_Msk                    (0x1UL << GPIO_IDR_IDR4_Pos)       /*!< 0x00000010 */
2106 #define GPIO_IDR_IDR4                        GPIO_IDR_IDR4_Msk                 /*!< Port input data, bit 4 */
2107 #define GPIO_IDR_IDR5_Pos                    (5U)
2108 #define GPIO_IDR_IDR5_Msk                    (0x1UL << GPIO_IDR_IDR5_Pos)       /*!< 0x00000020 */
2109 #define GPIO_IDR_IDR5                        GPIO_IDR_IDR5_Msk                 /*!< Port input data, bit 5 */
2110 #define GPIO_IDR_IDR6_Pos                    (6U)
2111 #define GPIO_IDR_IDR6_Msk                    (0x1UL << GPIO_IDR_IDR6_Pos)       /*!< 0x00000040 */
2112 #define GPIO_IDR_IDR6                        GPIO_IDR_IDR6_Msk                 /*!< Port input data, bit 6 */
2113 #define GPIO_IDR_IDR7_Pos                    (7U)
2114 #define GPIO_IDR_IDR7_Msk                    (0x1UL << GPIO_IDR_IDR7_Pos)       /*!< 0x00000080 */
2115 #define GPIO_IDR_IDR7                        GPIO_IDR_IDR7_Msk                 /*!< Port input data, bit 7 */
2116 #define GPIO_IDR_IDR8_Pos                    (8U)
2117 #define GPIO_IDR_IDR8_Msk                    (0x1UL << GPIO_IDR_IDR8_Pos)       /*!< 0x00000100 */
2118 #define GPIO_IDR_IDR8                        GPIO_IDR_IDR8_Msk                 /*!< Port input data, bit 8 */
2119 #define GPIO_IDR_IDR9_Pos                    (9U)
2120 #define GPIO_IDR_IDR9_Msk                    (0x1UL << GPIO_IDR_IDR9_Pos)       /*!< 0x00000200 */
2121 #define GPIO_IDR_IDR9                        GPIO_IDR_IDR9_Msk                 /*!< Port input data, bit 9 */
2122 #define GPIO_IDR_IDR10_Pos                   (10U)
2123 #define GPIO_IDR_IDR10_Msk                   (0x1UL << GPIO_IDR_IDR10_Pos)      /*!< 0x00000400 */
2124 #define GPIO_IDR_IDR10                       GPIO_IDR_IDR10_Msk                /*!< Port input data, bit 10 */
2125 #define GPIO_IDR_IDR11_Pos                   (11U)
2126 #define GPIO_IDR_IDR11_Msk                   (0x1UL << GPIO_IDR_IDR11_Pos)      /*!< 0x00000800 */
2127 #define GPIO_IDR_IDR11                       GPIO_IDR_IDR11_Msk                /*!< Port input data, bit 11 */
2128 #define GPIO_IDR_IDR12_Pos                   (12U)
2129 #define GPIO_IDR_IDR12_Msk                   (0x1UL << GPIO_IDR_IDR12_Pos)      /*!< 0x00001000 */
2130 #define GPIO_IDR_IDR12                       GPIO_IDR_IDR12_Msk                /*!< Port input data, bit 12 */
2131 #define GPIO_IDR_IDR13_Pos                   (13U)
2132 #define GPIO_IDR_IDR13_Msk                   (0x1UL << GPIO_IDR_IDR13_Pos)      /*!< 0x00002000 */
2133 #define GPIO_IDR_IDR13                       GPIO_IDR_IDR13_Msk                /*!< Port input data, bit 13 */
2134 #define GPIO_IDR_IDR14_Pos                   (14U)
2135 #define GPIO_IDR_IDR14_Msk                   (0x1UL << GPIO_IDR_IDR14_Pos)      /*!< 0x00004000 */
2136 #define GPIO_IDR_IDR14                       GPIO_IDR_IDR14_Msk                /*!< Port input data, bit 14 */
2137 #define GPIO_IDR_IDR15_Pos                   (15U)
2138 #define GPIO_IDR_IDR15_Msk                   (0x1UL << GPIO_IDR_IDR15_Pos)      /*!< 0x00008000 */
2139 #define GPIO_IDR_IDR15                       GPIO_IDR_IDR15_Msk                /*!< Port input data, bit 15 */
2140 
2141 /*******************  Bit definition for GPIO_ODR register  *******************/
2142 #define GPIO_ODR_ODR0_Pos                    (0U)
2143 #define GPIO_ODR_ODR0_Msk                    (0x1UL << GPIO_ODR_ODR0_Pos)       /*!< 0x00000001 */
2144 #define GPIO_ODR_ODR0                        GPIO_ODR_ODR0_Msk                 /*!< Port output data, bit 0 */
2145 #define GPIO_ODR_ODR1_Pos                    (1U)
2146 #define GPIO_ODR_ODR1_Msk                    (0x1UL << GPIO_ODR_ODR1_Pos)       /*!< 0x00000002 */
2147 #define GPIO_ODR_ODR1                        GPIO_ODR_ODR1_Msk                 /*!< Port output data, bit 1 */
2148 #define GPIO_ODR_ODR2_Pos                    (2U)
2149 #define GPIO_ODR_ODR2_Msk                    (0x1UL << GPIO_ODR_ODR2_Pos)       /*!< 0x00000004 */
2150 #define GPIO_ODR_ODR2                        GPIO_ODR_ODR2_Msk                 /*!< Port output data, bit 2 */
2151 #define GPIO_ODR_ODR3_Pos                    (3U)
2152 #define GPIO_ODR_ODR3_Msk                    (0x1UL << GPIO_ODR_ODR3_Pos)       /*!< 0x00000008 */
2153 #define GPIO_ODR_ODR3                        GPIO_ODR_ODR3_Msk                 /*!< Port output data, bit 3 */
2154 #define GPIO_ODR_ODR4_Pos                    (4U)
2155 #define GPIO_ODR_ODR4_Msk                    (0x1UL << GPIO_ODR_ODR4_Pos)       /*!< 0x00000010 */
2156 #define GPIO_ODR_ODR4                        GPIO_ODR_ODR4_Msk                 /*!< Port output data, bit 4 */
2157 #define GPIO_ODR_ODR5_Pos                    (5U)
2158 #define GPIO_ODR_ODR5_Msk                    (0x1UL << GPIO_ODR_ODR5_Pos)       /*!< 0x00000020 */
2159 #define GPIO_ODR_ODR5                        GPIO_ODR_ODR5_Msk                 /*!< Port output data, bit 5 */
2160 #define GPIO_ODR_ODR6_Pos                    (6U)
2161 #define GPIO_ODR_ODR6_Msk                    (0x1UL << GPIO_ODR_ODR6_Pos)       /*!< 0x00000040 */
2162 #define GPIO_ODR_ODR6                        GPIO_ODR_ODR6_Msk                 /*!< Port output data, bit 6 */
2163 #define GPIO_ODR_ODR7_Pos                    (7U)
2164 #define GPIO_ODR_ODR7_Msk                    (0x1UL << GPIO_ODR_ODR7_Pos)       /*!< 0x00000080 */
2165 #define GPIO_ODR_ODR7                        GPIO_ODR_ODR7_Msk                 /*!< Port output data, bit 7 */
2166 #define GPIO_ODR_ODR8_Pos                    (8U)
2167 #define GPIO_ODR_ODR8_Msk                    (0x1UL << GPIO_ODR_ODR8_Pos)       /*!< 0x00000100 */
2168 #define GPIO_ODR_ODR8                        GPIO_ODR_ODR8_Msk                 /*!< Port output data, bit 8 */
2169 #define GPIO_ODR_ODR9_Pos                    (9U)
2170 #define GPIO_ODR_ODR9_Msk                    (0x1UL << GPIO_ODR_ODR9_Pos)       /*!< 0x00000200 */
2171 #define GPIO_ODR_ODR9                        GPIO_ODR_ODR9_Msk                 /*!< Port output data, bit 9 */
2172 #define GPIO_ODR_ODR10_Pos                   (10U)
2173 #define GPIO_ODR_ODR10_Msk                   (0x1UL << GPIO_ODR_ODR10_Pos)      /*!< 0x00000400 */
2174 #define GPIO_ODR_ODR10                       GPIO_ODR_ODR10_Msk                /*!< Port output data, bit 10 */
2175 #define GPIO_ODR_ODR11_Pos                   (11U)
2176 #define GPIO_ODR_ODR11_Msk                   (0x1UL << GPIO_ODR_ODR11_Pos)      /*!< 0x00000800 */
2177 #define GPIO_ODR_ODR11                       GPIO_ODR_ODR11_Msk                /*!< Port output data, bit 11 */
2178 #define GPIO_ODR_ODR12_Pos                   (12U)
2179 #define GPIO_ODR_ODR12_Msk                   (0x1UL << GPIO_ODR_ODR12_Pos)      /*!< 0x00001000 */
2180 #define GPIO_ODR_ODR12                       GPIO_ODR_ODR12_Msk                /*!< Port output data, bit 12 */
2181 #define GPIO_ODR_ODR13_Pos                   (13U)
2182 #define GPIO_ODR_ODR13_Msk                   (0x1UL << GPIO_ODR_ODR13_Pos)      /*!< 0x00002000 */
2183 #define GPIO_ODR_ODR13                       GPIO_ODR_ODR13_Msk                /*!< Port output data, bit 13 */
2184 #define GPIO_ODR_ODR14_Pos                   (14U)
2185 #define GPIO_ODR_ODR14_Msk                   (0x1UL << GPIO_ODR_ODR14_Pos)      /*!< 0x00004000 */
2186 #define GPIO_ODR_ODR14                       GPIO_ODR_ODR14_Msk                /*!< Port output data, bit 14 */
2187 #define GPIO_ODR_ODR15_Pos                   (15U)
2188 #define GPIO_ODR_ODR15_Msk                   (0x1UL << GPIO_ODR_ODR15_Pos)      /*!< 0x00008000 */
2189 #define GPIO_ODR_ODR15                       GPIO_ODR_ODR15_Msk                /*!< Port output data, bit 15 */
2190 
2191 /******************  Bit definition for GPIO_BSRR register  *******************/
2192 #define GPIO_BSRR_BS0_Pos                    (0U)
2193 #define GPIO_BSRR_BS0_Msk                    (0x1UL << GPIO_BSRR_BS0_Pos)       /*!< 0x00000001 */
2194 #define GPIO_BSRR_BS0                        GPIO_BSRR_BS0_Msk                 /*!< Port x Set bit 0 */
2195 #define GPIO_BSRR_BS1_Pos                    (1U)
2196 #define GPIO_BSRR_BS1_Msk                    (0x1UL << GPIO_BSRR_BS1_Pos)       /*!< 0x00000002 */
2197 #define GPIO_BSRR_BS1                        GPIO_BSRR_BS1_Msk                 /*!< Port x Set bit 1 */
2198 #define GPIO_BSRR_BS2_Pos                    (2U)
2199 #define GPIO_BSRR_BS2_Msk                    (0x1UL << GPIO_BSRR_BS2_Pos)       /*!< 0x00000004 */
2200 #define GPIO_BSRR_BS2                        GPIO_BSRR_BS2_Msk                 /*!< Port x Set bit 2 */
2201 #define GPIO_BSRR_BS3_Pos                    (3U)
2202 #define GPIO_BSRR_BS3_Msk                    (0x1UL << GPIO_BSRR_BS3_Pos)       /*!< 0x00000008 */
2203 #define GPIO_BSRR_BS3                        GPIO_BSRR_BS3_Msk                 /*!< Port x Set bit 3 */
2204 #define GPIO_BSRR_BS4_Pos                    (4U)
2205 #define GPIO_BSRR_BS4_Msk                    (0x1UL << GPIO_BSRR_BS4_Pos)       /*!< 0x00000010 */
2206 #define GPIO_BSRR_BS4                        GPIO_BSRR_BS4_Msk                 /*!< Port x Set bit 4 */
2207 #define GPIO_BSRR_BS5_Pos                    (5U)
2208 #define GPIO_BSRR_BS5_Msk                    (0x1UL << GPIO_BSRR_BS5_Pos)       /*!< 0x00000020 */
2209 #define GPIO_BSRR_BS5                        GPIO_BSRR_BS5_Msk                 /*!< Port x Set bit 5 */
2210 #define GPIO_BSRR_BS6_Pos                    (6U)
2211 #define GPIO_BSRR_BS6_Msk                    (0x1UL << GPIO_BSRR_BS6_Pos)       /*!< 0x00000040 */
2212 #define GPIO_BSRR_BS6                        GPIO_BSRR_BS6_Msk                 /*!< Port x Set bit 6 */
2213 #define GPIO_BSRR_BS7_Pos                    (7U)
2214 #define GPIO_BSRR_BS7_Msk                    (0x1UL << GPIO_BSRR_BS7_Pos)       /*!< 0x00000080 */
2215 #define GPIO_BSRR_BS7                        GPIO_BSRR_BS7_Msk                 /*!< Port x Set bit 7 */
2216 #define GPIO_BSRR_BS8_Pos                    (8U)
2217 #define GPIO_BSRR_BS8_Msk                    (0x1UL << GPIO_BSRR_BS8_Pos)       /*!< 0x00000100 */
2218 #define GPIO_BSRR_BS8                        GPIO_BSRR_BS8_Msk                 /*!< Port x Set bit 8 */
2219 #define GPIO_BSRR_BS9_Pos                    (9U)
2220 #define GPIO_BSRR_BS9_Msk                    (0x1UL << GPIO_BSRR_BS9_Pos)       /*!< 0x00000200 */
2221 #define GPIO_BSRR_BS9                        GPIO_BSRR_BS9_Msk                 /*!< Port x Set bit 9 */
2222 #define GPIO_BSRR_BS10_Pos                   (10U)
2223 #define GPIO_BSRR_BS10_Msk                   (0x1UL << GPIO_BSRR_BS10_Pos)      /*!< 0x00000400 */
2224 #define GPIO_BSRR_BS10                       GPIO_BSRR_BS10_Msk                /*!< Port x Set bit 10 */
2225 #define GPIO_BSRR_BS11_Pos                   (11U)
2226 #define GPIO_BSRR_BS11_Msk                   (0x1UL << GPIO_BSRR_BS11_Pos)      /*!< 0x00000800 */
2227 #define GPIO_BSRR_BS11                       GPIO_BSRR_BS11_Msk                /*!< Port x Set bit 11 */
2228 #define GPIO_BSRR_BS12_Pos                   (12U)
2229 #define GPIO_BSRR_BS12_Msk                   (0x1UL << GPIO_BSRR_BS12_Pos)      /*!< 0x00001000 */
2230 #define GPIO_BSRR_BS12                       GPIO_BSRR_BS12_Msk                /*!< Port x Set bit 12 */
2231 #define GPIO_BSRR_BS13_Pos                   (13U)
2232 #define GPIO_BSRR_BS13_Msk                   (0x1UL << GPIO_BSRR_BS13_Pos)      /*!< 0x00002000 */
2233 #define GPIO_BSRR_BS13                       GPIO_BSRR_BS13_Msk                /*!< Port x Set bit 13 */
2234 #define GPIO_BSRR_BS14_Pos                   (14U)
2235 #define GPIO_BSRR_BS14_Msk                   (0x1UL << GPIO_BSRR_BS14_Pos)      /*!< 0x00004000 */
2236 #define GPIO_BSRR_BS14                       GPIO_BSRR_BS14_Msk                /*!< Port x Set bit 14 */
2237 #define GPIO_BSRR_BS15_Pos                   (15U)
2238 #define GPIO_BSRR_BS15_Msk                   (0x1UL << GPIO_BSRR_BS15_Pos)      /*!< 0x00008000 */
2239 #define GPIO_BSRR_BS15                       GPIO_BSRR_BS15_Msk                /*!< Port x Set bit 15 */
2240 
2241 #define GPIO_BSRR_BR0_Pos                    (16U)
2242 #define GPIO_BSRR_BR0_Msk                    (0x1UL << GPIO_BSRR_BR0_Pos)       /*!< 0x00010000 */
2243 #define GPIO_BSRR_BR0                        GPIO_BSRR_BR0_Msk                 /*!< Port x Reset bit 0 */
2244 #define GPIO_BSRR_BR1_Pos                    (17U)
2245 #define GPIO_BSRR_BR1_Msk                    (0x1UL << GPIO_BSRR_BR1_Pos)       /*!< 0x00020000 */
2246 #define GPIO_BSRR_BR1                        GPIO_BSRR_BR1_Msk                 /*!< Port x Reset bit 1 */
2247 #define GPIO_BSRR_BR2_Pos                    (18U)
2248 #define GPIO_BSRR_BR2_Msk                    (0x1UL << GPIO_BSRR_BR2_Pos)       /*!< 0x00040000 */
2249 #define GPIO_BSRR_BR2                        GPIO_BSRR_BR2_Msk                 /*!< Port x Reset bit 2 */
2250 #define GPIO_BSRR_BR3_Pos                    (19U)
2251 #define GPIO_BSRR_BR3_Msk                    (0x1UL << GPIO_BSRR_BR3_Pos)       /*!< 0x00080000 */
2252 #define GPIO_BSRR_BR3                        GPIO_BSRR_BR3_Msk                 /*!< Port x Reset bit 3 */
2253 #define GPIO_BSRR_BR4_Pos                    (20U)
2254 #define GPIO_BSRR_BR4_Msk                    (0x1UL << GPIO_BSRR_BR4_Pos)       /*!< 0x00100000 */
2255 #define GPIO_BSRR_BR4                        GPIO_BSRR_BR4_Msk                 /*!< Port x Reset bit 4 */
2256 #define GPIO_BSRR_BR5_Pos                    (21U)
2257 #define GPIO_BSRR_BR5_Msk                    (0x1UL << GPIO_BSRR_BR5_Pos)       /*!< 0x00200000 */
2258 #define GPIO_BSRR_BR5                        GPIO_BSRR_BR5_Msk                 /*!< Port x Reset bit 5 */
2259 #define GPIO_BSRR_BR6_Pos                    (22U)
2260 #define GPIO_BSRR_BR6_Msk                    (0x1UL << GPIO_BSRR_BR6_Pos)       /*!< 0x00400000 */
2261 #define GPIO_BSRR_BR6                        GPIO_BSRR_BR6_Msk                 /*!< Port x Reset bit 6 */
2262 #define GPIO_BSRR_BR7_Pos                    (23U)
2263 #define GPIO_BSRR_BR7_Msk                    (0x1UL << GPIO_BSRR_BR7_Pos)       /*!< 0x00800000 */
2264 #define GPIO_BSRR_BR7                        GPIO_BSRR_BR7_Msk                 /*!< Port x Reset bit 7 */
2265 #define GPIO_BSRR_BR8_Pos                    (24U)
2266 #define GPIO_BSRR_BR8_Msk                    (0x1UL << GPIO_BSRR_BR8_Pos)       /*!< 0x01000000 */
2267 #define GPIO_BSRR_BR8                        GPIO_BSRR_BR8_Msk                 /*!< Port x Reset bit 8 */
2268 #define GPIO_BSRR_BR9_Pos                    (25U)
2269 #define GPIO_BSRR_BR9_Msk                    (0x1UL << GPIO_BSRR_BR9_Pos)       /*!< 0x02000000 */
2270 #define GPIO_BSRR_BR9                        GPIO_BSRR_BR9_Msk                 /*!< Port x Reset bit 9 */
2271 #define GPIO_BSRR_BR10_Pos                   (26U)
2272 #define GPIO_BSRR_BR10_Msk                   (0x1UL << GPIO_BSRR_BR10_Pos)      /*!< 0x04000000 */
2273 #define GPIO_BSRR_BR10                       GPIO_BSRR_BR10_Msk                /*!< Port x Reset bit 10 */
2274 #define GPIO_BSRR_BR11_Pos                   (27U)
2275 #define GPIO_BSRR_BR11_Msk                   (0x1UL << GPIO_BSRR_BR11_Pos)      /*!< 0x08000000 */
2276 #define GPIO_BSRR_BR11                       GPIO_BSRR_BR11_Msk                /*!< Port x Reset bit 11 */
2277 #define GPIO_BSRR_BR12_Pos                   (28U)
2278 #define GPIO_BSRR_BR12_Msk                   (0x1UL << GPIO_BSRR_BR12_Pos)      /*!< 0x10000000 */
2279 #define GPIO_BSRR_BR12                       GPIO_BSRR_BR12_Msk                /*!< Port x Reset bit 12 */
2280 #define GPIO_BSRR_BR13_Pos                   (29U)
2281 #define GPIO_BSRR_BR13_Msk                   (0x1UL << GPIO_BSRR_BR13_Pos)      /*!< 0x20000000 */
2282 #define GPIO_BSRR_BR13                       GPIO_BSRR_BR13_Msk                /*!< Port x Reset bit 13 */
2283 #define GPIO_BSRR_BR14_Pos                   (30U)
2284 #define GPIO_BSRR_BR14_Msk                   (0x1UL << GPIO_BSRR_BR14_Pos)      /*!< 0x40000000 */
2285 #define GPIO_BSRR_BR14                       GPIO_BSRR_BR14_Msk                /*!< Port x Reset bit 14 */
2286 #define GPIO_BSRR_BR15_Pos                   (31U)
2287 #define GPIO_BSRR_BR15_Msk                   (0x1UL << GPIO_BSRR_BR15_Pos)      /*!< 0x80000000 */
2288 #define GPIO_BSRR_BR15                       GPIO_BSRR_BR15_Msk                /*!< Port x Reset bit 15 */
2289 
2290 /*******************  Bit definition for GPIO_BRR register  *******************/
2291 #define GPIO_BRR_BR0_Pos                     (0U)
2292 #define GPIO_BRR_BR0_Msk                     (0x1UL << GPIO_BRR_BR0_Pos)        /*!< 0x00000001 */
2293 #define GPIO_BRR_BR0                         GPIO_BRR_BR0_Msk                  /*!< Port x Reset bit 0 */
2294 #define GPIO_BRR_BR1_Pos                     (1U)
2295 #define GPIO_BRR_BR1_Msk                     (0x1UL << GPIO_BRR_BR1_Pos)        /*!< 0x00000002 */
2296 #define GPIO_BRR_BR1                         GPIO_BRR_BR1_Msk                  /*!< Port x Reset bit 1 */
2297 #define GPIO_BRR_BR2_Pos                     (2U)
2298 #define GPIO_BRR_BR2_Msk                     (0x1UL << GPIO_BRR_BR2_Pos)        /*!< 0x00000004 */
2299 #define GPIO_BRR_BR2                         GPIO_BRR_BR2_Msk                  /*!< Port x Reset bit 2 */
2300 #define GPIO_BRR_BR3_Pos                     (3U)
2301 #define GPIO_BRR_BR3_Msk                     (0x1UL << GPIO_BRR_BR3_Pos)        /*!< 0x00000008 */
2302 #define GPIO_BRR_BR3                         GPIO_BRR_BR3_Msk                  /*!< Port x Reset bit 3 */
2303 #define GPIO_BRR_BR4_Pos                     (4U)
2304 #define GPIO_BRR_BR4_Msk                     (0x1UL << GPIO_BRR_BR4_Pos)        /*!< 0x00000010 */
2305 #define GPIO_BRR_BR4                         GPIO_BRR_BR4_Msk                  /*!< Port x Reset bit 4 */
2306 #define GPIO_BRR_BR5_Pos                     (5U)
2307 #define GPIO_BRR_BR5_Msk                     (0x1UL << GPIO_BRR_BR5_Pos)        /*!< 0x00000020 */
2308 #define GPIO_BRR_BR5                         GPIO_BRR_BR5_Msk                  /*!< Port x Reset bit 5 */
2309 #define GPIO_BRR_BR6_Pos                     (6U)
2310 #define GPIO_BRR_BR6_Msk                     (0x1UL << GPIO_BRR_BR6_Pos)        /*!< 0x00000040 */
2311 #define GPIO_BRR_BR6                         GPIO_BRR_BR6_Msk                  /*!< Port x Reset bit 6 */
2312 #define GPIO_BRR_BR7_Pos                     (7U)
2313 #define GPIO_BRR_BR7_Msk                     (0x1UL << GPIO_BRR_BR7_Pos)        /*!< 0x00000080 */
2314 #define GPIO_BRR_BR7                         GPIO_BRR_BR7_Msk                  /*!< Port x Reset bit 7 */
2315 #define GPIO_BRR_BR8_Pos                     (8U)
2316 #define GPIO_BRR_BR8_Msk                     (0x1UL << GPIO_BRR_BR8_Pos)        /*!< 0x00000100 */
2317 #define GPIO_BRR_BR8                         GPIO_BRR_BR8_Msk                  /*!< Port x Reset bit 8 */
2318 #define GPIO_BRR_BR9_Pos                     (9U)
2319 #define GPIO_BRR_BR9_Msk                     (0x1UL << GPIO_BRR_BR9_Pos)        /*!< 0x00000200 */
2320 #define GPIO_BRR_BR9                         GPIO_BRR_BR9_Msk                  /*!< Port x Reset bit 9 */
2321 #define GPIO_BRR_BR10_Pos                    (10U)
2322 #define GPIO_BRR_BR10_Msk                    (0x1UL << GPIO_BRR_BR10_Pos)       /*!< 0x00000400 */
2323 #define GPIO_BRR_BR10                        GPIO_BRR_BR10_Msk                 /*!< Port x Reset bit 10 */
2324 #define GPIO_BRR_BR11_Pos                    (11U)
2325 #define GPIO_BRR_BR11_Msk                    (0x1UL << GPIO_BRR_BR11_Pos)       /*!< 0x00000800 */
2326 #define GPIO_BRR_BR11                        GPIO_BRR_BR11_Msk                 /*!< Port x Reset bit 11 */
2327 #define GPIO_BRR_BR12_Pos                    (12U)
2328 #define GPIO_BRR_BR12_Msk                    (0x1UL << GPIO_BRR_BR12_Pos)       /*!< 0x00001000 */
2329 #define GPIO_BRR_BR12                        GPIO_BRR_BR12_Msk                 /*!< Port x Reset bit 12 */
2330 #define GPIO_BRR_BR13_Pos                    (13U)
2331 #define GPIO_BRR_BR13_Msk                    (0x1UL << GPIO_BRR_BR13_Pos)       /*!< 0x00002000 */
2332 #define GPIO_BRR_BR13                        GPIO_BRR_BR13_Msk                 /*!< Port x Reset bit 13 */
2333 #define GPIO_BRR_BR14_Pos                    (14U)
2334 #define GPIO_BRR_BR14_Msk                    (0x1UL << GPIO_BRR_BR14_Pos)       /*!< 0x00004000 */
2335 #define GPIO_BRR_BR14                        GPIO_BRR_BR14_Msk                 /*!< Port x Reset bit 14 */
2336 #define GPIO_BRR_BR15_Pos                    (15U)
2337 #define GPIO_BRR_BR15_Msk                    (0x1UL << GPIO_BRR_BR15_Pos)       /*!< 0x00008000 */
2338 #define GPIO_BRR_BR15                        GPIO_BRR_BR15_Msk                 /*!< Port x Reset bit 15 */
2339 
2340 /******************  Bit definition for GPIO_LCKR register  *******************/
2341 #define GPIO_LCKR_LCK0_Pos                   (0U)
2342 #define GPIO_LCKR_LCK0_Msk                   (0x1UL << GPIO_LCKR_LCK0_Pos)      /*!< 0x00000001 */
2343 #define GPIO_LCKR_LCK0                       GPIO_LCKR_LCK0_Msk                /*!< Port x Lock bit 0 */
2344 #define GPIO_LCKR_LCK1_Pos                   (1U)
2345 #define GPIO_LCKR_LCK1_Msk                   (0x1UL << GPIO_LCKR_LCK1_Pos)      /*!< 0x00000002 */
2346 #define GPIO_LCKR_LCK1                       GPIO_LCKR_LCK1_Msk                /*!< Port x Lock bit 1 */
2347 #define GPIO_LCKR_LCK2_Pos                   (2U)
2348 #define GPIO_LCKR_LCK2_Msk                   (0x1UL << GPIO_LCKR_LCK2_Pos)      /*!< 0x00000004 */
2349 #define GPIO_LCKR_LCK2                       GPIO_LCKR_LCK2_Msk                /*!< Port x Lock bit 2 */
2350 #define GPIO_LCKR_LCK3_Pos                   (3U)
2351 #define GPIO_LCKR_LCK3_Msk                   (0x1UL << GPIO_LCKR_LCK3_Pos)      /*!< 0x00000008 */
2352 #define GPIO_LCKR_LCK3                       GPIO_LCKR_LCK3_Msk                /*!< Port x Lock bit 3 */
2353 #define GPIO_LCKR_LCK4_Pos                   (4U)
2354 #define GPIO_LCKR_LCK4_Msk                   (0x1UL << GPIO_LCKR_LCK4_Pos)      /*!< 0x00000010 */
2355 #define GPIO_LCKR_LCK4                       GPIO_LCKR_LCK4_Msk                /*!< Port x Lock bit 4 */
2356 #define GPIO_LCKR_LCK5_Pos                   (5U)
2357 #define GPIO_LCKR_LCK5_Msk                   (0x1UL << GPIO_LCKR_LCK5_Pos)      /*!< 0x00000020 */
2358 #define GPIO_LCKR_LCK5                       GPIO_LCKR_LCK5_Msk                /*!< Port x Lock bit 5 */
2359 #define GPIO_LCKR_LCK6_Pos                   (6U)
2360 #define GPIO_LCKR_LCK6_Msk                   (0x1UL << GPIO_LCKR_LCK6_Pos)      /*!< 0x00000040 */
2361 #define GPIO_LCKR_LCK6                       GPIO_LCKR_LCK6_Msk                /*!< Port x Lock bit 6 */
2362 #define GPIO_LCKR_LCK7_Pos                   (7U)
2363 #define GPIO_LCKR_LCK7_Msk                   (0x1UL << GPIO_LCKR_LCK7_Pos)      /*!< 0x00000080 */
2364 #define GPIO_LCKR_LCK7                       GPIO_LCKR_LCK7_Msk                /*!< Port x Lock bit 7 */
2365 #define GPIO_LCKR_LCK8_Pos                   (8U)
2366 #define GPIO_LCKR_LCK8_Msk                   (0x1UL << GPIO_LCKR_LCK8_Pos)      /*!< 0x00000100 */
2367 #define GPIO_LCKR_LCK8                       GPIO_LCKR_LCK8_Msk                /*!< Port x Lock bit 8 */
2368 #define GPIO_LCKR_LCK9_Pos                   (9U)
2369 #define GPIO_LCKR_LCK9_Msk                   (0x1UL << GPIO_LCKR_LCK9_Pos)      /*!< 0x00000200 */
2370 #define GPIO_LCKR_LCK9                       GPIO_LCKR_LCK9_Msk                /*!< Port x Lock bit 9 */
2371 #define GPIO_LCKR_LCK10_Pos                  (10U)
2372 #define GPIO_LCKR_LCK10_Msk                  (0x1UL << GPIO_LCKR_LCK10_Pos)     /*!< 0x00000400 */
2373 #define GPIO_LCKR_LCK10                      GPIO_LCKR_LCK10_Msk               /*!< Port x Lock bit 10 */
2374 #define GPIO_LCKR_LCK11_Pos                  (11U)
2375 #define GPIO_LCKR_LCK11_Msk                  (0x1UL << GPIO_LCKR_LCK11_Pos)     /*!< 0x00000800 */
2376 #define GPIO_LCKR_LCK11                      GPIO_LCKR_LCK11_Msk               /*!< Port x Lock bit 11 */
2377 #define GPIO_LCKR_LCK12_Pos                  (12U)
2378 #define GPIO_LCKR_LCK12_Msk                  (0x1UL << GPIO_LCKR_LCK12_Pos)     /*!< 0x00001000 */
2379 #define GPIO_LCKR_LCK12                      GPIO_LCKR_LCK12_Msk               /*!< Port x Lock bit 12 */
2380 #define GPIO_LCKR_LCK13_Pos                  (13U)
2381 #define GPIO_LCKR_LCK13_Msk                  (0x1UL << GPIO_LCKR_LCK13_Pos)     /*!< 0x00002000 */
2382 #define GPIO_LCKR_LCK13                      GPIO_LCKR_LCK13_Msk               /*!< Port x Lock bit 13 */
2383 #define GPIO_LCKR_LCK14_Pos                  (14U)
2384 #define GPIO_LCKR_LCK14_Msk                  (0x1UL << GPIO_LCKR_LCK14_Pos)     /*!< 0x00004000 */
2385 #define GPIO_LCKR_LCK14                      GPIO_LCKR_LCK14_Msk               /*!< Port x Lock bit 14 */
2386 #define GPIO_LCKR_LCK15_Pos                  (15U)
2387 #define GPIO_LCKR_LCK15_Msk                  (0x1UL << GPIO_LCKR_LCK15_Pos)     /*!< 0x00008000 */
2388 #define GPIO_LCKR_LCK15                      GPIO_LCKR_LCK15_Msk               /*!< Port x Lock bit 15 */
2389 #define GPIO_LCKR_LCKK_Pos                   (16U)
2390 #define GPIO_LCKR_LCKK_Msk                   (0x1UL << GPIO_LCKR_LCKK_Pos)      /*!< 0x00010000 */
2391 #define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                /*!< Lock key */
2392 
2393 /*----------------------------------------------------------------------------*/
2394 
2395 /******************  Bit definition for AFIO_EVCR register  *******************/
2396 #define AFIO_EVCR_PIN_Pos                    (0U)
2397 #define AFIO_EVCR_PIN_Msk                    (0xFUL << AFIO_EVCR_PIN_Pos)       /*!< 0x0000000F */
2398 #define AFIO_EVCR_PIN                        AFIO_EVCR_PIN_Msk                 /*!< PIN[3:0] bits (Pin selection) */
2399 #define AFIO_EVCR_PIN_0                      (0x1UL << AFIO_EVCR_PIN_Pos)       /*!< 0x00000001 */
2400 #define AFIO_EVCR_PIN_1                      (0x2UL << AFIO_EVCR_PIN_Pos)       /*!< 0x00000002 */
2401 #define AFIO_EVCR_PIN_2                      (0x4UL << AFIO_EVCR_PIN_Pos)       /*!< 0x00000004 */
2402 #define AFIO_EVCR_PIN_3                      (0x8UL << AFIO_EVCR_PIN_Pos)       /*!< 0x00000008 */
2403 
2404 /*!< PIN configuration */
2405 #define AFIO_EVCR_PIN_PX0                    0x00000000U                       /*!< Pin 0 selected */
2406 #define AFIO_EVCR_PIN_PX1_Pos                (0U)
2407 #define AFIO_EVCR_PIN_PX1_Msk                (0x1UL << AFIO_EVCR_PIN_PX1_Pos)   /*!< 0x00000001 */
2408 #define AFIO_EVCR_PIN_PX1                    AFIO_EVCR_PIN_PX1_Msk             /*!< Pin 1 selected */
2409 #define AFIO_EVCR_PIN_PX2_Pos                (1U)
2410 #define AFIO_EVCR_PIN_PX2_Msk                (0x1UL << AFIO_EVCR_PIN_PX2_Pos)   /*!< 0x00000002 */
2411 #define AFIO_EVCR_PIN_PX2                    AFIO_EVCR_PIN_PX2_Msk             /*!< Pin 2 selected */
2412 #define AFIO_EVCR_PIN_PX3_Pos                (0U)
2413 #define AFIO_EVCR_PIN_PX3_Msk                (0x3UL << AFIO_EVCR_PIN_PX3_Pos)   /*!< 0x00000003 */
2414 #define AFIO_EVCR_PIN_PX3                    AFIO_EVCR_PIN_PX3_Msk             /*!< Pin 3 selected */
2415 #define AFIO_EVCR_PIN_PX4_Pos                (2U)
2416 #define AFIO_EVCR_PIN_PX4_Msk                (0x1UL << AFIO_EVCR_PIN_PX4_Pos)   /*!< 0x00000004 */
2417 #define AFIO_EVCR_PIN_PX4                    AFIO_EVCR_PIN_PX4_Msk             /*!< Pin 4 selected */
2418 #define AFIO_EVCR_PIN_PX5_Pos                (0U)
2419 #define AFIO_EVCR_PIN_PX5_Msk                (0x5UL << AFIO_EVCR_PIN_PX5_Pos)   /*!< 0x00000005 */
2420 #define AFIO_EVCR_PIN_PX5                    AFIO_EVCR_PIN_PX5_Msk             /*!< Pin 5 selected */
2421 #define AFIO_EVCR_PIN_PX6_Pos                (1U)
2422 #define AFIO_EVCR_PIN_PX6_Msk                (0x3UL << AFIO_EVCR_PIN_PX6_Pos)   /*!< 0x00000006 */
2423 #define AFIO_EVCR_PIN_PX6                    AFIO_EVCR_PIN_PX6_Msk             /*!< Pin 6 selected */
2424 #define AFIO_EVCR_PIN_PX7_Pos                (0U)
2425 #define AFIO_EVCR_PIN_PX7_Msk                (0x7UL << AFIO_EVCR_PIN_PX7_Pos)   /*!< 0x00000007 */
2426 #define AFIO_EVCR_PIN_PX7                    AFIO_EVCR_PIN_PX7_Msk             /*!< Pin 7 selected */
2427 #define AFIO_EVCR_PIN_PX8_Pos                (3U)
2428 #define AFIO_EVCR_PIN_PX8_Msk                (0x1UL << AFIO_EVCR_PIN_PX8_Pos)   /*!< 0x00000008 */
2429 #define AFIO_EVCR_PIN_PX8                    AFIO_EVCR_PIN_PX8_Msk             /*!< Pin 8 selected */
2430 #define AFIO_EVCR_PIN_PX9_Pos                (0U)
2431 #define AFIO_EVCR_PIN_PX9_Msk                (0x9UL << AFIO_EVCR_PIN_PX9_Pos)   /*!< 0x00000009 */
2432 #define AFIO_EVCR_PIN_PX9                    AFIO_EVCR_PIN_PX9_Msk             /*!< Pin 9 selected */
2433 #define AFIO_EVCR_PIN_PX10_Pos               (1U)
2434 #define AFIO_EVCR_PIN_PX10_Msk               (0x5UL << AFIO_EVCR_PIN_PX10_Pos)  /*!< 0x0000000A */
2435 #define AFIO_EVCR_PIN_PX10                   AFIO_EVCR_PIN_PX10_Msk            /*!< Pin 10 selected */
2436 #define AFIO_EVCR_PIN_PX11_Pos               (0U)
2437 #define AFIO_EVCR_PIN_PX11_Msk               (0xBUL << AFIO_EVCR_PIN_PX11_Pos)  /*!< 0x0000000B */
2438 #define AFIO_EVCR_PIN_PX11                   AFIO_EVCR_PIN_PX11_Msk            /*!< Pin 11 selected */
2439 #define AFIO_EVCR_PIN_PX12_Pos               (2U)
2440 #define AFIO_EVCR_PIN_PX12_Msk               (0x3UL << AFIO_EVCR_PIN_PX12_Pos)  /*!< 0x0000000C */
2441 #define AFIO_EVCR_PIN_PX12                   AFIO_EVCR_PIN_PX12_Msk            /*!< Pin 12 selected */
2442 #define AFIO_EVCR_PIN_PX13_Pos               (0U)
2443 #define AFIO_EVCR_PIN_PX13_Msk               (0xDUL << AFIO_EVCR_PIN_PX13_Pos)  /*!< 0x0000000D */
2444 #define AFIO_EVCR_PIN_PX13                   AFIO_EVCR_PIN_PX13_Msk            /*!< Pin 13 selected */
2445 #define AFIO_EVCR_PIN_PX14_Pos               (1U)
2446 #define AFIO_EVCR_PIN_PX14_Msk               (0x7UL << AFIO_EVCR_PIN_PX14_Pos)  /*!< 0x0000000E */
2447 #define AFIO_EVCR_PIN_PX14                   AFIO_EVCR_PIN_PX14_Msk            /*!< Pin 14 selected */
2448 #define AFIO_EVCR_PIN_PX15_Pos               (0U)
2449 #define AFIO_EVCR_PIN_PX15_Msk               (0xFUL << AFIO_EVCR_PIN_PX15_Pos)  /*!< 0x0000000F */
2450 #define AFIO_EVCR_PIN_PX15                   AFIO_EVCR_PIN_PX15_Msk            /*!< Pin 15 selected */
2451 
2452 #define AFIO_EVCR_PORT_Pos                   (4U)
2453 #define AFIO_EVCR_PORT_Msk                   (0x7UL << AFIO_EVCR_PORT_Pos)      /*!< 0x00000070 */
2454 #define AFIO_EVCR_PORT                       AFIO_EVCR_PORT_Msk                /*!< PORT[2:0] bits (Port selection) */
2455 #define AFIO_EVCR_PORT_0                     (0x1UL << AFIO_EVCR_PORT_Pos)      /*!< 0x00000010 */
2456 #define AFIO_EVCR_PORT_1                     (0x2UL << AFIO_EVCR_PORT_Pos)      /*!< 0x00000020 */
2457 #define AFIO_EVCR_PORT_2                     (0x4UL << AFIO_EVCR_PORT_Pos)      /*!< 0x00000040 */
2458 
2459 /*!< PORT configuration */
2460 #define AFIO_EVCR_PORT_PA                    0x00000000                        /*!< Port A selected */
2461 #define AFIO_EVCR_PORT_PB_Pos                (4U)
2462 #define AFIO_EVCR_PORT_PB_Msk                (0x1UL << AFIO_EVCR_PORT_PB_Pos)   /*!< 0x00000010 */
2463 #define AFIO_EVCR_PORT_PB                    AFIO_EVCR_PORT_PB_Msk             /*!< Port B selected */
2464 #define AFIO_EVCR_PORT_PC_Pos                (5U)
2465 #define AFIO_EVCR_PORT_PC_Msk                (0x1UL << AFIO_EVCR_PORT_PC_Pos)   /*!< 0x00000020 */
2466 #define AFIO_EVCR_PORT_PC                    AFIO_EVCR_PORT_PC_Msk             /*!< Port C selected */
2467 #define AFIO_EVCR_PORT_PD_Pos                (4U)
2468 #define AFIO_EVCR_PORT_PD_Msk                (0x3UL << AFIO_EVCR_PORT_PD_Pos)   /*!< 0x00000030 */
2469 #define AFIO_EVCR_PORT_PD                    AFIO_EVCR_PORT_PD_Msk             /*!< Port D selected */
2470 #define AFIO_EVCR_PORT_PE_Pos                (6U)
2471 #define AFIO_EVCR_PORT_PE_Msk                (0x1UL << AFIO_EVCR_PORT_PE_Pos)   /*!< 0x00000040 */
2472 #define AFIO_EVCR_PORT_PE                    AFIO_EVCR_PORT_PE_Msk             /*!< Port E selected */
2473 
2474 #define AFIO_EVCR_EVOE_Pos                   (7U)
2475 #define AFIO_EVCR_EVOE_Msk                   (0x1UL << AFIO_EVCR_EVOE_Pos)      /*!< 0x00000080 */
2476 #define AFIO_EVCR_EVOE                       AFIO_EVCR_EVOE_Msk                /*!< Event Output Enable */
2477 
2478 /******************  Bit definition for AFIO_MAPR register  *******************/
2479 #define AFIO_MAPR_SPI1_REMAP_Pos             (0U)
2480 #define AFIO_MAPR_SPI1_REMAP_Msk             (0x1UL << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */
2481 #define AFIO_MAPR_SPI1_REMAP                 AFIO_MAPR_SPI1_REMAP_Msk          /*!< SPI1 remapping */
2482 #define AFIO_MAPR_I2C1_REMAP_Pos             (1U)
2483 #define AFIO_MAPR_I2C1_REMAP_Msk             (0x1UL << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */
2484 #define AFIO_MAPR_I2C1_REMAP                 AFIO_MAPR_I2C1_REMAP_Msk          /*!< I2C1 remapping */
2485 #define AFIO_MAPR_USART1_REMAP_Pos           (2U)
2486 #define AFIO_MAPR_USART1_REMAP_Msk           (0x1UL << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */
2487 #define AFIO_MAPR_USART1_REMAP               AFIO_MAPR_USART1_REMAP_Msk        /*!< USART1 remapping */
2488 #define AFIO_MAPR_USART2_REMAP_Pos           (3U)
2489 #define AFIO_MAPR_USART2_REMAP_Msk           (0x1UL << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */
2490 #define AFIO_MAPR_USART2_REMAP               AFIO_MAPR_USART2_REMAP_Msk        /*!< USART2 remapping */
2491 
2492 #define AFIO_MAPR_USART3_REMAP_Pos           (4U)
2493 #define AFIO_MAPR_USART3_REMAP_Msk           (0x3UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */
2494 #define AFIO_MAPR_USART3_REMAP               AFIO_MAPR_USART3_REMAP_Msk        /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
2495 #define AFIO_MAPR_USART3_REMAP_0             (0x1UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */
2496 #define AFIO_MAPR_USART3_REMAP_1             (0x2UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
2497 
2498 /* USART3_REMAP configuration */
2499 #define AFIO_MAPR_USART3_REMAP_NOREMAP       0x00000000U                          /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
2500 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
2501 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
2502 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP  AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
2503 #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U)
2504 #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */
2505 #define AFIO_MAPR_USART3_REMAP_FULLREMAP     AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
2506 
2507 #define AFIO_MAPR_TIM1_REMAP_Pos             (6U)
2508 #define AFIO_MAPR_TIM1_REMAP_Msk             (0x3UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */
2509 #define AFIO_MAPR_TIM1_REMAP                 AFIO_MAPR_TIM1_REMAP_Msk          /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
2510 #define AFIO_MAPR_TIM1_REMAP_0               (0x1UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */
2511 #define AFIO_MAPR_TIM1_REMAP_1               (0x2UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
2512 
2513 /*!< TIM1_REMAP configuration */
2514 #define AFIO_MAPR_TIM1_REMAP_NOREMAP         0x00000000U                          /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
2515 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
2516 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
2517 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP    AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
2518 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos   (6U)
2519 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk   (0x3UL << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */
2520 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP       AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
2521 
2522 #define AFIO_MAPR_TIM2_REMAP_Pos             (8U)
2523 #define AFIO_MAPR_TIM2_REMAP_Msk             (0x3UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */
2524 #define AFIO_MAPR_TIM2_REMAP                 AFIO_MAPR_TIM2_REMAP_Msk          /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
2525 #define AFIO_MAPR_TIM2_REMAP_0               (0x1UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */
2526 #define AFIO_MAPR_TIM2_REMAP_1               (0x2UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
2527 
2528 /*!< TIM2_REMAP configuration */
2529 #define AFIO_MAPR_TIM2_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
2530 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
2531 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
2532 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
2533 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
2534 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */
2535 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2   AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
2536 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos   (8U)
2537 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk   (0x3UL << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */
2538 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP       AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
2539 
2540 #define AFIO_MAPR_TIM3_REMAP_Pos             (10U)
2541 #define AFIO_MAPR_TIM3_REMAP_Msk             (0x3UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */
2542 #define AFIO_MAPR_TIM3_REMAP                 AFIO_MAPR_TIM3_REMAP_Msk          /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
2543 #define AFIO_MAPR_TIM3_REMAP_0               (0x1UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */
2544 #define AFIO_MAPR_TIM3_REMAP_1               (0x2UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
2545 
2546 /*!< TIM3_REMAP configuration */
2547 #define AFIO_MAPR_TIM3_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
2548 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
2549 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
2550 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP    AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
2551 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos   (10U)
2552 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk   (0x3UL << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */
2553 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP       AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
2554 
2555 #define AFIO_MAPR_TIM4_REMAP_Pos             (12U)
2556 #define AFIO_MAPR_TIM4_REMAP_Msk             (0x1UL << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */
2557 #define AFIO_MAPR_TIM4_REMAP                 AFIO_MAPR_TIM4_REMAP_Msk          /*!< TIM4_REMAP bit (TIM4 remapping) */
2558 
2559 #define AFIO_MAPR_CAN_REMAP_Pos              (13U)
2560 #define AFIO_MAPR_CAN_REMAP_Msk              (0x3UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */
2561 #define AFIO_MAPR_CAN_REMAP                  AFIO_MAPR_CAN_REMAP_Msk           /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
2562 #define AFIO_MAPR_CAN_REMAP_0                (0x1UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */
2563 #define AFIO_MAPR_CAN_REMAP_1                (0x2UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */
2564 
2565 /*!< CAN_REMAP configuration */
2566 #define AFIO_MAPR_CAN_REMAP_REMAP1           0x00000000U                          /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
2567 #define AFIO_MAPR_CAN_REMAP_REMAP2_Pos       (14U)
2568 #define AFIO_MAPR_CAN_REMAP_REMAP2_Msk       (0x1UL << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */
2569 #define AFIO_MAPR_CAN_REMAP_REMAP2           AFIO_MAPR_CAN_REMAP_REMAP2_Msk    /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
2570 #define AFIO_MAPR_CAN_REMAP_REMAP3_Pos       (13U)
2571 #define AFIO_MAPR_CAN_REMAP_REMAP3_Msk       (0x3UL << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */
2572 #define AFIO_MAPR_CAN_REMAP_REMAP3           AFIO_MAPR_CAN_REMAP_REMAP3_Msk    /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
2573 
2574 #define AFIO_MAPR_PD01_REMAP_Pos             (15U)
2575 #define AFIO_MAPR_PD01_REMAP_Msk             (0x1UL << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */
2576 #define AFIO_MAPR_PD01_REMAP                 AFIO_MAPR_PD01_REMAP_Msk          /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
2577 #define AFIO_MAPR_TIM5CH4_IREMAP_Pos         (16U)
2578 #define AFIO_MAPR_TIM5CH4_IREMAP_Msk         (0x1UL << AFIO_MAPR_TIM5CH4_IREMAP_Pos) /*!< 0x00010000 */
2579 #define AFIO_MAPR_TIM5CH4_IREMAP             AFIO_MAPR_TIM5CH4_IREMAP_Msk      /*!< TIM5 Channel4 Internal Remap */
2580 #define AFIO_MAPR_ADC1_ETRGINJ_REMAP_Pos     (17U)
2581 #define AFIO_MAPR_ADC1_ETRGINJ_REMAP_Msk     (0x1UL << AFIO_MAPR_ADC1_ETRGINJ_REMAP_Pos) /*!< 0x00020000 */
2582 #define AFIO_MAPR_ADC1_ETRGINJ_REMAP         AFIO_MAPR_ADC1_ETRGINJ_REMAP_Msk  /*!< ADC 1 External Trigger Injected Conversion remapping */
2583 #define AFIO_MAPR_ADC1_ETRGREG_REMAP_Pos     (18U)
2584 #define AFIO_MAPR_ADC1_ETRGREG_REMAP_Msk     (0x1UL << AFIO_MAPR_ADC1_ETRGREG_REMAP_Pos) /*!< 0x00040000 */
2585 #define AFIO_MAPR_ADC1_ETRGREG_REMAP         AFIO_MAPR_ADC1_ETRGREG_REMAP_Msk  /*!< ADC 1 External Trigger Regular Conversion remapping */
2586 #define AFIO_MAPR_ADC2_ETRGINJ_REMAP_Pos     (19U)
2587 #define AFIO_MAPR_ADC2_ETRGINJ_REMAP_Msk     (0x1UL << AFIO_MAPR_ADC2_ETRGINJ_REMAP_Pos) /*!< 0x00080000 */
2588 #define AFIO_MAPR_ADC2_ETRGINJ_REMAP         AFIO_MAPR_ADC2_ETRGINJ_REMAP_Msk  /*!< ADC 2 External Trigger Injected Conversion remapping */
2589 #define AFIO_MAPR_ADC2_ETRGREG_REMAP_Pos     (20U)
2590 #define AFIO_MAPR_ADC2_ETRGREG_REMAP_Msk     (0x1UL << AFIO_MAPR_ADC2_ETRGREG_REMAP_Pos) /*!< 0x00100000 */
2591 #define AFIO_MAPR_ADC2_ETRGREG_REMAP         AFIO_MAPR_ADC2_ETRGREG_REMAP_Msk  /*!< ADC 2 External Trigger Regular Conversion remapping */
2592 
2593 /*!< SWJ_CFG configuration */
2594 #define AFIO_MAPR_SWJ_CFG_Pos                (24U)
2595 #define AFIO_MAPR_SWJ_CFG_Msk                (0x7UL << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x07000000 */
2596 #define AFIO_MAPR_SWJ_CFG                    AFIO_MAPR_SWJ_CFG_Msk             /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
2597 #define AFIO_MAPR_SWJ_CFG_0                  (0x1UL << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x01000000 */
2598 #define AFIO_MAPR_SWJ_CFG_1                  (0x2UL << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x02000000 */
2599 #define AFIO_MAPR_SWJ_CFG_2                  (0x4UL << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x04000000 */
2600 
2601 #define AFIO_MAPR_SWJ_CFG_RESET              0x00000000U                          /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
2602 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos       (24U)
2603 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk       (0x1UL << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
2604 #define AFIO_MAPR_SWJ_CFG_NOJNTRST           AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk    /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
2605 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos    (25U)
2606 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk    (0x1UL << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */
2607 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE        AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */
2608 #define AFIO_MAPR_SWJ_CFG_DISABLE_Pos        (26U)
2609 #define AFIO_MAPR_SWJ_CFG_DISABLE_Msk        (0x1UL << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */
2610 #define AFIO_MAPR_SWJ_CFG_DISABLE            AFIO_MAPR_SWJ_CFG_DISABLE_Msk     /*!< JTAG-DP Disabled and SW-DP Disabled */
2611 
2612 
2613 /*****************  Bit definition for AFIO_EXTICR1 register  *****************/
2614 #define AFIO_EXTICR1_EXTI0_Pos               (0U)
2615 #define AFIO_EXTICR1_EXTI0_Msk               (0xFUL << AFIO_EXTICR1_EXTI0_Pos)  /*!< 0x0000000F */
2616 #define AFIO_EXTICR1_EXTI0                   AFIO_EXTICR1_EXTI0_Msk            /*!< EXTI 0 configuration */
2617 #define AFIO_EXTICR1_EXTI1_Pos               (4U)
2618 #define AFIO_EXTICR1_EXTI1_Msk               (0xFUL << AFIO_EXTICR1_EXTI1_Pos)  /*!< 0x000000F0 */
2619 #define AFIO_EXTICR1_EXTI1                   AFIO_EXTICR1_EXTI1_Msk            /*!< EXTI 1 configuration */
2620 #define AFIO_EXTICR1_EXTI2_Pos               (8U)
2621 #define AFIO_EXTICR1_EXTI2_Msk               (0xFUL << AFIO_EXTICR1_EXTI2_Pos)  /*!< 0x00000F00 */
2622 #define AFIO_EXTICR1_EXTI2                   AFIO_EXTICR1_EXTI2_Msk            /*!< EXTI 2 configuration */
2623 #define AFIO_EXTICR1_EXTI3_Pos               (12U)
2624 #define AFIO_EXTICR1_EXTI3_Msk               (0xFUL << AFIO_EXTICR1_EXTI3_Pos)  /*!< 0x0000F000 */
2625 #define AFIO_EXTICR1_EXTI3                   AFIO_EXTICR1_EXTI3_Msk            /*!< EXTI 3 configuration */
2626 
2627 /*!< EXTI0 configuration */
2628 #define AFIO_EXTICR1_EXTI0_PA                0x00000000U                          /*!< PA[0] pin */
2629 #define AFIO_EXTICR1_EXTI0_PB_Pos            (0U)
2630 #define AFIO_EXTICR1_EXTI0_PB_Msk            (0x1UL << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
2631 #define AFIO_EXTICR1_EXTI0_PB                AFIO_EXTICR1_EXTI0_PB_Msk         /*!< PB[0] pin */
2632 #define AFIO_EXTICR1_EXTI0_PC_Pos            (1U)
2633 #define AFIO_EXTICR1_EXTI0_PC_Msk            (0x1UL << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */
2634 #define AFIO_EXTICR1_EXTI0_PC                AFIO_EXTICR1_EXTI0_PC_Msk         /*!< PC[0] pin */
2635 #define AFIO_EXTICR1_EXTI0_PD_Pos            (0U)
2636 #define AFIO_EXTICR1_EXTI0_PD_Msk            (0x3UL << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */
2637 #define AFIO_EXTICR1_EXTI0_PD                AFIO_EXTICR1_EXTI0_PD_Msk         /*!< PD[0] pin */
2638 #define AFIO_EXTICR1_EXTI0_PE_Pos            (2U)
2639 #define AFIO_EXTICR1_EXTI0_PE_Msk            (0x1UL << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */
2640 #define AFIO_EXTICR1_EXTI0_PE                AFIO_EXTICR1_EXTI0_PE_Msk         /*!< PE[0] pin */
2641 #define AFIO_EXTICR1_EXTI0_PF_Pos            (0U)
2642 #define AFIO_EXTICR1_EXTI0_PF_Msk            (0x5UL << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */
2643 #define AFIO_EXTICR1_EXTI0_PF                AFIO_EXTICR1_EXTI0_PF_Msk         /*!< PF[0] pin */
2644 #define AFIO_EXTICR1_EXTI0_PG_Pos            (1U)
2645 #define AFIO_EXTICR1_EXTI0_PG_Msk            (0x3UL << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */
2646 #define AFIO_EXTICR1_EXTI0_PG                AFIO_EXTICR1_EXTI0_PG_Msk         /*!< PG[0] pin */
2647 
2648 /*!< EXTI1 configuration */
2649 #define AFIO_EXTICR1_EXTI1_PA                0x00000000U                          /*!< PA[1] pin */
2650 #define AFIO_EXTICR1_EXTI1_PB_Pos            (4U)
2651 #define AFIO_EXTICR1_EXTI1_PB_Msk            (0x1UL << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
2652 #define AFIO_EXTICR1_EXTI1_PB                AFIO_EXTICR1_EXTI1_PB_Msk         /*!< PB[1] pin */
2653 #define AFIO_EXTICR1_EXTI1_PC_Pos            (5U)
2654 #define AFIO_EXTICR1_EXTI1_PC_Msk            (0x1UL << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */
2655 #define AFIO_EXTICR1_EXTI1_PC                AFIO_EXTICR1_EXTI1_PC_Msk         /*!< PC[1] pin */
2656 #define AFIO_EXTICR1_EXTI1_PD_Pos            (4U)
2657 #define AFIO_EXTICR1_EXTI1_PD_Msk            (0x3UL << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */
2658 #define AFIO_EXTICR1_EXTI1_PD                AFIO_EXTICR1_EXTI1_PD_Msk         /*!< PD[1] pin */
2659 #define AFIO_EXTICR1_EXTI1_PE_Pos            (6U)
2660 #define AFIO_EXTICR1_EXTI1_PE_Msk            (0x1UL << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */
2661 #define AFIO_EXTICR1_EXTI1_PE                AFIO_EXTICR1_EXTI1_PE_Msk         /*!< PE[1] pin */
2662 #define AFIO_EXTICR1_EXTI1_PF_Pos            (4U)
2663 #define AFIO_EXTICR1_EXTI1_PF_Msk            (0x5UL << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */
2664 #define AFIO_EXTICR1_EXTI1_PF                AFIO_EXTICR1_EXTI1_PF_Msk         /*!< PF[1] pin */
2665 #define AFIO_EXTICR1_EXTI1_PG_Pos            (5U)
2666 #define AFIO_EXTICR1_EXTI1_PG_Msk            (0x3UL << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */
2667 #define AFIO_EXTICR1_EXTI1_PG                AFIO_EXTICR1_EXTI1_PG_Msk         /*!< PG[1] pin */
2668 
2669 /*!< EXTI2 configuration */
2670 #define AFIO_EXTICR1_EXTI2_PA                0x00000000U                          /*!< PA[2] pin */
2671 #define AFIO_EXTICR1_EXTI2_PB_Pos            (8U)
2672 #define AFIO_EXTICR1_EXTI2_PB_Msk            (0x1UL << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
2673 #define AFIO_EXTICR1_EXTI2_PB                AFIO_EXTICR1_EXTI2_PB_Msk         /*!< PB[2] pin */
2674 #define AFIO_EXTICR1_EXTI2_PC_Pos            (9U)
2675 #define AFIO_EXTICR1_EXTI2_PC_Msk            (0x1UL << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */
2676 #define AFIO_EXTICR1_EXTI2_PC                AFIO_EXTICR1_EXTI2_PC_Msk         /*!< PC[2] pin */
2677 #define AFIO_EXTICR1_EXTI2_PD_Pos            (8U)
2678 #define AFIO_EXTICR1_EXTI2_PD_Msk            (0x3UL << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */
2679 #define AFIO_EXTICR1_EXTI2_PD                AFIO_EXTICR1_EXTI2_PD_Msk         /*!< PD[2] pin */
2680 #define AFIO_EXTICR1_EXTI2_PE_Pos            (10U)
2681 #define AFIO_EXTICR1_EXTI2_PE_Msk            (0x1UL << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */
2682 #define AFIO_EXTICR1_EXTI2_PE                AFIO_EXTICR1_EXTI2_PE_Msk         /*!< PE[2] pin */
2683 #define AFIO_EXTICR1_EXTI2_PF_Pos            (8U)
2684 #define AFIO_EXTICR1_EXTI2_PF_Msk            (0x5UL << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */
2685 #define AFIO_EXTICR1_EXTI2_PF                AFIO_EXTICR1_EXTI2_PF_Msk         /*!< PF[2] pin */
2686 #define AFIO_EXTICR1_EXTI2_PG_Pos            (9U)
2687 #define AFIO_EXTICR1_EXTI2_PG_Msk            (0x3UL << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */
2688 #define AFIO_EXTICR1_EXTI2_PG                AFIO_EXTICR1_EXTI2_PG_Msk         /*!< PG[2] pin */
2689 
2690 /*!< EXTI3 configuration */
2691 #define AFIO_EXTICR1_EXTI3_PA                0x00000000U                          /*!< PA[3] pin */
2692 #define AFIO_EXTICR1_EXTI3_PB_Pos            (12U)
2693 #define AFIO_EXTICR1_EXTI3_PB_Msk            (0x1UL << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
2694 #define AFIO_EXTICR1_EXTI3_PB                AFIO_EXTICR1_EXTI3_PB_Msk         /*!< PB[3] pin */
2695 #define AFIO_EXTICR1_EXTI3_PC_Pos            (13U)
2696 #define AFIO_EXTICR1_EXTI3_PC_Msk            (0x1UL << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */
2697 #define AFIO_EXTICR1_EXTI3_PC                AFIO_EXTICR1_EXTI3_PC_Msk         /*!< PC[3] pin */
2698 #define AFIO_EXTICR1_EXTI3_PD_Pos            (12U)
2699 #define AFIO_EXTICR1_EXTI3_PD_Msk            (0x3UL << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */
2700 #define AFIO_EXTICR1_EXTI3_PD                AFIO_EXTICR1_EXTI3_PD_Msk         /*!< PD[3] pin */
2701 #define AFIO_EXTICR1_EXTI3_PE_Pos            (14U)
2702 #define AFIO_EXTICR1_EXTI3_PE_Msk            (0x1UL << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */
2703 #define AFIO_EXTICR1_EXTI3_PE                AFIO_EXTICR1_EXTI3_PE_Msk         /*!< PE[3] pin */
2704 #define AFIO_EXTICR1_EXTI3_PF_Pos            (12U)
2705 #define AFIO_EXTICR1_EXTI3_PF_Msk            (0x5UL << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */
2706 #define AFIO_EXTICR1_EXTI3_PF                AFIO_EXTICR1_EXTI3_PF_Msk         /*!< PF[3] pin */
2707 #define AFIO_EXTICR1_EXTI3_PG_Pos            (13U)
2708 #define AFIO_EXTICR1_EXTI3_PG_Msk            (0x3UL << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */
2709 #define AFIO_EXTICR1_EXTI3_PG                AFIO_EXTICR1_EXTI3_PG_Msk         /*!< PG[3] pin */
2710 
2711 /*****************  Bit definition for AFIO_EXTICR2 register  *****************/
2712 #define AFIO_EXTICR2_EXTI4_Pos               (0U)
2713 #define AFIO_EXTICR2_EXTI4_Msk               (0xFUL << AFIO_EXTICR2_EXTI4_Pos)  /*!< 0x0000000F */
2714 #define AFIO_EXTICR2_EXTI4                   AFIO_EXTICR2_EXTI4_Msk            /*!< EXTI 4 configuration */
2715 #define AFIO_EXTICR2_EXTI5_Pos               (4U)
2716 #define AFIO_EXTICR2_EXTI5_Msk               (0xFUL << AFIO_EXTICR2_EXTI5_Pos)  /*!< 0x000000F0 */
2717 #define AFIO_EXTICR2_EXTI5                   AFIO_EXTICR2_EXTI5_Msk            /*!< EXTI 5 configuration */
2718 #define AFIO_EXTICR2_EXTI6_Pos               (8U)
2719 #define AFIO_EXTICR2_EXTI6_Msk               (0xFUL << AFIO_EXTICR2_EXTI6_Pos)  /*!< 0x00000F00 */
2720 #define AFIO_EXTICR2_EXTI6                   AFIO_EXTICR2_EXTI6_Msk            /*!< EXTI 6 configuration */
2721 #define AFIO_EXTICR2_EXTI7_Pos               (12U)
2722 #define AFIO_EXTICR2_EXTI7_Msk               (0xFUL << AFIO_EXTICR2_EXTI7_Pos)  /*!< 0x0000F000 */
2723 #define AFIO_EXTICR2_EXTI7                   AFIO_EXTICR2_EXTI7_Msk            /*!< EXTI 7 configuration */
2724 
2725 /*!< EXTI4 configuration */
2726 #define AFIO_EXTICR2_EXTI4_PA                0x00000000U                          /*!< PA[4] pin */
2727 #define AFIO_EXTICR2_EXTI4_PB_Pos            (0U)
2728 #define AFIO_EXTICR2_EXTI4_PB_Msk            (0x1UL << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
2729 #define AFIO_EXTICR2_EXTI4_PB                AFIO_EXTICR2_EXTI4_PB_Msk         /*!< PB[4] pin */
2730 #define AFIO_EXTICR2_EXTI4_PC_Pos            (1U)
2731 #define AFIO_EXTICR2_EXTI4_PC_Msk            (0x1UL << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */
2732 #define AFIO_EXTICR2_EXTI4_PC                AFIO_EXTICR2_EXTI4_PC_Msk         /*!< PC[4] pin */
2733 #define AFIO_EXTICR2_EXTI4_PD_Pos            (0U)
2734 #define AFIO_EXTICR2_EXTI4_PD_Msk            (0x3UL << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */
2735 #define AFIO_EXTICR2_EXTI4_PD                AFIO_EXTICR2_EXTI4_PD_Msk         /*!< PD[4] pin */
2736 #define AFIO_EXTICR2_EXTI4_PE_Pos            (2U)
2737 #define AFIO_EXTICR2_EXTI4_PE_Msk            (0x1UL << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */
2738 #define AFIO_EXTICR2_EXTI4_PE                AFIO_EXTICR2_EXTI4_PE_Msk         /*!< PE[4] pin */
2739 #define AFIO_EXTICR2_EXTI4_PF_Pos            (0U)
2740 #define AFIO_EXTICR2_EXTI4_PF_Msk            (0x5UL << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */
2741 #define AFIO_EXTICR2_EXTI4_PF                AFIO_EXTICR2_EXTI4_PF_Msk         /*!< PF[4] pin */
2742 #define AFIO_EXTICR2_EXTI4_PG_Pos            (1U)
2743 #define AFIO_EXTICR2_EXTI4_PG_Msk            (0x3UL << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */
2744 #define AFIO_EXTICR2_EXTI4_PG                AFIO_EXTICR2_EXTI4_PG_Msk         /*!< PG[4] pin */
2745 
2746 /* EXTI5 configuration */
2747 #define AFIO_EXTICR2_EXTI5_PA                0x00000000U                          /*!< PA[5] pin */
2748 #define AFIO_EXTICR2_EXTI5_PB_Pos            (4U)
2749 #define AFIO_EXTICR2_EXTI5_PB_Msk            (0x1UL << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
2750 #define AFIO_EXTICR2_EXTI5_PB                AFIO_EXTICR2_EXTI5_PB_Msk         /*!< PB[5] pin */
2751 #define AFIO_EXTICR2_EXTI5_PC_Pos            (5U)
2752 #define AFIO_EXTICR2_EXTI5_PC_Msk            (0x1UL << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */
2753 #define AFIO_EXTICR2_EXTI5_PC                AFIO_EXTICR2_EXTI5_PC_Msk         /*!< PC[5] pin */
2754 #define AFIO_EXTICR2_EXTI5_PD_Pos            (4U)
2755 #define AFIO_EXTICR2_EXTI5_PD_Msk            (0x3UL << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */
2756 #define AFIO_EXTICR2_EXTI5_PD                AFIO_EXTICR2_EXTI5_PD_Msk         /*!< PD[5] pin */
2757 #define AFIO_EXTICR2_EXTI5_PE_Pos            (6U)
2758 #define AFIO_EXTICR2_EXTI5_PE_Msk            (0x1UL << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */
2759 #define AFIO_EXTICR2_EXTI5_PE                AFIO_EXTICR2_EXTI5_PE_Msk         /*!< PE[5] pin */
2760 #define AFIO_EXTICR2_EXTI5_PF_Pos            (4U)
2761 #define AFIO_EXTICR2_EXTI5_PF_Msk            (0x5UL << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */
2762 #define AFIO_EXTICR2_EXTI5_PF                AFIO_EXTICR2_EXTI5_PF_Msk         /*!< PF[5] pin */
2763 #define AFIO_EXTICR2_EXTI5_PG_Pos            (5U)
2764 #define AFIO_EXTICR2_EXTI5_PG_Msk            (0x3UL << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */
2765 #define AFIO_EXTICR2_EXTI5_PG                AFIO_EXTICR2_EXTI5_PG_Msk         /*!< PG[5] pin */
2766 
2767 /*!< EXTI6 configuration */
2768 #define AFIO_EXTICR2_EXTI6_PA                0x00000000U                          /*!< PA[6] pin */
2769 #define AFIO_EXTICR2_EXTI6_PB_Pos            (8U)
2770 #define AFIO_EXTICR2_EXTI6_PB_Msk            (0x1UL << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
2771 #define AFIO_EXTICR2_EXTI6_PB                AFIO_EXTICR2_EXTI6_PB_Msk         /*!< PB[6] pin */
2772 #define AFIO_EXTICR2_EXTI6_PC_Pos            (9U)
2773 #define AFIO_EXTICR2_EXTI6_PC_Msk            (0x1UL << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */
2774 #define AFIO_EXTICR2_EXTI6_PC                AFIO_EXTICR2_EXTI6_PC_Msk         /*!< PC[6] pin */
2775 #define AFIO_EXTICR2_EXTI6_PD_Pos            (8U)
2776 #define AFIO_EXTICR2_EXTI6_PD_Msk            (0x3UL << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */
2777 #define AFIO_EXTICR2_EXTI6_PD                AFIO_EXTICR2_EXTI6_PD_Msk         /*!< PD[6] pin */
2778 #define AFIO_EXTICR2_EXTI6_PE_Pos            (10U)
2779 #define AFIO_EXTICR2_EXTI6_PE_Msk            (0x1UL << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */
2780 #define AFIO_EXTICR2_EXTI6_PE                AFIO_EXTICR2_EXTI6_PE_Msk         /*!< PE[6] pin */
2781 #define AFIO_EXTICR2_EXTI6_PF_Pos            (8U)
2782 #define AFIO_EXTICR2_EXTI6_PF_Msk            (0x5UL << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */
2783 #define AFIO_EXTICR2_EXTI6_PF                AFIO_EXTICR2_EXTI6_PF_Msk         /*!< PF[6] pin */
2784 #define AFIO_EXTICR2_EXTI6_PG_Pos            (9U)
2785 #define AFIO_EXTICR2_EXTI6_PG_Msk            (0x3UL << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */
2786 #define AFIO_EXTICR2_EXTI6_PG                AFIO_EXTICR2_EXTI6_PG_Msk         /*!< PG[6] pin */
2787 
2788 /*!< EXTI7 configuration */
2789 #define AFIO_EXTICR2_EXTI7_PA                0x00000000U                          /*!< PA[7] pin */
2790 #define AFIO_EXTICR2_EXTI7_PB_Pos            (12U)
2791 #define AFIO_EXTICR2_EXTI7_PB_Msk            (0x1UL << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
2792 #define AFIO_EXTICR2_EXTI7_PB                AFIO_EXTICR2_EXTI7_PB_Msk         /*!< PB[7] pin */
2793 #define AFIO_EXTICR2_EXTI7_PC_Pos            (13U)
2794 #define AFIO_EXTICR2_EXTI7_PC_Msk            (0x1UL << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */
2795 #define AFIO_EXTICR2_EXTI7_PC                AFIO_EXTICR2_EXTI7_PC_Msk         /*!< PC[7] pin */
2796 #define AFIO_EXTICR2_EXTI7_PD_Pos            (12U)
2797 #define AFIO_EXTICR2_EXTI7_PD_Msk            (0x3UL << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */
2798 #define AFIO_EXTICR2_EXTI7_PD                AFIO_EXTICR2_EXTI7_PD_Msk         /*!< PD[7] pin */
2799 #define AFIO_EXTICR2_EXTI7_PE_Pos            (14U)
2800 #define AFIO_EXTICR2_EXTI7_PE_Msk            (0x1UL << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */
2801 #define AFIO_EXTICR2_EXTI7_PE                AFIO_EXTICR2_EXTI7_PE_Msk         /*!< PE[7] pin */
2802 #define AFIO_EXTICR2_EXTI7_PF_Pos            (12U)
2803 #define AFIO_EXTICR2_EXTI7_PF_Msk            (0x5UL << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */
2804 #define AFIO_EXTICR2_EXTI7_PF                AFIO_EXTICR2_EXTI7_PF_Msk         /*!< PF[7] pin */
2805 #define AFIO_EXTICR2_EXTI7_PG_Pos            (13U)
2806 #define AFIO_EXTICR2_EXTI7_PG_Msk            (0x3UL << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */
2807 #define AFIO_EXTICR2_EXTI7_PG                AFIO_EXTICR2_EXTI7_PG_Msk         /*!< PG[7] pin */
2808 
2809 /*****************  Bit definition for AFIO_EXTICR3 register  *****************/
2810 #define AFIO_EXTICR3_EXTI8_Pos               (0U)
2811 #define AFIO_EXTICR3_EXTI8_Msk               (0xFUL << AFIO_EXTICR3_EXTI8_Pos)  /*!< 0x0000000F */
2812 #define AFIO_EXTICR3_EXTI8                   AFIO_EXTICR3_EXTI8_Msk            /*!< EXTI 8 configuration */
2813 #define AFIO_EXTICR3_EXTI9_Pos               (4U)
2814 #define AFIO_EXTICR3_EXTI9_Msk               (0xFUL << AFIO_EXTICR3_EXTI9_Pos)  /*!< 0x000000F0 */
2815 #define AFIO_EXTICR3_EXTI9                   AFIO_EXTICR3_EXTI9_Msk            /*!< EXTI 9 configuration */
2816 #define AFIO_EXTICR3_EXTI10_Pos              (8U)
2817 #define AFIO_EXTICR3_EXTI10_Msk              (0xFUL << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
2818 #define AFIO_EXTICR3_EXTI10                  AFIO_EXTICR3_EXTI10_Msk           /*!< EXTI 10 configuration */
2819 #define AFIO_EXTICR3_EXTI11_Pos              (12U)
2820 #define AFIO_EXTICR3_EXTI11_Msk              (0xFUL << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
2821 #define AFIO_EXTICR3_EXTI11                  AFIO_EXTICR3_EXTI11_Msk           /*!< EXTI 11 configuration */
2822 
2823 /*!< EXTI8 configuration */
2824 #define AFIO_EXTICR3_EXTI8_PA                0x00000000U                          /*!< PA[8] pin */
2825 #define AFIO_EXTICR3_EXTI8_PB_Pos            (0U)
2826 #define AFIO_EXTICR3_EXTI8_PB_Msk            (0x1UL << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
2827 #define AFIO_EXTICR3_EXTI8_PB                AFIO_EXTICR3_EXTI8_PB_Msk         /*!< PB[8] pin */
2828 #define AFIO_EXTICR3_EXTI8_PC_Pos            (1U)
2829 #define AFIO_EXTICR3_EXTI8_PC_Msk            (0x1UL << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */
2830 #define AFIO_EXTICR3_EXTI8_PC                AFIO_EXTICR3_EXTI8_PC_Msk         /*!< PC[8] pin */
2831 #define AFIO_EXTICR3_EXTI8_PD_Pos            (0U)
2832 #define AFIO_EXTICR3_EXTI8_PD_Msk            (0x3UL << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */
2833 #define AFIO_EXTICR3_EXTI8_PD                AFIO_EXTICR3_EXTI8_PD_Msk         /*!< PD[8] pin */
2834 #define AFIO_EXTICR3_EXTI8_PE_Pos            (2U)
2835 #define AFIO_EXTICR3_EXTI8_PE_Msk            (0x1UL << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */
2836 #define AFIO_EXTICR3_EXTI8_PE                AFIO_EXTICR3_EXTI8_PE_Msk         /*!< PE[8] pin */
2837 #define AFIO_EXTICR3_EXTI8_PF_Pos            (0U)
2838 #define AFIO_EXTICR3_EXTI8_PF_Msk            (0x5UL << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */
2839 #define AFIO_EXTICR3_EXTI8_PF                AFIO_EXTICR3_EXTI8_PF_Msk         /*!< PF[8] pin */
2840 #define AFIO_EXTICR3_EXTI8_PG_Pos            (1U)
2841 #define AFIO_EXTICR3_EXTI8_PG_Msk            (0x3UL << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */
2842 #define AFIO_EXTICR3_EXTI8_PG                AFIO_EXTICR3_EXTI8_PG_Msk         /*!< PG[8] pin */
2843 
2844 /*!< EXTI9 configuration */
2845 #define AFIO_EXTICR3_EXTI9_PA                0x00000000U                          /*!< PA[9] pin */
2846 #define AFIO_EXTICR3_EXTI9_PB_Pos            (4U)
2847 #define AFIO_EXTICR3_EXTI9_PB_Msk            (0x1UL << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
2848 #define AFIO_EXTICR3_EXTI9_PB                AFIO_EXTICR3_EXTI9_PB_Msk         /*!< PB[9] pin */
2849 #define AFIO_EXTICR3_EXTI9_PC_Pos            (5U)
2850 #define AFIO_EXTICR3_EXTI9_PC_Msk            (0x1UL << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */
2851 #define AFIO_EXTICR3_EXTI9_PC                AFIO_EXTICR3_EXTI9_PC_Msk         /*!< PC[9] pin */
2852 #define AFIO_EXTICR3_EXTI9_PD_Pos            (4U)
2853 #define AFIO_EXTICR3_EXTI9_PD_Msk            (0x3UL << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */
2854 #define AFIO_EXTICR3_EXTI9_PD                AFIO_EXTICR3_EXTI9_PD_Msk         /*!< PD[9] pin */
2855 #define AFIO_EXTICR3_EXTI9_PE_Pos            (6U)
2856 #define AFIO_EXTICR3_EXTI9_PE_Msk            (0x1UL << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */
2857 #define AFIO_EXTICR3_EXTI9_PE                AFIO_EXTICR3_EXTI9_PE_Msk         /*!< PE[9] pin */
2858 #define AFIO_EXTICR3_EXTI9_PF_Pos            (4U)
2859 #define AFIO_EXTICR3_EXTI9_PF_Msk            (0x5UL << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */
2860 #define AFIO_EXTICR3_EXTI9_PF                AFIO_EXTICR3_EXTI9_PF_Msk         /*!< PF[9] pin */
2861 #define AFIO_EXTICR3_EXTI9_PG_Pos            (5U)
2862 #define AFIO_EXTICR3_EXTI9_PG_Msk            (0x3UL << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */
2863 #define AFIO_EXTICR3_EXTI9_PG                AFIO_EXTICR3_EXTI9_PG_Msk         /*!< PG[9] pin */
2864 
2865 /*!< EXTI10 configuration */
2866 #define AFIO_EXTICR3_EXTI10_PA               0x00000000U                          /*!< PA[10] pin */
2867 #define AFIO_EXTICR3_EXTI10_PB_Pos           (8U)
2868 #define AFIO_EXTICR3_EXTI10_PB_Msk           (0x1UL << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
2869 #define AFIO_EXTICR3_EXTI10_PB               AFIO_EXTICR3_EXTI10_PB_Msk        /*!< PB[10] pin */
2870 #define AFIO_EXTICR3_EXTI10_PC_Pos           (9U)
2871 #define AFIO_EXTICR3_EXTI10_PC_Msk           (0x1UL << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */
2872 #define AFIO_EXTICR3_EXTI10_PC               AFIO_EXTICR3_EXTI10_PC_Msk        /*!< PC[10] pin */
2873 #define AFIO_EXTICR3_EXTI10_PD_Pos           (8U)
2874 #define AFIO_EXTICR3_EXTI10_PD_Msk           (0x3UL << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */
2875 #define AFIO_EXTICR3_EXTI10_PD               AFIO_EXTICR3_EXTI10_PD_Msk        /*!< PD[10] pin */
2876 #define AFIO_EXTICR3_EXTI10_PE_Pos           (10U)
2877 #define AFIO_EXTICR3_EXTI10_PE_Msk           (0x1UL << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */
2878 #define AFIO_EXTICR3_EXTI10_PE               AFIO_EXTICR3_EXTI10_PE_Msk        /*!< PE[10] pin */
2879 #define AFIO_EXTICR3_EXTI10_PF_Pos           (8U)
2880 #define AFIO_EXTICR3_EXTI10_PF_Msk           (0x5UL << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */
2881 #define AFIO_EXTICR3_EXTI10_PF               AFIO_EXTICR3_EXTI10_PF_Msk        /*!< PF[10] pin */
2882 #define AFIO_EXTICR3_EXTI10_PG_Pos           (9U)
2883 #define AFIO_EXTICR3_EXTI10_PG_Msk           (0x3UL << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */
2884 #define AFIO_EXTICR3_EXTI10_PG               AFIO_EXTICR3_EXTI10_PG_Msk        /*!< PG[10] pin */
2885 
2886 /*!< EXTI11 configuration */
2887 #define AFIO_EXTICR3_EXTI11_PA               0x00000000U                          /*!< PA[11] pin */
2888 #define AFIO_EXTICR3_EXTI11_PB_Pos           (12U)
2889 #define AFIO_EXTICR3_EXTI11_PB_Msk           (0x1UL << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
2890 #define AFIO_EXTICR3_EXTI11_PB               AFIO_EXTICR3_EXTI11_PB_Msk        /*!< PB[11] pin */
2891 #define AFIO_EXTICR3_EXTI11_PC_Pos           (13U)
2892 #define AFIO_EXTICR3_EXTI11_PC_Msk           (0x1UL << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */
2893 #define AFIO_EXTICR3_EXTI11_PC               AFIO_EXTICR3_EXTI11_PC_Msk        /*!< PC[11] pin */
2894 #define AFIO_EXTICR3_EXTI11_PD_Pos           (12U)
2895 #define AFIO_EXTICR3_EXTI11_PD_Msk           (0x3UL << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */
2896 #define AFIO_EXTICR3_EXTI11_PD               AFIO_EXTICR3_EXTI11_PD_Msk        /*!< PD[11] pin */
2897 #define AFIO_EXTICR3_EXTI11_PE_Pos           (14U)
2898 #define AFIO_EXTICR3_EXTI11_PE_Msk           (0x1UL << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */
2899 #define AFIO_EXTICR3_EXTI11_PE               AFIO_EXTICR3_EXTI11_PE_Msk        /*!< PE[11] pin */
2900 #define AFIO_EXTICR3_EXTI11_PF_Pos           (12U)
2901 #define AFIO_EXTICR3_EXTI11_PF_Msk           (0x5UL << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */
2902 #define AFIO_EXTICR3_EXTI11_PF               AFIO_EXTICR3_EXTI11_PF_Msk        /*!< PF[11] pin */
2903 #define AFIO_EXTICR3_EXTI11_PG_Pos           (13U)
2904 #define AFIO_EXTICR3_EXTI11_PG_Msk           (0x3UL << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */
2905 #define AFIO_EXTICR3_EXTI11_PG               AFIO_EXTICR3_EXTI11_PG_Msk        /*!< PG[11] pin */
2906 
2907 /*****************  Bit definition for AFIO_EXTICR4 register  *****************/
2908 #define AFIO_EXTICR4_EXTI12_Pos              (0U)
2909 #define AFIO_EXTICR4_EXTI12_Msk              (0xFUL << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
2910 #define AFIO_EXTICR4_EXTI12                  AFIO_EXTICR4_EXTI12_Msk           /*!< EXTI 12 configuration */
2911 #define AFIO_EXTICR4_EXTI13_Pos              (4U)
2912 #define AFIO_EXTICR4_EXTI13_Msk              (0xFUL << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
2913 #define AFIO_EXTICR4_EXTI13                  AFIO_EXTICR4_EXTI13_Msk           /*!< EXTI 13 configuration */
2914 #define AFIO_EXTICR4_EXTI14_Pos              (8U)
2915 #define AFIO_EXTICR4_EXTI14_Msk              (0xFUL << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
2916 #define AFIO_EXTICR4_EXTI14                  AFIO_EXTICR4_EXTI14_Msk           /*!< EXTI 14 configuration */
2917 #define AFIO_EXTICR4_EXTI15_Pos              (12U)
2918 #define AFIO_EXTICR4_EXTI15_Msk              (0xFUL << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
2919 #define AFIO_EXTICR4_EXTI15                  AFIO_EXTICR4_EXTI15_Msk           /*!< EXTI 15 configuration */
2920 
2921 /* EXTI12 configuration */
2922 #define AFIO_EXTICR4_EXTI12_PA               0x00000000U                          /*!< PA[12] pin */
2923 #define AFIO_EXTICR4_EXTI12_PB_Pos           (0U)
2924 #define AFIO_EXTICR4_EXTI12_PB_Msk           (0x1UL << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
2925 #define AFIO_EXTICR4_EXTI12_PB               AFIO_EXTICR4_EXTI12_PB_Msk        /*!< PB[12] pin */
2926 #define AFIO_EXTICR4_EXTI12_PC_Pos           (1U)
2927 #define AFIO_EXTICR4_EXTI12_PC_Msk           (0x1UL << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */
2928 #define AFIO_EXTICR4_EXTI12_PC               AFIO_EXTICR4_EXTI12_PC_Msk        /*!< PC[12] pin */
2929 #define AFIO_EXTICR4_EXTI12_PD_Pos           (0U)
2930 #define AFIO_EXTICR4_EXTI12_PD_Msk           (0x3UL << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */
2931 #define AFIO_EXTICR4_EXTI12_PD               AFIO_EXTICR4_EXTI12_PD_Msk        /*!< PD[12] pin */
2932 #define AFIO_EXTICR4_EXTI12_PE_Pos           (2U)
2933 #define AFIO_EXTICR4_EXTI12_PE_Msk           (0x1UL << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */
2934 #define AFIO_EXTICR4_EXTI12_PE               AFIO_EXTICR4_EXTI12_PE_Msk        /*!< PE[12] pin */
2935 #define AFIO_EXTICR4_EXTI12_PF_Pos           (0U)
2936 #define AFIO_EXTICR4_EXTI12_PF_Msk           (0x5UL << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */
2937 #define AFIO_EXTICR4_EXTI12_PF               AFIO_EXTICR4_EXTI12_PF_Msk        /*!< PF[12] pin */
2938 #define AFIO_EXTICR4_EXTI12_PG_Pos           (1U)
2939 #define AFIO_EXTICR4_EXTI12_PG_Msk           (0x3UL << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */
2940 #define AFIO_EXTICR4_EXTI12_PG               AFIO_EXTICR4_EXTI12_PG_Msk        /*!< PG[12] pin */
2941 
2942 /* EXTI13 configuration */
2943 #define AFIO_EXTICR4_EXTI13_PA               0x00000000U                          /*!< PA[13] pin */
2944 #define AFIO_EXTICR4_EXTI13_PB_Pos           (4U)
2945 #define AFIO_EXTICR4_EXTI13_PB_Msk           (0x1UL << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
2946 #define AFIO_EXTICR4_EXTI13_PB               AFIO_EXTICR4_EXTI13_PB_Msk        /*!< PB[13] pin */
2947 #define AFIO_EXTICR4_EXTI13_PC_Pos           (5U)
2948 #define AFIO_EXTICR4_EXTI13_PC_Msk           (0x1UL << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */
2949 #define AFIO_EXTICR4_EXTI13_PC               AFIO_EXTICR4_EXTI13_PC_Msk        /*!< PC[13] pin */
2950 #define AFIO_EXTICR4_EXTI13_PD_Pos           (4U)
2951 #define AFIO_EXTICR4_EXTI13_PD_Msk           (0x3UL << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */
2952 #define AFIO_EXTICR4_EXTI13_PD               AFIO_EXTICR4_EXTI13_PD_Msk        /*!< PD[13] pin */
2953 #define AFIO_EXTICR4_EXTI13_PE_Pos           (6U)
2954 #define AFIO_EXTICR4_EXTI13_PE_Msk           (0x1UL << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */
2955 #define AFIO_EXTICR4_EXTI13_PE               AFIO_EXTICR4_EXTI13_PE_Msk        /*!< PE[13] pin */
2956 #define AFIO_EXTICR4_EXTI13_PF_Pos           (4U)
2957 #define AFIO_EXTICR4_EXTI13_PF_Msk           (0x5UL << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */
2958 #define AFIO_EXTICR4_EXTI13_PF               AFIO_EXTICR4_EXTI13_PF_Msk        /*!< PF[13] pin */
2959 #define AFIO_EXTICR4_EXTI13_PG_Pos           (5U)
2960 #define AFIO_EXTICR4_EXTI13_PG_Msk           (0x3UL << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */
2961 #define AFIO_EXTICR4_EXTI13_PG               AFIO_EXTICR4_EXTI13_PG_Msk        /*!< PG[13] pin */
2962 
2963 /*!< EXTI14 configuration */
2964 #define AFIO_EXTICR4_EXTI14_PA               0x00000000U                          /*!< PA[14] pin */
2965 #define AFIO_EXTICR4_EXTI14_PB_Pos           (8U)
2966 #define AFIO_EXTICR4_EXTI14_PB_Msk           (0x1UL << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
2967 #define AFIO_EXTICR4_EXTI14_PB               AFIO_EXTICR4_EXTI14_PB_Msk        /*!< PB[14] pin */
2968 #define AFIO_EXTICR4_EXTI14_PC_Pos           (9U)
2969 #define AFIO_EXTICR4_EXTI14_PC_Msk           (0x1UL << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */
2970 #define AFIO_EXTICR4_EXTI14_PC               AFIO_EXTICR4_EXTI14_PC_Msk        /*!< PC[14] pin */
2971 #define AFIO_EXTICR4_EXTI14_PD_Pos           (8U)
2972 #define AFIO_EXTICR4_EXTI14_PD_Msk           (0x3UL << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */
2973 #define AFIO_EXTICR4_EXTI14_PD               AFIO_EXTICR4_EXTI14_PD_Msk        /*!< PD[14] pin */
2974 #define AFIO_EXTICR4_EXTI14_PE_Pos           (10U)
2975 #define AFIO_EXTICR4_EXTI14_PE_Msk           (0x1UL << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */
2976 #define AFIO_EXTICR4_EXTI14_PE               AFIO_EXTICR4_EXTI14_PE_Msk        /*!< PE[14] pin */
2977 #define AFIO_EXTICR4_EXTI14_PF_Pos           (8U)
2978 #define AFIO_EXTICR4_EXTI14_PF_Msk           (0x5UL << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */
2979 #define AFIO_EXTICR4_EXTI14_PF               AFIO_EXTICR4_EXTI14_PF_Msk        /*!< PF[14] pin */
2980 #define AFIO_EXTICR4_EXTI14_PG_Pos           (9U)
2981 #define AFIO_EXTICR4_EXTI14_PG_Msk           (0x3UL << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */
2982 #define AFIO_EXTICR4_EXTI14_PG               AFIO_EXTICR4_EXTI14_PG_Msk        /*!< PG[14] pin */
2983 
2984 /*!< EXTI15 configuration */
2985 #define AFIO_EXTICR4_EXTI15_PA               0x00000000U                          /*!< PA[15] pin */
2986 #define AFIO_EXTICR4_EXTI15_PB_Pos           (12U)
2987 #define AFIO_EXTICR4_EXTI15_PB_Msk           (0x1UL << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
2988 #define AFIO_EXTICR4_EXTI15_PB               AFIO_EXTICR4_EXTI15_PB_Msk        /*!< PB[15] pin */
2989 #define AFIO_EXTICR4_EXTI15_PC_Pos           (13U)
2990 #define AFIO_EXTICR4_EXTI15_PC_Msk           (0x1UL << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */
2991 #define AFIO_EXTICR4_EXTI15_PC               AFIO_EXTICR4_EXTI15_PC_Msk        /*!< PC[15] pin */
2992 #define AFIO_EXTICR4_EXTI15_PD_Pos           (12U)
2993 #define AFIO_EXTICR4_EXTI15_PD_Msk           (0x3UL << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */
2994 #define AFIO_EXTICR4_EXTI15_PD               AFIO_EXTICR4_EXTI15_PD_Msk        /*!< PD[15] pin */
2995 #define AFIO_EXTICR4_EXTI15_PE_Pos           (14U)
2996 #define AFIO_EXTICR4_EXTI15_PE_Msk           (0x1UL << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */
2997 #define AFIO_EXTICR4_EXTI15_PE               AFIO_EXTICR4_EXTI15_PE_Msk        /*!< PE[15] pin */
2998 #define AFIO_EXTICR4_EXTI15_PF_Pos           (12U)
2999 #define AFIO_EXTICR4_EXTI15_PF_Msk           (0x5UL << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */
3000 #define AFIO_EXTICR4_EXTI15_PF               AFIO_EXTICR4_EXTI15_PF_Msk        /*!< PF[15] pin */
3001 #define AFIO_EXTICR4_EXTI15_PG_Pos           (13U)
3002 #define AFIO_EXTICR4_EXTI15_PG_Msk           (0x3UL << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */
3003 #define AFIO_EXTICR4_EXTI15_PG               AFIO_EXTICR4_EXTI15_PG_Msk        /*!< PG[15] pin */
3004 
3005 /******************  Bit definition for AFIO_MAPR2 register  ******************/
3006 
3007 
3008 #define AFIO_MAPR2_FSMC_NADV_REMAP_Pos       (10U)
3009 #define AFIO_MAPR2_FSMC_NADV_REMAP_Msk       (0x1UL << AFIO_MAPR2_FSMC_NADV_REMAP_Pos) /*!< 0x00000400 */
3010 #define AFIO_MAPR2_FSMC_NADV_REMAP           AFIO_MAPR2_FSMC_NADV_REMAP_Msk    /*!< FSMC NADV remapping */
3011 
3012 /******************************************************************************/
3013 /*                                                                            */
3014 /*                    External Interrupt/Event Controller                     */
3015 /*                                                                            */
3016 /******************************************************************************/
3017 
3018 /*******************  Bit definition for EXTI_IMR register  *******************/
3019 #define EXTI_IMR_MR0_Pos                    (0U)
3020 #define EXTI_IMR_MR0_Msk                    (0x1UL << EXTI_IMR_MR0_Pos)         /*!< 0x00000001 */
3021 #define EXTI_IMR_MR0                        EXTI_IMR_MR0_Msk                   /*!< Interrupt Mask on line 0 */
3022 #define EXTI_IMR_MR1_Pos                    (1U)
3023 #define EXTI_IMR_MR1_Msk                    (0x1UL << EXTI_IMR_MR1_Pos)         /*!< 0x00000002 */
3024 #define EXTI_IMR_MR1                        EXTI_IMR_MR1_Msk                   /*!< Interrupt Mask on line 1 */
3025 #define EXTI_IMR_MR2_Pos                    (2U)
3026 #define EXTI_IMR_MR2_Msk                    (0x1UL << EXTI_IMR_MR2_Pos)         /*!< 0x00000004 */
3027 #define EXTI_IMR_MR2                        EXTI_IMR_MR2_Msk                   /*!< Interrupt Mask on line 2 */
3028 #define EXTI_IMR_MR3_Pos                    (3U)
3029 #define EXTI_IMR_MR3_Msk                    (0x1UL << EXTI_IMR_MR3_Pos)         /*!< 0x00000008 */
3030 #define EXTI_IMR_MR3                        EXTI_IMR_MR3_Msk                   /*!< Interrupt Mask on line 3 */
3031 #define EXTI_IMR_MR4_Pos                    (4U)
3032 #define EXTI_IMR_MR4_Msk                    (0x1UL << EXTI_IMR_MR4_Pos)         /*!< 0x00000010 */
3033 #define EXTI_IMR_MR4                        EXTI_IMR_MR4_Msk                   /*!< Interrupt Mask on line 4 */
3034 #define EXTI_IMR_MR5_Pos                    (5U)
3035 #define EXTI_IMR_MR5_Msk                    (0x1UL << EXTI_IMR_MR5_Pos)         /*!< 0x00000020 */
3036 #define EXTI_IMR_MR5                        EXTI_IMR_MR5_Msk                   /*!< Interrupt Mask on line 5 */
3037 #define EXTI_IMR_MR6_Pos                    (6U)
3038 #define EXTI_IMR_MR6_Msk                    (0x1UL << EXTI_IMR_MR6_Pos)         /*!< 0x00000040 */
3039 #define EXTI_IMR_MR6                        EXTI_IMR_MR6_Msk                   /*!< Interrupt Mask on line 6 */
3040 #define EXTI_IMR_MR7_Pos                    (7U)
3041 #define EXTI_IMR_MR7_Msk                    (0x1UL << EXTI_IMR_MR7_Pos)         /*!< 0x00000080 */
3042 #define EXTI_IMR_MR7                        EXTI_IMR_MR7_Msk                   /*!< Interrupt Mask on line 7 */
3043 #define EXTI_IMR_MR8_Pos                    (8U)
3044 #define EXTI_IMR_MR8_Msk                    (0x1UL << EXTI_IMR_MR8_Pos)         /*!< 0x00000100 */
3045 #define EXTI_IMR_MR8                        EXTI_IMR_MR8_Msk                   /*!< Interrupt Mask on line 8 */
3046 #define EXTI_IMR_MR9_Pos                    (9U)
3047 #define EXTI_IMR_MR9_Msk                    (0x1UL << EXTI_IMR_MR9_Pos)         /*!< 0x00000200 */
3048 #define EXTI_IMR_MR9                        EXTI_IMR_MR9_Msk                   /*!< Interrupt Mask on line 9 */
3049 #define EXTI_IMR_MR10_Pos                   (10U)
3050 #define EXTI_IMR_MR10_Msk                   (0x1UL << EXTI_IMR_MR10_Pos)        /*!< 0x00000400 */
3051 #define EXTI_IMR_MR10                       EXTI_IMR_MR10_Msk                  /*!< Interrupt Mask on line 10 */
3052 #define EXTI_IMR_MR11_Pos                   (11U)
3053 #define EXTI_IMR_MR11_Msk                   (0x1UL << EXTI_IMR_MR11_Pos)        /*!< 0x00000800 */
3054 #define EXTI_IMR_MR11                       EXTI_IMR_MR11_Msk                  /*!< Interrupt Mask on line 11 */
3055 #define EXTI_IMR_MR12_Pos                   (12U)
3056 #define EXTI_IMR_MR12_Msk                   (0x1UL << EXTI_IMR_MR12_Pos)        /*!< 0x00001000 */
3057 #define EXTI_IMR_MR12                       EXTI_IMR_MR12_Msk                  /*!< Interrupt Mask on line 12 */
3058 #define EXTI_IMR_MR13_Pos                   (13U)
3059 #define EXTI_IMR_MR13_Msk                   (0x1UL << EXTI_IMR_MR13_Pos)        /*!< 0x00002000 */
3060 #define EXTI_IMR_MR13                       EXTI_IMR_MR13_Msk                  /*!< Interrupt Mask on line 13 */
3061 #define EXTI_IMR_MR14_Pos                   (14U)
3062 #define EXTI_IMR_MR14_Msk                   (0x1UL << EXTI_IMR_MR14_Pos)        /*!< 0x00004000 */
3063 #define EXTI_IMR_MR14                       EXTI_IMR_MR14_Msk                  /*!< Interrupt Mask on line 14 */
3064 #define EXTI_IMR_MR15_Pos                   (15U)
3065 #define EXTI_IMR_MR15_Msk                   (0x1UL << EXTI_IMR_MR15_Pos)        /*!< 0x00008000 */
3066 #define EXTI_IMR_MR15                       EXTI_IMR_MR15_Msk                  /*!< Interrupt Mask on line 15 */
3067 #define EXTI_IMR_MR16_Pos                   (16U)
3068 #define EXTI_IMR_MR16_Msk                   (0x1UL << EXTI_IMR_MR16_Pos)        /*!< 0x00010000 */
3069 #define EXTI_IMR_MR16                       EXTI_IMR_MR16_Msk                  /*!< Interrupt Mask on line 16 */
3070 #define EXTI_IMR_MR17_Pos                   (17U)
3071 #define EXTI_IMR_MR17_Msk                   (0x1UL << EXTI_IMR_MR17_Pos)        /*!< 0x00020000 */
3072 #define EXTI_IMR_MR17                       EXTI_IMR_MR17_Msk                  /*!< Interrupt Mask on line 17 */
3073 #define EXTI_IMR_MR18_Pos                   (18U)
3074 #define EXTI_IMR_MR18_Msk                   (0x1UL << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */
3075 #define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */
3076 
3077 /* References Defines */
3078 #define  EXTI_IMR_IM0 EXTI_IMR_MR0
3079 #define  EXTI_IMR_IM1 EXTI_IMR_MR1
3080 #define  EXTI_IMR_IM2 EXTI_IMR_MR2
3081 #define  EXTI_IMR_IM3 EXTI_IMR_MR3
3082 #define  EXTI_IMR_IM4 EXTI_IMR_MR4
3083 #define  EXTI_IMR_IM5 EXTI_IMR_MR5
3084 #define  EXTI_IMR_IM6 EXTI_IMR_MR6
3085 #define  EXTI_IMR_IM7 EXTI_IMR_MR7
3086 #define  EXTI_IMR_IM8 EXTI_IMR_MR8
3087 #define  EXTI_IMR_IM9 EXTI_IMR_MR9
3088 #define  EXTI_IMR_IM10 EXTI_IMR_MR10
3089 #define  EXTI_IMR_IM11 EXTI_IMR_MR11
3090 #define  EXTI_IMR_IM12 EXTI_IMR_MR12
3091 #define  EXTI_IMR_IM13 EXTI_IMR_MR13
3092 #define  EXTI_IMR_IM14 EXTI_IMR_MR14
3093 #define  EXTI_IMR_IM15 EXTI_IMR_MR15
3094 #define  EXTI_IMR_IM16 EXTI_IMR_MR16
3095 #define  EXTI_IMR_IM17 EXTI_IMR_MR17
3096 #define  EXTI_IMR_IM18 EXTI_IMR_MR18
3097 #define  EXTI_IMR_IM   0x0007FFFFU        /*!< Interrupt Mask All */
3098 
3099 /*******************  Bit definition for EXTI_EMR register  *******************/
3100 #define EXTI_EMR_MR0_Pos                    (0U)
3101 #define EXTI_EMR_MR0_Msk                    (0x1UL << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */
3102 #define EXTI_EMR_MR0                        EXTI_EMR_MR0_Msk                   /*!< Event Mask on line 0 */
3103 #define EXTI_EMR_MR1_Pos                    (1U)
3104 #define EXTI_EMR_MR1_Msk                    (0x1UL << EXTI_EMR_MR1_Pos)         /*!< 0x00000002 */
3105 #define EXTI_EMR_MR1                        EXTI_EMR_MR1_Msk                   /*!< Event Mask on line 1 */
3106 #define EXTI_EMR_MR2_Pos                    (2U)
3107 #define EXTI_EMR_MR2_Msk                    (0x1UL << EXTI_EMR_MR2_Pos)         /*!< 0x00000004 */
3108 #define EXTI_EMR_MR2                        EXTI_EMR_MR2_Msk                   /*!< Event Mask on line 2 */
3109 #define EXTI_EMR_MR3_Pos                    (3U)
3110 #define EXTI_EMR_MR3_Msk                    (0x1UL << EXTI_EMR_MR3_Pos)         /*!< 0x00000008 */
3111 #define EXTI_EMR_MR3                        EXTI_EMR_MR3_Msk                   /*!< Event Mask on line 3 */
3112 #define EXTI_EMR_MR4_Pos                    (4U)
3113 #define EXTI_EMR_MR4_Msk                    (0x1UL << EXTI_EMR_MR4_Pos)         /*!< 0x00000010 */
3114 #define EXTI_EMR_MR4                        EXTI_EMR_MR4_Msk                   /*!< Event Mask on line 4 */
3115 #define EXTI_EMR_MR5_Pos                    (5U)
3116 #define EXTI_EMR_MR5_Msk                    (0x1UL << EXTI_EMR_MR5_Pos)         /*!< 0x00000020 */
3117 #define EXTI_EMR_MR5                        EXTI_EMR_MR5_Msk                   /*!< Event Mask on line 5 */
3118 #define EXTI_EMR_MR6_Pos                    (6U)
3119 #define EXTI_EMR_MR6_Msk                    (0x1UL << EXTI_EMR_MR6_Pos)         /*!< 0x00000040 */
3120 #define EXTI_EMR_MR6                        EXTI_EMR_MR6_Msk                   /*!< Event Mask on line 6 */
3121 #define EXTI_EMR_MR7_Pos                    (7U)
3122 #define EXTI_EMR_MR7_Msk                    (0x1UL << EXTI_EMR_MR7_Pos)         /*!< 0x00000080 */
3123 #define EXTI_EMR_MR7                        EXTI_EMR_MR7_Msk                   /*!< Event Mask on line 7 */
3124 #define EXTI_EMR_MR8_Pos                    (8U)
3125 #define EXTI_EMR_MR8_Msk                    (0x1UL << EXTI_EMR_MR8_Pos)         /*!< 0x00000100 */
3126 #define EXTI_EMR_MR8                        EXTI_EMR_MR8_Msk                   /*!< Event Mask on line 8 */
3127 #define EXTI_EMR_MR9_Pos                    (9U)
3128 #define EXTI_EMR_MR9_Msk                    (0x1UL << EXTI_EMR_MR9_Pos)         /*!< 0x00000200 */
3129 #define EXTI_EMR_MR9                        EXTI_EMR_MR9_Msk                   /*!< Event Mask on line 9 */
3130 #define EXTI_EMR_MR10_Pos                   (10U)
3131 #define EXTI_EMR_MR10_Msk                   (0x1UL << EXTI_EMR_MR10_Pos)        /*!< 0x00000400 */
3132 #define EXTI_EMR_MR10                       EXTI_EMR_MR10_Msk                  /*!< Event Mask on line 10 */
3133 #define EXTI_EMR_MR11_Pos                   (11U)
3134 #define EXTI_EMR_MR11_Msk                   (0x1UL << EXTI_EMR_MR11_Pos)        /*!< 0x00000800 */
3135 #define EXTI_EMR_MR11                       EXTI_EMR_MR11_Msk                  /*!< Event Mask on line 11 */
3136 #define EXTI_EMR_MR12_Pos                   (12U)
3137 #define EXTI_EMR_MR12_Msk                   (0x1UL << EXTI_EMR_MR12_Pos)        /*!< 0x00001000 */
3138 #define EXTI_EMR_MR12                       EXTI_EMR_MR12_Msk                  /*!< Event Mask on line 12 */
3139 #define EXTI_EMR_MR13_Pos                   (13U)
3140 #define EXTI_EMR_MR13_Msk                   (0x1UL << EXTI_EMR_MR13_Pos)        /*!< 0x00002000 */
3141 #define EXTI_EMR_MR13                       EXTI_EMR_MR13_Msk                  /*!< Event Mask on line 13 */
3142 #define EXTI_EMR_MR14_Pos                   (14U)
3143 #define EXTI_EMR_MR14_Msk                   (0x1UL << EXTI_EMR_MR14_Pos)        /*!< 0x00004000 */
3144 #define EXTI_EMR_MR14                       EXTI_EMR_MR14_Msk                  /*!< Event Mask on line 14 */
3145 #define EXTI_EMR_MR15_Pos                   (15U)
3146 #define EXTI_EMR_MR15_Msk                   (0x1UL << EXTI_EMR_MR15_Pos)        /*!< 0x00008000 */
3147 #define EXTI_EMR_MR15                       EXTI_EMR_MR15_Msk                  /*!< Event Mask on line 15 */
3148 #define EXTI_EMR_MR16_Pos                   (16U)
3149 #define EXTI_EMR_MR16_Msk                   (0x1UL << EXTI_EMR_MR16_Pos)        /*!< 0x00010000 */
3150 #define EXTI_EMR_MR16                       EXTI_EMR_MR16_Msk                  /*!< Event Mask on line 16 */
3151 #define EXTI_EMR_MR17_Pos                   (17U)
3152 #define EXTI_EMR_MR17_Msk                   (0x1UL << EXTI_EMR_MR17_Pos)        /*!< 0x00020000 */
3153 #define EXTI_EMR_MR17                       EXTI_EMR_MR17_Msk                  /*!< Event Mask on line 17 */
3154 #define EXTI_EMR_MR18_Pos                   (18U)
3155 #define EXTI_EMR_MR18_Msk                   (0x1UL << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */
3156 #define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */
3157 
3158 /* References Defines */
3159 #define  EXTI_EMR_EM0 EXTI_EMR_MR0
3160 #define  EXTI_EMR_EM1 EXTI_EMR_MR1
3161 #define  EXTI_EMR_EM2 EXTI_EMR_MR2
3162 #define  EXTI_EMR_EM3 EXTI_EMR_MR3
3163 #define  EXTI_EMR_EM4 EXTI_EMR_MR4
3164 #define  EXTI_EMR_EM5 EXTI_EMR_MR5
3165 #define  EXTI_EMR_EM6 EXTI_EMR_MR6
3166 #define  EXTI_EMR_EM7 EXTI_EMR_MR7
3167 #define  EXTI_EMR_EM8 EXTI_EMR_MR8
3168 #define  EXTI_EMR_EM9 EXTI_EMR_MR9
3169 #define  EXTI_EMR_EM10 EXTI_EMR_MR10
3170 #define  EXTI_EMR_EM11 EXTI_EMR_MR11
3171 #define  EXTI_EMR_EM12 EXTI_EMR_MR12
3172 #define  EXTI_EMR_EM13 EXTI_EMR_MR13
3173 #define  EXTI_EMR_EM14 EXTI_EMR_MR14
3174 #define  EXTI_EMR_EM15 EXTI_EMR_MR15
3175 #define  EXTI_EMR_EM16 EXTI_EMR_MR16
3176 #define  EXTI_EMR_EM17 EXTI_EMR_MR17
3177 #define  EXTI_EMR_EM18 EXTI_EMR_MR18
3178 
3179 /******************  Bit definition for EXTI_RTSR register  *******************/
3180 #define EXTI_RTSR_TR0_Pos                   (0U)
3181 #define EXTI_RTSR_TR0_Msk                   (0x1UL << EXTI_RTSR_TR0_Pos)        /*!< 0x00000001 */
3182 #define EXTI_RTSR_TR0                       EXTI_RTSR_TR0_Msk                  /*!< Rising trigger event configuration bit of line 0 */
3183 #define EXTI_RTSR_TR1_Pos                   (1U)
3184 #define EXTI_RTSR_TR1_Msk                   (0x1UL << EXTI_RTSR_TR1_Pos)        /*!< 0x00000002 */
3185 #define EXTI_RTSR_TR1                       EXTI_RTSR_TR1_Msk                  /*!< Rising trigger event configuration bit of line 1 */
3186 #define EXTI_RTSR_TR2_Pos                   (2U)
3187 #define EXTI_RTSR_TR2_Msk                   (0x1UL << EXTI_RTSR_TR2_Pos)        /*!< 0x00000004 */
3188 #define EXTI_RTSR_TR2                       EXTI_RTSR_TR2_Msk                  /*!< Rising trigger event configuration bit of line 2 */
3189 #define EXTI_RTSR_TR3_Pos                   (3U)
3190 #define EXTI_RTSR_TR3_Msk                   (0x1UL << EXTI_RTSR_TR3_Pos)        /*!< 0x00000008 */
3191 #define EXTI_RTSR_TR3                       EXTI_RTSR_TR3_Msk                  /*!< Rising trigger event configuration bit of line 3 */
3192 #define EXTI_RTSR_TR4_Pos                   (4U)
3193 #define EXTI_RTSR_TR4_Msk                   (0x1UL << EXTI_RTSR_TR4_Pos)        /*!< 0x00000010 */
3194 #define EXTI_RTSR_TR4                       EXTI_RTSR_TR4_Msk                  /*!< Rising trigger event configuration bit of line 4 */
3195 #define EXTI_RTSR_TR5_Pos                   (5U)
3196 #define EXTI_RTSR_TR5_Msk                   (0x1UL << EXTI_RTSR_TR5_Pos)        /*!< 0x00000020 */
3197 #define EXTI_RTSR_TR5                       EXTI_RTSR_TR5_Msk                  /*!< Rising trigger event configuration bit of line 5 */
3198 #define EXTI_RTSR_TR6_Pos                   (6U)
3199 #define EXTI_RTSR_TR6_Msk                   (0x1UL << EXTI_RTSR_TR6_Pos)        /*!< 0x00000040 */
3200 #define EXTI_RTSR_TR6                       EXTI_RTSR_TR6_Msk                  /*!< Rising trigger event configuration bit of line 6 */
3201 #define EXTI_RTSR_TR7_Pos                   (7U)
3202 #define EXTI_RTSR_TR7_Msk                   (0x1UL << EXTI_RTSR_TR7_Pos)        /*!< 0x00000080 */
3203 #define EXTI_RTSR_TR7                       EXTI_RTSR_TR7_Msk                  /*!< Rising trigger event configuration bit of line 7 */
3204 #define EXTI_RTSR_TR8_Pos                   (8U)
3205 #define EXTI_RTSR_TR8_Msk                   (0x1UL << EXTI_RTSR_TR8_Pos)        /*!< 0x00000100 */
3206 #define EXTI_RTSR_TR8                       EXTI_RTSR_TR8_Msk                  /*!< Rising trigger event configuration bit of line 8 */
3207 #define EXTI_RTSR_TR9_Pos                   (9U)
3208 #define EXTI_RTSR_TR9_Msk                   (0x1UL << EXTI_RTSR_TR9_Pos)        /*!< 0x00000200 */
3209 #define EXTI_RTSR_TR9                       EXTI_RTSR_TR9_Msk                  /*!< Rising trigger event configuration bit of line 9 */
3210 #define EXTI_RTSR_TR10_Pos                  (10U)
3211 #define EXTI_RTSR_TR10_Msk                  (0x1UL << EXTI_RTSR_TR10_Pos)       /*!< 0x00000400 */
3212 #define EXTI_RTSR_TR10                      EXTI_RTSR_TR10_Msk                 /*!< Rising trigger event configuration bit of line 10 */
3213 #define EXTI_RTSR_TR11_Pos                  (11U)
3214 #define EXTI_RTSR_TR11_Msk                  (0x1UL << EXTI_RTSR_TR11_Pos)       /*!< 0x00000800 */
3215 #define EXTI_RTSR_TR11                      EXTI_RTSR_TR11_Msk                 /*!< Rising trigger event configuration bit of line 11 */
3216 #define EXTI_RTSR_TR12_Pos                  (12U)
3217 #define EXTI_RTSR_TR12_Msk                  (0x1UL << EXTI_RTSR_TR12_Pos)       /*!< 0x00001000 */
3218 #define EXTI_RTSR_TR12                      EXTI_RTSR_TR12_Msk                 /*!< Rising trigger event configuration bit of line 12 */
3219 #define EXTI_RTSR_TR13_Pos                  (13U)
3220 #define EXTI_RTSR_TR13_Msk                  (0x1UL << EXTI_RTSR_TR13_Pos)       /*!< 0x00002000 */
3221 #define EXTI_RTSR_TR13                      EXTI_RTSR_TR13_Msk                 /*!< Rising trigger event configuration bit of line 13 */
3222 #define EXTI_RTSR_TR14_Pos                  (14U)
3223 #define EXTI_RTSR_TR14_Msk                  (0x1UL << EXTI_RTSR_TR14_Pos)       /*!< 0x00004000 */
3224 #define EXTI_RTSR_TR14                      EXTI_RTSR_TR14_Msk                 /*!< Rising trigger event configuration bit of line 14 */
3225 #define EXTI_RTSR_TR15_Pos                  (15U)
3226 #define EXTI_RTSR_TR15_Msk                  (0x1UL << EXTI_RTSR_TR15_Pos)       /*!< 0x00008000 */
3227 #define EXTI_RTSR_TR15                      EXTI_RTSR_TR15_Msk                 /*!< Rising trigger event configuration bit of line 15 */
3228 #define EXTI_RTSR_TR16_Pos                  (16U)
3229 #define EXTI_RTSR_TR16_Msk                  (0x1UL << EXTI_RTSR_TR16_Pos)       /*!< 0x00010000 */
3230 #define EXTI_RTSR_TR16                      EXTI_RTSR_TR16_Msk                 /*!< Rising trigger event configuration bit of line 16 */
3231 #define EXTI_RTSR_TR17_Pos                  (17U)
3232 #define EXTI_RTSR_TR17_Msk                  (0x1UL << EXTI_RTSR_TR17_Pos)       /*!< 0x00020000 */
3233 #define EXTI_RTSR_TR17                      EXTI_RTSR_TR17_Msk                 /*!< Rising trigger event configuration bit of line 17 */
3234 #define EXTI_RTSR_TR18_Pos                  (18U)
3235 #define EXTI_RTSR_TR18_Msk                  (0x1UL << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */
3236 #define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */
3237 
3238 /* References Defines */
3239 #define  EXTI_RTSR_RT0 EXTI_RTSR_TR0
3240 #define  EXTI_RTSR_RT1 EXTI_RTSR_TR1
3241 #define  EXTI_RTSR_RT2 EXTI_RTSR_TR2
3242 #define  EXTI_RTSR_RT3 EXTI_RTSR_TR3
3243 #define  EXTI_RTSR_RT4 EXTI_RTSR_TR4
3244 #define  EXTI_RTSR_RT5 EXTI_RTSR_TR5
3245 #define  EXTI_RTSR_RT6 EXTI_RTSR_TR6
3246 #define  EXTI_RTSR_RT7 EXTI_RTSR_TR7
3247 #define  EXTI_RTSR_RT8 EXTI_RTSR_TR8
3248 #define  EXTI_RTSR_RT9 EXTI_RTSR_TR9
3249 #define  EXTI_RTSR_RT10 EXTI_RTSR_TR10
3250 #define  EXTI_RTSR_RT11 EXTI_RTSR_TR11
3251 #define  EXTI_RTSR_RT12 EXTI_RTSR_TR12
3252 #define  EXTI_RTSR_RT13 EXTI_RTSR_TR13
3253 #define  EXTI_RTSR_RT14 EXTI_RTSR_TR14
3254 #define  EXTI_RTSR_RT15 EXTI_RTSR_TR15
3255 #define  EXTI_RTSR_RT16 EXTI_RTSR_TR16
3256 #define  EXTI_RTSR_RT17 EXTI_RTSR_TR17
3257 #define  EXTI_RTSR_RT18 EXTI_RTSR_TR18
3258 
3259 /******************  Bit definition for EXTI_FTSR register  *******************/
3260 #define EXTI_FTSR_TR0_Pos                   (0U)
3261 #define EXTI_FTSR_TR0_Msk                   (0x1UL << EXTI_FTSR_TR0_Pos)        /*!< 0x00000001 */
3262 #define EXTI_FTSR_TR0                       EXTI_FTSR_TR0_Msk                  /*!< Falling trigger event configuration bit of line 0 */
3263 #define EXTI_FTSR_TR1_Pos                   (1U)
3264 #define EXTI_FTSR_TR1_Msk                   (0x1UL << EXTI_FTSR_TR1_Pos)        /*!< 0x00000002 */
3265 #define EXTI_FTSR_TR1                       EXTI_FTSR_TR1_Msk                  /*!< Falling trigger event configuration bit of line 1 */
3266 #define EXTI_FTSR_TR2_Pos                   (2U)
3267 #define EXTI_FTSR_TR2_Msk                   (0x1UL << EXTI_FTSR_TR2_Pos)        /*!< 0x00000004 */
3268 #define EXTI_FTSR_TR2                       EXTI_FTSR_TR2_Msk                  /*!< Falling trigger event configuration bit of line 2 */
3269 #define EXTI_FTSR_TR3_Pos                   (3U)
3270 #define EXTI_FTSR_TR3_Msk                   (0x1UL << EXTI_FTSR_TR3_Pos)        /*!< 0x00000008 */
3271 #define EXTI_FTSR_TR3                       EXTI_FTSR_TR3_Msk                  /*!< Falling trigger event configuration bit of line 3 */
3272 #define EXTI_FTSR_TR4_Pos                   (4U)
3273 #define EXTI_FTSR_TR4_Msk                   (0x1UL << EXTI_FTSR_TR4_Pos)        /*!< 0x00000010 */
3274 #define EXTI_FTSR_TR4                       EXTI_FTSR_TR4_Msk                  /*!< Falling trigger event configuration bit of line 4 */
3275 #define EXTI_FTSR_TR5_Pos                   (5U)
3276 #define EXTI_FTSR_TR5_Msk                   (0x1UL << EXTI_FTSR_TR5_Pos)        /*!< 0x00000020 */
3277 #define EXTI_FTSR_TR5                       EXTI_FTSR_TR5_Msk                  /*!< Falling trigger event configuration bit of line 5 */
3278 #define EXTI_FTSR_TR6_Pos                   (6U)
3279 #define EXTI_FTSR_TR6_Msk                   (0x1UL << EXTI_FTSR_TR6_Pos)        /*!< 0x00000040 */
3280 #define EXTI_FTSR_TR6                       EXTI_FTSR_TR6_Msk                  /*!< Falling trigger event configuration bit of line 6 */
3281 #define EXTI_FTSR_TR7_Pos                   (7U)
3282 #define EXTI_FTSR_TR7_Msk                   (0x1UL << EXTI_FTSR_TR7_Pos)        /*!< 0x00000080 */
3283 #define EXTI_FTSR_TR7                       EXTI_FTSR_TR7_Msk                  /*!< Falling trigger event configuration bit of line 7 */
3284 #define EXTI_FTSR_TR8_Pos                   (8U)
3285 #define EXTI_FTSR_TR8_Msk                   (0x1UL << EXTI_FTSR_TR8_Pos)        /*!< 0x00000100 */
3286 #define EXTI_FTSR_TR8                       EXTI_FTSR_TR8_Msk                  /*!< Falling trigger event configuration bit of line 8 */
3287 #define EXTI_FTSR_TR9_Pos                   (9U)
3288 #define EXTI_FTSR_TR9_Msk                   (0x1UL << EXTI_FTSR_TR9_Pos)        /*!< 0x00000200 */
3289 #define EXTI_FTSR_TR9                       EXTI_FTSR_TR9_Msk                  /*!< Falling trigger event configuration bit of line 9 */
3290 #define EXTI_FTSR_TR10_Pos                  (10U)
3291 #define EXTI_FTSR_TR10_Msk                  (0x1UL << EXTI_FTSR_TR10_Pos)       /*!< 0x00000400 */
3292 #define EXTI_FTSR_TR10                      EXTI_FTSR_TR10_Msk                 /*!< Falling trigger event configuration bit of line 10 */
3293 #define EXTI_FTSR_TR11_Pos                  (11U)
3294 #define EXTI_FTSR_TR11_Msk                  (0x1UL << EXTI_FTSR_TR11_Pos)       /*!< 0x00000800 */
3295 #define EXTI_FTSR_TR11                      EXTI_FTSR_TR11_Msk                 /*!< Falling trigger event configuration bit of line 11 */
3296 #define EXTI_FTSR_TR12_Pos                  (12U)
3297 #define EXTI_FTSR_TR12_Msk                  (0x1UL << EXTI_FTSR_TR12_Pos)       /*!< 0x00001000 */
3298 #define EXTI_FTSR_TR12                      EXTI_FTSR_TR12_Msk                 /*!< Falling trigger event configuration bit of line 12 */
3299 #define EXTI_FTSR_TR13_Pos                  (13U)
3300 #define EXTI_FTSR_TR13_Msk                  (0x1UL << EXTI_FTSR_TR13_Pos)       /*!< 0x00002000 */
3301 #define EXTI_FTSR_TR13                      EXTI_FTSR_TR13_Msk                 /*!< Falling trigger event configuration bit of line 13 */
3302 #define EXTI_FTSR_TR14_Pos                  (14U)
3303 #define EXTI_FTSR_TR14_Msk                  (0x1UL << EXTI_FTSR_TR14_Pos)       /*!< 0x00004000 */
3304 #define EXTI_FTSR_TR14                      EXTI_FTSR_TR14_Msk                 /*!< Falling trigger event configuration bit of line 14 */
3305 #define EXTI_FTSR_TR15_Pos                  (15U)
3306 #define EXTI_FTSR_TR15_Msk                  (0x1UL << EXTI_FTSR_TR15_Pos)       /*!< 0x00008000 */
3307 #define EXTI_FTSR_TR15                      EXTI_FTSR_TR15_Msk                 /*!< Falling trigger event configuration bit of line 15 */
3308 #define EXTI_FTSR_TR16_Pos                  (16U)
3309 #define EXTI_FTSR_TR16_Msk                  (0x1UL << EXTI_FTSR_TR16_Pos)       /*!< 0x00010000 */
3310 #define EXTI_FTSR_TR16                      EXTI_FTSR_TR16_Msk                 /*!< Falling trigger event configuration bit of line 16 */
3311 #define EXTI_FTSR_TR17_Pos                  (17U)
3312 #define EXTI_FTSR_TR17_Msk                  (0x1UL << EXTI_FTSR_TR17_Pos)       /*!< 0x00020000 */
3313 #define EXTI_FTSR_TR17                      EXTI_FTSR_TR17_Msk                 /*!< Falling trigger event configuration bit of line 17 */
3314 #define EXTI_FTSR_TR18_Pos                  (18U)
3315 #define EXTI_FTSR_TR18_Msk                  (0x1UL << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */
3316 #define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */
3317 
3318 /* References Defines */
3319 #define  EXTI_FTSR_FT0 EXTI_FTSR_TR0
3320 #define  EXTI_FTSR_FT1 EXTI_FTSR_TR1
3321 #define  EXTI_FTSR_FT2 EXTI_FTSR_TR2
3322 #define  EXTI_FTSR_FT3 EXTI_FTSR_TR3
3323 #define  EXTI_FTSR_FT4 EXTI_FTSR_TR4
3324 #define  EXTI_FTSR_FT5 EXTI_FTSR_TR5
3325 #define  EXTI_FTSR_FT6 EXTI_FTSR_TR6
3326 #define  EXTI_FTSR_FT7 EXTI_FTSR_TR7
3327 #define  EXTI_FTSR_FT8 EXTI_FTSR_TR8
3328 #define  EXTI_FTSR_FT9 EXTI_FTSR_TR9
3329 #define  EXTI_FTSR_FT10 EXTI_FTSR_TR10
3330 #define  EXTI_FTSR_FT11 EXTI_FTSR_TR11
3331 #define  EXTI_FTSR_FT12 EXTI_FTSR_TR12
3332 #define  EXTI_FTSR_FT13 EXTI_FTSR_TR13
3333 #define  EXTI_FTSR_FT14 EXTI_FTSR_TR14
3334 #define  EXTI_FTSR_FT15 EXTI_FTSR_TR15
3335 #define  EXTI_FTSR_FT16 EXTI_FTSR_TR16
3336 #define  EXTI_FTSR_FT17 EXTI_FTSR_TR17
3337 #define  EXTI_FTSR_FT18 EXTI_FTSR_TR18
3338 
3339 /******************  Bit definition for EXTI_SWIER register  ******************/
3340 #define EXTI_SWIER_SWIER0_Pos               (0U)
3341 #define EXTI_SWIER_SWIER0_Msk               (0x1UL << EXTI_SWIER_SWIER0_Pos)    /*!< 0x00000001 */
3342 #define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWIER0_Msk              /*!< Software Interrupt on line 0 */
3343 #define EXTI_SWIER_SWIER1_Pos               (1U)
3344 #define EXTI_SWIER_SWIER1_Msk               (0x1UL << EXTI_SWIER_SWIER1_Pos)    /*!< 0x00000002 */
3345 #define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWIER1_Msk              /*!< Software Interrupt on line 1 */
3346 #define EXTI_SWIER_SWIER2_Pos               (2U)
3347 #define EXTI_SWIER_SWIER2_Msk               (0x1UL << EXTI_SWIER_SWIER2_Pos)    /*!< 0x00000004 */
3348 #define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWIER2_Msk              /*!< Software Interrupt on line 2 */
3349 #define EXTI_SWIER_SWIER3_Pos               (3U)
3350 #define EXTI_SWIER_SWIER3_Msk               (0x1UL << EXTI_SWIER_SWIER3_Pos)    /*!< 0x00000008 */
3351 #define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWIER3_Msk              /*!< Software Interrupt on line 3 */
3352 #define EXTI_SWIER_SWIER4_Pos               (4U)
3353 #define EXTI_SWIER_SWIER4_Msk               (0x1UL << EXTI_SWIER_SWIER4_Pos)    /*!< 0x00000010 */
3354 #define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWIER4_Msk              /*!< Software Interrupt on line 4 */
3355 #define EXTI_SWIER_SWIER5_Pos               (5U)
3356 #define EXTI_SWIER_SWIER5_Msk               (0x1UL << EXTI_SWIER_SWIER5_Pos)    /*!< 0x00000020 */
3357 #define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWIER5_Msk              /*!< Software Interrupt on line 5 */
3358 #define EXTI_SWIER_SWIER6_Pos               (6U)
3359 #define EXTI_SWIER_SWIER6_Msk               (0x1UL << EXTI_SWIER_SWIER6_Pos)    /*!< 0x00000040 */
3360 #define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWIER6_Msk              /*!< Software Interrupt on line 6 */
3361 #define EXTI_SWIER_SWIER7_Pos               (7U)
3362 #define EXTI_SWIER_SWIER7_Msk               (0x1UL << EXTI_SWIER_SWIER7_Pos)    /*!< 0x00000080 */
3363 #define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWIER7_Msk              /*!< Software Interrupt on line 7 */
3364 #define EXTI_SWIER_SWIER8_Pos               (8U)
3365 #define EXTI_SWIER_SWIER8_Msk               (0x1UL << EXTI_SWIER_SWIER8_Pos)    /*!< 0x00000100 */
3366 #define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWIER8_Msk              /*!< Software Interrupt on line 8 */
3367 #define EXTI_SWIER_SWIER9_Pos               (9U)
3368 #define EXTI_SWIER_SWIER9_Msk               (0x1UL << EXTI_SWIER_SWIER9_Pos)    /*!< 0x00000200 */
3369 #define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWIER9_Msk              /*!< Software Interrupt on line 9 */
3370 #define EXTI_SWIER_SWIER10_Pos              (10U)
3371 #define EXTI_SWIER_SWIER10_Msk              (0x1UL << EXTI_SWIER_SWIER10_Pos)   /*!< 0x00000400 */
3372 #define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWIER10_Msk             /*!< Software Interrupt on line 10 */
3373 #define EXTI_SWIER_SWIER11_Pos              (11U)
3374 #define EXTI_SWIER_SWIER11_Msk              (0x1UL << EXTI_SWIER_SWIER11_Pos)   /*!< 0x00000800 */
3375 #define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWIER11_Msk             /*!< Software Interrupt on line 11 */
3376 #define EXTI_SWIER_SWIER12_Pos              (12U)
3377 #define EXTI_SWIER_SWIER12_Msk              (0x1UL << EXTI_SWIER_SWIER12_Pos)   /*!< 0x00001000 */
3378 #define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWIER12_Msk             /*!< Software Interrupt on line 12 */
3379 #define EXTI_SWIER_SWIER13_Pos              (13U)
3380 #define EXTI_SWIER_SWIER13_Msk              (0x1UL << EXTI_SWIER_SWIER13_Pos)   /*!< 0x00002000 */
3381 #define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWIER13_Msk             /*!< Software Interrupt on line 13 */
3382 #define EXTI_SWIER_SWIER14_Pos              (14U)
3383 #define EXTI_SWIER_SWIER14_Msk              (0x1UL << EXTI_SWIER_SWIER14_Pos)   /*!< 0x00004000 */
3384 #define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWIER14_Msk             /*!< Software Interrupt on line 14 */
3385 #define EXTI_SWIER_SWIER15_Pos              (15U)
3386 #define EXTI_SWIER_SWIER15_Msk              (0x1UL << EXTI_SWIER_SWIER15_Pos)   /*!< 0x00008000 */
3387 #define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWIER15_Msk             /*!< Software Interrupt on line 15 */
3388 #define EXTI_SWIER_SWIER16_Pos              (16U)
3389 #define EXTI_SWIER_SWIER16_Msk              (0x1UL << EXTI_SWIER_SWIER16_Pos)   /*!< 0x00010000 */
3390 #define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWIER16_Msk             /*!< Software Interrupt on line 16 */
3391 #define EXTI_SWIER_SWIER17_Pos              (17U)
3392 #define EXTI_SWIER_SWIER17_Msk              (0x1UL << EXTI_SWIER_SWIER17_Pos)   /*!< 0x00020000 */
3393 #define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWIER17_Msk             /*!< Software Interrupt on line 17 */
3394 #define EXTI_SWIER_SWIER18_Pos              (18U)
3395 #define EXTI_SWIER_SWIER18_Msk              (0x1UL << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */
3396 #define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */
3397 
3398 /* References Defines */
3399 #define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
3400 #define  EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
3401 #define  EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
3402 #define  EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
3403 #define  EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
3404 #define  EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
3405 #define  EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
3406 #define  EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
3407 #define  EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
3408 #define  EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
3409 #define  EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
3410 #define  EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
3411 #define  EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
3412 #define  EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
3413 #define  EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
3414 #define  EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
3415 #define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
3416 #define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
3417 #define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
3418 
3419 /*******************  Bit definition for EXTI_PR register  ********************/
3420 #define EXTI_PR_PR0_Pos                     (0U)
3421 #define EXTI_PR_PR0_Msk                     (0x1UL << EXTI_PR_PR0_Pos)          /*!< 0x00000001 */
3422 #define EXTI_PR_PR0                         EXTI_PR_PR0_Msk                    /*!< Pending bit for line 0 */
3423 #define EXTI_PR_PR1_Pos                     (1U)
3424 #define EXTI_PR_PR1_Msk                     (0x1UL << EXTI_PR_PR1_Pos)          /*!< 0x00000002 */
3425 #define EXTI_PR_PR1                         EXTI_PR_PR1_Msk                    /*!< Pending bit for line 1 */
3426 #define EXTI_PR_PR2_Pos                     (2U)
3427 #define EXTI_PR_PR2_Msk                     (0x1UL << EXTI_PR_PR2_Pos)          /*!< 0x00000004 */
3428 #define EXTI_PR_PR2                         EXTI_PR_PR2_Msk                    /*!< Pending bit for line 2 */
3429 #define EXTI_PR_PR3_Pos                     (3U)
3430 #define EXTI_PR_PR3_Msk                     (0x1UL << EXTI_PR_PR3_Pos)          /*!< 0x00000008 */
3431 #define EXTI_PR_PR3                         EXTI_PR_PR3_Msk                    /*!< Pending bit for line 3 */
3432 #define EXTI_PR_PR4_Pos                     (4U)
3433 #define EXTI_PR_PR4_Msk                     (0x1UL << EXTI_PR_PR4_Pos)          /*!< 0x00000010 */
3434 #define EXTI_PR_PR4                         EXTI_PR_PR4_Msk                    /*!< Pending bit for line 4 */
3435 #define EXTI_PR_PR5_Pos                     (5U)
3436 #define EXTI_PR_PR5_Msk                     (0x1UL << EXTI_PR_PR5_Pos)          /*!< 0x00000020 */
3437 #define EXTI_PR_PR5                         EXTI_PR_PR5_Msk                    /*!< Pending bit for line 5 */
3438 #define EXTI_PR_PR6_Pos                     (6U)
3439 #define EXTI_PR_PR6_Msk                     (0x1UL << EXTI_PR_PR6_Pos)          /*!< 0x00000040 */
3440 #define EXTI_PR_PR6                         EXTI_PR_PR6_Msk                    /*!< Pending bit for line 6 */
3441 #define EXTI_PR_PR7_Pos                     (7U)
3442 #define EXTI_PR_PR7_Msk                     (0x1UL << EXTI_PR_PR7_Pos)          /*!< 0x00000080 */
3443 #define EXTI_PR_PR7                         EXTI_PR_PR7_Msk                    /*!< Pending bit for line 7 */
3444 #define EXTI_PR_PR8_Pos                     (8U)
3445 #define EXTI_PR_PR8_Msk                     (0x1UL << EXTI_PR_PR8_Pos)          /*!< 0x00000100 */
3446 #define EXTI_PR_PR8                         EXTI_PR_PR8_Msk                    /*!< Pending bit for line 8 */
3447 #define EXTI_PR_PR9_Pos                     (9U)
3448 #define EXTI_PR_PR9_Msk                     (0x1UL << EXTI_PR_PR9_Pos)          /*!< 0x00000200 */
3449 #define EXTI_PR_PR9                         EXTI_PR_PR9_Msk                    /*!< Pending bit for line 9 */
3450 #define EXTI_PR_PR10_Pos                    (10U)
3451 #define EXTI_PR_PR10_Msk                    (0x1UL << EXTI_PR_PR10_Pos)         /*!< 0x00000400 */
3452 #define EXTI_PR_PR10                        EXTI_PR_PR10_Msk                   /*!< Pending bit for line 10 */
3453 #define EXTI_PR_PR11_Pos                    (11U)
3454 #define EXTI_PR_PR11_Msk                    (0x1UL << EXTI_PR_PR11_Pos)         /*!< 0x00000800 */
3455 #define EXTI_PR_PR11                        EXTI_PR_PR11_Msk                   /*!< Pending bit for line 11 */
3456 #define EXTI_PR_PR12_Pos                    (12U)
3457 #define EXTI_PR_PR12_Msk                    (0x1UL << EXTI_PR_PR12_Pos)         /*!< 0x00001000 */
3458 #define EXTI_PR_PR12                        EXTI_PR_PR12_Msk                   /*!< Pending bit for line 12 */
3459 #define EXTI_PR_PR13_Pos                    (13U)
3460 #define EXTI_PR_PR13_Msk                    (0x1UL << EXTI_PR_PR13_Pos)         /*!< 0x00002000 */
3461 #define EXTI_PR_PR13                        EXTI_PR_PR13_Msk                   /*!< Pending bit for line 13 */
3462 #define EXTI_PR_PR14_Pos                    (14U)
3463 #define EXTI_PR_PR14_Msk                    (0x1UL << EXTI_PR_PR14_Pos)         /*!< 0x00004000 */
3464 #define EXTI_PR_PR14                        EXTI_PR_PR14_Msk                   /*!< Pending bit for line 14 */
3465 #define EXTI_PR_PR15_Pos                    (15U)
3466 #define EXTI_PR_PR15_Msk                    (0x1UL << EXTI_PR_PR15_Pos)         /*!< 0x00008000 */
3467 #define EXTI_PR_PR15                        EXTI_PR_PR15_Msk                   /*!< Pending bit for line 15 */
3468 #define EXTI_PR_PR16_Pos                    (16U)
3469 #define EXTI_PR_PR16_Msk                    (0x1UL << EXTI_PR_PR16_Pos)         /*!< 0x00010000 */
3470 #define EXTI_PR_PR16                        EXTI_PR_PR16_Msk                   /*!< Pending bit for line 16 */
3471 #define EXTI_PR_PR17_Pos                    (17U)
3472 #define EXTI_PR_PR17_Msk                    (0x1UL << EXTI_PR_PR17_Pos)         /*!< 0x00020000 */
3473 #define EXTI_PR_PR17                        EXTI_PR_PR17_Msk                   /*!< Pending bit for line 17 */
3474 #define EXTI_PR_PR18_Pos                    (18U)
3475 #define EXTI_PR_PR18_Msk                    (0x1UL << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */
3476 #define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */
3477 
3478 /* References Defines */
3479 #define  EXTI_PR_PIF0 EXTI_PR_PR0
3480 #define  EXTI_PR_PIF1 EXTI_PR_PR1
3481 #define  EXTI_PR_PIF2 EXTI_PR_PR2
3482 #define  EXTI_PR_PIF3 EXTI_PR_PR3
3483 #define  EXTI_PR_PIF4 EXTI_PR_PR4
3484 #define  EXTI_PR_PIF5 EXTI_PR_PR5
3485 #define  EXTI_PR_PIF6 EXTI_PR_PR6
3486 #define  EXTI_PR_PIF7 EXTI_PR_PR7
3487 #define  EXTI_PR_PIF8 EXTI_PR_PR8
3488 #define  EXTI_PR_PIF9 EXTI_PR_PR9
3489 #define  EXTI_PR_PIF10 EXTI_PR_PR10
3490 #define  EXTI_PR_PIF11 EXTI_PR_PR11
3491 #define  EXTI_PR_PIF12 EXTI_PR_PR12
3492 #define  EXTI_PR_PIF13 EXTI_PR_PR13
3493 #define  EXTI_PR_PIF14 EXTI_PR_PR14
3494 #define  EXTI_PR_PIF15 EXTI_PR_PR15
3495 #define  EXTI_PR_PIF16 EXTI_PR_PR16
3496 #define  EXTI_PR_PIF17 EXTI_PR_PR17
3497 #define  EXTI_PR_PIF18 EXTI_PR_PR18
3498 
3499 /******************************************************************************/
3500 /*                                                                            */
3501 /*                             DMA Controller                                 */
3502 /*                                                                            */
3503 /******************************************************************************/
3504 
3505 /*******************  Bit definition for DMA_ISR register  ********************/
3506 #define DMA_ISR_GIF1_Pos                    (0U)
3507 #define DMA_ISR_GIF1_Msk                    (0x1UL << DMA_ISR_GIF1_Pos)         /*!< 0x00000001 */
3508 #define DMA_ISR_GIF1                        DMA_ISR_GIF1_Msk                   /*!< Channel 1 Global interrupt flag */
3509 #define DMA_ISR_TCIF1_Pos                   (1U)
3510 #define DMA_ISR_TCIF1_Msk                   (0x1UL << DMA_ISR_TCIF1_Pos)        /*!< 0x00000002 */
3511 #define DMA_ISR_TCIF1                       DMA_ISR_TCIF1_Msk                  /*!< Channel 1 Transfer Complete flag */
3512 #define DMA_ISR_HTIF1_Pos                   (2U)
3513 #define DMA_ISR_HTIF1_Msk                   (0x1UL << DMA_ISR_HTIF1_Pos)        /*!< 0x00000004 */
3514 #define DMA_ISR_HTIF1                       DMA_ISR_HTIF1_Msk                  /*!< Channel 1 Half Transfer flag */
3515 #define DMA_ISR_TEIF1_Pos                   (3U)
3516 #define DMA_ISR_TEIF1_Msk                   (0x1UL << DMA_ISR_TEIF1_Pos)        /*!< 0x00000008 */
3517 #define DMA_ISR_TEIF1                       DMA_ISR_TEIF1_Msk                  /*!< Channel 1 Transfer Error flag */
3518 #define DMA_ISR_GIF2_Pos                    (4U)
3519 #define DMA_ISR_GIF2_Msk                    (0x1UL << DMA_ISR_GIF2_Pos)         /*!< 0x00000010 */
3520 #define DMA_ISR_GIF2                        DMA_ISR_GIF2_Msk                   /*!< Channel 2 Global interrupt flag */
3521 #define DMA_ISR_TCIF2_Pos                   (5U)
3522 #define DMA_ISR_TCIF2_Msk                   (0x1UL << DMA_ISR_TCIF2_Pos)        /*!< 0x00000020 */
3523 #define DMA_ISR_TCIF2                       DMA_ISR_TCIF2_Msk                  /*!< Channel 2 Transfer Complete flag */
3524 #define DMA_ISR_HTIF2_Pos                   (6U)
3525 #define DMA_ISR_HTIF2_Msk                   (0x1UL << DMA_ISR_HTIF2_Pos)        /*!< 0x00000040 */
3526 #define DMA_ISR_HTIF2                       DMA_ISR_HTIF2_Msk                  /*!< Channel 2 Half Transfer flag */
3527 #define DMA_ISR_TEIF2_Pos                   (7U)
3528 #define DMA_ISR_TEIF2_Msk                   (0x1UL << DMA_ISR_TEIF2_Pos)        /*!< 0x00000080 */
3529 #define DMA_ISR_TEIF2                       DMA_ISR_TEIF2_Msk                  /*!< Channel 2 Transfer Error flag */
3530 #define DMA_ISR_GIF3_Pos                    (8U)
3531 #define DMA_ISR_GIF3_Msk                    (0x1UL << DMA_ISR_GIF3_Pos)         /*!< 0x00000100 */
3532 #define DMA_ISR_GIF3                        DMA_ISR_GIF3_Msk                   /*!< Channel 3 Global interrupt flag */
3533 #define DMA_ISR_TCIF3_Pos                   (9U)
3534 #define DMA_ISR_TCIF3_Msk                   (0x1UL << DMA_ISR_TCIF3_Pos)        /*!< 0x00000200 */
3535 #define DMA_ISR_TCIF3                       DMA_ISR_TCIF3_Msk                  /*!< Channel 3 Transfer Complete flag */
3536 #define DMA_ISR_HTIF3_Pos                   (10U)
3537 #define DMA_ISR_HTIF3_Msk                   (0x1UL << DMA_ISR_HTIF3_Pos)        /*!< 0x00000400 */
3538 #define DMA_ISR_HTIF3                       DMA_ISR_HTIF3_Msk                  /*!< Channel 3 Half Transfer flag */
3539 #define DMA_ISR_TEIF3_Pos                   (11U)
3540 #define DMA_ISR_TEIF3_Msk                   (0x1UL << DMA_ISR_TEIF3_Pos)        /*!< 0x00000800 */
3541 #define DMA_ISR_TEIF3                       DMA_ISR_TEIF3_Msk                  /*!< Channel 3 Transfer Error flag */
3542 #define DMA_ISR_GIF4_Pos                    (12U)
3543 #define DMA_ISR_GIF4_Msk                    (0x1UL << DMA_ISR_GIF4_Pos)         /*!< 0x00001000 */
3544 #define DMA_ISR_GIF4                        DMA_ISR_GIF4_Msk                   /*!< Channel 4 Global interrupt flag */
3545 #define DMA_ISR_TCIF4_Pos                   (13U)
3546 #define DMA_ISR_TCIF4_Msk                   (0x1UL << DMA_ISR_TCIF4_Pos)        /*!< 0x00002000 */
3547 #define DMA_ISR_TCIF4                       DMA_ISR_TCIF4_Msk                  /*!< Channel 4 Transfer Complete flag */
3548 #define DMA_ISR_HTIF4_Pos                   (14U)
3549 #define DMA_ISR_HTIF4_Msk                   (0x1UL << DMA_ISR_HTIF4_Pos)        /*!< 0x00004000 */
3550 #define DMA_ISR_HTIF4                       DMA_ISR_HTIF4_Msk                  /*!< Channel 4 Half Transfer flag */
3551 #define DMA_ISR_TEIF4_Pos                   (15U)
3552 #define DMA_ISR_TEIF4_Msk                   (0x1UL << DMA_ISR_TEIF4_Pos)        /*!< 0x00008000 */
3553 #define DMA_ISR_TEIF4                       DMA_ISR_TEIF4_Msk                  /*!< Channel 4 Transfer Error flag */
3554 #define DMA_ISR_GIF5_Pos                    (16U)
3555 #define DMA_ISR_GIF5_Msk                    (0x1UL << DMA_ISR_GIF5_Pos)         /*!< 0x00010000 */
3556 #define DMA_ISR_GIF5                        DMA_ISR_GIF5_Msk                   /*!< Channel 5 Global interrupt flag */
3557 #define DMA_ISR_TCIF5_Pos                   (17U)
3558 #define DMA_ISR_TCIF5_Msk                   (0x1UL << DMA_ISR_TCIF5_Pos)        /*!< 0x00020000 */
3559 #define DMA_ISR_TCIF5                       DMA_ISR_TCIF5_Msk                  /*!< Channel 5 Transfer Complete flag */
3560 #define DMA_ISR_HTIF5_Pos                   (18U)
3561 #define DMA_ISR_HTIF5_Msk                   (0x1UL << DMA_ISR_HTIF5_Pos)        /*!< 0x00040000 */
3562 #define DMA_ISR_HTIF5                       DMA_ISR_HTIF5_Msk                  /*!< Channel 5 Half Transfer flag */
3563 #define DMA_ISR_TEIF5_Pos                   (19U)
3564 #define DMA_ISR_TEIF5_Msk                   (0x1UL << DMA_ISR_TEIF5_Pos)        /*!< 0x00080000 */
3565 #define DMA_ISR_TEIF5                       DMA_ISR_TEIF5_Msk                  /*!< Channel 5 Transfer Error flag */
3566 #define DMA_ISR_GIF6_Pos                    (20U)
3567 #define DMA_ISR_GIF6_Msk                    (0x1UL << DMA_ISR_GIF6_Pos)         /*!< 0x00100000 */
3568 #define DMA_ISR_GIF6                        DMA_ISR_GIF6_Msk                   /*!< Channel 6 Global interrupt flag */
3569 #define DMA_ISR_TCIF6_Pos                   (21U)
3570 #define DMA_ISR_TCIF6_Msk                   (0x1UL << DMA_ISR_TCIF6_Pos)        /*!< 0x00200000 */
3571 #define DMA_ISR_TCIF6                       DMA_ISR_TCIF6_Msk                  /*!< Channel 6 Transfer Complete flag */
3572 #define DMA_ISR_HTIF6_Pos                   (22U)
3573 #define DMA_ISR_HTIF6_Msk                   (0x1UL << DMA_ISR_HTIF6_Pos)        /*!< 0x00400000 */
3574 #define DMA_ISR_HTIF6                       DMA_ISR_HTIF6_Msk                  /*!< Channel 6 Half Transfer flag */
3575 #define DMA_ISR_TEIF6_Pos                   (23U)
3576 #define DMA_ISR_TEIF6_Msk                   (0x1UL << DMA_ISR_TEIF6_Pos)        /*!< 0x00800000 */
3577 #define DMA_ISR_TEIF6                       DMA_ISR_TEIF6_Msk                  /*!< Channel 6 Transfer Error flag */
3578 #define DMA_ISR_GIF7_Pos                    (24U)
3579 #define DMA_ISR_GIF7_Msk                    (0x1UL << DMA_ISR_GIF7_Pos)         /*!< 0x01000000 */
3580 #define DMA_ISR_GIF7                        DMA_ISR_GIF7_Msk                   /*!< Channel 7 Global interrupt flag */
3581 #define DMA_ISR_TCIF7_Pos                   (25U)
3582 #define DMA_ISR_TCIF7_Msk                   (0x1UL << DMA_ISR_TCIF7_Pos)        /*!< 0x02000000 */
3583 #define DMA_ISR_TCIF7                       DMA_ISR_TCIF7_Msk                  /*!< Channel 7 Transfer Complete flag */
3584 #define DMA_ISR_HTIF7_Pos                   (26U)
3585 #define DMA_ISR_HTIF7_Msk                   (0x1UL << DMA_ISR_HTIF7_Pos)        /*!< 0x04000000 */
3586 #define DMA_ISR_HTIF7                       DMA_ISR_HTIF7_Msk                  /*!< Channel 7 Half Transfer flag */
3587 #define DMA_ISR_TEIF7_Pos                   (27U)
3588 #define DMA_ISR_TEIF7_Msk                   (0x1UL << DMA_ISR_TEIF7_Pos)        /*!< 0x08000000 */
3589 #define DMA_ISR_TEIF7                       DMA_ISR_TEIF7_Msk                  /*!< Channel 7 Transfer Error flag */
3590 
3591 /*******************  Bit definition for DMA_IFCR register  *******************/
3592 #define DMA_IFCR_CGIF1_Pos                  (0U)
3593 #define DMA_IFCR_CGIF1_Msk                  (0x1UL << DMA_IFCR_CGIF1_Pos)       /*!< 0x00000001 */
3594 #define DMA_IFCR_CGIF1                      DMA_IFCR_CGIF1_Msk                 /*!< Channel 1 Global interrupt clear */
3595 #define DMA_IFCR_CTCIF1_Pos                 (1U)
3596 #define DMA_IFCR_CTCIF1_Msk                 (0x1UL << DMA_IFCR_CTCIF1_Pos)      /*!< 0x00000002 */
3597 #define DMA_IFCR_CTCIF1                     DMA_IFCR_CTCIF1_Msk                /*!< Channel 1 Transfer Complete clear */
3598 #define DMA_IFCR_CHTIF1_Pos                 (2U)
3599 #define DMA_IFCR_CHTIF1_Msk                 (0x1UL << DMA_IFCR_CHTIF1_Pos)      /*!< 0x00000004 */
3600 #define DMA_IFCR_CHTIF1                     DMA_IFCR_CHTIF1_Msk                /*!< Channel 1 Half Transfer clear */
3601 #define DMA_IFCR_CTEIF1_Pos                 (3U)
3602 #define DMA_IFCR_CTEIF1_Msk                 (0x1UL << DMA_IFCR_CTEIF1_Pos)      /*!< 0x00000008 */
3603 #define DMA_IFCR_CTEIF1                     DMA_IFCR_CTEIF1_Msk                /*!< Channel 1 Transfer Error clear */
3604 #define DMA_IFCR_CGIF2_Pos                  (4U)
3605 #define DMA_IFCR_CGIF2_Msk                  (0x1UL << DMA_IFCR_CGIF2_Pos)       /*!< 0x00000010 */
3606 #define DMA_IFCR_CGIF2                      DMA_IFCR_CGIF2_Msk                 /*!< Channel 2 Global interrupt clear */
3607 #define DMA_IFCR_CTCIF2_Pos                 (5U)
3608 #define DMA_IFCR_CTCIF2_Msk                 (0x1UL << DMA_IFCR_CTCIF2_Pos)      /*!< 0x00000020 */
3609 #define DMA_IFCR_CTCIF2                     DMA_IFCR_CTCIF2_Msk                /*!< Channel 2 Transfer Complete clear */
3610 #define DMA_IFCR_CHTIF2_Pos                 (6U)
3611 #define DMA_IFCR_CHTIF2_Msk                 (0x1UL << DMA_IFCR_CHTIF2_Pos)      /*!< 0x00000040 */
3612 #define DMA_IFCR_CHTIF2                     DMA_IFCR_CHTIF2_Msk                /*!< Channel 2 Half Transfer clear */
3613 #define DMA_IFCR_CTEIF2_Pos                 (7U)
3614 #define DMA_IFCR_CTEIF2_Msk                 (0x1UL << DMA_IFCR_CTEIF2_Pos)      /*!< 0x00000080 */
3615 #define DMA_IFCR_CTEIF2                     DMA_IFCR_CTEIF2_Msk                /*!< Channel 2 Transfer Error clear */
3616 #define DMA_IFCR_CGIF3_Pos                  (8U)
3617 #define DMA_IFCR_CGIF3_Msk                  (0x1UL << DMA_IFCR_CGIF3_Pos)       /*!< 0x00000100 */
3618 #define DMA_IFCR_CGIF3                      DMA_IFCR_CGIF3_Msk                 /*!< Channel 3 Global interrupt clear */
3619 #define DMA_IFCR_CTCIF3_Pos                 (9U)
3620 #define DMA_IFCR_CTCIF3_Msk                 (0x1UL << DMA_IFCR_CTCIF3_Pos)      /*!< 0x00000200 */
3621 #define DMA_IFCR_CTCIF3                     DMA_IFCR_CTCIF3_Msk                /*!< Channel 3 Transfer Complete clear */
3622 #define DMA_IFCR_CHTIF3_Pos                 (10U)
3623 #define DMA_IFCR_CHTIF3_Msk                 (0x1UL << DMA_IFCR_CHTIF3_Pos)      /*!< 0x00000400 */
3624 #define DMA_IFCR_CHTIF3                     DMA_IFCR_CHTIF3_Msk                /*!< Channel 3 Half Transfer clear */
3625 #define DMA_IFCR_CTEIF3_Pos                 (11U)
3626 #define DMA_IFCR_CTEIF3_Msk                 (0x1UL << DMA_IFCR_CTEIF3_Pos)      /*!< 0x00000800 */
3627 #define DMA_IFCR_CTEIF3                     DMA_IFCR_CTEIF3_Msk                /*!< Channel 3 Transfer Error clear */
3628 #define DMA_IFCR_CGIF4_Pos                  (12U)
3629 #define DMA_IFCR_CGIF4_Msk                  (0x1UL << DMA_IFCR_CGIF4_Pos)       /*!< 0x00001000 */
3630 #define DMA_IFCR_CGIF4                      DMA_IFCR_CGIF4_Msk                 /*!< Channel 4 Global interrupt clear */
3631 #define DMA_IFCR_CTCIF4_Pos                 (13U)
3632 #define DMA_IFCR_CTCIF4_Msk                 (0x1UL << DMA_IFCR_CTCIF4_Pos)      /*!< 0x00002000 */
3633 #define DMA_IFCR_CTCIF4                     DMA_IFCR_CTCIF4_Msk                /*!< Channel 4 Transfer Complete clear */
3634 #define DMA_IFCR_CHTIF4_Pos                 (14U)
3635 #define DMA_IFCR_CHTIF4_Msk                 (0x1UL << DMA_IFCR_CHTIF4_Pos)      /*!< 0x00004000 */
3636 #define DMA_IFCR_CHTIF4                     DMA_IFCR_CHTIF4_Msk                /*!< Channel 4 Half Transfer clear */
3637 #define DMA_IFCR_CTEIF4_Pos                 (15U)
3638 #define DMA_IFCR_CTEIF4_Msk                 (0x1UL << DMA_IFCR_CTEIF4_Pos)      /*!< 0x00008000 */
3639 #define DMA_IFCR_CTEIF4                     DMA_IFCR_CTEIF4_Msk                /*!< Channel 4 Transfer Error clear */
3640 #define DMA_IFCR_CGIF5_Pos                  (16U)
3641 #define DMA_IFCR_CGIF5_Msk                  (0x1UL << DMA_IFCR_CGIF5_Pos)       /*!< 0x00010000 */
3642 #define DMA_IFCR_CGIF5                      DMA_IFCR_CGIF5_Msk                 /*!< Channel 5 Global interrupt clear */
3643 #define DMA_IFCR_CTCIF5_Pos                 (17U)
3644 #define DMA_IFCR_CTCIF5_Msk                 (0x1UL << DMA_IFCR_CTCIF5_Pos)      /*!< 0x00020000 */
3645 #define DMA_IFCR_CTCIF5                     DMA_IFCR_CTCIF5_Msk                /*!< Channel 5 Transfer Complete clear */
3646 #define DMA_IFCR_CHTIF5_Pos                 (18U)
3647 #define DMA_IFCR_CHTIF5_Msk                 (0x1UL << DMA_IFCR_CHTIF5_Pos)      /*!< 0x00040000 */
3648 #define DMA_IFCR_CHTIF5                     DMA_IFCR_CHTIF5_Msk                /*!< Channel 5 Half Transfer clear */
3649 #define DMA_IFCR_CTEIF5_Pos                 (19U)
3650 #define DMA_IFCR_CTEIF5_Msk                 (0x1UL << DMA_IFCR_CTEIF5_Pos)      /*!< 0x00080000 */
3651 #define DMA_IFCR_CTEIF5                     DMA_IFCR_CTEIF5_Msk                /*!< Channel 5 Transfer Error clear */
3652 #define DMA_IFCR_CGIF6_Pos                  (20U)
3653 #define DMA_IFCR_CGIF6_Msk                  (0x1UL << DMA_IFCR_CGIF6_Pos)       /*!< 0x00100000 */
3654 #define DMA_IFCR_CGIF6                      DMA_IFCR_CGIF6_Msk                 /*!< Channel 6 Global interrupt clear */
3655 #define DMA_IFCR_CTCIF6_Pos                 (21U)
3656 #define DMA_IFCR_CTCIF6_Msk                 (0x1UL << DMA_IFCR_CTCIF6_Pos)      /*!< 0x00200000 */
3657 #define DMA_IFCR_CTCIF6                     DMA_IFCR_CTCIF6_Msk                /*!< Channel 6 Transfer Complete clear */
3658 #define DMA_IFCR_CHTIF6_Pos                 (22U)
3659 #define DMA_IFCR_CHTIF6_Msk                 (0x1UL << DMA_IFCR_CHTIF6_Pos)      /*!< 0x00400000 */
3660 #define DMA_IFCR_CHTIF6                     DMA_IFCR_CHTIF6_Msk                /*!< Channel 6 Half Transfer clear */
3661 #define DMA_IFCR_CTEIF6_Pos                 (23U)
3662 #define DMA_IFCR_CTEIF6_Msk                 (0x1UL << DMA_IFCR_CTEIF6_Pos)      /*!< 0x00800000 */
3663 #define DMA_IFCR_CTEIF6                     DMA_IFCR_CTEIF6_Msk                /*!< Channel 6 Transfer Error clear */
3664 #define DMA_IFCR_CGIF7_Pos                  (24U)
3665 #define DMA_IFCR_CGIF7_Msk                  (0x1UL << DMA_IFCR_CGIF7_Pos)       /*!< 0x01000000 */
3666 #define DMA_IFCR_CGIF7                      DMA_IFCR_CGIF7_Msk                 /*!< Channel 7 Global interrupt clear */
3667 #define DMA_IFCR_CTCIF7_Pos                 (25U)
3668 #define DMA_IFCR_CTCIF7_Msk                 (0x1UL << DMA_IFCR_CTCIF7_Pos)      /*!< 0x02000000 */
3669 #define DMA_IFCR_CTCIF7                     DMA_IFCR_CTCIF7_Msk                /*!< Channel 7 Transfer Complete clear */
3670 #define DMA_IFCR_CHTIF7_Pos                 (26U)
3671 #define DMA_IFCR_CHTIF7_Msk                 (0x1UL << DMA_IFCR_CHTIF7_Pos)      /*!< 0x04000000 */
3672 #define DMA_IFCR_CHTIF7                     DMA_IFCR_CHTIF7_Msk                /*!< Channel 7 Half Transfer clear */
3673 #define DMA_IFCR_CTEIF7_Pos                 (27U)
3674 #define DMA_IFCR_CTEIF7_Msk                 (0x1UL << DMA_IFCR_CTEIF7_Pos)      /*!< 0x08000000 */
3675 #define DMA_IFCR_CTEIF7                     DMA_IFCR_CTEIF7_Msk                /*!< Channel 7 Transfer Error clear */
3676 
3677 /*******************  Bit definition for DMA_CCR register   *******************/
3678 #define DMA_CCR_EN_Pos                      (0U)
3679 #define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)           /*!< 0x00000001 */
3680 #define DMA_CCR_EN                          DMA_CCR_EN_Msk                     /*!< Channel enable */
3681 #define DMA_CCR_TCIE_Pos                    (1U)
3682 #define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)         /*!< 0x00000002 */
3683 #define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                   /*!< Transfer complete interrupt enable */
3684 #define DMA_CCR_HTIE_Pos                    (2U)
3685 #define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)         /*!< 0x00000004 */
3686 #define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                   /*!< Half Transfer interrupt enable */
3687 #define DMA_CCR_TEIE_Pos                    (3U)
3688 #define DMA_CCR_TEIE_Msk                    (0x1UL << DMA_CCR_TEIE_Pos)         /*!< 0x00000008 */
3689 #define DMA_CCR_TEIE                        DMA_CCR_TEIE_Msk                   /*!< Transfer error interrupt enable */
3690 #define DMA_CCR_DIR_Pos                     (4U)
3691 #define DMA_CCR_DIR_Msk                     (0x1UL << DMA_CCR_DIR_Pos)          /*!< 0x00000010 */
3692 #define DMA_CCR_DIR                         DMA_CCR_DIR_Msk                    /*!< Data transfer direction */
3693 #define DMA_CCR_CIRC_Pos                    (5U)
3694 #define DMA_CCR_CIRC_Msk                    (0x1UL << DMA_CCR_CIRC_Pos)         /*!< 0x00000020 */
3695 #define DMA_CCR_CIRC                        DMA_CCR_CIRC_Msk                   /*!< Circular mode */
3696 #define DMA_CCR_PINC_Pos                    (6U)
3697 #define DMA_CCR_PINC_Msk                    (0x1UL << DMA_CCR_PINC_Pos)         /*!< 0x00000040 */
3698 #define DMA_CCR_PINC                        DMA_CCR_PINC_Msk                   /*!< Peripheral increment mode */
3699 #define DMA_CCR_MINC_Pos                    (7U)
3700 #define DMA_CCR_MINC_Msk                    (0x1UL << DMA_CCR_MINC_Pos)         /*!< 0x00000080 */
3701 #define DMA_CCR_MINC                        DMA_CCR_MINC_Msk                   /*!< Memory increment mode */
3702 
3703 #define DMA_CCR_PSIZE_Pos                   (8U)
3704 #define DMA_CCR_PSIZE_Msk                   (0x3UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000300 */
3705 #define DMA_CCR_PSIZE                       DMA_CCR_PSIZE_Msk                  /*!< PSIZE[1:0] bits (Peripheral size) */
3706 #define DMA_CCR_PSIZE_0                     (0x1UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000100 */
3707 #define DMA_CCR_PSIZE_1                     (0x2UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000200 */
3708 
3709 #define DMA_CCR_MSIZE_Pos                   (10U)
3710 #define DMA_CCR_MSIZE_Msk                   (0x3UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000C00 */
3711 #define DMA_CCR_MSIZE                       DMA_CCR_MSIZE_Msk                  /*!< MSIZE[1:0] bits (Memory size) */
3712 #define DMA_CCR_MSIZE_0                     (0x1UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000400 */
3713 #define DMA_CCR_MSIZE_1                     (0x2UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000800 */
3714 
3715 #define DMA_CCR_PL_Pos                      (12U)
3716 #define DMA_CCR_PL_Msk                      (0x3UL << DMA_CCR_PL_Pos)           /*!< 0x00003000 */
3717 #define DMA_CCR_PL                          DMA_CCR_PL_Msk                     /*!< PL[1:0] bits(Channel Priority level) */
3718 #define DMA_CCR_PL_0                        (0x1UL << DMA_CCR_PL_Pos)           /*!< 0x00001000 */
3719 #define DMA_CCR_PL_1                        (0x2UL << DMA_CCR_PL_Pos)           /*!< 0x00002000 */
3720 
3721 #define DMA_CCR_MEM2MEM_Pos                 (14U)
3722 #define DMA_CCR_MEM2MEM_Msk                 (0x1UL << DMA_CCR_MEM2MEM_Pos)      /*!< 0x00004000 */
3723 #define DMA_CCR_MEM2MEM                     DMA_CCR_MEM2MEM_Msk                /*!< Memory to memory mode */
3724 
3725 /******************  Bit definition for DMA_CNDTR  register  ******************/
3726 #define DMA_CNDTR_NDT_Pos                   (0U)
3727 #define DMA_CNDTR_NDT_Msk                   (0xFFFFUL << DMA_CNDTR_NDT_Pos)     /*!< 0x0000FFFF */
3728 #define DMA_CNDTR_NDT                       DMA_CNDTR_NDT_Msk                  /*!< Number of data to Transfer */
3729 
3730 /******************  Bit definition for DMA_CPAR  register  *******************/
3731 #define DMA_CPAR_PA_Pos                     (0U)
3732 #define DMA_CPAR_PA_Msk                     (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)   /*!< 0xFFFFFFFF */
3733 #define DMA_CPAR_PA                         DMA_CPAR_PA_Msk                    /*!< Peripheral Address */
3734 
3735 /******************  Bit definition for DMA_CMAR  register  *******************/
3736 #define DMA_CMAR_MA_Pos                     (0U)
3737 #define DMA_CMAR_MA_Msk                     (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)   /*!< 0xFFFFFFFF */
3738 #define DMA_CMAR_MA                         DMA_CMAR_MA_Msk                    /*!< Memory Address */
3739 
3740 /******************************************************************************/
3741 /*                                                                            */
3742 /*                      Analog to Digital Converter (ADC)                     */
3743 /*                                                                            */
3744 /******************************************************************************/
3745 
3746 /*
3747  * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
3748  */
3749 #define ADC_MULTIMODE_SUPPORT                          /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
3750 
3751 /********************  Bit definition for ADC_SR register  ********************/
3752 #define ADC_SR_AWD_Pos                      (0U)
3753 #define ADC_SR_AWD_Msk                      (0x1UL << ADC_SR_AWD_Pos)           /*!< 0x00000001 */
3754 #define ADC_SR_AWD                          ADC_SR_AWD_Msk                     /*!< ADC analog watchdog 1 flag */
3755 #define ADC_SR_EOS_Pos                      (1U)
3756 #define ADC_SR_EOS_Msk                      (0x1UL << ADC_SR_EOS_Pos)           /*!< 0x00000002 */
3757 #define ADC_SR_EOS                          ADC_SR_EOS_Msk                     /*!< ADC group regular end of sequence conversions flag */
3758 #define ADC_SR_JEOS_Pos                     (2U)
3759 #define ADC_SR_JEOS_Msk                     (0x1UL << ADC_SR_JEOS_Pos)          /*!< 0x00000004 */
3760 #define ADC_SR_JEOS                         ADC_SR_JEOS_Msk                    /*!< ADC group injected end of sequence conversions flag */
3761 #define ADC_SR_JSTRT_Pos                    (3U)
3762 #define ADC_SR_JSTRT_Msk                    (0x1UL << ADC_SR_JSTRT_Pos)         /*!< 0x00000008 */
3763 #define ADC_SR_JSTRT                        ADC_SR_JSTRT_Msk                   /*!< ADC group injected conversion start flag */
3764 #define ADC_SR_STRT_Pos                     (4U)
3765 #define ADC_SR_STRT_Msk                     (0x1UL << ADC_SR_STRT_Pos)          /*!< 0x00000010 */
3766 #define ADC_SR_STRT                         ADC_SR_STRT_Msk                    /*!< ADC group regular conversion start flag */
3767 
3768 /* Legacy defines */
3769 #define  ADC_SR_EOC                          (ADC_SR_EOS)
3770 #define  ADC_SR_JEOC                         (ADC_SR_JEOS)
3771 
3772 /*******************  Bit definition for ADC_CR1 register  ********************/
3773 #define ADC_CR1_AWDCH_Pos                   (0U)
3774 #define ADC_CR1_AWDCH_Msk                   (0x1FUL << ADC_CR1_AWDCH_Pos)       /*!< 0x0000001F */
3775 #define ADC_CR1_AWDCH                       ADC_CR1_AWDCH_Msk                  /*!< ADC analog watchdog 1 monitored channel selection */
3776 #define ADC_CR1_AWDCH_0                     (0x01UL << ADC_CR1_AWDCH_Pos)       /*!< 0x00000001 */
3777 #define ADC_CR1_AWDCH_1                     (0x02UL << ADC_CR1_AWDCH_Pos)       /*!< 0x00000002 */
3778 #define ADC_CR1_AWDCH_2                     (0x04UL << ADC_CR1_AWDCH_Pos)       /*!< 0x00000004 */
3779 #define ADC_CR1_AWDCH_3                     (0x08UL << ADC_CR1_AWDCH_Pos)       /*!< 0x00000008 */
3780 #define ADC_CR1_AWDCH_4                     (0x10UL << ADC_CR1_AWDCH_Pos)       /*!< 0x00000010 */
3781 
3782 #define ADC_CR1_EOSIE_Pos                   (5U)
3783 #define ADC_CR1_EOSIE_Msk                   (0x1UL << ADC_CR1_EOSIE_Pos)        /*!< 0x00000020 */
3784 #define ADC_CR1_EOSIE                       ADC_CR1_EOSIE_Msk                  /*!< ADC group regular end of sequence conversions interrupt */
3785 #define ADC_CR1_AWDIE_Pos                   (6U)
3786 #define ADC_CR1_AWDIE_Msk                   (0x1UL << ADC_CR1_AWDIE_Pos)        /*!< 0x00000040 */
3787 #define ADC_CR1_AWDIE                       ADC_CR1_AWDIE_Msk                  /*!< ADC analog watchdog 1 interrupt */
3788 #define ADC_CR1_JEOSIE_Pos                  (7U)
3789 #define ADC_CR1_JEOSIE_Msk                  (0x1UL << ADC_CR1_JEOSIE_Pos)       /*!< 0x00000080 */
3790 #define ADC_CR1_JEOSIE                      ADC_CR1_JEOSIE_Msk                 /*!< ADC group injected end of sequence conversions interrupt */
3791 #define ADC_CR1_SCAN_Pos                    (8U)
3792 #define ADC_CR1_SCAN_Msk                    (0x1UL << ADC_CR1_SCAN_Pos)         /*!< 0x00000100 */
3793 #define ADC_CR1_SCAN                        ADC_CR1_SCAN_Msk                   /*!< ADC scan mode */
3794 #define ADC_CR1_AWDSGL_Pos                  (9U)
3795 #define ADC_CR1_AWDSGL_Msk                  (0x1UL << ADC_CR1_AWDSGL_Pos)       /*!< 0x00000200 */
3796 #define ADC_CR1_AWDSGL                      ADC_CR1_AWDSGL_Msk                 /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
3797 #define ADC_CR1_JAUTO_Pos                   (10U)
3798 #define ADC_CR1_JAUTO_Msk                   (0x1UL << ADC_CR1_JAUTO_Pos)        /*!< 0x00000400 */
3799 #define ADC_CR1_JAUTO                       ADC_CR1_JAUTO_Msk                  /*!< ADC group injected automatic trigger mode */
3800 #define ADC_CR1_DISCEN_Pos                  (11U)
3801 #define ADC_CR1_DISCEN_Msk                  (0x1UL << ADC_CR1_DISCEN_Pos)       /*!< 0x00000800 */
3802 #define ADC_CR1_DISCEN                      ADC_CR1_DISCEN_Msk                 /*!< ADC group regular sequencer discontinuous mode */
3803 #define ADC_CR1_JDISCEN_Pos                 (12U)
3804 #define ADC_CR1_JDISCEN_Msk                 (0x1UL << ADC_CR1_JDISCEN_Pos)      /*!< 0x00001000 */
3805 #define ADC_CR1_JDISCEN                     ADC_CR1_JDISCEN_Msk                /*!< ADC group injected sequencer discontinuous mode */
3806 
3807 #define ADC_CR1_DISCNUM_Pos                 (13U)
3808 #define ADC_CR1_DISCNUM_Msk                 (0x7UL << ADC_CR1_DISCNUM_Pos)      /*!< 0x0000E000 */
3809 #define ADC_CR1_DISCNUM                     ADC_CR1_DISCNUM_Msk                /*!< ADC group regular sequencer discontinuous number of ranks */
3810 #define ADC_CR1_DISCNUM_0                   (0x1UL << ADC_CR1_DISCNUM_Pos)      /*!< 0x00002000 */
3811 #define ADC_CR1_DISCNUM_1                   (0x2UL << ADC_CR1_DISCNUM_Pos)      /*!< 0x00004000 */
3812 #define ADC_CR1_DISCNUM_2                   (0x4UL << ADC_CR1_DISCNUM_Pos)      /*!< 0x00008000 */
3813 
3814 #define ADC_CR1_DUALMOD_Pos                 (16U)
3815 #define ADC_CR1_DUALMOD_Msk                 (0xFUL << ADC_CR1_DUALMOD_Pos)      /*!< 0x000F0000 */
3816 #define ADC_CR1_DUALMOD                     ADC_CR1_DUALMOD_Msk                /*!< ADC multimode mode selection */
3817 #define ADC_CR1_DUALMOD_0                   (0x1UL << ADC_CR1_DUALMOD_Pos)      /*!< 0x00010000 */
3818 #define ADC_CR1_DUALMOD_1                   (0x2UL << ADC_CR1_DUALMOD_Pos)      /*!< 0x00020000 */
3819 #define ADC_CR1_DUALMOD_2                   (0x4UL << ADC_CR1_DUALMOD_Pos)      /*!< 0x00040000 */
3820 #define ADC_CR1_DUALMOD_3                   (0x8UL << ADC_CR1_DUALMOD_Pos)      /*!< 0x00080000 */
3821 
3822 #define ADC_CR1_JAWDEN_Pos                  (22U)
3823 #define ADC_CR1_JAWDEN_Msk                  (0x1UL << ADC_CR1_JAWDEN_Pos)       /*!< 0x00400000 */
3824 #define ADC_CR1_JAWDEN                      ADC_CR1_JAWDEN_Msk                 /*!< ADC analog watchdog 1 enable on scope ADC group injected */
3825 #define ADC_CR1_AWDEN_Pos                   (23U)
3826 #define ADC_CR1_AWDEN_Msk                   (0x1UL << ADC_CR1_AWDEN_Pos)        /*!< 0x00800000 */
3827 #define ADC_CR1_AWDEN                       ADC_CR1_AWDEN_Msk                  /*!< ADC analog watchdog 1 enable on scope ADC group regular */
3828 
3829 /* Legacy defines */
3830 #define  ADC_CR1_EOCIE                       (ADC_CR1_EOSIE)
3831 #define  ADC_CR1_JEOCIE                      (ADC_CR1_JEOSIE)
3832 
3833 /*******************  Bit definition for ADC_CR2 register  ********************/
3834 #define ADC_CR2_ADON_Pos                    (0U)
3835 #define ADC_CR2_ADON_Msk                    (0x1UL << ADC_CR2_ADON_Pos)         /*!< 0x00000001 */
3836 #define ADC_CR2_ADON                        ADC_CR2_ADON_Msk                   /*!< ADC enable */
3837 #define ADC_CR2_CONT_Pos                    (1U)
3838 #define ADC_CR2_CONT_Msk                    (0x1UL << ADC_CR2_CONT_Pos)         /*!< 0x00000002 */
3839 #define ADC_CR2_CONT                        ADC_CR2_CONT_Msk                   /*!< ADC group regular continuous conversion mode */
3840 #define ADC_CR2_CAL_Pos                     (2U)
3841 #define ADC_CR2_CAL_Msk                     (0x1UL << ADC_CR2_CAL_Pos)          /*!< 0x00000004 */
3842 #define ADC_CR2_CAL                         ADC_CR2_CAL_Msk                    /*!< ADC calibration start */
3843 #define ADC_CR2_RSTCAL_Pos                  (3U)
3844 #define ADC_CR2_RSTCAL_Msk                  (0x1UL << ADC_CR2_RSTCAL_Pos)       /*!< 0x00000008 */
3845 #define ADC_CR2_RSTCAL                      ADC_CR2_RSTCAL_Msk                 /*!< ADC calibration reset */
3846 #define ADC_CR2_DMA_Pos                     (8U)
3847 #define ADC_CR2_DMA_Msk                     (0x1UL << ADC_CR2_DMA_Pos)          /*!< 0x00000100 */
3848 #define ADC_CR2_DMA                         ADC_CR2_DMA_Msk                    /*!< ADC DMA transfer enable */
3849 #define ADC_CR2_ALIGN_Pos                   (11U)
3850 #define ADC_CR2_ALIGN_Msk                   (0x1UL << ADC_CR2_ALIGN_Pos)        /*!< 0x00000800 */
3851 #define ADC_CR2_ALIGN                       ADC_CR2_ALIGN_Msk                  /*!< ADC data alignement */
3852 
3853 #define ADC_CR2_JEXTSEL_Pos                 (12U)
3854 #define ADC_CR2_JEXTSEL_Msk                 (0x7UL << ADC_CR2_JEXTSEL_Pos)      /*!< 0x00007000 */
3855 #define ADC_CR2_JEXTSEL                     ADC_CR2_JEXTSEL_Msk                /*!< ADC group injected external trigger source */
3856 #define ADC_CR2_JEXTSEL_0                   (0x1UL << ADC_CR2_JEXTSEL_Pos)      /*!< 0x00001000 */
3857 #define ADC_CR2_JEXTSEL_1                   (0x2UL << ADC_CR2_JEXTSEL_Pos)      /*!< 0x00002000 */
3858 #define ADC_CR2_JEXTSEL_2                   (0x4UL << ADC_CR2_JEXTSEL_Pos)      /*!< 0x00004000 */
3859 
3860 #define ADC_CR2_JEXTTRIG_Pos                (15U)
3861 #define ADC_CR2_JEXTTRIG_Msk                (0x1UL << ADC_CR2_JEXTTRIG_Pos)     /*!< 0x00008000 */
3862 #define ADC_CR2_JEXTTRIG                    ADC_CR2_JEXTTRIG_Msk               /*!< ADC group injected external trigger enable */
3863 
3864 #define ADC_CR2_EXTSEL_Pos                  (17U)
3865 #define ADC_CR2_EXTSEL_Msk                  (0x7UL << ADC_CR2_EXTSEL_Pos)       /*!< 0x000E0000 */
3866 #define ADC_CR2_EXTSEL                      ADC_CR2_EXTSEL_Msk                 /*!< ADC group regular external trigger source */
3867 #define ADC_CR2_EXTSEL_0                    (0x1UL << ADC_CR2_EXTSEL_Pos)       /*!< 0x00020000 */
3868 #define ADC_CR2_EXTSEL_1                    (0x2UL << ADC_CR2_EXTSEL_Pos)       /*!< 0x00040000 */
3869 #define ADC_CR2_EXTSEL_2                    (0x4UL << ADC_CR2_EXTSEL_Pos)       /*!< 0x00080000 */
3870 
3871 #define ADC_CR2_EXTTRIG_Pos                 (20U)
3872 #define ADC_CR2_EXTTRIG_Msk                 (0x1UL << ADC_CR2_EXTTRIG_Pos)      /*!< 0x00100000 */
3873 #define ADC_CR2_EXTTRIG                     ADC_CR2_EXTTRIG_Msk                /*!< ADC group regular external trigger enable */
3874 #define ADC_CR2_JSWSTART_Pos                (21U)
3875 #define ADC_CR2_JSWSTART_Msk                (0x1UL << ADC_CR2_JSWSTART_Pos)     /*!< 0x00200000 */
3876 #define ADC_CR2_JSWSTART                    ADC_CR2_JSWSTART_Msk               /*!< ADC group injected conversion start */
3877 #define ADC_CR2_SWSTART_Pos                 (22U)
3878 #define ADC_CR2_SWSTART_Msk                 (0x1UL << ADC_CR2_SWSTART_Pos)      /*!< 0x00400000 */
3879 #define ADC_CR2_SWSTART                     ADC_CR2_SWSTART_Msk                /*!< ADC group regular conversion start */
3880 #define ADC_CR2_TSVREFE_Pos                 (23U)
3881 #define ADC_CR2_TSVREFE_Msk                 (0x1UL << ADC_CR2_TSVREFE_Pos)      /*!< 0x00800000 */
3882 #define ADC_CR2_TSVREFE                     ADC_CR2_TSVREFE_Msk                /*!< ADC internal path to VrefInt and temperature sensor enable */
3883 
3884 /******************  Bit definition for ADC_SMPR1 register  *******************/
3885 #define ADC_SMPR1_SMP10_Pos                 (0U)
3886 #define ADC_SMPR1_SMP10_Msk                 (0x7UL << ADC_SMPR1_SMP10_Pos)      /*!< 0x00000007 */
3887 #define ADC_SMPR1_SMP10                     ADC_SMPR1_SMP10_Msk                /*!< ADC channel 10 sampling time selection  */
3888 #define ADC_SMPR1_SMP10_0                   (0x1UL << ADC_SMPR1_SMP10_Pos)      /*!< 0x00000001 */
3889 #define ADC_SMPR1_SMP10_1                   (0x2UL << ADC_SMPR1_SMP10_Pos)      /*!< 0x00000002 */
3890 #define ADC_SMPR1_SMP10_2                   (0x4UL << ADC_SMPR1_SMP10_Pos)      /*!< 0x00000004 */
3891 
3892 #define ADC_SMPR1_SMP11_Pos                 (3U)
3893 #define ADC_SMPR1_SMP11_Msk                 (0x7UL << ADC_SMPR1_SMP11_Pos)      /*!< 0x00000038 */
3894 #define ADC_SMPR1_SMP11                     ADC_SMPR1_SMP11_Msk                /*!< ADC channel 11 sampling time selection  */
3895 #define ADC_SMPR1_SMP11_0                   (0x1UL << ADC_SMPR1_SMP11_Pos)      /*!< 0x00000008 */
3896 #define ADC_SMPR1_SMP11_1                   (0x2UL << ADC_SMPR1_SMP11_Pos)      /*!< 0x00000010 */
3897 #define ADC_SMPR1_SMP11_2                   (0x4UL << ADC_SMPR1_SMP11_Pos)      /*!< 0x00000020 */
3898 
3899 #define ADC_SMPR1_SMP12_Pos                 (6U)
3900 #define ADC_SMPR1_SMP12_Msk                 (0x7UL << ADC_SMPR1_SMP12_Pos)      /*!< 0x000001C0 */
3901 #define ADC_SMPR1_SMP12                     ADC_SMPR1_SMP12_Msk                /*!< ADC channel 12 sampling time selection  */
3902 #define ADC_SMPR1_SMP12_0                   (0x1UL << ADC_SMPR1_SMP12_Pos)      /*!< 0x00000040 */
3903 #define ADC_SMPR1_SMP12_1                   (0x2UL << ADC_SMPR1_SMP12_Pos)      /*!< 0x00000080 */
3904 #define ADC_SMPR1_SMP12_2                   (0x4UL << ADC_SMPR1_SMP12_Pos)      /*!< 0x00000100 */
3905 
3906 #define ADC_SMPR1_SMP13_Pos                 (9U)
3907 #define ADC_SMPR1_SMP13_Msk                 (0x7UL << ADC_SMPR1_SMP13_Pos)      /*!< 0x00000E00 */
3908 #define ADC_SMPR1_SMP13                     ADC_SMPR1_SMP13_Msk                /*!< ADC channel 13 sampling time selection  */
3909 #define ADC_SMPR1_SMP13_0                   (0x1UL << ADC_SMPR1_SMP13_Pos)      /*!< 0x00000200 */
3910 #define ADC_SMPR1_SMP13_1                   (0x2UL << ADC_SMPR1_SMP13_Pos)      /*!< 0x00000400 */
3911 #define ADC_SMPR1_SMP13_2                   (0x4UL << ADC_SMPR1_SMP13_Pos)      /*!< 0x00000800 */
3912 
3913 #define ADC_SMPR1_SMP14_Pos                 (12U)
3914 #define ADC_SMPR1_SMP14_Msk                 (0x7UL << ADC_SMPR1_SMP14_Pos)      /*!< 0x00007000 */
3915 #define ADC_SMPR1_SMP14                     ADC_SMPR1_SMP14_Msk                /*!< ADC channel 14 sampling time selection  */
3916 #define ADC_SMPR1_SMP14_0                   (0x1UL << ADC_SMPR1_SMP14_Pos)      /*!< 0x00001000 */
3917 #define ADC_SMPR1_SMP14_1                   (0x2UL << ADC_SMPR1_SMP14_Pos)      /*!< 0x00002000 */
3918 #define ADC_SMPR1_SMP14_2                   (0x4UL << ADC_SMPR1_SMP14_Pos)      /*!< 0x00004000 */
3919 
3920 #define ADC_SMPR1_SMP15_Pos                 (15U)
3921 #define ADC_SMPR1_SMP15_Msk                 (0x7UL << ADC_SMPR1_SMP15_Pos)      /*!< 0x00038000 */
3922 #define ADC_SMPR1_SMP15                     ADC_SMPR1_SMP15_Msk                /*!< ADC channel 15 sampling time selection  */
3923 #define ADC_SMPR1_SMP15_0                   (0x1UL << ADC_SMPR1_SMP15_Pos)      /*!< 0x00008000 */
3924 #define ADC_SMPR1_SMP15_1                   (0x2UL << ADC_SMPR1_SMP15_Pos)      /*!< 0x00010000 */
3925 #define ADC_SMPR1_SMP15_2                   (0x4UL << ADC_SMPR1_SMP15_Pos)      /*!< 0x00020000 */
3926 
3927 #define ADC_SMPR1_SMP16_Pos                 (18U)
3928 #define ADC_SMPR1_SMP16_Msk                 (0x7UL << ADC_SMPR1_SMP16_Pos)      /*!< 0x001C0000 */
3929 #define ADC_SMPR1_SMP16                     ADC_SMPR1_SMP16_Msk                /*!< ADC channel 16 sampling time selection  */
3930 #define ADC_SMPR1_SMP16_0                   (0x1UL << ADC_SMPR1_SMP16_Pos)      /*!< 0x00040000 */
3931 #define ADC_SMPR1_SMP16_1                   (0x2UL << ADC_SMPR1_SMP16_Pos)      /*!< 0x00080000 */
3932 #define ADC_SMPR1_SMP16_2                   (0x4UL << ADC_SMPR1_SMP16_Pos)      /*!< 0x00100000 */
3933 
3934 #define ADC_SMPR1_SMP17_Pos                 (21U)
3935 #define ADC_SMPR1_SMP17_Msk                 (0x7UL << ADC_SMPR1_SMP17_Pos)      /*!< 0x00E00000 */
3936 #define ADC_SMPR1_SMP17                     ADC_SMPR1_SMP17_Msk                /*!< ADC channel 17 sampling time selection  */
3937 #define ADC_SMPR1_SMP17_0                   (0x1UL << ADC_SMPR1_SMP17_Pos)      /*!< 0x00200000 */
3938 #define ADC_SMPR1_SMP17_1                   (0x2UL << ADC_SMPR1_SMP17_Pos)      /*!< 0x00400000 */
3939 #define ADC_SMPR1_SMP17_2                   (0x4UL << ADC_SMPR1_SMP17_Pos)      /*!< 0x00800000 */
3940 
3941 /******************  Bit definition for ADC_SMPR2 register  *******************/
3942 #define ADC_SMPR2_SMP0_Pos                  (0U)
3943 #define ADC_SMPR2_SMP0_Msk                  (0x7UL << ADC_SMPR2_SMP0_Pos)       /*!< 0x00000007 */
3944 #define ADC_SMPR2_SMP0                      ADC_SMPR2_SMP0_Msk                 /*!< ADC channel 0 sampling time selection  */
3945 #define ADC_SMPR2_SMP0_0                    (0x1UL << ADC_SMPR2_SMP0_Pos)       /*!< 0x00000001 */
3946 #define ADC_SMPR2_SMP0_1                    (0x2UL << ADC_SMPR2_SMP0_Pos)       /*!< 0x00000002 */
3947 #define ADC_SMPR2_SMP0_2                    (0x4UL << ADC_SMPR2_SMP0_Pos)       /*!< 0x00000004 */
3948 
3949 #define ADC_SMPR2_SMP1_Pos                  (3U)
3950 #define ADC_SMPR2_SMP1_Msk                  (0x7UL << ADC_SMPR2_SMP1_Pos)       /*!< 0x00000038 */
3951 #define ADC_SMPR2_SMP1                      ADC_SMPR2_SMP1_Msk                 /*!< ADC channel 1 sampling time selection  */
3952 #define ADC_SMPR2_SMP1_0                    (0x1UL << ADC_SMPR2_SMP1_Pos)       /*!< 0x00000008 */
3953 #define ADC_SMPR2_SMP1_1                    (0x2UL << ADC_SMPR2_SMP1_Pos)       /*!< 0x00000010 */
3954 #define ADC_SMPR2_SMP1_2                    (0x4UL << ADC_SMPR2_SMP1_Pos)       /*!< 0x00000020 */
3955 
3956 #define ADC_SMPR2_SMP2_Pos                  (6U)
3957 #define ADC_SMPR2_SMP2_Msk                  (0x7UL << ADC_SMPR2_SMP2_Pos)       /*!< 0x000001C0 */
3958 #define ADC_SMPR2_SMP2                      ADC_SMPR2_SMP2_Msk                 /*!< ADC channel 2 sampling time selection  */
3959 #define ADC_SMPR2_SMP2_0                    (0x1UL << ADC_SMPR2_SMP2_Pos)       /*!< 0x00000040 */
3960 #define ADC_SMPR2_SMP2_1                    (0x2UL << ADC_SMPR2_SMP2_Pos)       /*!< 0x00000080 */
3961 #define ADC_SMPR2_SMP2_2                    (0x4UL << ADC_SMPR2_SMP2_Pos)       /*!< 0x00000100 */
3962 
3963 #define ADC_SMPR2_SMP3_Pos                  (9U)
3964 #define ADC_SMPR2_SMP3_Msk                  (0x7UL << ADC_SMPR2_SMP3_Pos)       /*!< 0x00000E00 */
3965 #define ADC_SMPR2_SMP3                      ADC_SMPR2_SMP3_Msk                 /*!< ADC channel 3 sampling time selection  */
3966 #define ADC_SMPR2_SMP3_0                    (0x1UL << ADC_SMPR2_SMP3_Pos)       /*!< 0x00000200 */
3967 #define ADC_SMPR2_SMP3_1                    (0x2UL << ADC_SMPR2_SMP3_Pos)       /*!< 0x00000400 */
3968 #define ADC_SMPR2_SMP3_2                    (0x4UL << ADC_SMPR2_SMP3_Pos)       /*!< 0x00000800 */
3969 
3970 #define ADC_SMPR2_SMP4_Pos                  (12U)
3971 #define ADC_SMPR2_SMP4_Msk                  (0x7UL << ADC_SMPR2_SMP4_Pos)       /*!< 0x00007000 */
3972 #define ADC_SMPR2_SMP4                      ADC_SMPR2_SMP4_Msk                 /*!< ADC channel 4 sampling time selection  */
3973 #define ADC_SMPR2_SMP4_0                    (0x1UL << ADC_SMPR2_SMP4_Pos)       /*!< 0x00001000 */
3974 #define ADC_SMPR2_SMP4_1                    (0x2UL << ADC_SMPR2_SMP4_Pos)       /*!< 0x00002000 */
3975 #define ADC_SMPR2_SMP4_2                    (0x4UL << ADC_SMPR2_SMP4_Pos)       /*!< 0x00004000 */
3976 
3977 #define ADC_SMPR2_SMP5_Pos                  (15U)
3978 #define ADC_SMPR2_SMP5_Msk                  (0x7UL << ADC_SMPR2_SMP5_Pos)       /*!< 0x00038000 */
3979 #define ADC_SMPR2_SMP5                      ADC_SMPR2_SMP5_Msk                 /*!< ADC channel 5 sampling time selection  */
3980 #define ADC_SMPR2_SMP5_0                    (0x1UL << ADC_SMPR2_SMP5_Pos)       /*!< 0x00008000 */
3981 #define ADC_SMPR2_SMP5_1                    (0x2UL << ADC_SMPR2_SMP5_Pos)       /*!< 0x00010000 */
3982 #define ADC_SMPR2_SMP5_2                    (0x4UL << ADC_SMPR2_SMP5_Pos)       /*!< 0x00020000 */
3983 
3984 #define ADC_SMPR2_SMP6_Pos                  (18U)
3985 #define ADC_SMPR2_SMP6_Msk                  (0x7UL << ADC_SMPR2_SMP6_Pos)       /*!< 0x001C0000 */
3986 #define ADC_SMPR2_SMP6                      ADC_SMPR2_SMP6_Msk                 /*!< ADC channel 6 sampling time selection  */
3987 #define ADC_SMPR2_SMP6_0                    (0x1UL << ADC_SMPR2_SMP6_Pos)       /*!< 0x00040000 */
3988 #define ADC_SMPR2_SMP6_1                    (0x2UL << ADC_SMPR2_SMP6_Pos)       /*!< 0x00080000 */
3989 #define ADC_SMPR2_SMP6_2                    (0x4UL << ADC_SMPR2_SMP6_Pos)       /*!< 0x00100000 */
3990 
3991 #define ADC_SMPR2_SMP7_Pos                  (21U)
3992 #define ADC_SMPR2_SMP7_Msk                  (0x7UL << ADC_SMPR2_SMP7_Pos)       /*!< 0x00E00000 */
3993 #define ADC_SMPR2_SMP7                      ADC_SMPR2_SMP7_Msk                 /*!< ADC channel 7 sampling time selection  */
3994 #define ADC_SMPR2_SMP7_0                    (0x1UL << ADC_SMPR2_SMP7_Pos)       /*!< 0x00200000 */
3995 #define ADC_SMPR2_SMP7_1                    (0x2UL << ADC_SMPR2_SMP7_Pos)       /*!< 0x00400000 */
3996 #define ADC_SMPR2_SMP7_2                    (0x4UL << ADC_SMPR2_SMP7_Pos)       /*!< 0x00800000 */
3997 
3998 #define ADC_SMPR2_SMP8_Pos                  (24U)
3999 #define ADC_SMPR2_SMP8_Msk                  (0x7UL << ADC_SMPR2_SMP8_Pos)       /*!< 0x07000000 */
4000 #define ADC_SMPR2_SMP8                      ADC_SMPR2_SMP8_Msk                 /*!< ADC channel 8 sampling time selection  */
4001 #define ADC_SMPR2_SMP8_0                    (0x1UL << ADC_SMPR2_SMP8_Pos)       /*!< 0x01000000 */
4002 #define ADC_SMPR2_SMP8_1                    (0x2UL << ADC_SMPR2_SMP8_Pos)       /*!< 0x02000000 */
4003 #define ADC_SMPR2_SMP8_2                    (0x4UL << ADC_SMPR2_SMP8_Pos)       /*!< 0x04000000 */
4004 
4005 #define ADC_SMPR2_SMP9_Pos                  (27U)
4006 #define ADC_SMPR2_SMP9_Msk                  (0x7UL << ADC_SMPR2_SMP9_Pos)       /*!< 0x38000000 */
4007 #define ADC_SMPR2_SMP9                      ADC_SMPR2_SMP9_Msk                 /*!< ADC channel 9 sampling time selection  */
4008 #define ADC_SMPR2_SMP9_0                    (0x1UL << ADC_SMPR2_SMP9_Pos)       /*!< 0x08000000 */
4009 #define ADC_SMPR2_SMP9_1                    (0x2UL << ADC_SMPR2_SMP9_Pos)       /*!< 0x10000000 */
4010 #define ADC_SMPR2_SMP9_2                    (0x4UL << ADC_SMPR2_SMP9_Pos)       /*!< 0x20000000 */
4011 
4012 /******************  Bit definition for ADC_JOFR1 register  *******************/
4013 #define ADC_JOFR1_JOFFSET1_Pos              (0U)
4014 #define ADC_JOFR1_JOFFSET1_Msk              (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
4015 #define ADC_JOFR1_JOFFSET1                  ADC_JOFR1_JOFFSET1_Msk             /*!< ADC group injected sequencer rank 1 offset value */
4016 
4017 /******************  Bit definition for ADC_JOFR2 register  *******************/
4018 #define ADC_JOFR2_JOFFSET2_Pos              (0U)
4019 #define ADC_JOFR2_JOFFSET2_Msk              (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
4020 #define ADC_JOFR2_JOFFSET2                  ADC_JOFR2_JOFFSET2_Msk             /*!< ADC group injected sequencer rank 2 offset value */
4021 
4022 /******************  Bit definition for ADC_JOFR3 register  *******************/
4023 #define ADC_JOFR3_JOFFSET3_Pos              (0U)
4024 #define ADC_JOFR3_JOFFSET3_Msk              (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
4025 #define ADC_JOFR3_JOFFSET3                  ADC_JOFR3_JOFFSET3_Msk             /*!< ADC group injected sequencer rank 3 offset value */
4026 
4027 /******************  Bit definition for ADC_JOFR4 register  *******************/
4028 #define ADC_JOFR4_JOFFSET4_Pos              (0U)
4029 #define ADC_JOFR4_JOFFSET4_Msk              (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
4030 #define ADC_JOFR4_JOFFSET4                  ADC_JOFR4_JOFFSET4_Msk             /*!< ADC group injected sequencer rank 4 offset value */
4031 
4032 /*******************  Bit definition for ADC_HTR register  ********************/
4033 #define ADC_HTR_HT_Pos                      (0U)
4034 #define ADC_HTR_HT_Msk                      (0xFFFUL << ADC_HTR_HT_Pos)         /*!< 0x00000FFF */
4035 #define ADC_HTR_HT                          ADC_HTR_HT_Msk                     /*!< ADC analog watchdog 1 threshold high */
4036 
4037 /*******************  Bit definition for ADC_LTR register  ********************/
4038 #define ADC_LTR_LT_Pos                      (0U)
4039 #define ADC_LTR_LT_Msk                      (0xFFFUL << ADC_LTR_LT_Pos)         /*!< 0x00000FFF */
4040 #define ADC_LTR_LT                          ADC_LTR_LT_Msk                     /*!< ADC analog watchdog 1 threshold low */
4041 
4042 /*******************  Bit definition for ADC_SQR1 register  *******************/
4043 #define ADC_SQR1_SQ13_Pos                   (0U)
4044 #define ADC_SQR1_SQ13_Msk                   (0x1FUL << ADC_SQR1_SQ13_Pos)       /*!< 0x0000001F */
4045 #define ADC_SQR1_SQ13                       ADC_SQR1_SQ13_Msk                  /*!< ADC group regular sequencer rank 13 */
4046 #define ADC_SQR1_SQ13_0                     (0x01UL << ADC_SQR1_SQ13_Pos)       /*!< 0x00000001 */
4047 #define ADC_SQR1_SQ13_1                     (0x02UL << ADC_SQR1_SQ13_Pos)       /*!< 0x00000002 */
4048 #define ADC_SQR1_SQ13_2                     (0x04UL << ADC_SQR1_SQ13_Pos)       /*!< 0x00000004 */
4049 #define ADC_SQR1_SQ13_3                     (0x08UL << ADC_SQR1_SQ13_Pos)       /*!< 0x00000008 */
4050 #define ADC_SQR1_SQ13_4                     (0x10UL << ADC_SQR1_SQ13_Pos)       /*!< 0x00000010 */
4051 
4052 #define ADC_SQR1_SQ14_Pos                   (5U)
4053 #define ADC_SQR1_SQ14_Msk                   (0x1FUL << ADC_SQR1_SQ14_Pos)       /*!< 0x000003E0 */
4054 #define ADC_SQR1_SQ14                       ADC_SQR1_SQ14_Msk                  /*!< ADC group regular sequencer rank 14 */
4055 #define ADC_SQR1_SQ14_0                     (0x01UL << ADC_SQR1_SQ14_Pos)       /*!< 0x00000020 */
4056 #define ADC_SQR1_SQ14_1                     (0x02UL << ADC_SQR1_SQ14_Pos)       /*!< 0x00000040 */
4057 #define ADC_SQR1_SQ14_2                     (0x04UL << ADC_SQR1_SQ14_Pos)       /*!< 0x00000080 */
4058 #define ADC_SQR1_SQ14_3                     (0x08UL << ADC_SQR1_SQ14_Pos)       /*!< 0x00000100 */
4059 #define ADC_SQR1_SQ14_4                     (0x10UL << ADC_SQR1_SQ14_Pos)       /*!< 0x00000200 */
4060 
4061 #define ADC_SQR1_SQ15_Pos                   (10U)
4062 #define ADC_SQR1_SQ15_Msk                   (0x1FUL << ADC_SQR1_SQ15_Pos)       /*!< 0x00007C00 */
4063 #define ADC_SQR1_SQ15                       ADC_SQR1_SQ15_Msk                  /*!< ADC group regular sequencer rank 15 */
4064 #define ADC_SQR1_SQ15_0                     (0x01UL << ADC_SQR1_SQ15_Pos)       /*!< 0x00000400 */
4065 #define ADC_SQR1_SQ15_1                     (0x02UL << ADC_SQR1_SQ15_Pos)       /*!< 0x00000800 */
4066 #define ADC_SQR1_SQ15_2                     (0x04UL << ADC_SQR1_SQ15_Pos)       /*!< 0x00001000 */
4067 #define ADC_SQR1_SQ15_3                     (0x08UL << ADC_SQR1_SQ15_Pos)       /*!< 0x00002000 */
4068 #define ADC_SQR1_SQ15_4                     (0x10UL << ADC_SQR1_SQ15_Pos)       /*!< 0x00004000 */
4069 
4070 #define ADC_SQR1_SQ16_Pos                   (15U)
4071 #define ADC_SQR1_SQ16_Msk                   (0x1FUL << ADC_SQR1_SQ16_Pos)       /*!< 0x000F8000 */
4072 #define ADC_SQR1_SQ16                       ADC_SQR1_SQ16_Msk                  /*!< ADC group regular sequencer rank 16 */
4073 #define ADC_SQR1_SQ16_0                     (0x01UL << ADC_SQR1_SQ16_Pos)       /*!< 0x00008000 */
4074 #define ADC_SQR1_SQ16_1                     (0x02UL << ADC_SQR1_SQ16_Pos)       /*!< 0x00010000 */
4075 #define ADC_SQR1_SQ16_2                     (0x04UL << ADC_SQR1_SQ16_Pos)       /*!< 0x00020000 */
4076 #define ADC_SQR1_SQ16_3                     (0x08UL << ADC_SQR1_SQ16_Pos)       /*!< 0x00040000 */
4077 #define ADC_SQR1_SQ16_4                     (0x10UL << ADC_SQR1_SQ16_Pos)       /*!< 0x00080000 */
4078 
4079 #define ADC_SQR1_L_Pos                      (20U)
4080 #define ADC_SQR1_L_Msk                      (0xFUL << ADC_SQR1_L_Pos)           /*!< 0x00F00000 */
4081 #define ADC_SQR1_L                          ADC_SQR1_L_Msk                     /*!< ADC group regular sequencer scan length */
4082 #define ADC_SQR1_L_0                        (0x1UL << ADC_SQR1_L_Pos)           /*!< 0x00100000 */
4083 #define ADC_SQR1_L_1                        (0x2UL << ADC_SQR1_L_Pos)           /*!< 0x00200000 */
4084 #define ADC_SQR1_L_2                        (0x4UL << ADC_SQR1_L_Pos)           /*!< 0x00400000 */
4085 #define ADC_SQR1_L_3                        (0x8UL << ADC_SQR1_L_Pos)           /*!< 0x00800000 */
4086 
4087 /*******************  Bit definition for ADC_SQR2 register  *******************/
4088 #define ADC_SQR2_SQ7_Pos                    (0U)
4089 #define ADC_SQR2_SQ7_Msk                    (0x1FUL << ADC_SQR2_SQ7_Pos)        /*!< 0x0000001F */
4090 #define ADC_SQR2_SQ7                        ADC_SQR2_SQ7_Msk                   /*!< ADC group regular sequencer rank 7 */
4091 #define ADC_SQR2_SQ7_0                      (0x01UL << ADC_SQR2_SQ7_Pos)        /*!< 0x00000001 */
4092 #define ADC_SQR2_SQ7_1                      (0x02UL << ADC_SQR2_SQ7_Pos)        /*!< 0x00000002 */
4093 #define ADC_SQR2_SQ7_2                      (0x04UL << ADC_SQR2_SQ7_Pos)        /*!< 0x00000004 */
4094 #define ADC_SQR2_SQ7_3                      (0x08UL << ADC_SQR2_SQ7_Pos)        /*!< 0x00000008 */
4095 #define ADC_SQR2_SQ7_4                      (0x10UL << ADC_SQR2_SQ7_Pos)        /*!< 0x00000010 */
4096 
4097 #define ADC_SQR2_SQ8_Pos                    (5U)
4098 #define ADC_SQR2_SQ8_Msk                    (0x1FUL << ADC_SQR2_SQ8_Pos)        /*!< 0x000003E0 */
4099 #define ADC_SQR2_SQ8                        ADC_SQR2_SQ8_Msk                   /*!< ADC group regular sequencer rank 8 */
4100 #define ADC_SQR2_SQ8_0                      (0x01UL << ADC_SQR2_SQ8_Pos)        /*!< 0x00000020 */
4101 #define ADC_SQR2_SQ8_1                      (0x02UL << ADC_SQR2_SQ8_Pos)        /*!< 0x00000040 */
4102 #define ADC_SQR2_SQ8_2                      (0x04UL << ADC_SQR2_SQ8_Pos)        /*!< 0x00000080 */
4103 #define ADC_SQR2_SQ8_3                      (0x08UL << ADC_SQR2_SQ8_Pos)        /*!< 0x00000100 */
4104 #define ADC_SQR2_SQ8_4                      (0x10UL << ADC_SQR2_SQ8_Pos)        /*!< 0x00000200 */
4105 
4106 #define ADC_SQR2_SQ9_Pos                    (10U)
4107 #define ADC_SQR2_SQ9_Msk                    (0x1FUL << ADC_SQR2_SQ9_Pos)        /*!< 0x00007C00 */
4108 #define ADC_SQR2_SQ9                        ADC_SQR2_SQ9_Msk                   /*!< ADC group regular sequencer rank 9 */
4109 #define ADC_SQR2_SQ9_0                      (0x01UL << ADC_SQR2_SQ9_Pos)        /*!< 0x00000400 */
4110 #define ADC_SQR2_SQ9_1                      (0x02UL << ADC_SQR2_SQ9_Pos)        /*!< 0x00000800 */
4111 #define ADC_SQR2_SQ9_2                      (0x04UL << ADC_SQR2_SQ9_Pos)        /*!< 0x00001000 */
4112 #define ADC_SQR2_SQ9_3                      (0x08UL << ADC_SQR2_SQ9_Pos)        /*!< 0x00002000 */
4113 #define ADC_SQR2_SQ9_4                      (0x10UL << ADC_SQR2_SQ9_Pos)        /*!< 0x00004000 */
4114 
4115 #define ADC_SQR2_SQ10_Pos                   (15U)
4116 #define ADC_SQR2_SQ10_Msk                   (0x1FUL << ADC_SQR2_SQ10_Pos)       /*!< 0x000F8000 */
4117 #define ADC_SQR2_SQ10                       ADC_SQR2_SQ10_Msk                  /*!< ADC group regular sequencer rank 10 */
4118 #define ADC_SQR2_SQ10_0                     (0x01UL << ADC_SQR2_SQ10_Pos)       /*!< 0x00008000 */
4119 #define ADC_SQR2_SQ10_1                     (0x02UL << ADC_SQR2_SQ10_Pos)       /*!< 0x00010000 */
4120 #define ADC_SQR2_SQ10_2                     (0x04UL << ADC_SQR2_SQ10_Pos)       /*!< 0x00020000 */
4121 #define ADC_SQR2_SQ10_3                     (0x08UL << ADC_SQR2_SQ10_Pos)       /*!< 0x00040000 */
4122 #define ADC_SQR2_SQ10_4                     (0x10UL << ADC_SQR2_SQ10_Pos)       /*!< 0x00080000 */
4123 
4124 #define ADC_SQR2_SQ11_Pos                   (20U)
4125 #define ADC_SQR2_SQ11_Msk                   (0x1FUL << ADC_SQR2_SQ11_Pos)       /*!< 0x01F00000 */
4126 #define ADC_SQR2_SQ11                       ADC_SQR2_SQ11_Msk                  /*!< ADC group regular sequencer rank 1 */
4127 #define ADC_SQR2_SQ11_0                     (0x01UL << ADC_SQR2_SQ11_Pos)       /*!< 0x00100000 */
4128 #define ADC_SQR2_SQ11_1                     (0x02UL << ADC_SQR2_SQ11_Pos)       /*!< 0x00200000 */
4129 #define ADC_SQR2_SQ11_2                     (0x04UL << ADC_SQR2_SQ11_Pos)       /*!< 0x00400000 */
4130 #define ADC_SQR2_SQ11_3                     (0x08UL << ADC_SQR2_SQ11_Pos)       /*!< 0x00800000 */
4131 #define ADC_SQR2_SQ11_4                     (0x10UL << ADC_SQR2_SQ11_Pos)       /*!< 0x01000000 */
4132 
4133 #define ADC_SQR2_SQ12_Pos                   (25U)
4134 #define ADC_SQR2_SQ12_Msk                   (0x1FUL << ADC_SQR2_SQ12_Pos)       /*!< 0x3E000000 */
4135 #define ADC_SQR2_SQ12                       ADC_SQR2_SQ12_Msk                  /*!< ADC group regular sequencer rank 12 */
4136 #define ADC_SQR2_SQ12_0                     (0x01UL << ADC_SQR2_SQ12_Pos)       /*!< 0x02000000 */
4137 #define ADC_SQR2_SQ12_1                     (0x02UL << ADC_SQR2_SQ12_Pos)       /*!< 0x04000000 */
4138 #define ADC_SQR2_SQ12_2                     (0x04UL << ADC_SQR2_SQ12_Pos)       /*!< 0x08000000 */
4139 #define ADC_SQR2_SQ12_3                     (0x08UL << ADC_SQR2_SQ12_Pos)       /*!< 0x10000000 */
4140 #define ADC_SQR2_SQ12_4                     (0x10UL << ADC_SQR2_SQ12_Pos)       /*!< 0x20000000 */
4141 
4142 /*******************  Bit definition for ADC_SQR3 register  *******************/
4143 #define ADC_SQR3_SQ1_Pos                    (0U)
4144 #define ADC_SQR3_SQ1_Msk                    (0x1FUL << ADC_SQR3_SQ1_Pos)        /*!< 0x0000001F */
4145 #define ADC_SQR3_SQ1                        ADC_SQR3_SQ1_Msk                   /*!< ADC group regular sequencer rank 1 */
4146 #define ADC_SQR3_SQ1_0                      (0x01UL << ADC_SQR3_SQ1_Pos)        /*!< 0x00000001 */
4147 #define ADC_SQR3_SQ1_1                      (0x02UL << ADC_SQR3_SQ1_Pos)        /*!< 0x00000002 */
4148 #define ADC_SQR3_SQ1_2                      (0x04UL << ADC_SQR3_SQ1_Pos)        /*!< 0x00000004 */
4149 #define ADC_SQR3_SQ1_3                      (0x08UL << ADC_SQR3_SQ1_Pos)        /*!< 0x00000008 */
4150 #define ADC_SQR3_SQ1_4                      (0x10UL << ADC_SQR3_SQ1_Pos)        /*!< 0x00000010 */
4151 
4152 #define ADC_SQR3_SQ2_Pos                    (5U)
4153 #define ADC_SQR3_SQ2_Msk                    (0x1FUL << ADC_SQR3_SQ2_Pos)        /*!< 0x000003E0 */
4154 #define ADC_SQR3_SQ2                        ADC_SQR3_SQ2_Msk                   /*!< ADC group regular sequencer rank 2 */
4155 #define ADC_SQR3_SQ2_0                      (0x01UL << ADC_SQR3_SQ2_Pos)        /*!< 0x00000020 */
4156 #define ADC_SQR3_SQ2_1                      (0x02UL << ADC_SQR3_SQ2_Pos)        /*!< 0x00000040 */
4157 #define ADC_SQR3_SQ2_2                      (0x04UL << ADC_SQR3_SQ2_Pos)        /*!< 0x00000080 */
4158 #define ADC_SQR3_SQ2_3                      (0x08UL << ADC_SQR3_SQ2_Pos)        /*!< 0x00000100 */
4159 #define ADC_SQR3_SQ2_4                      (0x10UL << ADC_SQR3_SQ2_Pos)        /*!< 0x00000200 */
4160 
4161 #define ADC_SQR3_SQ3_Pos                    (10U)
4162 #define ADC_SQR3_SQ3_Msk                    (0x1FUL << ADC_SQR3_SQ3_Pos)        /*!< 0x00007C00 */
4163 #define ADC_SQR3_SQ3                        ADC_SQR3_SQ3_Msk                   /*!< ADC group regular sequencer rank 3 */
4164 #define ADC_SQR3_SQ3_0                      (0x01UL << ADC_SQR3_SQ3_Pos)        /*!< 0x00000400 */
4165 #define ADC_SQR3_SQ3_1                      (0x02UL << ADC_SQR3_SQ3_Pos)        /*!< 0x00000800 */
4166 #define ADC_SQR3_SQ3_2                      (0x04UL << ADC_SQR3_SQ3_Pos)        /*!< 0x00001000 */
4167 #define ADC_SQR3_SQ3_3                      (0x08UL << ADC_SQR3_SQ3_Pos)        /*!< 0x00002000 */
4168 #define ADC_SQR3_SQ3_4                      (0x10UL << ADC_SQR3_SQ3_Pos)        /*!< 0x00004000 */
4169 
4170 #define ADC_SQR3_SQ4_Pos                    (15U)
4171 #define ADC_SQR3_SQ4_Msk                    (0x1FUL << ADC_SQR3_SQ4_Pos)        /*!< 0x000F8000 */
4172 #define ADC_SQR3_SQ4                        ADC_SQR3_SQ4_Msk                   /*!< ADC group regular sequencer rank 4 */
4173 #define ADC_SQR3_SQ4_0                      (0x01UL << ADC_SQR3_SQ4_Pos)        /*!< 0x00008000 */
4174 #define ADC_SQR3_SQ4_1                      (0x02UL << ADC_SQR3_SQ4_Pos)        /*!< 0x00010000 */
4175 #define ADC_SQR3_SQ4_2                      (0x04UL << ADC_SQR3_SQ4_Pos)        /*!< 0x00020000 */
4176 #define ADC_SQR3_SQ4_3                      (0x08UL << ADC_SQR3_SQ4_Pos)        /*!< 0x00040000 */
4177 #define ADC_SQR3_SQ4_4                      (0x10UL << ADC_SQR3_SQ4_Pos)        /*!< 0x00080000 */
4178 
4179 #define ADC_SQR3_SQ5_Pos                    (20U)
4180 #define ADC_SQR3_SQ5_Msk                    (0x1FUL << ADC_SQR3_SQ5_Pos)        /*!< 0x01F00000 */
4181 #define ADC_SQR3_SQ5                        ADC_SQR3_SQ5_Msk                   /*!< ADC group regular sequencer rank 5 */
4182 #define ADC_SQR3_SQ5_0                      (0x01UL << ADC_SQR3_SQ5_Pos)        /*!< 0x00100000 */
4183 #define ADC_SQR3_SQ5_1                      (0x02UL << ADC_SQR3_SQ5_Pos)        /*!< 0x00200000 */
4184 #define ADC_SQR3_SQ5_2                      (0x04UL << ADC_SQR3_SQ5_Pos)        /*!< 0x00400000 */
4185 #define ADC_SQR3_SQ5_3                      (0x08UL << ADC_SQR3_SQ5_Pos)        /*!< 0x00800000 */
4186 #define ADC_SQR3_SQ5_4                      (0x10UL << ADC_SQR3_SQ5_Pos)        /*!< 0x01000000 */
4187 
4188 #define ADC_SQR3_SQ6_Pos                    (25U)
4189 #define ADC_SQR3_SQ6_Msk                    (0x1FUL << ADC_SQR3_SQ6_Pos)        /*!< 0x3E000000 */
4190 #define ADC_SQR3_SQ6                        ADC_SQR3_SQ6_Msk                   /*!< ADC group regular sequencer rank 6 */
4191 #define ADC_SQR3_SQ6_0                      (0x01UL << ADC_SQR3_SQ6_Pos)        /*!< 0x02000000 */
4192 #define ADC_SQR3_SQ6_1                      (0x02UL << ADC_SQR3_SQ6_Pos)        /*!< 0x04000000 */
4193 #define ADC_SQR3_SQ6_2                      (0x04UL << ADC_SQR3_SQ6_Pos)        /*!< 0x08000000 */
4194 #define ADC_SQR3_SQ6_3                      (0x08UL << ADC_SQR3_SQ6_Pos)        /*!< 0x10000000 */
4195 #define ADC_SQR3_SQ6_4                      (0x10UL << ADC_SQR3_SQ6_Pos)        /*!< 0x20000000 */
4196 
4197 /*******************  Bit definition for ADC_JSQR register  *******************/
4198 #define ADC_JSQR_JSQ1_Pos                   (0U)
4199 #define ADC_JSQR_JSQ1_Msk                   (0x1FUL << ADC_JSQR_JSQ1_Pos)       /*!< 0x0000001F */
4200 #define ADC_JSQR_JSQ1                       ADC_JSQR_JSQ1_Msk                  /*!< ADC group injected sequencer rank 1 */
4201 #define ADC_JSQR_JSQ1_0                     (0x01UL << ADC_JSQR_JSQ1_Pos)       /*!< 0x00000001 */
4202 #define ADC_JSQR_JSQ1_1                     (0x02UL << ADC_JSQR_JSQ1_Pos)       /*!< 0x00000002 */
4203 #define ADC_JSQR_JSQ1_2                     (0x04UL << ADC_JSQR_JSQ1_Pos)       /*!< 0x00000004 */
4204 #define ADC_JSQR_JSQ1_3                     (0x08UL << ADC_JSQR_JSQ1_Pos)       /*!< 0x00000008 */
4205 #define ADC_JSQR_JSQ1_4                     (0x10UL << ADC_JSQR_JSQ1_Pos)       /*!< 0x00000010 */
4206 
4207 #define ADC_JSQR_JSQ2_Pos                   (5U)
4208 #define ADC_JSQR_JSQ2_Msk                   (0x1FUL << ADC_JSQR_JSQ2_Pos)       /*!< 0x000003E0 */
4209 #define ADC_JSQR_JSQ2                       ADC_JSQR_JSQ2_Msk                  /*!< ADC group injected sequencer rank 2 */
4210 #define ADC_JSQR_JSQ2_0                     (0x01UL << ADC_JSQR_JSQ2_Pos)       /*!< 0x00000020 */
4211 #define ADC_JSQR_JSQ2_1                     (0x02UL << ADC_JSQR_JSQ2_Pos)       /*!< 0x00000040 */
4212 #define ADC_JSQR_JSQ2_2                     (0x04UL << ADC_JSQR_JSQ2_Pos)       /*!< 0x00000080 */
4213 #define ADC_JSQR_JSQ2_3                     (0x08UL << ADC_JSQR_JSQ2_Pos)       /*!< 0x00000100 */
4214 #define ADC_JSQR_JSQ2_4                     (0x10UL << ADC_JSQR_JSQ2_Pos)       /*!< 0x00000200 */
4215 
4216 #define ADC_JSQR_JSQ3_Pos                   (10U)
4217 #define ADC_JSQR_JSQ3_Msk                   (0x1FUL << ADC_JSQR_JSQ3_Pos)       /*!< 0x00007C00 */
4218 #define ADC_JSQR_JSQ3                       ADC_JSQR_JSQ3_Msk                  /*!< ADC group injected sequencer rank 3 */
4219 #define ADC_JSQR_JSQ3_0                     (0x01UL << ADC_JSQR_JSQ3_Pos)       /*!< 0x00000400 */
4220 #define ADC_JSQR_JSQ3_1                     (0x02UL << ADC_JSQR_JSQ3_Pos)       /*!< 0x00000800 */
4221 #define ADC_JSQR_JSQ3_2                     (0x04UL << ADC_JSQR_JSQ3_Pos)       /*!< 0x00001000 */
4222 #define ADC_JSQR_JSQ3_3                     (0x08UL << ADC_JSQR_JSQ3_Pos)       /*!< 0x00002000 */
4223 #define ADC_JSQR_JSQ3_4                     (0x10UL << ADC_JSQR_JSQ3_Pos)       /*!< 0x00004000 */
4224 
4225 #define ADC_JSQR_JSQ4_Pos                   (15U)
4226 #define ADC_JSQR_JSQ4_Msk                   (0x1FUL << ADC_JSQR_JSQ4_Pos)       /*!< 0x000F8000 */
4227 #define ADC_JSQR_JSQ4                       ADC_JSQR_JSQ4_Msk                  /*!< ADC group injected sequencer rank 4 */
4228 #define ADC_JSQR_JSQ4_0                     (0x01UL << ADC_JSQR_JSQ4_Pos)       /*!< 0x00008000 */
4229 #define ADC_JSQR_JSQ4_1                     (0x02UL << ADC_JSQR_JSQ4_Pos)       /*!< 0x00010000 */
4230 #define ADC_JSQR_JSQ4_2                     (0x04UL << ADC_JSQR_JSQ4_Pos)       /*!< 0x00020000 */
4231 #define ADC_JSQR_JSQ4_3                     (0x08UL << ADC_JSQR_JSQ4_Pos)       /*!< 0x00040000 */
4232 #define ADC_JSQR_JSQ4_4                     (0x10UL << ADC_JSQR_JSQ4_Pos)       /*!< 0x00080000 */
4233 
4234 #define ADC_JSQR_JL_Pos                     (20U)
4235 #define ADC_JSQR_JL_Msk                     (0x3UL << ADC_JSQR_JL_Pos)          /*!< 0x00300000 */
4236 #define ADC_JSQR_JL                         ADC_JSQR_JL_Msk                    /*!< ADC group injected sequencer scan length */
4237 #define ADC_JSQR_JL_0                       (0x1UL << ADC_JSQR_JL_Pos)          /*!< 0x00100000 */
4238 #define ADC_JSQR_JL_1                       (0x2UL << ADC_JSQR_JL_Pos)          /*!< 0x00200000 */
4239 
4240 /*******************  Bit definition for ADC_JDR1 register  *******************/
4241 #define ADC_JDR1_JDATA_Pos                  (0U)
4242 #define ADC_JDR1_JDATA_Msk                  (0xFFFFUL << ADC_JDR1_JDATA_Pos)    /*!< 0x0000FFFF */
4243 #define ADC_JDR1_JDATA                      ADC_JDR1_JDATA_Msk                 /*!< ADC group injected sequencer rank 1 conversion data */
4244 
4245 /*******************  Bit definition for ADC_JDR2 register  *******************/
4246 #define ADC_JDR2_JDATA_Pos                  (0U)
4247 #define ADC_JDR2_JDATA_Msk                  (0xFFFFUL << ADC_JDR2_JDATA_Pos)    /*!< 0x0000FFFF */
4248 #define ADC_JDR2_JDATA                      ADC_JDR2_JDATA_Msk                 /*!< ADC group injected sequencer rank 2 conversion data */
4249 
4250 /*******************  Bit definition for ADC_JDR3 register  *******************/
4251 #define ADC_JDR3_JDATA_Pos                  (0U)
4252 #define ADC_JDR3_JDATA_Msk                  (0xFFFFUL << ADC_JDR3_JDATA_Pos)    /*!< 0x0000FFFF */
4253 #define ADC_JDR3_JDATA                      ADC_JDR3_JDATA_Msk                 /*!< ADC group injected sequencer rank 3 conversion data */
4254 
4255 /*******************  Bit definition for ADC_JDR4 register  *******************/
4256 #define ADC_JDR4_JDATA_Pos                  (0U)
4257 #define ADC_JDR4_JDATA_Msk                  (0xFFFFUL << ADC_JDR4_JDATA_Pos)    /*!< 0x0000FFFF */
4258 #define ADC_JDR4_JDATA                      ADC_JDR4_JDATA_Msk                 /*!< ADC group injected sequencer rank 4 conversion data */
4259 
4260 /********************  Bit definition for ADC_DR register  ********************/
4261 #define ADC_DR_DATA_Pos                     (0U)
4262 #define ADC_DR_DATA_Msk                     (0xFFFFUL << ADC_DR_DATA_Pos)       /*!< 0x0000FFFF */
4263 #define ADC_DR_DATA                         ADC_DR_DATA_Msk                    /*!< ADC group regular conversion data */
4264 #define ADC_DR_ADC2DATA_Pos                 (16U)
4265 #define ADC_DR_ADC2DATA_Msk                 (0xFFFFUL << ADC_DR_ADC2DATA_Pos)   /*!< 0xFFFF0000 */
4266 #define ADC_DR_ADC2DATA                     ADC_DR_ADC2DATA_Msk                /*!< ADC group regular conversion data for ADC slave, in multimode */
4267 /******************************************************************************/
4268 /*                                                                            */
4269 /*                      Digital to Analog Converter                           */
4270 /*                                                                            */
4271 /******************************************************************************/
4272 
4273 /********************  Bit definition for DAC_CR register  ********************/
4274 #define DAC_CR_EN1_Pos                      (0U)
4275 #define DAC_CR_EN1_Msk                      (0x1UL << DAC_CR_EN1_Pos)           /*!< 0x00000001 */
4276 #define DAC_CR_EN1                          DAC_CR_EN1_Msk                     /*!< DAC channel1 enable */
4277 #define DAC_CR_BOFF1_Pos                    (1U)
4278 #define DAC_CR_BOFF1_Msk                    (0x1UL << DAC_CR_BOFF1_Pos)         /*!< 0x00000002 */
4279 #define DAC_CR_BOFF1                        DAC_CR_BOFF1_Msk                   /*!< DAC channel1 output buffer disable */
4280 #define DAC_CR_TEN1_Pos                     (2U)
4281 #define DAC_CR_TEN1_Msk                     (0x1UL << DAC_CR_TEN1_Pos)          /*!< 0x00000004 */
4282 #define DAC_CR_TEN1                         DAC_CR_TEN1_Msk                    /*!< DAC channel1 Trigger enable */
4283 
4284 #define DAC_CR_TSEL1_Pos                    (3U)
4285 #define DAC_CR_TSEL1_Msk                    (0x7UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000038 */
4286 #define DAC_CR_TSEL1                        DAC_CR_TSEL1_Msk                   /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
4287 #define DAC_CR_TSEL1_0                      (0x1UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000008 */
4288 #define DAC_CR_TSEL1_1                      (0x2UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000010 */
4289 #define DAC_CR_TSEL1_2                      (0x4UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000020 */
4290 
4291 #define DAC_CR_WAVE1_Pos                    (6U)
4292 #define DAC_CR_WAVE1_Msk                    (0x3UL << DAC_CR_WAVE1_Pos)         /*!< 0x000000C0 */
4293 #define DAC_CR_WAVE1                        DAC_CR_WAVE1_Msk                   /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
4294 #define DAC_CR_WAVE1_0                      (0x1UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000040 */
4295 #define DAC_CR_WAVE1_1                      (0x2UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000080 */
4296 
4297 #define DAC_CR_MAMP1_Pos                    (8U)
4298 #define DAC_CR_MAMP1_Msk                    (0xFUL << DAC_CR_MAMP1_Pos)         /*!< 0x00000F00 */
4299 #define DAC_CR_MAMP1                        DAC_CR_MAMP1_Msk                   /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
4300 #define DAC_CR_MAMP1_0                      (0x1UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000100 */
4301 #define DAC_CR_MAMP1_1                      (0x2UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000200 */
4302 #define DAC_CR_MAMP1_2                      (0x4UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000400 */
4303 #define DAC_CR_MAMP1_3                      (0x8UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000800 */
4304 
4305 #define DAC_CR_DMAEN1_Pos                   (12U)
4306 #define DAC_CR_DMAEN1_Msk                   (0x1UL << DAC_CR_DMAEN1_Pos)        /*!< 0x00001000 */
4307 #define DAC_CR_DMAEN1                       DAC_CR_DMAEN1_Msk                  /*!< DAC channel1 DMA enable */
4308 #define DAC_CR_EN2_Pos                      (16U)
4309 #define DAC_CR_EN2_Msk                      (0x1UL << DAC_CR_EN2_Pos)           /*!< 0x00010000 */
4310 #define DAC_CR_EN2                          DAC_CR_EN2_Msk                     /*!< DAC channel2 enable */
4311 #define DAC_CR_BOFF2_Pos                    (17U)
4312 #define DAC_CR_BOFF2_Msk                    (0x1UL << DAC_CR_BOFF2_Pos)         /*!< 0x00020000 */
4313 #define DAC_CR_BOFF2                        DAC_CR_BOFF2_Msk                   /*!< DAC channel2 output buffer disable */
4314 #define DAC_CR_TEN2_Pos                     (18U)
4315 #define DAC_CR_TEN2_Msk                     (0x1UL << DAC_CR_TEN2_Pos)          /*!< 0x00040000 */
4316 #define DAC_CR_TEN2                         DAC_CR_TEN2_Msk                    /*!< DAC channel2 Trigger enable */
4317 
4318 #define DAC_CR_TSEL2_Pos                    (19U)
4319 #define DAC_CR_TSEL2_Msk                    (0x7UL << DAC_CR_TSEL2_Pos)         /*!< 0x00380000 */
4320 #define DAC_CR_TSEL2                        DAC_CR_TSEL2_Msk                   /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
4321 #define DAC_CR_TSEL2_0                      (0x1UL << DAC_CR_TSEL2_Pos)         /*!< 0x00080000 */
4322 #define DAC_CR_TSEL2_1                      (0x2UL << DAC_CR_TSEL2_Pos)         /*!< 0x00100000 */
4323 #define DAC_CR_TSEL2_2                      (0x4UL << DAC_CR_TSEL2_Pos)         /*!< 0x00200000 */
4324 
4325 #define DAC_CR_WAVE2_Pos                    (22U)
4326 #define DAC_CR_WAVE2_Msk                    (0x3UL << DAC_CR_WAVE2_Pos)         /*!< 0x00C00000 */
4327 #define DAC_CR_WAVE2                        DAC_CR_WAVE2_Msk                   /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
4328 #define DAC_CR_WAVE2_0                      (0x1UL << DAC_CR_WAVE2_Pos)         /*!< 0x00400000 */
4329 #define DAC_CR_WAVE2_1                      (0x2UL << DAC_CR_WAVE2_Pos)         /*!< 0x00800000 */
4330 
4331 #define DAC_CR_MAMP2_Pos                    (24U)
4332 #define DAC_CR_MAMP2_Msk                    (0xFUL << DAC_CR_MAMP2_Pos)         /*!< 0x0F000000 */
4333 #define DAC_CR_MAMP2                        DAC_CR_MAMP2_Msk                   /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
4334 #define DAC_CR_MAMP2_0                      (0x1UL << DAC_CR_MAMP2_Pos)         /*!< 0x01000000 */
4335 #define DAC_CR_MAMP2_1                      (0x2UL << DAC_CR_MAMP2_Pos)         /*!< 0x02000000 */
4336 #define DAC_CR_MAMP2_2                      (0x4UL << DAC_CR_MAMP2_Pos)         /*!< 0x04000000 */
4337 #define DAC_CR_MAMP2_3                      (0x8UL << DAC_CR_MAMP2_Pos)         /*!< 0x08000000 */
4338 
4339 #define DAC_CR_DMAEN2_Pos                   (28U)
4340 #define DAC_CR_DMAEN2_Msk                   (0x1UL << DAC_CR_DMAEN2_Pos)        /*!< 0x10000000 */
4341 #define DAC_CR_DMAEN2                       DAC_CR_DMAEN2_Msk                  /*!< DAC channel2 DMA enabled */
4342 
4343 
4344 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
4345 #define DAC_SWTRIGR_SWTRIG1_Pos             (0U)
4346 #define DAC_SWTRIGR_SWTRIG1_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)  /*!< 0x00000001 */
4347 #define DAC_SWTRIGR_SWTRIG1                 DAC_SWTRIGR_SWTRIG1_Msk            /*!< DAC channel1 software trigger */
4348 #define DAC_SWTRIGR_SWTRIG2_Pos             (1U)
4349 #define DAC_SWTRIGR_SWTRIG2_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)  /*!< 0x00000002 */
4350 #define DAC_SWTRIGR_SWTRIG2                 DAC_SWTRIGR_SWTRIG2_Msk            /*!< DAC channel2 software trigger */
4351 
4352 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
4353 #define DAC_DHR12R1_DACC1DHR_Pos            (0U)
4354 #define DAC_DHR12R1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
4355 #define DAC_DHR12R1_DACC1DHR                DAC_DHR12R1_DACC1DHR_Msk           /*!< DAC channel1 12-bit Right aligned data */
4356 
4357 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
4358 #define DAC_DHR12L1_DACC1DHR_Pos            (4U)
4359 #define DAC_DHR12L1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
4360 #define DAC_DHR12L1_DACC1DHR                DAC_DHR12L1_DACC1DHR_Msk           /*!< DAC channel1 12-bit Left aligned data */
4361 
4362 /******************  Bit definition for DAC_DHR8R1 register  ******************/
4363 #define DAC_DHR8R1_DACC1DHR_Pos             (0U)
4364 #define DAC_DHR8R1_DACC1DHR_Msk             (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
4365 #define DAC_DHR8R1_DACC1DHR                 DAC_DHR8R1_DACC1DHR_Msk            /*!< DAC channel1 8-bit Right aligned data */
4366 
4367 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
4368 #define DAC_DHR12R2_DACC2DHR_Pos            (0U)
4369 #define DAC_DHR12R2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
4370 #define DAC_DHR12R2_DACC2DHR                DAC_DHR12R2_DACC2DHR_Msk           /*!< DAC channel2 12-bit Right aligned data */
4371 
4372 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
4373 #define DAC_DHR12L2_DACC2DHR_Pos            (4U)
4374 #define DAC_DHR12L2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
4375 #define DAC_DHR12L2_DACC2DHR                DAC_DHR12L2_DACC2DHR_Msk           /*!< DAC channel2 12-bit Left aligned data */
4376 
4377 /******************  Bit definition for DAC_DHR8R2 register  ******************/
4378 #define DAC_DHR8R2_DACC2DHR_Pos             (0U)
4379 #define DAC_DHR8R2_DACC2DHR_Msk             (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
4380 #define DAC_DHR8R2_DACC2DHR                 DAC_DHR8R2_DACC2DHR_Msk            /*!< DAC channel2 8-bit Right aligned data */
4381 
4382 /*****************  Bit definition for DAC_DHR12RD register  ******************/
4383 #define DAC_DHR12RD_DACC1DHR_Pos            (0U)
4384 #define DAC_DHR12RD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
4385 #define DAC_DHR12RD_DACC1DHR                DAC_DHR12RD_DACC1DHR_Msk           /*!< DAC channel1 12-bit Right aligned data */
4386 #define DAC_DHR12RD_DACC2DHR_Pos            (16U)
4387 #define DAC_DHR12RD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
4388 #define DAC_DHR12RD_DACC2DHR                DAC_DHR12RD_DACC2DHR_Msk           /*!< DAC channel2 12-bit Right aligned data */
4389 
4390 /*****************  Bit definition for DAC_DHR12LD register  ******************/
4391 #define DAC_DHR12LD_DACC1DHR_Pos            (4U)
4392 #define DAC_DHR12LD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
4393 #define DAC_DHR12LD_DACC1DHR                DAC_DHR12LD_DACC1DHR_Msk           /*!< DAC channel1 12-bit Left aligned data */
4394 #define DAC_DHR12LD_DACC2DHR_Pos            (20U)
4395 #define DAC_DHR12LD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
4396 #define DAC_DHR12LD_DACC2DHR                DAC_DHR12LD_DACC2DHR_Msk           /*!< DAC channel2 12-bit Left aligned data */
4397 
4398 /******************  Bit definition for DAC_DHR8RD register  ******************/
4399 #define DAC_DHR8RD_DACC1DHR_Pos             (0U)
4400 #define DAC_DHR8RD_DACC1DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
4401 #define DAC_DHR8RD_DACC1DHR                 DAC_DHR8RD_DACC1DHR_Msk            /*!< DAC channel1 8-bit Right aligned data */
4402 #define DAC_DHR8RD_DACC2DHR_Pos             (8U)
4403 #define DAC_DHR8RD_DACC2DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
4404 #define DAC_DHR8RD_DACC2DHR                 DAC_DHR8RD_DACC2DHR_Msk            /*!< DAC channel2 8-bit Right aligned data */
4405 
4406 /*******************  Bit definition for DAC_DOR1 register  *******************/
4407 #define DAC_DOR1_DACC1DOR_Pos               (0U)
4408 #define DAC_DOR1_DACC1DOR_Msk               (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)  /*!< 0x00000FFF */
4409 #define DAC_DOR1_DACC1DOR                   DAC_DOR1_DACC1DOR_Msk              /*!< DAC channel1 data output */
4410 
4411 /*******************  Bit definition for DAC_DOR2 register  *******************/
4412 #define DAC_DOR2_DACC2DOR_Pos               (0U)
4413 #define DAC_DOR2_DACC2DOR_Msk               (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)  /*!< 0x00000FFF */
4414 #define DAC_DOR2_DACC2DOR                   DAC_DOR2_DACC2DOR_Msk              /*!< DAC channel2 data output */
4415 
4416 
4417 
4418 /*****************************************************************************/
4419 /*                                                                           */
4420 /*                               Timers (TIM)                                */
4421 /*                                                                           */
4422 /*****************************************************************************/
4423 /*******************  Bit definition for TIM_CR1 register  *******************/
4424 #define TIM_CR1_CEN_Pos                     (0U)
4425 #define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)          /*!< 0x00000001 */
4426 #define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                    /*!<Counter enable */
4427 #define TIM_CR1_UDIS_Pos                    (1U)
4428 #define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)         /*!< 0x00000002 */
4429 #define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                   /*!<Update disable */
4430 #define TIM_CR1_URS_Pos                     (2U)
4431 #define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)          /*!< 0x00000004 */
4432 #define TIM_CR1_URS                         TIM_CR1_URS_Msk                    /*!<Update request source */
4433 #define TIM_CR1_OPM_Pos                     (3U)
4434 #define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)          /*!< 0x00000008 */
4435 #define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                    /*!<One pulse mode */
4436 #define TIM_CR1_DIR_Pos                     (4U)
4437 #define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)          /*!< 0x00000010 */
4438 #define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                    /*!<Direction */
4439 
4440 #define TIM_CR1_CMS_Pos                     (5U)
4441 #define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)          /*!< 0x00000060 */
4442 #define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                    /*!<CMS[1:0] bits (Center-aligned mode selection) */
4443 #define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)          /*!< 0x00000020 */
4444 #define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)          /*!< 0x00000040 */
4445 
4446 #define TIM_CR1_ARPE_Pos                    (7U)
4447 #define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)         /*!< 0x00000080 */
4448 #define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                   /*!<Auto-reload preload enable */
4449 
4450 #define TIM_CR1_CKD_Pos                     (8U)
4451 #define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)          /*!< 0x00000300 */
4452 #define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                    /*!<CKD[1:0] bits (clock division) */
4453 #define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)          /*!< 0x00000100 */
4454 #define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)          /*!< 0x00000200 */
4455 
4456 /*******************  Bit definition for TIM_CR2 register  *******************/
4457 #define TIM_CR2_CCPC_Pos                    (0U)
4458 #define TIM_CR2_CCPC_Msk                    (0x1UL << TIM_CR2_CCPC_Pos)         /*!< 0x00000001 */
4459 #define TIM_CR2_CCPC                        TIM_CR2_CCPC_Msk                   /*!<Capture/Compare Preloaded Control */
4460 #define TIM_CR2_CCUS_Pos                    (2U)
4461 #define TIM_CR2_CCUS_Msk                    (0x1UL << TIM_CR2_CCUS_Pos)         /*!< 0x00000004 */
4462 #define TIM_CR2_CCUS                        TIM_CR2_CCUS_Msk                   /*!<Capture/Compare Control Update Selection */
4463 #define TIM_CR2_CCDS_Pos                    (3U)
4464 #define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)         /*!< 0x00000008 */
4465 #define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                   /*!<Capture/Compare DMA Selection */
4466 
4467 #define TIM_CR2_MMS_Pos                     (4U)
4468 #define TIM_CR2_MMS_Msk                     (0x7UL << TIM_CR2_MMS_Pos)          /*!< 0x00000070 */
4469 #define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                    /*!<MMS[2:0] bits (Master Mode Selection) */
4470 #define TIM_CR2_MMS_0                       (0x1UL << TIM_CR2_MMS_Pos)          /*!< 0x00000010 */
4471 #define TIM_CR2_MMS_1                       (0x2UL << TIM_CR2_MMS_Pos)          /*!< 0x00000020 */
4472 #define TIM_CR2_MMS_2                       (0x4UL << TIM_CR2_MMS_Pos)          /*!< 0x00000040 */
4473 
4474 #define TIM_CR2_TI1S_Pos                    (7U)
4475 #define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)         /*!< 0x00000080 */
4476 #define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                   /*!<TI1 Selection */
4477 #define TIM_CR2_OIS1_Pos                    (8U)
4478 #define TIM_CR2_OIS1_Msk                    (0x1UL << TIM_CR2_OIS1_Pos)         /*!< 0x00000100 */
4479 #define TIM_CR2_OIS1                        TIM_CR2_OIS1_Msk                   /*!<Output Idle state 1 (OC1 output) */
4480 #define TIM_CR2_OIS1N_Pos                   (9U)
4481 #define TIM_CR2_OIS1N_Msk                   (0x1UL << TIM_CR2_OIS1N_Pos)        /*!< 0x00000200 */
4482 #define TIM_CR2_OIS1N                       TIM_CR2_OIS1N_Msk                  /*!<Output Idle state 1 (OC1N output) */
4483 #define TIM_CR2_OIS2_Pos                    (10U)
4484 #define TIM_CR2_OIS2_Msk                    (0x1UL << TIM_CR2_OIS2_Pos)         /*!< 0x00000400 */
4485 #define TIM_CR2_OIS2                        TIM_CR2_OIS2_Msk                   /*!<Output Idle state 2 (OC2 output) */
4486 #define TIM_CR2_OIS2N_Pos                   (11U)
4487 #define TIM_CR2_OIS2N_Msk                   (0x1UL << TIM_CR2_OIS2N_Pos)        /*!< 0x00000800 */
4488 #define TIM_CR2_OIS2N                       TIM_CR2_OIS2N_Msk                  /*!<Output Idle state 2 (OC2N output) */
4489 #define TIM_CR2_OIS3_Pos                    (12U)
4490 #define TIM_CR2_OIS3_Msk                    (0x1UL << TIM_CR2_OIS3_Pos)         /*!< 0x00001000 */
4491 #define TIM_CR2_OIS3                        TIM_CR2_OIS3_Msk                   /*!<Output Idle state 3 (OC3 output) */
4492 #define TIM_CR2_OIS3N_Pos                   (13U)
4493 #define TIM_CR2_OIS3N_Msk                   (0x1UL << TIM_CR2_OIS3N_Pos)        /*!< 0x00002000 */
4494 #define TIM_CR2_OIS3N                       TIM_CR2_OIS3N_Msk                  /*!<Output Idle state 3 (OC3N output) */
4495 #define TIM_CR2_OIS4_Pos                    (14U)
4496 #define TIM_CR2_OIS4_Msk                    (0x1UL << TIM_CR2_OIS4_Pos)         /*!< 0x00004000 */
4497 #define TIM_CR2_OIS4                        TIM_CR2_OIS4_Msk                   /*!<Output Idle state 4 (OC4 output) */
4498 
4499 /*******************  Bit definition for TIM_SMCR register  ******************/
4500 #define TIM_SMCR_SMS_Pos                    (0U)
4501 #define TIM_SMCR_SMS_Msk                    (0x7UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000007 */
4502 #define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                   /*!<SMS[2:0] bits (Slave mode selection) */
4503 #define TIM_SMCR_SMS_0                      (0x1UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
4504 #define TIM_SMCR_SMS_1                      (0x2UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
4505 #define TIM_SMCR_SMS_2                      (0x4UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
4506 
4507 #define TIM_SMCR_TS_Pos                     (4U)
4508 #define TIM_SMCR_TS_Msk                     (0x7UL << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */
4509 #define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */
4510 #define TIM_SMCR_TS_0                       (0x1UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
4511 #define TIM_SMCR_TS_1                       (0x2UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
4512 #define TIM_SMCR_TS_2                       (0x4UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
4513 
4514 #define TIM_SMCR_MSM_Pos                    (7U)
4515 #define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)         /*!< 0x00000080 */
4516 #define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                   /*!<Master/slave mode */
4517 
4518 #define TIM_SMCR_ETF_Pos                    (8U)
4519 #define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)         /*!< 0x00000F00 */
4520 #define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                   /*!<ETF[3:0] bits (External trigger filter) */
4521 #define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000100 */
4522 #define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000200 */
4523 #define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000400 */
4524 #define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000800 */
4525 
4526 #define TIM_SMCR_ETPS_Pos                   (12U)
4527 #define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00003000 */
4528 #define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                  /*!<ETPS[1:0] bits (External trigger prescaler) */
4529 #define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00001000 */
4530 #define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00002000 */
4531 
4532 #define TIM_SMCR_ECE_Pos                    (14U)
4533 #define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)         /*!< 0x00004000 */
4534 #define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                   /*!<External clock enable */
4535 #define TIM_SMCR_ETP_Pos                    (15U)
4536 #define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)         /*!< 0x00008000 */
4537 #define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                   /*!<External trigger polarity */
4538 
4539 /*******************  Bit definition for TIM_DIER register  ******************/
4540 #define TIM_DIER_UIE_Pos                    (0U)
4541 #define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)         /*!< 0x00000001 */
4542 #define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                   /*!<Update interrupt enable */
4543 #define TIM_DIER_CC1IE_Pos                  (1U)
4544 #define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)       /*!< 0x00000002 */
4545 #define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                 /*!<Capture/Compare 1 interrupt enable */
4546 #define TIM_DIER_CC2IE_Pos                  (2U)
4547 #define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)       /*!< 0x00000004 */
4548 #define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                 /*!<Capture/Compare 2 interrupt enable */
4549 #define TIM_DIER_CC3IE_Pos                  (3U)
4550 #define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)       /*!< 0x00000008 */
4551 #define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                 /*!<Capture/Compare 3 interrupt enable */
4552 #define TIM_DIER_CC4IE_Pos                  (4U)
4553 #define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)       /*!< 0x00000010 */
4554 #define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                 /*!<Capture/Compare 4 interrupt enable */
4555 #define TIM_DIER_COMIE_Pos                  (5U)
4556 #define TIM_DIER_COMIE_Msk                  (0x1UL << TIM_DIER_COMIE_Pos)       /*!< 0x00000020 */
4557 #define TIM_DIER_COMIE                      TIM_DIER_COMIE_Msk                 /*!<COM interrupt enable */
4558 #define TIM_DIER_TIE_Pos                    (6U)
4559 #define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)         /*!< 0x00000040 */
4560 #define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                   /*!<Trigger interrupt enable */
4561 #define TIM_DIER_BIE_Pos                    (7U)
4562 #define TIM_DIER_BIE_Msk                    (0x1UL << TIM_DIER_BIE_Pos)         /*!< 0x00000080 */
4563 #define TIM_DIER_BIE                        TIM_DIER_BIE_Msk                   /*!<Break interrupt enable */
4564 #define TIM_DIER_UDE_Pos                    (8U)
4565 #define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)         /*!< 0x00000100 */
4566 #define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                   /*!<Update DMA request enable */
4567 #define TIM_DIER_CC1DE_Pos                  (9U)
4568 #define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)       /*!< 0x00000200 */
4569 #define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                 /*!<Capture/Compare 1 DMA request enable */
4570 #define TIM_DIER_CC2DE_Pos                  (10U)
4571 #define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)       /*!< 0x00000400 */
4572 #define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                 /*!<Capture/Compare 2 DMA request enable */
4573 #define TIM_DIER_CC3DE_Pos                  (11U)
4574 #define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)       /*!< 0x00000800 */
4575 #define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                 /*!<Capture/Compare 3 DMA request enable */
4576 #define TIM_DIER_CC4DE_Pos                  (12U)
4577 #define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)       /*!< 0x00001000 */
4578 #define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                 /*!<Capture/Compare 4 DMA request enable */
4579 #define TIM_DIER_COMDE_Pos                  (13U)
4580 #define TIM_DIER_COMDE_Msk                  (0x1UL << TIM_DIER_COMDE_Pos)       /*!< 0x00002000 */
4581 #define TIM_DIER_COMDE                      TIM_DIER_COMDE_Msk                 /*!<COM DMA request enable */
4582 #define TIM_DIER_TDE_Pos                    (14U)
4583 #define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)         /*!< 0x00004000 */
4584 #define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                   /*!<Trigger DMA request enable */
4585 
4586 /********************  Bit definition for TIM_SR register  *******************/
4587 #define TIM_SR_UIF_Pos                      (0U)
4588 #define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)           /*!< 0x00000001 */
4589 #define TIM_SR_UIF                          TIM_SR_UIF_Msk                     /*!<Update interrupt Flag */
4590 #define TIM_SR_CC1IF_Pos                    (1U)
4591 #define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)         /*!< 0x00000002 */
4592 #define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                   /*!<Capture/Compare 1 interrupt Flag */
4593 #define TIM_SR_CC2IF_Pos                    (2U)
4594 #define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)         /*!< 0x00000004 */
4595 #define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                   /*!<Capture/Compare 2 interrupt Flag */
4596 #define TIM_SR_CC3IF_Pos                    (3U)
4597 #define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)         /*!< 0x00000008 */
4598 #define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                   /*!<Capture/Compare 3 interrupt Flag */
4599 #define TIM_SR_CC4IF_Pos                    (4U)
4600 #define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)         /*!< 0x00000010 */
4601 #define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                   /*!<Capture/Compare 4 interrupt Flag */
4602 #define TIM_SR_COMIF_Pos                    (5U)
4603 #define TIM_SR_COMIF_Msk                    (0x1UL << TIM_SR_COMIF_Pos)         /*!< 0x00000020 */
4604 #define TIM_SR_COMIF                        TIM_SR_COMIF_Msk                   /*!<COM interrupt Flag */
4605 #define TIM_SR_TIF_Pos                      (6U)
4606 #define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)           /*!< 0x00000040 */
4607 #define TIM_SR_TIF                          TIM_SR_TIF_Msk                     /*!<Trigger interrupt Flag */
4608 #define TIM_SR_BIF_Pos                      (7U)
4609 #define TIM_SR_BIF_Msk                      (0x1UL << TIM_SR_BIF_Pos)           /*!< 0x00000080 */
4610 #define TIM_SR_BIF                          TIM_SR_BIF_Msk                     /*!<Break interrupt Flag */
4611 #define TIM_SR_CC1OF_Pos                    (9U)
4612 #define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)         /*!< 0x00000200 */
4613 #define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                   /*!<Capture/Compare 1 Overcapture Flag */
4614 #define TIM_SR_CC2OF_Pos                    (10U)
4615 #define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)         /*!< 0x00000400 */
4616 #define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                   /*!<Capture/Compare 2 Overcapture Flag */
4617 #define TIM_SR_CC3OF_Pos                    (11U)
4618 #define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)         /*!< 0x00000800 */
4619 #define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                   /*!<Capture/Compare 3 Overcapture Flag */
4620 #define TIM_SR_CC4OF_Pos                    (12U)
4621 #define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)         /*!< 0x00001000 */
4622 #define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                   /*!<Capture/Compare 4 Overcapture Flag */
4623 
4624 /*******************  Bit definition for TIM_EGR register  *******************/
4625 #define TIM_EGR_UG_Pos                      (0U)
4626 #define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)           /*!< 0x00000001 */
4627 #define TIM_EGR_UG                          TIM_EGR_UG_Msk                     /*!<Update Generation */
4628 #define TIM_EGR_CC1G_Pos                    (1U)
4629 #define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)         /*!< 0x00000002 */
4630 #define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                   /*!<Capture/Compare 1 Generation */
4631 #define TIM_EGR_CC2G_Pos                    (2U)
4632 #define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)         /*!< 0x00000004 */
4633 #define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                   /*!<Capture/Compare 2 Generation */
4634 #define TIM_EGR_CC3G_Pos                    (3U)
4635 #define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)         /*!< 0x00000008 */
4636 #define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                   /*!<Capture/Compare 3 Generation */
4637 #define TIM_EGR_CC4G_Pos                    (4U)
4638 #define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)         /*!< 0x00000010 */
4639 #define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                   /*!<Capture/Compare 4 Generation */
4640 #define TIM_EGR_COMG_Pos                    (5U)
4641 #define TIM_EGR_COMG_Msk                    (0x1UL << TIM_EGR_COMG_Pos)         /*!< 0x00000020 */
4642 #define TIM_EGR_COMG                        TIM_EGR_COMG_Msk                   /*!<Capture/Compare Control Update Generation */
4643 #define TIM_EGR_TG_Pos                      (6U)
4644 #define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)           /*!< 0x00000040 */
4645 #define TIM_EGR_TG                          TIM_EGR_TG_Msk                     /*!<Trigger Generation */
4646 #define TIM_EGR_BG_Pos                      (7U)
4647 #define TIM_EGR_BG_Msk                      (0x1UL << TIM_EGR_BG_Pos)           /*!< 0x00000080 */
4648 #define TIM_EGR_BG                          TIM_EGR_BG_Msk                     /*!<Break Generation */
4649 
4650 /******************  Bit definition for TIM_CCMR1 register  ******************/
4651 #define TIM_CCMR1_CC1S_Pos                  (0U)
4652 #define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000003 */
4653 #define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                 /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
4654 #define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000001 */
4655 #define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000002 */
4656 
4657 #define TIM_CCMR1_OC1FE_Pos                 (2U)
4658 #define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)      /*!< 0x00000004 */
4659 #define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                /*!<Output Compare 1 Fast enable */
4660 #define TIM_CCMR1_OC1PE_Pos                 (3U)
4661 #define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)      /*!< 0x00000008 */
4662 #define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                /*!<Output Compare 1 Preload enable */
4663 
4664 #define TIM_CCMR1_OC1M_Pos                  (4U)
4665 #define TIM_CCMR1_OC1M_Msk                  (0x7UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000070 */
4666 #define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                 /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
4667 #define TIM_CCMR1_OC1M_0                    (0x1UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000010 */
4668 #define TIM_CCMR1_OC1M_1                    (0x2UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000020 */
4669 #define TIM_CCMR1_OC1M_2                    (0x4UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000040 */
4670 
4671 #define TIM_CCMR1_OC1CE_Pos                 (7U)
4672 #define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)      /*!< 0x00000080 */
4673 #define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                /*!<Output Compare 1Clear Enable */
4674 
4675 #define TIM_CCMR1_CC2S_Pos                  (8U)
4676 #define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000300 */
4677 #define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                 /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
4678 #define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000100 */
4679 #define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000200 */
4680 
4681 #define TIM_CCMR1_OC2FE_Pos                 (10U)
4682 #define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)      /*!< 0x00000400 */
4683 #define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                /*!<Output Compare 2 Fast enable */
4684 #define TIM_CCMR1_OC2PE_Pos                 (11U)
4685 #define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)      /*!< 0x00000800 */
4686 #define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                /*!<Output Compare 2 Preload enable */
4687 
4688 #define TIM_CCMR1_OC2M_Pos                  (12U)
4689 #define TIM_CCMR1_OC2M_Msk                  (0x7UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00007000 */
4690 #define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                 /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
4691 #define TIM_CCMR1_OC2M_0                    (0x1UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00001000 */
4692 #define TIM_CCMR1_OC2M_1                    (0x2UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00002000 */
4693 #define TIM_CCMR1_OC2M_2                    (0x4UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00004000 */
4694 
4695 #define TIM_CCMR1_OC2CE_Pos                 (15U)
4696 #define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)      /*!< 0x00008000 */
4697 #define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                /*!<Output Compare 2 Clear Enable */
4698 
4699 /*---------------------------------------------------------------------------*/
4700 
4701 #define TIM_CCMR1_IC1PSC_Pos                (2U)
4702 #define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x0000000C */
4703 #define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk               /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
4704 #define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000004 */
4705 #define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000008 */
4706 
4707 #define TIM_CCMR1_IC1F_Pos                  (4U)
4708 #define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)       /*!< 0x000000F0 */
4709 #define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                 /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
4710 #define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000010 */
4711 #define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000020 */
4712 #define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000040 */
4713 #define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000080 */
4714 
4715 #define TIM_CCMR1_IC2PSC_Pos                (10U)
4716 #define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000C00 */
4717 #define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk               /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
4718 #define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000400 */
4719 #define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000800 */
4720 
4721 #define TIM_CCMR1_IC2F_Pos                  (12U)
4722 #define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)       /*!< 0x0000F000 */
4723 #define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                 /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
4724 #define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00001000 */
4725 #define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00002000 */
4726 #define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00004000 */
4727 #define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00008000 */
4728 
4729 /******************  Bit definition for TIM_CCMR2 register  ******************/
4730 #define TIM_CCMR2_CC3S_Pos                  (0U)
4731 #define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000003 */
4732 #define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                 /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
4733 #define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000001 */
4734 #define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000002 */
4735 
4736 #define TIM_CCMR2_OC3FE_Pos                 (2U)
4737 #define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)      /*!< 0x00000004 */
4738 #define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                /*!<Output Compare 3 Fast enable */
4739 #define TIM_CCMR2_OC3PE_Pos                 (3U)
4740 #define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)      /*!< 0x00000008 */
4741 #define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                /*!<Output Compare 3 Preload enable */
4742 
4743 #define TIM_CCMR2_OC3M_Pos                  (4U)
4744 #define TIM_CCMR2_OC3M_Msk                  (0x7UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000070 */
4745 #define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                 /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
4746 #define TIM_CCMR2_OC3M_0                    (0x1UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000010 */
4747 #define TIM_CCMR2_OC3M_1                    (0x2UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000020 */
4748 #define TIM_CCMR2_OC3M_2                    (0x4UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000040 */
4749 
4750 #define TIM_CCMR2_OC3CE_Pos                 (7U)
4751 #define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)      /*!< 0x00000080 */
4752 #define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                /*!<Output Compare 3 Clear Enable */
4753 
4754 #define TIM_CCMR2_CC4S_Pos                  (8U)
4755 #define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000300 */
4756 #define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                 /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
4757 #define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000100 */
4758 #define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000200 */
4759 
4760 #define TIM_CCMR2_OC4FE_Pos                 (10U)
4761 #define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)      /*!< 0x00000400 */
4762 #define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                /*!<Output Compare 4 Fast enable */
4763 #define TIM_CCMR2_OC4PE_Pos                 (11U)
4764 #define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)      /*!< 0x00000800 */
4765 #define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                /*!<Output Compare 4 Preload enable */
4766 
4767 #define TIM_CCMR2_OC4M_Pos                  (12U)
4768 #define TIM_CCMR2_OC4M_Msk                  (0x7UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00007000 */
4769 #define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                 /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
4770 #define TIM_CCMR2_OC4M_0                    (0x1UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00001000 */
4771 #define TIM_CCMR2_OC4M_1                    (0x2UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00002000 */
4772 #define TIM_CCMR2_OC4M_2                    (0x4UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00004000 */
4773 
4774 #define TIM_CCMR2_OC4CE_Pos                 (15U)
4775 #define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)      /*!< 0x00008000 */
4776 #define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                /*!<Output Compare 4 Clear Enable */
4777 
4778 /*---------------------------------------------------------------------------*/
4779 
4780 #define TIM_CCMR2_IC3PSC_Pos                (2U)
4781 #define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x0000000C */
4782 #define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk               /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
4783 #define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000004 */
4784 #define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000008 */
4785 
4786 #define TIM_CCMR2_IC3F_Pos                  (4U)
4787 #define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)       /*!< 0x000000F0 */
4788 #define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                 /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
4789 #define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000010 */
4790 #define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000020 */
4791 #define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000040 */
4792 #define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000080 */
4793 
4794 #define TIM_CCMR2_IC4PSC_Pos                (10U)
4795 #define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000C00 */
4796 #define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk               /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
4797 #define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000400 */
4798 #define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000800 */
4799 
4800 #define TIM_CCMR2_IC4F_Pos                  (12U)
4801 #define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)       /*!< 0x0000F000 */
4802 #define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                 /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
4803 #define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00001000 */
4804 #define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00002000 */
4805 #define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00004000 */
4806 #define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00008000 */
4807 
4808 /*******************  Bit definition for TIM_CCER register  ******************/
4809 #define TIM_CCER_CC1E_Pos                   (0U)
4810 #define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)        /*!< 0x00000001 */
4811 #define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                  /*!<Capture/Compare 1 output enable */
4812 #define TIM_CCER_CC1P_Pos                   (1U)
4813 #define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)        /*!< 0x00000002 */
4814 #define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                  /*!<Capture/Compare 1 output Polarity */
4815 #define TIM_CCER_CC1NE_Pos                  (2U)
4816 #define TIM_CCER_CC1NE_Msk                  (0x1UL << TIM_CCER_CC1NE_Pos)       /*!< 0x00000004 */
4817 #define TIM_CCER_CC1NE                      TIM_CCER_CC1NE_Msk                 /*!<Capture/Compare 1 Complementary output enable */
4818 #define TIM_CCER_CC1NP_Pos                  (3U)
4819 #define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)       /*!< 0x00000008 */
4820 #define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                 /*!<Capture/Compare 1 Complementary output Polarity */
4821 #define TIM_CCER_CC2E_Pos                   (4U)
4822 #define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)        /*!< 0x00000010 */
4823 #define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                  /*!<Capture/Compare 2 output enable */
4824 #define TIM_CCER_CC2P_Pos                   (5U)
4825 #define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)        /*!< 0x00000020 */
4826 #define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                  /*!<Capture/Compare 2 output Polarity */
4827 #define TIM_CCER_CC2NE_Pos                  (6U)
4828 #define TIM_CCER_CC2NE_Msk                  (0x1UL << TIM_CCER_CC2NE_Pos)       /*!< 0x00000040 */
4829 #define TIM_CCER_CC2NE                      TIM_CCER_CC2NE_Msk                 /*!<Capture/Compare 2 Complementary output enable */
4830 #define TIM_CCER_CC2NP_Pos                  (7U)
4831 #define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)       /*!< 0x00000080 */
4832 #define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                 /*!<Capture/Compare 2 Complementary output Polarity */
4833 #define TIM_CCER_CC3E_Pos                   (8U)
4834 #define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)        /*!< 0x00000100 */
4835 #define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                  /*!<Capture/Compare 3 output enable */
4836 #define TIM_CCER_CC3P_Pos                   (9U)
4837 #define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)        /*!< 0x00000200 */
4838 #define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                  /*!<Capture/Compare 3 output Polarity */
4839 #define TIM_CCER_CC3NE_Pos                  (10U)
4840 #define TIM_CCER_CC3NE_Msk                  (0x1UL << TIM_CCER_CC3NE_Pos)       /*!< 0x00000400 */
4841 #define TIM_CCER_CC3NE                      TIM_CCER_CC3NE_Msk                 /*!<Capture/Compare 3 Complementary output enable */
4842 #define TIM_CCER_CC3NP_Pos                  (11U)
4843 #define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)       /*!< 0x00000800 */
4844 #define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                 /*!<Capture/Compare 3 Complementary output Polarity */
4845 #define TIM_CCER_CC4E_Pos                   (12U)
4846 #define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)        /*!< 0x00001000 */
4847 #define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                  /*!<Capture/Compare 4 output enable */
4848 #define TIM_CCER_CC4P_Pos                   (13U)
4849 #define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */
4850 #define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */
4851 
4852 /*******************  Bit definition for TIM_CNT register  *******************/
4853 #define TIM_CNT_CNT_Pos                     (0U)
4854 #define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)   /*!< 0xFFFFFFFF */
4855 #define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                    /*!<Counter Value */
4856 
4857 /*******************  Bit definition for TIM_PSC register  *******************/
4858 #define TIM_PSC_PSC_Pos                     (0U)
4859 #define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)       /*!< 0x0000FFFF */
4860 #define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                    /*!<Prescaler Value */
4861 
4862 /*******************  Bit definition for TIM_ARR register  *******************/
4863 #define TIM_ARR_ARR_Pos                     (0U)
4864 #define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)   /*!< 0xFFFFFFFF */
4865 #define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                    /*!<actual auto-reload Value */
4866 
4867 /*******************  Bit definition for TIM_RCR register  *******************/
4868 #define TIM_RCR_REP_Pos                     (0U)
4869 #define TIM_RCR_REP_Msk                     (0xFFUL << TIM_RCR_REP_Pos)         /*!< 0x000000FF */
4870 #define TIM_RCR_REP                         TIM_RCR_REP_Msk                    /*!<Repetition Counter Value */
4871 
4872 /*******************  Bit definition for TIM_CCR1 register  ******************/
4873 #define TIM_CCR1_CCR1_Pos                   (0U)
4874 #define TIM_CCR1_CCR1_Msk                   (0xFFFFUL << TIM_CCR1_CCR1_Pos)     /*!< 0x0000FFFF */
4875 #define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                  /*!<Capture/Compare 1 Value */
4876 
4877 /*******************  Bit definition for TIM_CCR2 register  ******************/
4878 #define TIM_CCR2_CCR2_Pos                   (0U)
4879 #define TIM_CCR2_CCR2_Msk                   (0xFFFFUL << TIM_CCR2_CCR2_Pos)     /*!< 0x0000FFFF */
4880 #define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                  /*!<Capture/Compare 2 Value */
4881 
4882 /*******************  Bit definition for TIM_CCR3 register  ******************/
4883 #define TIM_CCR3_CCR3_Pos                   (0U)
4884 #define TIM_CCR3_CCR3_Msk                   (0xFFFFUL << TIM_CCR3_CCR3_Pos)     /*!< 0x0000FFFF */
4885 #define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                  /*!<Capture/Compare 3 Value */
4886 
4887 /*******************  Bit definition for TIM_CCR4 register  ******************/
4888 #define TIM_CCR4_CCR4_Pos                   (0U)
4889 #define TIM_CCR4_CCR4_Msk                   (0xFFFFUL << TIM_CCR4_CCR4_Pos)     /*!< 0x0000FFFF */
4890 #define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                  /*!<Capture/Compare 4 Value */
4891 
4892 /*******************  Bit definition for TIM_BDTR register  ******************/
4893 #define TIM_BDTR_DTG_Pos                    (0U)
4894 #define TIM_BDTR_DTG_Msk                    (0xFFUL << TIM_BDTR_DTG_Pos)        /*!< 0x000000FF */
4895 #define TIM_BDTR_DTG                        TIM_BDTR_DTG_Msk                   /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
4896 #define TIM_BDTR_DTG_0                      (0x01UL << TIM_BDTR_DTG_Pos)        /*!< 0x00000001 */
4897 #define TIM_BDTR_DTG_1                      (0x02UL << TIM_BDTR_DTG_Pos)        /*!< 0x00000002 */
4898 #define TIM_BDTR_DTG_2                      (0x04UL << TIM_BDTR_DTG_Pos)        /*!< 0x00000004 */
4899 #define TIM_BDTR_DTG_3                      (0x08UL << TIM_BDTR_DTG_Pos)        /*!< 0x00000008 */
4900 #define TIM_BDTR_DTG_4                      (0x10UL << TIM_BDTR_DTG_Pos)        /*!< 0x00000010 */
4901 #define TIM_BDTR_DTG_5                      (0x20UL << TIM_BDTR_DTG_Pos)        /*!< 0x00000020 */
4902 #define TIM_BDTR_DTG_6                      (0x40UL << TIM_BDTR_DTG_Pos)        /*!< 0x00000040 */
4903 #define TIM_BDTR_DTG_7                      (0x80UL << TIM_BDTR_DTG_Pos)        /*!< 0x00000080 */
4904 
4905 #define TIM_BDTR_LOCK_Pos                   (8U)
4906 #define TIM_BDTR_LOCK_Msk                   (0x3UL << TIM_BDTR_LOCK_Pos)        /*!< 0x00000300 */
4907 #define TIM_BDTR_LOCK                       TIM_BDTR_LOCK_Msk                  /*!<LOCK[1:0] bits (Lock Configuration) */
4908 #define TIM_BDTR_LOCK_0                     (0x1UL << TIM_BDTR_LOCK_Pos)        /*!< 0x00000100 */
4909 #define TIM_BDTR_LOCK_1                     (0x2UL << TIM_BDTR_LOCK_Pos)        /*!< 0x00000200 */
4910 
4911 #define TIM_BDTR_OSSI_Pos                   (10U)
4912 #define TIM_BDTR_OSSI_Msk                   (0x1UL << TIM_BDTR_OSSI_Pos)        /*!< 0x00000400 */
4913 #define TIM_BDTR_OSSI                       TIM_BDTR_OSSI_Msk                  /*!<Off-State Selection for Idle mode */
4914 #define TIM_BDTR_OSSR_Pos                   (11U)
4915 #define TIM_BDTR_OSSR_Msk                   (0x1UL << TIM_BDTR_OSSR_Pos)        /*!< 0x00000800 */
4916 #define TIM_BDTR_OSSR                       TIM_BDTR_OSSR_Msk                  /*!<Off-State Selection for Run mode */
4917 #define TIM_BDTR_BKE_Pos                    (12U)
4918 #define TIM_BDTR_BKE_Msk                    (0x1UL << TIM_BDTR_BKE_Pos)         /*!< 0x00001000 */
4919 #define TIM_BDTR_BKE                        TIM_BDTR_BKE_Msk                   /*!<Break enable */
4920 #define TIM_BDTR_BKP_Pos                    (13U)
4921 #define TIM_BDTR_BKP_Msk                    (0x1UL << TIM_BDTR_BKP_Pos)         /*!< 0x00002000 */
4922 #define TIM_BDTR_BKP                        TIM_BDTR_BKP_Msk                   /*!<Break Polarity */
4923 #define TIM_BDTR_AOE_Pos                    (14U)
4924 #define TIM_BDTR_AOE_Msk                    (0x1UL << TIM_BDTR_AOE_Pos)         /*!< 0x00004000 */
4925 #define TIM_BDTR_AOE                        TIM_BDTR_AOE_Msk                   /*!<Automatic Output enable */
4926 #define TIM_BDTR_MOE_Pos                    (15U)
4927 #define TIM_BDTR_MOE_Msk                    (0x1UL << TIM_BDTR_MOE_Pos)         /*!< 0x00008000 */
4928 #define TIM_BDTR_MOE                        TIM_BDTR_MOE_Msk                   /*!<Main Output enable */
4929 
4930 /*******************  Bit definition for TIM_DCR register  *******************/
4931 #define TIM_DCR_DBA_Pos                     (0U)
4932 #define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)         /*!< 0x0000001F */
4933 #define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                    /*!<DBA[4:0] bits (DMA Base Address) */
4934 #define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)         /*!< 0x00000001 */
4935 #define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)         /*!< 0x00000002 */
4936 #define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)         /*!< 0x00000004 */
4937 #define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)         /*!< 0x00000008 */
4938 #define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)         /*!< 0x00000010 */
4939 
4940 #define TIM_DCR_DBL_Pos                     (8U)
4941 #define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)         /*!< 0x00001F00 */
4942 #define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                    /*!<DBL[4:0] bits (DMA Burst Length) */
4943 #define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)         /*!< 0x00000100 */
4944 #define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)         /*!< 0x00000200 */
4945 #define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)         /*!< 0x00000400 */
4946 #define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)         /*!< 0x00000800 */
4947 #define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)         /*!< 0x00001000 */
4948 
4949 /*******************  Bit definition for TIM_DMAR register  ******************/
4950 #define TIM_DMAR_DMAB_Pos                   (0U)
4951 #define TIM_DMAR_DMAB_Msk                   (0xFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */
4952 #define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */
4953 
4954 /******************************************************************************/
4955 /*                                                                            */
4956 /*                             Real-Time Clock                                */
4957 /*                                                                            */
4958 /******************************************************************************/
4959 
4960 /*******************  Bit definition for RTC_CRH register  ********************/
4961 #define RTC_CRH_SECIE_Pos                   (0U)
4962 #define RTC_CRH_SECIE_Msk                   (0x1UL << RTC_CRH_SECIE_Pos)        /*!< 0x00000001 */
4963 #define RTC_CRH_SECIE                       RTC_CRH_SECIE_Msk                  /*!< Second Interrupt Enable */
4964 #define RTC_CRH_ALRIE_Pos                   (1U)
4965 #define RTC_CRH_ALRIE_Msk                   (0x1UL << RTC_CRH_ALRIE_Pos)        /*!< 0x00000002 */
4966 #define RTC_CRH_ALRIE                       RTC_CRH_ALRIE_Msk                  /*!< Alarm Interrupt Enable */
4967 #define RTC_CRH_OWIE_Pos                    (2U)
4968 #define RTC_CRH_OWIE_Msk                    (0x1UL << RTC_CRH_OWIE_Pos)         /*!< 0x00000004 */
4969 #define RTC_CRH_OWIE                        RTC_CRH_OWIE_Msk                   /*!< OverfloW Interrupt Enable */
4970 
4971 /*******************  Bit definition for RTC_CRL register  ********************/
4972 #define RTC_CRL_SECF_Pos                    (0U)
4973 #define RTC_CRL_SECF_Msk                    (0x1UL << RTC_CRL_SECF_Pos)         /*!< 0x00000001 */
4974 #define RTC_CRL_SECF                        RTC_CRL_SECF_Msk                   /*!< Second Flag */
4975 #define RTC_CRL_ALRF_Pos                    (1U)
4976 #define RTC_CRL_ALRF_Msk                    (0x1UL << RTC_CRL_ALRF_Pos)         /*!< 0x00000002 */
4977 #define RTC_CRL_ALRF                        RTC_CRL_ALRF_Msk                   /*!< Alarm Flag */
4978 #define RTC_CRL_OWF_Pos                     (2U)
4979 #define RTC_CRL_OWF_Msk                     (0x1UL << RTC_CRL_OWF_Pos)          /*!< 0x00000004 */
4980 #define RTC_CRL_OWF                         RTC_CRL_OWF_Msk                    /*!< OverfloW Flag */
4981 #define RTC_CRL_RSF_Pos                     (3U)
4982 #define RTC_CRL_RSF_Msk                     (0x1UL << RTC_CRL_RSF_Pos)          /*!< 0x00000008 */
4983 #define RTC_CRL_RSF                         RTC_CRL_RSF_Msk                    /*!< Registers Synchronized Flag */
4984 #define RTC_CRL_CNF_Pos                     (4U)
4985 #define RTC_CRL_CNF_Msk                     (0x1UL << RTC_CRL_CNF_Pos)          /*!< 0x00000010 */
4986 #define RTC_CRL_CNF                         RTC_CRL_CNF_Msk                    /*!< Configuration Flag */
4987 #define RTC_CRL_RTOFF_Pos                   (5U)
4988 #define RTC_CRL_RTOFF_Msk                   (0x1UL << RTC_CRL_RTOFF_Pos)        /*!< 0x00000020 */
4989 #define RTC_CRL_RTOFF                       RTC_CRL_RTOFF_Msk                  /*!< RTC operation OFF */
4990 
4991 /*******************  Bit definition for RTC_PRLH register  *******************/
4992 #define RTC_PRLH_PRL_Pos                    (0U)
4993 #define RTC_PRLH_PRL_Msk                    (0xFUL << RTC_PRLH_PRL_Pos)         /*!< 0x0000000F */
4994 #define RTC_PRLH_PRL                        RTC_PRLH_PRL_Msk                   /*!< RTC Prescaler Reload Value High */
4995 
4996 /*******************  Bit definition for RTC_PRLL register  *******************/
4997 #define RTC_PRLL_PRL_Pos                    (0U)
4998 #define RTC_PRLL_PRL_Msk                    (0xFFFFUL << RTC_PRLL_PRL_Pos)      /*!< 0x0000FFFF */
4999 #define RTC_PRLL_PRL                        RTC_PRLL_PRL_Msk                   /*!< RTC Prescaler Reload Value Low */
5000 
5001 /*******************  Bit definition for RTC_DIVH register  *******************/
5002 #define RTC_DIVH_RTC_DIV_Pos                (0U)
5003 #define RTC_DIVH_RTC_DIV_Msk                (0xFUL << RTC_DIVH_RTC_DIV_Pos)     /*!< 0x0000000F */
5004 #define RTC_DIVH_RTC_DIV                    RTC_DIVH_RTC_DIV_Msk               /*!< RTC Clock Divider High */
5005 
5006 /*******************  Bit definition for RTC_DIVL register  *******************/
5007 #define RTC_DIVL_RTC_DIV_Pos                (0U)
5008 #define RTC_DIVL_RTC_DIV_Msk                (0xFFFFUL << RTC_DIVL_RTC_DIV_Pos)  /*!< 0x0000FFFF */
5009 #define RTC_DIVL_RTC_DIV                    RTC_DIVL_RTC_DIV_Msk               /*!< RTC Clock Divider Low */
5010 
5011 /*******************  Bit definition for RTC_CNTH register  *******************/
5012 #define RTC_CNTH_RTC_CNT_Pos                (0U)
5013 #define RTC_CNTH_RTC_CNT_Msk                (0xFFFFUL << RTC_CNTH_RTC_CNT_Pos)  /*!< 0x0000FFFF */
5014 #define RTC_CNTH_RTC_CNT                    RTC_CNTH_RTC_CNT_Msk               /*!< RTC Counter High */
5015 
5016 /*******************  Bit definition for RTC_CNTL register  *******************/
5017 #define RTC_CNTL_RTC_CNT_Pos                (0U)
5018 #define RTC_CNTL_RTC_CNT_Msk                (0xFFFFUL << RTC_CNTL_RTC_CNT_Pos)  /*!< 0x0000FFFF */
5019 #define RTC_CNTL_RTC_CNT                    RTC_CNTL_RTC_CNT_Msk               /*!< RTC Counter Low */
5020 
5021 /*******************  Bit definition for RTC_ALRH register  *******************/
5022 #define RTC_ALRH_RTC_ALR_Pos                (0U)
5023 #define RTC_ALRH_RTC_ALR_Msk                (0xFFFFUL << RTC_ALRH_RTC_ALR_Pos)  /*!< 0x0000FFFF */
5024 #define RTC_ALRH_RTC_ALR                    RTC_ALRH_RTC_ALR_Msk               /*!< RTC Alarm High */
5025 
5026 /*******************  Bit definition for RTC_ALRL register  *******************/
5027 #define RTC_ALRL_RTC_ALR_Pos                (0U)
5028 #define RTC_ALRL_RTC_ALR_Msk                (0xFFFFUL << RTC_ALRL_RTC_ALR_Pos)  /*!< 0x0000FFFF */
5029 #define RTC_ALRL_RTC_ALR                    RTC_ALRL_RTC_ALR_Msk               /*!< RTC Alarm Low */
5030 
5031 /******************************************************************************/
5032 /*                                                                            */
5033 /*                        Independent WATCHDOG (IWDG)                         */
5034 /*                                                                            */
5035 /******************************************************************************/
5036 
5037 /*******************  Bit definition for IWDG_KR register  ********************/
5038 #define IWDG_KR_KEY_Pos                     (0U)
5039 #define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)       /*!< 0x0000FFFF */
5040 #define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                    /*!< Key value (write only, read 0000h) */
5041 
5042 /*******************  Bit definition for IWDG_PR register  ********************/
5043 #define IWDG_PR_PR_Pos                      (0U)
5044 #define IWDG_PR_PR_Msk                      (0x7UL << IWDG_PR_PR_Pos)           /*!< 0x00000007 */
5045 #define IWDG_PR_PR                          IWDG_PR_PR_Msk                     /*!< PR[2:0] (Prescaler divider) */
5046 #define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)           /*!< 0x00000001 */
5047 #define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)           /*!< 0x00000002 */
5048 #define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)           /*!< 0x00000004 */
5049 
5050 /*******************  Bit definition for IWDG_RLR register  *******************/
5051 #define IWDG_RLR_RL_Pos                     (0U)
5052 #define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)        /*!< 0x00000FFF */
5053 #define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                    /*!< Watchdog counter reload value */
5054 
5055 /*******************  Bit definition for IWDG_SR register  ********************/
5056 #define IWDG_SR_PVU_Pos                     (0U)
5057 #define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)          /*!< 0x00000001 */
5058 #define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                    /*!< Watchdog prescaler value update */
5059 #define IWDG_SR_RVU_Pos                     (1U)
5060 #define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)          /*!< 0x00000002 */
5061 #define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                    /*!< Watchdog counter reload value update */
5062 
5063 /******************************************************************************/
5064 /*                                                                            */
5065 /*                         Window WATCHDOG (WWDG)                             */
5066 /*                                                                            */
5067 /******************************************************************************/
5068 
5069 /*******************  Bit definition for WWDG_CR register  ********************/
5070 #define WWDG_CR_T_Pos                       (0U)
5071 #define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)           /*!< 0x0000007F */
5072 #define WWDG_CR_T                           WWDG_CR_T_Msk                      /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
5073 #define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)           /*!< 0x00000001 */
5074 #define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)           /*!< 0x00000002 */
5075 #define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)           /*!< 0x00000004 */
5076 #define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)           /*!< 0x00000008 */
5077 #define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)           /*!< 0x00000010 */
5078 #define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)           /*!< 0x00000020 */
5079 #define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)           /*!< 0x00000040 */
5080 
5081 /* Legacy defines */
5082 #define  WWDG_CR_T0 WWDG_CR_T_0
5083 #define  WWDG_CR_T1 WWDG_CR_T_1
5084 #define  WWDG_CR_T2 WWDG_CR_T_2
5085 #define  WWDG_CR_T3 WWDG_CR_T_3
5086 #define  WWDG_CR_T4 WWDG_CR_T_4
5087 #define  WWDG_CR_T5 WWDG_CR_T_5
5088 #define  WWDG_CR_T6 WWDG_CR_T_6
5089 
5090 #define WWDG_CR_WDGA_Pos                    (7U)
5091 #define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)         /*!< 0x00000080 */
5092 #define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                   /*!< Activation bit */
5093 
5094 /*******************  Bit definition for WWDG_CFR register  *******************/
5095 #define WWDG_CFR_W_Pos                      (0U)
5096 #define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)          /*!< 0x0000007F */
5097 #define WWDG_CFR_W                          WWDG_CFR_W_Msk                     /*!< W[6:0] bits (7-bit window value) */
5098 #define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)          /*!< 0x00000001 */
5099 #define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)          /*!< 0x00000002 */
5100 #define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)          /*!< 0x00000004 */
5101 #define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)          /*!< 0x00000008 */
5102 #define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)          /*!< 0x00000010 */
5103 #define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)          /*!< 0x00000020 */
5104 #define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)          /*!< 0x00000040 */
5105 
5106 /* Legacy defines */
5107 #define  WWDG_CFR_W0 WWDG_CFR_W_0
5108 #define  WWDG_CFR_W1 WWDG_CFR_W_1
5109 #define  WWDG_CFR_W2 WWDG_CFR_W_2
5110 #define  WWDG_CFR_W3 WWDG_CFR_W_3
5111 #define  WWDG_CFR_W4 WWDG_CFR_W_4
5112 #define  WWDG_CFR_W5 WWDG_CFR_W_5
5113 #define  WWDG_CFR_W6 WWDG_CFR_W_6
5114 
5115 #define WWDG_CFR_WDGTB_Pos                  (7U)
5116 #define WWDG_CFR_WDGTB_Msk                  (0x3UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000180 */
5117 #define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                 /*!< WDGTB[1:0] bits (Timer Base) */
5118 #define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000080 */
5119 #define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000100 */
5120 
5121 /* Legacy defines */
5122 #define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
5123 #define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
5124 
5125 #define WWDG_CFR_EWI_Pos                    (9U)
5126 #define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)         /*!< 0x00000200 */
5127 #define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                   /*!< Early Wakeup Interrupt */
5128 
5129 /*******************  Bit definition for WWDG_SR register  ********************/
5130 #define WWDG_SR_EWIF_Pos                    (0U)
5131 #define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)         /*!< 0x00000001 */
5132 #define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                   /*!< Early Wakeup Interrupt Flag */
5133 
5134 /******************************************************************************/
5135 /*                                                                            */
5136 /*                       Flexible Static Memory Controller                    */
5137 /*                                                                            */
5138 /******************************************************************************/
5139 
5140 /******************  Bit definition for FSMC_BCRx (x=1..4) register  **********/
5141 #define FSMC_BCRx_MBKEN_Pos                 (0U)
5142 #define FSMC_BCRx_MBKEN_Msk                 (0x1UL << FSMC_BCRx_MBKEN_Pos)      /*!< 0x00000001 */
5143 #define FSMC_BCRx_MBKEN                     FSMC_BCRx_MBKEN_Msk                /*!< Memory bank enable bit */
5144 #define FSMC_BCRx_MUXEN_Pos                 (1U)
5145 #define FSMC_BCRx_MUXEN_Msk                 (0x1UL << FSMC_BCRx_MUXEN_Pos)      /*!< 0x00000002 */
5146 #define FSMC_BCRx_MUXEN                     FSMC_BCRx_MUXEN_Msk                /*!< Address/data multiplexing enable bit */
5147 
5148 #define FSMC_BCRx_MTYP_Pos                  (2U)
5149 #define FSMC_BCRx_MTYP_Msk                  (0x3UL << FSMC_BCRx_MTYP_Pos)       /*!< 0x0000000C */
5150 #define FSMC_BCRx_MTYP                      FSMC_BCRx_MTYP_Msk                 /*!< MTYP[1:0] bits (Memory type) */
5151 #define FSMC_BCRx_MTYP_0                    (0x1UL << FSMC_BCRx_MTYP_Pos)       /*!< 0x00000004 */
5152 #define FSMC_BCRx_MTYP_1                    (0x2UL << FSMC_BCRx_MTYP_Pos)       /*!< 0x00000008 */
5153 
5154 #define FSMC_BCRx_MWID_Pos                  (4U)
5155 #define FSMC_BCRx_MWID_Msk                  (0x3UL << FSMC_BCRx_MWID_Pos)       /*!< 0x00000030 */
5156 #define FSMC_BCRx_MWID                      FSMC_BCRx_MWID_Msk                 /*!< MWID[1:0] bits (Memory data bus width) */
5157 #define FSMC_BCRx_MWID_0                    (0x1UL << FSMC_BCRx_MWID_Pos)       /*!< 0x00000010 */
5158 #define FSMC_BCRx_MWID_1                    (0x2UL << FSMC_BCRx_MWID_Pos)       /*!< 0x00000020 */
5159 
5160 #define FSMC_BCRx_FACCEN_Pos                (6U)
5161 #define FSMC_BCRx_FACCEN_Msk                (0x1UL << FSMC_BCRx_FACCEN_Pos)     /*!< 0x00000040 */
5162 #define FSMC_BCRx_FACCEN                    FSMC_BCRx_FACCEN_Msk               /*!< Flash access enable */
5163 #define FSMC_BCRx_BURSTEN_Pos               (8U)
5164 #define FSMC_BCRx_BURSTEN_Msk               (0x1UL << FSMC_BCRx_BURSTEN_Pos)    /*!< 0x00000100 */
5165 #define FSMC_BCRx_BURSTEN                   FSMC_BCRx_BURSTEN_Msk              /*!< Burst enable bit */
5166 #define FSMC_BCRx_WAITPOL_Pos               (9U)
5167 #define FSMC_BCRx_WAITPOL_Msk               (0x1UL << FSMC_BCRx_WAITPOL_Pos)    /*!< 0x00000200 */
5168 #define FSMC_BCRx_WAITPOL                   FSMC_BCRx_WAITPOL_Msk              /*!< Wait signal polarity bit */
5169 #define FSMC_BCRx_WRAPMOD_Pos               (10U)
5170 #define FSMC_BCRx_WRAPMOD_Msk               (0x1UL << FSMC_BCRx_WRAPMOD_Pos)    /*!< 0x00000400 */
5171 #define FSMC_BCRx_WRAPMOD                   FSMC_BCRx_WRAPMOD_Msk              /*!< Wrapped burst mode support */
5172 #define FSMC_BCRx_WAITCFG_Pos               (11U)
5173 #define FSMC_BCRx_WAITCFG_Msk               (0x1UL << FSMC_BCRx_WAITCFG_Pos)    /*!< 0x00000800 */
5174 #define FSMC_BCRx_WAITCFG                   FSMC_BCRx_WAITCFG_Msk              /*!< Wait timing configuration */
5175 #define FSMC_BCRx_WREN_Pos                  (12U)
5176 #define FSMC_BCRx_WREN_Msk                  (0x1UL << FSMC_BCRx_WREN_Pos)       /*!< 0x00001000 */
5177 #define FSMC_BCRx_WREN                      FSMC_BCRx_WREN_Msk                 /*!< Write enable bit */
5178 #define FSMC_BCRx_WAITEN_Pos                (13U)
5179 #define FSMC_BCRx_WAITEN_Msk                (0x1UL << FSMC_BCRx_WAITEN_Pos)     /*!< 0x00002000 */
5180 #define FSMC_BCRx_WAITEN                    FSMC_BCRx_WAITEN_Msk               /*!< Wait enable bit */
5181 #define FSMC_BCRx_EXTMOD_Pos                (14U)
5182 #define FSMC_BCRx_EXTMOD_Msk                (0x1UL << FSMC_BCRx_EXTMOD_Pos)     /*!< 0x00004000 */
5183 #define FSMC_BCRx_EXTMOD                    FSMC_BCRx_EXTMOD_Msk               /*!< Extended mode enable */
5184 #define FSMC_BCRx_ASYNCWAIT_Pos             (15U)
5185 #define FSMC_BCRx_ASYNCWAIT_Msk             (0x1UL << FSMC_BCRx_ASYNCWAIT_Pos)  /*!< 0x00008000 */
5186 #define FSMC_BCRx_ASYNCWAIT                 FSMC_BCRx_ASYNCWAIT_Msk            /*!< Asynchronous wait */
5187 #define FSMC_BCRx_CBURSTRW_Pos              (19U)
5188 #define FSMC_BCRx_CBURSTRW_Msk              (0x1UL << FSMC_BCRx_CBURSTRW_Pos)   /*!< 0x00080000 */
5189 #define FSMC_BCRx_CBURSTRW                  FSMC_BCRx_CBURSTRW_Msk             /*!< Write burst enable */
5190 
5191 /******************  Bit definition for FSMC_BTRx (x=1..4) register  ******/
5192 #define FSMC_BTRx_ADDSET_Pos                (0U)
5193 #define FSMC_BTRx_ADDSET_Msk                (0xFUL << FSMC_BTRx_ADDSET_Pos)     /*!< 0x0000000F */
5194 #define FSMC_BTRx_ADDSET                    FSMC_BTRx_ADDSET_Msk               /*!< ADDSET[3:0] bits (Address setup phase duration) */
5195 #define FSMC_BTRx_ADDSET_0                  (0x1UL << FSMC_BTRx_ADDSET_Pos)     /*!< 0x00000001 */
5196 #define FSMC_BTRx_ADDSET_1                  (0x2UL << FSMC_BTRx_ADDSET_Pos)     /*!< 0x00000002 */
5197 #define FSMC_BTRx_ADDSET_2                  (0x4UL << FSMC_BTRx_ADDSET_Pos)     /*!< 0x00000004 */
5198 #define FSMC_BTRx_ADDSET_3                  (0x8UL << FSMC_BTRx_ADDSET_Pos)     /*!< 0x00000008 */
5199 
5200 #define FSMC_BTRx_ADDHLD_Pos                (4U)
5201 #define FSMC_BTRx_ADDHLD_Msk                (0xFUL << FSMC_BTRx_ADDHLD_Pos)     /*!< 0x000000F0 */
5202 #define FSMC_BTRx_ADDHLD                    FSMC_BTRx_ADDHLD_Msk               /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
5203 #define FSMC_BTRx_ADDHLD_0                  (0x1UL << FSMC_BTRx_ADDHLD_Pos)     /*!< 0x00000010 */
5204 #define FSMC_BTRx_ADDHLD_1                  (0x2UL << FSMC_BTRx_ADDHLD_Pos)     /*!< 0x00000020 */
5205 #define FSMC_BTRx_ADDHLD_2                  (0x4UL << FSMC_BTRx_ADDHLD_Pos)     /*!< 0x00000040 */
5206 #define FSMC_BTRx_ADDHLD_3                  (0x8UL << FSMC_BTRx_ADDHLD_Pos)     /*!< 0x00000080 */
5207 
5208 #define FSMC_BTRx_DATAST_Pos                (8U)
5209 #define FSMC_BTRx_DATAST_Msk                (0xFFUL << FSMC_BTRx_DATAST_Pos)    /*!< 0x0000FF00 */
5210 #define FSMC_BTRx_DATAST                    FSMC_BTRx_DATAST_Msk               /*!< DATAST [3:0] bits (Data-phase duration) */
5211 #define FSMC_BTRx_DATAST_0                  (0x01UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00000100 */
5212 #define FSMC_BTRx_DATAST_1                  (0x02UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00000200 */
5213 #define FSMC_BTRx_DATAST_2                  (0x04UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00000400 */
5214 #define FSMC_BTRx_DATAST_3                  (0x08UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00000800 */
5215 #define FSMC_BTRx_DATAST_4                  (0x10UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00001000 */
5216 #define FSMC_BTRx_DATAST_5                  (0x20UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00002000 */
5217 #define FSMC_BTRx_DATAST_6                  (0x40UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00004000 */
5218 #define FSMC_BTRx_DATAST_7                  (0x80UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00008000 */
5219 
5220 #define FSMC_BTRx_BUSTURN_Pos               (16U)
5221 #define FSMC_BTRx_BUSTURN_Msk               (0xFUL << FSMC_BTRx_BUSTURN_Pos)    /*!< 0x000F0000 */
5222 #define FSMC_BTRx_BUSTURN                   FSMC_BTRx_BUSTURN_Msk              /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
5223 #define FSMC_BTRx_BUSTURN_0                 (0x1UL << FSMC_BTRx_BUSTURN_Pos)    /*!< 0x00010000 */
5224 #define FSMC_BTRx_BUSTURN_1                 (0x2UL << FSMC_BTRx_BUSTURN_Pos)    /*!< 0x00020000 */
5225 #define FSMC_BTRx_BUSTURN_2                 (0x4UL << FSMC_BTRx_BUSTURN_Pos)    /*!< 0x00040000 */
5226 #define FSMC_BTRx_BUSTURN_3                 (0x8UL << FSMC_BTRx_BUSTURN_Pos)    /*!< 0x00080000 */
5227 
5228 #define FSMC_BTRx_CLKDIV_Pos                (20U)
5229 #define FSMC_BTRx_CLKDIV_Msk                (0xFUL << FSMC_BTRx_CLKDIV_Pos)     /*!< 0x00F00000 */
5230 #define FSMC_BTRx_CLKDIV                    FSMC_BTRx_CLKDIV_Msk               /*!< CLKDIV[3:0] bits (Clock divide ratio) */
5231 #define FSMC_BTRx_CLKDIV_0                  (0x1UL << FSMC_BTRx_CLKDIV_Pos)     /*!< 0x00100000 */
5232 #define FSMC_BTRx_CLKDIV_1                  (0x2UL << FSMC_BTRx_CLKDIV_Pos)     /*!< 0x00200000 */
5233 #define FSMC_BTRx_CLKDIV_2                  (0x4UL << FSMC_BTRx_CLKDIV_Pos)     /*!< 0x00400000 */
5234 #define FSMC_BTRx_CLKDIV_3                  (0x8UL << FSMC_BTRx_CLKDIV_Pos)     /*!< 0x00800000 */
5235 
5236 #define FSMC_BTRx_DATLAT_Pos                (24U)
5237 #define FSMC_BTRx_DATLAT_Msk                (0xFUL << FSMC_BTRx_DATLAT_Pos)     /*!< 0x0F000000 */
5238 #define FSMC_BTRx_DATLAT                    FSMC_BTRx_DATLAT_Msk               /*!< DATLA[3:0] bits (Data latency) */
5239 #define FSMC_BTRx_DATLAT_0                  (0x1UL << FSMC_BTRx_DATLAT_Pos)     /*!< 0x01000000 */
5240 #define FSMC_BTRx_DATLAT_1                  (0x2UL << FSMC_BTRx_DATLAT_Pos)     /*!< 0x02000000 */
5241 #define FSMC_BTRx_DATLAT_2                  (0x4UL << FSMC_BTRx_DATLAT_Pos)     /*!< 0x04000000 */
5242 #define FSMC_BTRx_DATLAT_3                  (0x8UL << FSMC_BTRx_DATLAT_Pos)     /*!< 0x08000000 */
5243 
5244 #define FSMC_BTRx_ACCMOD_Pos                (28U)
5245 #define FSMC_BTRx_ACCMOD_Msk                (0x3UL << FSMC_BTRx_ACCMOD_Pos)     /*!< 0x30000000 */
5246 #define FSMC_BTRx_ACCMOD                    FSMC_BTRx_ACCMOD_Msk               /*!< ACCMOD[1:0] bits (Access mode) */
5247 #define FSMC_BTRx_ACCMOD_0                  (0x1UL << FSMC_BTRx_ACCMOD_Pos)     /*!< 0x10000000 */
5248 #define FSMC_BTRx_ACCMOD_1                  (0x2UL << FSMC_BTRx_ACCMOD_Pos)     /*!< 0x20000000 */
5249 
5250 /******************  Bit definition for FSMC_BWTRx (x=1..4) register  ******/
5251 #define FSMC_BWTRx_ADDSET_Pos               (0U)
5252 #define FSMC_BWTRx_ADDSET_Msk               (0xFUL << FSMC_BWTRx_ADDSET_Pos)    /*!< 0x0000000F */
5253 #define FSMC_BWTRx_ADDSET                   FSMC_BWTRx_ADDSET_Msk              /*!< ADDSET[3:0] bits (Address setup phase duration) */
5254 #define FSMC_BWTRx_ADDSET_0                 (0x1UL << FSMC_BWTRx_ADDSET_Pos)    /*!< 0x00000001 */
5255 #define FSMC_BWTRx_ADDSET_1                 (0x2UL << FSMC_BWTRx_ADDSET_Pos)    /*!< 0x00000002 */
5256 #define FSMC_BWTRx_ADDSET_2                 (0x4UL << FSMC_BWTRx_ADDSET_Pos)    /*!< 0x00000004 */
5257 #define FSMC_BWTRx_ADDSET_3                 (0x8UL << FSMC_BWTRx_ADDSET_Pos)    /*!< 0x00000008 */
5258 
5259 #define FSMC_BWTRx_ADDHLD_Pos               (4U)
5260 #define FSMC_BWTRx_ADDHLD_Msk               (0xFUL << FSMC_BWTRx_ADDHLD_Pos)    /*!< 0x000000F0 */
5261 #define FSMC_BWTRx_ADDHLD                   FSMC_BWTRx_ADDHLD_Msk              /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
5262 #define FSMC_BWTRx_ADDHLD_0                 (0x1UL << FSMC_BWTRx_ADDHLD_Pos)    /*!< 0x00000010 */
5263 #define FSMC_BWTRx_ADDHLD_1                 (0x2UL << FSMC_BWTRx_ADDHLD_Pos)    /*!< 0x00000020 */
5264 #define FSMC_BWTRx_ADDHLD_2                 (0x4UL << FSMC_BWTRx_ADDHLD_Pos)    /*!< 0x00000040 */
5265 #define FSMC_BWTRx_ADDHLD_3                 (0x8UL << FSMC_BWTRx_ADDHLD_Pos)    /*!< 0x00000080 */
5266 
5267 #define FSMC_BWTRx_DATAST_Pos               (8U)
5268 #define FSMC_BWTRx_DATAST_Msk               (0xFFUL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x0000FF00 */
5269 #define FSMC_BWTRx_DATAST                   FSMC_BWTRx_DATAST_Msk              /*!< DATAST [3:0] bits (Data-phase duration) */
5270 #define FSMC_BWTRx_DATAST_0                 (0x01UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00000100 */
5271 #define FSMC_BWTRx_DATAST_1                 (0x02UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00000200 */
5272 #define FSMC_BWTRx_DATAST_2                 (0x04UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00000400 */
5273 #define FSMC_BWTRx_DATAST_3                 (0x08UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00000800 */
5274 #define FSMC_BWTRx_DATAST_4                 (0x10UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00001000 */
5275 #define FSMC_BWTRx_DATAST_5                 (0x20UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00002000 */
5276 #define FSMC_BWTRx_DATAST_6                 (0x40UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00004000 */
5277 #define FSMC_BWTRx_DATAST_7                 (0x80UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00008000 */
5278 
5279 #define FSMC_BWTRx_BUSTURN_Pos              (16U)
5280 #define FSMC_BWTRx_BUSTURN_Msk              (0xFUL << FSMC_BWTRx_BUSTURN_Pos)   /*!< 0x000F0000 */
5281 #define FSMC_BWTRx_BUSTURN                  FSMC_BWTRx_BUSTURN_Msk             /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
5282 #define FSMC_BWTRx_BUSTURN_0                (0x1UL << FSMC_BWTRx_BUSTURN_Pos)   /*!< 0x00010000 */
5283 #define FSMC_BWTRx_BUSTURN_1                (0x2UL << FSMC_BWTRx_BUSTURN_Pos)   /*!< 0x00020000 */
5284 #define FSMC_BWTRx_BUSTURN_2                (0x4UL << FSMC_BWTRx_BUSTURN_Pos)   /*!< 0x00040000 */
5285 #define FSMC_BWTRx_BUSTURN_3                (0x8UL << FSMC_BWTRx_BUSTURN_Pos)   /*!< 0x00080000 */
5286 
5287 #define FSMC_BWTRx_ACCMOD_Pos               (28U)
5288 #define FSMC_BWTRx_ACCMOD_Msk               (0x3UL << FSMC_BWTRx_ACCMOD_Pos)    /*!< 0x30000000 */
5289 #define FSMC_BWTRx_ACCMOD                   FSMC_BWTRx_ACCMOD_Msk              /*!< ACCMOD[1:0] bits (Access mode) */
5290 #define FSMC_BWTRx_ACCMOD_0                 (0x1UL << FSMC_BWTRx_ACCMOD_Pos)    /*!< 0x10000000 */
5291 #define FSMC_BWTRx_ACCMOD_1                 (0x2UL << FSMC_BWTRx_ACCMOD_Pos)    /*!< 0x20000000 */
5292 
5293 /******************  Bit definition for FSMC_PCRx (x = 2 to 4) register  *******************/
5294 #define FSMC_PCRx_PWAITEN_Pos               (1U)
5295 #define FSMC_PCRx_PWAITEN_Msk               (0x1UL << FSMC_PCRx_PWAITEN_Pos)    /*!< 0x00000002 */
5296 #define FSMC_PCRx_PWAITEN                   FSMC_PCRx_PWAITEN_Msk              /*!< Wait feature enable bit */
5297 #define FSMC_PCRx_PBKEN_Pos                 (2U)
5298 #define FSMC_PCRx_PBKEN_Msk                 (0x1UL << FSMC_PCRx_PBKEN_Pos)      /*!< 0x00000004 */
5299 #define FSMC_PCRx_PBKEN                     FSMC_PCRx_PBKEN_Msk                /*!< PC Card/NAND Flash memory bank enable bit */
5300 #define FSMC_PCRx_PTYP_Pos                  (3U)
5301 #define FSMC_PCRx_PTYP_Msk                  (0x1UL << FSMC_PCRx_PTYP_Pos)       /*!< 0x00000008 */
5302 #define FSMC_PCRx_PTYP                      FSMC_PCRx_PTYP_Msk                 /*!< Memory type */
5303 
5304 #define FSMC_PCRx_PWID_Pos                  (4U)
5305 #define FSMC_PCRx_PWID_Msk                  (0x3UL << FSMC_PCRx_PWID_Pos)       /*!< 0x00000030 */
5306 #define FSMC_PCRx_PWID                      FSMC_PCRx_PWID_Msk                 /*!< PWID[1:0] bits (NAND Flash databus width) */
5307 #define FSMC_PCRx_PWID_0                    (0x1UL << FSMC_PCRx_PWID_Pos)       /*!< 0x00000010 */
5308 #define FSMC_PCRx_PWID_1                    (0x2UL << FSMC_PCRx_PWID_Pos)       /*!< 0x00000020 */
5309 
5310 #define FSMC_PCRx_ECCEN_Pos                 (6U)
5311 #define FSMC_PCRx_ECCEN_Msk                 (0x1UL << FSMC_PCRx_ECCEN_Pos)      /*!< 0x00000040 */
5312 #define FSMC_PCRx_ECCEN                     FSMC_PCRx_ECCEN_Msk                /*!< ECC computation logic enable bit */
5313 
5314 #define FSMC_PCRx_TCLR_Pos                  (9U)
5315 #define FSMC_PCRx_TCLR_Msk                  (0xFUL << FSMC_PCRx_TCLR_Pos)       /*!< 0x00001E00 */
5316 #define FSMC_PCRx_TCLR                      FSMC_PCRx_TCLR_Msk                 /*!< TCLR[3:0] bits (CLE to RE delay) */
5317 #define FSMC_PCRx_TCLR_0                    (0x1UL << FSMC_PCRx_TCLR_Pos)       /*!< 0x00000200 */
5318 #define FSMC_PCRx_TCLR_1                    (0x2UL << FSMC_PCRx_TCLR_Pos)       /*!< 0x00000400 */
5319 #define FSMC_PCRx_TCLR_2                    (0x4UL << FSMC_PCRx_TCLR_Pos)       /*!< 0x00000800 */
5320 #define FSMC_PCRx_TCLR_3                    (0x8UL << FSMC_PCRx_TCLR_Pos)       /*!< 0x00001000 */
5321 
5322 #define FSMC_PCRx_TAR_Pos                   (13U)
5323 #define FSMC_PCRx_TAR_Msk                   (0xFUL << FSMC_PCRx_TAR_Pos)        /*!< 0x0001E000 */
5324 #define FSMC_PCRx_TAR                       FSMC_PCRx_TAR_Msk                  /*!< TAR[3:0] bits (ALE to RE delay) */
5325 #define FSMC_PCRx_TAR_0                     (0x1UL << FSMC_PCRx_TAR_Pos)        /*!< 0x00002000 */
5326 #define FSMC_PCRx_TAR_1                     (0x2UL << FSMC_PCRx_TAR_Pos)        /*!< 0x00004000 */
5327 #define FSMC_PCRx_TAR_2                     (0x4UL << FSMC_PCRx_TAR_Pos)        /*!< 0x00008000 */
5328 #define FSMC_PCRx_TAR_3                     (0x8UL << FSMC_PCRx_TAR_Pos)        /*!< 0x00010000 */
5329 
5330 #define FSMC_PCRx_ECCPS_Pos                 (17U)
5331 #define FSMC_PCRx_ECCPS_Msk                 (0x7UL << FSMC_PCRx_ECCPS_Pos)      /*!< 0x000E0000 */
5332 #define FSMC_PCRx_ECCPS                     FSMC_PCRx_ECCPS_Msk                /*!< ECCPS[1:0] bits (ECC page size) */
5333 #define FSMC_PCRx_ECCPS_0                   (0x1UL << FSMC_PCRx_ECCPS_Pos)      /*!< 0x00020000 */
5334 #define FSMC_PCRx_ECCPS_1                   (0x2UL << FSMC_PCRx_ECCPS_Pos)      /*!< 0x00040000 */
5335 #define FSMC_PCRx_ECCPS_2                   (0x4UL << FSMC_PCRx_ECCPS_Pos)      /*!< 0x00080000 */
5336 
5337 /*******************  Bit definition for FSMC_SRx (x = 2 to 4) register  *******************/
5338 #define FSMC_SRx_IRS_Pos                    (0U)
5339 #define FSMC_SRx_IRS_Msk                    (0x1UL << FSMC_SRx_IRS_Pos)         /*!< 0x00000001 */
5340 #define FSMC_SRx_IRS                        FSMC_SRx_IRS_Msk                   /*!< Interrupt Rising Edge status */
5341 #define FSMC_SRx_ILS_Pos                    (1U)
5342 #define FSMC_SRx_ILS_Msk                    (0x1UL << FSMC_SRx_ILS_Pos)         /*!< 0x00000002 */
5343 #define FSMC_SRx_ILS                        FSMC_SRx_ILS_Msk                   /*!< Interrupt Level status */
5344 #define FSMC_SRx_IFS_Pos                    (2U)
5345 #define FSMC_SRx_IFS_Msk                    (0x1UL << FSMC_SRx_IFS_Pos)         /*!< 0x00000004 */
5346 #define FSMC_SRx_IFS                        FSMC_SRx_IFS_Msk                   /*!< Interrupt Falling Edge status */
5347 #define FSMC_SRx_IREN_Pos                   (3U)
5348 #define FSMC_SRx_IREN_Msk                   (0x1UL << FSMC_SRx_IREN_Pos)        /*!< 0x00000008 */
5349 #define FSMC_SRx_IREN                       FSMC_SRx_IREN_Msk                  /*!< Interrupt Rising Edge detection Enable bit */
5350 #define FSMC_SRx_ILEN_Pos                   (4U)
5351 #define FSMC_SRx_ILEN_Msk                   (0x1UL << FSMC_SRx_ILEN_Pos)        /*!< 0x00000010 */
5352 #define FSMC_SRx_ILEN                       FSMC_SRx_ILEN_Msk                  /*!< Interrupt Level detection Enable bit */
5353 #define FSMC_SRx_IFEN_Pos                   (5U)
5354 #define FSMC_SRx_IFEN_Msk                   (0x1UL << FSMC_SRx_IFEN_Pos)        /*!< 0x00000020 */
5355 #define FSMC_SRx_IFEN                       FSMC_SRx_IFEN_Msk                  /*!< Interrupt Falling Edge detection Enable bit */
5356 #define FSMC_SRx_FEMPT_Pos                  (6U)
5357 #define FSMC_SRx_FEMPT_Msk                  (0x1UL << FSMC_SRx_FEMPT_Pos)       /*!< 0x00000040 */
5358 #define FSMC_SRx_FEMPT                      FSMC_SRx_FEMPT_Msk                 /*!< FIFO empty */
5359 
5360 /******************  Bit definition for FSMC_PMEMx (x = 2 to 4) register  ******************/
5361 #define FSMC_PMEMx_MEMSETx_Pos              (0U)
5362 #define FSMC_PMEMx_MEMSETx_Msk              (0xFFUL << FSMC_PMEMx_MEMSETx_Pos)  /*!< 0x000000FF */
5363 #define FSMC_PMEMx_MEMSETx                  FSMC_PMEMx_MEMSETx_Msk             /*!< MEMSETx[7:0] bits (Common memory x setup time) */
5364 #define FSMC_PMEMx_MEMSETx_0                (0x01UL << FSMC_PMEMx_MEMSETx_Pos)  /*!< 0x00000001 */
5365 #define FSMC_PMEMx_MEMSETx_1                (0x02UL << FSMC_PMEMx_MEMSETx_Pos)  /*!< 0x00000002 */
5366 #define FSMC_PMEMx_MEMSETx_2                (0x04UL << FSMC_PMEMx_MEMSETx_Pos)  /*!< 0x00000004 */
5367 #define FSMC_PMEMx_MEMSETx_3                (0x08UL << FSMC_PMEMx_MEMSETx_Pos)  /*!< 0x00000008 */
5368 #define FSMC_PMEMx_MEMSETx_4                (0x10UL << FSMC_PMEMx_MEMSETx_Pos)  /*!< 0x00000010 */
5369 #define FSMC_PMEMx_MEMSETx_5                (0x20UL << FSMC_PMEMx_MEMSETx_Pos)  /*!< 0x00000020 */
5370 #define FSMC_PMEMx_MEMSETx_6                (0x40UL << FSMC_PMEMx_MEMSETx_Pos)  /*!< 0x00000040 */
5371 #define FSMC_PMEMx_MEMSETx_7                (0x80UL << FSMC_PMEMx_MEMSETx_Pos)  /*!< 0x00000080 */
5372 
5373 #define FSMC_PMEMx_MEMWAITx_Pos             (8U)
5374 #define FSMC_PMEMx_MEMWAITx_Msk             (0xFFUL << FSMC_PMEMx_MEMWAITx_Pos) /*!< 0x0000FF00 */
5375 #define FSMC_PMEMx_MEMWAITx                 FSMC_PMEMx_MEMWAITx_Msk            /*!< MEMWAITx[7:0] bits (Common memory x wait time) */
5376 #define FSMC_PMEMx_MEMWAIT2_0               0x00000100U                        /*!< Bit 0 */
5377 #define FSMC_PMEMx_MEMWAITx_1               0x00000200U                        /*!< Bit 1 */
5378 #define FSMC_PMEMx_MEMWAITx_2               0x00000400U                        /*!< Bit 2 */
5379 #define FSMC_PMEMx_MEMWAITx_3               0x00000800U                        /*!< Bit 3 */
5380 #define FSMC_PMEMx_MEMWAITx_4               0x00001000U                        /*!< Bit 4 */
5381 #define FSMC_PMEMx_MEMWAITx_5               0x00002000U                        /*!< Bit 5 */
5382 #define FSMC_PMEMx_MEMWAITx_6               0x00004000U                        /*!< Bit 6 */
5383 #define FSMC_PMEMx_MEMWAITx_7               0x00008000U                        /*!< Bit 7 */
5384 
5385 #define FSMC_PMEMx_MEMHOLDx_Pos             (16U)
5386 #define FSMC_PMEMx_MEMHOLDx_Msk             (0xFFUL << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00FF0000 */
5387 #define FSMC_PMEMx_MEMHOLDx                 FSMC_PMEMx_MEMHOLDx_Msk            /*!< MEMHOLDx[7:0] bits (Common memory x hold time) */
5388 #define FSMC_PMEMx_MEMHOLDx_0               (0x01UL << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00010000 */
5389 #define FSMC_PMEMx_MEMHOLDx_1               (0x02UL << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00020000 */
5390 #define FSMC_PMEMx_MEMHOLDx_2               (0x04UL << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00040000 */
5391 #define FSMC_PMEMx_MEMHOLDx_3               (0x08UL << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00080000 */
5392 #define FSMC_PMEMx_MEMHOLDx_4               (0x10UL << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00100000 */
5393 #define FSMC_PMEMx_MEMHOLDx_5               (0x20UL << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00200000 */
5394 #define FSMC_PMEMx_MEMHOLDx_6               (0x40UL << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00400000 */
5395 #define FSMC_PMEMx_MEMHOLDx_7               (0x80UL << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00800000 */
5396 
5397 #define FSMC_PMEMx_MEMHIZx_Pos              (24U)
5398 #define FSMC_PMEMx_MEMHIZx_Msk              (0xFFUL << FSMC_PMEMx_MEMHIZx_Pos)  /*!< 0xFF000000 */
5399 #define FSMC_PMEMx_MEMHIZx                  FSMC_PMEMx_MEMHIZx_Msk             /*!< MEMHIZx[7:0] bits (Common memory x databus HiZ time) */
5400 #define FSMC_PMEMx_MEMHIZx_0                (0x01UL << FSMC_PMEMx_MEMHIZx_Pos)  /*!< 0x01000000 */
5401 #define FSMC_PMEMx_MEMHIZx_1                (0x02UL << FSMC_PMEMx_MEMHIZx_Pos)  /*!< 0x02000000 */
5402 #define FSMC_PMEMx_MEMHIZx_2                (0x04UL << FSMC_PMEMx_MEMHIZx_Pos)  /*!< 0x04000000 */
5403 #define FSMC_PMEMx_MEMHIZx_3                (0x08UL << FSMC_PMEMx_MEMHIZx_Pos)  /*!< 0x08000000 */
5404 #define FSMC_PMEMx_MEMHIZx_4                (0x10UL << FSMC_PMEMx_MEMHIZx_Pos)  /*!< 0x10000000 */
5405 #define FSMC_PMEMx_MEMHIZx_5                (0x20UL << FSMC_PMEMx_MEMHIZx_Pos)  /*!< 0x20000000 */
5406 #define FSMC_PMEMx_MEMHIZx_6                (0x40UL << FSMC_PMEMx_MEMHIZx_Pos)  /*!< 0x40000000 */
5407 #define FSMC_PMEMx_MEMHIZx_7                (0x80UL << FSMC_PMEMx_MEMHIZx_Pos)  /*!< 0x80000000 */
5408 
5409 /******************  Bit definition for FSMC_PATTx (x = 2 to 4) register  ******************/
5410 #define FSMC_PATTx_ATTSETx_Pos              (0U)
5411 #define FSMC_PATTx_ATTSETx_Msk              (0xFFUL << FSMC_PATTx_ATTSETx_Pos)  /*!< 0x000000FF */
5412 #define FSMC_PATTx_ATTSETx                  FSMC_PATTx_ATTSETx_Msk             /*!< ATTSETx[7:0] bits (Attribute memory x setup time) */
5413 #define FSMC_PATTx_ATTSETx_0                (0x01UL << FSMC_PATTx_ATTSETx_Pos)  /*!< 0x00000001 */
5414 #define FSMC_PATTx_ATTSETx_1                (0x02UL << FSMC_PATTx_ATTSETx_Pos)  /*!< 0x00000002 */
5415 #define FSMC_PATTx_ATTSETx_2                (0x04UL << FSMC_PATTx_ATTSETx_Pos)  /*!< 0x00000004 */
5416 #define FSMC_PATTx_ATTSETx_3                (0x08UL << FSMC_PATTx_ATTSETx_Pos)  /*!< 0x00000008 */
5417 #define FSMC_PATTx_ATTSETx_4                (0x10UL << FSMC_PATTx_ATTSETx_Pos)  /*!< 0x00000010 */
5418 #define FSMC_PATTx_ATTSETx_5                (0x20UL << FSMC_PATTx_ATTSETx_Pos)  /*!< 0x00000020 */
5419 #define FSMC_PATTx_ATTSETx_6                (0x40UL << FSMC_PATTx_ATTSETx_Pos)  /*!< 0x00000040 */
5420 #define FSMC_PATTx_ATTSETx_7                (0x80UL << FSMC_PATTx_ATTSETx_Pos)  /*!< 0x00000080 */
5421 
5422 #define FSMC_PATTx_ATTWAITx_Pos             (8U)
5423 #define FSMC_PATTx_ATTWAITx_Msk             (0xFFUL << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x0000FF00 */
5424 #define FSMC_PATTx_ATTWAITx                 FSMC_PATTx_ATTWAITx_Msk            /*!< ATTWAITx[7:0] bits (Attribute memory x wait time) */
5425 #define FSMC_PATTx_ATTWAITx_0               (0x01UL << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00000100 */
5426 #define FSMC_PATTx_ATTWAITx_1               (0x02UL << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00000200 */
5427 #define FSMC_PATTx_ATTWAITx_2               (0x04UL << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00000400 */
5428 #define FSMC_PATTx_ATTWAITx_3               (0x08UL << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00000800 */
5429 #define FSMC_PATTx_ATTWAITx_4               (0x10UL << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00001000 */
5430 #define FSMC_PATTx_ATTWAITx_5               (0x20UL << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00002000 */
5431 #define FSMC_PATTx_ATTWAITx_6               (0x40UL << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00004000 */
5432 #define FSMC_PATTx_ATTWAITx_7               (0x80UL << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00008000 */
5433 
5434 #define FSMC_PATTx_ATTHOLDx_Pos             (16U)
5435 #define FSMC_PATTx_ATTHOLDx_Msk             (0xFFUL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00FF0000 */
5436 #define FSMC_PATTx_ATTHOLDx                 FSMC_PATTx_ATTHOLDx_Msk            /*!< ATTHOLDx[7:0] bits (Attribute memory x hold time) */
5437 #define FSMC_PATTx_ATTHOLDx_0               (0x01UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00010000 */
5438 #define FSMC_PATTx_ATTHOLDx_1               (0x02UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00020000 */
5439 #define FSMC_PATTx_ATTHOLDx_2               (0x04UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00040000 */
5440 #define FSMC_PATTx_ATTHOLDx_3               (0x08UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00080000 */
5441 #define FSMC_PATTx_ATTHOLDx_4               (0x10UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00100000 */
5442 #define FSMC_PATTx_ATTHOLDx_5               (0x20UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00200000 */
5443 #define FSMC_PATTx_ATTHOLDx_6               (0x40UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00400000 */
5444 #define FSMC_PATTx_ATTHOLDx_7               (0x80UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00800000 */
5445 
5446 #define FSMC_PATTx_ATTHIZx_Pos              (24U)
5447 #define FSMC_PATTx_ATTHIZx_Msk              (0xFFUL << FSMC_PATTx_ATTHIZx_Pos)  /*!< 0xFF000000 */
5448 #define FSMC_PATTx_ATTHIZx                  FSMC_PATTx_ATTHIZx_Msk             /*!< ATTHIZx[7:0] bits (Attribute memory x databus HiZ time) */
5449 #define FSMC_PATTx_ATTHIZx_0                (0x01UL << FSMC_PATTx_ATTHIZx_Pos)  /*!< 0x01000000 */
5450 #define FSMC_PATTx_ATTHIZx_1                (0x02UL << FSMC_PATTx_ATTHIZx_Pos)  /*!< 0x02000000 */
5451 #define FSMC_PATTx_ATTHIZx_2                (0x04UL << FSMC_PATTx_ATTHIZx_Pos)  /*!< 0x04000000 */
5452 #define FSMC_PATTx_ATTHIZx_3                (0x08UL << FSMC_PATTx_ATTHIZx_Pos)  /*!< 0x08000000 */
5453 #define FSMC_PATTx_ATTHIZx_4                (0x10UL << FSMC_PATTx_ATTHIZx_Pos)  /*!< 0x10000000 */
5454 #define FSMC_PATTx_ATTHIZx_5                (0x20UL << FSMC_PATTx_ATTHIZx_Pos)  /*!< 0x20000000 */
5455 #define FSMC_PATTx_ATTHIZx_6                (0x40UL << FSMC_PATTx_ATTHIZx_Pos)  /*!< 0x40000000 */
5456 #define FSMC_PATTx_ATTHIZx_7                (0x80UL << FSMC_PATTx_ATTHIZx_Pos)  /*!< 0x80000000 */
5457 
5458 /******************  Bit definition for FSMC_PIO4 register  *******************/
5459 #define FSMC_PIO4_IOSET4_Pos                (0U)
5460 #define FSMC_PIO4_IOSET4_Msk                (0xFFUL << FSMC_PIO4_IOSET4_Pos)    /*!< 0x000000FF */
5461 #define FSMC_PIO4_IOSET4                    FSMC_PIO4_IOSET4_Msk               /*!< IOSET4[7:0] bits (I/O 4 setup time) */
5462 #define FSMC_PIO4_IOSET4_0                  (0x01UL << FSMC_PIO4_IOSET4_Pos)    /*!< 0x00000001 */
5463 #define FSMC_PIO4_IOSET4_1                  (0x02UL << FSMC_PIO4_IOSET4_Pos)    /*!< 0x00000002 */
5464 #define FSMC_PIO4_IOSET4_2                  (0x04UL << FSMC_PIO4_IOSET4_Pos)    /*!< 0x00000004 */
5465 #define FSMC_PIO4_IOSET4_3                  (0x08UL << FSMC_PIO4_IOSET4_Pos)    /*!< 0x00000008 */
5466 #define FSMC_PIO4_IOSET4_4                  (0x10UL << FSMC_PIO4_IOSET4_Pos)    /*!< 0x00000010 */
5467 #define FSMC_PIO4_IOSET4_5                  (0x20UL << FSMC_PIO4_IOSET4_Pos)    /*!< 0x00000020 */
5468 #define FSMC_PIO4_IOSET4_6                  (0x40UL << FSMC_PIO4_IOSET4_Pos)    /*!< 0x00000040 */
5469 #define FSMC_PIO4_IOSET4_7                  (0x80UL << FSMC_PIO4_IOSET4_Pos)    /*!< 0x00000080 */
5470 
5471 #define FSMC_PIO4_IOWAIT4_Pos               (8U)
5472 #define FSMC_PIO4_IOWAIT4_Msk               (0xFFUL << FSMC_PIO4_IOWAIT4_Pos)   /*!< 0x0000FF00 */
5473 #define FSMC_PIO4_IOWAIT4                   FSMC_PIO4_IOWAIT4_Msk              /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */
5474 #define FSMC_PIO4_IOWAIT4_0                 (0x01UL << FSMC_PIO4_IOWAIT4_Pos)   /*!< 0x00000100 */
5475 #define FSMC_PIO4_IOWAIT4_1                 (0x02UL << FSMC_PIO4_IOWAIT4_Pos)   /*!< 0x00000200 */
5476 #define FSMC_PIO4_IOWAIT4_2                 (0x04UL << FSMC_PIO4_IOWAIT4_Pos)   /*!< 0x00000400 */
5477 #define FSMC_PIO4_IOWAIT4_3                 (0x08UL << FSMC_PIO4_IOWAIT4_Pos)   /*!< 0x00000800 */
5478 #define FSMC_PIO4_IOWAIT4_4                 (0x10UL << FSMC_PIO4_IOWAIT4_Pos)   /*!< 0x00001000 */
5479 #define FSMC_PIO4_IOWAIT4_5                 (0x20UL << FSMC_PIO4_IOWAIT4_Pos)   /*!< 0x00002000 */
5480 #define FSMC_PIO4_IOWAIT4_6                 (0x40UL << FSMC_PIO4_IOWAIT4_Pos)   /*!< 0x00004000 */
5481 #define FSMC_PIO4_IOWAIT4_7                 (0x80UL << FSMC_PIO4_IOWAIT4_Pos)   /*!< 0x00008000 */
5482 
5483 #define FSMC_PIO4_IOHOLD4_Pos               (16U)
5484 #define FSMC_PIO4_IOHOLD4_Msk               (0xFFUL << FSMC_PIO4_IOHOLD4_Pos)   /*!< 0x00FF0000 */
5485 #define FSMC_PIO4_IOHOLD4                   FSMC_PIO4_IOHOLD4_Msk              /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */
5486 #define FSMC_PIO4_IOHOLD4_0                 (0x01UL << FSMC_PIO4_IOHOLD4_Pos)   /*!< 0x00010000 */
5487 #define FSMC_PIO4_IOHOLD4_1                 (0x02UL << FSMC_PIO4_IOHOLD4_Pos)   /*!< 0x00020000 */
5488 #define FSMC_PIO4_IOHOLD4_2                 (0x04UL << FSMC_PIO4_IOHOLD4_Pos)   /*!< 0x00040000 */
5489 #define FSMC_PIO4_IOHOLD4_3                 (0x08UL << FSMC_PIO4_IOHOLD4_Pos)   /*!< 0x00080000 */
5490 #define FSMC_PIO4_IOHOLD4_4                 (0x10UL << FSMC_PIO4_IOHOLD4_Pos)   /*!< 0x00100000 */
5491 #define FSMC_PIO4_IOHOLD4_5                 (0x20UL << FSMC_PIO4_IOHOLD4_Pos)   /*!< 0x00200000 */
5492 #define FSMC_PIO4_IOHOLD4_6                 (0x40UL << FSMC_PIO4_IOHOLD4_Pos)   /*!< 0x00400000 */
5493 #define FSMC_PIO4_IOHOLD4_7                 (0x80UL << FSMC_PIO4_IOHOLD4_Pos)   /*!< 0x00800000 */
5494 
5495 #define FSMC_PIO4_IOHIZ4_Pos                (24U)
5496 #define FSMC_PIO4_IOHIZ4_Msk                (0xFFUL << FSMC_PIO4_IOHIZ4_Pos)    /*!< 0xFF000000 */
5497 #define FSMC_PIO4_IOHIZ4                    FSMC_PIO4_IOHIZ4_Msk               /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
5498 #define FSMC_PIO4_IOHIZ4_0                  (0x01UL << FSMC_PIO4_IOHIZ4_Pos)    /*!< 0x01000000 */
5499 #define FSMC_PIO4_IOHIZ4_1                  (0x02UL << FSMC_PIO4_IOHIZ4_Pos)    /*!< 0x02000000 */
5500 #define FSMC_PIO4_IOHIZ4_2                  (0x04UL << FSMC_PIO4_IOHIZ4_Pos)    /*!< 0x04000000 */
5501 #define FSMC_PIO4_IOHIZ4_3                  (0x08UL << FSMC_PIO4_IOHIZ4_Pos)    /*!< 0x08000000 */
5502 #define FSMC_PIO4_IOHIZ4_4                  (0x10UL << FSMC_PIO4_IOHIZ4_Pos)    /*!< 0x10000000 */
5503 #define FSMC_PIO4_IOHIZ4_5                  (0x20UL << FSMC_PIO4_IOHIZ4_Pos)    /*!< 0x20000000 */
5504 #define FSMC_PIO4_IOHIZ4_6                  (0x40UL << FSMC_PIO4_IOHIZ4_Pos)    /*!< 0x40000000 */
5505 #define FSMC_PIO4_IOHIZ4_7                  (0x80UL << FSMC_PIO4_IOHIZ4_Pos)    /*!< 0x80000000 */
5506 
5507 /******************  Bit definition for FSMC_ECCR2 register  ******************/
5508 #define FSMC_ECCR2_ECC2_Pos                 (0U)
5509 #define FSMC_ECCR2_ECC2_Msk                 (0xFFFFFFFFUL << FSMC_ECCR2_ECC2_Pos) /*!< 0xFFFFFFFF */
5510 #define FSMC_ECCR2_ECC2                     FSMC_ECCR2_ECC2_Msk                /*!< ECC result */
5511 
5512 /******************  Bit definition for FSMC_ECCR3 register  ******************/
5513 #define FSMC_ECCR3_ECC3_Pos                 (0U)
5514 #define FSMC_ECCR3_ECC3_Msk                 (0xFFFFFFFFUL << FSMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */
5515 #define FSMC_ECCR3_ECC3                     FSMC_ECCR3_ECC3_Msk                /*!< ECC result */
5516 
5517 /******************************************************************************/
5518 /*                                                                            */
5519 /*                          SD host Interface                                 */
5520 /*                                                                            */
5521 /******************************************************************************/
5522 
5523 /******************  Bit definition for SDIO_POWER register  ******************/
5524 #define SDIO_POWER_PWRCTRL_Pos              (0U)
5525 #define SDIO_POWER_PWRCTRL_Msk              (0x3UL << SDIO_POWER_PWRCTRL_Pos)   /*!< 0x00000003 */
5526 #define SDIO_POWER_PWRCTRL                  SDIO_POWER_PWRCTRL_Msk             /*!< PWRCTRL[1:0] bits (Power supply control bits) */
5527 #define SDIO_POWER_PWRCTRL_0                (0x1UL << SDIO_POWER_PWRCTRL_Pos)   /*!< 0x01 */
5528 #define SDIO_POWER_PWRCTRL_1                (0x2UL << SDIO_POWER_PWRCTRL_Pos)   /*!< 0x02 */
5529 
5530 /******************  Bit definition for SDIO_CLKCR register  ******************/
5531 #define SDIO_CLKCR_CLKDIV_Pos               (0U)
5532 #define SDIO_CLKCR_CLKDIV_Msk               (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)   /*!< 0x000000FF */
5533 #define SDIO_CLKCR_CLKDIV                   SDIO_CLKCR_CLKDIV_Msk              /*!< Clock divide factor */
5534 #define SDIO_CLKCR_CLKEN_Pos                (8U)
5535 #define SDIO_CLKCR_CLKEN_Msk                (0x1UL << SDIO_CLKCR_CLKEN_Pos)     /*!< 0x00000100 */
5536 #define SDIO_CLKCR_CLKEN                    SDIO_CLKCR_CLKEN_Msk               /*!< Clock enable bit */
5537 #define SDIO_CLKCR_PWRSAV_Pos               (9U)
5538 #define SDIO_CLKCR_PWRSAV_Msk               (0x1UL << SDIO_CLKCR_PWRSAV_Pos)    /*!< 0x00000200 */
5539 #define SDIO_CLKCR_PWRSAV                   SDIO_CLKCR_PWRSAV_Msk              /*!< Power saving configuration bit */
5540 #define SDIO_CLKCR_BYPASS_Pos               (10U)
5541 #define SDIO_CLKCR_BYPASS_Msk               (0x1UL << SDIO_CLKCR_BYPASS_Pos)    /*!< 0x00000400 */
5542 #define SDIO_CLKCR_BYPASS                   SDIO_CLKCR_BYPASS_Msk              /*!< Clock divider bypass enable bit */
5543 
5544 #define SDIO_CLKCR_WIDBUS_Pos               (11U)
5545 #define SDIO_CLKCR_WIDBUS_Msk               (0x3UL << SDIO_CLKCR_WIDBUS_Pos)    /*!< 0x00001800 */
5546 #define SDIO_CLKCR_WIDBUS                   SDIO_CLKCR_WIDBUS_Msk              /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
5547 #define SDIO_CLKCR_WIDBUS_0                 (0x1UL << SDIO_CLKCR_WIDBUS_Pos)    /*!< 0x0800 */
5548 #define SDIO_CLKCR_WIDBUS_1                 (0x2UL << SDIO_CLKCR_WIDBUS_Pos)    /*!< 0x1000 */
5549 
5550 #define SDIO_CLKCR_NEGEDGE_Pos              (13U)
5551 #define SDIO_CLKCR_NEGEDGE_Msk              (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)   /*!< 0x00002000 */
5552 #define SDIO_CLKCR_NEGEDGE                  SDIO_CLKCR_NEGEDGE_Msk             /*!< SDIO_CK dephasing selection bit */
5553 #define SDIO_CLKCR_HWFC_EN_Pos              (14U)
5554 #define SDIO_CLKCR_HWFC_EN_Msk              (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)   /*!< 0x00004000 */
5555 #define SDIO_CLKCR_HWFC_EN                  SDIO_CLKCR_HWFC_EN_Msk             /*!< HW Flow Control enable */
5556 
5557 /*******************  Bit definition for SDIO_ARG register  *******************/
5558 #define SDIO_ARG_CMDARG_Pos                 (0U)
5559 #define SDIO_ARG_CMDARG_Msk                 (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
5560 #define SDIO_ARG_CMDARG                     SDIO_ARG_CMDARG_Msk                /*!< Command argument */
5561 
5562 /*******************  Bit definition for SDIO_CMD register  *******************/
5563 #define SDIO_CMD_CMDINDEX_Pos               (0U)
5564 #define SDIO_CMD_CMDINDEX_Msk               (0x3FUL << SDIO_CMD_CMDINDEX_Pos)   /*!< 0x0000003F */
5565 #define SDIO_CMD_CMDINDEX                   SDIO_CMD_CMDINDEX_Msk              /*!< Command Index */
5566 
5567 #define SDIO_CMD_WAITRESP_Pos               (6U)
5568 #define SDIO_CMD_WAITRESP_Msk               (0x3UL << SDIO_CMD_WAITRESP_Pos)    /*!< 0x000000C0 */
5569 #define SDIO_CMD_WAITRESP                   SDIO_CMD_WAITRESP_Msk              /*!< WAITRESP[1:0] bits (Wait for response bits) */
5570 #define SDIO_CMD_WAITRESP_0                 (0x1UL << SDIO_CMD_WAITRESP_Pos)    /*!< 0x0040 */
5571 #define SDIO_CMD_WAITRESP_1                 (0x2UL << SDIO_CMD_WAITRESP_Pos)    /*!< 0x0080 */
5572 
5573 #define SDIO_CMD_WAITINT_Pos                (8U)
5574 #define SDIO_CMD_WAITINT_Msk                (0x1UL << SDIO_CMD_WAITINT_Pos)     /*!< 0x00000100 */
5575 #define SDIO_CMD_WAITINT                    SDIO_CMD_WAITINT_Msk               /*!< CPSM Waits for Interrupt Request */
5576 #define SDIO_CMD_WAITPEND_Pos               (9U)
5577 #define SDIO_CMD_WAITPEND_Msk               (0x1UL << SDIO_CMD_WAITPEND_Pos)    /*!< 0x00000200 */
5578 #define SDIO_CMD_WAITPEND                   SDIO_CMD_WAITPEND_Msk              /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
5579 #define SDIO_CMD_CPSMEN_Pos                 (10U)
5580 #define SDIO_CMD_CPSMEN_Msk                 (0x1UL << SDIO_CMD_CPSMEN_Pos)      /*!< 0x00000400 */
5581 #define SDIO_CMD_CPSMEN                     SDIO_CMD_CPSMEN_Msk                /*!< Command path state machine (CPSM) Enable bit */
5582 #define SDIO_CMD_SDIOSUSPEND_Pos            (11U)
5583 #define SDIO_CMD_SDIOSUSPEND_Msk            (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
5584 #define SDIO_CMD_SDIOSUSPEND                SDIO_CMD_SDIOSUSPEND_Msk           /*!< SD I/O suspend command */
5585 #define SDIO_CMD_ENCMDCOMPL_Pos             (12U)
5586 #define SDIO_CMD_ENCMDCOMPL_Msk             (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos)  /*!< 0x00001000 */
5587 #define SDIO_CMD_ENCMDCOMPL                 SDIO_CMD_ENCMDCOMPL_Msk            /*!< Enable CMD completion */
5588 #define SDIO_CMD_NIEN_Pos                   (13U)
5589 #define SDIO_CMD_NIEN_Msk                   (0x1UL << SDIO_CMD_NIEN_Pos)        /*!< 0x00002000 */
5590 #define SDIO_CMD_NIEN                       SDIO_CMD_NIEN_Msk                  /*!< Not Interrupt Enable */
5591 #define SDIO_CMD_CEATACMD_Pos               (14U)
5592 #define SDIO_CMD_CEATACMD_Msk               (0x1UL << SDIO_CMD_CEATACMD_Pos)    /*!< 0x00004000 */
5593 #define SDIO_CMD_CEATACMD                   SDIO_CMD_CEATACMD_Msk              /*!< CE-ATA command */
5594 
5595 /*****************  Bit definition for SDIO_RESPCMD register  *****************/
5596 #define SDIO_RESPCMD_RESPCMD_Pos            (0U)
5597 #define SDIO_RESPCMD_RESPCMD_Msk            (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
5598 #define SDIO_RESPCMD_RESPCMD                SDIO_RESPCMD_RESPCMD_Msk           /*!< Response command index */
5599 
5600 /******************  Bit definition for SDIO_RESP0 register  ******************/
5601 #define SDIO_RESP0_CARDSTATUS0_Pos          (0U)
5602 #define SDIO_RESP0_CARDSTATUS0_Msk          (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
5603 #define SDIO_RESP0_CARDSTATUS0              SDIO_RESP0_CARDSTATUS0_Msk         /*!< Card Status */
5604 
5605 /******************  Bit definition for SDIO_RESP1 register  ******************/
5606 #define SDIO_RESP1_CARDSTATUS1_Pos          (0U)
5607 #define SDIO_RESP1_CARDSTATUS1_Msk          (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
5608 #define SDIO_RESP1_CARDSTATUS1              SDIO_RESP1_CARDSTATUS1_Msk         /*!< Card Status */
5609 
5610 /******************  Bit definition for SDIO_RESP2 register  ******************/
5611 #define SDIO_RESP2_CARDSTATUS2_Pos          (0U)
5612 #define SDIO_RESP2_CARDSTATUS2_Msk          (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
5613 #define SDIO_RESP2_CARDSTATUS2              SDIO_RESP2_CARDSTATUS2_Msk         /*!< Card Status */
5614 
5615 /******************  Bit definition for SDIO_RESP3 register  ******************/
5616 #define SDIO_RESP3_CARDSTATUS3_Pos          (0U)
5617 #define SDIO_RESP3_CARDSTATUS3_Msk          (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
5618 #define SDIO_RESP3_CARDSTATUS3              SDIO_RESP3_CARDSTATUS3_Msk         /*!< Card Status */
5619 
5620 /******************  Bit definition for SDIO_RESP4 register  ******************/
5621 #define SDIO_RESP4_CARDSTATUS4_Pos          (0U)
5622 #define SDIO_RESP4_CARDSTATUS4_Msk          (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
5623 #define SDIO_RESP4_CARDSTATUS4              SDIO_RESP4_CARDSTATUS4_Msk         /*!< Card Status */
5624 
5625 /******************  Bit definition for SDIO_DTIMER register  *****************/
5626 #define SDIO_DTIMER_DATATIME_Pos            (0U)
5627 #define SDIO_DTIMER_DATATIME_Msk            (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
5628 #define SDIO_DTIMER_DATATIME                SDIO_DTIMER_DATATIME_Msk           /*!< Data timeout period. */
5629 
5630 /******************  Bit definition for SDIO_DLEN register  *******************/
5631 #define SDIO_DLEN_DATALENGTH_Pos            (0U)
5632 #define SDIO_DLEN_DATALENGTH_Msk            (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
5633 #define SDIO_DLEN_DATALENGTH                SDIO_DLEN_DATALENGTH_Msk           /*!< Data length value */
5634 
5635 /******************  Bit definition for SDIO_DCTRL register  ******************/
5636 #define SDIO_DCTRL_DTEN_Pos                 (0U)
5637 #define SDIO_DCTRL_DTEN_Msk                 (0x1UL << SDIO_DCTRL_DTEN_Pos)      /*!< 0x00000001 */
5638 #define SDIO_DCTRL_DTEN                     SDIO_DCTRL_DTEN_Msk                /*!< Data transfer enabled bit */
5639 #define SDIO_DCTRL_DTDIR_Pos                (1U)
5640 #define SDIO_DCTRL_DTDIR_Msk                (0x1UL << SDIO_DCTRL_DTDIR_Pos)     /*!< 0x00000002 */
5641 #define SDIO_DCTRL_DTDIR                    SDIO_DCTRL_DTDIR_Msk               /*!< Data transfer direction selection */
5642 #define SDIO_DCTRL_DTMODE_Pos               (2U)
5643 #define SDIO_DCTRL_DTMODE_Msk               (0x1UL << SDIO_DCTRL_DTMODE_Pos)    /*!< 0x00000004 */
5644 #define SDIO_DCTRL_DTMODE                   SDIO_DCTRL_DTMODE_Msk              /*!< Data transfer mode selection */
5645 #define SDIO_DCTRL_DMAEN_Pos                (3U)
5646 #define SDIO_DCTRL_DMAEN_Msk                (0x1UL << SDIO_DCTRL_DMAEN_Pos)     /*!< 0x00000008 */
5647 #define SDIO_DCTRL_DMAEN                    SDIO_DCTRL_DMAEN_Msk               /*!< DMA enabled bit */
5648 
5649 #define SDIO_DCTRL_DBLOCKSIZE_Pos           (4U)
5650 #define SDIO_DCTRL_DBLOCKSIZE_Msk           (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
5651 #define SDIO_DCTRL_DBLOCKSIZE               SDIO_DCTRL_DBLOCKSIZE_Msk          /*!< DBLOCKSIZE[3:0] bits (Data block size) */
5652 #define SDIO_DCTRL_DBLOCKSIZE_0             (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
5653 #define SDIO_DCTRL_DBLOCKSIZE_1             (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
5654 #define SDIO_DCTRL_DBLOCKSIZE_2             (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
5655 #define SDIO_DCTRL_DBLOCKSIZE_3             (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
5656 
5657 #define SDIO_DCTRL_RWSTART_Pos              (8U)
5658 #define SDIO_DCTRL_RWSTART_Msk              (0x1UL << SDIO_DCTRL_RWSTART_Pos)   /*!< 0x00000100 */
5659 #define SDIO_DCTRL_RWSTART                  SDIO_DCTRL_RWSTART_Msk             /*!< Read wait start */
5660 #define SDIO_DCTRL_RWSTOP_Pos               (9U)
5661 #define SDIO_DCTRL_RWSTOP_Msk               (0x1UL << SDIO_DCTRL_RWSTOP_Pos)    /*!< 0x00000200 */
5662 #define SDIO_DCTRL_RWSTOP                   SDIO_DCTRL_RWSTOP_Msk              /*!< Read wait stop */
5663 #define SDIO_DCTRL_RWMOD_Pos                (10U)
5664 #define SDIO_DCTRL_RWMOD_Msk                (0x1UL << SDIO_DCTRL_RWMOD_Pos)     /*!< 0x00000400 */
5665 #define SDIO_DCTRL_RWMOD                    SDIO_DCTRL_RWMOD_Msk               /*!< Read wait mode */
5666 #define SDIO_DCTRL_SDIOEN_Pos               (11U)
5667 #define SDIO_DCTRL_SDIOEN_Msk               (0x1UL << SDIO_DCTRL_SDIOEN_Pos)    /*!< 0x00000800 */
5668 #define SDIO_DCTRL_SDIOEN                   SDIO_DCTRL_SDIOEN_Msk              /*!< SD I/O enable functions */
5669 
5670 /******************  Bit definition for SDIO_DCOUNT register  *****************/
5671 #define SDIO_DCOUNT_DATACOUNT_Pos           (0U)
5672 #define SDIO_DCOUNT_DATACOUNT_Msk           (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
5673 #define SDIO_DCOUNT_DATACOUNT               SDIO_DCOUNT_DATACOUNT_Msk          /*!< Data count value */
5674 
5675 /******************  Bit definition for SDIO_STA register  ********************/
5676 #define SDIO_STA_CCRCFAIL_Pos               (0U)
5677 #define SDIO_STA_CCRCFAIL_Msk               (0x1UL << SDIO_STA_CCRCFAIL_Pos)    /*!< 0x00000001 */
5678 #define SDIO_STA_CCRCFAIL                   SDIO_STA_CCRCFAIL_Msk              /*!< Command response received (CRC check failed) */
5679 #define SDIO_STA_DCRCFAIL_Pos               (1U)
5680 #define SDIO_STA_DCRCFAIL_Msk               (0x1UL << SDIO_STA_DCRCFAIL_Pos)    /*!< 0x00000002 */
5681 #define SDIO_STA_DCRCFAIL                   SDIO_STA_DCRCFAIL_Msk              /*!< Data block sent/received (CRC check failed) */
5682 #define SDIO_STA_CTIMEOUT_Pos               (2U)
5683 #define SDIO_STA_CTIMEOUT_Msk               (0x1UL << SDIO_STA_CTIMEOUT_Pos)    /*!< 0x00000004 */
5684 #define SDIO_STA_CTIMEOUT                   SDIO_STA_CTIMEOUT_Msk              /*!< Command response timeout */
5685 #define SDIO_STA_DTIMEOUT_Pos               (3U)
5686 #define SDIO_STA_DTIMEOUT_Msk               (0x1UL << SDIO_STA_DTIMEOUT_Pos)    /*!< 0x00000008 */
5687 #define SDIO_STA_DTIMEOUT                   SDIO_STA_DTIMEOUT_Msk              /*!< Data timeout */
5688 #define SDIO_STA_TXUNDERR_Pos               (4U)
5689 #define SDIO_STA_TXUNDERR_Msk               (0x1UL << SDIO_STA_TXUNDERR_Pos)    /*!< 0x00000010 */
5690 #define SDIO_STA_TXUNDERR                   SDIO_STA_TXUNDERR_Msk              /*!< Transmit FIFO underrun error */
5691 #define SDIO_STA_RXOVERR_Pos                (5U)
5692 #define SDIO_STA_RXOVERR_Msk                (0x1UL << SDIO_STA_RXOVERR_Pos)     /*!< 0x00000020 */
5693 #define SDIO_STA_RXOVERR                    SDIO_STA_RXOVERR_Msk               /*!< Received FIFO overrun error */
5694 #define SDIO_STA_CMDREND_Pos                (6U)
5695 #define SDIO_STA_CMDREND_Msk                (0x1UL << SDIO_STA_CMDREND_Pos)     /*!< 0x00000040 */
5696 #define SDIO_STA_CMDREND                    SDIO_STA_CMDREND_Msk               /*!< Command response received (CRC check passed) */
5697 #define SDIO_STA_CMDSENT_Pos                (7U)
5698 #define SDIO_STA_CMDSENT_Msk                (0x1UL << SDIO_STA_CMDSENT_Pos)     /*!< 0x00000080 */
5699 #define SDIO_STA_CMDSENT                    SDIO_STA_CMDSENT_Msk               /*!< Command sent (no response required) */
5700 #define SDIO_STA_DATAEND_Pos                (8U)
5701 #define SDIO_STA_DATAEND_Msk                (0x1UL << SDIO_STA_DATAEND_Pos)     /*!< 0x00000100 */
5702 #define SDIO_STA_DATAEND                    SDIO_STA_DATAEND_Msk               /*!< Data end (data counter, SDIDCOUNT, is zero) */
5703 #define SDIO_STA_STBITERR_Pos               (9U)
5704 #define SDIO_STA_STBITERR_Msk               (0x1UL << SDIO_STA_STBITERR_Pos)    /*!< 0x00000200 */
5705 #define SDIO_STA_STBITERR                   SDIO_STA_STBITERR_Msk              /*!< Start bit not detected on all data signals in wide bus mode */
5706 #define SDIO_STA_DBCKEND_Pos                (10U)
5707 #define SDIO_STA_DBCKEND_Msk                (0x1UL << SDIO_STA_DBCKEND_Pos)     /*!< 0x00000400 */
5708 #define SDIO_STA_DBCKEND                    SDIO_STA_DBCKEND_Msk               /*!< Data block sent/received (CRC check passed) */
5709 #define SDIO_STA_CMDACT_Pos                 (11U)
5710 #define SDIO_STA_CMDACT_Msk                 (0x1UL << SDIO_STA_CMDACT_Pos)      /*!< 0x00000800 */
5711 #define SDIO_STA_CMDACT                     SDIO_STA_CMDACT_Msk                /*!< Command transfer in progress */
5712 #define SDIO_STA_TXACT_Pos                  (12U)
5713 #define SDIO_STA_TXACT_Msk                  (0x1UL << SDIO_STA_TXACT_Pos)       /*!< 0x00001000 */
5714 #define SDIO_STA_TXACT                      SDIO_STA_TXACT_Msk                 /*!< Data transmit in progress */
5715 #define SDIO_STA_RXACT_Pos                  (13U)
5716 #define SDIO_STA_RXACT_Msk                  (0x1UL << SDIO_STA_RXACT_Pos)       /*!< 0x00002000 */
5717 #define SDIO_STA_RXACT                      SDIO_STA_RXACT_Msk                 /*!< Data receive in progress */
5718 #define SDIO_STA_TXFIFOHE_Pos               (14U)
5719 #define SDIO_STA_TXFIFOHE_Msk               (0x1UL << SDIO_STA_TXFIFOHE_Pos)    /*!< 0x00004000 */
5720 #define SDIO_STA_TXFIFOHE                   SDIO_STA_TXFIFOHE_Msk              /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
5721 #define SDIO_STA_RXFIFOHF_Pos               (15U)
5722 #define SDIO_STA_RXFIFOHF_Msk               (0x1UL << SDIO_STA_RXFIFOHF_Pos)    /*!< 0x00008000 */
5723 #define SDIO_STA_RXFIFOHF                   SDIO_STA_RXFIFOHF_Msk              /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
5724 #define SDIO_STA_TXFIFOF_Pos                (16U)
5725 #define SDIO_STA_TXFIFOF_Msk                (0x1UL << SDIO_STA_TXFIFOF_Pos)     /*!< 0x00010000 */
5726 #define SDIO_STA_TXFIFOF                    SDIO_STA_TXFIFOF_Msk               /*!< Transmit FIFO full */
5727 #define SDIO_STA_RXFIFOF_Pos                (17U)
5728 #define SDIO_STA_RXFIFOF_Msk                (0x1UL << SDIO_STA_RXFIFOF_Pos)     /*!< 0x00020000 */
5729 #define SDIO_STA_RXFIFOF                    SDIO_STA_RXFIFOF_Msk               /*!< Receive FIFO full */
5730 #define SDIO_STA_TXFIFOE_Pos                (18U)
5731 #define SDIO_STA_TXFIFOE_Msk                (0x1UL << SDIO_STA_TXFIFOE_Pos)     /*!< 0x00040000 */
5732 #define SDIO_STA_TXFIFOE                    SDIO_STA_TXFIFOE_Msk               /*!< Transmit FIFO empty */
5733 #define SDIO_STA_RXFIFOE_Pos                (19U)
5734 #define SDIO_STA_RXFIFOE_Msk                (0x1UL << SDIO_STA_RXFIFOE_Pos)     /*!< 0x00080000 */
5735 #define SDIO_STA_RXFIFOE                    SDIO_STA_RXFIFOE_Msk               /*!< Receive FIFO empty */
5736 #define SDIO_STA_TXDAVL_Pos                 (20U)
5737 #define SDIO_STA_TXDAVL_Msk                 (0x1UL << SDIO_STA_TXDAVL_Pos)      /*!< 0x00100000 */
5738 #define SDIO_STA_TXDAVL                     SDIO_STA_TXDAVL_Msk                /*!< Data available in transmit FIFO */
5739 #define SDIO_STA_RXDAVL_Pos                 (21U)
5740 #define SDIO_STA_RXDAVL_Msk                 (0x1UL << SDIO_STA_RXDAVL_Pos)      /*!< 0x00200000 */
5741 #define SDIO_STA_RXDAVL                     SDIO_STA_RXDAVL_Msk                /*!< Data available in receive FIFO */
5742 #define SDIO_STA_SDIOIT_Pos                 (22U)
5743 #define SDIO_STA_SDIOIT_Msk                 (0x1UL << SDIO_STA_SDIOIT_Pos)      /*!< 0x00400000 */
5744 #define SDIO_STA_SDIOIT                     SDIO_STA_SDIOIT_Msk                /*!< SDIO interrupt received */
5745 #define SDIO_STA_CEATAEND_Pos               (23U)
5746 #define SDIO_STA_CEATAEND_Msk               (0x1UL << SDIO_STA_CEATAEND_Pos)    /*!< 0x00800000 */
5747 #define SDIO_STA_CEATAEND                   SDIO_STA_CEATAEND_Msk              /*!< CE-ATA command completion signal received for CMD61 */
5748 
5749 /*******************  Bit definition for SDIO_ICR register  *******************/
5750 #define SDIO_ICR_CCRCFAILC_Pos              (0U)
5751 #define SDIO_ICR_CCRCFAILC_Msk              (0x1UL << SDIO_ICR_CCRCFAILC_Pos)   /*!< 0x00000001 */
5752 #define SDIO_ICR_CCRCFAILC                  SDIO_ICR_CCRCFAILC_Msk             /*!< CCRCFAIL flag clear bit */
5753 #define SDIO_ICR_DCRCFAILC_Pos              (1U)
5754 #define SDIO_ICR_DCRCFAILC_Msk              (0x1UL << SDIO_ICR_DCRCFAILC_Pos)   /*!< 0x00000002 */
5755 #define SDIO_ICR_DCRCFAILC                  SDIO_ICR_DCRCFAILC_Msk             /*!< DCRCFAIL flag clear bit */
5756 #define SDIO_ICR_CTIMEOUTC_Pos              (2U)
5757 #define SDIO_ICR_CTIMEOUTC_Msk              (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)   /*!< 0x00000004 */
5758 #define SDIO_ICR_CTIMEOUTC                  SDIO_ICR_CTIMEOUTC_Msk             /*!< CTIMEOUT flag clear bit */
5759 #define SDIO_ICR_DTIMEOUTC_Pos              (3U)
5760 #define SDIO_ICR_DTIMEOUTC_Msk              (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)   /*!< 0x00000008 */
5761 #define SDIO_ICR_DTIMEOUTC                  SDIO_ICR_DTIMEOUTC_Msk             /*!< DTIMEOUT flag clear bit */
5762 #define SDIO_ICR_TXUNDERRC_Pos              (4U)
5763 #define SDIO_ICR_TXUNDERRC_Msk              (0x1UL << SDIO_ICR_TXUNDERRC_Pos)   /*!< 0x00000010 */
5764 #define SDIO_ICR_TXUNDERRC                  SDIO_ICR_TXUNDERRC_Msk             /*!< TXUNDERR flag clear bit */
5765 #define SDIO_ICR_RXOVERRC_Pos               (5U)
5766 #define SDIO_ICR_RXOVERRC_Msk               (0x1UL << SDIO_ICR_RXOVERRC_Pos)    /*!< 0x00000020 */
5767 #define SDIO_ICR_RXOVERRC                   SDIO_ICR_RXOVERRC_Msk              /*!< RXOVERR flag clear bit */
5768 #define SDIO_ICR_CMDRENDC_Pos               (6U)
5769 #define SDIO_ICR_CMDRENDC_Msk               (0x1UL << SDIO_ICR_CMDRENDC_Pos)    /*!< 0x00000040 */
5770 #define SDIO_ICR_CMDRENDC                   SDIO_ICR_CMDRENDC_Msk              /*!< CMDREND flag clear bit */
5771 #define SDIO_ICR_CMDSENTC_Pos               (7U)
5772 #define SDIO_ICR_CMDSENTC_Msk               (0x1UL << SDIO_ICR_CMDSENTC_Pos)    /*!< 0x00000080 */
5773 #define SDIO_ICR_CMDSENTC                   SDIO_ICR_CMDSENTC_Msk              /*!< CMDSENT flag clear bit */
5774 #define SDIO_ICR_DATAENDC_Pos               (8U)
5775 #define SDIO_ICR_DATAENDC_Msk               (0x1UL << SDIO_ICR_DATAENDC_Pos)    /*!< 0x00000100 */
5776 #define SDIO_ICR_DATAENDC                   SDIO_ICR_DATAENDC_Msk              /*!< DATAEND flag clear bit */
5777 #define SDIO_ICR_STBITERRC_Pos              (9U)
5778 #define SDIO_ICR_STBITERRC_Msk              (0x1UL << SDIO_ICR_STBITERRC_Pos)   /*!< 0x00000200 */
5779 #define SDIO_ICR_STBITERRC                  SDIO_ICR_STBITERRC_Msk             /*!< STBITERR flag clear bit */
5780 #define SDIO_ICR_DBCKENDC_Pos               (10U)
5781 #define SDIO_ICR_DBCKENDC_Msk               (0x1UL << SDIO_ICR_DBCKENDC_Pos)    /*!< 0x00000400 */
5782 #define SDIO_ICR_DBCKENDC                   SDIO_ICR_DBCKENDC_Msk              /*!< DBCKEND flag clear bit */
5783 #define SDIO_ICR_SDIOITC_Pos                (22U)
5784 #define SDIO_ICR_SDIOITC_Msk                (0x1UL << SDIO_ICR_SDIOITC_Pos)     /*!< 0x00400000 */
5785 #define SDIO_ICR_SDIOITC                    SDIO_ICR_SDIOITC_Msk               /*!< SDIOIT flag clear bit */
5786 #define SDIO_ICR_CEATAENDC_Pos              (23U)
5787 #define SDIO_ICR_CEATAENDC_Msk              (0x1UL << SDIO_ICR_CEATAENDC_Pos)   /*!< 0x00800000 */
5788 #define SDIO_ICR_CEATAENDC                  SDIO_ICR_CEATAENDC_Msk             /*!< CEATAEND flag clear bit */
5789 
5790 /******************  Bit definition for SDIO_MASK register  *******************/
5791 #define SDIO_MASK_CCRCFAILIE_Pos            (0U)
5792 #define SDIO_MASK_CCRCFAILIE_Msk            (0x1UL << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
5793 #define SDIO_MASK_CCRCFAILIE                SDIO_MASK_CCRCFAILIE_Msk           /*!< Command CRC Fail Interrupt Enable */
5794 #define SDIO_MASK_DCRCFAILIE_Pos            (1U)
5795 #define SDIO_MASK_DCRCFAILIE_Msk            (0x1UL << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
5796 #define SDIO_MASK_DCRCFAILIE                SDIO_MASK_DCRCFAILIE_Msk           /*!< Data CRC Fail Interrupt Enable */
5797 #define SDIO_MASK_CTIMEOUTIE_Pos            (2U)
5798 #define SDIO_MASK_CTIMEOUTIE_Msk            (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
5799 #define SDIO_MASK_CTIMEOUTIE                SDIO_MASK_CTIMEOUTIE_Msk           /*!< Command TimeOut Interrupt Enable */
5800 #define SDIO_MASK_DTIMEOUTIE_Pos            (3U)
5801 #define SDIO_MASK_DTIMEOUTIE_Msk            (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
5802 #define SDIO_MASK_DTIMEOUTIE                SDIO_MASK_DTIMEOUTIE_Msk           /*!< Data TimeOut Interrupt Enable */
5803 #define SDIO_MASK_TXUNDERRIE_Pos            (4U)
5804 #define SDIO_MASK_TXUNDERRIE_Msk            (0x1UL << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
5805 #define SDIO_MASK_TXUNDERRIE                SDIO_MASK_TXUNDERRIE_Msk           /*!< Tx FIFO UnderRun Error Interrupt Enable */
5806 #define SDIO_MASK_RXOVERRIE_Pos             (5U)
5807 #define SDIO_MASK_RXOVERRIE_Msk             (0x1UL << SDIO_MASK_RXOVERRIE_Pos)  /*!< 0x00000020 */
5808 #define SDIO_MASK_RXOVERRIE                 SDIO_MASK_RXOVERRIE_Msk            /*!< Rx FIFO OverRun Error Interrupt Enable */
5809 #define SDIO_MASK_CMDRENDIE_Pos             (6U)
5810 #define SDIO_MASK_CMDRENDIE_Msk             (0x1UL << SDIO_MASK_CMDRENDIE_Pos)  /*!< 0x00000040 */
5811 #define SDIO_MASK_CMDRENDIE                 SDIO_MASK_CMDRENDIE_Msk            /*!< Command Response Received Interrupt Enable */
5812 #define SDIO_MASK_CMDSENTIE_Pos             (7U)
5813 #define SDIO_MASK_CMDSENTIE_Msk             (0x1UL << SDIO_MASK_CMDSENTIE_Pos)  /*!< 0x00000080 */
5814 #define SDIO_MASK_CMDSENTIE                 SDIO_MASK_CMDSENTIE_Msk            /*!< Command Sent Interrupt Enable */
5815 #define SDIO_MASK_DATAENDIE_Pos             (8U)
5816 #define SDIO_MASK_DATAENDIE_Msk             (0x1UL << SDIO_MASK_DATAENDIE_Pos)  /*!< 0x00000100 */
5817 #define SDIO_MASK_DATAENDIE                 SDIO_MASK_DATAENDIE_Msk            /*!< Data End Interrupt Enable */
5818 #define SDIO_MASK_STBITERRIE_Pos            (9U)
5819 #define SDIO_MASK_STBITERRIE_Msk            (0x1UL << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
5820 #define SDIO_MASK_STBITERRIE                SDIO_MASK_STBITERRIE_Msk           /*!< Start Bit Error Interrupt Enable */
5821 #define SDIO_MASK_DBCKENDIE_Pos             (10U)
5822 #define SDIO_MASK_DBCKENDIE_Msk             (0x1UL << SDIO_MASK_DBCKENDIE_Pos)  /*!< 0x00000400 */
5823 #define SDIO_MASK_DBCKENDIE                 SDIO_MASK_DBCKENDIE_Msk            /*!< Data Block End Interrupt Enable */
5824 #define SDIO_MASK_CMDACTIE_Pos              (11U)
5825 #define SDIO_MASK_CMDACTIE_Msk              (0x1UL << SDIO_MASK_CMDACTIE_Pos)   /*!< 0x00000800 */
5826 #define SDIO_MASK_CMDACTIE                  SDIO_MASK_CMDACTIE_Msk             /*!< Command Acting Interrupt Enable */
5827 #define SDIO_MASK_TXACTIE_Pos               (12U)
5828 #define SDIO_MASK_TXACTIE_Msk               (0x1UL << SDIO_MASK_TXACTIE_Pos)    /*!< 0x00001000 */
5829 #define SDIO_MASK_TXACTIE                   SDIO_MASK_TXACTIE_Msk              /*!< Data Transmit Acting Interrupt Enable */
5830 #define SDIO_MASK_RXACTIE_Pos               (13U)
5831 #define SDIO_MASK_RXACTIE_Msk               (0x1UL << SDIO_MASK_RXACTIE_Pos)    /*!< 0x00002000 */
5832 #define SDIO_MASK_RXACTIE                   SDIO_MASK_RXACTIE_Msk              /*!< Data receive acting interrupt enabled */
5833 #define SDIO_MASK_TXFIFOHEIE_Pos            (14U)
5834 #define SDIO_MASK_TXFIFOHEIE_Msk            (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
5835 #define SDIO_MASK_TXFIFOHEIE                SDIO_MASK_TXFIFOHEIE_Msk           /*!< Tx FIFO Half Empty interrupt Enable */
5836 #define SDIO_MASK_RXFIFOHFIE_Pos            (15U)
5837 #define SDIO_MASK_RXFIFOHFIE_Msk            (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
5838 #define SDIO_MASK_RXFIFOHFIE                SDIO_MASK_RXFIFOHFIE_Msk           /*!< Rx FIFO Half Full interrupt Enable */
5839 #define SDIO_MASK_TXFIFOFIE_Pos             (16U)
5840 #define SDIO_MASK_TXFIFOFIE_Msk             (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)  /*!< 0x00010000 */
5841 #define SDIO_MASK_TXFIFOFIE                 SDIO_MASK_TXFIFOFIE_Msk            /*!< Tx FIFO Full interrupt Enable */
5842 #define SDIO_MASK_RXFIFOFIE_Pos             (17U)
5843 #define SDIO_MASK_RXFIFOFIE_Msk             (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)  /*!< 0x00020000 */
5844 #define SDIO_MASK_RXFIFOFIE                 SDIO_MASK_RXFIFOFIE_Msk            /*!< Rx FIFO Full interrupt Enable */
5845 #define SDIO_MASK_TXFIFOEIE_Pos             (18U)
5846 #define SDIO_MASK_TXFIFOEIE_Msk             (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)  /*!< 0x00040000 */
5847 #define SDIO_MASK_TXFIFOEIE                 SDIO_MASK_TXFIFOEIE_Msk            /*!< Tx FIFO Empty interrupt Enable */
5848 #define SDIO_MASK_RXFIFOEIE_Pos             (19U)
5849 #define SDIO_MASK_RXFIFOEIE_Msk             (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)  /*!< 0x00080000 */
5850 #define SDIO_MASK_RXFIFOEIE                 SDIO_MASK_RXFIFOEIE_Msk            /*!< Rx FIFO Empty interrupt Enable */
5851 #define SDIO_MASK_TXDAVLIE_Pos              (20U)
5852 #define SDIO_MASK_TXDAVLIE_Msk              (0x1UL << SDIO_MASK_TXDAVLIE_Pos)   /*!< 0x00100000 */
5853 #define SDIO_MASK_TXDAVLIE                  SDIO_MASK_TXDAVLIE_Msk             /*!< Data available in Tx FIFO interrupt Enable */
5854 #define SDIO_MASK_RXDAVLIE_Pos              (21U)
5855 #define SDIO_MASK_RXDAVLIE_Msk              (0x1UL << SDIO_MASK_RXDAVLIE_Pos)   /*!< 0x00200000 */
5856 #define SDIO_MASK_RXDAVLIE                  SDIO_MASK_RXDAVLIE_Msk             /*!< Data available in Rx FIFO interrupt Enable */
5857 #define SDIO_MASK_SDIOITIE_Pos              (22U)
5858 #define SDIO_MASK_SDIOITIE_Msk              (0x1UL << SDIO_MASK_SDIOITIE_Pos)   /*!< 0x00400000 */
5859 #define SDIO_MASK_SDIOITIE                  SDIO_MASK_SDIOITIE_Msk             /*!< SDIO Mode Interrupt Received interrupt Enable */
5860 #define SDIO_MASK_CEATAENDIE_Pos            (23U)
5861 #define SDIO_MASK_CEATAENDIE_Msk            (0x1UL << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
5862 #define SDIO_MASK_CEATAENDIE                SDIO_MASK_CEATAENDIE_Msk           /*!< CE-ATA command completion signal received Interrupt Enable */
5863 
5864 /*****************  Bit definition for SDIO_FIFOCNT register  *****************/
5865 #define SDIO_FIFOCNT_FIFOCOUNT_Pos          (0U)
5866 #define SDIO_FIFOCNT_FIFOCOUNT_Msk          (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
5867 #define SDIO_FIFOCNT_FIFOCOUNT              SDIO_FIFOCNT_FIFOCOUNT_Msk         /*!< Remaining number of words to be written to or read from the FIFO */
5868 
5869 /******************  Bit definition for SDIO_FIFO register  *******************/
5870 #define SDIO_FIFO_FIFODATA_Pos              (0U)
5871 #define SDIO_FIFO_FIFODATA_Msk              (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
5872 #define SDIO_FIFO_FIFODATA                  SDIO_FIFO_FIFODATA_Msk             /*!< Receive and transmit FIFO data */
5873 
5874 /******************************************************************************/
5875 /*                                                                            */
5876 /*                                   USB Device FS                            */
5877 /*                                                                            */
5878 /******************************************************************************/
5879 
5880 /*!< Endpoint-specific registers */
5881 #define  USB_EP0R                            USB_BASE                      /*!< Endpoint 0 register address */
5882 #define  USB_EP1R                            (USB_BASE + 0x00000004)       /*!< Endpoint 1 register address */
5883 #define  USB_EP2R                            (USB_BASE + 0x00000008)       /*!< Endpoint 2 register address */
5884 #define  USB_EP3R                            (USB_BASE + 0x0000000C)       /*!< Endpoint 3 register address */
5885 #define  USB_EP4R                            (USB_BASE + 0x00000010)       /*!< Endpoint 4 register address */
5886 #define  USB_EP5R                            (USB_BASE + 0x00000014)       /*!< Endpoint 5 register address */
5887 #define  USB_EP6R                            (USB_BASE + 0x00000018)       /*!< Endpoint 6 register address */
5888 #define  USB_EP7R                            (USB_BASE + 0x0000001C)       /*!< Endpoint 7 register address */
5889 
5890 /* bit positions */
5891 #define USB_EP_CTR_RX_Pos                       (15U)
5892 #define USB_EP_CTR_RX_Msk                       (0x1UL << USB_EP_CTR_RX_Pos)    /*!< 0x00008000 */
5893 #define USB_EP_CTR_RX                           USB_EP_CTR_RX_Msk              /*!< EndPoint Correct TRansfer RX */
5894 #define USB_EP_DTOG_RX_Pos                      (14U)
5895 #define USB_EP_DTOG_RX_Msk                      (0x1UL << USB_EP_DTOG_RX_Pos)   /*!< 0x00004000 */
5896 #define USB_EP_DTOG_RX                          USB_EP_DTOG_RX_Msk             /*!< EndPoint Data TOGGLE RX */
5897 #define USB_EPRX_STAT_Pos                       (12U)
5898 #define USB_EPRX_STAT_Msk                       (0x3UL << USB_EPRX_STAT_Pos)    /*!< 0x00003000 */
5899 #define USB_EPRX_STAT                           USB_EPRX_STAT_Msk              /*!< EndPoint RX STATus bit field */
5900 #define USB_EP_SETUP_Pos                        (11U)
5901 #define USB_EP_SETUP_Msk                        (0x1UL << USB_EP_SETUP_Pos)     /*!< 0x00000800 */
5902 #define USB_EP_SETUP                            USB_EP_SETUP_Msk               /*!< EndPoint SETUP */
5903 #define USB_EP_T_FIELD_Pos                      (9U)
5904 #define USB_EP_T_FIELD_Msk                      (0x3UL << USB_EP_T_FIELD_Pos)   /*!< 0x00000600 */
5905 #define USB_EP_T_FIELD                          USB_EP_T_FIELD_Msk             /*!< EndPoint TYPE */
5906 #define USB_EP_KIND_Pos                         (8U)
5907 #define USB_EP_KIND_Msk                         (0x1UL << USB_EP_KIND_Pos)      /*!< 0x00000100 */
5908 #define USB_EP_KIND                             USB_EP_KIND_Msk                /*!< EndPoint KIND */
5909 #define USB_EP_CTR_TX_Pos                       (7U)
5910 #define USB_EP_CTR_TX_Msk                       (0x1UL << USB_EP_CTR_TX_Pos)    /*!< 0x00000080 */
5911 #define USB_EP_CTR_TX                           USB_EP_CTR_TX_Msk              /*!< EndPoint Correct TRansfer TX */
5912 #define USB_EP_DTOG_TX_Pos                      (6U)
5913 #define USB_EP_DTOG_TX_Msk                      (0x1UL << USB_EP_DTOG_TX_Pos)   /*!< 0x00000040 */
5914 #define USB_EP_DTOG_TX                          USB_EP_DTOG_TX_Msk             /*!< EndPoint Data TOGGLE TX */
5915 #define USB_EPTX_STAT_Pos                       (4U)
5916 #define USB_EPTX_STAT_Msk                       (0x3UL << USB_EPTX_STAT_Pos)    /*!< 0x00000030 */
5917 #define USB_EPTX_STAT                           USB_EPTX_STAT_Msk              /*!< EndPoint TX STATus bit field */
5918 #define USB_EPADDR_FIELD_Pos                    (0U)
5919 #define USB_EPADDR_FIELD_Msk                    (0xFUL << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */
5920 #define USB_EPADDR_FIELD                        USB_EPADDR_FIELD_Msk           /*!< EndPoint ADDRess FIELD */
5921 
5922 /* EndPoint REGister MASK (no toggle fields) */
5923 #define  USB_EPREG_MASK                      (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
5924                                                                            /*!< EP_TYPE[1:0] EndPoint TYPE */
5925 #define USB_EP_TYPE_MASK_Pos                    (9U)
5926 #define USB_EP_TYPE_MASK_Msk                    (0x3UL << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */
5927 #define USB_EP_TYPE_MASK                        USB_EP_TYPE_MASK_Msk           /*!< EndPoint TYPE Mask */
5928 #define USB_EP_BULK                             0x00000000U                    /*!< EndPoint BULK */
5929 #define USB_EP_CONTROL                          0x00000200U                    /*!< EndPoint CONTROL */
5930 #define USB_EP_ISOCHRONOUS                      0x00000400U                    /*!< EndPoint ISOCHRONOUS */
5931 #define USB_EP_INTERRUPT                        0x00000600U                    /*!< EndPoint INTERRUPT */
5932 #define  USB_EP_T_MASK                          (~USB_EP_T_FIELD & USB_EPREG_MASK)
5933 
5934 #define  USB_EPKIND_MASK                        (~USB_EP_KIND & USB_EPREG_MASK)  /*!< EP_KIND EndPoint KIND */
5935                                                                                /*!< STAT_TX[1:0] STATus for TX transfer */
5936 #define USB_EP_TX_DIS                           0x00000000U                    /*!< EndPoint TX DISabled */
5937 #define USB_EP_TX_STALL                         0x00000010U                    /*!< EndPoint TX STALLed */
5938 #define USB_EP_TX_NAK                           0x00000020U                    /*!< EndPoint TX NAKed */
5939 #define USB_EP_TX_VALID                         0x00000030U                    /*!< EndPoint TX VALID */
5940 #define USB_EPTX_DTOG1                          0x00000010U                    /*!< EndPoint TX Data TOGgle bit1 */
5941 #define USB_EPTX_DTOG2                          0x00000020U                    /*!< EndPoint TX Data TOGgle bit2 */
5942 #define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
5943                                                                                /*!< STAT_RX[1:0] STATus for RX transfer */
5944 #define USB_EP_RX_DIS                           0x00000000U                    /*!< EndPoint RX DISabled */
5945 #define USB_EP_RX_STALL                         0x00001000U                    /*!< EndPoint RX STALLed */
5946 #define USB_EP_RX_NAK                           0x00002000U                    /*!< EndPoint RX NAKed */
5947 #define USB_EP_RX_VALID                         0x00003000U                    /*!< EndPoint RX VALID */
5948 #define USB_EPRX_DTOG1                          0x00001000U                    /*!< EndPoint RX Data TOGgle bit1 */
5949 #define USB_EPRX_DTOG2                          0x00002000U                    /*!< EndPoint RX Data TOGgle bit1 */
5950 #define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
5951 
5952 /*******************  Bit definition for USB_EP0R register  *******************/
5953 #define USB_EP0R_EA_Pos                         (0U)
5954 #define USB_EP0R_EA_Msk                         (0xFUL << USB_EP0R_EA_Pos)      /*!< 0x0000000F */
5955 #define USB_EP0R_EA                             USB_EP0R_EA_Msk                /*!< Endpoint Address */
5956 
5957 #define USB_EP0R_STAT_TX_Pos                    (4U)
5958 #define USB_EP0R_STAT_TX_Msk                    (0x3UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */
5959 #define USB_EP0R_STAT_TX                        USB_EP0R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5960 #define USB_EP0R_STAT_TX_0                      (0x1UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */
5961 #define USB_EP0R_STAT_TX_1                      (0x2UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */
5962 
5963 #define USB_EP0R_DTOG_TX_Pos                    (6U)
5964 #define USB_EP0R_DTOG_TX_Msk                    (0x1UL << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */
5965 #define USB_EP0R_DTOG_TX                        USB_EP0R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
5966 #define USB_EP0R_CTR_TX_Pos                     (7U)
5967 #define USB_EP0R_CTR_TX_Msk                     (0x1UL << USB_EP0R_CTR_TX_Pos)  /*!< 0x00000080 */
5968 #define USB_EP0R_CTR_TX                         USB_EP0R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
5969 #define USB_EP0R_EP_KIND_Pos                    (8U)
5970 #define USB_EP0R_EP_KIND_Msk                    (0x1UL << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */
5971 #define USB_EP0R_EP_KIND                        USB_EP0R_EP_KIND_Msk           /*!< Endpoint Kind */
5972 
5973 #define USB_EP0R_EP_TYPE_Pos                    (9U)
5974 #define USB_EP0R_EP_TYPE_Msk                    (0x3UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */
5975 #define USB_EP0R_EP_TYPE                        USB_EP0R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
5976 #define USB_EP0R_EP_TYPE_0                      (0x1UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */
5977 #define USB_EP0R_EP_TYPE_1                      (0x2UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */
5978 
5979 #define USB_EP0R_SETUP_Pos                      (11U)
5980 #define USB_EP0R_SETUP_Msk                      (0x1UL << USB_EP0R_SETUP_Pos)   /*!< 0x00000800 */
5981 #define USB_EP0R_SETUP                          USB_EP0R_SETUP_Msk             /*!< Setup transaction completed */
5982 
5983 #define USB_EP0R_STAT_RX_Pos                    (12U)
5984 #define USB_EP0R_STAT_RX_Msk                    (0x3UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */
5985 #define USB_EP0R_STAT_RX                        USB_EP0R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
5986 #define USB_EP0R_STAT_RX_0                      (0x1UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */
5987 #define USB_EP0R_STAT_RX_1                      (0x2UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */
5988 
5989 #define USB_EP0R_DTOG_RX_Pos                    (14U)
5990 #define USB_EP0R_DTOG_RX_Msk                    (0x1UL << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */
5991 #define USB_EP0R_DTOG_RX                        USB_EP0R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
5992 #define USB_EP0R_CTR_RX_Pos                     (15U)
5993 #define USB_EP0R_CTR_RX_Msk                     (0x1UL << USB_EP0R_CTR_RX_Pos)  /*!< 0x00008000 */
5994 #define USB_EP0R_CTR_RX                         USB_EP0R_CTR_RX_Msk            /*!< Correct Transfer for reception */
5995 
5996 /*******************  Bit definition for USB_EP1R register  *******************/
5997 #define USB_EP1R_EA_Pos                         (0U)
5998 #define USB_EP1R_EA_Msk                         (0xFUL << USB_EP1R_EA_Pos)      /*!< 0x0000000F */
5999 #define USB_EP1R_EA                             USB_EP1R_EA_Msk                /*!< Endpoint Address */
6000 
6001 #define USB_EP1R_STAT_TX_Pos                    (4U)
6002 #define USB_EP1R_STAT_TX_Msk                    (0x3UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */
6003 #define USB_EP1R_STAT_TX                        USB_EP1R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
6004 #define USB_EP1R_STAT_TX_0                      (0x1UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */
6005 #define USB_EP1R_STAT_TX_1                      (0x2UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */
6006 
6007 #define USB_EP1R_DTOG_TX_Pos                    (6U)
6008 #define USB_EP1R_DTOG_TX_Msk                    (0x1UL << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */
6009 #define USB_EP1R_DTOG_TX                        USB_EP1R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
6010 #define USB_EP1R_CTR_TX_Pos                     (7U)
6011 #define USB_EP1R_CTR_TX_Msk                     (0x1UL << USB_EP1R_CTR_TX_Pos)  /*!< 0x00000080 */
6012 #define USB_EP1R_CTR_TX                         USB_EP1R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
6013 #define USB_EP1R_EP_KIND_Pos                    (8U)
6014 #define USB_EP1R_EP_KIND_Msk                    (0x1UL << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */
6015 #define USB_EP1R_EP_KIND                        USB_EP1R_EP_KIND_Msk           /*!< Endpoint Kind */
6016 
6017 #define USB_EP1R_EP_TYPE_Pos                    (9U)
6018 #define USB_EP1R_EP_TYPE_Msk                    (0x3UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */
6019 #define USB_EP1R_EP_TYPE                        USB_EP1R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
6020 #define USB_EP1R_EP_TYPE_0                      (0x1UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */
6021 #define USB_EP1R_EP_TYPE_1                      (0x2UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */
6022 
6023 #define USB_EP1R_SETUP_Pos                      (11U)
6024 #define USB_EP1R_SETUP_Msk                      (0x1UL << USB_EP1R_SETUP_Pos)   /*!< 0x00000800 */
6025 #define USB_EP1R_SETUP                          USB_EP1R_SETUP_Msk             /*!< Setup transaction completed */
6026 
6027 #define USB_EP1R_STAT_RX_Pos                    (12U)
6028 #define USB_EP1R_STAT_RX_Msk                    (0x3UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */
6029 #define USB_EP1R_STAT_RX                        USB_EP1R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
6030 #define USB_EP1R_STAT_RX_0                      (0x1UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */
6031 #define USB_EP1R_STAT_RX_1                      (0x2UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */
6032 
6033 #define USB_EP1R_DTOG_RX_Pos                    (14U)
6034 #define USB_EP1R_DTOG_RX_Msk                    (0x1UL << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */
6035 #define USB_EP1R_DTOG_RX                        USB_EP1R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
6036 #define USB_EP1R_CTR_RX_Pos                     (15U)
6037 #define USB_EP1R_CTR_RX_Msk                     (0x1UL << USB_EP1R_CTR_RX_Pos)  /*!< 0x00008000 */
6038 #define USB_EP1R_CTR_RX                         USB_EP1R_CTR_RX_Msk            /*!< Correct Transfer for reception */
6039 
6040 /*******************  Bit definition for USB_EP2R register  *******************/
6041 #define USB_EP2R_EA_Pos                         (0U)
6042 #define USB_EP2R_EA_Msk                         (0xFUL << USB_EP2R_EA_Pos)      /*!< 0x0000000F */
6043 #define USB_EP2R_EA                             USB_EP2R_EA_Msk                /*!< Endpoint Address */
6044 
6045 #define USB_EP2R_STAT_TX_Pos                    (4U)
6046 #define USB_EP2R_STAT_TX_Msk                    (0x3UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */
6047 #define USB_EP2R_STAT_TX                        USB_EP2R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
6048 #define USB_EP2R_STAT_TX_0                      (0x1UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */
6049 #define USB_EP2R_STAT_TX_1                      (0x2UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */
6050 
6051 #define USB_EP2R_DTOG_TX_Pos                    (6U)
6052 #define USB_EP2R_DTOG_TX_Msk                    (0x1UL << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */
6053 #define USB_EP2R_DTOG_TX                        USB_EP2R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
6054 #define USB_EP2R_CTR_TX_Pos                     (7U)
6055 #define USB_EP2R_CTR_TX_Msk                     (0x1UL << USB_EP2R_CTR_TX_Pos)  /*!< 0x00000080 */
6056 #define USB_EP2R_CTR_TX                         USB_EP2R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
6057 #define USB_EP2R_EP_KIND_Pos                    (8U)
6058 #define USB_EP2R_EP_KIND_Msk                    (0x1UL << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */
6059 #define USB_EP2R_EP_KIND                        USB_EP2R_EP_KIND_Msk           /*!< Endpoint Kind */
6060 
6061 #define USB_EP2R_EP_TYPE_Pos                    (9U)
6062 #define USB_EP2R_EP_TYPE_Msk                    (0x3UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */
6063 #define USB_EP2R_EP_TYPE                        USB_EP2R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
6064 #define USB_EP2R_EP_TYPE_0                      (0x1UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */
6065 #define USB_EP2R_EP_TYPE_1                      (0x2UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */
6066 
6067 #define USB_EP2R_SETUP_Pos                      (11U)
6068 #define USB_EP2R_SETUP_Msk                      (0x1UL << USB_EP2R_SETUP_Pos)   /*!< 0x00000800 */
6069 #define USB_EP2R_SETUP                          USB_EP2R_SETUP_Msk             /*!< Setup transaction completed */
6070 
6071 #define USB_EP2R_STAT_RX_Pos                    (12U)
6072 #define USB_EP2R_STAT_RX_Msk                    (0x3UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */
6073 #define USB_EP2R_STAT_RX                        USB_EP2R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
6074 #define USB_EP2R_STAT_RX_0                      (0x1UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */
6075 #define USB_EP2R_STAT_RX_1                      (0x2UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */
6076 
6077 #define USB_EP2R_DTOG_RX_Pos                    (14U)
6078 #define USB_EP2R_DTOG_RX_Msk                    (0x1UL << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */
6079 #define USB_EP2R_DTOG_RX                        USB_EP2R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
6080 #define USB_EP2R_CTR_RX_Pos                     (15U)
6081 #define USB_EP2R_CTR_RX_Msk                     (0x1UL << USB_EP2R_CTR_RX_Pos)  /*!< 0x00008000 */
6082 #define USB_EP2R_CTR_RX                         USB_EP2R_CTR_RX_Msk            /*!< Correct Transfer for reception */
6083 
6084 /*******************  Bit definition for USB_EP3R register  *******************/
6085 #define USB_EP3R_EA_Pos                         (0U)
6086 #define USB_EP3R_EA_Msk                         (0xFUL << USB_EP3R_EA_Pos)      /*!< 0x0000000F */
6087 #define USB_EP3R_EA                             USB_EP3R_EA_Msk                /*!< Endpoint Address */
6088 
6089 #define USB_EP3R_STAT_TX_Pos                    (4U)
6090 #define USB_EP3R_STAT_TX_Msk                    (0x3UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */
6091 #define USB_EP3R_STAT_TX                        USB_EP3R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
6092 #define USB_EP3R_STAT_TX_0                      (0x1UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */
6093 #define USB_EP3R_STAT_TX_1                      (0x2UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */
6094 
6095 #define USB_EP3R_DTOG_TX_Pos                    (6U)
6096 #define USB_EP3R_DTOG_TX_Msk                    (0x1UL << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */
6097 #define USB_EP3R_DTOG_TX                        USB_EP3R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
6098 #define USB_EP3R_CTR_TX_Pos                     (7U)
6099 #define USB_EP3R_CTR_TX_Msk                     (0x1UL << USB_EP3R_CTR_TX_Pos)  /*!< 0x00000080 */
6100 #define USB_EP3R_CTR_TX                         USB_EP3R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
6101 #define USB_EP3R_EP_KIND_Pos                    (8U)
6102 #define USB_EP3R_EP_KIND_Msk                    (0x1UL << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */
6103 #define USB_EP3R_EP_KIND                        USB_EP3R_EP_KIND_Msk           /*!< Endpoint Kind */
6104 
6105 #define USB_EP3R_EP_TYPE_Pos                    (9U)
6106 #define USB_EP3R_EP_TYPE_Msk                    (0x3UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */
6107 #define USB_EP3R_EP_TYPE                        USB_EP3R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
6108 #define USB_EP3R_EP_TYPE_0                      (0x1UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */
6109 #define USB_EP3R_EP_TYPE_1                      (0x2UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */
6110 
6111 #define USB_EP3R_SETUP_Pos                      (11U)
6112 #define USB_EP3R_SETUP_Msk                      (0x1UL << USB_EP3R_SETUP_Pos)   /*!< 0x00000800 */
6113 #define USB_EP3R_SETUP                          USB_EP3R_SETUP_Msk             /*!< Setup transaction completed */
6114 
6115 #define USB_EP3R_STAT_RX_Pos                    (12U)
6116 #define USB_EP3R_STAT_RX_Msk                    (0x3UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */
6117 #define USB_EP3R_STAT_RX                        USB_EP3R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
6118 #define USB_EP3R_STAT_RX_0                      (0x1UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */
6119 #define USB_EP3R_STAT_RX_1                      (0x2UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */
6120 
6121 #define USB_EP3R_DTOG_RX_Pos                    (14U)
6122 #define USB_EP3R_DTOG_RX_Msk                    (0x1UL << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */
6123 #define USB_EP3R_DTOG_RX                        USB_EP3R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
6124 #define USB_EP3R_CTR_RX_Pos                     (15U)
6125 #define USB_EP3R_CTR_RX_Msk                     (0x1UL << USB_EP3R_CTR_RX_Pos)  /*!< 0x00008000 */
6126 #define USB_EP3R_CTR_RX                         USB_EP3R_CTR_RX_Msk            /*!< Correct Transfer for reception */
6127 
6128 /*******************  Bit definition for USB_EP4R register  *******************/
6129 #define USB_EP4R_EA_Pos                         (0U)
6130 #define USB_EP4R_EA_Msk                         (0xFUL << USB_EP4R_EA_Pos)      /*!< 0x0000000F */
6131 #define USB_EP4R_EA                             USB_EP4R_EA_Msk                /*!< Endpoint Address */
6132 
6133 #define USB_EP4R_STAT_TX_Pos                    (4U)
6134 #define USB_EP4R_STAT_TX_Msk                    (0x3UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */
6135 #define USB_EP4R_STAT_TX                        USB_EP4R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
6136 #define USB_EP4R_STAT_TX_0                      (0x1UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */
6137 #define USB_EP4R_STAT_TX_1                      (0x2UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */
6138 
6139 #define USB_EP4R_DTOG_TX_Pos                    (6U)
6140 #define USB_EP4R_DTOG_TX_Msk                    (0x1UL << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */
6141 #define USB_EP4R_DTOG_TX                        USB_EP4R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
6142 #define USB_EP4R_CTR_TX_Pos                     (7U)
6143 #define USB_EP4R_CTR_TX_Msk                     (0x1UL << USB_EP4R_CTR_TX_Pos)  /*!< 0x00000080 */
6144 #define USB_EP4R_CTR_TX                         USB_EP4R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
6145 #define USB_EP4R_EP_KIND_Pos                    (8U)
6146 #define USB_EP4R_EP_KIND_Msk                    (0x1UL << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */
6147 #define USB_EP4R_EP_KIND                        USB_EP4R_EP_KIND_Msk           /*!< Endpoint Kind */
6148 
6149 #define USB_EP4R_EP_TYPE_Pos                    (9U)
6150 #define USB_EP4R_EP_TYPE_Msk                    (0x3UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */
6151 #define USB_EP4R_EP_TYPE                        USB_EP4R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
6152 #define USB_EP4R_EP_TYPE_0                      (0x1UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */
6153 #define USB_EP4R_EP_TYPE_1                      (0x2UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */
6154 
6155 #define USB_EP4R_SETUP_Pos                      (11U)
6156 #define USB_EP4R_SETUP_Msk                      (0x1UL << USB_EP4R_SETUP_Pos)   /*!< 0x00000800 */
6157 #define USB_EP4R_SETUP                          USB_EP4R_SETUP_Msk             /*!< Setup transaction completed */
6158 
6159 #define USB_EP4R_STAT_RX_Pos                    (12U)
6160 #define USB_EP4R_STAT_RX_Msk                    (0x3UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */
6161 #define USB_EP4R_STAT_RX                        USB_EP4R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
6162 #define USB_EP4R_STAT_RX_0                      (0x1UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */
6163 #define USB_EP4R_STAT_RX_1                      (0x2UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */
6164 
6165 #define USB_EP4R_DTOG_RX_Pos                    (14U)
6166 #define USB_EP4R_DTOG_RX_Msk                    (0x1UL << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */
6167 #define USB_EP4R_DTOG_RX                        USB_EP4R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
6168 #define USB_EP4R_CTR_RX_Pos                     (15U)
6169 #define USB_EP4R_CTR_RX_Msk                     (0x1UL << USB_EP4R_CTR_RX_Pos)  /*!< 0x00008000 */
6170 #define USB_EP4R_CTR_RX                         USB_EP4R_CTR_RX_Msk            /*!< Correct Transfer for reception */
6171 
6172 /*******************  Bit definition for USB_EP5R register  *******************/
6173 #define USB_EP5R_EA_Pos                         (0U)
6174 #define USB_EP5R_EA_Msk                         (0xFUL << USB_EP5R_EA_Pos)      /*!< 0x0000000F */
6175 #define USB_EP5R_EA                             USB_EP5R_EA_Msk                /*!< Endpoint Address */
6176 
6177 #define USB_EP5R_STAT_TX_Pos                    (4U)
6178 #define USB_EP5R_STAT_TX_Msk                    (0x3UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */
6179 #define USB_EP5R_STAT_TX                        USB_EP5R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
6180 #define USB_EP5R_STAT_TX_0                      (0x1UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */
6181 #define USB_EP5R_STAT_TX_1                      (0x2UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */
6182 
6183 #define USB_EP5R_DTOG_TX_Pos                    (6U)
6184 #define USB_EP5R_DTOG_TX_Msk                    (0x1UL << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */
6185 #define USB_EP5R_DTOG_TX                        USB_EP5R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
6186 #define USB_EP5R_CTR_TX_Pos                     (7U)
6187 #define USB_EP5R_CTR_TX_Msk                     (0x1UL << USB_EP5R_CTR_TX_Pos)  /*!< 0x00000080 */
6188 #define USB_EP5R_CTR_TX                         USB_EP5R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
6189 #define USB_EP5R_EP_KIND_Pos                    (8U)
6190 #define USB_EP5R_EP_KIND_Msk                    (0x1UL << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */
6191 #define USB_EP5R_EP_KIND                        USB_EP5R_EP_KIND_Msk           /*!< Endpoint Kind */
6192 
6193 #define USB_EP5R_EP_TYPE_Pos                    (9U)
6194 #define USB_EP5R_EP_TYPE_Msk                    (0x3UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */
6195 #define USB_EP5R_EP_TYPE                        USB_EP5R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
6196 #define USB_EP5R_EP_TYPE_0                      (0x1UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */
6197 #define USB_EP5R_EP_TYPE_1                      (0x2UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */
6198 
6199 #define USB_EP5R_SETUP_Pos                      (11U)
6200 #define USB_EP5R_SETUP_Msk                      (0x1UL << USB_EP5R_SETUP_Pos)   /*!< 0x00000800 */
6201 #define USB_EP5R_SETUP                          USB_EP5R_SETUP_Msk             /*!< Setup transaction completed */
6202 
6203 #define USB_EP5R_STAT_RX_Pos                    (12U)
6204 #define USB_EP5R_STAT_RX_Msk                    (0x3UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */
6205 #define USB_EP5R_STAT_RX                        USB_EP5R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
6206 #define USB_EP5R_STAT_RX_0                      (0x1UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */
6207 #define USB_EP5R_STAT_RX_1                      (0x2UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */
6208 
6209 #define USB_EP5R_DTOG_RX_Pos                    (14U)
6210 #define USB_EP5R_DTOG_RX_Msk                    (0x1UL << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */
6211 #define USB_EP5R_DTOG_RX                        USB_EP5R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
6212 #define USB_EP5R_CTR_RX_Pos                     (15U)
6213 #define USB_EP5R_CTR_RX_Msk                     (0x1UL << USB_EP5R_CTR_RX_Pos)  /*!< 0x00008000 */
6214 #define USB_EP5R_CTR_RX                         USB_EP5R_CTR_RX_Msk            /*!< Correct Transfer for reception */
6215 
6216 /*******************  Bit definition for USB_EP6R register  *******************/
6217 #define USB_EP6R_EA_Pos                         (0U)
6218 #define USB_EP6R_EA_Msk                         (0xFUL << USB_EP6R_EA_Pos)      /*!< 0x0000000F */
6219 #define USB_EP6R_EA                             USB_EP6R_EA_Msk                /*!< Endpoint Address */
6220 
6221 #define USB_EP6R_STAT_TX_Pos                    (4U)
6222 #define USB_EP6R_STAT_TX_Msk                    (0x3UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */
6223 #define USB_EP6R_STAT_TX                        USB_EP6R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
6224 #define USB_EP6R_STAT_TX_0                      (0x1UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */
6225 #define USB_EP6R_STAT_TX_1                      (0x2UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */
6226 
6227 #define USB_EP6R_DTOG_TX_Pos                    (6U)
6228 #define USB_EP6R_DTOG_TX_Msk                    (0x1UL << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */
6229 #define USB_EP6R_DTOG_TX                        USB_EP6R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
6230 #define USB_EP6R_CTR_TX_Pos                     (7U)
6231 #define USB_EP6R_CTR_TX_Msk                     (0x1UL << USB_EP6R_CTR_TX_Pos)  /*!< 0x00000080 */
6232 #define USB_EP6R_CTR_TX                         USB_EP6R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
6233 #define USB_EP6R_EP_KIND_Pos                    (8U)
6234 #define USB_EP6R_EP_KIND_Msk                    (0x1UL << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */
6235 #define USB_EP6R_EP_KIND                        USB_EP6R_EP_KIND_Msk           /*!< Endpoint Kind */
6236 
6237 #define USB_EP6R_EP_TYPE_Pos                    (9U)
6238 #define USB_EP6R_EP_TYPE_Msk                    (0x3UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */
6239 #define USB_EP6R_EP_TYPE                        USB_EP6R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
6240 #define USB_EP6R_EP_TYPE_0                      (0x1UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */
6241 #define USB_EP6R_EP_TYPE_1                      (0x2UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */
6242 
6243 #define USB_EP6R_SETUP_Pos                      (11U)
6244 #define USB_EP6R_SETUP_Msk                      (0x1UL << USB_EP6R_SETUP_Pos)   /*!< 0x00000800 */
6245 #define USB_EP6R_SETUP                          USB_EP6R_SETUP_Msk             /*!< Setup transaction completed */
6246 
6247 #define USB_EP6R_STAT_RX_Pos                    (12U)
6248 #define USB_EP6R_STAT_RX_Msk                    (0x3UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */
6249 #define USB_EP6R_STAT_RX                        USB_EP6R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
6250 #define USB_EP6R_STAT_RX_0                      (0x1UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */
6251 #define USB_EP6R_STAT_RX_1                      (0x2UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */
6252 
6253 #define USB_EP6R_DTOG_RX_Pos                    (14U)
6254 #define USB_EP6R_DTOG_RX_Msk                    (0x1UL << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */
6255 #define USB_EP6R_DTOG_RX                        USB_EP6R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
6256 #define USB_EP6R_CTR_RX_Pos                     (15U)
6257 #define USB_EP6R_CTR_RX_Msk                     (0x1UL << USB_EP6R_CTR_RX_Pos)  /*!< 0x00008000 */
6258 #define USB_EP6R_CTR_RX                         USB_EP6R_CTR_RX_Msk            /*!< Correct Transfer for reception */
6259 
6260 /*******************  Bit definition for USB_EP7R register  *******************/
6261 #define USB_EP7R_EA_Pos                         (0U)
6262 #define USB_EP7R_EA_Msk                         (0xFUL << USB_EP7R_EA_Pos)      /*!< 0x0000000F */
6263 #define USB_EP7R_EA                             USB_EP7R_EA_Msk                /*!< Endpoint Address */
6264 
6265 #define USB_EP7R_STAT_TX_Pos                    (4U)
6266 #define USB_EP7R_STAT_TX_Msk                    (0x3UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */
6267 #define USB_EP7R_STAT_TX                        USB_EP7R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
6268 #define USB_EP7R_STAT_TX_0                      (0x1UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */
6269 #define USB_EP7R_STAT_TX_1                      (0x2UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */
6270 
6271 #define USB_EP7R_DTOG_TX_Pos                    (6U)
6272 #define USB_EP7R_DTOG_TX_Msk                    (0x1UL << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */
6273 #define USB_EP7R_DTOG_TX                        USB_EP7R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
6274 #define USB_EP7R_CTR_TX_Pos                     (7U)
6275 #define USB_EP7R_CTR_TX_Msk                     (0x1UL << USB_EP7R_CTR_TX_Pos)  /*!< 0x00000080 */
6276 #define USB_EP7R_CTR_TX                         USB_EP7R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
6277 #define USB_EP7R_EP_KIND_Pos                    (8U)
6278 #define USB_EP7R_EP_KIND_Msk                    (0x1UL << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */
6279 #define USB_EP7R_EP_KIND                        USB_EP7R_EP_KIND_Msk           /*!< Endpoint Kind */
6280 
6281 #define USB_EP7R_EP_TYPE_Pos                    (9U)
6282 #define USB_EP7R_EP_TYPE_Msk                    (0x3UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */
6283 #define USB_EP7R_EP_TYPE                        USB_EP7R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
6284 #define USB_EP7R_EP_TYPE_0                      (0x1UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */
6285 #define USB_EP7R_EP_TYPE_1                      (0x2UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */
6286 
6287 #define USB_EP7R_SETUP_Pos                      (11U)
6288 #define USB_EP7R_SETUP_Msk                      (0x1UL << USB_EP7R_SETUP_Pos)   /*!< 0x00000800 */
6289 #define USB_EP7R_SETUP                          USB_EP7R_SETUP_Msk             /*!< Setup transaction completed */
6290 
6291 #define USB_EP7R_STAT_RX_Pos                    (12U)
6292 #define USB_EP7R_STAT_RX_Msk                    (0x3UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */
6293 #define USB_EP7R_STAT_RX                        USB_EP7R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
6294 #define USB_EP7R_STAT_RX_0                      (0x1UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */
6295 #define USB_EP7R_STAT_RX_1                      (0x2UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */
6296 
6297 #define USB_EP7R_DTOG_RX_Pos                    (14U)
6298 #define USB_EP7R_DTOG_RX_Msk                    (0x1UL << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */
6299 #define USB_EP7R_DTOG_RX                        USB_EP7R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
6300 #define USB_EP7R_CTR_RX_Pos                     (15U)
6301 #define USB_EP7R_CTR_RX_Msk                     (0x1UL << USB_EP7R_CTR_RX_Pos)  /*!< 0x00008000 */
6302 #define USB_EP7R_CTR_RX                         USB_EP7R_CTR_RX_Msk            /*!< Correct Transfer for reception */
6303 
6304 /*!< Common registers */
6305 /*******************  Bit definition for USB_CNTR register  *******************/
6306 #define USB_CNTR_FRES_Pos                       (0U)
6307 #define USB_CNTR_FRES_Msk                       (0x1UL << USB_CNTR_FRES_Pos)    /*!< 0x00000001 */
6308 #define USB_CNTR_FRES                           USB_CNTR_FRES_Msk              /*!< Force USB Reset */
6309 #define USB_CNTR_PDWN_Pos                       (1U)
6310 #define USB_CNTR_PDWN_Msk                       (0x1UL << USB_CNTR_PDWN_Pos)    /*!< 0x00000002 */
6311 #define USB_CNTR_PDWN                           USB_CNTR_PDWN_Msk              /*!< Power down */
6312 #define USB_CNTR_LP_MODE_Pos                    (2U)
6313 #define USB_CNTR_LP_MODE_Msk                    (0x1UL << USB_CNTR_LP_MODE_Pos) /*!< 0x00000004 */
6314 #define USB_CNTR_LP_MODE                        USB_CNTR_LP_MODE_Msk           /*!< Low-power mode */
6315 #define USB_CNTR_FSUSP_Pos                      (3U)
6316 #define USB_CNTR_FSUSP_Msk                      (0x1UL << USB_CNTR_FSUSP_Pos)   /*!< 0x00000008 */
6317 #define USB_CNTR_FSUSP                          USB_CNTR_FSUSP_Msk             /*!< Force suspend */
6318 #define USB_CNTR_RESUME_Pos                     (4U)
6319 #define USB_CNTR_RESUME_Msk                     (0x1UL << USB_CNTR_RESUME_Pos)  /*!< 0x00000010 */
6320 #define USB_CNTR_RESUME                         USB_CNTR_RESUME_Msk            /*!< Resume request */
6321 #define USB_CNTR_ESOFM_Pos                      (8U)
6322 #define USB_CNTR_ESOFM_Msk                      (0x1UL << USB_CNTR_ESOFM_Pos)   /*!< 0x00000100 */
6323 #define USB_CNTR_ESOFM                          USB_CNTR_ESOFM_Msk             /*!< Expected Start Of Frame Interrupt Mask */
6324 #define USB_CNTR_SOFM_Pos                       (9U)
6325 #define USB_CNTR_SOFM_Msk                       (0x1UL << USB_CNTR_SOFM_Pos)    /*!< 0x00000200 */
6326 #define USB_CNTR_SOFM                           USB_CNTR_SOFM_Msk              /*!< Start Of Frame Interrupt Mask */
6327 #define USB_CNTR_RESETM_Pos                     (10U)
6328 #define USB_CNTR_RESETM_Msk                     (0x1UL << USB_CNTR_RESETM_Pos)  /*!< 0x00000400 */
6329 #define USB_CNTR_RESETM                         USB_CNTR_RESETM_Msk            /*!< RESET Interrupt Mask */
6330 #define USB_CNTR_SUSPM_Pos                      (11U)
6331 #define USB_CNTR_SUSPM_Msk                      (0x1UL << USB_CNTR_SUSPM_Pos)   /*!< 0x00000800 */
6332 #define USB_CNTR_SUSPM                          USB_CNTR_SUSPM_Msk             /*!< Suspend mode Interrupt Mask */
6333 #define USB_CNTR_WKUPM_Pos                      (12U)
6334 #define USB_CNTR_WKUPM_Msk                      (0x1UL << USB_CNTR_WKUPM_Pos)   /*!< 0x00001000 */
6335 #define USB_CNTR_WKUPM                          USB_CNTR_WKUPM_Msk             /*!< Wakeup Interrupt Mask */
6336 #define USB_CNTR_ERRM_Pos                       (13U)
6337 #define USB_CNTR_ERRM_Msk                       (0x1UL << USB_CNTR_ERRM_Pos)    /*!< 0x00002000 */
6338 #define USB_CNTR_ERRM                           USB_CNTR_ERRM_Msk              /*!< Error Interrupt Mask */
6339 #define USB_CNTR_PMAOVRM_Pos                    (14U)
6340 #define USB_CNTR_PMAOVRM_Msk                    (0x1UL << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */
6341 #define USB_CNTR_PMAOVRM                        USB_CNTR_PMAOVRM_Msk           /*!< Packet Memory Area Over / Underrun Interrupt Mask */
6342 #define USB_CNTR_CTRM_Pos                       (15U)
6343 #define USB_CNTR_CTRM_Msk                       (0x1UL << USB_CNTR_CTRM_Pos)    /*!< 0x00008000 */
6344 #define USB_CNTR_CTRM                           USB_CNTR_CTRM_Msk              /*!< Correct Transfer Interrupt Mask */
6345 
6346 /*******************  Bit definition for USB_ISTR register  *******************/
6347 #define USB_ISTR_EP_ID_Pos                      (0U)
6348 #define USB_ISTR_EP_ID_Msk                      (0xFUL << USB_ISTR_EP_ID_Pos)   /*!< 0x0000000F */
6349 #define USB_ISTR_EP_ID                          USB_ISTR_EP_ID_Msk             /*!< Endpoint Identifier */
6350 #define USB_ISTR_DIR_Pos                        (4U)
6351 #define USB_ISTR_DIR_Msk                        (0x1UL << USB_ISTR_DIR_Pos)     /*!< 0x00000010 */
6352 #define USB_ISTR_DIR                            USB_ISTR_DIR_Msk               /*!< Direction of transaction */
6353 #define USB_ISTR_ESOF_Pos                       (8U)
6354 #define USB_ISTR_ESOF_Msk                       (0x1UL << USB_ISTR_ESOF_Pos)    /*!< 0x00000100 */
6355 #define USB_ISTR_ESOF                           USB_ISTR_ESOF_Msk              /*!< Expected Start Of Frame */
6356 #define USB_ISTR_SOF_Pos                        (9U)
6357 #define USB_ISTR_SOF_Msk                        (0x1UL << USB_ISTR_SOF_Pos)     /*!< 0x00000200 */
6358 #define USB_ISTR_SOF                            USB_ISTR_SOF_Msk               /*!< Start Of Frame */
6359 #define USB_ISTR_RESET_Pos                      (10U)
6360 #define USB_ISTR_RESET_Msk                      (0x1UL << USB_ISTR_RESET_Pos)   /*!< 0x00000400 */
6361 #define USB_ISTR_RESET                          USB_ISTR_RESET_Msk             /*!< USB RESET request */
6362 #define USB_ISTR_SUSP_Pos                       (11U)
6363 #define USB_ISTR_SUSP_Msk                       (0x1UL << USB_ISTR_SUSP_Pos)    /*!< 0x00000800 */
6364 #define USB_ISTR_SUSP                           USB_ISTR_SUSP_Msk              /*!< Suspend mode request */
6365 #define USB_ISTR_WKUP_Pos                       (12U)
6366 #define USB_ISTR_WKUP_Msk                       (0x1UL << USB_ISTR_WKUP_Pos)    /*!< 0x00001000 */
6367 #define USB_ISTR_WKUP                           USB_ISTR_WKUP_Msk              /*!< Wake up */
6368 #define USB_ISTR_ERR_Pos                        (13U)
6369 #define USB_ISTR_ERR_Msk                        (0x1UL << USB_ISTR_ERR_Pos)     /*!< 0x00002000 */
6370 #define USB_ISTR_ERR                            USB_ISTR_ERR_Msk               /*!< Error */
6371 #define USB_ISTR_PMAOVR_Pos                     (14U)
6372 #define USB_ISTR_PMAOVR_Msk                     (0x1UL << USB_ISTR_PMAOVR_Pos)  /*!< 0x00004000 */
6373 #define USB_ISTR_PMAOVR                         USB_ISTR_PMAOVR_Msk            /*!< Packet Memory Area Over / Underrun */
6374 #define USB_ISTR_CTR_Pos                        (15U)
6375 #define USB_ISTR_CTR_Msk                        (0x1UL << USB_ISTR_CTR_Pos)     /*!< 0x00008000 */
6376 #define USB_ISTR_CTR                            USB_ISTR_CTR_Msk               /*!< Correct Transfer */
6377 
6378 /*******************  Bit definition for USB_FNR register  ********************/
6379 #define USB_FNR_FN_Pos                          (0U)
6380 #define USB_FNR_FN_Msk                          (0x7FFUL << USB_FNR_FN_Pos)     /*!< 0x000007FF */
6381 #define USB_FNR_FN                              USB_FNR_FN_Msk                 /*!< Frame Number */
6382 #define USB_FNR_LSOF_Pos                        (11U)
6383 #define USB_FNR_LSOF_Msk                        (0x3UL << USB_FNR_LSOF_Pos)     /*!< 0x00001800 */
6384 #define USB_FNR_LSOF                            USB_FNR_LSOF_Msk               /*!< Lost SOF */
6385 #define USB_FNR_LCK_Pos                         (13U)
6386 #define USB_FNR_LCK_Msk                         (0x1UL << USB_FNR_LCK_Pos)      /*!< 0x00002000 */
6387 #define USB_FNR_LCK                             USB_FNR_LCK_Msk                /*!< Locked */
6388 #define USB_FNR_RXDM_Pos                        (14U)
6389 #define USB_FNR_RXDM_Msk                        (0x1UL << USB_FNR_RXDM_Pos)     /*!< 0x00004000 */
6390 #define USB_FNR_RXDM                            USB_FNR_RXDM_Msk               /*!< Receive Data - Line Status */
6391 #define USB_FNR_RXDP_Pos                        (15U)
6392 #define USB_FNR_RXDP_Msk                        (0x1UL << USB_FNR_RXDP_Pos)     /*!< 0x00008000 */
6393 #define USB_FNR_RXDP                            USB_FNR_RXDP_Msk               /*!< Receive Data + Line Status */
6394 
6395 /******************  Bit definition for USB_DADDR register  *******************/
6396 #define USB_DADDR_ADD_Pos                       (0U)
6397 #define USB_DADDR_ADD_Msk                       (0x7FUL << USB_DADDR_ADD_Pos)   /*!< 0x0000007F */
6398 #define USB_DADDR_ADD                           USB_DADDR_ADD_Msk              /*!< ADD[6:0] bits (Device Address) */
6399 #define USB_DADDR_ADD0_Pos                      (0U)
6400 #define USB_DADDR_ADD0_Msk                      (0x1UL << USB_DADDR_ADD0_Pos)   /*!< 0x00000001 */
6401 #define USB_DADDR_ADD0                          USB_DADDR_ADD0_Msk             /*!< Bit 0 */
6402 #define USB_DADDR_ADD1_Pos                      (1U)
6403 #define USB_DADDR_ADD1_Msk                      (0x1UL << USB_DADDR_ADD1_Pos)   /*!< 0x00000002 */
6404 #define USB_DADDR_ADD1                          USB_DADDR_ADD1_Msk             /*!< Bit 1 */
6405 #define USB_DADDR_ADD2_Pos                      (2U)
6406 #define USB_DADDR_ADD2_Msk                      (0x1UL << USB_DADDR_ADD2_Pos)   /*!< 0x00000004 */
6407 #define USB_DADDR_ADD2                          USB_DADDR_ADD2_Msk             /*!< Bit 2 */
6408 #define USB_DADDR_ADD3_Pos                      (3U)
6409 #define USB_DADDR_ADD3_Msk                      (0x1UL << USB_DADDR_ADD3_Pos)   /*!< 0x00000008 */
6410 #define USB_DADDR_ADD3                          USB_DADDR_ADD3_Msk             /*!< Bit 3 */
6411 #define USB_DADDR_ADD4_Pos                      (4U)
6412 #define USB_DADDR_ADD4_Msk                      (0x1UL << USB_DADDR_ADD4_Pos)   /*!< 0x00000010 */
6413 #define USB_DADDR_ADD4                          USB_DADDR_ADD4_Msk             /*!< Bit 4 */
6414 #define USB_DADDR_ADD5_Pos                      (5U)
6415 #define USB_DADDR_ADD5_Msk                      (0x1UL << USB_DADDR_ADD5_Pos)   /*!< 0x00000020 */
6416 #define USB_DADDR_ADD5                          USB_DADDR_ADD5_Msk             /*!< Bit 5 */
6417 #define USB_DADDR_ADD6_Pos                      (6U)
6418 #define USB_DADDR_ADD6_Msk                      (0x1UL << USB_DADDR_ADD6_Pos)   /*!< 0x00000040 */
6419 #define USB_DADDR_ADD6                          USB_DADDR_ADD6_Msk             /*!< Bit 6 */
6420 
6421 #define USB_DADDR_EF_Pos                        (7U)
6422 #define USB_DADDR_EF_Msk                        (0x1UL << USB_DADDR_EF_Pos)     /*!< 0x00000080 */
6423 #define USB_DADDR_EF                            USB_DADDR_EF_Msk               /*!< Enable Function */
6424 
6425 /******************  Bit definition for USB_BTABLE register  ******************/
6426 #define USB_BTABLE_BTABLE_Pos                   (3U)
6427 #define USB_BTABLE_BTABLE_Msk                   (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
6428 #define USB_BTABLE_BTABLE                       USB_BTABLE_BTABLE_Msk          /*!< Buffer Table */
6429 
6430 /*!< Buffer descriptor table */
6431 /*****************  Bit definition for USB_ADDR0_TX register  *****************/
6432 #define USB_ADDR0_TX_ADDR0_TX_Pos               (1U)
6433 #define USB_ADDR0_TX_ADDR0_TX_Msk               (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
6434 #define USB_ADDR0_TX_ADDR0_TX                   USB_ADDR0_TX_ADDR0_TX_Msk      /*!< Transmission Buffer Address 0 */
6435 
6436 /*****************  Bit definition for USB_ADDR1_TX register  *****************/
6437 #define USB_ADDR1_TX_ADDR1_TX_Pos               (1U)
6438 #define USB_ADDR1_TX_ADDR1_TX_Msk               (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
6439 #define USB_ADDR1_TX_ADDR1_TX                   USB_ADDR1_TX_ADDR1_TX_Msk      /*!< Transmission Buffer Address 1 */
6440 
6441 /*****************  Bit definition for USB_ADDR2_TX register  *****************/
6442 #define USB_ADDR2_TX_ADDR2_TX_Pos               (1U)
6443 #define USB_ADDR2_TX_ADDR2_TX_Msk               (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
6444 #define USB_ADDR2_TX_ADDR2_TX                   USB_ADDR2_TX_ADDR2_TX_Msk      /*!< Transmission Buffer Address 2 */
6445 
6446 /*****************  Bit definition for USB_ADDR3_TX register  *****************/
6447 #define USB_ADDR3_TX_ADDR3_TX_Pos               (1U)
6448 #define USB_ADDR3_TX_ADDR3_TX_Msk               (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
6449 #define USB_ADDR3_TX_ADDR3_TX                   USB_ADDR3_TX_ADDR3_TX_Msk      /*!< Transmission Buffer Address 3 */
6450 
6451 /*****************  Bit definition for USB_ADDR4_TX register  *****************/
6452 #define USB_ADDR4_TX_ADDR4_TX_Pos               (1U)
6453 #define USB_ADDR4_TX_ADDR4_TX_Msk               (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
6454 #define USB_ADDR4_TX_ADDR4_TX                   USB_ADDR4_TX_ADDR4_TX_Msk      /*!< Transmission Buffer Address 4 */
6455 
6456 /*****************  Bit definition for USB_ADDR5_TX register  *****************/
6457 #define USB_ADDR5_TX_ADDR5_TX_Pos               (1U)
6458 #define USB_ADDR5_TX_ADDR5_TX_Msk               (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
6459 #define USB_ADDR5_TX_ADDR5_TX                   USB_ADDR5_TX_ADDR5_TX_Msk      /*!< Transmission Buffer Address 5 */
6460 
6461 /*****************  Bit definition for USB_ADDR6_TX register  *****************/
6462 #define USB_ADDR6_TX_ADDR6_TX_Pos               (1U)
6463 #define USB_ADDR6_TX_ADDR6_TX_Msk               (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
6464 #define USB_ADDR6_TX_ADDR6_TX                   USB_ADDR6_TX_ADDR6_TX_Msk      /*!< Transmission Buffer Address 6 */
6465 
6466 /*****************  Bit definition for USB_ADDR7_TX register  *****************/
6467 #define USB_ADDR7_TX_ADDR7_TX_Pos               (1U)
6468 #define USB_ADDR7_TX_ADDR7_TX_Msk               (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
6469 #define USB_ADDR7_TX_ADDR7_TX                   USB_ADDR7_TX_ADDR7_TX_Msk      /*!< Transmission Buffer Address 7 */
6470 
6471 /*----------------------------------------------------------------------------*/
6472 
6473 /*****************  Bit definition for USB_COUNT0_TX register  ****************/
6474 #define USB_COUNT0_TX_COUNT0_TX_Pos             (0U)
6475 #define USB_COUNT0_TX_COUNT0_TX_Msk             (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
6476 #define USB_COUNT0_TX_COUNT0_TX                 USB_COUNT0_TX_COUNT0_TX_Msk    /*!< Transmission Byte Count 0 */
6477 
6478 /*****************  Bit definition for USB_COUNT1_TX register  ****************/
6479 #define USB_COUNT1_TX_COUNT1_TX_Pos             (0U)
6480 #define USB_COUNT1_TX_COUNT1_TX_Msk             (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
6481 #define USB_COUNT1_TX_COUNT1_TX                 USB_COUNT1_TX_COUNT1_TX_Msk    /*!< Transmission Byte Count 1 */
6482 
6483 /*****************  Bit definition for USB_COUNT2_TX register  ****************/
6484 #define USB_COUNT2_TX_COUNT2_TX_Pos             (0U)
6485 #define USB_COUNT2_TX_COUNT2_TX_Msk             (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
6486 #define USB_COUNT2_TX_COUNT2_TX                 USB_COUNT2_TX_COUNT2_TX_Msk    /*!< Transmission Byte Count 2 */
6487 
6488 /*****************  Bit definition for USB_COUNT3_TX register  ****************/
6489 #define USB_COUNT3_TX_COUNT3_TX_Pos             (0U)
6490 #define USB_COUNT3_TX_COUNT3_TX_Msk             (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
6491 #define USB_COUNT3_TX_COUNT3_TX                 USB_COUNT3_TX_COUNT3_TX_Msk    /*!< Transmission Byte Count 3 */
6492 
6493 /*****************  Bit definition for USB_COUNT4_TX register  ****************/
6494 #define USB_COUNT4_TX_COUNT4_TX_Pos             (0U)
6495 #define USB_COUNT4_TX_COUNT4_TX_Msk             (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
6496 #define USB_COUNT4_TX_COUNT4_TX                 USB_COUNT4_TX_COUNT4_TX_Msk    /*!< Transmission Byte Count 4 */
6497 
6498 /*****************  Bit definition for USB_COUNT5_TX register  ****************/
6499 #define USB_COUNT5_TX_COUNT5_TX_Pos             (0U)
6500 #define USB_COUNT5_TX_COUNT5_TX_Msk             (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
6501 #define USB_COUNT5_TX_COUNT5_TX                 USB_COUNT5_TX_COUNT5_TX_Msk    /*!< Transmission Byte Count 5 */
6502 
6503 /*****************  Bit definition for USB_COUNT6_TX register  ****************/
6504 #define USB_COUNT6_TX_COUNT6_TX_Pos             (0U)
6505 #define USB_COUNT6_TX_COUNT6_TX_Msk             (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
6506 #define USB_COUNT6_TX_COUNT6_TX                 USB_COUNT6_TX_COUNT6_TX_Msk    /*!< Transmission Byte Count 6 */
6507 
6508 /*****************  Bit definition for USB_COUNT7_TX register  ****************/
6509 #define USB_COUNT7_TX_COUNT7_TX_Pos             (0U)
6510 #define USB_COUNT7_TX_COUNT7_TX_Msk             (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
6511 #define USB_COUNT7_TX_COUNT7_TX                 USB_COUNT7_TX_COUNT7_TX_Msk    /*!< Transmission Byte Count 7 */
6512 
6513 /*----------------------------------------------------------------------------*/
6514 
6515 /****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
6516 #define USB_COUNT0_TX_0_COUNT0_TX_0             0x000003FFU         /*!< Transmission Byte Count 0 (low) */
6517 
6518 /****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
6519 #define USB_COUNT0_TX_1_COUNT0_TX_1             0x03FF0000U         /*!< Transmission Byte Count 0 (high) */
6520 
6521 /****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
6522 #define USB_COUNT1_TX_0_COUNT1_TX_0             0x000003FFU         /*!< Transmission Byte Count 1 (low) */
6523 
6524 /****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
6525 #define USB_COUNT1_TX_1_COUNT1_TX_1             0x03FF0000U         /*!< Transmission Byte Count 1 (high) */
6526 
6527 /****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
6528 #define USB_COUNT2_TX_0_COUNT2_TX_0             0x000003FFU         /*!< Transmission Byte Count 2 (low) */
6529 
6530 /****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
6531 #define USB_COUNT2_TX_1_COUNT2_TX_1             0x03FF0000U         /*!< Transmission Byte Count 2 (high) */
6532 
6533 /****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
6534 #define USB_COUNT3_TX_0_COUNT3_TX_0             0x000003FFU         /*!< Transmission Byte Count 3 (low) */
6535 
6536 /****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
6537 #define USB_COUNT3_TX_1_COUNT3_TX_1             0x03FF0000U         /*!< Transmission Byte Count 3 (high) */
6538 
6539 /****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
6540 #define USB_COUNT4_TX_0_COUNT4_TX_0             0x000003FFU         /*!< Transmission Byte Count 4 (low) */
6541 
6542 /****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
6543 #define USB_COUNT4_TX_1_COUNT4_TX_1             0x03FF0000U         /*!< Transmission Byte Count 4 (high) */
6544 
6545 /****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
6546 #define USB_COUNT5_TX_0_COUNT5_TX_0             0x000003FFU         /*!< Transmission Byte Count 5 (low) */
6547 
6548 /****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
6549 #define USB_COUNT5_TX_1_COUNT5_TX_1             0x03FF0000U         /*!< Transmission Byte Count 5 (high) */
6550 
6551 /****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
6552 #define USB_COUNT6_TX_0_COUNT6_TX_0             0x000003FFU         /*!< Transmission Byte Count 6 (low) */
6553 
6554 /****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
6555 #define USB_COUNT6_TX_1_COUNT6_TX_1             0x03FF0000U         /*!< Transmission Byte Count 6 (high) */
6556 
6557 /****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
6558 #define USB_COUNT7_TX_0_COUNT7_TX_0             0x000003FFU         /*!< Transmission Byte Count 7 (low) */
6559 
6560 /****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
6561 #define USB_COUNT7_TX_1_COUNT7_TX_1             0x03FF0000U         /*!< Transmission Byte Count 7 (high) */
6562 
6563 /*----------------------------------------------------------------------------*/
6564 
6565 /*****************  Bit definition for USB_ADDR0_RX register  *****************/
6566 #define USB_ADDR0_RX_ADDR0_RX_Pos               (1U)
6567 #define USB_ADDR0_RX_ADDR0_RX_Msk               (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
6568 #define USB_ADDR0_RX_ADDR0_RX                   USB_ADDR0_RX_ADDR0_RX_Msk      /*!< Reception Buffer Address 0 */
6569 
6570 /*****************  Bit definition for USB_ADDR1_RX register  *****************/
6571 #define USB_ADDR1_RX_ADDR1_RX_Pos               (1U)
6572 #define USB_ADDR1_RX_ADDR1_RX_Msk               (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
6573 #define USB_ADDR1_RX_ADDR1_RX                   USB_ADDR1_RX_ADDR1_RX_Msk      /*!< Reception Buffer Address 1 */
6574 
6575 /*****************  Bit definition for USB_ADDR2_RX register  *****************/
6576 #define USB_ADDR2_RX_ADDR2_RX_Pos               (1U)
6577 #define USB_ADDR2_RX_ADDR2_RX_Msk               (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
6578 #define USB_ADDR2_RX_ADDR2_RX                   USB_ADDR2_RX_ADDR2_RX_Msk      /*!< Reception Buffer Address 2 */
6579 
6580 /*****************  Bit definition for USB_ADDR3_RX register  *****************/
6581 #define USB_ADDR3_RX_ADDR3_RX_Pos               (1U)
6582 #define USB_ADDR3_RX_ADDR3_RX_Msk               (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
6583 #define USB_ADDR3_RX_ADDR3_RX                   USB_ADDR3_RX_ADDR3_RX_Msk      /*!< Reception Buffer Address 3 */
6584 
6585 /*****************  Bit definition for USB_ADDR4_RX register  *****************/
6586 #define USB_ADDR4_RX_ADDR4_RX_Pos               (1U)
6587 #define USB_ADDR4_RX_ADDR4_RX_Msk               (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
6588 #define USB_ADDR4_RX_ADDR4_RX                   USB_ADDR4_RX_ADDR4_RX_Msk      /*!< Reception Buffer Address 4 */
6589 
6590 /*****************  Bit definition for USB_ADDR5_RX register  *****************/
6591 #define USB_ADDR5_RX_ADDR5_RX_Pos               (1U)
6592 #define USB_ADDR5_RX_ADDR5_RX_Msk               (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
6593 #define USB_ADDR5_RX_ADDR5_RX                   USB_ADDR5_RX_ADDR5_RX_Msk      /*!< Reception Buffer Address 5 */
6594 
6595 /*****************  Bit definition for USB_ADDR6_RX register  *****************/
6596 #define USB_ADDR6_RX_ADDR6_RX_Pos               (1U)
6597 #define USB_ADDR6_RX_ADDR6_RX_Msk               (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
6598 #define USB_ADDR6_RX_ADDR6_RX                   USB_ADDR6_RX_ADDR6_RX_Msk      /*!< Reception Buffer Address 6 */
6599 
6600 /*****************  Bit definition for USB_ADDR7_RX register  *****************/
6601 #define USB_ADDR7_RX_ADDR7_RX_Pos               (1U)
6602 #define USB_ADDR7_RX_ADDR7_RX_Msk               (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
6603 #define USB_ADDR7_RX_ADDR7_RX                   USB_ADDR7_RX_ADDR7_RX_Msk      /*!< Reception Buffer Address 7 */
6604 
6605 /*----------------------------------------------------------------------------*/
6606 
6607 /*****************  Bit definition for USB_COUNT0_RX register  ****************/
6608 #define USB_COUNT0_RX_COUNT0_RX_Pos             (0U)
6609 #define USB_COUNT0_RX_COUNT0_RX_Msk             (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
6610 #define USB_COUNT0_RX_COUNT0_RX                 USB_COUNT0_RX_COUNT0_RX_Msk    /*!< Reception Byte Count */
6611 
6612 #define USB_COUNT0_RX_NUM_BLOCK_Pos             (10U)
6613 #define USB_COUNT0_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
6614 #define USB_COUNT0_RX_NUM_BLOCK                 USB_COUNT0_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
6615 #define USB_COUNT0_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
6616 #define USB_COUNT0_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
6617 #define USB_COUNT0_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
6618 #define USB_COUNT0_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
6619 #define USB_COUNT0_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
6620 
6621 #define USB_COUNT0_RX_BLSIZE_Pos                (15U)
6622 #define USB_COUNT0_RX_BLSIZE_Msk                (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
6623 #define USB_COUNT0_RX_BLSIZE                    USB_COUNT0_RX_BLSIZE_Msk       /*!< BLock SIZE */
6624 
6625 /*****************  Bit definition for USB_COUNT1_RX register  ****************/
6626 #define USB_COUNT1_RX_COUNT1_RX_Pos             (0U)
6627 #define USB_COUNT1_RX_COUNT1_RX_Msk             (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
6628 #define USB_COUNT1_RX_COUNT1_RX                 USB_COUNT1_RX_COUNT1_RX_Msk    /*!< Reception Byte Count */
6629 
6630 #define USB_COUNT1_RX_NUM_BLOCK_Pos             (10U)
6631 #define USB_COUNT1_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
6632 #define USB_COUNT1_RX_NUM_BLOCK                 USB_COUNT1_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
6633 #define USB_COUNT1_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
6634 #define USB_COUNT1_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
6635 #define USB_COUNT1_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
6636 #define USB_COUNT1_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
6637 #define USB_COUNT1_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
6638 
6639 #define USB_COUNT1_RX_BLSIZE_Pos                (15U)
6640 #define USB_COUNT1_RX_BLSIZE_Msk                (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
6641 #define USB_COUNT1_RX_BLSIZE                    USB_COUNT1_RX_BLSIZE_Msk       /*!< BLock SIZE */
6642 
6643 /*****************  Bit definition for USB_COUNT2_RX register  ****************/
6644 #define USB_COUNT2_RX_COUNT2_RX_Pos             (0U)
6645 #define USB_COUNT2_RX_COUNT2_RX_Msk             (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
6646 #define USB_COUNT2_RX_COUNT2_RX                 USB_COUNT2_RX_COUNT2_RX_Msk    /*!< Reception Byte Count */
6647 
6648 #define USB_COUNT2_RX_NUM_BLOCK_Pos             (10U)
6649 #define USB_COUNT2_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
6650 #define USB_COUNT2_RX_NUM_BLOCK                 USB_COUNT2_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
6651 #define USB_COUNT2_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
6652 #define USB_COUNT2_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
6653 #define USB_COUNT2_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
6654 #define USB_COUNT2_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
6655 #define USB_COUNT2_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
6656 
6657 #define USB_COUNT2_RX_BLSIZE_Pos                (15U)
6658 #define USB_COUNT2_RX_BLSIZE_Msk                (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
6659 #define USB_COUNT2_RX_BLSIZE                    USB_COUNT2_RX_BLSIZE_Msk       /*!< BLock SIZE */
6660 
6661 /*****************  Bit definition for USB_COUNT3_RX register  ****************/
6662 #define USB_COUNT3_RX_COUNT3_RX_Pos             (0U)
6663 #define USB_COUNT3_RX_COUNT3_RX_Msk             (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
6664 #define USB_COUNT3_RX_COUNT3_RX                 USB_COUNT3_RX_COUNT3_RX_Msk    /*!< Reception Byte Count */
6665 
6666 #define USB_COUNT3_RX_NUM_BLOCK_Pos             (10U)
6667 #define USB_COUNT3_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
6668 #define USB_COUNT3_RX_NUM_BLOCK                 USB_COUNT3_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
6669 #define USB_COUNT3_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
6670 #define USB_COUNT3_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
6671 #define USB_COUNT3_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
6672 #define USB_COUNT3_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
6673 #define USB_COUNT3_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
6674 
6675 #define USB_COUNT3_RX_BLSIZE_Pos                (15U)
6676 #define USB_COUNT3_RX_BLSIZE_Msk                (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
6677 #define USB_COUNT3_RX_BLSIZE                    USB_COUNT3_RX_BLSIZE_Msk       /*!< BLock SIZE */
6678 
6679 /*****************  Bit definition for USB_COUNT4_RX register  ****************/
6680 #define USB_COUNT4_RX_COUNT4_RX_Pos             (0U)
6681 #define USB_COUNT4_RX_COUNT4_RX_Msk             (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
6682 #define USB_COUNT4_RX_COUNT4_RX                 USB_COUNT4_RX_COUNT4_RX_Msk    /*!< Reception Byte Count */
6683 
6684 #define USB_COUNT4_RX_NUM_BLOCK_Pos             (10U)
6685 #define USB_COUNT4_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
6686 #define USB_COUNT4_RX_NUM_BLOCK                 USB_COUNT4_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
6687 #define USB_COUNT4_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
6688 #define USB_COUNT4_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
6689 #define USB_COUNT4_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
6690 #define USB_COUNT4_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
6691 #define USB_COUNT4_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
6692 
6693 #define USB_COUNT4_RX_BLSIZE_Pos                (15U)
6694 #define USB_COUNT4_RX_BLSIZE_Msk                (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
6695 #define USB_COUNT4_RX_BLSIZE                    USB_COUNT4_RX_BLSIZE_Msk       /*!< BLock SIZE */
6696 
6697 /*****************  Bit definition for USB_COUNT5_RX register  ****************/
6698 #define USB_COUNT5_RX_COUNT5_RX_Pos             (0U)
6699 #define USB_COUNT5_RX_COUNT5_RX_Msk             (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
6700 #define USB_COUNT5_RX_COUNT5_RX                 USB_COUNT5_RX_COUNT5_RX_Msk    /*!< Reception Byte Count */
6701 
6702 #define USB_COUNT5_RX_NUM_BLOCK_Pos             (10U)
6703 #define USB_COUNT5_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
6704 #define USB_COUNT5_RX_NUM_BLOCK                 USB_COUNT5_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
6705 #define USB_COUNT5_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
6706 #define USB_COUNT5_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
6707 #define USB_COUNT5_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
6708 #define USB_COUNT5_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
6709 #define USB_COUNT5_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
6710 
6711 #define USB_COUNT5_RX_BLSIZE_Pos                (15U)
6712 #define USB_COUNT5_RX_BLSIZE_Msk                (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
6713 #define USB_COUNT5_RX_BLSIZE                    USB_COUNT5_RX_BLSIZE_Msk       /*!< BLock SIZE */
6714 
6715 /*****************  Bit definition for USB_COUNT6_RX register  ****************/
6716 #define USB_COUNT6_RX_COUNT6_RX_Pos             (0U)
6717 #define USB_COUNT6_RX_COUNT6_RX_Msk             (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
6718 #define USB_COUNT6_RX_COUNT6_RX                 USB_COUNT6_RX_COUNT6_RX_Msk    /*!< Reception Byte Count */
6719 
6720 #define USB_COUNT6_RX_NUM_BLOCK_Pos             (10U)
6721 #define USB_COUNT6_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
6722 #define USB_COUNT6_RX_NUM_BLOCK                 USB_COUNT6_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
6723 #define USB_COUNT6_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
6724 #define USB_COUNT6_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
6725 #define USB_COUNT6_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
6726 #define USB_COUNT6_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
6727 #define USB_COUNT6_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
6728 
6729 #define USB_COUNT6_RX_BLSIZE_Pos                (15U)
6730 #define USB_COUNT6_RX_BLSIZE_Msk                (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
6731 #define USB_COUNT6_RX_BLSIZE                    USB_COUNT6_RX_BLSIZE_Msk       /*!< BLock SIZE */
6732 
6733 /*****************  Bit definition for USB_COUNT7_RX register  ****************/
6734 #define USB_COUNT7_RX_COUNT7_RX_Pos             (0U)
6735 #define USB_COUNT7_RX_COUNT7_RX_Msk             (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
6736 #define USB_COUNT7_RX_COUNT7_RX                 USB_COUNT7_RX_COUNT7_RX_Msk    /*!< Reception Byte Count */
6737 
6738 #define USB_COUNT7_RX_NUM_BLOCK_Pos             (10U)
6739 #define USB_COUNT7_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
6740 #define USB_COUNT7_RX_NUM_BLOCK                 USB_COUNT7_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
6741 #define USB_COUNT7_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
6742 #define USB_COUNT7_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
6743 #define USB_COUNT7_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
6744 #define USB_COUNT7_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
6745 #define USB_COUNT7_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
6746 
6747 #define USB_COUNT7_RX_BLSIZE_Pos                (15U)
6748 #define USB_COUNT7_RX_BLSIZE_Msk                (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
6749 #define USB_COUNT7_RX_BLSIZE                    USB_COUNT7_RX_BLSIZE_Msk       /*!< BLock SIZE */
6750 
6751 /*----------------------------------------------------------------------------*/
6752 
6753 /****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
6754 #define USB_COUNT0_RX_0_COUNT0_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */
6755 
6756 #define USB_COUNT0_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
6757 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */
6758 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */
6759 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */
6760 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */
6761 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */
6762 
6763 #define USB_COUNT0_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */
6764 
6765 /****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
6766 #define USB_COUNT0_RX_1_COUNT0_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */
6767 
6768 #define USB_COUNT0_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
6769 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 1 */
6770 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */
6771 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */
6772 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */
6773 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */
6774 
6775 #define USB_COUNT0_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */
6776 
6777 /****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
6778 #define USB_COUNT1_RX_0_COUNT1_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */
6779 
6780 #define USB_COUNT1_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
6781 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */
6782 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */
6783 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */
6784 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */
6785 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */
6786 
6787 #define USB_COUNT1_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */
6788 
6789 /****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
6790 #define USB_COUNT1_RX_1_COUNT1_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */
6791 
6792 #define USB_COUNT1_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
6793 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */
6794 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */
6795 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */
6796 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */
6797 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */
6798 
6799 #define USB_COUNT1_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */
6800 
6801 /****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
6802 #define USB_COUNT2_RX_0_COUNT2_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */
6803 
6804 #define USB_COUNT2_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
6805 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */
6806 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */
6807 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */
6808 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */
6809 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */
6810 
6811 #define USB_COUNT2_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */
6812 
6813 /****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
6814 #define USB_COUNT2_RX_1_COUNT2_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */
6815 
6816 #define USB_COUNT2_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
6817 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */
6818 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */
6819 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */
6820 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */
6821 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */
6822 
6823 #define USB_COUNT2_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */
6824 
6825 /****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
6826 #define USB_COUNT3_RX_0_COUNT3_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */
6827 
6828 #define USB_COUNT3_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
6829 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */
6830 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */
6831 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */
6832 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */
6833 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */
6834 
6835 #define USB_COUNT3_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */
6836 
6837 /****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
6838 #define USB_COUNT3_RX_1_COUNT3_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */
6839 
6840 #define USB_COUNT3_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
6841 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */
6842 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */
6843 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */
6844 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */
6845 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */
6846 
6847 #define USB_COUNT3_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */
6848 
6849 /****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
6850 #define USB_COUNT4_RX_0_COUNT4_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */
6851 
6852 #define USB_COUNT4_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
6853 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */
6854 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */
6855 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */
6856 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */
6857 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */
6858 
6859 #define USB_COUNT4_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */
6860 
6861 /****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
6862 #define USB_COUNT4_RX_1_COUNT4_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */
6863 
6864 #define USB_COUNT4_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
6865 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */
6866 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */
6867 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */
6868 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */
6869 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */
6870 
6871 #define USB_COUNT4_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */
6872 
6873 /****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
6874 #define USB_COUNT5_RX_0_COUNT5_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */
6875 
6876 #define USB_COUNT5_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
6877 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */
6878 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */
6879 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */
6880 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */
6881 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */
6882 
6883 #define USB_COUNT5_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */
6884 
6885 /****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
6886 #define USB_COUNT5_RX_1_COUNT5_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */
6887 
6888 #define USB_COUNT5_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
6889 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */
6890 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */
6891 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */
6892 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */
6893 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */
6894 
6895 #define USB_COUNT5_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */
6896 
6897 /***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
6898 #define USB_COUNT6_RX_0_COUNT6_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */
6899 
6900 #define USB_COUNT6_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
6901 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */
6902 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */
6903 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */
6904 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */
6905 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */
6906 
6907 #define USB_COUNT6_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */
6908 
6909 /****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
6910 #define USB_COUNT6_RX_1_COUNT6_RX_1             0x03FF0000U                   /*!< Reception Byte Count (high) */
6911 
6912 #define USB_COUNT6_RX_1_NUM_BLOCK_1             0x7C000000U                   /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
6913 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0           0x04000000U                   /*!< Bit 0 */
6914 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1           0x08000000U                   /*!< Bit 1 */
6915 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2           0x10000000U                   /*!< Bit 2 */
6916 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3           0x20000000U                   /*!< Bit 3 */
6917 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4           0x40000000U                   /*!< Bit 4 */
6918 
6919 #define USB_COUNT6_RX_1_BLSIZE_1                0x80000000U                   /*!< BLock SIZE (high) */
6920 
6921 /***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
6922 #define USB_COUNT7_RX_0_COUNT7_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */
6923 
6924 #define USB_COUNT7_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
6925 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */
6926 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */
6927 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */
6928 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */
6929 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */
6930 
6931 #define USB_COUNT7_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */
6932 
6933 /***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
6934 #define USB_COUNT7_RX_1_COUNT7_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */
6935 
6936 #define USB_COUNT7_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
6937 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */
6938 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */
6939 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */
6940 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */
6941 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */
6942 
6943 #define USB_COUNT7_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */
6944 
6945 /******************************************************************************/
6946 /*                                                                            */
6947 /*                         Controller Area Network                            */
6948 /*                                                                            */
6949 /******************************************************************************/
6950 
6951 /*!< CAN control and status registers */
6952 /*******************  Bit definition for CAN_MCR register  ********************/
6953 #define CAN_MCR_INRQ_Pos                     (0U)
6954 #define CAN_MCR_INRQ_Msk                     (0x1UL << CAN_MCR_INRQ_Pos)        /*!< 0x00000001 */
6955 #define CAN_MCR_INRQ                         CAN_MCR_INRQ_Msk                  /*!< Initialization Request */
6956 #define CAN_MCR_SLEEP_Pos                    (1U)
6957 #define CAN_MCR_SLEEP_Msk                    (0x1UL << CAN_MCR_SLEEP_Pos)       /*!< 0x00000002 */
6958 #define CAN_MCR_SLEEP                        CAN_MCR_SLEEP_Msk                 /*!< Sleep Mode Request */
6959 #define CAN_MCR_TXFP_Pos                     (2U)
6960 #define CAN_MCR_TXFP_Msk                     (0x1UL << CAN_MCR_TXFP_Pos)        /*!< 0x00000004 */
6961 #define CAN_MCR_TXFP                         CAN_MCR_TXFP_Msk                  /*!< Transmit FIFO Priority */
6962 #define CAN_MCR_RFLM_Pos                     (3U)
6963 #define CAN_MCR_RFLM_Msk                     (0x1UL << CAN_MCR_RFLM_Pos)        /*!< 0x00000008 */
6964 #define CAN_MCR_RFLM                         CAN_MCR_RFLM_Msk                  /*!< Receive FIFO Locked Mode */
6965 #define CAN_MCR_NART_Pos                     (4U)
6966 #define CAN_MCR_NART_Msk                     (0x1UL << CAN_MCR_NART_Pos)        /*!< 0x00000010 */
6967 #define CAN_MCR_NART                         CAN_MCR_NART_Msk                  /*!< No Automatic Retransmission */
6968 #define CAN_MCR_AWUM_Pos                     (5U)
6969 #define CAN_MCR_AWUM_Msk                     (0x1UL << CAN_MCR_AWUM_Pos)        /*!< 0x00000020 */
6970 #define CAN_MCR_AWUM                         CAN_MCR_AWUM_Msk                  /*!< Automatic Wakeup Mode */
6971 #define CAN_MCR_ABOM_Pos                     (6U)
6972 #define CAN_MCR_ABOM_Msk                     (0x1UL << CAN_MCR_ABOM_Pos)        /*!< 0x00000040 */
6973 #define CAN_MCR_ABOM                         CAN_MCR_ABOM_Msk                  /*!< Automatic Bus-Off Management */
6974 #define CAN_MCR_TTCM_Pos                     (7U)
6975 #define CAN_MCR_TTCM_Msk                     (0x1UL << CAN_MCR_TTCM_Pos)        /*!< 0x00000080 */
6976 #define CAN_MCR_TTCM                         CAN_MCR_TTCM_Msk                  /*!< Time Triggered Communication Mode */
6977 #define CAN_MCR_RESET_Pos                    (15U)
6978 #define CAN_MCR_RESET_Msk                    (0x1UL << CAN_MCR_RESET_Pos)       /*!< 0x00008000 */
6979 #define CAN_MCR_RESET                        CAN_MCR_RESET_Msk                 /*!< CAN software master reset */
6980 #define CAN_MCR_DBF_Pos                      (16U)
6981 #define CAN_MCR_DBF_Msk                      (0x1UL << CAN_MCR_DBF_Pos)         /*!< 0x00010000 */
6982 #define CAN_MCR_DBF                          CAN_MCR_DBF_Msk                   /*!< CAN Debug freeze */
6983 
6984 /*******************  Bit definition for CAN_MSR register  ********************/
6985 #define CAN_MSR_INAK_Pos                     (0U)
6986 #define CAN_MSR_INAK_Msk                     (0x1UL << CAN_MSR_INAK_Pos)        /*!< 0x00000001 */
6987 #define CAN_MSR_INAK                         CAN_MSR_INAK_Msk                  /*!< Initialization Acknowledge */
6988 #define CAN_MSR_SLAK_Pos                     (1U)
6989 #define CAN_MSR_SLAK_Msk                     (0x1UL << CAN_MSR_SLAK_Pos)        /*!< 0x00000002 */
6990 #define CAN_MSR_SLAK                         CAN_MSR_SLAK_Msk                  /*!< Sleep Acknowledge */
6991 #define CAN_MSR_ERRI_Pos                     (2U)
6992 #define CAN_MSR_ERRI_Msk                     (0x1UL << CAN_MSR_ERRI_Pos)        /*!< 0x00000004 */
6993 #define CAN_MSR_ERRI                         CAN_MSR_ERRI_Msk                  /*!< Error Interrupt */
6994 #define CAN_MSR_WKUI_Pos                     (3U)
6995 #define CAN_MSR_WKUI_Msk                     (0x1UL << CAN_MSR_WKUI_Pos)        /*!< 0x00000008 */
6996 #define CAN_MSR_WKUI                         CAN_MSR_WKUI_Msk                  /*!< Wakeup Interrupt */
6997 #define CAN_MSR_SLAKI_Pos                    (4U)
6998 #define CAN_MSR_SLAKI_Msk                    (0x1UL << CAN_MSR_SLAKI_Pos)       /*!< 0x00000010 */
6999 #define CAN_MSR_SLAKI                        CAN_MSR_SLAKI_Msk                 /*!< Sleep Acknowledge Interrupt */
7000 #define CAN_MSR_TXM_Pos                      (8U)
7001 #define CAN_MSR_TXM_Msk                      (0x1UL << CAN_MSR_TXM_Pos)         /*!< 0x00000100 */
7002 #define CAN_MSR_TXM                          CAN_MSR_TXM_Msk                   /*!< Transmit Mode */
7003 #define CAN_MSR_RXM_Pos                      (9U)
7004 #define CAN_MSR_RXM_Msk                      (0x1UL << CAN_MSR_RXM_Pos)         /*!< 0x00000200 */
7005 #define CAN_MSR_RXM                          CAN_MSR_RXM_Msk                   /*!< Receive Mode */
7006 #define CAN_MSR_SAMP_Pos                     (10U)
7007 #define CAN_MSR_SAMP_Msk                     (0x1UL << CAN_MSR_SAMP_Pos)        /*!< 0x00000400 */
7008 #define CAN_MSR_SAMP                         CAN_MSR_SAMP_Msk                  /*!< Last Sample Point */
7009 #define CAN_MSR_RX_Pos                       (11U)
7010 #define CAN_MSR_RX_Msk                       (0x1UL << CAN_MSR_RX_Pos)          /*!< 0x00000800 */
7011 #define CAN_MSR_RX                           CAN_MSR_RX_Msk                    /*!< CAN Rx Signal */
7012 
7013 /*******************  Bit definition for CAN_TSR register  ********************/
7014 #define CAN_TSR_RQCP0_Pos                    (0U)
7015 #define CAN_TSR_RQCP0_Msk                    (0x1UL << CAN_TSR_RQCP0_Pos)       /*!< 0x00000001 */
7016 #define CAN_TSR_RQCP0                        CAN_TSR_RQCP0_Msk                 /*!< Request Completed Mailbox0 */
7017 #define CAN_TSR_TXOK0_Pos                    (1U)
7018 #define CAN_TSR_TXOK0_Msk                    (0x1UL << CAN_TSR_TXOK0_Pos)       /*!< 0x00000002 */
7019 #define CAN_TSR_TXOK0                        CAN_TSR_TXOK0_Msk                 /*!< Transmission OK of Mailbox0 */
7020 #define CAN_TSR_ALST0_Pos                    (2U)
7021 #define CAN_TSR_ALST0_Msk                    (0x1UL << CAN_TSR_ALST0_Pos)       /*!< 0x00000004 */
7022 #define CAN_TSR_ALST0                        CAN_TSR_ALST0_Msk                 /*!< Arbitration Lost for Mailbox0 */
7023 #define CAN_TSR_TERR0_Pos                    (3U)
7024 #define CAN_TSR_TERR0_Msk                    (0x1UL << CAN_TSR_TERR0_Pos)       /*!< 0x00000008 */
7025 #define CAN_TSR_TERR0                        CAN_TSR_TERR0_Msk                 /*!< Transmission Error of Mailbox0 */
7026 #define CAN_TSR_ABRQ0_Pos                    (7U)
7027 #define CAN_TSR_ABRQ0_Msk                    (0x1UL << CAN_TSR_ABRQ0_Pos)       /*!< 0x00000080 */
7028 #define CAN_TSR_ABRQ0                        CAN_TSR_ABRQ0_Msk                 /*!< Abort Request for Mailbox0 */
7029 #define CAN_TSR_RQCP1_Pos                    (8U)
7030 #define CAN_TSR_RQCP1_Msk                    (0x1UL << CAN_TSR_RQCP1_Pos)       /*!< 0x00000100 */
7031 #define CAN_TSR_RQCP1                        CAN_TSR_RQCP1_Msk                 /*!< Request Completed Mailbox1 */
7032 #define CAN_TSR_TXOK1_Pos                    (9U)
7033 #define CAN_TSR_TXOK1_Msk                    (0x1UL << CAN_TSR_TXOK1_Pos)       /*!< 0x00000200 */
7034 #define CAN_TSR_TXOK1                        CAN_TSR_TXOK1_Msk                 /*!< Transmission OK of Mailbox1 */
7035 #define CAN_TSR_ALST1_Pos                    (10U)
7036 #define CAN_TSR_ALST1_Msk                    (0x1UL << CAN_TSR_ALST1_Pos)       /*!< 0x00000400 */
7037 #define CAN_TSR_ALST1                        CAN_TSR_ALST1_Msk                 /*!< Arbitration Lost for Mailbox1 */
7038 #define CAN_TSR_TERR1_Pos                    (11U)
7039 #define CAN_TSR_TERR1_Msk                    (0x1UL << CAN_TSR_TERR1_Pos)       /*!< 0x00000800 */
7040 #define CAN_TSR_TERR1                        CAN_TSR_TERR1_Msk                 /*!< Transmission Error of Mailbox1 */
7041 #define CAN_TSR_ABRQ1_Pos                    (15U)
7042 #define CAN_TSR_ABRQ1_Msk                    (0x1UL << CAN_TSR_ABRQ1_Pos)       /*!< 0x00008000 */
7043 #define CAN_TSR_ABRQ1                        CAN_TSR_ABRQ1_Msk                 /*!< Abort Request for Mailbox 1 */
7044 #define CAN_TSR_RQCP2_Pos                    (16U)
7045 #define CAN_TSR_RQCP2_Msk                    (0x1UL << CAN_TSR_RQCP2_Pos)       /*!< 0x00010000 */
7046 #define CAN_TSR_RQCP2                        CAN_TSR_RQCP2_Msk                 /*!< Request Completed Mailbox2 */
7047 #define CAN_TSR_TXOK2_Pos                    (17U)
7048 #define CAN_TSR_TXOK2_Msk                    (0x1UL << CAN_TSR_TXOK2_Pos)       /*!< 0x00020000 */
7049 #define CAN_TSR_TXOK2                        CAN_TSR_TXOK2_Msk                 /*!< Transmission OK of Mailbox 2 */
7050 #define CAN_TSR_ALST2_Pos                    (18U)
7051 #define CAN_TSR_ALST2_Msk                    (0x1UL << CAN_TSR_ALST2_Pos)       /*!< 0x00040000 */
7052 #define CAN_TSR_ALST2                        CAN_TSR_ALST2_Msk                 /*!< Arbitration Lost for mailbox 2 */
7053 #define CAN_TSR_TERR2_Pos                    (19U)
7054 #define CAN_TSR_TERR2_Msk                    (0x1UL << CAN_TSR_TERR2_Pos)       /*!< 0x00080000 */
7055 #define CAN_TSR_TERR2                        CAN_TSR_TERR2_Msk                 /*!< Transmission Error of Mailbox 2 */
7056 #define CAN_TSR_ABRQ2_Pos                    (23U)
7057 #define CAN_TSR_ABRQ2_Msk                    (0x1UL << CAN_TSR_ABRQ2_Pos)       /*!< 0x00800000 */
7058 #define CAN_TSR_ABRQ2                        CAN_TSR_ABRQ2_Msk                 /*!< Abort Request for Mailbox 2 */
7059 #define CAN_TSR_CODE_Pos                     (24U)
7060 #define CAN_TSR_CODE_Msk                     (0x3UL << CAN_TSR_CODE_Pos)        /*!< 0x03000000 */
7061 #define CAN_TSR_CODE                         CAN_TSR_CODE_Msk                  /*!< Mailbox Code */
7062 
7063 #define CAN_TSR_TME_Pos                      (26U)
7064 #define CAN_TSR_TME_Msk                      (0x7UL << CAN_TSR_TME_Pos)         /*!< 0x1C000000 */
7065 #define CAN_TSR_TME                          CAN_TSR_TME_Msk                   /*!< TME[2:0] bits */
7066 #define CAN_TSR_TME0_Pos                     (26U)
7067 #define CAN_TSR_TME0_Msk                     (0x1UL << CAN_TSR_TME0_Pos)        /*!< 0x04000000 */
7068 #define CAN_TSR_TME0                         CAN_TSR_TME0_Msk                  /*!< Transmit Mailbox 0 Empty */
7069 #define CAN_TSR_TME1_Pos                     (27U)
7070 #define CAN_TSR_TME1_Msk                     (0x1UL << CAN_TSR_TME1_Pos)        /*!< 0x08000000 */
7071 #define CAN_TSR_TME1                         CAN_TSR_TME1_Msk                  /*!< Transmit Mailbox 1 Empty */
7072 #define CAN_TSR_TME2_Pos                     (28U)
7073 #define CAN_TSR_TME2_Msk                     (0x1UL << CAN_TSR_TME2_Pos)        /*!< 0x10000000 */
7074 #define CAN_TSR_TME2                         CAN_TSR_TME2_Msk                  /*!< Transmit Mailbox 2 Empty */
7075 
7076 #define CAN_TSR_LOW_Pos                      (29U)
7077 #define CAN_TSR_LOW_Msk                      (0x7UL << CAN_TSR_LOW_Pos)         /*!< 0xE0000000 */
7078 #define CAN_TSR_LOW                          CAN_TSR_LOW_Msk                   /*!< LOW[2:0] bits */
7079 #define CAN_TSR_LOW0_Pos                     (29U)
7080 #define CAN_TSR_LOW0_Msk                     (0x1UL << CAN_TSR_LOW0_Pos)        /*!< 0x20000000 */
7081 #define CAN_TSR_LOW0                         CAN_TSR_LOW0_Msk                  /*!< Lowest Priority Flag for Mailbox 0 */
7082 #define CAN_TSR_LOW1_Pos                     (30U)
7083 #define CAN_TSR_LOW1_Msk                     (0x1UL << CAN_TSR_LOW1_Pos)        /*!< 0x40000000 */
7084 #define CAN_TSR_LOW1                         CAN_TSR_LOW1_Msk                  /*!< Lowest Priority Flag for Mailbox 1 */
7085 #define CAN_TSR_LOW2_Pos                     (31U)
7086 #define CAN_TSR_LOW2_Msk                     (0x1UL << CAN_TSR_LOW2_Pos)        /*!< 0x80000000 */
7087 #define CAN_TSR_LOW2                         CAN_TSR_LOW2_Msk                  /*!< Lowest Priority Flag for Mailbox 2 */
7088 
7089 /*******************  Bit definition for CAN_RF0R register  *******************/
7090 #define CAN_RF0R_FMP0_Pos                    (0U)
7091 #define CAN_RF0R_FMP0_Msk                    (0x3UL << CAN_RF0R_FMP0_Pos)       /*!< 0x00000003 */
7092 #define CAN_RF0R_FMP0                        CAN_RF0R_FMP0_Msk                 /*!< FIFO 0 Message Pending */
7093 #define CAN_RF0R_FULL0_Pos                   (3U)
7094 #define CAN_RF0R_FULL0_Msk                   (0x1UL << CAN_RF0R_FULL0_Pos)      /*!< 0x00000008 */
7095 #define CAN_RF0R_FULL0                       CAN_RF0R_FULL0_Msk                /*!< FIFO 0 Full */
7096 #define CAN_RF0R_FOVR0_Pos                   (4U)
7097 #define CAN_RF0R_FOVR0_Msk                   (0x1UL << CAN_RF0R_FOVR0_Pos)      /*!< 0x00000010 */
7098 #define CAN_RF0R_FOVR0                       CAN_RF0R_FOVR0_Msk                /*!< FIFO 0 Overrun */
7099 #define CAN_RF0R_RFOM0_Pos                   (5U)
7100 #define CAN_RF0R_RFOM0_Msk                   (0x1UL << CAN_RF0R_RFOM0_Pos)      /*!< 0x00000020 */
7101 #define CAN_RF0R_RFOM0                       CAN_RF0R_RFOM0_Msk                /*!< Release FIFO 0 Output Mailbox */
7102 
7103 /*******************  Bit definition for CAN_RF1R register  *******************/
7104 #define CAN_RF1R_FMP1_Pos                    (0U)
7105 #define CAN_RF1R_FMP1_Msk                    (0x3UL << CAN_RF1R_FMP1_Pos)       /*!< 0x00000003 */
7106 #define CAN_RF1R_FMP1                        CAN_RF1R_FMP1_Msk                 /*!< FIFO 1 Message Pending */
7107 #define CAN_RF1R_FULL1_Pos                   (3U)
7108 #define CAN_RF1R_FULL1_Msk                   (0x1UL << CAN_RF1R_FULL1_Pos)      /*!< 0x00000008 */
7109 #define CAN_RF1R_FULL1                       CAN_RF1R_FULL1_Msk                /*!< FIFO 1 Full */
7110 #define CAN_RF1R_FOVR1_Pos                   (4U)
7111 #define CAN_RF1R_FOVR1_Msk                   (0x1UL << CAN_RF1R_FOVR1_Pos)      /*!< 0x00000010 */
7112 #define CAN_RF1R_FOVR1                       CAN_RF1R_FOVR1_Msk                /*!< FIFO 1 Overrun */
7113 #define CAN_RF1R_RFOM1_Pos                   (5U)
7114 #define CAN_RF1R_RFOM1_Msk                   (0x1UL << CAN_RF1R_RFOM1_Pos)      /*!< 0x00000020 */
7115 #define CAN_RF1R_RFOM1                       CAN_RF1R_RFOM1_Msk                /*!< Release FIFO 1 Output Mailbox */
7116 
7117 /********************  Bit definition for CAN_IER register  *******************/
7118 #define CAN_IER_TMEIE_Pos                    (0U)
7119 #define CAN_IER_TMEIE_Msk                    (0x1UL << CAN_IER_TMEIE_Pos)       /*!< 0x00000001 */
7120 #define CAN_IER_TMEIE                        CAN_IER_TMEIE_Msk                 /*!< Transmit Mailbox Empty Interrupt Enable */
7121 #define CAN_IER_FMPIE0_Pos                   (1U)
7122 #define CAN_IER_FMPIE0_Msk                   (0x1UL << CAN_IER_FMPIE0_Pos)      /*!< 0x00000002 */
7123 #define CAN_IER_FMPIE0                       CAN_IER_FMPIE0_Msk                /*!< FIFO Message Pending Interrupt Enable */
7124 #define CAN_IER_FFIE0_Pos                    (2U)
7125 #define CAN_IER_FFIE0_Msk                    (0x1UL << CAN_IER_FFIE0_Pos)       /*!< 0x00000004 */
7126 #define CAN_IER_FFIE0                        CAN_IER_FFIE0_Msk                 /*!< FIFO Full Interrupt Enable */
7127 #define CAN_IER_FOVIE0_Pos                   (3U)
7128 #define CAN_IER_FOVIE0_Msk                   (0x1UL << CAN_IER_FOVIE0_Pos)      /*!< 0x00000008 */
7129 #define CAN_IER_FOVIE0                       CAN_IER_FOVIE0_Msk                /*!< FIFO Overrun Interrupt Enable */
7130 #define CAN_IER_FMPIE1_Pos                   (4U)
7131 #define CAN_IER_FMPIE1_Msk                   (0x1UL << CAN_IER_FMPIE1_Pos)      /*!< 0x00000010 */
7132 #define CAN_IER_FMPIE1                       CAN_IER_FMPIE1_Msk                /*!< FIFO Message Pending Interrupt Enable */
7133 #define CAN_IER_FFIE1_Pos                    (5U)
7134 #define CAN_IER_FFIE1_Msk                    (0x1UL << CAN_IER_FFIE1_Pos)       /*!< 0x00000020 */
7135 #define CAN_IER_FFIE1                        CAN_IER_FFIE1_Msk                 /*!< FIFO Full Interrupt Enable */
7136 #define CAN_IER_FOVIE1_Pos                   (6U)
7137 #define CAN_IER_FOVIE1_Msk                   (0x1UL << CAN_IER_FOVIE1_Pos)      /*!< 0x00000040 */
7138 #define CAN_IER_FOVIE1                       CAN_IER_FOVIE1_Msk                /*!< FIFO Overrun Interrupt Enable */
7139 #define CAN_IER_EWGIE_Pos                    (8U)
7140 #define CAN_IER_EWGIE_Msk                    (0x1UL << CAN_IER_EWGIE_Pos)       /*!< 0x00000100 */
7141 #define CAN_IER_EWGIE                        CAN_IER_EWGIE_Msk                 /*!< Error Warning Interrupt Enable */
7142 #define CAN_IER_EPVIE_Pos                    (9U)
7143 #define CAN_IER_EPVIE_Msk                    (0x1UL << CAN_IER_EPVIE_Pos)       /*!< 0x00000200 */
7144 #define CAN_IER_EPVIE                        CAN_IER_EPVIE_Msk                 /*!< Error Passive Interrupt Enable */
7145 #define CAN_IER_BOFIE_Pos                    (10U)
7146 #define CAN_IER_BOFIE_Msk                    (0x1UL << CAN_IER_BOFIE_Pos)       /*!< 0x00000400 */
7147 #define CAN_IER_BOFIE                        CAN_IER_BOFIE_Msk                 /*!< Bus-Off Interrupt Enable */
7148 #define CAN_IER_LECIE_Pos                    (11U)
7149 #define CAN_IER_LECIE_Msk                    (0x1UL << CAN_IER_LECIE_Pos)       /*!< 0x00000800 */
7150 #define CAN_IER_LECIE                        CAN_IER_LECIE_Msk                 /*!< Last Error Code Interrupt Enable */
7151 #define CAN_IER_ERRIE_Pos                    (15U)
7152 #define CAN_IER_ERRIE_Msk                    (0x1UL << CAN_IER_ERRIE_Pos)       /*!< 0x00008000 */
7153 #define CAN_IER_ERRIE                        CAN_IER_ERRIE_Msk                 /*!< Error Interrupt Enable */
7154 #define CAN_IER_WKUIE_Pos                    (16U)
7155 #define CAN_IER_WKUIE_Msk                    (0x1UL << CAN_IER_WKUIE_Pos)       /*!< 0x00010000 */
7156 #define CAN_IER_WKUIE                        CAN_IER_WKUIE_Msk                 /*!< Wakeup Interrupt Enable */
7157 #define CAN_IER_SLKIE_Pos                    (17U)
7158 #define CAN_IER_SLKIE_Msk                    (0x1UL << CAN_IER_SLKIE_Pos)       /*!< 0x00020000 */
7159 #define CAN_IER_SLKIE                        CAN_IER_SLKIE_Msk                 /*!< Sleep Interrupt Enable */
7160 
7161 /********************  Bit definition for CAN_ESR register  *******************/
7162 #define CAN_ESR_EWGF_Pos                     (0U)
7163 #define CAN_ESR_EWGF_Msk                     (0x1UL << CAN_ESR_EWGF_Pos)        /*!< 0x00000001 */
7164 #define CAN_ESR_EWGF                         CAN_ESR_EWGF_Msk                  /*!< Error Warning Flag */
7165 #define CAN_ESR_EPVF_Pos                     (1U)
7166 #define CAN_ESR_EPVF_Msk                     (0x1UL << CAN_ESR_EPVF_Pos)        /*!< 0x00000002 */
7167 #define CAN_ESR_EPVF                         CAN_ESR_EPVF_Msk                  /*!< Error Passive Flag */
7168 #define CAN_ESR_BOFF_Pos                     (2U)
7169 #define CAN_ESR_BOFF_Msk                     (0x1UL << CAN_ESR_BOFF_Pos)        /*!< 0x00000004 */
7170 #define CAN_ESR_BOFF                         CAN_ESR_BOFF_Msk                  /*!< Bus-Off Flag */
7171 
7172 #define CAN_ESR_LEC_Pos                      (4U)
7173 #define CAN_ESR_LEC_Msk                      (0x7UL << CAN_ESR_LEC_Pos)         /*!< 0x00000070 */
7174 #define CAN_ESR_LEC                          CAN_ESR_LEC_Msk                   /*!< LEC[2:0] bits (Last Error Code) */
7175 #define CAN_ESR_LEC_0                        (0x1UL << CAN_ESR_LEC_Pos)         /*!< 0x00000010 */
7176 #define CAN_ESR_LEC_1                        (0x2UL << CAN_ESR_LEC_Pos)         /*!< 0x00000020 */
7177 #define CAN_ESR_LEC_2                        (0x4UL << CAN_ESR_LEC_Pos)         /*!< 0x00000040 */
7178 
7179 #define CAN_ESR_TEC_Pos                      (16U)
7180 #define CAN_ESR_TEC_Msk                      (0xFFUL << CAN_ESR_TEC_Pos)        /*!< 0x00FF0000 */
7181 #define CAN_ESR_TEC                          CAN_ESR_TEC_Msk                   /*!< Least significant byte of the 9-bit Transmit Error Counter */
7182 #define CAN_ESR_REC_Pos                      (24U)
7183 #define CAN_ESR_REC_Msk                      (0xFFUL << CAN_ESR_REC_Pos)        /*!< 0xFF000000 */
7184 #define CAN_ESR_REC                          CAN_ESR_REC_Msk                   /*!< Receive Error Counter */
7185 
7186 /*******************  Bit definition for CAN_BTR register  ********************/
7187 #define CAN_BTR_BRP_Pos                      (0U)
7188 #define CAN_BTR_BRP_Msk                      (0x3FFUL << CAN_BTR_BRP_Pos)       /*!< 0x000003FF */
7189 #define CAN_BTR_BRP                          CAN_BTR_BRP_Msk                   /*!<Baud Rate Prescaler */
7190 #define CAN_BTR_TS1_Pos                      (16U)
7191 #define CAN_BTR_TS1_Msk                      (0xFUL << CAN_BTR_TS1_Pos)         /*!< 0x000F0000 */
7192 #define CAN_BTR_TS1                          CAN_BTR_TS1_Msk                   /*!<Time Segment 1 */
7193 #define CAN_BTR_TS1_0                        (0x1UL << CAN_BTR_TS1_Pos)         /*!< 0x00010000 */
7194 #define CAN_BTR_TS1_1                        (0x2UL << CAN_BTR_TS1_Pos)         /*!< 0x00020000 */
7195 #define CAN_BTR_TS1_2                        (0x4UL << CAN_BTR_TS1_Pos)         /*!< 0x00040000 */
7196 #define CAN_BTR_TS1_3                        (0x8UL << CAN_BTR_TS1_Pos)         /*!< 0x00080000 */
7197 #define CAN_BTR_TS2_Pos                      (20U)
7198 #define CAN_BTR_TS2_Msk                      (0x7UL << CAN_BTR_TS2_Pos)         /*!< 0x00700000 */
7199 #define CAN_BTR_TS2                          CAN_BTR_TS2_Msk                   /*!<Time Segment 2 */
7200 #define CAN_BTR_TS2_0                        (0x1UL << CAN_BTR_TS2_Pos)         /*!< 0x00100000 */
7201 #define CAN_BTR_TS2_1                        (0x2UL << CAN_BTR_TS2_Pos)         /*!< 0x00200000 */
7202 #define CAN_BTR_TS2_2                        (0x4UL << CAN_BTR_TS2_Pos)         /*!< 0x00400000 */
7203 #define CAN_BTR_SJW_Pos                      (24U)
7204 #define CAN_BTR_SJW_Msk                      (0x3UL << CAN_BTR_SJW_Pos)         /*!< 0x03000000 */
7205 #define CAN_BTR_SJW                          CAN_BTR_SJW_Msk                   /*!<Resynchronization Jump Width */
7206 #define CAN_BTR_SJW_0                        (0x1UL << CAN_BTR_SJW_Pos)         /*!< 0x01000000 */
7207 #define CAN_BTR_SJW_1                        (0x2UL << CAN_BTR_SJW_Pos)         /*!< 0x02000000 */
7208 #define CAN_BTR_LBKM_Pos                     (30U)
7209 #define CAN_BTR_LBKM_Msk                     (0x1UL << CAN_BTR_LBKM_Pos)        /*!< 0x40000000 */
7210 #define CAN_BTR_LBKM                         CAN_BTR_LBKM_Msk                  /*!<Loop Back Mode (Debug) */
7211 #define CAN_BTR_SILM_Pos                     (31U)
7212 #define CAN_BTR_SILM_Msk                     (0x1UL << CAN_BTR_SILM_Pos)        /*!< 0x80000000 */
7213 #define CAN_BTR_SILM                         CAN_BTR_SILM_Msk                  /*!<Silent Mode */
7214 
7215 /*!< Mailbox registers */
7216 /******************  Bit definition for CAN_TI0R register  ********************/
7217 #define CAN_TI0R_TXRQ_Pos                    (0U)
7218 #define CAN_TI0R_TXRQ_Msk                    (0x1UL << CAN_TI0R_TXRQ_Pos)       /*!< 0x00000001 */
7219 #define CAN_TI0R_TXRQ                        CAN_TI0R_TXRQ_Msk                 /*!< Transmit Mailbox Request */
7220 #define CAN_TI0R_RTR_Pos                     (1U)
7221 #define CAN_TI0R_RTR_Msk                     (0x1UL << CAN_TI0R_RTR_Pos)        /*!< 0x00000002 */
7222 #define CAN_TI0R_RTR                         CAN_TI0R_RTR_Msk                  /*!< Remote Transmission Request */
7223 #define CAN_TI0R_IDE_Pos                     (2U)
7224 #define CAN_TI0R_IDE_Msk                     (0x1UL << CAN_TI0R_IDE_Pos)        /*!< 0x00000004 */
7225 #define CAN_TI0R_IDE                         CAN_TI0R_IDE_Msk                  /*!< Identifier Extension */
7226 #define CAN_TI0R_EXID_Pos                    (3U)
7227 #define CAN_TI0R_EXID_Msk                    (0x3FFFFUL << CAN_TI0R_EXID_Pos)   /*!< 0x001FFFF8 */
7228 #define CAN_TI0R_EXID                        CAN_TI0R_EXID_Msk                 /*!< Extended Identifier */
7229 #define CAN_TI0R_STID_Pos                    (21U)
7230 #define CAN_TI0R_STID_Msk                    (0x7FFUL << CAN_TI0R_STID_Pos)     /*!< 0xFFE00000 */
7231 #define CAN_TI0R_STID                        CAN_TI0R_STID_Msk                 /*!< Standard Identifier or Extended Identifier */
7232 
7233 /******************  Bit definition for CAN_TDT0R register  *******************/
7234 #define CAN_TDT0R_DLC_Pos                    (0U)
7235 #define CAN_TDT0R_DLC_Msk                    (0xFUL << CAN_TDT0R_DLC_Pos)       /*!< 0x0000000F */
7236 #define CAN_TDT0R_DLC                        CAN_TDT0R_DLC_Msk                 /*!< Data Length Code */
7237 #define CAN_TDT0R_TGT_Pos                    (8U)
7238 #define CAN_TDT0R_TGT_Msk                    (0x1UL << CAN_TDT0R_TGT_Pos)       /*!< 0x00000100 */
7239 #define CAN_TDT0R_TGT                        CAN_TDT0R_TGT_Msk                 /*!< Transmit Global Time */
7240 #define CAN_TDT0R_TIME_Pos                   (16U)
7241 #define CAN_TDT0R_TIME_Msk                   (0xFFFFUL << CAN_TDT0R_TIME_Pos)   /*!< 0xFFFF0000 */
7242 #define CAN_TDT0R_TIME                       CAN_TDT0R_TIME_Msk                /*!< Message Time Stamp */
7243 
7244 /******************  Bit definition for CAN_TDL0R register  *******************/
7245 #define CAN_TDL0R_DATA0_Pos                  (0U)
7246 #define CAN_TDL0R_DATA0_Msk                  (0xFFUL << CAN_TDL0R_DATA0_Pos)    /*!< 0x000000FF */
7247 #define CAN_TDL0R_DATA0                      CAN_TDL0R_DATA0_Msk               /*!< Data byte 0 */
7248 #define CAN_TDL0R_DATA1_Pos                  (8U)
7249 #define CAN_TDL0R_DATA1_Msk                  (0xFFUL << CAN_TDL0R_DATA1_Pos)    /*!< 0x0000FF00 */
7250 #define CAN_TDL0R_DATA1                      CAN_TDL0R_DATA1_Msk               /*!< Data byte 1 */
7251 #define CAN_TDL0R_DATA2_Pos                  (16U)
7252 #define CAN_TDL0R_DATA2_Msk                  (0xFFUL << CAN_TDL0R_DATA2_Pos)    /*!< 0x00FF0000 */
7253 #define CAN_TDL0R_DATA2                      CAN_TDL0R_DATA2_Msk               /*!< Data byte 2 */
7254 #define CAN_TDL0R_DATA3_Pos                  (24U)
7255 #define CAN_TDL0R_DATA3_Msk                  (0xFFUL << CAN_TDL0R_DATA3_Pos)    /*!< 0xFF000000 */
7256 #define CAN_TDL0R_DATA3                      CAN_TDL0R_DATA3_Msk               /*!< Data byte 3 */
7257 
7258 /******************  Bit definition for CAN_TDH0R register  *******************/
7259 #define CAN_TDH0R_DATA4_Pos                  (0U)
7260 #define CAN_TDH0R_DATA4_Msk                  (0xFFUL << CAN_TDH0R_DATA4_Pos)    /*!< 0x000000FF */
7261 #define CAN_TDH0R_DATA4                      CAN_TDH0R_DATA4_Msk               /*!< Data byte 4 */
7262 #define CAN_TDH0R_DATA5_Pos                  (8U)
7263 #define CAN_TDH0R_DATA5_Msk                  (0xFFUL << CAN_TDH0R_DATA5_Pos)    /*!< 0x0000FF00 */
7264 #define CAN_TDH0R_DATA5                      CAN_TDH0R_DATA5_Msk               /*!< Data byte 5 */
7265 #define CAN_TDH0R_DATA6_Pos                  (16U)
7266 #define CAN_TDH0R_DATA6_Msk                  (0xFFUL << CAN_TDH0R_DATA6_Pos)    /*!< 0x00FF0000 */
7267 #define CAN_TDH0R_DATA6                      CAN_TDH0R_DATA6_Msk               /*!< Data byte 6 */
7268 #define CAN_TDH0R_DATA7_Pos                  (24U)
7269 #define CAN_TDH0R_DATA7_Msk                  (0xFFUL << CAN_TDH0R_DATA7_Pos)    /*!< 0xFF000000 */
7270 #define CAN_TDH0R_DATA7                      CAN_TDH0R_DATA7_Msk               /*!< Data byte 7 */
7271 
7272 /*******************  Bit definition for CAN_TI1R register  *******************/
7273 #define CAN_TI1R_TXRQ_Pos                    (0U)
7274 #define CAN_TI1R_TXRQ_Msk                    (0x1UL << CAN_TI1R_TXRQ_Pos)       /*!< 0x00000001 */
7275 #define CAN_TI1R_TXRQ                        CAN_TI1R_TXRQ_Msk                 /*!< Transmit Mailbox Request */
7276 #define CAN_TI1R_RTR_Pos                     (1U)
7277 #define CAN_TI1R_RTR_Msk                     (0x1UL << CAN_TI1R_RTR_Pos)        /*!< 0x00000002 */
7278 #define CAN_TI1R_RTR                         CAN_TI1R_RTR_Msk                  /*!< Remote Transmission Request */
7279 #define CAN_TI1R_IDE_Pos                     (2U)
7280 #define CAN_TI1R_IDE_Msk                     (0x1UL << CAN_TI1R_IDE_Pos)        /*!< 0x00000004 */
7281 #define CAN_TI1R_IDE                         CAN_TI1R_IDE_Msk                  /*!< Identifier Extension */
7282 #define CAN_TI1R_EXID_Pos                    (3U)
7283 #define CAN_TI1R_EXID_Msk                    (0x3FFFFUL << CAN_TI1R_EXID_Pos)   /*!< 0x001FFFF8 */
7284 #define CAN_TI1R_EXID                        CAN_TI1R_EXID_Msk                 /*!< Extended Identifier */
7285 #define CAN_TI1R_STID_Pos                    (21U)
7286 #define CAN_TI1R_STID_Msk                    (0x7FFUL << CAN_TI1R_STID_Pos)     /*!< 0xFFE00000 */
7287 #define CAN_TI1R_STID                        CAN_TI1R_STID_Msk                 /*!< Standard Identifier or Extended Identifier */
7288 
7289 /*******************  Bit definition for CAN_TDT1R register  ******************/
7290 #define CAN_TDT1R_DLC_Pos                    (0U)
7291 #define CAN_TDT1R_DLC_Msk                    (0xFUL << CAN_TDT1R_DLC_Pos)       /*!< 0x0000000F */
7292 #define CAN_TDT1R_DLC                        CAN_TDT1R_DLC_Msk                 /*!< Data Length Code */
7293 #define CAN_TDT1R_TGT_Pos                    (8U)
7294 #define CAN_TDT1R_TGT_Msk                    (0x1UL << CAN_TDT1R_TGT_Pos)       /*!< 0x00000100 */
7295 #define CAN_TDT1R_TGT                        CAN_TDT1R_TGT_Msk                 /*!< Transmit Global Time */
7296 #define CAN_TDT1R_TIME_Pos                   (16U)
7297 #define CAN_TDT1R_TIME_Msk                   (0xFFFFUL << CAN_TDT1R_TIME_Pos)   /*!< 0xFFFF0000 */
7298 #define CAN_TDT1R_TIME                       CAN_TDT1R_TIME_Msk                /*!< Message Time Stamp */
7299 
7300 /*******************  Bit definition for CAN_TDL1R register  ******************/
7301 #define CAN_TDL1R_DATA0_Pos                  (0U)
7302 #define CAN_TDL1R_DATA0_Msk                  (0xFFUL << CAN_TDL1R_DATA0_Pos)    /*!< 0x000000FF */
7303 #define CAN_TDL1R_DATA0                      CAN_TDL1R_DATA0_Msk               /*!< Data byte 0 */
7304 #define CAN_TDL1R_DATA1_Pos                  (8U)
7305 #define CAN_TDL1R_DATA1_Msk                  (0xFFUL << CAN_TDL1R_DATA1_Pos)    /*!< 0x0000FF00 */
7306 #define CAN_TDL1R_DATA1                      CAN_TDL1R_DATA1_Msk               /*!< Data byte 1 */
7307 #define CAN_TDL1R_DATA2_Pos                  (16U)
7308 #define CAN_TDL1R_DATA2_Msk                  (0xFFUL << CAN_TDL1R_DATA2_Pos)    /*!< 0x00FF0000 */
7309 #define CAN_TDL1R_DATA2                      CAN_TDL1R_DATA2_Msk               /*!< Data byte 2 */
7310 #define CAN_TDL1R_DATA3_Pos                  (24U)
7311 #define CAN_TDL1R_DATA3_Msk                  (0xFFUL << CAN_TDL1R_DATA3_Pos)    /*!< 0xFF000000 */
7312 #define CAN_TDL1R_DATA3                      CAN_TDL1R_DATA3_Msk               /*!< Data byte 3 */
7313 
7314 /*******************  Bit definition for CAN_TDH1R register  ******************/
7315 #define CAN_TDH1R_DATA4_Pos                  (0U)
7316 #define CAN_TDH1R_DATA4_Msk                  (0xFFUL << CAN_TDH1R_DATA4_Pos)    /*!< 0x000000FF */
7317 #define CAN_TDH1R_DATA4                      CAN_TDH1R_DATA4_Msk               /*!< Data byte 4 */
7318 #define CAN_TDH1R_DATA5_Pos                  (8U)
7319 #define CAN_TDH1R_DATA5_Msk                  (0xFFUL << CAN_TDH1R_DATA5_Pos)    /*!< 0x0000FF00 */
7320 #define CAN_TDH1R_DATA5                      CAN_TDH1R_DATA5_Msk               /*!< Data byte 5 */
7321 #define CAN_TDH1R_DATA6_Pos                  (16U)
7322 #define CAN_TDH1R_DATA6_Msk                  (0xFFUL << CAN_TDH1R_DATA6_Pos)    /*!< 0x00FF0000 */
7323 #define CAN_TDH1R_DATA6                      CAN_TDH1R_DATA6_Msk               /*!< Data byte 6 */
7324 #define CAN_TDH1R_DATA7_Pos                  (24U)
7325 #define CAN_TDH1R_DATA7_Msk                  (0xFFUL << CAN_TDH1R_DATA7_Pos)    /*!< 0xFF000000 */
7326 #define CAN_TDH1R_DATA7                      CAN_TDH1R_DATA7_Msk               /*!< Data byte 7 */
7327 
7328 /*******************  Bit definition for CAN_TI2R register  *******************/
7329 #define CAN_TI2R_TXRQ_Pos                    (0U)
7330 #define CAN_TI2R_TXRQ_Msk                    (0x1UL << CAN_TI2R_TXRQ_Pos)       /*!< 0x00000001 */
7331 #define CAN_TI2R_TXRQ                        CAN_TI2R_TXRQ_Msk                 /*!< Transmit Mailbox Request */
7332 #define CAN_TI2R_RTR_Pos                     (1U)
7333 #define CAN_TI2R_RTR_Msk                     (0x1UL << CAN_TI2R_RTR_Pos)        /*!< 0x00000002 */
7334 #define CAN_TI2R_RTR                         CAN_TI2R_RTR_Msk                  /*!< Remote Transmission Request */
7335 #define CAN_TI2R_IDE_Pos                     (2U)
7336 #define CAN_TI2R_IDE_Msk                     (0x1UL << CAN_TI2R_IDE_Pos)        /*!< 0x00000004 */
7337 #define CAN_TI2R_IDE                         CAN_TI2R_IDE_Msk                  /*!< Identifier Extension */
7338 #define CAN_TI2R_EXID_Pos                    (3U)
7339 #define CAN_TI2R_EXID_Msk                    (0x3FFFFUL << CAN_TI2R_EXID_Pos)   /*!< 0x001FFFF8 */
7340 #define CAN_TI2R_EXID                        CAN_TI2R_EXID_Msk                 /*!< Extended identifier */
7341 #define CAN_TI2R_STID_Pos                    (21U)
7342 #define CAN_TI2R_STID_Msk                    (0x7FFUL << CAN_TI2R_STID_Pos)     /*!< 0xFFE00000 */
7343 #define CAN_TI2R_STID                        CAN_TI2R_STID_Msk                 /*!< Standard Identifier or Extended Identifier */
7344 
7345 /*******************  Bit definition for CAN_TDT2R register  ******************/
7346 #define CAN_TDT2R_DLC_Pos                    (0U)
7347 #define CAN_TDT2R_DLC_Msk                    (0xFUL << CAN_TDT2R_DLC_Pos)       /*!< 0x0000000F */
7348 #define CAN_TDT2R_DLC                        CAN_TDT2R_DLC_Msk                 /*!< Data Length Code */
7349 #define CAN_TDT2R_TGT_Pos                    (8U)
7350 #define CAN_TDT2R_TGT_Msk                    (0x1UL << CAN_TDT2R_TGT_Pos)       /*!< 0x00000100 */
7351 #define CAN_TDT2R_TGT                        CAN_TDT2R_TGT_Msk                 /*!< Transmit Global Time */
7352 #define CAN_TDT2R_TIME_Pos                   (16U)
7353 #define CAN_TDT2R_TIME_Msk                   (0xFFFFUL << CAN_TDT2R_TIME_Pos)   /*!< 0xFFFF0000 */
7354 #define CAN_TDT2R_TIME                       CAN_TDT2R_TIME_Msk                /*!< Message Time Stamp */
7355 
7356 /*******************  Bit definition for CAN_TDL2R register  ******************/
7357 #define CAN_TDL2R_DATA0_Pos                  (0U)
7358 #define CAN_TDL2R_DATA0_Msk                  (0xFFUL << CAN_TDL2R_DATA0_Pos)    /*!< 0x000000FF */
7359 #define CAN_TDL2R_DATA0                      CAN_TDL2R_DATA0_Msk               /*!< Data byte 0 */
7360 #define CAN_TDL2R_DATA1_Pos                  (8U)
7361 #define CAN_TDL2R_DATA1_Msk                  (0xFFUL << CAN_TDL2R_DATA1_Pos)    /*!< 0x0000FF00 */
7362 #define CAN_TDL2R_DATA1                      CAN_TDL2R_DATA1_Msk               /*!< Data byte 1 */
7363 #define CAN_TDL2R_DATA2_Pos                  (16U)
7364 #define CAN_TDL2R_DATA2_Msk                  (0xFFUL << CAN_TDL2R_DATA2_Pos)    /*!< 0x00FF0000 */
7365 #define CAN_TDL2R_DATA2                      CAN_TDL2R_DATA2_Msk               /*!< Data byte 2 */
7366 #define CAN_TDL2R_DATA3_Pos                  (24U)
7367 #define CAN_TDL2R_DATA3_Msk                  (0xFFUL << CAN_TDL2R_DATA3_Pos)    /*!< 0xFF000000 */
7368 #define CAN_TDL2R_DATA3                      CAN_TDL2R_DATA3_Msk               /*!< Data byte 3 */
7369 
7370 /*******************  Bit definition for CAN_TDH2R register  ******************/
7371 #define CAN_TDH2R_DATA4_Pos                  (0U)
7372 #define CAN_TDH2R_DATA4_Msk                  (0xFFUL << CAN_TDH2R_DATA4_Pos)    /*!< 0x000000FF */
7373 #define CAN_TDH2R_DATA4                      CAN_TDH2R_DATA4_Msk               /*!< Data byte 4 */
7374 #define CAN_TDH2R_DATA5_Pos                  (8U)
7375 #define CAN_TDH2R_DATA5_Msk                  (0xFFUL << CAN_TDH2R_DATA5_Pos)    /*!< 0x0000FF00 */
7376 #define CAN_TDH2R_DATA5                      CAN_TDH2R_DATA5_Msk               /*!< Data byte 5 */
7377 #define CAN_TDH2R_DATA6_Pos                  (16U)
7378 #define CAN_TDH2R_DATA6_Msk                  (0xFFUL << CAN_TDH2R_DATA6_Pos)    /*!< 0x00FF0000 */
7379 #define CAN_TDH2R_DATA6                      CAN_TDH2R_DATA6_Msk               /*!< Data byte 6 */
7380 #define CAN_TDH2R_DATA7_Pos                  (24U)
7381 #define CAN_TDH2R_DATA7_Msk                  (0xFFUL << CAN_TDH2R_DATA7_Pos)    /*!< 0xFF000000 */
7382 #define CAN_TDH2R_DATA7                      CAN_TDH2R_DATA7_Msk               /*!< Data byte 7 */
7383 
7384 /*******************  Bit definition for CAN_RI0R register  *******************/
7385 #define CAN_RI0R_RTR_Pos                     (1U)
7386 #define CAN_RI0R_RTR_Msk                     (0x1UL << CAN_RI0R_RTR_Pos)        /*!< 0x00000002 */
7387 #define CAN_RI0R_RTR                         CAN_RI0R_RTR_Msk                  /*!< Remote Transmission Request */
7388 #define CAN_RI0R_IDE_Pos                     (2U)
7389 #define CAN_RI0R_IDE_Msk                     (0x1UL << CAN_RI0R_IDE_Pos)        /*!< 0x00000004 */
7390 #define CAN_RI0R_IDE                         CAN_RI0R_IDE_Msk                  /*!< Identifier Extension */
7391 #define CAN_RI0R_EXID_Pos                    (3U)
7392 #define CAN_RI0R_EXID_Msk                    (0x3FFFFUL << CAN_RI0R_EXID_Pos)   /*!< 0x001FFFF8 */
7393 #define CAN_RI0R_EXID                        CAN_RI0R_EXID_Msk                 /*!< Extended Identifier */
7394 #define CAN_RI0R_STID_Pos                    (21U)
7395 #define CAN_RI0R_STID_Msk                    (0x7FFUL << CAN_RI0R_STID_Pos)     /*!< 0xFFE00000 */
7396 #define CAN_RI0R_STID                        CAN_RI0R_STID_Msk                 /*!< Standard Identifier or Extended Identifier */
7397 
7398 /*******************  Bit definition for CAN_RDT0R register  ******************/
7399 #define CAN_RDT0R_DLC_Pos                    (0U)
7400 #define CAN_RDT0R_DLC_Msk                    (0xFUL << CAN_RDT0R_DLC_Pos)       /*!< 0x0000000F */
7401 #define CAN_RDT0R_DLC                        CAN_RDT0R_DLC_Msk                 /*!< Data Length Code */
7402 #define CAN_RDT0R_FMI_Pos                    (8U)
7403 #define CAN_RDT0R_FMI_Msk                    (0xFFUL << CAN_RDT0R_FMI_Pos)      /*!< 0x0000FF00 */
7404 #define CAN_RDT0R_FMI                        CAN_RDT0R_FMI_Msk                 /*!< Filter Match Index */
7405 #define CAN_RDT0R_TIME_Pos                   (16U)
7406 #define CAN_RDT0R_TIME_Msk                   (0xFFFFUL << CAN_RDT0R_TIME_Pos)   /*!< 0xFFFF0000 */
7407 #define CAN_RDT0R_TIME                       CAN_RDT0R_TIME_Msk                /*!< Message Time Stamp */
7408 
7409 /*******************  Bit definition for CAN_RDL0R register  ******************/
7410 #define CAN_RDL0R_DATA0_Pos                  (0U)
7411 #define CAN_RDL0R_DATA0_Msk                  (0xFFUL << CAN_RDL0R_DATA0_Pos)    /*!< 0x000000FF */
7412 #define CAN_RDL0R_DATA0                      CAN_RDL0R_DATA0_Msk               /*!< Data byte 0 */
7413 #define CAN_RDL0R_DATA1_Pos                  (8U)
7414 #define CAN_RDL0R_DATA1_Msk                  (0xFFUL << CAN_RDL0R_DATA1_Pos)    /*!< 0x0000FF00 */
7415 #define CAN_RDL0R_DATA1                      CAN_RDL0R_DATA1_Msk               /*!< Data byte 1 */
7416 #define CAN_RDL0R_DATA2_Pos                  (16U)
7417 #define CAN_RDL0R_DATA2_Msk                  (0xFFUL << CAN_RDL0R_DATA2_Pos)    /*!< 0x00FF0000 */
7418 #define CAN_RDL0R_DATA2                      CAN_RDL0R_DATA2_Msk               /*!< Data byte 2 */
7419 #define CAN_RDL0R_DATA3_Pos                  (24U)
7420 #define CAN_RDL0R_DATA3_Msk                  (0xFFUL << CAN_RDL0R_DATA3_Pos)    /*!< 0xFF000000 */
7421 #define CAN_RDL0R_DATA3                      CAN_RDL0R_DATA3_Msk               /*!< Data byte 3 */
7422 
7423 /*******************  Bit definition for CAN_RDH0R register  ******************/
7424 #define CAN_RDH0R_DATA4_Pos                  (0U)
7425 #define CAN_RDH0R_DATA4_Msk                  (0xFFUL << CAN_RDH0R_DATA4_Pos)    /*!< 0x000000FF */
7426 #define CAN_RDH0R_DATA4                      CAN_RDH0R_DATA4_Msk               /*!< Data byte 4 */
7427 #define CAN_RDH0R_DATA5_Pos                  (8U)
7428 #define CAN_RDH0R_DATA5_Msk                  (0xFFUL << CAN_RDH0R_DATA5_Pos)    /*!< 0x0000FF00 */
7429 #define CAN_RDH0R_DATA5                      CAN_RDH0R_DATA5_Msk               /*!< Data byte 5 */
7430 #define CAN_RDH0R_DATA6_Pos                  (16U)
7431 #define CAN_RDH0R_DATA6_Msk                  (0xFFUL << CAN_RDH0R_DATA6_Pos)    /*!< 0x00FF0000 */
7432 #define CAN_RDH0R_DATA6                      CAN_RDH0R_DATA6_Msk               /*!< Data byte 6 */
7433 #define CAN_RDH0R_DATA7_Pos                  (24U)
7434 #define CAN_RDH0R_DATA7_Msk                  (0xFFUL << CAN_RDH0R_DATA7_Pos)    /*!< 0xFF000000 */
7435 #define CAN_RDH0R_DATA7                      CAN_RDH0R_DATA7_Msk               /*!< Data byte 7 */
7436 
7437 /*******************  Bit definition for CAN_RI1R register  *******************/
7438 #define CAN_RI1R_RTR_Pos                     (1U)
7439 #define CAN_RI1R_RTR_Msk                     (0x1UL << CAN_RI1R_RTR_Pos)        /*!< 0x00000002 */
7440 #define CAN_RI1R_RTR                         CAN_RI1R_RTR_Msk                  /*!< Remote Transmission Request */
7441 #define CAN_RI1R_IDE_Pos                     (2U)
7442 #define CAN_RI1R_IDE_Msk                     (0x1UL << CAN_RI1R_IDE_Pos)        /*!< 0x00000004 */
7443 #define CAN_RI1R_IDE                         CAN_RI1R_IDE_Msk                  /*!< Identifier Extension */
7444 #define CAN_RI1R_EXID_Pos                    (3U)
7445 #define CAN_RI1R_EXID_Msk                    (0x3FFFFUL << CAN_RI1R_EXID_Pos)   /*!< 0x001FFFF8 */
7446 #define CAN_RI1R_EXID                        CAN_RI1R_EXID_Msk                 /*!< Extended identifier */
7447 #define CAN_RI1R_STID_Pos                    (21U)
7448 #define CAN_RI1R_STID_Msk                    (0x7FFUL << CAN_RI1R_STID_Pos)     /*!< 0xFFE00000 */
7449 #define CAN_RI1R_STID                        CAN_RI1R_STID_Msk                 /*!< Standard Identifier or Extended Identifier */
7450 
7451 /*******************  Bit definition for CAN_RDT1R register  ******************/
7452 #define CAN_RDT1R_DLC_Pos                    (0U)
7453 #define CAN_RDT1R_DLC_Msk                    (0xFUL << CAN_RDT1R_DLC_Pos)       /*!< 0x0000000F */
7454 #define CAN_RDT1R_DLC                        CAN_RDT1R_DLC_Msk                 /*!< Data Length Code */
7455 #define CAN_RDT1R_FMI_Pos                    (8U)
7456 #define CAN_RDT1R_FMI_Msk                    (0xFFUL << CAN_RDT1R_FMI_Pos)      /*!< 0x0000FF00 */
7457 #define CAN_RDT1R_FMI                        CAN_RDT1R_FMI_Msk                 /*!< Filter Match Index */
7458 #define CAN_RDT1R_TIME_Pos                   (16U)
7459 #define CAN_RDT1R_TIME_Msk                   (0xFFFFUL << CAN_RDT1R_TIME_Pos)   /*!< 0xFFFF0000 */
7460 #define CAN_RDT1R_TIME                       CAN_RDT1R_TIME_Msk                /*!< Message Time Stamp */
7461 
7462 /*******************  Bit definition for CAN_RDL1R register  ******************/
7463 #define CAN_RDL1R_DATA0_Pos                  (0U)
7464 #define CAN_RDL1R_DATA0_Msk                  (0xFFUL << CAN_RDL1R_DATA0_Pos)    /*!< 0x000000FF */
7465 #define CAN_RDL1R_DATA0                      CAN_RDL1R_DATA0_Msk               /*!< Data byte 0 */
7466 #define CAN_RDL1R_DATA1_Pos                  (8U)
7467 #define CAN_RDL1R_DATA1_Msk                  (0xFFUL << CAN_RDL1R_DATA1_Pos)    /*!< 0x0000FF00 */
7468 #define CAN_RDL1R_DATA1                      CAN_RDL1R_DATA1_Msk               /*!< Data byte 1 */
7469 #define CAN_RDL1R_DATA2_Pos                  (16U)
7470 #define CAN_RDL1R_DATA2_Msk                  (0xFFUL << CAN_RDL1R_DATA2_Pos)    /*!< 0x00FF0000 */
7471 #define CAN_RDL1R_DATA2                      CAN_RDL1R_DATA2_Msk               /*!< Data byte 2 */
7472 #define CAN_RDL1R_DATA3_Pos                  (24U)
7473 #define CAN_RDL1R_DATA3_Msk                  (0xFFUL << CAN_RDL1R_DATA3_Pos)    /*!< 0xFF000000 */
7474 #define CAN_RDL1R_DATA3                      CAN_RDL1R_DATA3_Msk               /*!< Data byte 3 */
7475 
7476 /*******************  Bit definition for CAN_RDH1R register  ******************/
7477 #define CAN_RDH1R_DATA4_Pos                  (0U)
7478 #define CAN_RDH1R_DATA4_Msk                  (0xFFUL << CAN_RDH1R_DATA4_Pos)    /*!< 0x000000FF */
7479 #define CAN_RDH1R_DATA4                      CAN_RDH1R_DATA4_Msk               /*!< Data byte 4 */
7480 #define CAN_RDH1R_DATA5_Pos                  (8U)
7481 #define CAN_RDH1R_DATA5_Msk                  (0xFFUL << CAN_RDH1R_DATA5_Pos)    /*!< 0x0000FF00 */
7482 #define CAN_RDH1R_DATA5                      CAN_RDH1R_DATA5_Msk               /*!< Data byte 5 */
7483 #define CAN_RDH1R_DATA6_Pos                  (16U)
7484 #define CAN_RDH1R_DATA6_Msk                  (0xFFUL << CAN_RDH1R_DATA6_Pos)    /*!< 0x00FF0000 */
7485 #define CAN_RDH1R_DATA6                      CAN_RDH1R_DATA6_Msk               /*!< Data byte 6 */
7486 #define CAN_RDH1R_DATA7_Pos                  (24U)
7487 #define CAN_RDH1R_DATA7_Msk                  (0xFFUL << CAN_RDH1R_DATA7_Pos)    /*!< 0xFF000000 */
7488 #define CAN_RDH1R_DATA7                      CAN_RDH1R_DATA7_Msk               /*!< Data byte 7 */
7489 
7490 /*!< CAN filter registers */
7491 /*******************  Bit definition for CAN_FMR register  ********************/
7492 #define CAN_FMR_FINIT_Pos                    (0U)
7493 #define CAN_FMR_FINIT_Msk                    (0x1UL << CAN_FMR_FINIT_Pos)       /*!< 0x00000001 */
7494 #define CAN_FMR_FINIT                        CAN_FMR_FINIT_Msk                 /*!< Filter Init Mode */
7495 #define CAN_FMR_CAN2SB_Pos                   (8U)
7496 #define CAN_FMR_CAN2SB_Msk                   (0x3FUL << CAN_FMR_CAN2SB_Pos)     /*!< 0x00003F00 */
7497 #define CAN_FMR_CAN2SB                       CAN_FMR_CAN2SB_Msk                /*!< CAN2 start bank */
7498 
7499 /*******************  Bit definition for CAN_FM1R register  *******************/
7500 #define CAN_FM1R_FBM_Pos                     (0U)
7501 #define CAN_FM1R_FBM_Msk                     (0x3FFFUL << CAN_FM1R_FBM_Pos)     /*!< 0x00003FFF */
7502 #define CAN_FM1R_FBM                         CAN_FM1R_FBM_Msk                  /*!< Filter Mode */
7503 #define CAN_FM1R_FBM0_Pos                    (0U)
7504 #define CAN_FM1R_FBM0_Msk                    (0x1UL << CAN_FM1R_FBM0_Pos)       /*!< 0x00000001 */
7505 #define CAN_FM1R_FBM0                        CAN_FM1R_FBM0_Msk                 /*!< Filter Init Mode for filter 0 */
7506 #define CAN_FM1R_FBM1_Pos                    (1U)
7507 #define CAN_FM1R_FBM1_Msk                    (0x1UL << CAN_FM1R_FBM1_Pos)       /*!< 0x00000002 */
7508 #define CAN_FM1R_FBM1                        CAN_FM1R_FBM1_Msk                 /*!< Filter Init Mode for filter 1 */
7509 #define CAN_FM1R_FBM2_Pos                    (2U)
7510 #define CAN_FM1R_FBM2_Msk                    (0x1UL << CAN_FM1R_FBM2_Pos)       /*!< 0x00000004 */
7511 #define CAN_FM1R_FBM2                        CAN_FM1R_FBM2_Msk                 /*!< Filter Init Mode for filter 2 */
7512 #define CAN_FM1R_FBM3_Pos                    (3U)
7513 #define CAN_FM1R_FBM3_Msk                    (0x1UL << CAN_FM1R_FBM3_Pos)       /*!< 0x00000008 */
7514 #define CAN_FM1R_FBM3                        CAN_FM1R_FBM3_Msk                 /*!< Filter Init Mode for filter 3 */
7515 #define CAN_FM1R_FBM4_Pos                    (4U)
7516 #define CAN_FM1R_FBM4_Msk                    (0x1UL << CAN_FM1R_FBM4_Pos)       /*!< 0x00000010 */
7517 #define CAN_FM1R_FBM4                        CAN_FM1R_FBM4_Msk                 /*!< Filter Init Mode for filter 4 */
7518 #define CAN_FM1R_FBM5_Pos                    (5U)
7519 #define CAN_FM1R_FBM5_Msk                    (0x1UL << CAN_FM1R_FBM5_Pos)       /*!< 0x00000020 */
7520 #define CAN_FM1R_FBM5                        CAN_FM1R_FBM5_Msk                 /*!< Filter Init Mode for filter 5 */
7521 #define CAN_FM1R_FBM6_Pos                    (6U)
7522 #define CAN_FM1R_FBM6_Msk                    (0x1UL << CAN_FM1R_FBM6_Pos)       /*!< 0x00000040 */
7523 #define CAN_FM1R_FBM6                        CAN_FM1R_FBM6_Msk                 /*!< Filter Init Mode for filter 6 */
7524 #define CAN_FM1R_FBM7_Pos                    (7U)
7525 #define CAN_FM1R_FBM7_Msk                    (0x1UL << CAN_FM1R_FBM7_Pos)       /*!< 0x00000080 */
7526 #define CAN_FM1R_FBM7                        CAN_FM1R_FBM7_Msk                 /*!< Filter Init Mode for filter 7 */
7527 #define CAN_FM1R_FBM8_Pos                    (8U)
7528 #define CAN_FM1R_FBM8_Msk                    (0x1UL << CAN_FM1R_FBM8_Pos)       /*!< 0x00000100 */
7529 #define CAN_FM1R_FBM8                        CAN_FM1R_FBM8_Msk                 /*!< Filter Init Mode for filter 8 */
7530 #define CAN_FM1R_FBM9_Pos                    (9U)
7531 #define CAN_FM1R_FBM9_Msk                    (0x1UL << CAN_FM1R_FBM9_Pos)       /*!< 0x00000200 */
7532 #define CAN_FM1R_FBM9                        CAN_FM1R_FBM9_Msk                 /*!< Filter Init Mode for filter 9 */
7533 #define CAN_FM1R_FBM10_Pos                   (10U)
7534 #define CAN_FM1R_FBM10_Msk                   (0x1UL << CAN_FM1R_FBM10_Pos)      /*!< 0x00000400 */
7535 #define CAN_FM1R_FBM10                       CAN_FM1R_FBM10_Msk                /*!< Filter Init Mode for filter 10 */
7536 #define CAN_FM1R_FBM11_Pos                   (11U)
7537 #define CAN_FM1R_FBM11_Msk                   (0x1UL << CAN_FM1R_FBM11_Pos)      /*!< 0x00000800 */
7538 #define CAN_FM1R_FBM11                       CAN_FM1R_FBM11_Msk                /*!< Filter Init Mode for filter 11 */
7539 #define CAN_FM1R_FBM12_Pos                   (12U)
7540 #define CAN_FM1R_FBM12_Msk                   (0x1UL << CAN_FM1R_FBM12_Pos)      /*!< 0x00001000 */
7541 #define CAN_FM1R_FBM12                       CAN_FM1R_FBM12_Msk                /*!< Filter Init Mode for filter 12 */
7542 #define CAN_FM1R_FBM13_Pos                   (13U)
7543 #define CAN_FM1R_FBM13_Msk                   (0x1UL << CAN_FM1R_FBM13_Pos)      /*!< 0x00002000 */
7544 #define CAN_FM1R_FBM13                       CAN_FM1R_FBM13_Msk                /*!< Filter Init Mode for filter 13 */
7545 
7546 /*******************  Bit definition for CAN_FS1R register  *******************/
7547 #define CAN_FS1R_FSC_Pos                     (0U)
7548 #define CAN_FS1R_FSC_Msk                     (0x3FFFUL << CAN_FS1R_FSC_Pos)     /*!< 0x00003FFF */
7549 #define CAN_FS1R_FSC                         CAN_FS1R_FSC_Msk                  /*!< Filter Scale Configuration */
7550 #define CAN_FS1R_FSC0_Pos                    (0U)
7551 #define CAN_FS1R_FSC0_Msk                    (0x1UL << CAN_FS1R_FSC0_Pos)       /*!< 0x00000001 */
7552 #define CAN_FS1R_FSC0                        CAN_FS1R_FSC0_Msk                 /*!< Filter Scale Configuration for filter 0 */
7553 #define CAN_FS1R_FSC1_Pos                    (1U)
7554 #define CAN_FS1R_FSC1_Msk                    (0x1UL << CAN_FS1R_FSC1_Pos)       /*!< 0x00000002 */
7555 #define CAN_FS1R_FSC1                        CAN_FS1R_FSC1_Msk                 /*!< Filter Scale Configuration for filter 1 */
7556 #define CAN_FS1R_FSC2_Pos                    (2U)
7557 #define CAN_FS1R_FSC2_Msk                    (0x1UL << CAN_FS1R_FSC2_Pos)       /*!< 0x00000004 */
7558 #define CAN_FS1R_FSC2                        CAN_FS1R_FSC2_Msk                 /*!< Filter Scale Configuration for filter 2 */
7559 #define CAN_FS1R_FSC3_Pos                    (3U)
7560 #define CAN_FS1R_FSC3_Msk                    (0x1UL << CAN_FS1R_FSC3_Pos)       /*!< 0x00000008 */
7561 #define CAN_FS1R_FSC3                        CAN_FS1R_FSC3_Msk                 /*!< Filter Scale Configuration for filter 3 */
7562 #define CAN_FS1R_FSC4_Pos                    (4U)
7563 #define CAN_FS1R_FSC4_Msk                    (0x1UL << CAN_FS1R_FSC4_Pos)       /*!< 0x00000010 */
7564 #define CAN_FS1R_FSC4                        CAN_FS1R_FSC4_Msk                 /*!< Filter Scale Configuration for filter 4 */
7565 #define CAN_FS1R_FSC5_Pos                    (5U)
7566 #define CAN_FS1R_FSC5_Msk                    (0x1UL << CAN_FS1R_FSC5_Pos)       /*!< 0x00000020 */
7567 #define CAN_FS1R_FSC5                        CAN_FS1R_FSC5_Msk                 /*!< Filter Scale Configuration for filter 5 */
7568 #define CAN_FS1R_FSC6_Pos                    (6U)
7569 #define CAN_FS1R_FSC6_Msk                    (0x1UL << CAN_FS1R_FSC6_Pos)       /*!< 0x00000040 */
7570 #define CAN_FS1R_FSC6                        CAN_FS1R_FSC6_Msk                 /*!< Filter Scale Configuration for filter 6 */
7571 #define CAN_FS1R_FSC7_Pos                    (7U)
7572 #define CAN_FS1R_FSC7_Msk                    (0x1UL << CAN_FS1R_FSC7_Pos)       /*!< 0x00000080 */
7573 #define CAN_FS1R_FSC7                        CAN_FS1R_FSC7_Msk                 /*!< Filter Scale Configuration for filter 7 */
7574 #define CAN_FS1R_FSC8_Pos                    (8U)
7575 #define CAN_FS1R_FSC8_Msk                    (0x1UL << CAN_FS1R_FSC8_Pos)       /*!< 0x00000100 */
7576 #define CAN_FS1R_FSC8                        CAN_FS1R_FSC8_Msk                 /*!< Filter Scale Configuration for filter 8 */
7577 #define CAN_FS1R_FSC9_Pos                    (9U)
7578 #define CAN_FS1R_FSC9_Msk                    (0x1UL << CAN_FS1R_FSC9_Pos)       /*!< 0x00000200 */
7579 #define CAN_FS1R_FSC9                        CAN_FS1R_FSC9_Msk                 /*!< Filter Scale Configuration for filter 9 */
7580 #define CAN_FS1R_FSC10_Pos                   (10U)
7581 #define CAN_FS1R_FSC10_Msk                   (0x1UL << CAN_FS1R_FSC10_Pos)      /*!< 0x00000400 */
7582 #define CAN_FS1R_FSC10                       CAN_FS1R_FSC10_Msk                /*!< Filter Scale Configuration for filter 10 */
7583 #define CAN_FS1R_FSC11_Pos                   (11U)
7584 #define CAN_FS1R_FSC11_Msk                   (0x1UL << CAN_FS1R_FSC11_Pos)      /*!< 0x00000800 */
7585 #define CAN_FS1R_FSC11                       CAN_FS1R_FSC11_Msk                /*!< Filter Scale Configuration for filter 11 */
7586 #define CAN_FS1R_FSC12_Pos                   (12U)
7587 #define CAN_FS1R_FSC12_Msk                   (0x1UL << CAN_FS1R_FSC12_Pos)      /*!< 0x00001000 */
7588 #define CAN_FS1R_FSC12                       CAN_FS1R_FSC12_Msk                /*!< Filter Scale Configuration for filter 12 */
7589 #define CAN_FS1R_FSC13_Pos                   (13U)
7590 #define CAN_FS1R_FSC13_Msk                   (0x1UL << CAN_FS1R_FSC13_Pos)      /*!< 0x00002000 */
7591 #define CAN_FS1R_FSC13                       CAN_FS1R_FSC13_Msk                /*!< Filter Scale Configuration for filter 13 */
7592 
7593 /******************  Bit definition for CAN_FFA1R register  *******************/
7594 #define CAN_FFA1R_FFA_Pos                    (0U)
7595 #define CAN_FFA1R_FFA_Msk                    (0x3FFFUL << CAN_FFA1R_FFA_Pos)    /*!< 0x00003FFF */
7596 #define CAN_FFA1R_FFA                        CAN_FFA1R_FFA_Msk                 /*!< Filter FIFO Assignment */
7597 #define CAN_FFA1R_FFA0_Pos                   (0U)
7598 #define CAN_FFA1R_FFA0_Msk                   (0x1UL << CAN_FFA1R_FFA0_Pos)      /*!< 0x00000001 */
7599 #define CAN_FFA1R_FFA0                       CAN_FFA1R_FFA0_Msk                /*!< Filter FIFO Assignment for filter 0 */
7600 #define CAN_FFA1R_FFA1_Pos                   (1U)
7601 #define CAN_FFA1R_FFA1_Msk                   (0x1UL << CAN_FFA1R_FFA1_Pos)      /*!< 0x00000002 */
7602 #define CAN_FFA1R_FFA1                       CAN_FFA1R_FFA1_Msk                /*!< Filter FIFO Assignment for filter 1 */
7603 #define CAN_FFA1R_FFA2_Pos                   (2U)
7604 #define CAN_FFA1R_FFA2_Msk                   (0x1UL << CAN_FFA1R_FFA2_Pos)      /*!< 0x00000004 */
7605 #define CAN_FFA1R_FFA2                       CAN_FFA1R_FFA2_Msk                /*!< Filter FIFO Assignment for filter 2 */
7606 #define CAN_FFA1R_FFA3_Pos                   (3U)
7607 #define CAN_FFA1R_FFA3_Msk                   (0x1UL << CAN_FFA1R_FFA3_Pos)      /*!< 0x00000008 */
7608 #define CAN_FFA1R_FFA3                       CAN_FFA1R_FFA3_Msk                /*!< Filter FIFO Assignment for filter 3 */
7609 #define CAN_FFA1R_FFA4_Pos                   (4U)
7610 #define CAN_FFA1R_FFA4_Msk                   (0x1UL << CAN_FFA1R_FFA4_Pos)      /*!< 0x00000010 */
7611 #define CAN_FFA1R_FFA4                       CAN_FFA1R_FFA4_Msk                /*!< Filter FIFO Assignment for filter 4 */
7612 #define CAN_FFA1R_FFA5_Pos                   (5U)
7613 #define CAN_FFA1R_FFA5_Msk                   (0x1UL << CAN_FFA1R_FFA5_Pos)      /*!< 0x00000020 */
7614 #define CAN_FFA1R_FFA5                       CAN_FFA1R_FFA5_Msk                /*!< Filter FIFO Assignment for filter 5 */
7615 #define CAN_FFA1R_FFA6_Pos                   (6U)
7616 #define CAN_FFA1R_FFA6_Msk                   (0x1UL << CAN_FFA1R_FFA6_Pos)      /*!< 0x00000040 */
7617 #define CAN_FFA1R_FFA6                       CAN_FFA1R_FFA6_Msk                /*!< Filter FIFO Assignment for filter 6 */
7618 #define CAN_FFA1R_FFA7_Pos                   (7U)
7619 #define CAN_FFA1R_FFA7_Msk                   (0x1UL << CAN_FFA1R_FFA7_Pos)      /*!< 0x00000080 */
7620 #define CAN_FFA1R_FFA7                       CAN_FFA1R_FFA7_Msk                /*!< Filter FIFO Assignment for filter 7 */
7621 #define CAN_FFA1R_FFA8_Pos                   (8U)
7622 #define CAN_FFA1R_FFA8_Msk                   (0x1UL << CAN_FFA1R_FFA8_Pos)      /*!< 0x00000100 */
7623 #define CAN_FFA1R_FFA8                       CAN_FFA1R_FFA8_Msk                /*!< Filter FIFO Assignment for filter 8 */
7624 #define CAN_FFA1R_FFA9_Pos                   (9U)
7625 #define CAN_FFA1R_FFA9_Msk                   (0x1UL << CAN_FFA1R_FFA9_Pos)      /*!< 0x00000200 */
7626 #define CAN_FFA1R_FFA9                       CAN_FFA1R_FFA9_Msk                /*!< Filter FIFO Assignment for filter 9 */
7627 #define CAN_FFA1R_FFA10_Pos                  (10U)
7628 #define CAN_FFA1R_FFA10_Msk                  (0x1UL << CAN_FFA1R_FFA10_Pos)     /*!< 0x00000400 */
7629 #define CAN_FFA1R_FFA10                      CAN_FFA1R_FFA10_Msk               /*!< Filter FIFO Assignment for filter 10 */
7630 #define CAN_FFA1R_FFA11_Pos                  (11U)
7631 #define CAN_FFA1R_FFA11_Msk                  (0x1UL << CAN_FFA1R_FFA11_Pos)     /*!< 0x00000800 */
7632 #define CAN_FFA1R_FFA11                      CAN_FFA1R_FFA11_Msk               /*!< Filter FIFO Assignment for filter 11 */
7633 #define CAN_FFA1R_FFA12_Pos                  (12U)
7634 #define CAN_FFA1R_FFA12_Msk                  (0x1UL << CAN_FFA1R_FFA12_Pos)     /*!< 0x00001000 */
7635 #define CAN_FFA1R_FFA12                      CAN_FFA1R_FFA12_Msk               /*!< Filter FIFO Assignment for filter 12 */
7636 #define CAN_FFA1R_FFA13_Pos                  (13U)
7637 #define CAN_FFA1R_FFA13_Msk                  (0x1UL << CAN_FFA1R_FFA13_Pos)     /*!< 0x00002000 */
7638 #define CAN_FFA1R_FFA13                      CAN_FFA1R_FFA13_Msk               /*!< Filter FIFO Assignment for filter 13 */
7639 
7640 /*******************  Bit definition for CAN_FA1R register  *******************/
7641 #define CAN_FA1R_FACT_Pos                    (0U)
7642 #define CAN_FA1R_FACT_Msk                    (0x3FFFUL << CAN_FA1R_FACT_Pos)    /*!< 0x00003FFF */
7643 #define CAN_FA1R_FACT                        CAN_FA1R_FACT_Msk                 /*!< Filter Active */
7644 #define CAN_FA1R_FACT0_Pos                   (0U)
7645 #define CAN_FA1R_FACT0_Msk                   (0x1UL << CAN_FA1R_FACT0_Pos)      /*!< 0x00000001 */
7646 #define CAN_FA1R_FACT0                       CAN_FA1R_FACT0_Msk                /*!< Filter 0 Active */
7647 #define CAN_FA1R_FACT1_Pos                   (1U)
7648 #define CAN_FA1R_FACT1_Msk                   (0x1UL << CAN_FA1R_FACT1_Pos)      /*!< 0x00000002 */
7649 #define CAN_FA1R_FACT1                       CAN_FA1R_FACT1_Msk                /*!< Filter 1 Active */
7650 #define CAN_FA1R_FACT2_Pos                   (2U)
7651 #define CAN_FA1R_FACT2_Msk                   (0x1UL << CAN_FA1R_FACT2_Pos)      /*!< 0x00000004 */
7652 #define CAN_FA1R_FACT2                       CAN_FA1R_FACT2_Msk                /*!< Filter 2 Active */
7653 #define CAN_FA1R_FACT3_Pos                   (3U)
7654 #define CAN_FA1R_FACT3_Msk                   (0x1UL << CAN_FA1R_FACT3_Pos)      /*!< 0x00000008 */
7655 #define CAN_FA1R_FACT3                       CAN_FA1R_FACT3_Msk                /*!< Filter 3 Active */
7656 #define CAN_FA1R_FACT4_Pos                   (4U)
7657 #define CAN_FA1R_FACT4_Msk                   (0x1UL << CAN_FA1R_FACT4_Pos)      /*!< 0x00000010 */
7658 #define CAN_FA1R_FACT4                       CAN_FA1R_FACT4_Msk                /*!< Filter 4 Active */
7659 #define CAN_FA1R_FACT5_Pos                   (5U)
7660 #define CAN_FA1R_FACT5_Msk                   (0x1UL << CAN_FA1R_FACT5_Pos)      /*!< 0x00000020 */
7661 #define CAN_FA1R_FACT5                       CAN_FA1R_FACT5_Msk                /*!< Filter 5 Active */
7662 #define CAN_FA1R_FACT6_Pos                   (6U)
7663 #define CAN_FA1R_FACT6_Msk                   (0x1UL << CAN_FA1R_FACT6_Pos)      /*!< 0x00000040 */
7664 #define CAN_FA1R_FACT6                       CAN_FA1R_FACT6_Msk                /*!< Filter 6 Active */
7665 #define CAN_FA1R_FACT7_Pos                   (7U)
7666 #define CAN_FA1R_FACT7_Msk                   (0x1UL << CAN_FA1R_FACT7_Pos)      /*!< 0x00000080 */
7667 #define CAN_FA1R_FACT7                       CAN_FA1R_FACT7_Msk                /*!< Filter 7 Active */
7668 #define CAN_FA1R_FACT8_Pos                   (8U)
7669 #define CAN_FA1R_FACT8_Msk                   (0x1UL << CAN_FA1R_FACT8_Pos)      /*!< 0x00000100 */
7670 #define CAN_FA1R_FACT8                       CAN_FA1R_FACT8_Msk                /*!< Filter 8 Active */
7671 #define CAN_FA1R_FACT9_Pos                   (9U)
7672 #define CAN_FA1R_FACT9_Msk                   (0x1UL << CAN_FA1R_FACT9_Pos)      /*!< 0x00000200 */
7673 #define CAN_FA1R_FACT9                       CAN_FA1R_FACT9_Msk                /*!< Filter 9 Active */
7674 #define CAN_FA1R_FACT10_Pos                  (10U)
7675 #define CAN_FA1R_FACT10_Msk                  (0x1UL << CAN_FA1R_FACT10_Pos)     /*!< 0x00000400 */
7676 #define CAN_FA1R_FACT10                      CAN_FA1R_FACT10_Msk               /*!< Filter 10 Active */
7677 #define CAN_FA1R_FACT11_Pos                  (11U)
7678 #define CAN_FA1R_FACT11_Msk                  (0x1UL << CAN_FA1R_FACT11_Pos)     /*!< 0x00000800 */
7679 #define CAN_FA1R_FACT11                      CAN_FA1R_FACT11_Msk               /*!< Filter 11 Active */
7680 #define CAN_FA1R_FACT12_Pos                  (12U)
7681 #define CAN_FA1R_FACT12_Msk                  (0x1UL << CAN_FA1R_FACT12_Pos)     /*!< 0x00001000 */
7682 #define CAN_FA1R_FACT12                      CAN_FA1R_FACT12_Msk               /*!< Filter 12 Active */
7683 #define CAN_FA1R_FACT13_Pos                  (13U)
7684 #define CAN_FA1R_FACT13_Msk                  (0x1UL << CAN_FA1R_FACT13_Pos)     /*!< 0x00002000 */
7685 #define CAN_FA1R_FACT13                      CAN_FA1R_FACT13_Msk               /*!< Filter 13 Active */
7686 
7687 /*******************  Bit definition for CAN_F0R1 register  *******************/
7688 #define CAN_F0R1_FB0_Pos                     (0U)
7689 #define CAN_F0R1_FB0_Msk                     (0x1UL << CAN_F0R1_FB0_Pos)        /*!< 0x00000001 */
7690 #define CAN_F0R1_FB0                         CAN_F0R1_FB0_Msk                  /*!< Filter bit 0 */
7691 #define CAN_F0R1_FB1_Pos                     (1U)
7692 #define CAN_F0R1_FB1_Msk                     (0x1UL << CAN_F0R1_FB1_Pos)        /*!< 0x00000002 */
7693 #define CAN_F0R1_FB1                         CAN_F0R1_FB1_Msk                  /*!< Filter bit 1 */
7694 #define CAN_F0R1_FB2_Pos                     (2U)
7695 #define CAN_F0R1_FB2_Msk                     (0x1UL << CAN_F0R1_FB2_Pos)        /*!< 0x00000004 */
7696 #define CAN_F0R1_FB2                         CAN_F0R1_FB2_Msk                  /*!< Filter bit 2 */
7697 #define CAN_F0R1_FB3_Pos                     (3U)
7698 #define CAN_F0R1_FB3_Msk                     (0x1UL << CAN_F0R1_FB3_Pos)        /*!< 0x00000008 */
7699 #define CAN_F0R1_FB3                         CAN_F0R1_FB3_Msk                  /*!< Filter bit 3 */
7700 #define CAN_F0R1_FB4_Pos                     (4U)
7701 #define CAN_F0R1_FB4_Msk                     (0x1UL << CAN_F0R1_FB4_Pos)        /*!< 0x00000010 */
7702 #define CAN_F0R1_FB4                         CAN_F0R1_FB4_Msk                  /*!< Filter bit 4 */
7703 #define CAN_F0R1_FB5_Pos                     (5U)
7704 #define CAN_F0R1_FB5_Msk                     (0x1UL << CAN_F0R1_FB5_Pos)        /*!< 0x00000020 */
7705 #define CAN_F0R1_FB5                         CAN_F0R1_FB5_Msk                  /*!< Filter bit 5 */
7706 #define CAN_F0R1_FB6_Pos                     (6U)
7707 #define CAN_F0R1_FB6_Msk                     (0x1UL << CAN_F0R1_FB6_Pos)        /*!< 0x00000040 */
7708 #define CAN_F0R1_FB6                         CAN_F0R1_FB6_Msk                  /*!< Filter bit 6 */
7709 #define CAN_F0R1_FB7_Pos                     (7U)
7710 #define CAN_F0R1_FB7_Msk                     (0x1UL << CAN_F0R1_FB7_Pos)        /*!< 0x00000080 */
7711 #define CAN_F0R1_FB7                         CAN_F0R1_FB7_Msk                  /*!< Filter bit 7 */
7712 #define CAN_F0R1_FB8_Pos                     (8U)
7713 #define CAN_F0R1_FB8_Msk                     (0x1UL << CAN_F0R1_FB8_Pos)        /*!< 0x00000100 */
7714 #define CAN_F0R1_FB8                         CAN_F0R1_FB8_Msk                  /*!< Filter bit 8 */
7715 #define CAN_F0R1_FB9_Pos                     (9U)
7716 #define CAN_F0R1_FB9_Msk                     (0x1UL << CAN_F0R1_FB9_Pos)        /*!< 0x00000200 */
7717 #define CAN_F0R1_FB9                         CAN_F0R1_FB9_Msk                  /*!< Filter bit 9 */
7718 #define CAN_F0R1_FB10_Pos                    (10U)
7719 #define CAN_F0R1_FB10_Msk                    (0x1UL << CAN_F0R1_FB10_Pos)       /*!< 0x00000400 */
7720 #define CAN_F0R1_FB10                        CAN_F0R1_FB10_Msk                 /*!< Filter bit 10 */
7721 #define CAN_F0R1_FB11_Pos                    (11U)
7722 #define CAN_F0R1_FB11_Msk                    (0x1UL << CAN_F0R1_FB11_Pos)       /*!< 0x00000800 */
7723 #define CAN_F0R1_FB11                        CAN_F0R1_FB11_Msk                 /*!< Filter bit 11 */
7724 #define CAN_F0R1_FB12_Pos                    (12U)
7725 #define CAN_F0R1_FB12_Msk                    (0x1UL << CAN_F0R1_FB12_Pos)       /*!< 0x00001000 */
7726 #define CAN_F0R1_FB12                        CAN_F0R1_FB12_Msk                 /*!< Filter bit 12 */
7727 #define CAN_F0R1_FB13_Pos                    (13U)
7728 #define CAN_F0R1_FB13_Msk                    (0x1UL << CAN_F0R1_FB13_Pos)       /*!< 0x00002000 */
7729 #define CAN_F0R1_FB13                        CAN_F0R1_FB13_Msk                 /*!< Filter bit 13 */
7730 #define CAN_F0R1_FB14_Pos                    (14U)
7731 #define CAN_F0R1_FB14_Msk                    (0x1UL << CAN_F0R1_FB14_Pos)       /*!< 0x00004000 */
7732 #define CAN_F0R1_FB14                        CAN_F0R1_FB14_Msk                 /*!< Filter bit 14 */
7733 #define CAN_F0R1_FB15_Pos                    (15U)
7734 #define CAN_F0R1_FB15_Msk                    (0x1UL << CAN_F0R1_FB15_Pos)       /*!< 0x00008000 */
7735 #define CAN_F0R1_FB15                        CAN_F0R1_FB15_Msk                 /*!< Filter bit 15 */
7736 #define CAN_F0R1_FB16_Pos                    (16U)
7737 #define CAN_F0R1_FB16_Msk                    (0x1UL << CAN_F0R1_FB16_Pos)       /*!< 0x00010000 */
7738 #define CAN_F0R1_FB16                        CAN_F0R1_FB16_Msk                 /*!< Filter bit 16 */
7739 #define CAN_F0R1_FB17_Pos                    (17U)
7740 #define CAN_F0R1_FB17_Msk                    (0x1UL << CAN_F0R1_FB17_Pos)       /*!< 0x00020000 */
7741 #define CAN_F0R1_FB17                        CAN_F0R1_FB17_Msk                 /*!< Filter bit 17 */
7742 #define CAN_F0R1_FB18_Pos                    (18U)
7743 #define CAN_F0R1_FB18_Msk                    (0x1UL << CAN_F0R1_FB18_Pos)       /*!< 0x00040000 */
7744 #define CAN_F0R1_FB18                        CAN_F0R1_FB18_Msk                 /*!< Filter bit 18 */
7745 #define CAN_F0R1_FB19_Pos                    (19U)
7746 #define CAN_F0R1_FB19_Msk                    (0x1UL << CAN_F0R1_FB19_Pos)       /*!< 0x00080000 */
7747 #define CAN_F0R1_FB19                        CAN_F0R1_FB19_Msk                 /*!< Filter bit 19 */
7748 #define CAN_F0R1_FB20_Pos                    (20U)
7749 #define CAN_F0R1_FB20_Msk                    (0x1UL << CAN_F0R1_FB20_Pos)       /*!< 0x00100000 */
7750 #define CAN_F0R1_FB20                        CAN_F0R1_FB20_Msk                 /*!< Filter bit 20 */
7751 #define CAN_F0R1_FB21_Pos                    (21U)
7752 #define CAN_F0R1_FB21_Msk                    (0x1UL << CAN_F0R1_FB21_Pos)       /*!< 0x00200000 */
7753 #define CAN_F0R1_FB21                        CAN_F0R1_FB21_Msk                 /*!< Filter bit 21 */
7754 #define CAN_F0R1_FB22_Pos                    (22U)
7755 #define CAN_F0R1_FB22_Msk                    (0x1UL << CAN_F0R1_FB22_Pos)       /*!< 0x00400000 */
7756 #define CAN_F0R1_FB22                        CAN_F0R1_FB22_Msk                 /*!< Filter bit 22 */
7757 #define CAN_F0R1_FB23_Pos                    (23U)
7758 #define CAN_F0R1_FB23_Msk                    (0x1UL << CAN_F0R1_FB23_Pos)       /*!< 0x00800000 */
7759 #define CAN_F0R1_FB23                        CAN_F0R1_FB23_Msk                 /*!< Filter bit 23 */
7760 #define CAN_F0R1_FB24_Pos                    (24U)
7761 #define CAN_F0R1_FB24_Msk                    (0x1UL << CAN_F0R1_FB24_Pos)       /*!< 0x01000000 */
7762 #define CAN_F0R1_FB24                        CAN_F0R1_FB24_Msk                 /*!< Filter bit 24 */
7763 #define CAN_F0R1_FB25_Pos                    (25U)
7764 #define CAN_F0R1_FB25_Msk                    (0x1UL << CAN_F0R1_FB25_Pos)       /*!< 0x02000000 */
7765 #define CAN_F0R1_FB25                        CAN_F0R1_FB25_Msk                 /*!< Filter bit 25 */
7766 #define CAN_F0R1_FB26_Pos                    (26U)
7767 #define CAN_F0R1_FB26_Msk                    (0x1UL << CAN_F0R1_FB26_Pos)       /*!< 0x04000000 */
7768 #define CAN_F0R1_FB26                        CAN_F0R1_FB26_Msk                 /*!< Filter bit 26 */
7769 #define CAN_F0R1_FB27_Pos                    (27U)
7770 #define CAN_F0R1_FB27_Msk                    (0x1UL << CAN_F0R1_FB27_Pos)       /*!< 0x08000000 */
7771 #define CAN_F0R1_FB27                        CAN_F0R1_FB27_Msk                 /*!< Filter bit 27 */
7772 #define CAN_F0R1_FB28_Pos                    (28U)
7773 #define CAN_F0R1_FB28_Msk                    (0x1UL << CAN_F0R1_FB28_Pos)       /*!< 0x10000000 */
7774 #define CAN_F0R1_FB28                        CAN_F0R1_FB28_Msk                 /*!< Filter bit 28 */
7775 #define CAN_F0R1_FB29_Pos                    (29U)
7776 #define CAN_F0R1_FB29_Msk                    (0x1UL << CAN_F0R1_FB29_Pos)       /*!< 0x20000000 */
7777 #define CAN_F0R1_FB29                        CAN_F0R1_FB29_Msk                 /*!< Filter bit 29 */
7778 #define CAN_F0R1_FB30_Pos                    (30U)
7779 #define CAN_F0R1_FB30_Msk                    (0x1UL << CAN_F0R1_FB30_Pos)       /*!< 0x40000000 */
7780 #define CAN_F0R1_FB30                        CAN_F0R1_FB30_Msk                 /*!< Filter bit 30 */
7781 #define CAN_F0R1_FB31_Pos                    (31U)
7782 #define CAN_F0R1_FB31_Msk                    (0x1UL << CAN_F0R1_FB31_Pos)       /*!< 0x80000000 */
7783 #define CAN_F0R1_FB31                        CAN_F0R1_FB31_Msk                 /*!< Filter bit 31 */
7784 
7785 /*******************  Bit definition for CAN_F1R1 register  *******************/
7786 #define CAN_F1R1_FB0_Pos                     (0U)
7787 #define CAN_F1R1_FB0_Msk                     (0x1UL << CAN_F1R1_FB0_Pos)        /*!< 0x00000001 */
7788 #define CAN_F1R1_FB0                         CAN_F1R1_FB0_Msk                  /*!< Filter bit 0 */
7789 #define CAN_F1R1_FB1_Pos                     (1U)
7790 #define CAN_F1R1_FB1_Msk                     (0x1UL << CAN_F1R1_FB1_Pos)        /*!< 0x00000002 */
7791 #define CAN_F1R1_FB1                         CAN_F1R1_FB1_Msk                  /*!< Filter bit 1 */
7792 #define CAN_F1R1_FB2_Pos                     (2U)
7793 #define CAN_F1R1_FB2_Msk                     (0x1UL << CAN_F1R1_FB2_Pos)        /*!< 0x00000004 */
7794 #define CAN_F1R1_FB2                         CAN_F1R1_FB2_Msk                  /*!< Filter bit 2 */
7795 #define CAN_F1R1_FB3_Pos                     (3U)
7796 #define CAN_F1R1_FB3_Msk                     (0x1UL << CAN_F1R1_FB3_Pos)        /*!< 0x00000008 */
7797 #define CAN_F1R1_FB3                         CAN_F1R1_FB3_Msk                  /*!< Filter bit 3 */
7798 #define CAN_F1R1_FB4_Pos                     (4U)
7799 #define CAN_F1R1_FB4_Msk                     (0x1UL << CAN_F1R1_FB4_Pos)        /*!< 0x00000010 */
7800 #define CAN_F1R1_FB4                         CAN_F1R1_FB4_Msk                  /*!< Filter bit 4 */
7801 #define CAN_F1R1_FB5_Pos                     (5U)
7802 #define CAN_F1R1_FB5_Msk                     (0x1UL << CAN_F1R1_FB5_Pos)        /*!< 0x00000020 */
7803 #define CAN_F1R1_FB5                         CAN_F1R1_FB5_Msk                  /*!< Filter bit 5 */
7804 #define CAN_F1R1_FB6_Pos                     (6U)
7805 #define CAN_F1R1_FB6_Msk                     (0x1UL << CAN_F1R1_FB6_Pos)        /*!< 0x00000040 */
7806 #define CAN_F1R1_FB6                         CAN_F1R1_FB6_Msk                  /*!< Filter bit 6 */
7807 #define CAN_F1R1_FB7_Pos                     (7U)
7808 #define CAN_F1R1_FB7_Msk                     (0x1UL << CAN_F1R1_FB7_Pos)        /*!< 0x00000080 */
7809 #define CAN_F1R1_FB7                         CAN_F1R1_FB7_Msk                  /*!< Filter bit 7 */
7810 #define CAN_F1R1_FB8_Pos                     (8U)
7811 #define CAN_F1R1_FB8_Msk                     (0x1UL << CAN_F1R1_FB8_Pos)        /*!< 0x00000100 */
7812 #define CAN_F1R1_FB8                         CAN_F1R1_FB8_Msk                  /*!< Filter bit 8 */
7813 #define CAN_F1R1_FB9_Pos                     (9U)
7814 #define CAN_F1R1_FB9_Msk                     (0x1UL << CAN_F1R1_FB9_Pos)        /*!< 0x00000200 */
7815 #define CAN_F1R1_FB9                         CAN_F1R1_FB9_Msk                  /*!< Filter bit 9 */
7816 #define CAN_F1R1_FB10_Pos                    (10U)
7817 #define CAN_F1R1_FB10_Msk                    (0x1UL << CAN_F1R1_FB10_Pos)       /*!< 0x00000400 */
7818 #define CAN_F1R1_FB10                        CAN_F1R1_FB10_Msk                 /*!< Filter bit 10 */
7819 #define CAN_F1R1_FB11_Pos                    (11U)
7820 #define CAN_F1R1_FB11_Msk                    (0x1UL << CAN_F1R1_FB11_Pos)       /*!< 0x00000800 */
7821 #define CAN_F1R1_FB11                        CAN_F1R1_FB11_Msk                 /*!< Filter bit 11 */
7822 #define CAN_F1R1_FB12_Pos                    (12U)
7823 #define CAN_F1R1_FB12_Msk                    (0x1UL << CAN_F1R1_FB12_Pos)       /*!< 0x00001000 */
7824 #define CAN_F1R1_FB12                        CAN_F1R1_FB12_Msk                 /*!< Filter bit 12 */
7825 #define CAN_F1R1_FB13_Pos                    (13U)
7826 #define CAN_F1R1_FB13_Msk                    (0x1UL << CAN_F1R1_FB13_Pos)       /*!< 0x00002000 */
7827 #define CAN_F1R1_FB13                        CAN_F1R1_FB13_Msk                 /*!< Filter bit 13 */
7828 #define CAN_F1R1_FB14_Pos                    (14U)
7829 #define CAN_F1R1_FB14_Msk                    (0x1UL << CAN_F1R1_FB14_Pos)       /*!< 0x00004000 */
7830 #define CAN_F1R1_FB14                        CAN_F1R1_FB14_Msk                 /*!< Filter bit 14 */
7831 #define CAN_F1R1_FB15_Pos                    (15U)
7832 #define CAN_F1R1_FB15_Msk                    (0x1UL << CAN_F1R1_FB15_Pos)       /*!< 0x00008000 */
7833 #define CAN_F1R1_FB15                        CAN_F1R1_FB15_Msk                 /*!< Filter bit 15 */
7834 #define CAN_F1R1_FB16_Pos                    (16U)
7835 #define CAN_F1R1_FB16_Msk                    (0x1UL << CAN_F1R1_FB16_Pos)       /*!< 0x00010000 */
7836 #define CAN_F1R1_FB16                        CAN_F1R1_FB16_Msk                 /*!< Filter bit 16 */
7837 #define CAN_F1R1_FB17_Pos                    (17U)
7838 #define CAN_F1R1_FB17_Msk                    (0x1UL << CAN_F1R1_FB17_Pos)       /*!< 0x00020000 */
7839 #define CAN_F1R1_FB17                        CAN_F1R1_FB17_Msk                 /*!< Filter bit 17 */
7840 #define CAN_F1R1_FB18_Pos                    (18U)
7841 #define CAN_F1R1_FB18_Msk                    (0x1UL << CAN_F1R1_FB18_Pos)       /*!< 0x00040000 */
7842 #define CAN_F1R1_FB18                        CAN_F1R1_FB18_Msk                 /*!< Filter bit 18 */
7843 #define CAN_F1R1_FB19_Pos                    (19U)
7844 #define CAN_F1R1_FB19_Msk                    (0x1UL << CAN_F1R1_FB19_Pos)       /*!< 0x00080000 */
7845 #define CAN_F1R1_FB19                        CAN_F1R1_FB19_Msk                 /*!< Filter bit 19 */
7846 #define CAN_F1R1_FB20_Pos                    (20U)
7847 #define CAN_F1R1_FB20_Msk                    (0x1UL << CAN_F1R1_FB20_Pos)       /*!< 0x00100000 */
7848 #define CAN_F1R1_FB20                        CAN_F1R1_FB20_Msk                 /*!< Filter bit 20 */
7849 #define CAN_F1R1_FB21_Pos                    (21U)
7850 #define CAN_F1R1_FB21_Msk                    (0x1UL << CAN_F1R1_FB21_Pos)       /*!< 0x00200000 */
7851 #define CAN_F1R1_FB21                        CAN_F1R1_FB21_Msk                 /*!< Filter bit 21 */
7852 #define CAN_F1R1_FB22_Pos                    (22U)
7853 #define CAN_F1R1_FB22_Msk                    (0x1UL << CAN_F1R1_FB22_Pos)       /*!< 0x00400000 */
7854 #define CAN_F1R1_FB22                        CAN_F1R1_FB22_Msk                 /*!< Filter bit 22 */
7855 #define CAN_F1R1_FB23_Pos                    (23U)
7856 #define CAN_F1R1_FB23_Msk                    (0x1UL << CAN_F1R1_FB23_Pos)       /*!< 0x00800000 */
7857 #define CAN_F1R1_FB23                        CAN_F1R1_FB23_Msk                 /*!< Filter bit 23 */
7858 #define CAN_F1R1_FB24_Pos                    (24U)
7859 #define CAN_F1R1_FB24_Msk                    (0x1UL << CAN_F1R1_FB24_Pos)       /*!< 0x01000000 */
7860 #define CAN_F1R1_FB24                        CAN_F1R1_FB24_Msk                 /*!< Filter bit 24 */
7861 #define CAN_F1R1_FB25_Pos                    (25U)
7862 #define CAN_F1R1_FB25_Msk                    (0x1UL << CAN_F1R1_FB25_Pos)       /*!< 0x02000000 */
7863 #define CAN_F1R1_FB25                        CAN_F1R1_FB25_Msk                 /*!< Filter bit 25 */
7864 #define CAN_F1R1_FB26_Pos                    (26U)
7865 #define CAN_F1R1_FB26_Msk                    (0x1UL << CAN_F1R1_FB26_Pos)       /*!< 0x04000000 */
7866 #define CAN_F1R1_FB26                        CAN_F1R1_FB26_Msk                 /*!< Filter bit 26 */
7867 #define CAN_F1R1_FB27_Pos                    (27U)
7868 #define CAN_F1R1_FB27_Msk                    (0x1UL << CAN_F1R1_FB27_Pos)       /*!< 0x08000000 */
7869 #define CAN_F1R1_FB27                        CAN_F1R1_FB27_Msk                 /*!< Filter bit 27 */
7870 #define CAN_F1R1_FB28_Pos                    (28U)
7871 #define CAN_F1R1_FB28_Msk                    (0x1UL << CAN_F1R1_FB28_Pos)       /*!< 0x10000000 */
7872 #define CAN_F1R1_FB28                        CAN_F1R1_FB28_Msk                 /*!< Filter bit 28 */
7873 #define CAN_F1R1_FB29_Pos                    (29U)
7874 #define CAN_F1R1_FB29_Msk                    (0x1UL << CAN_F1R1_FB29_Pos)       /*!< 0x20000000 */
7875 #define CAN_F1R1_FB29                        CAN_F1R1_FB29_Msk                 /*!< Filter bit 29 */
7876 #define CAN_F1R1_FB30_Pos                    (30U)
7877 #define CAN_F1R1_FB30_Msk                    (0x1UL << CAN_F1R1_FB30_Pos)       /*!< 0x40000000 */
7878 #define CAN_F1R1_FB30                        CAN_F1R1_FB30_Msk                 /*!< Filter bit 30 */
7879 #define CAN_F1R1_FB31_Pos                    (31U)
7880 #define CAN_F1R1_FB31_Msk                    (0x1UL << CAN_F1R1_FB31_Pos)       /*!< 0x80000000 */
7881 #define CAN_F1R1_FB31                        CAN_F1R1_FB31_Msk                 /*!< Filter bit 31 */
7882 
7883 /*******************  Bit definition for CAN_F2R1 register  *******************/
7884 #define CAN_F2R1_FB0_Pos                     (0U)
7885 #define CAN_F2R1_FB0_Msk                     (0x1UL << CAN_F2R1_FB0_Pos)        /*!< 0x00000001 */
7886 #define CAN_F2R1_FB0                         CAN_F2R1_FB0_Msk                  /*!< Filter bit 0 */
7887 #define CAN_F2R1_FB1_Pos                     (1U)
7888 #define CAN_F2R1_FB1_Msk                     (0x1UL << CAN_F2R1_FB1_Pos)        /*!< 0x00000002 */
7889 #define CAN_F2R1_FB1                         CAN_F2R1_FB1_Msk                  /*!< Filter bit 1 */
7890 #define CAN_F2R1_FB2_Pos                     (2U)
7891 #define CAN_F2R1_FB2_Msk                     (0x1UL << CAN_F2R1_FB2_Pos)        /*!< 0x00000004 */
7892 #define CAN_F2R1_FB2                         CAN_F2R1_FB2_Msk                  /*!< Filter bit 2 */
7893 #define CAN_F2R1_FB3_Pos                     (3U)
7894 #define CAN_F2R1_FB3_Msk                     (0x1UL << CAN_F2R1_FB3_Pos)        /*!< 0x00000008 */
7895 #define CAN_F2R1_FB3                         CAN_F2R1_FB3_Msk                  /*!< Filter bit 3 */
7896 #define CAN_F2R1_FB4_Pos                     (4U)
7897 #define CAN_F2R1_FB4_Msk                     (0x1UL << CAN_F2R1_FB4_Pos)        /*!< 0x00000010 */
7898 #define CAN_F2R1_FB4                         CAN_F2R1_FB4_Msk                  /*!< Filter bit 4 */
7899 #define CAN_F2R1_FB5_Pos                     (5U)
7900 #define CAN_F2R1_FB5_Msk                     (0x1UL << CAN_F2R1_FB5_Pos)        /*!< 0x00000020 */
7901 #define CAN_F2R1_FB5                         CAN_F2R1_FB5_Msk                  /*!< Filter bit 5 */
7902 #define CAN_F2R1_FB6_Pos                     (6U)
7903 #define CAN_F2R1_FB6_Msk                     (0x1UL << CAN_F2R1_FB6_Pos)        /*!< 0x00000040 */
7904 #define CAN_F2R1_FB6                         CAN_F2R1_FB6_Msk                  /*!< Filter bit 6 */
7905 #define CAN_F2R1_FB7_Pos                     (7U)
7906 #define CAN_F2R1_FB7_Msk                     (0x1UL << CAN_F2R1_FB7_Pos)        /*!< 0x00000080 */
7907 #define CAN_F2R1_FB7                         CAN_F2R1_FB7_Msk                  /*!< Filter bit 7 */
7908 #define CAN_F2R1_FB8_Pos                     (8U)
7909 #define CAN_F2R1_FB8_Msk                     (0x1UL << CAN_F2R1_FB8_Pos)        /*!< 0x00000100 */
7910 #define CAN_F2R1_FB8                         CAN_F2R1_FB8_Msk                  /*!< Filter bit 8 */
7911 #define CAN_F2R1_FB9_Pos                     (9U)
7912 #define CAN_F2R1_FB9_Msk                     (0x1UL << CAN_F2R1_FB9_Pos)        /*!< 0x00000200 */
7913 #define CAN_F2R1_FB9                         CAN_F2R1_FB9_Msk                  /*!< Filter bit 9 */
7914 #define CAN_F2R1_FB10_Pos                    (10U)
7915 #define CAN_F2R1_FB10_Msk                    (0x1UL << CAN_F2R1_FB10_Pos)       /*!< 0x00000400 */
7916 #define CAN_F2R1_FB10                        CAN_F2R1_FB10_Msk                 /*!< Filter bit 10 */
7917 #define CAN_F2R1_FB11_Pos                    (11U)
7918 #define CAN_F2R1_FB11_Msk                    (0x1UL << CAN_F2R1_FB11_Pos)       /*!< 0x00000800 */
7919 #define CAN_F2R1_FB11                        CAN_F2R1_FB11_Msk                 /*!< Filter bit 11 */
7920 #define CAN_F2R1_FB12_Pos                    (12U)
7921 #define CAN_F2R1_FB12_Msk                    (0x1UL << CAN_F2R1_FB12_Pos)       /*!< 0x00001000 */
7922 #define CAN_F2R1_FB12                        CAN_F2R1_FB12_Msk                 /*!< Filter bit 12 */
7923 #define CAN_F2R1_FB13_Pos                    (13U)
7924 #define CAN_F2R1_FB13_Msk                    (0x1UL << CAN_F2R1_FB13_Pos)       /*!< 0x00002000 */
7925 #define CAN_F2R1_FB13                        CAN_F2R1_FB13_Msk                 /*!< Filter bit 13 */
7926 #define CAN_F2R1_FB14_Pos                    (14U)
7927 #define CAN_F2R1_FB14_Msk                    (0x1UL << CAN_F2R1_FB14_Pos)       /*!< 0x00004000 */
7928 #define CAN_F2R1_FB14                        CAN_F2R1_FB14_Msk                 /*!< Filter bit 14 */
7929 #define CAN_F2R1_FB15_Pos                    (15U)
7930 #define CAN_F2R1_FB15_Msk                    (0x1UL << CAN_F2R1_FB15_Pos)       /*!< 0x00008000 */
7931 #define CAN_F2R1_FB15                        CAN_F2R1_FB15_Msk                 /*!< Filter bit 15 */
7932 #define CAN_F2R1_FB16_Pos                    (16U)
7933 #define CAN_F2R1_FB16_Msk                    (0x1UL << CAN_F2R1_FB16_Pos)       /*!< 0x00010000 */
7934 #define CAN_F2R1_FB16                        CAN_F2R1_FB16_Msk                 /*!< Filter bit 16 */
7935 #define CAN_F2R1_FB17_Pos                    (17U)
7936 #define CAN_F2R1_FB17_Msk                    (0x1UL << CAN_F2R1_FB17_Pos)       /*!< 0x00020000 */
7937 #define CAN_F2R1_FB17                        CAN_F2R1_FB17_Msk                 /*!< Filter bit 17 */
7938 #define CAN_F2R1_FB18_Pos                    (18U)
7939 #define CAN_F2R1_FB18_Msk                    (0x1UL << CAN_F2R1_FB18_Pos)       /*!< 0x00040000 */
7940 #define CAN_F2R1_FB18                        CAN_F2R1_FB18_Msk                 /*!< Filter bit 18 */
7941 #define CAN_F2R1_FB19_Pos                    (19U)
7942 #define CAN_F2R1_FB19_Msk                    (0x1UL << CAN_F2R1_FB19_Pos)       /*!< 0x00080000 */
7943 #define CAN_F2R1_FB19                        CAN_F2R1_FB19_Msk                 /*!< Filter bit 19 */
7944 #define CAN_F2R1_FB20_Pos                    (20U)
7945 #define CAN_F2R1_FB20_Msk                    (0x1UL << CAN_F2R1_FB20_Pos)       /*!< 0x00100000 */
7946 #define CAN_F2R1_FB20                        CAN_F2R1_FB20_Msk                 /*!< Filter bit 20 */
7947 #define CAN_F2R1_FB21_Pos                    (21U)
7948 #define CAN_F2R1_FB21_Msk                    (0x1UL << CAN_F2R1_FB21_Pos)       /*!< 0x00200000 */
7949 #define CAN_F2R1_FB21                        CAN_F2R1_FB21_Msk                 /*!< Filter bit 21 */
7950 #define CAN_F2R1_FB22_Pos                    (22U)
7951 #define CAN_F2R1_FB22_Msk                    (0x1UL << CAN_F2R1_FB22_Pos)       /*!< 0x00400000 */
7952 #define CAN_F2R1_FB22                        CAN_F2R1_FB22_Msk                 /*!< Filter bit 22 */
7953 #define CAN_F2R1_FB23_Pos                    (23U)
7954 #define CAN_F2R1_FB23_Msk                    (0x1UL << CAN_F2R1_FB23_Pos)       /*!< 0x00800000 */
7955 #define CAN_F2R1_FB23                        CAN_F2R1_FB23_Msk                 /*!< Filter bit 23 */
7956 #define CAN_F2R1_FB24_Pos                    (24U)
7957 #define CAN_F2R1_FB24_Msk                    (0x1UL << CAN_F2R1_FB24_Pos)       /*!< 0x01000000 */
7958 #define CAN_F2R1_FB24                        CAN_F2R1_FB24_Msk                 /*!< Filter bit 24 */
7959 #define CAN_F2R1_FB25_Pos                    (25U)
7960 #define CAN_F2R1_FB25_Msk                    (0x1UL << CAN_F2R1_FB25_Pos)       /*!< 0x02000000 */
7961 #define CAN_F2R1_FB25                        CAN_F2R1_FB25_Msk                 /*!< Filter bit 25 */
7962 #define CAN_F2R1_FB26_Pos                    (26U)
7963 #define CAN_F2R1_FB26_Msk                    (0x1UL << CAN_F2R1_FB26_Pos)       /*!< 0x04000000 */
7964 #define CAN_F2R1_FB26                        CAN_F2R1_FB26_Msk                 /*!< Filter bit 26 */
7965 #define CAN_F2R1_FB27_Pos                    (27U)
7966 #define CAN_F2R1_FB27_Msk                    (0x1UL << CAN_F2R1_FB27_Pos)       /*!< 0x08000000 */
7967 #define CAN_F2R1_FB27                        CAN_F2R1_FB27_Msk                 /*!< Filter bit 27 */
7968 #define CAN_F2R1_FB28_Pos                    (28U)
7969 #define CAN_F2R1_FB28_Msk                    (0x1UL << CAN_F2R1_FB28_Pos)       /*!< 0x10000000 */
7970 #define CAN_F2R1_FB28                        CAN_F2R1_FB28_Msk                 /*!< Filter bit 28 */
7971 #define CAN_F2R1_FB29_Pos                    (29U)
7972 #define CAN_F2R1_FB29_Msk                    (0x1UL << CAN_F2R1_FB29_Pos)       /*!< 0x20000000 */
7973 #define CAN_F2R1_FB29                        CAN_F2R1_FB29_Msk                 /*!< Filter bit 29 */
7974 #define CAN_F2R1_FB30_Pos                    (30U)
7975 #define CAN_F2R1_FB30_Msk                    (0x1UL << CAN_F2R1_FB30_Pos)       /*!< 0x40000000 */
7976 #define CAN_F2R1_FB30                        CAN_F2R1_FB30_Msk                 /*!< Filter bit 30 */
7977 #define CAN_F2R1_FB31_Pos                    (31U)
7978 #define CAN_F2R1_FB31_Msk                    (0x1UL << CAN_F2R1_FB31_Pos)       /*!< 0x80000000 */
7979 #define CAN_F2R1_FB31                        CAN_F2R1_FB31_Msk                 /*!< Filter bit 31 */
7980 
7981 /*******************  Bit definition for CAN_F3R1 register  *******************/
7982 #define CAN_F3R1_FB0_Pos                     (0U)
7983 #define CAN_F3R1_FB0_Msk                     (0x1UL << CAN_F3R1_FB0_Pos)        /*!< 0x00000001 */
7984 #define CAN_F3R1_FB0                         CAN_F3R1_FB0_Msk                  /*!< Filter bit 0 */
7985 #define CAN_F3R1_FB1_Pos                     (1U)
7986 #define CAN_F3R1_FB1_Msk                     (0x1UL << CAN_F3R1_FB1_Pos)        /*!< 0x00000002 */
7987 #define CAN_F3R1_FB1                         CAN_F3R1_FB1_Msk                  /*!< Filter bit 1 */
7988 #define CAN_F3R1_FB2_Pos                     (2U)
7989 #define CAN_F3R1_FB2_Msk                     (0x1UL << CAN_F3R1_FB2_Pos)        /*!< 0x00000004 */
7990 #define CAN_F3R1_FB2                         CAN_F3R1_FB2_Msk                  /*!< Filter bit 2 */
7991 #define CAN_F3R1_FB3_Pos                     (3U)
7992 #define CAN_F3R1_FB3_Msk                     (0x1UL << CAN_F3R1_FB3_Pos)        /*!< 0x00000008 */
7993 #define CAN_F3R1_FB3                         CAN_F3R1_FB3_Msk                  /*!< Filter bit 3 */
7994 #define CAN_F3R1_FB4_Pos                     (4U)
7995 #define CAN_F3R1_FB4_Msk                     (0x1UL << CAN_F3R1_FB4_Pos)        /*!< 0x00000010 */
7996 #define CAN_F3R1_FB4                         CAN_F3R1_FB4_Msk                  /*!< Filter bit 4 */
7997 #define CAN_F3R1_FB5_Pos                     (5U)
7998 #define CAN_F3R1_FB5_Msk                     (0x1UL << CAN_F3R1_FB5_Pos)        /*!< 0x00000020 */
7999 #define CAN_F3R1_FB5                         CAN_F3R1_FB5_Msk                  /*!< Filter bit 5 */
8000 #define CAN_F3R1_FB6_Pos                     (6U)
8001 #define CAN_F3R1_FB6_Msk                     (0x1UL << CAN_F3R1_FB6_Pos)        /*!< 0x00000040 */
8002 #define CAN_F3R1_FB6                         CAN_F3R1_FB6_Msk                  /*!< Filter bit 6 */
8003 #define CAN_F3R1_FB7_Pos                     (7U)
8004 #define CAN_F3R1_FB7_Msk                     (0x1UL << CAN_F3R1_FB7_Pos)        /*!< 0x00000080 */
8005 #define CAN_F3R1_FB7                         CAN_F3R1_FB7_Msk                  /*!< Filter bit 7 */
8006 #define CAN_F3R1_FB8_Pos                     (8U)
8007 #define CAN_F3R1_FB8_Msk                     (0x1UL << CAN_F3R1_FB8_Pos)        /*!< 0x00000100 */
8008 #define CAN_F3R1_FB8                         CAN_F3R1_FB8_Msk                  /*!< Filter bit 8 */
8009 #define CAN_F3R1_FB9_Pos                     (9U)
8010 #define CAN_F3R1_FB9_Msk                     (0x1UL << CAN_F3R1_FB9_Pos)        /*!< 0x00000200 */
8011 #define CAN_F3R1_FB9                         CAN_F3R1_FB9_Msk                  /*!< Filter bit 9 */
8012 #define CAN_F3R1_FB10_Pos                    (10U)
8013 #define CAN_F3R1_FB10_Msk                    (0x1UL << CAN_F3R1_FB10_Pos)       /*!< 0x00000400 */
8014 #define CAN_F3R1_FB10                        CAN_F3R1_FB10_Msk                 /*!< Filter bit 10 */
8015 #define CAN_F3R1_FB11_Pos                    (11U)
8016 #define CAN_F3R1_FB11_Msk                    (0x1UL << CAN_F3R1_FB11_Pos)       /*!< 0x00000800 */
8017 #define CAN_F3R1_FB11                        CAN_F3R1_FB11_Msk                 /*!< Filter bit 11 */
8018 #define CAN_F3R1_FB12_Pos                    (12U)
8019 #define CAN_F3R1_FB12_Msk                    (0x1UL << CAN_F3R1_FB12_Pos)       /*!< 0x00001000 */
8020 #define CAN_F3R1_FB12                        CAN_F3R1_FB12_Msk                 /*!< Filter bit 12 */
8021 #define CAN_F3R1_FB13_Pos                    (13U)
8022 #define CAN_F3R1_FB13_Msk                    (0x1UL << CAN_F3R1_FB13_Pos)       /*!< 0x00002000 */
8023 #define CAN_F3R1_FB13                        CAN_F3R1_FB13_Msk                 /*!< Filter bit 13 */
8024 #define CAN_F3R1_FB14_Pos                    (14U)
8025 #define CAN_F3R1_FB14_Msk                    (0x1UL << CAN_F3R1_FB14_Pos)       /*!< 0x00004000 */
8026 #define CAN_F3R1_FB14                        CAN_F3R1_FB14_Msk                 /*!< Filter bit 14 */
8027 #define CAN_F3R1_FB15_Pos                    (15U)
8028 #define CAN_F3R1_FB15_Msk                    (0x1UL << CAN_F3R1_FB15_Pos)       /*!< 0x00008000 */
8029 #define CAN_F3R1_FB15                        CAN_F3R1_FB15_Msk                 /*!< Filter bit 15 */
8030 #define CAN_F3R1_FB16_Pos                    (16U)
8031 #define CAN_F3R1_FB16_Msk                    (0x1UL << CAN_F3R1_FB16_Pos)       /*!< 0x00010000 */
8032 #define CAN_F3R1_FB16                        CAN_F3R1_FB16_Msk                 /*!< Filter bit 16 */
8033 #define CAN_F3R1_FB17_Pos                    (17U)
8034 #define CAN_F3R1_FB17_Msk                    (0x1UL << CAN_F3R1_FB17_Pos)       /*!< 0x00020000 */
8035 #define CAN_F3R1_FB17                        CAN_F3R1_FB17_Msk                 /*!< Filter bit 17 */
8036 #define CAN_F3R1_FB18_Pos                    (18U)
8037 #define CAN_F3R1_FB18_Msk                    (0x1UL << CAN_F3R1_FB18_Pos)       /*!< 0x00040000 */
8038 #define CAN_F3R1_FB18                        CAN_F3R1_FB18_Msk                 /*!< Filter bit 18 */
8039 #define CAN_F3R1_FB19_Pos                    (19U)
8040 #define CAN_F3R1_FB19_Msk                    (0x1UL << CAN_F3R1_FB19_Pos)       /*!< 0x00080000 */
8041 #define CAN_F3R1_FB19                        CAN_F3R1_FB19_Msk                 /*!< Filter bit 19 */
8042 #define CAN_F3R1_FB20_Pos                    (20U)
8043 #define CAN_F3R1_FB20_Msk                    (0x1UL << CAN_F3R1_FB20_Pos)       /*!< 0x00100000 */
8044 #define CAN_F3R1_FB20                        CAN_F3R1_FB20_Msk                 /*!< Filter bit 20 */
8045 #define CAN_F3R1_FB21_Pos                    (21U)
8046 #define CAN_F3R1_FB21_Msk                    (0x1UL << CAN_F3R1_FB21_Pos)       /*!< 0x00200000 */
8047 #define CAN_F3R1_FB21                        CAN_F3R1_FB21_Msk                 /*!< Filter bit 21 */
8048 #define CAN_F3R1_FB22_Pos                    (22U)
8049 #define CAN_F3R1_FB22_Msk                    (0x1UL << CAN_F3R1_FB22_Pos)       /*!< 0x00400000 */
8050 #define CAN_F3R1_FB22                        CAN_F3R1_FB22_Msk                 /*!< Filter bit 22 */
8051 #define CAN_F3R1_FB23_Pos                    (23U)
8052 #define CAN_F3R1_FB23_Msk                    (0x1UL << CAN_F3R1_FB23_Pos)       /*!< 0x00800000 */
8053 #define CAN_F3R1_FB23                        CAN_F3R1_FB23_Msk                 /*!< Filter bit 23 */
8054 #define CAN_F3R1_FB24_Pos                    (24U)
8055 #define CAN_F3R1_FB24_Msk                    (0x1UL << CAN_F3R1_FB24_Pos)       /*!< 0x01000000 */
8056 #define CAN_F3R1_FB24                        CAN_F3R1_FB24_Msk                 /*!< Filter bit 24 */
8057 #define CAN_F3R1_FB25_Pos                    (25U)
8058 #define CAN_F3R1_FB25_Msk                    (0x1UL << CAN_F3R1_FB25_Pos)       /*!< 0x02000000 */
8059 #define CAN_F3R1_FB25                        CAN_F3R1_FB25_Msk                 /*!< Filter bit 25 */
8060 #define CAN_F3R1_FB26_Pos                    (26U)
8061 #define CAN_F3R1_FB26_Msk                    (0x1UL << CAN_F3R1_FB26_Pos)       /*!< 0x04000000 */
8062 #define CAN_F3R1_FB26                        CAN_F3R1_FB26_Msk                 /*!< Filter bit 26 */
8063 #define CAN_F3R1_FB27_Pos                    (27U)
8064 #define CAN_F3R1_FB27_Msk                    (0x1UL << CAN_F3R1_FB27_Pos)       /*!< 0x08000000 */
8065 #define CAN_F3R1_FB27                        CAN_F3R1_FB27_Msk                 /*!< Filter bit 27 */
8066 #define CAN_F3R1_FB28_Pos                    (28U)
8067 #define CAN_F3R1_FB28_Msk                    (0x1UL << CAN_F3R1_FB28_Pos)       /*!< 0x10000000 */
8068 #define CAN_F3R1_FB28                        CAN_F3R1_FB28_Msk                 /*!< Filter bit 28 */
8069 #define CAN_F3R1_FB29_Pos                    (29U)
8070 #define CAN_F3R1_FB29_Msk                    (0x1UL << CAN_F3R1_FB29_Pos)       /*!< 0x20000000 */
8071 #define CAN_F3R1_FB29                        CAN_F3R1_FB29_Msk                 /*!< Filter bit 29 */
8072 #define CAN_F3R1_FB30_Pos                    (30U)
8073 #define CAN_F3R1_FB30_Msk                    (0x1UL << CAN_F3R1_FB30_Pos)       /*!< 0x40000000 */
8074 #define CAN_F3R1_FB30                        CAN_F3R1_FB30_Msk                 /*!< Filter bit 30 */
8075 #define CAN_F3R1_FB31_Pos                    (31U)
8076 #define CAN_F3R1_FB31_Msk                    (0x1UL << CAN_F3R1_FB31_Pos)       /*!< 0x80000000 */
8077 #define CAN_F3R1_FB31                        CAN_F3R1_FB31_Msk                 /*!< Filter bit 31 */
8078 
8079 /*******************  Bit definition for CAN_F4R1 register  *******************/
8080 #define CAN_F4R1_FB0_Pos                     (0U)
8081 #define CAN_F4R1_FB0_Msk                     (0x1UL << CAN_F4R1_FB0_Pos)        /*!< 0x00000001 */
8082 #define CAN_F4R1_FB0                         CAN_F4R1_FB0_Msk                  /*!< Filter bit 0 */
8083 #define CAN_F4R1_FB1_Pos                     (1U)
8084 #define CAN_F4R1_FB1_Msk                     (0x1UL << CAN_F4R1_FB1_Pos)        /*!< 0x00000002 */
8085 #define CAN_F4R1_FB1                         CAN_F4R1_FB1_Msk                  /*!< Filter bit 1 */
8086 #define CAN_F4R1_FB2_Pos                     (2U)
8087 #define CAN_F4R1_FB2_Msk                     (0x1UL << CAN_F4R1_FB2_Pos)        /*!< 0x00000004 */
8088 #define CAN_F4R1_FB2                         CAN_F4R1_FB2_Msk                  /*!< Filter bit 2 */
8089 #define CAN_F4R1_FB3_Pos                     (3U)
8090 #define CAN_F4R1_FB3_Msk                     (0x1UL << CAN_F4R1_FB3_Pos)        /*!< 0x00000008 */
8091 #define CAN_F4R1_FB3                         CAN_F4R1_FB3_Msk                  /*!< Filter bit 3 */
8092 #define CAN_F4R1_FB4_Pos                     (4U)
8093 #define CAN_F4R1_FB4_Msk                     (0x1UL << CAN_F4R1_FB4_Pos)        /*!< 0x00000010 */
8094 #define CAN_F4R1_FB4                         CAN_F4R1_FB4_Msk                  /*!< Filter bit 4 */
8095 #define CAN_F4R1_FB5_Pos                     (5U)
8096 #define CAN_F4R1_FB5_Msk                     (0x1UL << CAN_F4R1_FB5_Pos)        /*!< 0x00000020 */
8097 #define CAN_F4R1_FB5                         CAN_F4R1_FB5_Msk                  /*!< Filter bit 5 */
8098 #define CAN_F4R1_FB6_Pos                     (6U)
8099 #define CAN_F4R1_FB6_Msk                     (0x1UL << CAN_F4R1_FB6_Pos)        /*!< 0x00000040 */
8100 #define CAN_F4R1_FB6                         CAN_F4R1_FB6_Msk                  /*!< Filter bit 6 */
8101 #define CAN_F4R1_FB7_Pos                     (7U)
8102 #define CAN_F4R1_FB7_Msk                     (0x1UL << CAN_F4R1_FB7_Pos)        /*!< 0x00000080 */
8103 #define CAN_F4R1_FB7                         CAN_F4R1_FB7_Msk                  /*!< Filter bit 7 */
8104 #define CAN_F4R1_FB8_Pos                     (8U)
8105 #define CAN_F4R1_FB8_Msk                     (0x1UL << CAN_F4R1_FB8_Pos)        /*!< 0x00000100 */
8106 #define CAN_F4R1_FB8                         CAN_F4R1_FB8_Msk                  /*!< Filter bit 8 */
8107 #define CAN_F4R1_FB9_Pos                     (9U)
8108 #define CAN_F4R1_FB9_Msk                     (0x1UL << CAN_F4R1_FB9_Pos)        /*!< 0x00000200 */
8109 #define CAN_F4R1_FB9                         CAN_F4R1_FB9_Msk                  /*!< Filter bit 9 */
8110 #define CAN_F4R1_FB10_Pos                    (10U)
8111 #define CAN_F4R1_FB10_Msk                    (0x1UL << CAN_F4R1_FB10_Pos)       /*!< 0x00000400 */
8112 #define CAN_F4R1_FB10                        CAN_F4R1_FB10_Msk                 /*!< Filter bit 10 */
8113 #define CAN_F4R1_FB11_Pos                    (11U)
8114 #define CAN_F4R1_FB11_Msk                    (0x1UL << CAN_F4R1_FB11_Pos)       /*!< 0x00000800 */
8115 #define CAN_F4R1_FB11                        CAN_F4R1_FB11_Msk                 /*!< Filter bit 11 */
8116 #define CAN_F4R1_FB12_Pos                    (12U)
8117 #define CAN_F4R1_FB12_Msk                    (0x1UL << CAN_F4R1_FB12_Pos)       /*!< 0x00001000 */
8118 #define CAN_F4R1_FB12                        CAN_F4R1_FB12_Msk                 /*!< Filter bit 12 */
8119 #define CAN_F4R1_FB13_Pos                    (13U)
8120 #define CAN_F4R1_FB13_Msk                    (0x1UL << CAN_F4R1_FB13_Pos)       /*!< 0x00002000 */
8121 #define CAN_F4R1_FB13                        CAN_F4R1_FB13_Msk                 /*!< Filter bit 13 */
8122 #define CAN_F4R1_FB14_Pos                    (14U)
8123 #define CAN_F4R1_FB14_Msk                    (0x1UL << CAN_F4R1_FB14_Pos)       /*!< 0x00004000 */
8124 #define CAN_F4R1_FB14                        CAN_F4R1_FB14_Msk                 /*!< Filter bit 14 */
8125 #define CAN_F4R1_FB15_Pos                    (15U)
8126 #define CAN_F4R1_FB15_Msk                    (0x1UL << CAN_F4R1_FB15_Pos)       /*!< 0x00008000 */
8127 #define CAN_F4R1_FB15                        CAN_F4R1_FB15_Msk                 /*!< Filter bit 15 */
8128 #define CAN_F4R1_FB16_Pos                    (16U)
8129 #define CAN_F4R1_FB16_Msk                    (0x1UL << CAN_F4R1_FB16_Pos)       /*!< 0x00010000 */
8130 #define CAN_F4R1_FB16                        CAN_F4R1_FB16_Msk                 /*!< Filter bit 16 */
8131 #define CAN_F4R1_FB17_Pos                    (17U)
8132 #define CAN_F4R1_FB17_Msk                    (0x1UL << CAN_F4R1_FB17_Pos)       /*!< 0x00020000 */
8133 #define CAN_F4R1_FB17                        CAN_F4R1_FB17_Msk                 /*!< Filter bit 17 */
8134 #define CAN_F4R1_FB18_Pos                    (18U)
8135 #define CAN_F4R1_FB18_Msk                    (0x1UL << CAN_F4R1_FB18_Pos)       /*!< 0x00040000 */
8136 #define CAN_F4R1_FB18                        CAN_F4R1_FB18_Msk                 /*!< Filter bit 18 */
8137 #define CAN_F4R1_FB19_Pos                    (19U)
8138 #define CAN_F4R1_FB19_Msk                    (0x1UL << CAN_F4R1_FB19_Pos)       /*!< 0x00080000 */
8139 #define CAN_F4R1_FB19                        CAN_F4R1_FB19_Msk                 /*!< Filter bit 19 */
8140 #define CAN_F4R1_FB20_Pos                    (20U)
8141 #define CAN_F4R1_FB20_Msk                    (0x1UL << CAN_F4R1_FB20_Pos)       /*!< 0x00100000 */
8142 #define CAN_F4R1_FB20                        CAN_F4R1_FB20_Msk                 /*!< Filter bit 20 */
8143 #define CAN_F4R1_FB21_Pos                    (21U)
8144 #define CAN_F4R1_FB21_Msk                    (0x1UL << CAN_F4R1_FB21_Pos)       /*!< 0x00200000 */
8145 #define CAN_F4R1_FB21                        CAN_F4R1_FB21_Msk                 /*!< Filter bit 21 */
8146 #define CAN_F4R1_FB22_Pos                    (22U)
8147 #define CAN_F4R1_FB22_Msk                    (0x1UL << CAN_F4R1_FB22_Pos)       /*!< 0x00400000 */
8148 #define CAN_F4R1_FB22                        CAN_F4R1_FB22_Msk                 /*!< Filter bit 22 */
8149 #define CAN_F4R1_FB23_Pos                    (23U)
8150 #define CAN_F4R1_FB23_Msk                    (0x1UL << CAN_F4R1_FB23_Pos)       /*!< 0x00800000 */
8151 #define CAN_F4R1_FB23                        CAN_F4R1_FB23_Msk                 /*!< Filter bit 23 */
8152 #define CAN_F4R1_FB24_Pos                    (24U)
8153 #define CAN_F4R1_FB24_Msk                    (0x1UL << CAN_F4R1_FB24_Pos)       /*!< 0x01000000 */
8154 #define CAN_F4R1_FB24                        CAN_F4R1_FB24_Msk                 /*!< Filter bit 24 */
8155 #define CAN_F4R1_FB25_Pos                    (25U)
8156 #define CAN_F4R1_FB25_Msk                    (0x1UL << CAN_F4R1_FB25_Pos)       /*!< 0x02000000 */
8157 #define CAN_F4R1_FB25                        CAN_F4R1_FB25_Msk                 /*!< Filter bit 25 */
8158 #define CAN_F4R1_FB26_Pos                    (26U)
8159 #define CAN_F4R1_FB26_Msk                    (0x1UL << CAN_F4R1_FB26_Pos)       /*!< 0x04000000 */
8160 #define CAN_F4R1_FB26                        CAN_F4R1_FB26_Msk                 /*!< Filter bit 26 */
8161 #define CAN_F4R1_FB27_Pos                    (27U)
8162 #define CAN_F4R1_FB27_Msk                    (0x1UL << CAN_F4R1_FB27_Pos)       /*!< 0x08000000 */
8163 #define CAN_F4R1_FB27                        CAN_F4R1_FB27_Msk                 /*!< Filter bit 27 */
8164 #define CAN_F4R1_FB28_Pos                    (28U)
8165 #define CAN_F4R1_FB28_Msk                    (0x1UL << CAN_F4R1_FB28_Pos)       /*!< 0x10000000 */
8166 #define CAN_F4R1_FB28                        CAN_F4R1_FB28_Msk                 /*!< Filter bit 28 */
8167 #define CAN_F4R1_FB29_Pos                    (29U)
8168 #define CAN_F4R1_FB29_Msk                    (0x1UL << CAN_F4R1_FB29_Pos)       /*!< 0x20000000 */
8169 #define CAN_F4R1_FB29                        CAN_F4R1_FB29_Msk                 /*!< Filter bit 29 */
8170 #define CAN_F4R1_FB30_Pos                    (30U)
8171 #define CAN_F4R1_FB30_Msk                    (0x1UL << CAN_F4R1_FB30_Pos)       /*!< 0x40000000 */
8172 #define CAN_F4R1_FB30                        CAN_F4R1_FB30_Msk                 /*!< Filter bit 30 */
8173 #define CAN_F4R1_FB31_Pos                    (31U)
8174 #define CAN_F4R1_FB31_Msk                    (0x1UL << CAN_F4R1_FB31_Pos)       /*!< 0x80000000 */
8175 #define CAN_F4R1_FB31                        CAN_F4R1_FB31_Msk                 /*!< Filter bit 31 */
8176 
8177 /*******************  Bit definition for CAN_F5R1 register  *******************/
8178 #define CAN_F5R1_FB0_Pos                     (0U)
8179 #define CAN_F5R1_FB0_Msk                     (0x1UL << CAN_F5R1_FB0_Pos)        /*!< 0x00000001 */
8180 #define CAN_F5R1_FB0                         CAN_F5R1_FB0_Msk                  /*!< Filter bit 0 */
8181 #define CAN_F5R1_FB1_Pos                     (1U)
8182 #define CAN_F5R1_FB1_Msk                     (0x1UL << CAN_F5R1_FB1_Pos)        /*!< 0x00000002 */
8183 #define CAN_F5R1_FB1                         CAN_F5R1_FB1_Msk                  /*!< Filter bit 1 */
8184 #define CAN_F5R1_FB2_Pos                     (2U)
8185 #define CAN_F5R1_FB2_Msk                     (0x1UL << CAN_F5R1_FB2_Pos)        /*!< 0x00000004 */
8186 #define CAN_F5R1_FB2                         CAN_F5R1_FB2_Msk                  /*!< Filter bit 2 */
8187 #define CAN_F5R1_FB3_Pos                     (3U)
8188 #define CAN_F5R1_FB3_Msk                     (0x1UL << CAN_F5R1_FB3_Pos)        /*!< 0x00000008 */
8189 #define CAN_F5R1_FB3                         CAN_F5R1_FB3_Msk                  /*!< Filter bit 3 */
8190 #define CAN_F5R1_FB4_Pos                     (4U)
8191 #define CAN_F5R1_FB4_Msk                     (0x1UL << CAN_F5R1_FB4_Pos)        /*!< 0x00000010 */
8192 #define CAN_F5R1_FB4                         CAN_F5R1_FB4_Msk                  /*!< Filter bit 4 */
8193 #define CAN_F5R1_FB5_Pos                     (5U)
8194 #define CAN_F5R1_FB5_Msk                     (0x1UL << CAN_F5R1_FB5_Pos)        /*!< 0x00000020 */
8195 #define CAN_F5R1_FB5                         CAN_F5R1_FB5_Msk                  /*!< Filter bit 5 */
8196 #define CAN_F5R1_FB6_Pos                     (6U)
8197 #define CAN_F5R1_FB6_Msk                     (0x1UL << CAN_F5R1_FB6_Pos)        /*!< 0x00000040 */
8198 #define CAN_F5R1_FB6                         CAN_F5R1_FB6_Msk                  /*!< Filter bit 6 */
8199 #define CAN_F5R1_FB7_Pos                     (7U)
8200 #define CAN_F5R1_FB7_Msk                     (0x1UL << CAN_F5R1_FB7_Pos)        /*!< 0x00000080 */
8201 #define CAN_F5R1_FB7                         CAN_F5R1_FB7_Msk                  /*!< Filter bit 7 */
8202 #define CAN_F5R1_FB8_Pos                     (8U)
8203 #define CAN_F5R1_FB8_Msk                     (0x1UL << CAN_F5R1_FB8_Pos)        /*!< 0x00000100 */
8204 #define CAN_F5R1_FB8                         CAN_F5R1_FB8_Msk                  /*!< Filter bit 8 */
8205 #define CAN_F5R1_FB9_Pos                     (9U)
8206 #define CAN_F5R1_FB9_Msk                     (0x1UL << CAN_F5R1_FB9_Pos)        /*!< 0x00000200 */
8207 #define CAN_F5R1_FB9                         CAN_F5R1_FB9_Msk                  /*!< Filter bit 9 */
8208 #define CAN_F5R1_FB10_Pos                    (10U)
8209 #define CAN_F5R1_FB10_Msk                    (0x1UL << CAN_F5R1_FB10_Pos)       /*!< 0x00000400 */
8210 #define CAN_F5R1_FB10                        CAN_F5R1_FB10_Msk                 /*!< Filter bit 10 */
8211 #define CAN_F5R1_FB11_Pos                    (11U)
8212 #define CAN_F5R1_FB11_Msk                    (0x1UL << CAN_F5R1_FB11_Pos)       /*!< 0x00000800 */
8213 #define CAN_F5R1_FB11                        CAN_F5R1_FB11_Msk                 /*!< Filter bit 11 */
8214 #define CAN_F5R1_FB12_Pos                    (12U)
8215 #define CAN_F5R1_FB12_Msk                    (0x1UL << CAN_F5R1_FB12_Pos)       /*!< 0x00001000 */
8216 #define CAN_F5R1_FB12                        CAN_F5R1_FB12_Msk                 /*!< Filter bit 12 */
8217 #define CAN_F5R1_FB13_Pos                    (13U)
8218 #define CAN_F5R1_FB13_Msk                    (0x1UL << CAN_F5R1_FB13_Pos)       /*!< 0x00002000 */
8219 #define CAN_F5R1_FB13                        CAN_F5R1_FB13_Msk                 /*!< Filter bit 13 */
8220 #define CAN_F5R1_FB14_Pos                    (14U)
8221 #define CAN_F5R1_FB14_Msk                    (0x1UL << CAN_F5R1_FB14_Pos)       /*!< 0x00004000 */
8222 #define CAN_F5R1_FB14                        CAN_F5R1_FB14_Msk                 /*!< Filter bit 14 */
8223 #define CAN_F5R1_FB15_Pos                    (15U)
8224 #define CAN_F5R1_FB15_Msk                    (0x1UL << CAN_F5R1_FB15_Pos)       /*!< 0x00008000 */
8225 #define CAN_F5R1_FB15                        CAN_F5R1_FB15_Msk                 /*!< Filter bit 15 */
8226 #define CAN_F5R1_FB16_Pos                    (16U)
8227 #define CAN_F5R1_FB16_Msk                    (0x1UL << CAN_F5R1_FB16_Pos)       /*!< 0x00010000 */
8228 #define CAN_F5R1_FB16                        CAN_F5R1_FB16_Msk                 /*!< Filter bit 16 */
8229 #define CAN_F5R1_FB17_Pos                    (17U)
8230 #define CAN_F5R1_FB17_Msk                    (0x1UL << CAN_F5R1_FB17_Pos)       /*!< 0x00020000 */
8231 #define CAN_F5R1_FB17                        CAN_F5R1_FB17_Msk                 /*!< Filter bit 17 */
8232 #define CAN_F5R1_FB18_Pos                    (18U)
8233 #define CAN_F5R1_FB18_Msk                    (0x1UL << CAN_F5R1_FB18_Pos)       /*!< 0x00040000 */
8234 #define CAN_F5R1_FB18                        CAN_F5R1_FB18_Msk                 /*!< Filter bit 18 */
8235 #define CAN_F5R1_FB19_Pos                    (19U)
8236 #define CAN_F5R1_FB19_Msk                    (0x1UL << CAN_F5R1_FB19_Pos)       /*!< 0x00080000 */
8237 #define CAN_F5R1_FB19                        CAN_F5R1_FB19_Msk                 /*!< Filter bit 19 */
8238 #define CAN_F5R1_FB20_Pos                    (20U)
8239 #define CAN_F5R1_FB20_Msk                    (0x1UL << CAN_F5R1_FB20_Pos)       /*!< 0x00100000 */
8240 #define CAN_F5R1_FB20                        CAN_F5R1_FB20_Msk                 /*!< Filter bit 20 */
8241 #define CAN_F5R1_FB21_Pos                    (21U)
8242 #define CAN_F5R1_FB21_Msk                    (0x1UL << CAN_F5R1_FB21_Pos)       /*!< 0x00200000 */
8243 #define CAN_F5R1_FB21                        CAN_F5R1_FB21_Msk                 /*!< Filter bit 21 */
8244 #define CAN_F5R1_FB22_Pos                    (22U)
8245 #define CAN_F5R1_FB22_Msk                    (0x1UL << CAN_F5R1_FB22_Pos)       /*!< 0x00400000 */
8246 #define CAN_F5R1_FB22                        CAN_F5R1_FB22_Msk                 /*!< Filter bit 22 */
8247 #define CAN_F5R1_FB23_Pos                    (23U)
8248 #define CAN_F5R1_FB23_Msk                    (0x1UL << CAN_F5R1_FB23_Pos)       /*!< 0x00800000 */
8249 #define CAN_F5R1_FB23                        CAN_F5R1_FB23_Msk                 /*!< Filter bit 23 */
8250 #define CAN_F5R1_FB24_Pos                    (24U)
8251 #define CAN_F5R1_FB24_Msk                    (0x1UL << CAN_F5R1_FB24_Pos)       /*!< 0x01000000 */
8252 #define CAN_F5R1_FB24                        CAN_F5R1_FB24_Msk                 /*!< Filter bit 24 */
8253 #define CAN_F5R1_FB25_Pos                    (25U)
8254 #define CAN_F5R1_FB25_Msk                    (0x1UL << CAN_F5R1_FB25_Pos)       /*!< 0x02000000 */
8255 #define CAN_F5R1_FB25                        CAN_F5R1_FB25_Msk                 /*!< Filter bit 25 */
8256 #define CAN_F5R1_FB26_Pos                    (26U)
8257 #define CAN_F5R1_FB26_Msk                    (0x1UL << CAN_F5R1_FB26_Pos)       /*!< 0x04000000 */
8258 #define CAN_F5R1_FB26                        CAN_F5R1_FB26_Msk                 /*!< Filter bit 26 */
8259 #define CAN_F5R1_FB27_Pos                    (27U)
8260 #define CAN_F5R1_FB27_Msk                    (0x1UL << CAN_F5R1_FB27_Pos)       /*!< 0x08000000 */
8261 #define CAN_F5R1_FB27                        CAN_F5R1_FB27_Msk                 /*!< Filter bit 27 */
8262 #define CAN_F5R1_FB28_Pos                    (28U)
8263 #define CAN_F5R1_FB28_Msk                    (0x1UL << CAN_F5R1_FB28_Pos)       /*!< 0x10000000 */
8264 #define CAN_F5R1_FB28                        CAN_F5R1_FB28_Msk                 /*!< Filter bit 28 */
8265 #define CAN_F5R1_FB29_Pos                    (29U)
8266 #define CAN_F5R1_FB29_Msk                    (0x1UL << CAN_F5R1_FB29_Pos)       /*!< 0x20000000 */
8267 #define CAN_F5R1_FB29                        CAN_F5R1_FB29_Msk                 /*!< Filter bit 29 */
8268 #define CAN_F5R1_FB30_Pos                    (30U)
8269 #define CAN_F5R1_FB30_Msk                    (0x1UL << CAN_F5R1_FB30_Pos)       /*!< 0x40000000 */
8270 #define CAN_F5R1_FB30                        CAN_F5R1_FB30_Msk                 /*!< Filter bit 30 */
8271 #define CAN_F5R1_FB31_Pos                    (31U)
8272 #define CAN_F5R1_FB31_Msk                    (0x1UL << CAN_F5R1_FB31_Pos)       /*!< 0x80000000 */
8273 #define CAN_F5R1_FB31                        CAN_F5R1_FB31_Msk                 /*!< Filter bit 31 */
8274 
8275 /*******************  Bit definition for CAN_F6R1 register  *******************/
8276 #define CAN_F6R1_FB0_Pos                     (0U)
8277 #define CAN_F6R1_FB0_Msk                     (0x1UL << CAN_F6R1_FB0_Pos)        /*!< 0x00000001 */
8278 #define CAN_F6R1_FB0                         CAN_F6R1_FB0_Msk                  /*!< Filter bit 0 */
8279 #define CAN_F6R1_FB1_Pos                     (1U)
8280 #define CAN_F6R1_FB1_Msk                     (0x1UL << CAN_F6R1_FB1_Pos)        /*!< 0x00000002 */
8281 #define CAN_F6R1_FB1                         CAN_F6R1_FB1_Msk                  /*!< Filter bit 1 */
8282 #define CAN_F6R1_FB2_Pos                     (2U)
8283 #define CAN_F6R1_FB2_Msk                     (0x1UL << CAN_F6R1_FB2_Pos)        /*!< 0x00000004 */
8284 #define CAN_F6R1_FB2                         CAN_F6R1_FB2_Msk                  /*!< Filter bit 2 */
8285 #define CAN_F6R1_FB3_Pos                     (3U)
8286 #define CAN_F6R1_FB3_Msk                     (0x1UL << CAN_F6R1_FB3_Pos)        /*!< 0x00000008 */
8287 #define CAN_F6R1_FB3                         CAN_F6R1_FB3_Msk                  /*!< Filter bit 3 */
8288 #define CAN_F6R1_FB4_Pos                     (4U)
8289 #define CAN_F6R1_FB4_Msk                     (0x1UL << CAN_F6R1_FB4_Pos)        /*!< 0x00000010 */
8290 #define CAN_F6R1_FB4                         CAN_F6R1_FB4_Msk                  /*!< Filter bit 4 */
8291 #define CAN_F6R1_FB5_Pos                     (5U)
8292 #define CAN_F6R1_FB5_Msk                     (0x1UL << CAN_F6R1_FB5_Pos)        /*!< 0x00000020 */
8293 #define CAN_F6R1_FB5                         CAN_F6R1_FB5_Msk                  /*!< Filter bit 5 */
8294 #define CAN_F6R1_FB6_Pos                     (6U)
8295 #define CAN_F6R1_FB6_Msk                     (0x1UL << CAN_F6R1_FB6_Pos)        /*!< 0x00000040 */
8296 #define CAN_F6R1_FB6                         CAN_F6R1_FB6_Msk                  /*!< Filter bit 6 */
8297 #define CAN_F6R1_FB7_Pos                     (7U)
8298 #define CAN_F6R1_FB7_Msk                     (0x1UL << CAN_F6R1_FB7_Pos)        /*!< 0x00000080 */
8299 #define CAN_F6R1_FB7                         CAN_F6R1_FB7_Msk                  /*!< Filter bit 7 */
8300 #define CAN_F6R1_FB8_Pos                     (8U)
8301 #define CAN_F6R1_FB8_Msk                     (0x1UL << CAN_F6R1_FB8_Pos)        /*!< 0x00000100 */
8302 #define CAN_F6R1_FB8                         CAN_F6R1_FB8_Msk                  /*!< Filter bit 8 */
8303 #define CAN_F6R1_FB9_Pos                     (9U)
8304 #define CAN_F6R1_FB9_Msk                     (0x1UL << CAN_F6R1_FB9_Pos)        /*!< 0x00000200 */
8305 #define CAN_F6R1_FB9                         CAN_F6R1_FB9_Msk                  /*!< Filter bit 9 */
8306 #define CAN_F6R1_FB10_Pos                    (10U)
8307 #define CAN_F6R1_FB10_Msk                    (0x1UL << CAN_F6R1_FB10_Pos)       /*!< 0x00000400 */
8308 #define CAN_F6R1_FB10                        CAN_F6R1_FB10_Msk                 /*!< Filter bit 10 */
8309 #define CAN_F6R1_FB11_Pos                    (11U)
8310 #define CAN_F6R1_FB11_Msk                    (0x1UL << CAN_F6R1_FB11_Pos)       /*!< 0x00000800 */
8311 #define CAN_F6R1_FB11                        CAN_F6R1_FB11_Msk                 /*!< Filter bit 11 */
8312 #define CAN_F6R1_FB12_Pos                    (12U)
8313 #define CAN_F6R1_FB12_Msk                    (0x1UL << CAN_F6R1_FB12_Pos)       /*!< 0x00001000 */
8314 #define CAN_F6R1_FB12                        CAN_F6R1_FB12_Msk                 /*!< Filter bit 12 */
8315 #define CAN_F6R1_FB13_Pos                    (13U)
8316 #define CAN_F6R1_FB13_Msk                    (0x1UL << CAN_F6R1_FB13_Pos)       /*!< 0x00002000 */
8317 #define CAN_F6R1_FB13                        CAN_F6R1_FB13_Msk                 /*!< Filter bit 13 */
8318 #define CAN_F6R1_FB14_Pos                    (14U)
8319 #define CAN_F6R1_FB14_Msk                    (0x1UL << CAN_F6R1_FB14_Pos)       /*!< 0x00004000 */
8320 #define CAN_F6R1_FB14                        CAN_F6R1_FB14_Msk                 /*!< Filter bit 14 */
8321 #define CAN_F6R1_FB15_Pos                    (15U)
8322 #define CAN_F6R1_FB15_Msk                    (0x1UL << CAN_F6R1_FB15_Pos)       /*!< 0x00008000 */
8323 #define CAN_F6R1_FB15                        CAN_F6R1_FB15_Msk                 /*!< Filter bit 15 */
8324 #define CAN_F6R1_FB16_Pos                    (16U)
8325 #define CAN_F6R1_FB16_Msk                    (0x1UL << CAN_F6R1_FB16_Pos)       /*!< 0x00010000 */
8326 #define CAN_F6R1_FB16                        CAN_F6R1_FB16_Msk                 /*!< Filter bit 16 */
8327 #define CAN_F6R1_FB17_Pos                    (17U)
8328 #define CAN_F6R1_FB17_Msk                    (0x1UL << CAN_F6R1_FB17_Pos)       /*!< 0x00020000 */
8329 #define CAN_F6R1_FB17                        CAN_F6R1_FB17_Msk                 /*!< Filter bit 17 */
8330 #define CAN_F6R1_FB18_Pos                    (18U)
8331 #define CAN_F6R1_FB18_Msk                    (0x1UL << CAN_F6R1_FB18_Pos)       /*!< 0x00040000 */
8332 #define CAN_F6R1_FB18                        CAN_F6R1_FB18_Msk                 /*!< Filter bit 18 */
8333 #define CAN_F6R1_FB19_Pos                    (19U)
8334 #define CAN_F6R1_FB19_Msk                    (0x1UL << CAN_F6R1_FB19_Pos)       /*!< 0x00080000 */
8335 #define CAN_F6R1_FB19                        CAN_F6R1_FB19_Msk                 /*!< Filter bit 19 */
8336 #define CAN_F6R1_FB20_Pos                    (20U)
8337 #define CAN_F6R1_FB20_Msk                    (0x1UL << CAN_F6R1_FB20_Pos)       /*!< 0x00100000 */
8338 #define CAN_F6R1_FB20                        CAN_F6R1_FB20_Msk                 /*!< Filter bit 20 */
8339 #define CAN_F6R1_FB21_Pos                    (21U)
8340 #define CAN_F6R1_FB21_Msk                    (0x1UL << CAN_F6R1_FB21_Pos)       /*!< 0x00200000 */
8341 #define CAN_F6R1_FB21                        CAN_F6R1_FB21_Msk                 /*!< Filter bit 21 */
8342 #define CAN_F6R1_FB22_Pos                    (22U)
8343 #define CAN_F6R1_FB22_Msk                    (0x1UL << CAN_F6R1_FB22_Pos)       /*!< 0x00400000 */
8344 #define CAN_F6R1_FB22                        CAN_F6R1_FB22_Msk                 /*!< Filter bit 22 */
8345 #define CAN_F6R1_FB23_Pos                    (23U)
8346 #define CAN_F6R1_FB23_Msk                    (0x1UL << CAN_F6R1_FB23_Pos)       /*!< 0x00800000 */
8347 #define CAN_F6R1_FB23                        CAN_F6R1_FB23_Msk                 /*!< Filter bit 23 */
8348 #define CAN_F6R1_FB24_Pos                    (24U)
8349 #define CAN_F6R1_FB24_Msk                    (0x1UL << CAN_F6R1_FB24_Pos)       /*!< 0x01000000 */
8350 #define CAN_F6R1_FB24                        CAN_F6R1_FB24_Msk                 /*!< Filter bit 24 */
8351 #define CAN_F6R1_FB25_Pos                    (25U)
8352 #define CAN_F6R1_FB25_Msk                    (0x1UL << CAN_F6R1_FB25_Pos)       /*!< 0x02000000 */
8353 #define CAN_F6R1_FB25                        CAN_F6R1_FB25_Msk                 /*!< Filter bit 25 */
8354 #define CAN_F6R1_FB26_Pos                    (26U)
8355 #define CAN_F6R1_FB26_Msk                    (0x1UL << CAN_F6R1_FB26_Pos)       /*!< 0x04000000 */
8356 #define CAN_F6R1_FB26                        CAN_F6R1_FB26_Msk                 /*!< Filter bit 26 */
8357 #define CAN_F6R1_FB27_Pos                    (27U)
8358 #define CAN_F6R1_FB27_Msk                    (0x1UL << CAN_F6R1_FB27_Pos)       /*!< 0x08000000 */
8359 #define CAN_F6R1_FB27                        CAN_F6R1_FB27_Msk                 /*!< Filter bit 27 */
8360 #define CAN_F6R1_FB28_Pos                    (28U)
8361 #define CAN_F6R1_FB28_Msk                    (0x1UL << CAN_F6R1_FB28_Pos)       /*!< 0x10000000 */
8362 #define CAN_F6R1_FB28                        CAN_F6R1_FB28_Msk                 /*!< Filter bit 28 */
8363 #define CAN_F6R1_FB29_Pos                    (29U)
8364 #define CAN_F6R1_FB29_Msk                    (0x1UL << CAN_F6R1_FB29_Pos)       /*!< 0x20000000 */
8365 #define CAN_F6R1_FB29                        CAN_F6R1_FB29_Msk                 /*!< Filter bit 29 */
8366 #define CAN_F6R1_FB30_Pos                    (30U)
8367 #define CAN_F6R1_FB30_Msk                    (0x1UL << CAN_F6R1_FB30_Pos)       /*!< 0x40000000 */
8368 #define CAN_F6R1_FB30                        CAN_F6R1_FB30_Msk                 /*!< Filter bit 30 */
8369 #define CAN_F6R1_FB31_Pos                    (31U)
8370 #define CAN_F6R1_FB31_Msk                    (0x1UL << CAN_F6R1_FB31_Pos)       /*!< 0x80000000 */
8371 #define CAN_F6R1_FB31                        CAN_F6R1_FB31_Msk                 /*!< Filter bit 31 */
8372 
8373 /*******************  Bit definition for CAN_F7R1 register  *******************/
8374 #define CAN_F7R1_FB0_Pos                     (0U)
8375 #define CAN_F7R1_FB0_Msk                     (0x1UL << CAN_F7R1_FB0_Pos)        /*!< 0x00000001 */
8376 #define CAN_F7R1_FB0                         CAN_F7R1_FB0_Msk                  /*!< Filter bit 0 */
8377 #define CAN_F7R1_FB1_Pos                     (1U)
8378 #define CAN_F7R1_FB1_Msk                     (0x1UL << CAN_F7R1_FB1_Pos)        /*!< 0x00000002 */
8379 #define CAN_F7R1_FB1                         CAN_F7R1_FB1_Msk                  /*!< Filter bit 1 */
8380 #define CAN_F7R1_FB2_Pos                     (2U)
8381 #define CAN_F7R1_FB2_Msk                     (0x1UL << CAN_F7R1_FB2_Pos)        /*!< 0x00000004 */
8382 #define CAN_F7R1_FB2                         CAN_F7R1_FB2_Msk                  /*!< Filter bit 2 */
8383 #define CAN_F7R1_FB3_Pos                     (3U)
8384 #define CAN_F7R1_FB3_Msk                     (0x1UL << CAN_F7R1_FB3_Pos)        /*!< 0x00000008 */
8385 #define CAN_F7R1_FB3                         CAN_F7R1_FB3_Msk                  /*!< Filter bit 3 */
8386 #define CAN_F7R1_FB4_Pos                     (4U)
8387 #define CAN_F7R1_FB4_Msk                     (0x1UL << CAN_F7R1_FB4_Pos)        /*!< 0x00000010 */
8388 #define CAN_F7R1_FB4                         CAN_F7R1_FB4_Msk                  /*!< Filter bit 4 */
8389 #define CAN_F7R1_FB5_Pos                     (5U)
8390 #define CAN_F7R1_FB5_Msk                     (0x1UL << CAN_F7R1_FB5_Pos)        /*!< 0x00000020 */
8391 #define CAN_F7R1_FB5                         CAN_F7R1_FB5_Msk                  /*!< Filter bit 5 */
8392 #define CAN_F7R1_FB6_Pos                     (6U)
8393 #define CAN_F7R1_FB6_Msk                     (0x1UL << CAN_F7R1_FB6_Pos)        /*!< 0x00000040 */
8394 #define CAN_F7R1_FB6                         CAN_F7R1_FB6_Msk                  /*!< Filter bit 6 */
8395 #define CAN_F7R1_FB7_Pos                     (7U)
8396 #define CAN_F7R1_FB7_Msk                     (0x1UL << CAN_F7R1_FB7_Pos)        /*!< 0x00000080 */
8397 #define CAN_F7R1_FB7                         CAN_F7R1_FB7_Msk                  /*!< Filter bit 7 */
8398 #define CAN_F7R1_FB8_Pos                     (8U)
8399 #define CAN_F7R1_FB8_Msk                     (0x1UL << CAN_F7R1_FB8_Pos)        /*!< 0x00000100 */
8400 #define CAN_F7R1_FB8                         CAN_F7R1_FB8_Msk                  /*!< Filter bit 8 */
8401 #define CAN_F7R1_FB9_Pos                     (9U)
8402 #define CAN_F7R1_FB9_Msk                     (0x1UL << CAN_F7R1_FB9_Pos)        /*!< 0x00000200 */
8403 #define CAN_F7R1_FB9                         CAN_F7R1_FB9_Msk                  /*!< Filter bit 9 */
8404 #define CAN_F7R1_FB10_Pos                    (10U)
8405 #define CAN_F7R1_FB10_Msk                    (0x1UL << CAN_F7R1_FB10_Pos)       /*!< 0x00000400 */
8406 #define CAN_F7R1_FB10                        CAN_F7R1_FB10_Msk                 /*!< Filter bit 10 */
8407 #define CAN_F7R1_FB11_Pos                    (11U)
8408 #define CAN_F7R1_FB11_Msk                    (0x1UL << CAN_F7R1_FB11_Pos)       /*!< 0x00000800 */
8409 #define CAN_F7R1_FB11                        CAN_F7R1_FB11_Msk                 /*!< Filter bit 11 */
8410 #define CAN_F7R1_FB12_Pos                    (12U)
8411 #define CAN_F7R1_FB12_Msk                    (0x1UL << CAN_F7R1_FB12_Pos)       /*!< 0x00001000 */
8412 #define CAN_F7R1_FB12                        CAN_F7R1_FB12_Msk                 /*!< Filter bit 12 */
8413 #define CAN_F7R1_FB13_Pos                    (13U)
8414 #define CAN_F7R1_FB13_Msk                    (0x1UL << CAN_F7R1_FB13_Pos)       /*!< 0x00002000 */
8415 #define CAN_F7R1_FB13                        CAN_F7R1_FB13_Msk                 /*!< Filter bit 13 */
8416 #define CAN_F7R1_FB14_Pos                    (14U)
8417 #define CAN_F7R1_FB14_Msk                    (0x1UL << CAN_F7R1_FB14_Pos)       /*!< 0x00004000 */
8418 #define CAN_F7R1_FB14                        CAN_F7R1_FB14_Msk                 /*!< Filter bit 14 */
8419 #define CAN_F7R1_FB15_Pos                    (15U)
8420 #define CAN_F7R1_FB15_Msk                    (0x1UL << CAN_F7R1_FB15_Pos)       /*!< 0x00008000 */
8421 #define CAN_F7R1_FB15                        CAN_F7R1_FB15_Msk                 /*!< Filter bit 15 */
8422 #define CAN_F7R1_FB16_Pos                    (16U)
8423 #define CAN_F7R1_FB16_Msk                    (0x1UL << CAN_F7R1_FB16_Pos)       /*!< 0x00010000 */
8424 #define CAN_F7R1_FB16                        CAN_F7R1_FB16_Msk                 /*!< Filter bit 16 */
8425 #define CAN_F7R1_FB17_Pos                    (17U)
8426 #define CAN_F7R1_FB17_Msk                    (0x1UL << CAN_F7R1_FB17_Pos)       /*!< 0x00020000 */
8427 #define CAN_F7R1_FB17                        CAN_F7R1_FB17_Msk                 /*!< Filter bit 17 */
8428 #define CAN_F7R1_FB18_Pos                    (18U)
8429 #define CAN_F7R1_FB18_Msk                    (0x1UL << CAN_F7R1_FB18_Pos)       /*!< 0x00040000 */
8430 #define CAN_F7R1_FB18                        CAN_F7R1_FB18_Msk                 /*!< Filter bit 18 */
8431 #define CAN_F7R1_FB19_Pos                    (19U)
8432 #define CAN_F7R1_FB19_Msk                    (0x1UL << CAN_F7R1_FB19_Pos)       /*!< 0x00080000 */
8433 #define CAN_F7R1_FB19                        CAN_F7R1_FB19_Msk                 /*!< Filter bit 19 */
8434 #define CAN_F7R1_FB20_Pos                    (20U)
8435 #define CAN_F7R1_FB20_Msk                    (0x1UL << CAN_F7R1_FB20_Pos)       /*!< 0x00100000 */
8436 #define CAN_F7R1_FB20                        CAN_F7R1_FB20_Msk                 /*!< Filter bit 20 */
8437 #define CAN_F7R1_FB21_Pos                    (21U)
8438 #define CAN_F7R1_FB21_Msk                    (0x1UL << CAN_F7R1_FB21_Pos)       /*!< 0x00200000 */
8439 #define CAN_F7R1_FB21                        CAN_F7R1_FB21_Msk                 /*!< Filter bit 21 */
8440 #define CAN_F7R1_FB22_Pos                    (22U)
8441 #define CAN_F7R1_FB22_Msk                    (0x1UL << CAN_F7R1_FB22_Pos)       /*!< 0x00400000 */
8442 #define CAN_F7R1_FB22                        CAN_F7R1_FB22_Msk                 /*!< Filter bit 22 */
8443 #define CAN_F7R1_FB23_Pos                    (23U)
8444 #define CAN_F7R1_FB23_Msk                    (0x1UL << CAN_F7R1_FB23_Pos)       /*!< 0x00800000 */
8445 #define CAN_F7R1_FB23                        CAN_F7R1_FB23_Msk                 /*!< Filter bit 23 */
8446 #define CAN_F7R1_FB24_Pos                    (24U)
8447 #define CAN_F7R1_FB24_Msk                    (0x1UL << CAN_F7R1_FB24_Pos)       /*!< 0x01000000 */
8448 #define CAN_F7R1_FB24                        CAN_F7R1_FB24_Msk                 /*!< Filter bit 24 */
8449 #define CAN_F7R1_FB25_Pos                    (25U)
8450 #define CAN_F7R1_FB25_Msk                    (0x1UL << CAN_F7R1_FB25_Pos)       /*!< 0x02000000 */
8451 #define CAN_F7R1_FB25                        CAN_F7R1_FB25_Msk                 /*!< Filter bit 25 */
8452 #define CAN_F7R1_FB26_Pos                    (26U)
8453 #define CAN_F7R1_FB26_Msk                    (0x1UL << CAN_F7R1_FB26_Pos)       /*!< 0x04000000 */
8454 #define CAN_F7R1_FB26                        CAN_F7R1_FB26_Msk                 /*!< Filter bit 26 */
8455 #define CAN_F7R1_FB27_Pos                    (27U)
8456 #define CAN_F7R1_FB27_Msk                    (0x1UL << CAN_F7R1_FB27_Pos)       /*!< 0x08000000 */
8457 #define CAN_F7R1_FB27                        CAN_F7R1_FB27_Msk                 /*!< Filter bit 27 */
8458 #define CAN_F7R1_FB28_Pos                    (28U)
8459 #define CAN_F7R1_FB28_Msk                    (0x1UL << CAN_F7R1_FB28_Pos)       /*!< 0x10000000 */
8460 #define CAN_F7R1_FB28                        CAN_F7R1_FB28_Msk                 /*!< Filter bit 28 */
8461 #define CAN_F7R1_FB29_Pos                    (29U)
8462 #define CAN_F7R1_FB29_Msk                    (0x1UL << CAN_F7R1_FB29_Pos)       /*!< 0x20000000 */
8463 #define CAN_F7R1_FB29                        CAN_F7R1_FB29_Msk                 /*!< Filter bit 29 */
8464 #define CAN_F7R1_FB30_Pos                    (30U)
8465 #define CAN_F7R1_FB30_Msk                    (0x1UL << CAN_F7R1_FB30_Pos)       /*!< 0x40000000 */
8466 #define CAN_F7R1_FB30                        CAN_F7R1_FB30_Msk                 /*!< Filter bit 30 */
8467 #define CAN_F7R1_FB31_Pos                    (31U)
8468 #define CAN_F7R1_FB31_Msk                    (0x1UL << CAN_F7R1_FB31_Pos)       /*!< 0x80000000 */
8469 #define CAN_F7R1_FB31                        CAN_F7R1_FB31_Msk                 /*!< Filter bit 31 */
8470 
8471 /*******************  Bit definition for CAN_F8R1 register  *******************/
8472 #define CAN_F8R1_FB0_Pos                     (0U)
8473 #define CAN_F8R1_FB0_Msk                     (0x1UL << CAN_F8R1_FB0_Pos)        /*!< 0x00000001 */
8474 #define CAN_F8R1_FB0                         CAN_F8R1_FB0_Msk                  /*!< Filter bit 0 */
8475 #define CAN_F8R1_FB1_Pos                     (1U)
8476 #define CAN_F8R1_FB1_Msk                     (0x1UL << CAN_F8R1_FB1_Pos)        /*!< 0x00000002 */
8477 #define CAN_F8R1_FB1                         CAN_F8R1_FB1_Msk                  /*!< Filter bit 1 */
8478 #define CAN_F8R1_FB2_Pos                     (2U)
8479 #define CAN_F8R1_FB2_Msk                     (0x1UL << CAN_F8R1_FB2_Pos)        /*!< 0x00000004 */
8480 #define CAN_F8R1_FB2                         CAN_F8R1_FB2_Msk                  /*!< Filter bit 2 */
8481 #define CAN_F8R1_FB3_Pos                     (3U)
8482 #define CAN_F8R1_FB3_Msk                     (0x1UL << CAN_F8R1_FB3_Pos)        /*!< 0x00000008 */
8483 #define CAN_F8R1_FB3                         CAN_F8R1_FB3_Msk                  /*!< Filter bit 3 */
8484 #define CAN_F8R1_FB4_Pos                     (4U)
8485 #define CAN_F8R1_FB4_Msk                     (0x1UL << CAN_F8R1_FB4_Pos)        /*!< 0x00000010 */
8486 #define CAN_F8R1_FB4                         CAN_F8R1_FB4_Msk                  /*!< Filter bit 4 */
8487 #define CAN_F8R1_FB5_Pos                     (5U)
8488 #define CAN_F8R1_FB5_Msk                     (0x1UL << CAN_F8R1_FB5_Pos)        /*!< 0x00000020 */
8489 #define CAN_F8R1_FB5                         CAN_F8R1_FB5_Msk                  /*!< Filter bit 5 */
8490 #define CAN_F8R1_FB6_Pos                     (6U)
8491 #define CAN_F8R1_FB6_Msk                     (0x1UL << CAN_F8R1_FB6_Pos)        /*!< 0x00000040 */
8492 #define CAN_F8R1_FB6                         CAN_F8R1_FB6_Msk                  /*!< Filter bit 6 */
8493 #define CAN_F8R1_FB7_Pos                     (7U)
8494 #define CAN_F8R1_FB7_Msk                     (0x1UL << CAN_F8R1_FB7_Pos)        /*!< 0x00000080 */
8495 #define CAN_F8R1_FB7                         CAN_F8R1_FB7_Msk                  /*!< Filter bit 7 */
8496 #define CAN_F8R1_FB8_Pos                     (8U)
8497 #define CAN_F8R1_FB8_Msk                     (0x1UL << CAN_F8R1_FB8_Pos)        /*!< 0x00000100 */
8498 #define CAN_F8R1_FB8                         CAN_F8R1_FB8_Msk                  /*!< Filter bit 8 */
8499 #define CAN_F8R1_FB9_Pos                     (9U)
8500 #define CAN_F8R1_FB9_Msk                     (0x1UL << CAN_F8R1_FB9_Pos)        /*!< 0x00000200 */
8501 #define CAN_F8R1_FB9                         CAN_F8R1_FB9_Msk                  /*!< Filter bit 9 */
8502 #define CAN_F8R1_FB10_Pos                    (10U)
8503 #define CAN_F8R1_FB10_Msk                    (0x1UL << CAN_F8R1_FB10_Pos)       /*!< 0x00000400 */
8504 #define CAN_F8R1_FB10                        CAN_F8R1_FB10_Msk                 /*!< Filter bit 10 */
8505 #define CAN_F8R1_FB11_Pos                    (11U)
8506 #define CAN_F8R1_FB11_Msk                    (0x1UL << CAN_F8R1_FB11_Pos)       /*!< 0x00000800 */
8507 #define CAN_F8R1_FB11                        CAN_F8R1_FB11_Msk                 /*!< Filter bit 11 */
8508 #define CAN_F8R1_FB12_Pos                    (12U)
8509 #define CAN_F8R1_FB12_Msk                    (0x1UL << CAN_F8R1_FB12_Pos)       /*!< 0x00001000 */
8510 #define CAN_F8R1_FB12                        CAN_F8R1_FB12_Msk                 /*!< Filter bit 12 */
8511 #define CAN_F8R1_FB13_Pos                    (13U)
8512 #define CAN_F8R1_FB13_Msk                    (0x1UL << CAN_F8R1_FB13_Pos)       /*!< 0x00002000 */
8513 #define CAN_F8R1_FB13                        CAN_F8R1_FB13_Msk                 /*!< Filter bit 13 */
8514 #define CAN_F8R1_FB14_Pos                    (14U)
8515 #define CAN_F8R1_FB14_Msk                    (0x1UL << CAN_F8R1_FB14_Pos)       /*!< 0x00004000 */
8516 #define CAN_F8R1_FB14                        CAN_F8R1_FB14_Msk                 /*!< Filter bit 14 */
8517 #define CAN_F8R1_FB15_Pos                    (15U)
8518 #define CAN_F8R1_FB15_Msk                    (0x1UL << CAN_F8R1_FB15_Pos)       /*!< 0x00008000 */
8519 #define CAN_F8R1_FB15                        CAN_F8R1_FB15_Msk                 /*!< Filter bit 15 */
8520 #define CAN_F8R1_FB16_Pos                    (16U)
8521 #define CAN_F8R1_FB16_Msk                    (0x1UL << CAN_F8R1_FB16_Pos)       /*!< 0x00010000 */
8522 #define CAN_F8R1_FB16                        CAN_F8R1_FB16_Msk                 /*!< Filter bit 16 */
8523 #define CAN_F8R1_FB17_Pos                    (17U)
8524 #define CAN_F8R1_FB17_Msk                    (0x1UL << CAN_F8R1_FB17_Pos)       /*!< 0x00020000 */
8525 #define CAN_F8R1_FB17                        CAN_F8R1_FB17_Msk                 /*!< Filter bit 17 */
8526 #define CAN_F8R1_FB18_Pos                    (18U)
8527 #define CAN_F8R1_FB18_Msk                    (0x1UL << CAN_F8R1_FB18_Pos)       /*!< 0x00040000 */
8528 #define CAN_F8R1_FB18                        CAN_F8R1_FB18_Msk                 /*!< Filter bit 18 */
8529 #define CAN_F8R1_FB19_Pos                    (19U)
8530 #define CAN_F8R1_FB19_Msk                    (0x1UL << CAN_F8R1_FB19_Pos)       /*!< 0x00080000 */
8531 #define CAN_F8R1_FB19                        CAN_F8R1_FB19_Msk                 /*!< Filter bit 19 */
8532 #define CAN_F8R1_FB20_Pos                    (20U)
8533 #define CAN_F8R1_FB20_Msk                    (0x1UL << CAN_F8R1_FB20_Pos)       /*!< 0x00100000 */
8534 #define CAN_F8R1_FB20                        CAN_F8R1_FB20_Msk                 /*!< Filter bit 20 */
8535 #define CAN_F8R1_FB21_Pos                    (21U)
8536 #define CAN_F8R1_FB21_Msk                    (0x1UL << CAN_F8R1_FB21_Pos)       /*!< 0x00200000 */
8537 #define CAN_F8R1_FB21                        CAN_F8R1_FB21_Msk                 /*!< Filter bit 21 */
8538 #define CAN_F8R1_FB22_Pos                    (22U)
8539 #define CAN_F8R1_FB22_Msk                    (0x1UL << CAN_F8R1_FB22_Pos)       /*!< 0x00400000 */
8540 #define CAN_F8R1_FB22                        CAN_F8R1_FB22_Msk                 /*!< Filter bit 22 */
8541 #define CAN_F8R1_FB23_Pos                    (23U)
8542 #define CAN_F8R1_FB23_Msk                    (0x1UL << CAN_F8R1_FB23_Pos)       /*!< 0x00800000 */
8543 #define CAN_F8R1_FB23                        CAN_F8R1_FB23_Msk                 /*!< Filter bit 23 */
8544 #define CAN_F8R1_FB24_Pos                    (24U)
8545 #define CAN_F8R1_FB24_Msk                    (0x1UL << CAN_F8R1_FB24_Pos)       /*!< 0x01000000 */
8546 #define CAN_F8R1_FB24                        CAN_F8R1_FB24_Msk                 /*!< Filter bit 24 */
8547 #define CAN_F8R1_FB25_Pos                    (25U)
8548 #define CAN_F8R1_FB25_Msk                    (0x1UL << CAN_F8R1_FB25_Pos)       /*!< 0x02000000 */
8549 #define CAN_F8R1_FB25                        CAN_F8R1_FB25_Msk                 /*!< Filter bit 25 */
8550 #define CAN_F8R1_FB26_Pos                    (26U)
8551 #define CAN_F8R1_FB26_Msk                    (0x1UL << CAN_F8R1_FB26_Pos)       /*!< 0x04000000 */
8552 #define CAN_F8R1_FB26                        CAN_F8R1_FB26_Msk                 /*!< Filter bit 26 */
8553 #define CAN_F8R1_FB27_Pos                    (27U)
8554 #define CAN_F8R1_FB27_Msk                    (0x1UL << CAN_F8R1_FB27_Pos)       /*!< 0x08000000 */
8555 #define CAN_F8R1_FB27                        CAN_F8R1_FB27_Msk                 /*!< Filter bit 27 */
8556 #define CAN_F8R1_FB28_Pos                    (28U)
8557 #define CAN_F8R1_FB28_Msk                    (0x1UL << CAN_F8R1_FB28_Pos)       /*!< 0x10000000 */
8558 #define CAN_F8R1_FB28                        CAN_F8R1_FB28_Msk                 /*!< Filter bit 28 */
8559 #define CAN_F8R1_FB29_Pos                    (29U)
8560 #define CAN_F8R1_FB29_Msk                    (0x1UL << CAN_F8R1_FB29_Pos)       /*!< 0x20000000 */
8561 #define CAN_F8R1_FB29                        CAN_F8R1_FB29_Msk                 /*!< Filter bit 29 */
8562 #define CAN_F8R1_FB30_Pos                    (30U)
8563 #define CAN_F8R1_FB30_Msk                    (0x1UL << CAN_F8R1_FB30_Pos)       /*!< 0x40000000 */
8564 #define CAN_F8R1_FB30                        CAN_F8R1_FB30_Msk                 /*!< Filter bit 30 */
8565 #define CAN_F8R1_FB31_Pos                    (31U)
8566 #define CAN_F8R1_FB31_Msk                    (0x1UL << CAN_F8R1_FB31_Pos)       /*!< 0x80000000 */
8567 #define CAN_F8R1_FB31                        CAN_F8R1_FB31_Msk                 /*!< Filter bit 31 */
8568 
8569 /*******************  Bit definition for CAN_F9R1 register  *******************/
8570 #define CAN_F9R1_FB0_Pos                     (0U)
8571 #define CAN_F9R1_FB0_Msk                     (0x1UL << CAN_F9R1_FB0_Pos)        /*!< 0x00000001 */
8572 #define CAN_F9R1_FB0                         CAN_F9R1_FB0_Msk                  /*!< Filter bit 0 */
8573 #define CAN_F9R1_FB1_Pos                     (1U)
8574 #define CAN_F9R1_FB1_Msk                     (0x1UL << CAN_F9R1_FB1_Pos)        /*!< 0x00000002 */
8575 #define CAN_F9R1_FB1                         CAN_F9R1_FB1_Msk                  /*!< Filter bit 1 */
8576 #define CAN_F9R1_FB2_Pos                     (2U)
8577 #define CAN_F9R1_FB2_Msk                     (0x1UL << CAN_F9R1_FB2_Pos)        /*!< 0x00000004 */
8578 #define CAN_F9R1_FB2                         CAN_F9R1_FB2_Msk                  /*!< Filter bit 2 */
8579 #define CAN_F9R1_FB3_Pos                     (3U)
8580 #define CAN_F9R1_FB3_Msk                     (0x1UL << CAN_F9R1_FB3_Pos)        /*!< 0x00000008 */
8581 #define CAN_F9R1_FB3                         CAN_F9R1_FB3_Msk                  /*!< Filter bit 3 */
8582 #define CAN_F9R1_FB4_Pos                     (4U)
8583 #define CAN_F9R1_FB4_Msk                     (0x1UL << CAN_F9R1_FB4_Pos)        /*!< 0x00000010 */
8584 #define CAN_F9R1_FB4                         CAN_F9R1_FB4_Msk                  /*!< Filter bit 4 */
8585 #define CAN_F9R1_FB5_Pos                     (5U)
8586 #define CAN_F9R1_FB5_Msk                     (0x1UL << CAN_F9R1_FB5_Pos)        /*!< 0x00000020 */
8587 #define CAN_F9R1_FB5                         CAN_F9R1_FB5_Msk                  /*!< Filter bit 5 */
8588 #define CAN_F9R1_FB6_Pos                     (6U)
8589 #define CAN_F9R1_FB6_Msk                     (0x1UL << CAN_F9R1_FB6_Pos)        /*!< 0x00000040 */
8590 #define CAN_F9R1_FB6                         CAN_F9R1_FB6_Msk                  /*!< Filter bit 6 */
8591 #define CAN_F9R1_FB7_Pos                     (7U)
8592 #define CAN_F9R1_FB7_Msk                     (0x1UL << CAN_F9R1_FB7_Pos)        /*!< 0x00000080 */
8593 #define CAN_F9R1_FB7                         CAN_F9R1_FB7_Msk                  /*!< Filter bit 7 */
8594 #define CAN_F9R1_FB8_Pos                     (8U)
8595 #define CAN_F9R1_FB8_Msk                     (0x1UL << CAN_F9R1_FB8_Pos)        /*!< 0x00000100 */
8596 #define CAN_F9R1_FB8                         CAN_F9R1_FB8_Msk                  /*!< Filter bit 8 */
8597 #define CAN_F9R1_FB9_Pos                     (9U)
8598 #define CAN_F9R1_FB9_Msk                     (0x1UL << CAN_F9R1_FB9_Pos)        /*!< 0x00000200 */
8599 #define CAN_F9R1_FB9                         CAN_F9R1_FB9_Msk                  /*!< Filter bit 9 */
8600 #define CAN_F9R1_FB10_Pos                    (10U)
8601 #define CAN_F9R1_FB10_Msk                    (0x1UL << CAN_F9R1_FB10_Pos)       /*!< 0x00000400 */
8602 #define CAN_F9R1_FB10                        CAN_F9R1_FB10_Msk                 /*!< Filter bit 10 */
8603 #define CAN_F9R1_FB11_Pos                    (11U)
8604 #define CAN_F9R1_FB11_Msk                    (0x1UL << CAN_F9R1_FB11_Pos)       /*!< 0x00000800 */
8605 #define CAN_F9R1_FB11                        CAN_F9R1_FB11_Msk                 /*!< Filter bit 11 */
8606 #define CAN_F9R1_FB12_Pos                    (12U)
8607 #define CAN_F9R1_FB12_Msk                    (0x1UL << CAN_F9R1_FB12_Pos)       /*!< 0x00001000 */
8608 #define CAN_F9R1_FB12                        CAN_F9R1_FB12_Msk                 /*!< Filter bit 12 */
8609 #define CAN_F9R1_FB13_Pos                    (13U)
8610 #define CAN_F9R1_FB13_Msk                    (0x1UL << CAN_F9R1_FB13_Pos)       /*!< 0x00002000 */
8611 #define CAN_F9R1_FB13                        CAN_F9R1_FB13_Msk                 /*!< Filter bit 13 */
8612 #define CAN_F9R1_FB14_Pos                    (14U)
8613 #define CAN_F9R1_FB14_Msk                    (0x1UL << CAN_F9R1_FB14_Pos)       /*!< 0x00004000 */
8614 #define CAN_F9R1_FB14                        CAN_F9R1_FB14_Msk                 /*!< Filter bit 14 */
8615 #define CAN_F9R1_FB15_Pos                    (15U)
8616 #define CAN_F9R1_FB15_Msk                    (0x1UL << CAN_F9R1_FB15_Pos)       /*!< 0x00008000 */
8617 #define CAN_F9R1_FB15                        CAN_F9R1_FB15_Msk                 /*!< Filter bit 15 */
8618 #define CAN_F9R1_FB16_Pos                    (16U)
8619 #define CAN_F9R1_FB16_Msk                    (0x1UL << CAN_F9R1_FB16_Pos)       /*!< 0x00010000 */
8620 #define CAN_F9R1_FB16                        CAN_F9R1_FB16_Msk                 /*!< Filter bit 16 */
8621 #define CAN_F9R1_FB17_Pos                    (17U)
8622 #define CAN_F9R1_FB17_Msk                    (0x1UL << CAN_F9R1_FB17_Pos)       /*!< 0x00020000 */
8623 #define CAN_F9R1_FB17                        CAN_F9R1_FB17_Msk                 /*!< Filter bit 17 */
8624 #define CAN_F9R1_FB18_Pos                    (18U)
8625 #define CAN_F9R1_FB18_Msk                    (0x1UL << CAN_F9R1_FB18_Pos)       /*!< 0x00040000 */
8626 #define CAN_F9R1_FB18                        CAN_F9R1_FB18_Msk                 /*!< Filter bit 18 */
8627 #define CAN_F9R1_FB19_Pos                    (19U)
8628 #define CAN_F9R1_FB19_Msk                    (0x1UL << CAN_F9R1_FB19_Pos)       /*!< 0x00080000 */
8629 #define CAN_F9R1_FB19                        CAN_F9R1_FB19_Msk                 /*!< Filter bit 19 */
8630 #define CAN_F9R1_FB20_Pos                    (20U)
8631 #define CAN_F9R1_FB20_Msk                    (0x1UL << CAN_F9R1_FB20_Pos)       /*!< 0x00100000 */
8632 #define CAN_F9R1_FB20                        CAN_F9R1_FB20_Msk                 /*!< Filter bit 20 */
8633 #define CAN_F9R1_FB21_Pos                    (21U)
8634 #define CAN_F9R1_FB21_Msk                    (0x1UL << CAN_F9R1_FB21_Pos)       /*!< 0x00200000 */
8635 #define CAN_F9R1_FB21                        CAN_F9R1_FB21_Msk                 /*!< Filter bit 21 */
8636 #define CAN_F9R1_FB22_Pos                    (22U)
8637 #define CAN_F9R1_FB22_Msk                    (0x1UL << CAN_F9R1_FB22_Pos)       /*!< 0x00400000 */
8638 #define CAN_F9R1_FB22                        CAN_F9R1_FB22_Msk                 /*!< Filter bit 22 */
8639 #define CAN_F9R1_FB23_Pos                    (23U)
8640 #define CAN_F9R1_FB23_Msk                    (0x1UL << CAN_F9R1_FB23_Pos)       /*!< 0x00800000 */
8641 #define CAN_F9R1_FB23                        CAN_F9R1_FB23_Msk                 /*!< Filter bit 23 */
8642 #define CAN_F9R1_FB24_Pos                    (24U)
8643 #define CAN_F9R1_FB24_Msk                    (0x1UL << CAN_F9R1_FB24_Pos)       /*!< 0x01000000 */
8644 #define CAN_F9R1_FB24                        CAN_F9R1_FB24_Msk                 /*!< Filter bit 24 */
8645 #define CAN_F9R1_FB25_Pos                    (25U)
8646 #define CAN_F9R1_FB25_Msk                    (0x1UL << CAN_F9R1_FB25_Pos)       /*!< 0x02000000 */
8647 #define CAN_F9R1_FB25                        CAN_F9R1_FB25_Msk                 /*!< Filter bit 25 */
8648 #define CAN_F9R1_FB26_Pos                    (26U)
8649 #define CAN_F9R1_FB26_Msk                    (0x1UL << CAN_F9R1_FB26_Pos)       /*!< 0x04000000 */
8650 #define CAN_F9R1_FB26                        CAN_F9R1_FB26_Msk                 /*!< Filter bit 26 */
8651 #define CAN_F9R1_FB27_Pos                    (27U)
8652 #define CAN_F9R1_FB27_Msk                    (0x1UL << CAN_F9R1_FB27_Pos)       /*!< 0x08000000 */
8653 #define CAN_F9R1_FB27                        CAN_F9R1_FB27_Msk                 /*!< Filter bit 27 */
8654 #define CAN_F9R1_FB28_Pos                    (28U)
8655 #define CAN_F9R1_FB28_Msk                    (0x1UL << CAN_F9R1_FB28_Pos)       /*!< 0x10000000 */
8656 #define CAN_F9R1_FB28                        CAN_F9R1_FB28_Msk                 /*!< Filter bit 28 */
8657 #define CAN_F9R1_FB29_Pos                    (29U)
8658 #define CAN_F9R1_FB29_Msk                    (0x1UL << CAN_F9R1_FB29_Pos)       /*!< 0x20000000 */
8659 #define CAN_F9R1_FB29                        CAN_F9R1_FB29_Msk                 /*!< Filter bit 29 */
8660 #define CAN_F9R1_FB30_Pos                    (30U)
8661 #define CAN_F9R1_FB30_Msk                    (0x1UL << CAN_F9R1_FB30_Pos)       /*!< 0x40000000 */
8662 #define CAN_F9R1_FB30                        CAN_F9R1_FB30_Msk                 /*!< Filter bit 30 */
8663 #define CAN_F9R1_FB31_Pos                    (31U)
8664 #define CAN_F9R1_FB31_Msk                    (0x1UL << CAN_F9R1_FB31_Pos)       /*!< 0x80000000 */
8665 #define CAN_F9R1_FB31                        CAN_F9R1_FB31_Msk                 /*!< Filter bit 31 */
8666 
8667 /*******************  Bit definition for CAN_F10R1 register  ******************/
8668 #define CAN_F10R1_FB0_Pos                    (0U)
8669 #define CAN_F10R1_FB0_Msk                    (0x1UL << CAN_F10R1_FB0_Pos)       /*!< 0x00000001 */
8670 #define CAN_F10R1_FB0                        CAN_F10R1_FB0_Msk                 /*!< Filter bit 0 */
8671 #define CAN_F10R1_FB1_Pos                    (1U)
8672 #define CAN_F10R1_FB1_Msk                    (0x1UL << CAN_F10R1_FB1_Pos)       /*!< 0x00000002 */
8673 #define CAN_F10R1_FB1                        CAN_F10R1_FB1_Msk                 /*!< Filter bit 1 */
8674 #define CAN_F10R1_FB2_Pos                    (2U)
8675 #define CAN_F10R1_FB2_Msk                    (0x1UL << CAN_F10R1_FB2_Pos)       /*!< 0x00000004 */
8676 #define CAN_F10R1_FB2                        CAN_F10R1_FB2_Msk                 /*!< Filter bit 2 */
8677 #define CAN_F10R1_FB3_Pos                    (3U)
8678 #define CAN_F10R1_FB3_Msk                    (0x1UL << CAN_F10R1_FB3_Pos)       /*!< 0x00000008 */
8679 #define CAN_F10R1_FB3                        CAN_F10R1_FB3_Msk                 /*!< Filter bit 3 */
8680 #define CAN_F10R1_FB4_Pos                    (4U)
8681 #define CAN_F10R1_FB4_Msk                    (0x1UL << CAN_F10R1_FB4_Pos)       /*!< 0x00000010 */
8682 #define CAN_F10R1_FB4                        CAN_F10R1_FB4_Msk                 /*!< Filter bit 4 */
8683 #define CAN_F10R1_FB5_Pos                    (5U)
8684 #define CAN_F10R1_FB5_Msk                    (0x1UL << CAN_F10R1_FB5_Pos)       /*!< 0x00000020 */
8685 #define CAN_F10R1_FB5                        CAN_F10R1_FB5_Msk                 /*!< Filter bit 5 */
8686 #define CAN_F10R1_FB6_Pos                    (6U)
8687 #define CAN_F10R1_FB6_Msk                    (0x1UL << CAN_F10R1_FB6_Pos)       /*!< 0x00000040 */
8688 #define CAN_F10R1_FB6                        CAN_F10R1_FB6_Msk                 /*!< Filter bit 6 */
8689 #define CAN_F10R1_FB7_Pos                    (7U)
8690 #define CAN_F10R1_FB7_Msk                    (0x1UL << CAN_F10R1_FB7_Pos)       /*!< 0x00000080 */
8691 #define CAN_F10R1_FB7                        CAN_F10R1_FB7_Msk                 /*!< Filter bit 7 */
8692 #define CAN_F10R1_FB8_Pos                    (8U)
8693 #define CAN_F10R1_FB8_Msk                    (0x1UL << CAN_F10R1_FB8_Pos)       /*!< 0x00000100 */
8694 #define CAN_F10R1_FB8                        CAN_F10R1_FB8_Msk                 /*!< Filter bit 8 */
8695 #define CAN_F10R1_FB9_Pos                    (9U)
8696 #define CAN_F10R1_FB9_Msk                    (0x1UL << CAN_F10R1_FB9_Pos)       /*!< 0x00000200 */
8697 #define CAN_F10R1_FB9                        CAN_F10R1_FB9_Msk                 /*!< Filter bit 9 */
8698 #define CAN_F10R1_FB10_Pos                   (10U)
8699 #define CAN_F10R1_FB10_Msk                   (0x1UL << CAN_F10R1_FB10_Pos)      /*!< 0x00000400 */
8700 #define CAN_F10R1_FB10                       CAN_F10R1_FB10_Msk                /*!< Filter bit 10 */
8701 #define CAN_F10R1_FB11_Pos                   (11U)
8702 #define CAN_F10R1_FB11_Msk                   (0x1UL << CAN_F10R1_FB11_Pos)      /*!< 0x00000800 */
8703 #define CAN_F10R1_FB11                       CAN_F10R1_FB11_Msk                /*!< Filter bit 11 */
8704 #define CAN_F10R1_FB12_Pos                   (12U)
8705 #define CAN_F10R1_FB12_Msk                   (0x1UL << CAN_F10R1_FB12_Pos)      /*!< 0x00001000 */
8706 #define CAN_F10R1_FB12                       CAN_F10R1_FB12_Msk                /*!< Filter bit 12 */
8707 #define CAN_F10R1_FB13_Pos                   (13U)
8708 #define CAN_F10R1_FB13_Msk                   (0x1UL << CAN_F10R1_FB13_Pos)      /*!< 0x00002000 */
8709 #define CAN_F10R1_FB13                       CAN_F10R1_FB13_Msk                /*!< Filter bit 13 */
8710 #define CAN_F10R1_FB14_Pos                   (14U)
8711 #define CAN_F10R1_FB14_Msk                   (0x1UL << CAN_F10R1_FB14_Pos)      /*!< 0x00004000 */
8712 #define CAN_F10R1_FB14                       CAN_F10R1_FB14_Msk                /*!< Filter bit 14 */
8713 #define CAN_F10R1_FB15_Pos                   (15U)
8714 #define CAN_F10R1_FB15_Msk                   (0x1UL << CAN_F10R1_FB15_Pos)      /*!< 0x00008000 */
8715 #define CAN_F10R1_FB15                       CAN_F10R1_FB15_Msk                /*!< Filter bit 15 */
8716 #define CAN_F10R1_FB16_Pos                   (16U)
8717 #define CAN_F10R1_FB16_Msk                   (0x1UL << CAN_F10R1_FB16_Pos)      /*!< 0x00010000 */
8718 #define CAN_F10R1_FB16                       CAN_F10R1_FB16_Msk                /*!< Filter bit 16 */
8719 #define CAN_F10R1_FB17_Pos                   (17U)
8720 #define CAN_F10R1_FB17_Msk                   (0x1UL << CAN_F10R1_FB17_Pos)      /*!< 0x00020000 */
8721 #define CAN_F10R1_FB17                       CAN_F10R1_FB17_Msk                /*!< Filter bit 17 */
8722 #define CAN_F10R1_FB18_Pos                   (18U)
8723 #define CAN_F10R1_FB18_Msk                   (0x1UL << CAN_F10R1_FB18_Pos)      /*!< 0x00040000 */
8724 #define CAN_F10R1_FB18                       CAN_F10R1_FB18_Msk                /*!< Filter bit 18 */
8725 #define CAN_F10R1_FB19_Pos                   (19U)
8726 #define CAN_F10R1_FB19_Msk                   (0x1UL << CAN_F10R1_FB19_Pos)      /*!< 0x00080000 */
8727 #define CAN_F10R1_FB19                       CAN_F10R1_FB19_Msk                /*!< Filter bit 19 */
8728 #define CAN_F10R1_FB20_Pos                   (20U)
8729 #define CAN_F10R1_FB20_Msk                   (0x1UL << CAN_F10R1_FB20_Pos)      /*!< 0x00100000 */
8730 #define CAN_F10R1_FB20                       CAN_F10R1_FB20_Msk                /*!< Filter bit 20 */
8731 #define CAN_F10R1_FB21_Pos                   (21U)
8732 #define CAN_F10R1_FB21_Msk                   (0x1UL << CAN_F10R1_FB21_Pos)      /*!< 0x00200000 */
8733 #define CAN_F10R1_FB21                       CAN_F10R1_FB21_Msk                /*!< Filter bit 21 */
8734 #define CAN_F10R1_FB22_Pos                   (22U)
8735 #define CAN_F10R1_FB22_Msk                   (0x1UL << CAN_F10R1_FB22_Pos)      /*!< 0x00400000 */
8736 #define CAN_F10R1_FB22                       CAN_F10R1_FB22_Msk                /*!< Filter bit 22 */
8737 #define CAN_F10R1_FB23_Pos                   (23U)
8738 #define CAN_F10R1_FB23_Msk                   (0x1UL << CAN_F10R1_FB23_Pos)      /*!< 0x00800000 */
8739 #define CAN_F10R1_FB23                       CAN_F10R1_FB23_Msk                /*!< Filter bit 23 */
8740 #define CAN_F10R1_FB24_Pos                   (24U)
8741 #define CAN_F10R1_FB24_Msk                   (0x1UL << CAN_F10R1_FB24_Pos)      /*!< 0x01000000 */
8742 #define CAN_F10R1_FB24                       CAN_F10R1_FB24_Msk                /*!< Filter bit 24 */
8743 #define CAN_F10R1_FB25_Pos                   (25U)
8744 #define CAN_F10R1_FB25_Msk                   (0x1UL << CAN_F10R1_FB25_Pos)      /*!< 0x02000000 */
8745 #define CAN_F10R1_FB25                       CAN_F10R1_FB25_Msk                /*!< Filter bit 25 */
8746 #define CAN_F10R1_FB26_Pos                   (26U)
8747 #define CAN_F10R1_FB26_Msk                   (0x1UL << CAN_F10R1_FB26_Pos)      /*!< 0x04000000 */
8748 #define CAN_F10R1_FB26                       CAN_F10R1_FB26_Msk                /*!< Filter bit 26 */
8749 #define CAN_F10R1_FB27_Pos                   (27U)
8750 #define CAN_F10R1_FB27_Msk                   (0x1UL << CAN_F10R1_FB27_Pos)      /*!< 0x08000000 */
8751 #define CAN_F10R1_FB27                       CAN_F10R1_FB27_Msk                /*!< Filter bit 27 */
8752 #define CAN_F10R1_FB28_Pos                   (28U)
8753 #define CAN_F10R1_FB28_Msk                   (0x1UL << CAN_F10R1_FB28_Pos)      /*!< 0x10000000 */
8754 #define CAN_F10R1_FB28                       CAN_F10R1_FB28_Msk                /*!< Filter bit 28 */
8755 #define CAN_F10R1_FB29_Pos                   (29U)
8756 #define CAN_F10R1_FB29_Msk                   (0x1UL << CAN_F10R1_FB29_Pos)      /*!< 0x20000000 */
8757 #define CAN_F10R1_FB29                       CAN_F10R1_FB29_Msk                /*!< Filter bit 29 */
8758 #define CAN_F10R1_FB30_Pos                   (30U)
8759 #define CAN_F10R1_FB30_Msk                   (0x1UL << CAN_F10R1_FB30_Pos)      /*!< 0x40000000 */
8760 #define CAN_F10R1_FB30                       CAN_F10R1_FB30_Msk                /*!< Filter bit 30 */
8761 #define CAN_F10R1_FB31_Pos                   (31U)
8762 #define CAN_F10R1_FB31_Msk                   (0x1UL << CAN_F10R1_FB31_Pos)      /*!< 0x80000000 */
8763 #define CAN_F10R1_FB31                       CAN_F10R1_FB31_Msk                /*!< Filter bit 31 */
8764 
8765 /*******************  Bit definition for CAN_F11R1 register  ******************/
8766 #define CAN_F11R1_FB0_Pos                    (0U)
8767 #define CAN_F11R1_FB0_Msk                    (0x1UL << CAN_F11R1_FB0_Pos)       /*!< 0x00000001 */
8768 #define CAN_F11R1_FB0                        CAN_F11R1_FB0_Msk                 /*!< Filter bit 0 */
8769 #define CAN_F11R1_FB1_Pos                    (1U)
8770 #define CAN_F11R1_FB1_Msk                    (0x1UL << CAN_F11R1_FB1_Pos)       /*!< 0x00000002 */
8771 #define CAN_F11R1_FB1                        CAN_F11R1_FB1_Msk                 /*!< Filter bit 1 */
8772 #define CAN_F11R1_FB2_Pos                    (2U)
8773 #define CAN_F11R1_FB2_Msk                    (0x1UL << CAN_F11R1_FB2_Pos)       /*!< 0x00000004 */
8774 #define CAN_F11R1_FB2                        CAN_F11R1_FB2_Msk                 /*!< Filter bit 2 */
8775 #define CAN_F11R1_FB3_Pos                    (3U)
8776 #define CAN_F11R1_FB3_Msk                    (0x1UL << CAN_F11R1_FB3_Pos)       /*!< 0x00000008 */
8777 #define CAN_F11R1_FB3                        CAN_F11R1_FB3_Msk                 /*!< Filter bit 3 */
8778 #define CAN_F11R1_FB4_Pos                    (4U)
8779 #define CAN_F11R1_FB4_Msk                    (0x1UL << CAN_F11R1_FB4_Pos)       /*!< 0x00000010 */
8780 #define CAN_F11R1_FB4                        CAN_F11R1_FB4_Msk                 /*!< Filter bit 4 */
8781 #define CAN_F11R1_FB5_Pos                    (5U)
8782 #define CAN_F11R1_FB5_Msk                    (0x1UL << CAN_F11R1_FB5_Pos)       /*!< 0x00000020 */
8783 #define CAN_F11R1_FB5                        CAN_F11R1_FB5_Msk                 /*!< Filter bit 5 */
8784 #define CAN_F11R1_FB6_Pos                    (6U)
8785 #define CAN_F11R1_FB6_Msk                    (0x1UL << CAN_F11R1_FB6_Pos)       /*!< 0x00000040 */
8786 #define CAN_F11R1_FB6                        CAN_F11R1_FB6_Msk                 /*!< Filter bit 6 */
8787 #define CAN_F11R1_FB7_Pos                    (7U)
8788 #define CAN_F11R1_FB7_Msk                    (0x1UL << CAN_F11R1_FB7_Pos)       /*!< 0x00000080 */
8789 #define CAN_F11R1_FB7                        CAN_F11R1_FB7_Msk                 /*!< Filter bit 7 */
8790 #define CAN_F11R1_FB8_Pos                    (8U)
8791 #define CAN_F11R1_FB8_Msk                    (0x1UL << CAN_F11R1_FB8_Pos)       /*!< 0x00000100 */
8792 #define CAN_F11R1_FB8                        CAN_F11R1_FB8_Msk                 /*!< Filter bit 8 */
8793 #define CAN_F11R1_FB9_Pos                    (9U)
8794 #define CAN_F11R1_FB9_Msk                    (0x1UL << CAN_F11R1_FB9_Pos)       /*!< 0x00000200 */
8795 #define CAN_F11R1_FB9                        CAN_F11R1_FB9_Msk                 /*!< Filter bit 9 */
8796 #define CAN_F11R1_FB10_Pos                   (10U)
8797 #define CAN_F11R1_FB10_Msk                   (0x1UL << CAN_F11R1_FB10_Pos)      /*!< 0x00000400 */
8798 #define CAN_F11R1_FB10                       CAN_F11R1_FB10_Msk                /*!< Filter bit 10 */
8799 #define CAN_F11R1_FB11_Pos                   (11U)
8800 #define CAN_F11R1_FB11_Msk                   (0x1UL << CAN_F11R1_FB11_Pos)      /*!< 0x00000800 */
8801 #define CAN_F11R1_FB11                       CAN_F11R1_FB11_Msk                /*!< Filter bit 11 */
8802 #define CAN_F11R1_FB12_Pos                   (12U)
8803 #define CAN_F11R1_FB12_Msk                   (0x1UL << CAN_F11R1_FB12_Pos)      /*!< 0x00001000 */
8804 #define CAN_F11R1_FB12                       CAN_F11R1_FB12_Msk                /*!< Filter bit 12 */
8805 #define CAN_F11R1_FB13_Pos                   (13U)
8806 #define CAN_F11R1_FB13_Msk                   (0x1UL << CAN_F11R1_FB13_Pos)      /*!< 0x00002000 */
8807 #define CAN_F11R1_FB13                       CAN_F11R1_FB13_Msk                /*!< Filter bit 13 */
8808 #define CAN_F11R1_FB14_Pos                   (14U)
8809 #define CAN_F11R1_FB14_Msk                   (0x1UL << CAN_F11R1_FB14_Pos)      /*!< 0x00004000 */
8810 #define CAN_F11R1_FB14                       CAN_F11R1_FB14_Msk                /*!< Filter bit 14 */
8811 #define CAN_F11R1_FB15_Pos                   (15U)
8812 #define CAN_F11R1_FB15_Msk                   (0x1UL << CAN_F11R1_FB15_Pos)      /*!< 0x00008000 */
8813 #define CAN_F11R1_FB15                       CAN_F11R1_FB15_Msk                /*!< Filter bit 15 */
8814 #define CAN_F11R1_FB16_Pos                   (16U)
8815 #define CAN_F11R1_FB16_Msk                   (0x1UL << CAN_F11R1_FB16_Pos)      /*!< 0x00010000 */
8816 #define CAN_F11R1_FB16                       CAN_F11R1_FB16_Msk                /*!< Filter bit 16 */
8817 #define CAN_F11R1_FB17_Pos                   (17U)
8818 #define CAN_F11R1_FB17_Msk                   (0x1UL << CAN_F11R1_FB17_Pos)      /*!< 0x00020000 */
8819 #define CAN_F11R1_FB17                       CAN_F11R1_FB17_Msk                /*!< Filter bit 17 */
8820 #define CAN_F11R1_FB18_Pos                   (18U)
8821 #define CAN_F11R1_FB18_Msk                   (0x1UL << CAN_F11R1_FB18_Pos)      /*!< 0x00040000 */
8822 #define CAN_F11R1_FB18                       CAN_F11R1_FB18_Msk                /*!< Filter bit 18 */
8823 #define CAN_F11R1_FB19_Pos                   (19U)
8824 #define CAN_F11R1_FB19_Msk                   (0x1UL << CAN_F11R1_FB19_Pos)      /*!< 0x00080000 */
8825 #define CAN_F11R1_FB19                       CAN_F11R1_FB19_Msk                /*!< Filter bit 19 */
8826 #define CAN_F11R1_FB20_Pos                   (20U)
8827 #define CAN_F11R1_FB20_Msk                   (0x1UL << CAN_F11R1_FB20_Pos)      /*!< 0x00100000 */
8828 #define CAN_F11R1_FB20                       CAN_F11R1_FB20_Msk                /*!< Filter bit 20 */
8829 #define CAN_F11R1_FB21_Pos                   (21U)
8830 #define CAN_F11R1_FB21_Msk                   (0x1UL << CAN_F11R1_FB21_Pos)      /*!< 0x00200000 */
8831 #define CAN_F11R1_FB21                       CAN_F11R1_FB21_Msk                /*!< Filter bit 21 */
8832 #define CAN_F11R1_FB22_Pos                   (22U)
8833 #define CAN_F11R1_FB22_Msk                   (0x1UL << CAN_F11R1_FB22_Pos)      /*!< 0x00400000 */
8834 #define CAN_F11R1_FB22                       CAN_F11R1_FB22_Msk                /*!< Filter bit 22 */
8835 #define CAN_F11R1_FB23_Pos                   (23U)
8836 #define CAN_F11R1_FB23_Msk                   (0x1UL << CAN_F11R1_FB23_Pos)      /*!< 0x00800000 */
8837 #define CAN_F11R1_FB23                       CAN_F11R1_FB23_Msk                /*!< Filter bit 23 */
8838 #define CAN_F11R1_FB24_Pos                   (24U)
8839 #define CAN_F11R1_FB24_Msk                   (0x1UL << CAN_F11R1_FB24_Pos)      /*!< 0x01000000 */
8840 #define CAN_F11R1_FB24                       CAN_F11R1_FB24_Msk                /*!< Filter bit 24 */
8841 #define CAN_F11R1_FB25_Pos                   (25U)
8842 #define CAN_F11R1_FB25_Msk                   (0x1UL << CAN_F11R1_FB25_Pos)      /*!< 0x02000000 */
8843 #define CAN_F11R1_FB25                       CAN_F11R1_FB25_Msk                /*!< Filter bit 25 */
8844 #define CAN_F11R1_FB26_Pos                   (26U)
8845 #define CAN_F11R1_FB26_Msk                   (0x1UL << CAN_F11R1_FB26_Pos)      /*!< 0x04000000 */
8846 #define CAN_F11R1_FB26                       CAN_F11R1_FB26_Msk                /*!< Filter bit 26 */
8847 #define CAN_F11R1_FB27_Pos                   (27U)
8848 #define CAN_F11R1_FB27_Msk                   (0x1UL << CAN_F11R1_FB27_Pos)      /*!< 0x08000000 */
8849 #define CAN_F11R1_FB27                       CAN_F11R1_FB27_Msk                /*!< Filter bit 27 */
8850 #define CAN_F11R1_FB28_Pos                   (28U)
8851 #define CAN_F11R1_FB28_Msk                   (0x1UL << CAN_F11R1_FB28_Pos)      /*!< 0x10000000 */
8852 #define CAN_F11R1_FB28                       CAN_F11R1_FB28_Msk                /*!< Filter bit 28 */
8853 #define CAN_F11R1_FB29_Pos                   (29U)
8854 #define CAN_F11R1_FB29_Msk                   (0x1UL << CAN_F11R1_FB29_Pos)      /*!< 0x20000000 */
8855 #define CAN_F11R1_FB29                       CAN_F11R1_FB29_Msk                /*!< Filter bit 29 */
8856 #define CAN_F11R1_FB30_Pos                   (30U)
8857 #define CAN_F11R1_FB30_Msk                   (0x1UL << CAN_F11R1_FB30_Pos)      /*!< 0x40000000 */
8858 #define CAN_F11R1_FB30                       CAN_F11R1_FB30_Msk                /*!< Filter bit 30 */
8859 #define CAN_F11R1_FB31_Pos                   (31U)
8860 #define CAN_F11R1_FB31_Msk                   (0x1UL << CAN_F11R1_FB31_Pos)      /*!< 0x80000000 */
8861 #define CAN_F11R1_FB31                       CAN_F11R1_FB31_Msk                /*!< Filter bit 31 */
8862 
8863 /*******************  Bit definition for CAN_F12R1 register  ******************/
8864 #define CAN_F12R1_FB0_Pos                    (0U)
8865 #define CAN_F12R1_FB0_Msk                    (0x1UL << CAN_F12R1_FB0_Pos)       /*!< 0x00000001 */
8866 #define CAN_F12R1_FB0                        CAN_F12R1_FB0_Msk                 /*!< Filter bit 0 */
8867 #define CAN_F12R1_FB1_Pos                    (1U)
8868 #define CAN_F12R1_FB1_Msk                    (0x1UL << CAN_F12R1_FB1_Pos)       /*!< 0x00000002 */
8869 #define CAN_F12R1_FB1                        CAN_F12R1_FB1_Msk                 /*!< Filter bit 1 */
8870 #define CAN_F12R1_FB2_Pos                    (2U)
8871 #define CAN_F12R1_FB2_Msk                    (0x1UL << CAN_F12R1_FB2_Pos)       /*!< 0x00000004 */
8872 #define CAN_F12R1_FB2                        CAN_F12R1_FB2_Msk                 /*!< Filter bit 2 */
8873 #define CAN_F12R1_FB3_Pos                    (3U)
8874 #define CAN_F12R1_FB3_Msk                    (0x1UL << CAN_F12R1_FB3_Pos)       /*!< 0x00000008 */
8875 #define CAN_F12R1_FB3                        CAN_F12R1_FB3_Msk                 /*!< Filter bit 3 */
8876 #define CAN_F12R1_FB4_Pos                    (4U)
8877 #define CAN_F12R1_FB4_Msk                    (0x1UL << CAN_F12R1_FB4_Pos)       /*!< 0x00000010 */
8878 #define CAN_F12R1_FB4                        CAN_F12R1_FB4_Msk                 /*!< Filter bit 4 */
8879 #define CAN_F12R1_FB5_Pos                    (5U)
8880 #define CAN_F12R1_FB5_Msk                    (0x1UL << CAN_F12R1_FB5_Pos)       /*!< 0x00000020 */
8881 #define CAN_F12R1_FB5                        CAN_F12R1_FB5_Msk                 /*!< Filter bit 5 */
8882 #define CAN_F12R1_FB6_Pos                    (6U)
8883 #define CAN_F12R1_FB6_Msk                    (0x1UL << CAN_F12R1_FB6_Pos)       /*!< 0x00000040 */
8884 #define CAN_F12R1_FB6                        CAN_F12R1_FB6_Msk                 /*!< Filter bit 6 */
8885 #define CAN_F12R1_FB7_Pos                    (7U)
8886 #define CAN_F12R1_FB7_Msk                    (0x1UL << CAN_F12R1_FB7_Pos)       /*!< 0x00000080 */
8887 #define CAN_F12R1_FB7                        CAN_F12R1_FB7_Msk                 /*!< Filter bit 7 */
8888 #define CAN_F12R1_FB8_Pos                    (8U)
8889 #define CAN_F12R1_FB8_Msk                    (0x1UL << CAN_F12R1_FB8_Pos)       /*!< 0x00000100 */
8890 #define CAN_F12R1_FB8                        CAN_F12R1_FB8_Msk                 /*!< Filter bit 8 */
8891 #define CAN_F12R1_FB9_Pos                    (9U)
8892 #define CAN_F12R1_FB9_Msk                    (0x1UL << CAN_F12R1_FB9_Pos)       /*!< 0x00000200 */
8893 #define CAN_F12R1_FB9                        CAN_F12R1_FB9_Msk                 /*!< Filter bit 9 */
8894 #define CAN_F12R1_FB10_Pos                   (10U)
8895 #define CAN_F12R1_FB10_Msk                   (0x1UL << CAN_F12R1_FB10_Pos)      /*!< 0x00000400 */
8896 #define CAN_F12R1_FB10                       CAN_F12R1_FB10_Msk                /*!< Filter bit 10 */
8897 #define CAN_F12R1_FB11_Pos                   (11U)
8898 #define CAN_F12R1_FB11_Msk                   (0x1UL << CAN_F12R1_FB11_Pos)      /*!< 0x00000800 */
8899 #define CAN_F12R1_FB11                       CAN_F12R1_FB11_Msk                /*!< Filter bit 11 */
8900 #define CAN_F12R1_FB12_Pos                   (12U)
8901 #define CAN_F12R1_FB12_Msk                   (0x1UL << CAN_F12R1_FB12_Pos)      /*!< 0x00001000 */
8902 #define CAN_F12R1_FB12                       CAN_F12R1_FB12_Msk                /*!< Filter bit 12 */
8903 #define CAN_F12R1_FB13_Pos                   (13U)
8904 #define CAN_F12R1_FB13_Msk                   (0x1UL << CAN_F12R1_FB13_Pos)      /*!< 0x00002000 */
8905 #define CAN_F12R1_FB13                       CAN_F12R1_FB13_Msk                /*!< Filter bit 13 */
8906 #define CAN_F12R1_FB14_Pos                   (14U)
8907 #define CAN_F12R1_FB14_Msk                   (0x1UL << CAN_F12R1_FB14_Pos)      /*!< 0x00004000 */
8908 #define CAN_F12R1_FB14                       CAN_F12R1_FB14_Msk                /*!< Filter bit 14 */
8909 #define CAN_F12R1_FB15_Pos                   (15U)
8910 #define CAN_F12R1_FB15_Msk                   (0x1UL << CAN_F12R1_FB15_Pos)      /*!< 0x00008000 */
8911 #define CAN_F12R1_FB15                       CAN_F12R1_FB15_Msk                /*!< Filter bit 15 */
8912 #define CAN_F12R1_FB16_Pos                   (16U)
8913 #define CAN_F12R1_FB16_Msk                   (0x1UL << CAN_F12R1_FB16_Pos)      /*!< 0x00010000 */
8914 #define CAN_F12R1_FB16                       CAN_F12R1_FB16_Msk                /*!< Filter bit 16 */
8915 #define CAN_F12R1_FB17_Pos                   (17U)
8916 #define CAN_F12R1_FB17_Msk                   (0x1UL << CAN_F12R1_FB17_Pos)      /*!< 0x00020000 */
8917 #define CAN_F12R1_FB17                       CAN_F12R1_FB17_Msk                /*!< Filter bit 17 */
8918 #define CAN_F12R1_FB18_Pos                   (18U)
8919 #define CAN_F12R1_FB18_Msk                   (0x1UL << CAN_F12R1_FB18_Pos)      /*!< 0x00040000 */
8920 #define CAN_F12R1_FB18                       CAN_F12R1_FB18_Msk                /*!< Filter bit 18 */
8921 #define CAN_F12R1_FB19_Pos                   (19U)
8922 #define CAN_F12R1_FB19_Msk                   (0x1UL << CAN_F12R1_FB19_Pos)      /*!< 0x00080000 */
8923 #define CAN_F12R1_FB19                       CAN_F12R1_FB19_Msk                /*!< Filter bit 19 */
8924 #define CAN_F12R1_FB20_Pos                   (20U)
8925 #define CAN_F12R1_FB20_Msk                   (0x1UL << CAN_F12R1_FB20_Pos)      /*!< 0x00100000 */
8926 #define CAN_F12R1_FB20                       CAN_F12R1_FB20_Msk                /*!< Filter bit 20 */
8927 #define CAN_F12R1_FB21_Pos                   (21U)
8928 #define CAN_F12R1_FB21_Msk                   (0x1UL << CAN_F12R1_FB21_Pos)      /*!< 0x00200000 */
8929 #define CAN_F12R1_FB21                       CAN_F12R1_FB21_Msk                /*!< Filter bit 21 */
8930 #define CAN_F12R1_FB22_Pos                   (22U)
8931 #define CAN_F12R1_FB22_Msk                   (0x1UL << CAN_F12R1_FB22_Pos)      /*!< 0x00400000 */
8932 #define CAN_F12R1_FB22                       CAN_F12R1_FB22_Msk                /*!< Filter bit 22 */
8933 #define CAN_F12R1_FB23_Pos                   (23U)
8934 #define CAN_F12R1_FB23_Msk                   (0x1UL << CAN_F12R1_FB23_Pos)      /*!< 0x00800000 */
8935 #define CAN_F12R1_FB23                       CAN_F12R1_FB23_Msk                /*!< Filter bit 23 */
8936 #define CAN_F12R1_FB24_Pos                   (24U)
8937 #define CAN_F12R1_FB24_Msk                   (0x1UL << CAN_F12R1_FB24_Pos)      /*!< 0x01000000 */
8938 #define CAN_F12R1_FB24                       CAN_F12R1_FB24_Msk                /*!< Filter bit 24 */
8939 #define CAN_F12R1_FB25_Pos                   (25U)
8940 #define CAN_F12R1_FB25_Msk                   (0x1UL << CAN_F12R1_FB25_Pos)      /*!< 0x02000000 */
8941 #define CAN_F12R1_FB25                       CAN_F12R1_FB25_Msk                /*!< Filter bit 25 */
8942 #define CAN_F12R1_FB26_Pos                   (26U)
8943 #define CAN_F12R1_FB26_Msk                   (0x1UL << CAN_F12R1_FB26_Pos)      /*!< 0x04000000 */
8944 #define CAN_F12R1_FB26                       CAN_F12R1_FB26_Msk                /*!< Filter bit 26 */
8945 #define CAN_F12R1_FB27_Pos                   (27U)
8946 #define CAN_F12R1_FB27_Msk                   (0x1UL << CAN_F12R1_FB27_Pos)      /*!< 0x08000000 */
8947 #define CAN_F12R1_FB27                       CAN_F12R1_FB27_Msk                /*!< Filter bit 27 */
8948 #define CAN_F12R1_FB28_Pos                   (28U)
8949 #define CAN_F12R1_FB28_Msk                   (0x1UL << CAN_F12R1_FB28_Pos)      /*!< 0x10000000 */
8950 #define CAN_F12R1_FB28                       CAN_F12R1_FB28_Msk                /*!< Filter bit 28 */
8951 #define CAN_F12R1_FB29_Pos                   (29U)
8952 #define CAN_F12R1_FB29_Msk                   (0x1UL << CAN_F12R1_FB29_Pos)      /*!< 0x20000000 */
8953 #define CAN_F12R1_FB29                       CAN_F12R1_FB29_Msk                /*!< Filter bit 29 */
8954 #define CAN_F12R1_FB30_Pos                   (30U)
8955 #define CAN_F12R1_FB30_Msk                   (0x1UL << CAN_F12R1_FB30_Pos)      /*!< 0x40000000 */
8956 #define CAN_F12R1_FB30                       CAN_F12R1_FB30_Msk                /*!< Filter bit 30 */
8957 #define CAN_F12R1_FB31_Pos                   (31U)
8958 #define CAN_F12R1_FB31_Msk                   (0x1UL << CAN_F12R1_FB31_Pos)      /*!< 0x80000000 */
8959 #define CAN_F12R1_FB31                       CAN_F12R1_FB31_Msk                /*!< Filter bit 31 */
8960 
8961 /*******************  Bit definition for CAN_F13R1 register  ******************/
8962 #define CAN_F13R1_FB0_Pos                    (0U)
8963 #define CAN_F13R1_FB0_Msk                    (0x1UL << CAN_F13R1_FB0_Pos)       /*!< 0x00000001 */
8964 #define CAN_F13R1_FB0                        CAN_F13R1_FB0_Msk                 /*!< Filter bit 0 */
8965 #define CAN_F13R1_FB1_Pos                    (1U)
8966 #define CAN_F13R1_FB1_Msk                    (0x1UL << CAN_F13R1_FB1_Pos)       /*!< 0x00000002 */
8967 #define CAN_F13R1_FB1                        CAN_F13R1_FB1_Msk                 /*!< Filter bit 1 */
8968 #define CAN_F13R1_FB2_Pos                    (2U)
8969 #define CAN_F13R1_FB2_Msk                    (0x1UL << CAN_F13R1_FB2_Pos)       /*!< 0x00000004 */
8970 #define CAN_F13R1_FB2                        CAN_F13R1_FB2_Msk                 /*!< Filter bit 2 */
8971 #define CAN_F13R1_FB3_Pos                    (3U)
8972 #define CAN_F13R1_FB3_Msk                    (0x1UL << CAN_F13R1_FB3_Pos)       /*!< 0x00000008 */
8973 #define CAN_F13R1_FB3                        CAN_F13R1_FB3_Msk                 /*!< Filter bit 3 */
8974 #define CAN_F13R1_FB4_Pos                    (4U)
8975 #define CAN_F13R1_FB4_Msk                    (0x1UL << CAN_F13R1_FB4_Pos)       /*!< 0x00000010 */
8976 #define CAN_F13R1_FB4                        CAN_F13R1_FB4_Msk                 /*!< Filter bit 4 */
8977 #define CAN_F13R1_FB5_Pos                    (5U)
8978 #define CAN_F13R1_FB5_Msk                    (0x1UL << CAN_F13R1_FB5_Pos)       /*!< 0x00000020 */
8979 #define CAN_F13R1_FB5                        CAN_F13R1_FB5_Msk                 /*!< Filter bit 5 */
8980 #define CAN_F13R1_FB6_Pos                    (6U)
8981 #define CAN_F13R1_FB6_Msk                    (0x1UL << CAN_F13R1_FB6_Pos)       /*!< 0x00000040 */
8982 #define CAN_F13R1_FB6                        CAN_F13R1_FB6_Msk                 /*!< Filter bit 6 */
8983 #define CAN_F13R1_FB7_Pos                    (7U)
8984 #define CAN_F13R1_FB7_Msk                    (0x1UL << CAN_F13R1_FB7_Pos)       /*!< 0x00000080 */
8985 #define CAN_F13R1_FB7                        CAN_F13R1_FB7_Msk                 /*!< Filter bit 7 */
8986 #define CAN_F13R1_FB8_Pos                    (8U)
8987 #define CAN_F13R1_FB8_Msk                    (0x1UL << CAN_F13R1_FB8_Pos)       /*!< 0x00000100 */
8988 #define CAN_F13R1_FB8                        CAN_F13R1_FB8_Msk                 /*!< Filter bit 8 */
8989 #define CAN_F13R1_FB9_Pos                    (9U)
8990 #define CAN_F13R1_FB9_Msk                    (0x1UL << CAN_F13R1_FB9_Pos)       /*!< 0x00000200 */
8991 #define CAN_F13R1_FB9                        CAN_F13R1_FB9_Msk                 /*!< Filter bit 9 */
8992 #define CAN_F13R1_FB10_Pos                   (10U)
8993 #define CAN_F13R1_FB10_Msk                   (0x1UL << CAN_F13R1_FB10_Pos)      /*!< 0x00000400 */
8994 #define CAN_F13R1_FB10                       CAN_F13R1_FB10_Msk                /*!< Filter bit 10 */
8995 #define CAN_F13R1_FB11_Pos                   (11U)
8996 #define CAN_F13R1_FB11_Msk                   (0x1UL << CAN_F13R1_FB11_Pos)      /*!< 0x00000800 */
8997 #define CAN_F13R1_FB11                       CAN_F13R1_FB11_Msk                /*!< Filter bit 11 */
8998 #define CAN_F13R1_FB12_Pos                   (12U)
8999 #define CAN_F13R1_FB12_Msk                   (0x1UL << CAN_F13R1_FB12_Pos)      /*!< 0x00001000 */
9000 #define CAN_F13R1_FB12                       CAN_F13R1_FB12_Msk                /*!< Filter bit 12 */
9001 #define CAN_F13R1_FB13_Pos                   (13U)
9002 #define CAN_F13R1_FB13_Msk                   (0x1UL << CAN_F13R1_FB13_Pos)      /*!< 0x00002000 */
9003 #define CAN_F13R1_FB13                       CAN_F13R1_FB13_Msk                /*!< Filter bit 13 */
9004 #define CAN_F13R1_FB14_Pos                   (14U)
9005 #define CAN_F13R1_FB14_Msk                   (0x1UL << CAN_F13R1_FB14_Pos)      /*!< 0x00004000 */
9006 #define CAN_F13R1_FB14                       CAN_F13R1_FB14_Msk                /*!< Filter bit 14 */
9007 #define CAN_F13R1_FB15_Pos                   (15U)
9008 #define CAN_F13R1_FB15_Msk                   (0x1UL << CAN_F13R1_FB15_Pos)      /*!< 0x00008000 */
9009 #define CAN_F13R1_FB15                       CAN_F13R1_FB15_Msk                /*!< Filter bit 15 */
9010 #define CAN_F13R1_FB16_Pos                   (16U)
9011 #define CAN_F13R1_FB16_Msk                   (0x1UL << CAN_F13R1_FB16_Pos)      /*!< 0x00010000 */
9012 #define CAN_F13R1_FB16                       CAN_F13R1_FB16_Msk                /*!< Filter bit 16 */
9013 #define CAN_F13R1_FB17_Pos                   (17U)
9014 #define CAN_F13R1_FB17_Msk                   (0x1UL << CAN_F13R1_FB17_Pos)      /*!< 0x00020000 */
9015 #define CAN_F13R1_FB17                       CAN_F13R1_FB17_Msk                /*!< Filter bit 17 */
9016 #define CAN_F13R1_FB18_Pos                   (18U)
9017 #define CAN_F13R1_FB18_Msk                   (0x1UL << CAN_F13R1_FB18_Pos)      /*!< 0x00040000 */
9018 #define CAN_F13R1_FB18                       CAN_F13R1_FB18_Msk                /*!< Filter bit 18 */
9019 #define CAN_F13R1_FB19_Pos                   (19U)
9020 #define CAN_F13R1_FB19_Msk                   (0x1UL << CAN_F13R1_FB19_Pos)      /*!< 0x00080000 */
9021 #define CAN_F13R1_FB19                       CAN_F13R1_FB19_Msk                /*!< Filter bit 19 */
9022 #define CAN_F13R1_FB20_Pos                   (20U)
9023 #define CAN_F13R1_FB20_Msk                   (0x1UL << CAN_F13R1_FB20_Pos)      /*!< 0x00100000 */
9024 #define CAN_F13R1_FB20                       CAN_F13R1_FB20_Msk                /*!< Filter bit 20 */
9025 #define CAN_F13R1_FB21_Pos                   (21U)
9026 #define CAN_F13R1_FB21_Msk                   (0x1UL << CAN_F13R1_FB21_Pos)      /*!< 0x00200000 */
9027 #define CAN_F13R1_FB21                       CAN_F13R1_FB21_Msk                /*!< Filter bit 21 */
9028 #define CAN_F13R1_FB22_Pos                   (22U)
9029 #define CAN_F13R1_FB22_Msk                   (0x1UL << CAN_F13R1_FB22_Pos)      /*!< 0x00400000 */
9030 #define CAN_F13R1_FB22                       CAN_F13R1_FB22_Msk                /*!< Filter bit 22 */
9031 #define CAN_F13R1_FB23_Pos                   (23U)
9032 #define CAN_F13R1_FB23_Msk                   (0x1UL << CAN_F13R1_FB23_Pos)      /*!< 0x00800000 */
9033 #define CAN_F13R1_FB23                       CAN_F13R1_FB23_Msk                /*!< Filter bit 23 */
9034 #define CAN_F13R1_FB24_Pos                   (24U)
9035 #define CAN_F13R1_FB24_Msk                   (0x1UL << CAN_F13R1_FB24_Pos)      /*!< 0x01000000 */
9036 #define CAN_F13R1_FB24                       CAN_F13R1_FB24_Msk                /*!< Filter bit 24 */
9037 #define CAN_F13R1_FB25_Pos                   (25U)
9038 #define CAN_F13R1_FB25_Msk                   (0x1UL << CAN_F13R1_FB25_Pos)      /*!< 0x02000000 */
9039 #define CAN_F13R1_FB25                       CAN_F13R1_FB25_Msk                /*!< Filter bit 25 */
9040 #define CAN_F13R1_FB26_Pos                   (26U)
9041 #define CAN_F13R1_FB26_Msk                   (0x1UL << CAN_F13R1_FB26_Pos)      /*!< 0x04000000 */
9042 #define CAN_F13R1_FB26                       CAN_F13R1_FB26_Msk                /*!< Filter bit 26 */
9043 #define CAN_F13R1_FB27_Pos                   (27U)
9044 #define CAN_F13R1_FB27_Msk                   (0x1UL << CAN_F13R1_FB27_Pos)      /*!< 0x08000000 */
9045 #define CAN_F13R1_FB27                       CAN_F13R1_FB27_Msk                /*!< Filter bit 27 */
9046 #define CAN_F13R1_FB28_Pos                   (28U)
9047 #define CAN_F13R1_FB28_Msk                   (0x1UL << CAN_F13R1_FB28_Pos)      /*!< 0x10000000 */
9048 #define CAN_F13R1_FB28                       CAN_F13R1_FB28_Msk                /*!< Filter bit 28 */
9049 #define CAN_F13R1_FB29_Pos                   (29U)
9050 #define CAN_F13R1_FB29_Msk                   (0x1UL << CAN_F13R1_FB29_Pos)      /*!< 0x20000000 */
9051 #define CAN_F13R1_FB29                       CAN_F13R1_FB29_Msk                /*!< Filter bit 29 */
9052 #define CAN_F13R1_FB30_Pos                   (30U)
9053 #define CAN_F13R1_FB30_Msk                   (0x1UL << CAN_F13R1_FB30_Pos)      /*!< 0x40000000 */
9054 #define CAN_F13R1_FB30                       CAN_F13R1_FB30_Msk                /*!< Filter bit 30 */
9055 #define CAN_F13R1_FB31_Pos                   (31U)
9056 #define CAN_F13R1_FB31_Msk                   (0x1UL << CAN_F13R1_FB31_Pos)      /*!< 0x80000000 */
9057 #define CAN_F13R1_FB31                       CAN_F13R1_FB31_Msk                /*!< Filter bit 31 */
9058 
9059 /*******************  Bit definition for CAN_F0R2 register  *******************/
9060 #define CAN_F0R2_FB0_Pos                     (0U)
9061 #define CAN_F0R2_FB0_Msk                     (0x1UL << CAN_F0R2_FB0_Pos)        /*!< 0x00000001 */
9062 #define CAN_F0R2_FB0                         CAN_F0R2_FB0_Msk                  /*!< Filter bit 0 */
9063 #define CAN_F0R2_FB1_Pos                     (1U)
9064 #define CAN_F0R2_FB1_Msk                     (0x1UL << CAN_F0R2_FB1_Pos)        /*!< 0x00000002 */
9065 #define CAN_F0R2_FB1                         CAN_F0R2_FB1_Msk                  /*!< Filter bit 1 */
9066 #define CAN_F0R2_FB2_Pos                     (2U)
9067 #define CAN_F0R2_FB2_Msk                     (0x1UL << CAN_F0R2_FB2_Pos)        /*!< 0x00000004 */
9068 #define CAN_F0R2_FB2                         CAN_F0R2_FB2_Msk                  /*!< Filter bit 2 */
9069 #define CAN_F0R2_FB3_Pos                     (3U)
9070 #define CAN_F0R2_FB3_Msk                     (0x1UL << CAN_F0R2_FB3_Pos)        /*!< 0x00000008 */
9071 #define CAN_F0R2_FB3                         CAN_F0R2_FB3_Msk                  /*!< Filter bit 3 */
9072 #define CAN_F0R2_FB4_Pos                     (4U)
9073 #define CAN_F0R2_FB4_Msk                     (0x1UL << CAN_F0R2_FB4_Pos)        /*!< 0x00000010 */
9074 #define CAN_F0R2_FB4                         CAN_F0R2_FB4_Msk                  /*!< Filter bit 4 */
9075 #define CAN_F0R2_FB5_Pos                     (5U)
9076 #define CAN_F0R2_FB5_Msk                     (0x1UL << CAN_F0R2_FB5_Pos)        /*!< 0x00000020 */
9077 #define CAN_F0R2_FB5                         CAN_F0R2_FB5_Msk                  /*!< Filter bit 5 */
9078 #define CAN_F0R2_FB6_Pos                     (6U)
9079 #define CAN_F0R2_FB6_Msk                     (0x1UL << CAN_F0R2_FB6_Pos)        /*!< 0x00000040 */
9080 #define CAN_F0R2_FB6                         CAN_F0R2_FB6_Msk                  /*!< Filter bit 6 */
9081 #define CAN_F0R2_FB7_Pos                     (7U)
9082 #define CAN_F0R2_FB7_Msk                     (0x1UL << CAN_F0R2_FB7_Pos)        /*!< 0x00000080 */
9083 #define CAN_F0R2_FB7                         CAN_F0R2_FB7_Msk                  /*!< Filter bit 7 */
9084 #define CAN_F0R2_FB8_Pos                     (8U)
9085 #define CAN_F0R2_FB8_Msk                     (0x1UL << CAN_F0R2_FB8_Pos)        /*!< 0x00000100 */
9086 #define CAN_F0R2_FB8                         CAN_F0R2_FB8_Msk                  /*!< Filter bit 8 */
9087 #define CAN_F0R2_FB9_Pos                     (9U)
9088 #define CAN_F0R2_FB9_Msk                     (0x1UL << CAN_F0R2_FB9_Pos)        /*!< 0x00000200 */
9089 #define CAN_F0R2_FB9                         CAN_F0R2_FB9_Msk                  /*!< Filter bit 9 */
9090 #define CAN_F0R2_FB10_Pos                    (10U)
9091 #define CAN_F0R2_FB10_Msk                    (0x1UL << CAN_F0R2_FB10_Pos)       /*!< 0x00000400 */
9092 #define CAN_F0R2_FB10                        CAN_F0R2_FB10_Msk                 /*!< Filter bit 10 */
9093 #define CAN_F0R2_FB11_Pos                    (11U)
9094 #define CAN_F0R2_FB11_Msk                    (0x1UL << CAN_F0R2_FB11_Pos)       /*!< 0x00000800 */
9095 #define CAN_F0R2_FB11                        CAN_F0R2_FB11_Msk                 /*!< Filter bit 11 */
9096 #define CAN_F0R2_FB12_Pos                    (12U)
9097 #define CAN_F0R2_FB12_Msk                    (0x1UL << CAN_F0R2_FB12_Pos)       /*!< 0x00001000 */
9098 #define CAN_F0R2_FB12                        CAN_F0R2_FB12_Msk                 /*!< Filter bit 12 */
9099 #define CAN_F0R2_FB13_Pos                    (13U)
9100 #define CAN_F0R2_FB13_Msk                    (0x1UL << CAN_F0R2_FB13_Pos)       /*!< 0x00002000 */
9101 #define CAN_F0R2_FB13                        CAN_F0R2_FB13_Msk                 /*!< Filter bit 13 */
9102 #define CAN_F0R2_FB14_Pos                    (14U)
9103 #define CAN_F0R2_FB14_Msk                    (0x1UL << CAN_F0R2_FB14_Pos)       /*!< 0x00004000 */
9104 #define CAN_F0R2_FB14                        CAN_F0R2_FB14_Msk                 /*!< Filter bit 14 */
9105 #define CAN_F0R2_FB15_Pos                    (15U)
9106 #define CAN_F0R2_FB15_Msk                    (0x1UL << CAN_F0R2_FB15_Pos)       /*!< 0x00008000 */
9107 #define CAN_F0R2_FB15                        CAN_F0R2_FB15_Msk                 /*!< Filter bit 15 */
9108 #define CAN_F0R2_FB16_Pos                    (16U)
9109 #define CAN_F0R2_FB16_Msk                    (0x1UL << CAN_F0R2_FB16_Pos)       /*!< 0x00010000 */
9110 #define CAN_F0R2_FB16                        CAN_F0R2_FB16_Msk                 /*!< Filter bit 16 */
9111 #define CAN_F0R2_FB17_Pos                    (17U)
9112 #define CAN_F0R2_FB17_Msk                    (0x1UL << CAN_F0R2_FB17_Pos)       /*!< 0x00020000 */
9113 #define CAN_F0R2_FB17                        CAN_F0R2_FB17_Msk                 /*!< Filter bit 17 */
9114 #define CAN_F0R2_FB18_Pos                    (18U)
9115 #define CAN_F0R2_FB18_Msk                    (0x1UL << CAN_F0R2_FB18_Pos)       /*!< 0x00040000 */
9116 #define CAN_F0R2_FB18                        CAN_F0R2_FB18_Msk                 /*!< Filter bit 18 */
9117 #define CAN_F0R2_FB19_Pos                    (19U)
9118 #define CAN_F0R2_FB19_Msk                    (0x1UL << CAN_F0R2_FB19_Pos)       /*!< 0x00080000 */
9119 #define CAN_F0R2_FB19                        CAN_F0R2_FB19_Msk                 /*!< Filter bit 19 */
9120 #define CAN_F0R2_FB20_Pos                    (20U)
9121 #define CAN_F0R2_FB20_Msk                    (0x1UL << CAN_F0R2_FB20_Pos)       /*!< 0x00100000 */
9122 #define CAN_F0R2_FB20                        CAN_F0R2_FB20_Msk                 /*!< Filter bit 20 */
9123 #define CAN_F0R2_FB21_Pos                    (21U)
9124 #define CAN_F0R2_FB21_Msk                    (0x1UL << CAN_F0R2_FB21_Pos)       /*!< 0x00200000 */
9125 #define CAN_F0R2_FB21                        CAN_F0R2_FB21_Msk                 /*!< Filter bit 21 */
9126 #define CAN_F0R2_FB22_Pos                    (22U)
9127 #define CAN_F0R2_FB22_Msk                    (0x1UL << CAN_F0R2_FB22_Pos)       /*!< 0x00400000 */
9128 #define CAN_F0R2_FB22                        CAN_F0R2_FB22_Msk                 /*!< Filter bit 22 */
9129 #define CAN_F0R2_FB23_Pos                    (23U)
9130 #define CAN_F0R2_FB23_Msk                    (0x1UL << CAN_F0R2_FB23_Pos)       /*!< 0x00800000 */
9131 #define CAN_F0R2_FB23                        CAN_F0R2_FB23_Msk                 /*!< Filter bit 23 */
9132 #define CAN_F0R2_FB24_Pos                    (24U)
9133 #define CAN_F0R2_FB24_Msk                    (0x1UL << CAN_F0R2_FB24_Pos)       /*!< 0x01000000 */
9134 #define CAN_F0R2_FB24                        CAN_F0R2_FB24_Msk                 /*!< Filter bit 24 */
9135 #define CAN_F0R2_FB25_Pos                    (25U)
9136 #define CAN_F0R2_FB25_Msk                    (0x1UL << CAN_F0R2_FB25_Pos)       /*!< 0x02000000 */
9137 #define CAN_F0R2_FB25                        CAN_F0R2_FB25_Msk                 /*!< Filter bit 25 */
9138 #define CAN_F0R2_FB26_Pos                    (26U)
9139 #define CAN_F0R2_FB26_Msk                    (0x1UL << CAN_F0R2_FB26_Pos)       /*!< 0x04000000 */
9140 #define CAN_F0R2_FB26                        CAN_F0R2_FB26_Msk                 /*!< Filter bit 26 */
9141 #define CAN_F0R2_FB27_Pos                    (27U)
9142 #define CAN_F0R2_FB27_Msk                    (0x1UL << CAN_F0R2_FB27_Pos)       /*!< 0x08000000 */
9143 #define CAN_F0R2_FB27                        CAN_F0R2_FB27_Msk                 /*!< Filter bit 27 */
9144 #define CAN_F0R2_FB28_Pos                    (28U)
9145 #define CAN_F0R2_FB28_Msk                    (0x1UL << CAN_F0R2_FB28_Pos)       /*!< 0x10000000 */
9146 #define CAN_F0R2_FB28                        CAN_F0R2_FB28_Msk                 /*!< Filter bit 28 */
9147 #define CAN_F0R2_FB29_Pos                    (29U)
9148 #define CAN_F0R2_FB29_Msk                    (0x1UL << CAN_F0R2_FB29_Pos)       /*!< 0x20000000 */
9149 #define CAN_F0R2_FB29                        CAN_F0R2_FB29_Msk                 /*!< Filter bit 29 */
9150 #define CAN_F0R2_FB30_Pos                    (30U)
9151 #define CAN_F0R2_FB30_Msk                    (0x1UL << CAN_F0R2_FB30_Pos)       /*!< 0x40000000 */
9152 #define CAN_F0R2_FB30                        CAN_F0R2_FB30_Msk                 /*!< Filter bit 30 */
9153 #define CAN_F0R2_FB31_Pos                    (31U)
9154 #define CAN_F0R2_FB31_Msk                    (0x1UL << CAN_F0R2_FB31_Pos)       /*!< 0x80000000 */
9155 #define CAN_F0R2_FB31                        CAN_F0R2_FB31_Msk                 /*!< Filter bit 31 */
9156 
9157 /*******************  Bit definition for CAN_F1R2 register  *******************/
9158 #define CAN_F1R2_FB0_Pos                     (0U)
9159 #define CAN_F1R2_FB0_Msk                     (0x1UL << CAN_F1R2_FB0_Pos)        /*!< 0x00000001 */
9160 #define CAN_F1R2_FB0                         CAN_F1R2_FB0_Msk                  /*!< Filter bit 0 */
9161 #define CAN_F1R2_FB1_Pos                     (1U)
9162 #define CAN_F1R2_FB1_Msk                     (0x1UL << CAN_F1R2_FB1_Pos)        /*!< 0x00000002 */
9163 #define CAN_F1R2_FB1                         CAN_F1R2_FB1_Msk                  /*!< Filter bit 1 */
9164 #define CAN_F1R2_FB2_Pos                     (2U)
9165 #define CAN_F1R2_FB2_Msk                     (0x1UL << CAN_F1R2_FB2_Pos)        /*!< 0x00000004 */
9166 #define CAN_F1R2_FB2                         CAN_F1R2_FB2_Msk                  /*!< Filter bit 2 */
9167 #define CAN_F1R2_FB3_Pos                     (3U)
9168 #define CAN_F1R2_FB3_Msk                     (0x1UL << CAN_F1R2_FB3_Pos)        /*!< 0x00000008 */
9169 #define CAN_F1R2_FB3                         CAN_F1R2_FB3_Msk                  /*!< Filter bit 3 */
9170 #define CAN_F1R2_FB4_Pos                     (4U)
9171 #define CAN_F1R2_FB4_Msk                     (0x1UL << CAN_F1R2_FB4_Pos)        /*!< 0x00000010 */
9172 #define CAN_F1R2_FB4                         CAN_F1R2_FB4_Msk                  /*!< Filter bit 4 */
9173 #define CAN_F1R2_FB5_Pos                     (5U)
9174 #define CAN_F1R2_FB5_Msk                     (0x1UL << CAN_F1R2_FB5_Pos)        /*!< 0x00000020 */
9175 #define CAN_F1R2_FB5                         CAN_F1R2_FB5_Msk                  /*!< Filter bit 5 */
9176 #define CAN_F1R2_FB6_Pos                     (6U)
9177 #define CAN_F1R2_FB6_Msk                     (0x1UL << CAN_F1R2_FB6_Pos)        /*!< 0x00000040 */
9178 #define CAN_F1R2_FB6                         CAN_F1R2_FB6_Msk                  /*!< Filter bit 6 */
9179 #define CAN_F1R2_FB7_Pos                     (7U)
9180 #define CAN_F1R2_FB7_Msk                     (0x1UL << CAN_F1R2_FB7_Pos)        /*!< 0x00000080 */
9181 #define CAN_F1R2_FB7                         CAN_F1R2_FB7_Msk                  /*!< Filter bit 7 */
9182 #define CAN_F1R2_FB8_Pos                     (8U)
9183 #define CAN_F1R2_FB8_Msk                     (0x1UL << CAN_F1R2_FB8_Pos)        /*!< 0x00000100 */
9184 #define CAN_F1R2_FB8                         CAN_F1R2_FB8_Msk                  /*!< Filter bit 8 */
9185 #define CAN_F1R2_FB9_Pos                     (9U)
9186 #define CAN_F1R2_FB9_Msk                     (0x1UL << CAN_F1R2_FB9_Pos)        /*!< 0x00000200 */
9187 #define CAN_F1R2_FB9                         CAN_F1R2_FB9_Msk                  /*!< Filter bit 9 */
9188 #define CAN_F1R2_FB10_Pos                    (10U)
9189 #define CAN_F1R2_FB10_Msk                    (0x1UL << CAN_F1R2_FB10_Pos)       /*!< 0x00000400 */
9190 #define CAN_F1R2_FB10                        CAN_F1R2_FB10_Msk                 /*!< Filter bit 10 */
9191 #define CAN_F1R2_FB11_Pos                    (11U)
9192 #define CAN_F1R2_FB11_Msk                    (0x1UL << CAN_F1R2_FB11_Pos)       /*!< 0x00000800 */
9193 #define CAN_F1R2_FB11                        CAN_F1R2_FB11_Msk                 /*!< Filter bit 11 */
9194 #define CAN_F1R2_FB12_Pos                    (12U)
9195 #define CAN_F1R2_FB12_Msk                    (0x1UL << CAN_F1R2_FB12_Pos)       /*!< 0x00001000 */
9196 #define CAN_F1R2_FB12                        CAN_F1R2_FB12_Msk                 /*!< Filter bit 12 */
9197 #define CAN_F1R2_FB13_Pos                    (13U)
9198 #define CAN_F1R2_FB13_Msk                    (0x1UL << CAN_F1R2_FB13_Pos)       /*!< 0x00002000 */
9199 #define CAN_F1R2_FB13                        CAN_F1R2_FB13_Msk                 /*!< Filter bit 13 */
9200 #define CAN_F1R2_FB14_Pos                    (14U)
9201 #define CAN_F1R2_FB14_Msk                    (0x1UL << CAN_F1R2_FB14_Pos)       /*!< 0x00004000 */
9202 #define CAN_F1R2_FB14                        CAN_F1R2_FB14_Msk                 /*!< Filter bit 14 */
9203 #define CAN_F1R2_FB15_Pos                    (15U)
9204 #define CAN_F1R2_FB15_Msk                    (0x1UL << CAN_F1R2_FB15_Pos)       /*!< 0x00008000 */
9205 #define CAN_F1R2_FB15                        CAN_F1R2_FB15_Msk                 /*!< Filter bit 15 */
9206 #define CAN_F1R2_FB16_Pos                    (16U)
9207 #define CAN_F1R2_FB16_Msk                    (0x1UL << CAN_F1R2_FB16_Pos)       /*!< 0x00010000 */
9208 #define CAN_F1R2_FB16                        CAN_F1R2_FB16_Msk                 /*!< Filter bit 16 */
9209 #define CAN_F1R2_FB17_Pos                    (17U)
9210 #define CAN_F1R2_FB17_Msk                    (0x1UL << CAN_F1R2_FB17_Pos)       /*!< 0x00020000 */
9211 #define CAN_F1R2_FB17                        CAN_F1R2_FB17_Msk                 /*!< Filter bit 17 */
9212 #define CAN_F1R2_FB18_Pos                    (18U)
9213 #define CAN_F1R2_FB18_Msk                    (0x1UL << CAN_F1R2_FB18_Pos)       /*!< 0x00040000 */
9214 #define CAN_F1R2_FB18                        CAN_F1R2_FB18_Msk                 /*!< Filter bit 18 */
9215 #define CAN_F1R2_FB19_Pos                    (19U)
9216 #define CAN_F1R2_FB19_Msk                    (0x1UL << CAN_F1R2_FB19_Pos)       /*!< 0x00080000 */
9217 #define CAN_F1R2_FB19                        CAN_F1R2_FB19_Msk                 /*!< Filter bit 19 */
9218 #define CAN_F1R2_FB20_Pos                    (20U)
9219 #define CAN_F1R2_FB20_Msk                    (0x1UL << CAN_F1R2_FB20_Pos)       /*!< 0x00100000 */
9220 #define CAN_F1R2_FB20                        CAN_F1R2_FB20_Msk                 /*!< Filter bit 20 */
9221 #define CAN_F1R2_FB21_Pos                    (21U)
9222 #define CAN_F1R2_FB21_Msk                    (0x1UL << CAN_F1R2_FB21_Pos)       /*!< 0x00200000 */
9223 #define CAN_F1R2_FB21                        CAN_F1R2_FB21_Msk                 /*!< Filter bit 21 */
9224 #define CAN_F1R2_FB22_Pos                    (22U)
9225 #define CAN_F1R2_FB22_Msk                    (0x1UL << CAN_F1R2_FB22_Pos)       /*!< 0x00400000 */
9226 #define CAN_F1R2_FB22                        CAN_F1R2_FB22_Msk                 /*!< Filter bit 22 */
9227 #define CAN_F1R2_FB23_Pos                    (23U)
9228 #define CAN_F1R2_FB23_Msk                    (0x1UL << CAN_F1R2_FB23_Pos)       /*!< 0x00800000 */
9229 #define CAN_F1R2_FB23                        CAN_F1R2_FB23_Msk                 /*!< Filter bit 23 */
9230 #define CAN_F1R2_FB24_Pos                    (24U)
9231 #define CAN_F1R2_FB24_Msk                    (0x1UL << CAN_F1R2_FB24_Pos)       /*!< 0x01000000 */
9232 #define CAN_F1R2_FB24                        CAN_F1R2_FB24_Msk                 /*!< Filter bit 24 */
9233 #define CAN_F1R2_FB25_Pos                    (25U)
9234 #define CAN_F1R2_FB25_Msk                    (0x1UL << CAN_F1R2_FB25_Pos)       /*!< 0x02000000 */
9235 #define CAN_F1R2_FB25                        CAN_F1R2_FB25_Msk                 /*!< Filter bit 25 */
9236 #define CAN_F1R2_FB26_Pos                    (26U)
9237 #define CAN_F1R2_FB26_Msk                    (0x1UL << CAN_F1R2_FB26_Pos)       /*!< 0x04000000 */
9238 #define CAN_F1R2_FB26                        CAN_F1R2_FB26_Msk                 /*!< Filter bit 26 */
9239 #define CAN_F1R2_FB27_Pos                    (27U)
9240 #define CAN_F1R2_FB27_Msk                    (0x1UL << CAN_F1R2_FB27_Pos)       /*!< 0x08000000 */
9241 #define CAN_F1R2_FB27                        CAN_F1R2_FB27_Msk                 /*!< Filter bit 27 */
9242 #define CAN_F1R2_FB28_Pos                    (28U)
9243 #define CAN_F1R2_FB28_Msk                    (0x1UL << CAN_F1R2_FB28_Pos)       /*!< 0x10000000 */
9244 #define CAN_F1R2_FB28                        CAN_F1R2_FB28_Msk                 /*!< Filter bit 28 */
9245 #define CAN_F1R2_FB29_Pos                    (29U)
9246 #define CAN_F1R2_FB29_Msk                    (0x1UL << CAN_F1R2_FB29_Pos)       /*!< 0x20000000 */
9247 #define CAN_F1R2_FB29                        CAN_F1R2_FB29_Msk                 /*!< Filter bit 29 */
9248 #define CAN_F1R2_FB30_Pos                    (30U)
9249 #define CAN_F1R2_FB30_Msk                    (0x1UL << CAN_F1R2_FB30_Pos)       /*!< 0x40000000 */
9250 #define CAN_F1R2_FB30                        CAN_F1R2_FB30_Msk                 /*!< Filter bit 30 */
9251 #define CAN_F1R2_FB31_Pos                    (31U)
9252 #define CAN_F1R2_FB31_Msk                    (0x1UL << CAN_F1R2_FB31_Pos)       /*!< 0x80000000 */
9253 #define CAN_F1R2_FB31                        CAN_F1R2_FB31_Msk                 /*!< Filter bit 31 */
9254 
9255 /*******************  Bit definition for CAN_F2R2 register  *******************/
9256 #define CAN_F2R2_FB0_Pos                     (0U)
9257 #define CAN_F2R2_FB0_Msk                     (0x1UL << CAN_F2R2_FB0_Pos)        /*!< 0x00000001 */
9258 #define CAN_F2R2_FB0                         CAN_F2R2_FB0_Msk                  /*!< Filter bit 0 */
9259 #define CAN_F2R2_FB1_Pos                     (1U)
9260 #define CAN_F2R2_FB1_Msk                     (0x1UL << CAN_F2R2_FB1_Pos)        /*!< 0x00000002 */
9261 #define CAN_F2R2_FB1                         CAN_F2R2_FB1_Msk                  /*!< Filter bit 1 */
9262 #define CAN_F2R2_FB2_Pos                     (2U)
9263 #define CAN_F2R2_FB2_Msk                     (0x1UL << CAN_F2R2_FB2_Pos)        /*!< 0x00000004 */
9264 #define CAN_F2R2_FB2                         CAN_F2R2_FB2_Msk                  /*!< Filter bit 2 */
9265 #define CAN_F2R2_FB3_Pos                     (3U)
9266 #define CAN_F2R2_FB3_Msk                     (0x1UL << CAN_F2R2_FB3_Pos)        /*!< 0x00000008 */
9267 #define CAN_F2R2_FB3                         CAN_F2R2_FB3_Msk                  /*!< Filter bit 3 */
9268 #define CAN_F2R2_FB4_Pos                     (4U)
9269 #define CAN_F2R2_FB4_Msk                     (0x1UL << CAN_F2R2_FB4_Pos)        /*!< 0x00000010 */
9270 #define CAN_F2R2_FB4                         CAN_F2R2_FB4_Msk                  /*!< Filter bit 4 */
9271 #define CAN_F2R2_FB5_Pos                     (5U)
9272 #define CAN_F2R2_FB5_Msk                     (0x1UL << CAN_F2R2_FB5_Pos)        /*!< 0x00000020 */
9273 #define CAN_F2R2_FB5                         CAN_F2R2_FB5_Msk                  /*!< Filter bit 5 */
9274 #define CAN_F2R2_FB6_Pos                     (6U)
9275 #define CAN_F2R2_FB6_Msk                     (0x1UL << CAN_F2R2_FB6_Pos)        /*!< 0x00000040 */
9276 #define CAN_F2R2_FB6                         CAN_F2R2_FB6_Msk                  /*!< Filter bit 6 */
9277 #define CAN_F2R2_FB7_Pos                     (7U)
9278 #define CAN_F2R2_FB7_Msk                     (0x1UL << CAN_F2R2_FB7_Pos)        /*!< 0x00000080 */
9279 #define CAN_F2R2_FB7                         CAN_F2R2_FB7_Msk                  /*!< Filter bit 7 */
9280 #define CAN_F2R2_FB8_Pos                     (8U)
9281 #define CAN_F2R2_FB8_Msk                     (0x1UL << CAN_F2R2_FB8_Pos)        /*!< 0x00000100 */
9282 #define CAN_F2R2_FB8                         CAN_F2R2_FB8_Msk                  /*!< Filter bit 8 */
9283 #define CAN_F2R2_FB9_Pos                     (9U)
9284 #define CAN_F2R2_FB9_Msk                     (0x1UL << CAN_F2R2_FB9_Pos)        /*!< 0x00000200 */
9285 #define CAN_F2R2_FB9                         CAN_F2R2_FB9_Msk                  /*!< Filter bit 9 */
9286 #define CAN_F2R2_FB10_Pos                    (10U)
9287 #define CAN_F2R2_FB10_Msk                    (0x1UL << CAN_F2R2_FB10_Pos)       /*!< 0x00000400 */
9288 #define CAN_F2R2_FB10                        CAN_F2R2_FB10_Msk                 /*!< Filter bit 10 */
9289 #define CAN_F2R2_FB11_Pos                    (11U)
9290 #define CAN_F2R2_FB11_Msk                    (0x1UL << CAN_F2R2_FB11_Pos)       /*!< 0x00000800 */
9291 #define CAN_F2R2_FB11                        CAN_F2R2_FB11_Msk                 /*!< Filter bit 11 */
9292 #define CAN_F2R2_FB12_Pos                    (12U)
9293 #define CAN_F2R2_FB12_Msk                    (0x1UL << CAN_F2R2_FB12_Pos)       /*!< 0x00001000 */
9294 #define CAN_F2R2_FB12                        CAN_F2R2_FB12_Msk                 /*!< Filter bit 12 */
9295 #define CAN_F2R2_FB13_Pos                    (13U)
9296 #define CAN_F2R2_FB13_Msk                    (0x1UL << CAN_F2R2_FB13_Pos)       /*!< 0x00002000 */
9297 #define CAN_F2R2_FB13                        CAN_F2R2_FB13_Msk                 /*!< Filter bit 13 */
9298 #define CAN_F2R2_FB14_Pos                    (14U)
9299 #define CAN_F2R2_FB14_Msk                    (0x1UL << CAN_F2R2_FB14_Pos)       /*!< 0x00004000 */
9300 #define CAN_F2R2_FB14                        CAN_F2R2_FB14_Msk                 /*!< Filter bit 14 */
9301 #define CAN_F2R2_FB15_Pos                    (15U)
9302 #define CAN_F2R2_FB15_Msk                    (0x1UL << CAN_F2R2_FB15_Pos)       /*!< 0x00008000 */
9303 #define CAN_F2R2_FB15                        CAN_F2R2_FB15_Msk                 /*!< Filter bit 15 */
9304 #define CAN_F2R2_FB16_Pos                    (16U)
9305 #define CAN_F2R2_FB16_Msk                    (0x1UL << CAN_F2R2_FB16_Pos)       /*!< 0x00010000 */
9306 #define CAN_F2R2_FB16                        CAN_F2R2_FB16_Msk                 /*!< Filter bit 16 */
9307 #define CAN_F2R2_FB17_Pos                    (17U)
9308 #define CAN_F2R2_FB17_Msk                    (0x1UL << CAN_F2R2_FB17_Pos)       /*!< 0x00020000 */
9309 #define CAN_F2R2_FB17                        CAN_F2R2_FB17_Msk                 /*!< Filter bit 17 */
9310 #define CAN_F2R2_FB18_Pos                    (18U)
9311 #define CAN_F2R2_FB18_Msk                    (0x1UL << CAN_F2R2_FB18_Pos)       /*!< 0x00040000 */
9312 #define CAN_F2R2_FB18                        CAN_F2R2_FB18_Msk                 /*!< Filter bit 18 */
9313 #define CAN_F2R2_FB19_Pos                    (19U)
9314 #define CAN_F2R2_FB19_Msk                    (0x1UL << CAN_F2R2_FB19_Pos)       /*!< 0x00080000 */
9315 #define CAN_F2R2_FB19                        CAN_F2R2_FB19_Msk                 /*!< Filter bit 19 */
9316 #define CAN_F2R2_FB20_Pos                    (20U)
9317 #define CAN_F2R2_FB20_Msk                    (0x1UL << CAN_F2R2_FB20_Pos)       /*!< 0x00100000 */
9318 #define CAN_F2R2_FB20                        CAN_F2R2_FB20_Msk                 /*!< Filter bit 20 */
9319 #define CAN_F2R2_FB21_Pos                    (21U)
9320 #define CAN_F2R2_FB21_Msk                    (0x1UL << CAN_F2R2_FB21_Pos)       /*!< 0x00200000 */
9321 #define CAN_F2R2_FB21                        CAN_F2R2_FB21_Msk                 /*!< Filter bit 21 */
9322 #define CAN_F2R2_FB22_Pos                    (22U)
9323 #define CAN_F2R2_FB22_Msk                    (0x1UL << CAN_F2R2_FB22_Pos)       /*!< 0x00400000 */
9324 #define CAN_F2R2_FB22                        CAN_F2R2_FB22_Msk                 /*!< Filter bit 22 */
9325 #define CAN_F2R2_FB23_Pos                    (23U)
9326 #define CAN_F2R2_FB23_Msk                    (0x1UL << CAN_F2R2_FB23_Pos)       /*!< 0x00800000 */
9327 #define CAN_F2R2_FB23                        CAN_F2R2_FB23_Msk                 /*!< Filter bit 23 */
9328 #define CAN_F2R2_FB24_Pos                    (24U)
9329 #define CAN_F2R2_FB24_Msk                    (0x1UL << CAN_F2R2_FB24_Pos)       /*!< 0x01000000 */
9330 #define CAN_F2R2_FB24                        CAN_F2R2_FB24_Msk                 /*!< Filter bit 24 */
9331 #define CAN_F2R2_FB25_Pos                    (25U)
9332 #define CAN_F2R2_FB25_Msk                    (0x1UL << CAN_F2R2_FB25_Pos)       /*!< 0x02000000 */
9333 #define CAN_F2R2_FB25                        CAN_F2R2_FB25_Msk                 /*!< Filter bit 25 */
9334 #define CAN_F2R2_FB26_Pos                    (26U)
9335 #define CAN_F2R2_FB26_Msk                    (0x1UL << CAN_F2R2_FB26_Pos)       /*!< 0x04000000 */
9336 #define CAN_F2R2_FB26                        CAN_F2R2_FB26_Msk                 /*!< Filter bit 26 */
9337 #define CAN_F2R2_FB27_Pos                    (27U)
9338 #define CAN_F2R2_FB27_Msk                    (0x1UL << CAN_F2R2_FB27_Pos)       /*!< 0x08000000 */
9339 #define CAN_F2R2_FB27                        CAN_F2R2_FB27_Msk                 /*!< Filter bit 27 */
9340 #define CAN_F2R2_FB28_Pos                    (28U)
9341 #define CAN_F2R2_FB28_Msk                    (0x1UL << CAN_F2R2_FB28_Pos)       /*!< 0x10000000 */
9342 #define CAN_F2R2_FB28                        CAN_F2R2_FB28_Msk                 /*!< Filter bit 28 */
9343 #define CAN_F2R2_FB29_Pos                    (29U)
9344 #define CAN_F2R2_FB29_Msk                    (0x1UL << CAN_F2R2_FB29_Pos)       /*!< 0x20000000 */
9345 #define CAN_F2R2_FB29                        CAN_F2R2_FB29_Msk                 /*!< Filter bit 29 */
9346 #define CAN_F2R2_FB30_Pos                    (30U)
9347 #define CAN_F2R2_FB30_Msk                    (0x1UL << CAN_F2R2_FB30_Pos)       /*!< 0x40000000 */
9348 #define CAN_F2R2_FB30                        CAN_F2R2_FB30_Msk                 /*!< Filter bit 30 */
9349 #define CAN_F2R2_FB31_Pos                    (31U)
9350 #define CAN_F2R2_FB31_Msk                    (0x1UL << CAN_F2R2_FB31_Pos)       /*!< 0x80000000 */
9351 #define CAN_F2R2_FB31                        CAN_F2R2_FB31_Msk                 /*!< Filter bit 31 */
9352 
9353 /*******************  Bit definition for CAN_F3R2 register  *******************/
9354 #define CAN_F3R2_FB0_Pos                     (0U)
9355 #define CAN_F3R2_FB0_Msk                     (0x1UL << CAN_F3R2_FB0_Pos)        /*!< 0x00000001 */
9356 #define CAN_F3R2_FB0                         CAN_F3R2_FB0_Msk                  /*!< Filter bit 0 */
9357 #define CAN_F3R2_FB1_Pos                     (1U)
9358 #define CAN_F3R2_FB1_Msk                     (0x1UL << CAN_F3R2_FB1_Pos)        /*!< 0x00000002 */
9359 #define CAN_F3R2_FB1                         CAN_F3R2_FB1_Msk                  /*!< Filter bit 1 */
9360 #define CAN_F3R2_FB2_Pos                     (2U)
9361 #define CAN_F3R2_FB2_Msk                     (0x1UL << CAN_F3R2_FB2_Pos)        /*!< 0x00000004 */
9362 #define CAN_F3R2_FB2                         CAN_F3R2_FB2_Msk                  /*!< Filter bit 2 */
9363 #define CAN_F3R2_FB3_Pos                     (3U)
9364 #define CAN_F3R2_FB3_Msk                     (0x1UL << CAN_F3R2_FB3_Pos)        /*!< 0x00000008 */
9365 #define CAN_F3R2_FB3                         CAN_F3R2_FB3_Msk                  /*!< Filter bit 3 */
9366 #define CAN_F3R2_FB4_Pos                     (4U)
9367 #define CAN_F3R2_FB4_Msk                     (0x1UL << CAN_F3R2_FB4_Pos)        /*!< 0x00000010 */
9368 #define CAN_F3R2_FB4                         CAN_F3R2_FB4_Msk                  /*!< Filter bit 4 */
9369 #define CAN_F3R2_FB5_Pos                     (5U)
9370 #define CAN_F3R2_FB5_Msk                     (0x1UL << CAN_F3R2_FB5_Pos)        /*!< 0x00000020 */
9371 #define CAN_F3R2_FB5                         CAN_F3R2_FB5_Msk                  /*!< Filter bit 5 */
9372 #define CAN_F3R2_FB6_Pos                     (6U)
9373 #define CAN_F3R2_FB6_Msk                     (0x1UL << CAN_F3R2_FB6_Pos)        /*!< 0x00000040 */
9374 #define CAN_F3R2_FB6                         CAN_F3R2_FB6_Msk                  /*!< Filter bit 6 */
9375 #define CAN_F3R2_FB7_Pos                     (7U)
9376 #define CAN_F3R2_FB7_Msk                     (0x1UL << CAN_F3R2_FB7_Pos)        /*!< 0x00000080 */
9377 #define CAN_F3R2_FB7                         CAN_F3R2_FB7_Msk                  /*!< Filter bit 7 */
9378 #define CAN_F3R2_FB8_Pos                     (8U)
9379 #define CAN_F3R2_FB8_Msk                     (0x1UL << CAN_F3R2_FB8_Pos)        /*!< 0x00000100 */
9380 #define CAN_F3R2_FB8                         CAN_F3R2_FB8_Msk                  /*!< Filter bit 8 */
9381 #define CAN_F3R2_FB9_Pos                     (9U)
9382 #define CAN_F3R2_FB9_Msk                     (0x1UL << CAN_F3R2_FB9_Pos)        /*!< 0x00000200 */
9383 #define CAN_F3R2_FB9                         CAN_F3R2_FB9_Msk                  /*!< Filter bit 9 */
9384 #define CAN_F3R2_FB10_Pos                    (10U)
9385 #define CAN_F3R2_FB10_Msk                    (0x1UL << CAN_F3R2_FB10_Pos)       /*!< 0x00000400 */
9386 #define CAN_F3R2_FB10                        CAN_F3R2_FB10_Msk                 /*!< Filter bit 10 */
9387 #define CAN_F3R2_FB11_Pos                    (11U)
9388 #define CAN_F3R2_FB11_Msk                    (0x1UL << CAN_F3R2_FB11_Pos)       /*!< 0x00000800 */
9389 #define CAN_F3R2_FB11                        CAN_F3R2_FB11_Msk                 /*!< Filter bit 11 */
9390 #define CAN_F3R2_FB12_Pos                    (12U)
9391 #define CAN_F3R2_FB12_Msk                    (0x1UL << CAN_F3R2_FB12_Pos)       /*!< 0x00001000 */
9392 #define CAN_F3R2_FB12                        CAN_F3R2_FB12_Msk                 /*!< Filter bit 12 */
9393 #define CAN_F3R2_FB13_Pos                    (13U)
9394 #define CAN_F3R2_FB13_Msk                    (0x1UL << CAN_F3R2_FB13_Pos)       /*!< 0x00002000 */
9395 #define CAN_F3R2_FB13                        CAN_F3R2_FB13_Msk                 /*!< Filter bit 13 */
9396 #define CAN_F3R2_FB14_Pos                    (14U)
9397 #define CAN_F3R2_FB14_Msk                    (0x1UL << CAN_F3R2_FB14_Pos)       /*!< 0x00004000 */
9398 #define CAN_F3R2_FB14                        CAN_F3R2_FB14_Msk                 /*!< Filter bit 14 */
9399 #define CAN_F3R2_FB15_Pos                    (15U)
9400 #define CAN_F3R2_FB15_Msk                    (0x1UL << CAN_F3R2_FB15_Pos)       /*!< 0x00008000 */
9401 #define CAN_F3R2_FB15                        CAN_F3R2_FB15_Msk                 /*!< Filter bit 15 */
9402 #define CAN_F3R2_FB16_Pos                    (16U)
9403 #define CAN_F3R2_FB16_Msk                    (0x1UL << CAN_F3R2_FB16_Pos)       /*!< 0x00010000 */
9404 #define CAN_F3R2_FB16                        CAN_F3R2_FB16_Msk                 /*!< Filter bit 16 */
9405 #define CAN_F3R2_FB17_Pos                    (17U)
9406 #define CAN_F3R2_FB17_Msk                    (0x1UL << CAN_F3R2_FB17_Pos)       /*!< 0x00020000 */
9407 #define CAN_F3R2_FB17                        CAN_F3R2_FB17_Msk                 /*!< Filter bit 17 */
9408 #define CAN_F3R2_FB18_Pos                    (18U)
9409 #define CAN_F3R2_FB18_Msk                    (0x1UL << CAN_F3R2_FB18_Pos)       /*!< 0x00040000 */
9410 #define CAN_F3R2_FB18                        CAN_F3R2_FB18_Msk                 /*!< Filter bit 18 */
9411 #define CAN_F3R2_FB19_Pos                    (19U)
9412 #define CAN_F3R2_FB19_Msk                    (0x1UL << CAN_F3R2_FB19_Pos)       /*!< 0x00080000 */
9413 #define CAN_F3R2_FB19                        CAN_F3R2_FB19_Msk                 /*!< Filter bit 19 */
9414 #define CAN_F3R2_FB20_Pos                    (20U)
9415 #define CAN_F3R2_FB20_Msk                    (0x1UL << CAN_F3R2_FB20_Pos)       /*!< 0x00100000 */
9416 #define CAN_F3R2_FB20                        CAN_F3R2_FB20_Msk                 /*!< Filter bit 20 */
9417 #define CAN_F3R2_FB21_Pos                    (21U)
9418 #define CAN_F3R2_FB21_Msk                    (0x1UL << CAN_F3R2_FB21_Pos)       /*!< 0x00200000 */
9419 #define CAN_F3R2_FB21                        CAN_F3R2_FB21_Msk                 /*!< Filter bit 21 */
9420 #define CAN_F3R2_FB22_Pos                    (22U)
9421 #define CAN_F3R2_FB22_Msk                    (0x1UL << CAN_F3R2_FB22_Pos)       /*!< 0x00400000 */
9422 #define CAN_F3R2_FB22                        CAN_F3R2_FB22_Msk                 /*!< Filter bit 22 */
9423 #define CAN_F3R2_FB23_Pos                    (23U)
9424 #define CAN_F3R2_FB23_Msk                    (0x1UL << CAN_F3R2_FB23_Pos)       /*!< 0x00800000 */
9425 #define CAN_F3R2_FB23                        CAN_F3R2_FB23_Msk                 /*!< Filter bit 23 */
9426 #define CAN_F3R2_FB24_Pos                    (24U)
9427 #define CAN_F3R2_FB24_Msk                    (0x1UL << CAN_F3R2_FB24_Pos)       /*!< 0x01000000 */
9428 #define CAN_F3R2_FB24                        CAN_F3R2_FB24_Msk                 /*!< Filter bit 24 */
9429 #define CAN_F3R2_FB25_Pos                    (25U)
9430 #define CAN_F3R2_FB25_Msk                    (0x1UL << CAN_F3R2_FB25_Pos)       /*!< 0x02000000 */
9431 #define CAN_F3R2_FB25                        CAN_F3R2_FB25_Msk                 /*!< Filter bit 25 */
9432 #define CAN_F3R2_FB26_Pos                    (26U)
9433 #define CAN_F3R2_FB26_Msk                    (0x1UL << CAN_F3R2_FB26_Pos)       /*!< 0x04000000 */
9434 #define CAN_F3R2_FB26                        CAN_F3R2_FB26_Msk                 /*!< Filter bit 26 */
9435 #define CAN_F3R2_FB27_Pos                    (27U)
9436 #define CAN_F3R2_FB27_Msk                    (0x1UL << CAN_F3R2_FB27_Pos)       /*!< 0x08000000 */
9437 #define CAN_F3R2_FB27                        CAN_F3R2_FB27_Msk                 /*!< Filter bit 27 */
9438 #define CAN_F3R2_FB28_Pos                    (28U)
9439 #define CAN_F3R2_FB28_Msk                    (0x1UL << CAN_F3R2_FB28_Pos)       /*!< 0x10000000 */
9440 #define CAN_F3R2_FB28                        CAN_F3R2_FB28_Msk                 /*!< Filter bit 28 */
9441 #define CAN_F3R2_FB29_Pos                    (29U)
9442 #define CAN_F3R2_FB29_Msk                    (0x1UL << CAN_F3R2_FB29_Pos)       /*!< 0x20000000 */
9443 #define CAN_F3R2_FB29                        CAN_F3R2_FB29_Msk                 /*!< Filter bit 29 */
9444 #define CAN_F3R2_FB30_Pos                    (30U)
9445 #define CAN_F3R2_FB30_Msk                    (0x1UL << CAN_F3R2_FB30_Pos)       /*!< 0x40000000 */
9446 #define CAN_F3R2_FB30                        CAN_F3R2_FB30_Msk                 /*!< Filter bit 30 */
9447 #define CAN_F3R2_FB31_Pos                    (31U)
9448 #define CAN_F3R2_FB31_Msk                    (0x1UL << CAN_F3R2_FB31_Pos)       /*!< 0x80000000 */
9449 #define CAN_F3R2_FB31                        CAN_F3R2_FB31_Msk                 /*!< Filter bit 31 */
9450 
9451 /*******************  Bit definition for CAN_F4R2 register  *******************/
9452 #define CAN_F4R2_FB0_Pos                     (0U)
9453 #define CAN_F4R2_FB0_Msk                     (0x1UL << CAN_F4R2_FB0_Pos)        /*!< 0x00000001 */
9454 #define CAN_F4R2_FB0                         CAN_F4R2_FB0_Msk                  /*!< Filter bit 0 */
9455 #define CAN_F4R2_FB1_Pos                     (1U)
9456 #define CAN_F4R2_FB1_Msk                     (0x1UL << CAN_F4R2_FB1_Pos)        /*!< 0x00000002 */
9457 #define CAN_F4R2_FB1                         CAN_F4R2_FB1_Msk                  /*!< Filter bit 1 */
9458 #define CAN_F4R2_FB2_Pos                     (2U)
9459 #define CAN_F4R2_FB2_Msk                     (0x1UL << CAN_F4R2_FB2_Pos)        /*!< 0x00000004 */
9460 #define CAN_F4R2_FB2                         CAN_F4R2_FB2_Msk                  /*!< Filter bit 2 */
9461 #define CAN_F4R2_FB3_Pos                     (3U)
9462 #define CAN_F4R2_FB3_Msk                     (0x1UL << CAN_F4R2_FB3_Pos)        /*!< 0x00000008 */
9463 #define CAN_F4R2_FB3                         CAN_F4R2_FB3_Msk                  /*!< Filter bit 3 */
9464 #define CAN_F4R2_FB4_Pos                     (4U)
9465 #define CAN_F4R2_FB4_Msk                     (0x1UL << CAN_F4R2_FB4_Pos)        /*!< 0x00000010 */
9466 #define CAN_F4R2_FB4                         CAN_F4R2_FB4_Msk                  /*!< Filter bit 4 */
9467 #define CAN_F4R2_FB5_Pos                     (5U)
9468 #define CAN_F4R2_FB5_Msk                     (0x1UL << CAN_F4R2_FB5_Pos)        /*!< 0x00000020 */
9469 #define CAN_F4R2_FB5                         CAN_F4R2_FB5_Msk                  /*!< Filter bit 5 */
9470 #define CAN_F4R2_FB6_Pos                     (6U)
9471 #define CAN_F4R2_FB6_Msk                     (0x1UL << CAN_F4R2_FB6_Pos)        /*!< 0x00000040 */
9472 #define CAN_F4R2_FB6                         CAN_F4R2_FB6_Msk                  /*!< Filter bit 6 */
9473 #define CAN_F4R2_FB7_Pos                     (7U)
9474 #define CAN_F4R2_FB7_Msk                     (0x1UL << CAN_F4R2_FB7_Pos)        /*!< 0x00000080 */
9475 #define CAN_F4R2_FB7                         CAN_F4R2_FB7_Msk                  /*!< Filter bit 7 */
9476 #define CAN_F4R2_FB8_Pos                     (8U)
9477 #define CAN_F4R2_FB8_Msk                     (0x1UL << CAN_F4R2_FB8_Pos)        /*!< 0x00000100 */
9478 #define CAN_F4R2_FB8                         CAN_F4R2_FB8_Msk                  /*!< Filter bit 8 */
9479 #define CAN_F4R2_FB9_Pos                     (9U)
9480 #define CAN_F4R2_FB9_Msk                     (0x1UL << CAN_F4R2_FB9_Pos)        /*!< 0x00000200 */
9481 #define CAN_F4R2_FB9                         CAN_F4R2_FB9_Msk                  /*!< Filter bit 9 */
9482 #define CAN_F4R2_FB10_Pos                    (10U)
9483 #define CAN_F4R2_FB10_Msk                    (0x1UL << CAN_F4R2_FB10_Pos)       /*!< 0x00000400 */
9484 #define CAN_F4R2_FB10                        CAN_F4R2_FB10_Msk                 /*!< Filter bit 10 */
9485 #define CAN_F4R2_FB11_Pos                    (11U)
9486 #define CAN_F4R2_FB11_Msk                    (0x1UL << CAN_F4R2_FB11_Pos)       /*!< 0x00000800 */
9487 #define CAN_F4R2_FB11                        CAN_F4R2_FB11_Msk                 /*!< Filter bit 11 */
9488 #define CAN_F4R2_FB12_Pos                    (12U)
9489 #define CAN_F4R2_FB12_Msk                    (0x1UL << CAN_F4R2_FB12_Pos)       /*!< 0x00001000 */
9490 #define CAN_F4R2_FB12                        CAN_F4R2_FB12_Msk                 /*!< Filter bit 12 */
9491 #define CAN_F4R2_FB13_Pos                    (13U)
9492 #define CAN_F4R2_FB13_Msk                    (0x1UL << CAN_F4R2_FB13_Pos)       /*!< 0x00002000 */
9493 #define CAN_F4R2_FB13                        CAN_F4R2_FB13_Msk                 /*!< Filter bit 13 */
9494 #define CAN_F4R2_FB14_Pos                    (14U)
9495 #define CAN_F4R2_FB14_Msk                    (0x1UL << CAN_F4R2_FB14_Pos)       /*!< 0x00004000 */
9496 #define CAN_F4R2_FB14                        CAN_F4R2_FB14_Msk                 /*!< Filter bit 14 */
9497 #define CAN_F4R2_FB15_Pos                    (15U)
9498 #define CAN_F4R2_FB15_Msk                    (0x1UL << CAN_F4R2_FB15_Pos)       /*!< 0x00008000 */
9499 #define CAN_F4R2_FB15                        CAN_F4R2_FB15_Msk                 /*!< Filter bit 15 */
9500 #define CAN_F4R2_FB16_Pos                    (16U)
9501 #define CAN_F4R2_FB16_Msk                    (0x1UL << CAN_F4R2_FB16_Pos)       /*!< 0x00010000 */
9502 #define CAN_F4R2_FB16                        CAN_F4R2_FB16_Msk                 /*!< Filter bit 16 */
9503 #define CAN_F4R2_FB17_Pos                    (17U)
9504 #define CAN_F4R2_FB17_Msk                    (0x1UL << CAN_F4R2_FB17_Pos)       /*!< 0x00020000 */
9505 #define CAN_F4R2_FB17                        CAN_F4R2_FB17_Msk                 /*!< Filter bit 17 */
9506 #define CAN_F4R2_FB18_Pos                    (18U)
9507 #define CAN_F4R2_FB18_Msk                    (0x1UL << CAN_F4R2_FB18_Pos)       /*!< 0x00040000 */
9508 #define CAN_F4R2_FB18                        CAN_F4R2_FB18_Msk                 /*!< Filter bit 18 */
9509 #define CAN_F4R2_FB19_Pos                    (19U)
9510 #define CAN_F4R2_FB19_Msk                    (0x1UL << CAN_F4R2_FB19_Pos)       /*!< 0x00080000 */
9511 #define CAN_F4R2_FB19                        CAN_F4R2_FB19_Msk                 /*!< Filter bit 19 */
9512 #define CAN_F4R2_FB20_Pos                    (20U)
9513 #define CAN_F4R2_FB20_Msk                    (0x1UL << CAN_F4R2_FB20_Pos)       /*!< 0x00100000 */
9514 #define CAN_F4R2_FB20                        CAN_F4R2_FB20_Msk                 /*!< Filter bit 20 */
9515 #define CAN_F4R2_FB21_Pos                    (21U)
9516 #define CAN_F4R2_FB21_Msk                    (0x1UL << CAN_F4R2_FB21_Pos)       /*!< 0x00200000 */
9517 #define CAN_F4R2_FB21                        CAN_F4R2_FB21_Msk                 /*!< Filter bit 21 */
9518 #define CAN_F4R2_FB22_Pos                    (22U)
9519 #define CAN_F4R2_FB22_Msk                    (0x1UL << CAN_F4R2_FB22_Pos)       /*!< 0x00400000 */
9520 #define CAN_F4R2_FB22                        CAN_F4R2_FB22_Msk                 /*!< Filter bit 22 */
9521 #define CAN_F4R2_FB23_Pos                    (23U)
9522 #define CAN_F4R2_FB23_Msk                    (0x1UL << CAN_F4R2_FB23_Pos)       /*!< 0x00800000 */
9523 #define CAN_F4R2_FB23                        CAN_F4R2_FB23_Msk                 /*!< Filter bit 23 */
9524 #define CAN_F4R2_FB24_Pos                    (24U)
9525 #define CAN_F4R2_FB24_Msk                    (0x1UL << CAN_F4R2_FB24_Pos)       /*!< 0x01000000 */
9526 #define CAN_F4R2_FB24                        CAN_F4R2_FB24_Msk                 /*!< Filter bit 24 */
9527 #define CAN_F4R2_FB25_Pos                    (25U)
9528 #define CAN_F4R2_FB25_Msk                    (0x1UL << CAN_F4R2_FB25_Pos)       /*!< 0x02000000 */
9529 #define CAN_F4R2_FB25                        CAN_F4R2_FB25_Msk                 /*!< Filter bit 25 */
9530 #define CAN_F4R2_FB26_Pos                    (26U)
9531 #define CAN_F4R2_FB26_Msk                    (0x1UL << CAN_F4R2_FB26_Pos)       /*!< 0x04000000 */
9532 #define CAN_F4R2_FB26                        CAN_F4R2_FB26_Msk                 /*!< Filter bit 26 */
9533 #define CAN_F4R2_FB27_Pos                    (27U)
9534 #define CAN_F4R2_FB27_Msk                    (0x1UL << CAN_F4R2_FB27_Pos)       /*!< 0x08000000 */
9535 #define CAN_F4R2_FB27                        CAN_F4R2_FB27_Msk                 /*!< Filter bit 27 */
9536 #define CAN_F4R2_FB28_Pos                    (28U)
9537 #define CAN_F4R2_FB28_Msk                    (0x1UL << CAN_F4R2_FB28_Pos)       /*!< 0x10000000 */
9538 #define CAN_F4R2_FB28                        CAN_F4R2_FB28_Msk                 /*!< Filter bit 28 */
9539 #define CAN_F4R2_FB29_Pos                    (29U)
9540 #define CAN_F4R2_FB29_Msk                    (0x1UL << CAN_F4R2_FB29_Pos)       /*!< 0x20000000 */
9541 #define CAN_F4R2_FB29                        CAN_F4R2_FB29_Msk                 /*!< Filter bit 29 */
9542 #define CAN_F4R2_FB30_Pos                    (30U)
9543 #define CAN_F4R2_FB30_Msk                    (0x1UL << CAN_F4R2_FB30_Pos)       /*!< 0x40000000 */
9544 #define CAN_F4R2_FB30                        CAN_F4R2_FB30_Msk                 /*!< Filter bit 30 */
9545 #define CAN_F4R2_FB31_Pos                    (31U)
9546 #define CAN_F4R2_FB31_Msk                    (0x1UL << CAN_F4R2_FB31_Pos)       /*!< 0x80000000 */
9547 #define CAN_F4R2_FB31                        CAN_F4R2_FB31_Msk                 /*!< Filter bit 31 */
9548 
9549 /*******************  Bit definition for CAN_F5R2 register  *******************/
9550 #define CAN_F5R2_FB0_Pos                     (0U)
9551 #define CAN_F5R2_FB0_Msk                     (0x1UL << CAN_F5R2_FB0_Pos)        /*!< 0x00000001 */
9552 #define CAN_F5R2_FB0                         CAN_F5R2_FB0_Msk                  /*!< Filter bit 0 */
9553 #define CAN_F5R2_FB1_Pos                     (1U)
9554 #define CAN_F5R2_FB1_Msk                     (0x1UL << CAN_F5R2_FB1_Pos)        /*!< 0x00000002 */
9555 #define CAN_F5R2_FB1                         CAN_F5R2_FB1_Msk                  /*!< Filter bit 1 */
9556 #define CAN_F5R2_FB2_Pos                     (2U)
9557 #define CAN_F5R2_FB2_Msk                     (0x1UL << CAN_F5R2_FB2_Pos)        /*!< 0x00000004 */
9558 #define CAN_F5R2_FB2                         CAN_F5R2_FB2_Msk                  /*!< Filter bit 2 */
9559 #define CAN_F5R2_FB3_Pos                     (3U)
9560 #define CAN_F5R2_FB3_Msk                     (0x1UL << CAN_F5R2_FB3_Pos)        /*!< 0x00000008 */
9561 #define CAN_F5R2_FB3                         CAN_F5R2_FB3_Msk                  /*!< Filter bit 3 */
9562 #define CAN_F5R2_FB4_Pos                     (4U)
9563 #define CAN_F5R2_FB4_Msk                     (0x1UL << CAN_F5R2_FB4_Pos)        /*!< 0x00000010 */
9564 #define CAN_F5R2_FB4                         CAN_F5R2_FB4_Msk                  /*!< Filter bit 4 */
9565 #define CAN_F5R2_FB5_Pos                     (5U)
9566 #define CAN_F5R2_FB5_Msk                     (0x1UL << CAN_F5R2_FB5_Pos)        /*!< 0x00000020 */
9567 #define CAN_F5R2_FB5                         CAN_F5R2_FB5_Msk                  /*!< Filter bit 5 */
9568 #define CAN_F5R2_FB6_Pos                     (6U)
9569 #define CAN_F5R2_FB6_Msk                     (0x1UL << CAN_F5R2_FB6_Pos)        /*!< 0x00000040 */
9570 #define CAN_F5R2_FB6                         CAN_F5R2_FB6_Msk                  /*!< Filter bit 6 */
9571 #define CAN_F5R2_FB7_Pos                     (7U)
9572 #define CAN_F5R2_FB7_Msk                     (0x1UL << CAN_F5R2_FB7_Pos)        /*!< 0x00000080 */
9573 #define CAN_F5R2_FB7                         CAN_F5R2_FB7_Msk                  /*!< Filter bit 7 */
9574 #define CAN_F5R2_FB8_Pos                     (8U)
9575 #define CAN_F5R2_FB8_Msk                     (0x1UL << CAN_F5R2_FB8_Pos)        /*!< 0x00000100 */
9576 #define CAN_F5R2_FB8                         CAN_F5R2_FB8_Msk                  /*!< Filter bit 8 */
9577 #define CAN_F5R2_FB9_Pos                     (9U)
9578 #define CAN_F5R2_FB9_Msk                     (0x1UL << CAN_F5R2_FB9_Pos)        /*!< 0x00000200 */
9579 #define CAN_F5R2_FB9                         CAN_F5R2_FB9_Msk                  /*!< Filter bit 9 */
9580 #define CAN_F5R2_FB10_Pos                    (10U)
9581 #define CAN_F5R2_FB10_Msk                    (0x1UL << CAN_F5R2_FB10_Pos)       /*!< 0x00000400 */
9582 #define CAN_F5R2_FB10                        CAN_F5R2_FB10_Msk                 /*!< Filter bit 10 */
9583 #define CAN_F5R2_FB11_Pos                    (11U)
9584 #define CAN_F5R2_FB11_Msk                    (0x1UL << CAN_F5R2_FB11_Pos)       /*!< 0x00000800 */
9585 #define CAN_F5R2_FB11                        CAN_F5R2_FB11_Msk                 /*!< Filter bit 11 */
9586 #define CAN_F5R2_FB12_Pos                    (12U)
9587 #define CAN_F5R2_FB12_Msk                    (0x1UL << CAN_F5R2_FB12_Pos)       /*!< 0x00001000 */
9588 #define CAN_F5R2_FB12                        CAN_F5R2_FB12_Msk                 /*!< Filter bit 12 */
9589 #define CAN_F5R2_FB13_Pos                    (13U)
9590 #define CAN_F5R2_FB13_Msk                    (0x1UL << CAN_F5R2_FB13_Pos)       /*!< 0x00002000 */
9591 #define CAN_F5R2_FB13                        CAN_F5R2_FB13_Msk                 /*!< Filter bit 13 */
9592 #define CAN_F5R2_FB14_Pos                    (14U)
9593 #define CAN_F5R2_FB14_Msk                    (0x1UL << CAN_F5R2_FB14_Pos)       /*!< 0x00004000 */
9594 #define CAN_F5R2_FB14                        CAN_F5R2_FB14_Msk                 /*!< Filter bit 14 */
9595 #define CAN_F5R2_FB15_Pos                    (15U)
9596 #define CAN_F5R2_FB15_Msk                    (0x1UL << CAN_F5R2_FB15_Pos)       /*!< 0x00008000 */
9597 #define CAN_F5R2_FB15                        CAN_F5R2_FB15_Msk                 /*!< Filter bit 15 */
9598 #define CAN_F5R2_FB16_Pos                    (16U)
9599 #define CAN_F5R2_FB16_Msk                    (0x1UL << CAN_F5R2_FB16_Pos)       /*!< 0x00010000 */
9600 #define CAN_F5R2_FB16                        CAN_F5R2_FB16_Msk                 /*!< Filter bit 16 */
9601 #define CAN_F5R2_FB17_Pos                    (17U)
9602 #define CAN_F5R2_FB17_Msk                    (0x1UL << CAN_F5R2_FB17_Pos)       /*!< 0x00020000 */
9603 #define CAN_F5R2_FB17                        CAN_F5R2_FB17_Msk                 /*!< Filter bit 17 */
9604 #define CAN_F5R2_FB18_Pos                    (18U)
9605 #define CAN_F5R2_FB18_Msk                    (0x1UL << CAN_F5R2_FB18_Pos)       /*!< 0x00040000 */
9606 #define CAN_F5R2_FB18                        CAN_F5R2_FB18_Msk                 /*!< Filter bit 18 */
9607 #define CAN_F5R2_FB19_Pos                    (19U)
9608 #define CAN_F5R2_FB19_Msk                    (0x1UL << CAN_F5R2_FB19_Pos)       /*!< 0x00080000 */
9609 #define CAN_F5R2_FB19                        CAN_F5R2_FB19_Msk                 /*!< Filter bit 19 */
9610 #define CAN_F5R2_FB20_Pos                    (20U)
9611 #define CAN_F5R2_FB20_Msk                    (0x1UL << CAN_F5R2_FB20_Pos)       /*!< 0x00100000 */
9612 #define CAN_F5R2_FB20                        CAN_F5R2_FB20_Msk                 /*!< Filter bit 20 */
9613 #define CAN_F5R2_FB21_Pos                    (21U)
9614 #define CAN_F5R2_FB21_Msk                    (0x1UL << CAN_F5R2_FB21_Pos)       /*!< 0x00200000 */
9615 #define CAN_F5R2_FB21                        CAN_F5R2_FB21_Msk                 /*!< Filter bit 21 */
9616 #define CAN_F5R2_FB22_Pos                    (22U)
9617 #define CAN_F5R2_FB22_Msk                    (0x1UL << CAN_F5R2_FB22_Pos)       /*!< 0x00400000 */
9618 #define CAN_F5R2_FB22                        CAN_F5R2_FB22_Msk                 /*!< Filter bit 22 */
9619 #define CAN_F5R2_FB23_Pos                    (23U)
9620 #define CAN_F5R2_FB23_Msk                    (0x1UL << CAN_F5R2_FB23_Pos)       /*!< 0x00800000 */
9621 #define CAN_F5R2_FB23                        CAN_F5R2_FB23_Msk                 /*!< Filter bit 23 */
9622 #define CAN_F5R2_FB24_Pos                    (24U)
9623 #define CAN_F5R2_FB24_Msk                    (0x1UL << CAN_F5R2_FB24_Pos)       /*!< 0x01000000 */
9624 #define CAN_F5R2_FB24                        CAN_F5R2_FB24_Msk                 /*!< Filter bit 24 */
9625 #define CAN_F5R2_FB25_Pos                    (25U)
9626 #define CAN_F5R2_FB25_Msk                    (0x1UL << CAN_F5R2_FB25_Pos)       /*!< 0x02000000 */
9627 #define CAN_F5R2_FB25                        CAN_F5R2_FB25_Msk                 /*!< Filter bit 25 */
9628 #define CAN_F5R2_FB26_Pos                    (26U)
9629 #define CAN_F5R2_FB26_Msk                    (0x1UL << CAN_F5R2_FB26_Pos)       /*!< 0x04000000 */
9630 #define CAN_F5R2_FB26                        CAN_F5R2_FB26_Msk                 /*!< Filter bit 26 */
9631 #define CAN_F5R2_FB27_Pos                    (27U)
9632 #define CAN_F5R2_FB27_Msk                    (0x1UL << CAN_F5R2_FB27_Pos)       /*!< 0x08000000 */
9633 #define CAN_F5R2_FB27                        CAN_F5R2_FB27_Msk                 /*!< Filter bit 27 */
9634 #define CAN_F5R2_FB28_Pos                    (28U)
9635 #define CAN_F5R2_FB28_Msk                    (0x1UL << CAN_F5R2_FB28_Pos)       /*!< 0x10000000 */
9636 #define CAN_F5R2_FB28                        CAN_F5R2_FB28_Msk                 /*!< Filter bit 28 */
9637 #define CAN_F5R2_FB29_Pos                    (29U)
9638 #define CAN_F5R2_FB29_Msk                    (0x1UL << CAN_F5R2_FB29_Pos)       /*!< 0x20000000 */
9639 #define CAN_F5R2_FB29                        CAN_F5R2_FB29_Msk                 /*!< Filter bit 29 */
9640 #define CAN_F5R2_FB30_Pos                    (30U)
9641 #define CAN_F5R2_FB30_Msk                    (0x1UL << CAN_F5R2_FB30_Pos)       /*!< 0x40000000 */
9642 #define CAN_F5R2_FB30                        CAN_F5R2_FB30_Msk                 /*!< Filter bit 30 */
9643 #define CAN_F5R2_FB31_Pos                    (31U)
9644 #define CAN_F5R2_FB31_Msk                    (0x1UL << CAN_F5R2_FB31_Pos)       /*!< 0x80000000 */
9645 #define CAN_F5R2_FB31                        CAN_F5R2_FB31_Msk                 /*!< Filter bit 31 */
9646 
9647 /*******************  Bit definition for CAN_F6R2 register  *******************/
9648 #define CAN_F6R2_FB0_Pos                     (0U)
9649 #define CAN_F6R2_FB0_Msk                     (0x1UL << CAN_F6R2_FB0_Pos)        /*!< 0x00000001 */
9650 #define CAN_F6R2_FB0                         CAN_F6R2_FB0_Msk                  /*!< Filter bit 0 */
9651 #define CAN_F6R2_FB1_Pos                     (1U)
9652 #define CAN_F6R2_FB1_Msk                     (0x1UL << CAN_F6R2_FB1_Pos)        /*!< 0x00000002 */
9653 #define CAN_F6R2_FB1                         CAN_F6R2_FB1_Msk                  /*!< Filter bit 1 */
9654 #define CAN_F6R2_FB2_Pos                     (2U)
9655 #define CAN_F6R2_FB2_Msk                     (0x1UL << CAN_F6R2_FB2_Pos)        /*!< 0x00000004 */
9656 #define CAN_F6R2_FB2                         CAN_F6R2_FB2_Msk                  /*!< Filter bit 2 */
9657 #define CAN_F6R2_FB3_Pos                     (3U)
9658 #define CAN_F6R2_FB3_Msk                     (0x1UL << CAN_F6R2_FB3_Pos)        /*!< 0x00000008 */
9659 #define CAN_F6R2_FB3                         CAN_F6R2_FB3_Msk                  /*!< Filter bit 3 */
9660 #define CAN_F6R2_FB4_Pos                     (4U)
9661 #define CAN_F6R2_FB4_Msk                     (0x1UL << CAN_F6R2_FB4_Pos)        /*!< 0x00000010 */
9662 #define CAN_F6R2_FB4                         CAN_F6R2_FB4_Msk                  /*!< Filter bit 4 */
9663 #define CAN_F6R2_FB5_Pos                     (5U)
9664 #define CAN_F6R2_FB5_Msk                     (0x1UL << CAN_F6R2_FB5_Pos)        /*!< 0x00000020 */
9665 #define CAN_F6R2_FB5                         CAN_F6R2_FB5_Msk                  /*!< Filter bit 5 */
9666 #define CAN_F6R2_FB6_Pos                     (6U)
9667 #define CAN_F6R2_FB6_Msk                     (0x1UL << CAN_F6R2_FB6_Pos)        /*!< 0x00000040 */
9668 #define CAN_F6R2_FB6                         CAN_F6R2_FB6_Msk                  /*!< Filter bit 6 */
9669 #define CAN_F6R2_FB7_Pos                     (7U)
9670 #define CAN_F6R2_FB7_Msk                     (0x1UL << CAN_F6R2_FB7_Pos)        /*!< 0x00000080 */
9671 #define CAN_F6R2_FB7                         CAN_F6R2_FB7_Msk                  /*!< Filter bit 7 */
9672 #define CAN_F6R2_FB8_Pos                     (8U)
9673 #define CAN_F6R2_FB8_Msk                     (0x1UL << CAN_F6R2_FB8_Pos)        /*!< 0x00000100 */
9674 #define CAN_F6R2_FB8                         CAN_F6R2_FB8_Msk                  /*!< Filter bit 8 */
9675 #define CAN_F6R2_FB9_Pos                     (9U)
9676 #define CAN_F6R2_FB9_Msk                     (0x1UL << CAN_F6R2_FB9_Pos)        /*!< 0x00000200 */
9677 #define CAN_F6R2_FB9                         CAN_F6R2_FB9_Msk                  /*!< Filter bit 9 */
9678 #define CAN_F6R2_FB10_Pos                    (10U)
9679 #define CAN_F6R2_FB10_Msk                    (0x1UL << CAN_F6R2_FB10_Pos)       /*!< 0x00000400 */
9680 #define CAN_F6R2_FB10                        CAN_F6R2_FB10_Msk                 /*!< Filter bit 10 */
9681 #define CAN_F6R2_FB11_Pos                    (11U)
9682 #define CAN_F6R2_FB11_Msk                    (0x1UL << CAN_F6R2_FB11_Pos)       /*!< 0x00000800 */
9683 #define CAN_F6R2_FB11                        CAN_F6R2_FB11_Msk                 /*!< Filter bit 11 */
9684 #define CAN_F6R2_FB12_Pos                    (12U)
9685 #define CAN_F6R2_FB12_Msk                    (0x1UL << CAN_F6R2_FB12_Pos)       /*!< 0x00001000 */
9686 #define CAN_F6R2_FB12                        CAN_F6R2_FB12_Msk                 /*!< Filter bit 12 */
9687 #define CAN_F6R2_FB13_Pos                    (13U)
9688 #define CAN_F6R2_FB13_Msk                    (0x1UL << CAN_F6R2_FB13_Pos)       /*!< 0x00002000 */
9689 #define CAN_F6R2_FB13                        CAN_F6R2_FB13_Msk                 /*!< Filter bit 13 */
9690 #define CAN_F6R2_FB14_Pos                    (14U)
9691 #define CAN_F6R2_FB14_Msk                    (0x1UL << CAN_F6R2_FB14_Pos)       /*!< 0x00004000 */
9692 #define CAN_F6R2_FB14                        CAN_F6R2_FB14_Msk                 /*!< Filter bit 14 */
9693 #define CAN_F6R2_FB15_Pos                    (15U)
9694 #define CAN_F6R2_FB15_Msk                    (0x1UL << CAN_F6R2_FB15_Pos)       /*!< 0x00008000 */
9695 #define CAN_F6R2_FB15                        CAN_F6R2_FB15_Msk                 /*!< Filter bit 15 */
9696 #define CAN_F6R2_FB16_Pos                    (16U)
9697 #define CAN_F6R2_FB16_Msk                    (0x1UL << CAN_F6R2_FB16_Pos)       /*!< 0x00010000 */
9698 #define CAN_F6R2_FB16                        CAN_F6R2_FB16_Msk                 /*!< Filter bit 16 */
9699 #define CAN_F6R2_FB17_Pos                    (17U)
9700 #define CAN_F6R2_FB17_Msk                    (0x1UL << CAN_F6R2_FB17_Pos)       /*!< 0x00020000 */
9701 #define CAN_F6R2_FB17                        CAN_F6R2_FB17_Msk                 /*!< Filter bit 17 */
9702 #define CAN_F6R2_FB18_Pos                    (18U)
9703 #define CAN_F6R2_FB18_Msk                    (0x1UL << CAN_F6R2_FB18_Pos)       /*!< 0x00040000 */
9704 #define CAN_F6R2_FB18                        CAN_F6R2_FB18_Msk                 /*!< Filter bit 18 */
9705 #define CAN_F6R2_FB19_Pos                    (19U)
9706 #define CAN_F6R2_FB19_Msk                    (0x1UL << CAN_F6R2_FB19_Pos)       /*!< 0x00080000 */
9707 #define CAN_F6R2_FB19                        CAN_F6R2_FB19_Msk                 /*!< Filter bit 19 */
9708 #define CAN_F6R2_FB20_Pos                    (20U)
9709 #define CAN_F6R2_FB20_Msk                    (0x1UL << CAN_F6R2_FB20_Pos)       /*!< 0x00100000 */
9710 #define CAN_F6R2_FB20                        CAN_F6R2_FB20_Msk                 /*!< Filter bit 20 */
9711 #define CAN_F6R2_FB21_Pos                    (21U)
9712 #define CAN_F6R2_FB21_Msk                    (0x1UL << CAN_F6R2_FB21_Pos)       /*!< 0x00200000 */
9713 #define CAN_F6R2_FB21                        CAN_F6R2_FB21_Msk                 /*!< Filter bit 21 */
9714 #define CAN_F6R2_FB22_Pos                    (22U)
9715 #define CAN_F6R2_FB22_Msk                    (0x1UL << CAN_F6R2_FB22_Pos)       /*!< 0x00400000 */
9716 #define CAN_F6R2_FB22                        CAN_F6R2_FB22_Msk                 /*!< Filter bit 22 */
9717 #define CAN_F6R2_FB23_Pos                    (23U)
9718 #define CAN_F6R2_FB23_Msk                    (0x1UL << CAN_F6R2_FB23_Pos)       /*!< 0x00800000 */
9719 #define CAN_F6R2_FB23                        CAN_F6R2_FB23_Msk                 /*!< Filter bit 23 */
9720 #define CAN_F6R2_FB24_Pos                    (24U)
9721 #define CAN_F6R2_FB24_Msk                    (0x1UL << CAN_F6R2_FB24_Pos)       /*!< 0x01000000 */
9722 #define CAN_F6R2_FB24                        CAN_F6R2_FB24_Msk                 /*!< Filter bit 24 */
9723 #define CAN_F6R2_FB25_Pos                    (25U)
9724 #define CAN_F6R2_FB25_Msk                    (0x1UL << CAN_F6R2_FB25_Pos)       /*!< 0x02000000 */
9725 #define CAN_F6R2_FB25                        CAN_F6R2_FB25_Msk                 /*!< Filter bit 25 */
9726 #define CAN_F6R2_FB26_Pos                    (26U)
9727 #define CAN_F6R2_FB26_Msk                    (0x1UL << CAN_F6R2_FB26_Pos)       /*!< 0x04000000 */
9728 #define CAN_F6R2_FB26                        CAN_F6R2_FB26_Msk                 /*!< Filter bit 26 */
9729 #define CAN_F6R2_FB27_Pos                    (27U)
9730 #define CAN_F6R2_FB27_Msk                    (0x1UL << CAN_F6R2_FB27_Pos)       /*!< 0x08000000 */
9731 #define CAN_F6R2_FB27                        CAN_F6R2_FB27_Msk                 /*!< Filter bit 27 */
9732 #define CAN_F6R2_FB28_Pos                    (28U)
9733 #define CAN_F6R2_FB28_Msk                    (0x1UL << CAN_F6R2_FB28_Pos)       /*!< 0x10000000 */
9734 #define CAN_F6R2_FB28                        CAN_F6R2_FB28_Msk                 /*!< Filter bit 28 */
9735 #define CAN_F6R2_FB29_Pos                    (29U)
9736 #define CAN_F6R2_FB29_Msk                    (0x1UL << CAN_F6R2_FB29_Pos)       /*!< 0x20000000 */
9737 #define CAN_F6R2_FB29                        CAN_F6R2_FB29_Msk                 /*!< Filter bit 29 */
9738 #define CAN_F6R2_FB30_Pos                    (30U)
9739 #define CAN_F6R2_FB30_Msk                    (0x1UL << CAN_F6R2_FB30_Pos)       /*!< 0x40000000 */
9740 #define CAN_F6R2_FB30                        CAN_F6R2_FB30_Msk                 /*!< Filter bit 30 */
9741 #define CAN_F6R2_FB31_Pos                    (31U)
9742 #define CAN_F6R2_FB31_Msk                    (0x1UL << CAN_F6R2_FB31_Pos)       /*!< 0x80000000 */
9743 #define CAN_F6R2_FB31                        CAN_F6R2_FB31_Msk                 /*!< Filter bit 31 */
9744 
9745 /*******************  Bit definition for CAN_F7R2 register  *******************/
9746 #define CAN_F7R2_FB0_Pos                     (0U)
9747 #define CAN_F7R2_FB0_Msk                     (0x1UL << CAN_F7R2_FB0_Pos)        /*!< 0x00000001 */
9748 #define CAN_F7R2_FB0                         CAN_F7R2_FB0_Msk                  /*!< Filter bit 0 */
9749 #define CAN_F7R2_FB1_Pos                     (1U)
9750 #define CAN_F7R2_FB1_Msk                     (0x1UL << CAN_F7R2_FB1_Pos)        /*!< 0x00000002 */
9751 #define CAN_F7R2_FB1                         CAN_F7R2_FB1_Msk                  /*!< Filter bit 1 */
9752 #define CAN_F7R2_FB2_Pos                     (2U)
9753 #define CAN_F7R2_FB2_Msk                     (0x1UL << CAN_F7R2_FB2_Pos)        /*!< 0x00000004 */
9754 #define CAN_F7R2_FB2                         CAN_F7R2_FB2_Msk                  /*!< Filter bit 2 */
9755 #define CAN_F7R2_FB3_Pos                     (3U)
9756 #define CAN_F7R2_FB3_Msk                     (0x1UL << CAN_F7R2_FB3_Pos)        /*!< 0x00000008 */
9757 #define CAN_F7R2_FB3                         CAN_F7R2_FB3_Msk                  /*!< Filter bit 3 */
9758 #define CAN_F7R2_FB4_Pos                     (4U)
9759 #define CAN_F7R2_FB4_Msk                     (0x1UL << CAN_F7R2_FB4_Pos)        /*!< 0x00000010 */
9760 #define CAN_F7R2_FB4                         CAN_F7R2_FB4_Msk                  /*!< Filter bit 4 */
9761 #define CAN_F7R2_FB5_Pos                     (5U)
9762 #define CAN_F7R2_FB5_Msk                     (0x1UL << CAN_F7R2_FB5_Pos)        /*!< 0x00000020 */
9763 #define CAN_F7R2_FB5                         CAN_F7R2_FB5_Msk                  /*!< Filter bit 5 */
9764 #define CAN_F7R2_FB6_Pos                     (6U)
9765 #define CAN_F7R2_FB6_Msk                     (0x1UL << CAN_F7R2_FB6_Pos)        /*!< 0x00000040 */
9766 #define CAN_F7R2_FB6                         CAN_F7R2_FB6_Msk                  /*!< Filter bit 6 */
9767 #define CAN_F7R2_FB7_Pos                     (7U)
9768 #define CAN_F7R2_FB7_Msk                     (0x1UL << CAN_F7R2_FB7_Pos)        /*!< 0x00000080 */
9769 #define CAN_F7R2_FB7                         CAN_F7R2_FB7_Msk                  /*!< Filter bit 7 */
9770 #define CAN_F7R2_FB8_Pos                     (8U)
9771 #define CAN_F7R2_FB8_Msk                     (0x1UL << CAN_F7R2_FB8_Pos)        /*!< 0x00000100 */
9772 #define CAN_F7R2_FB8                         CAN_F7R2_FB8_Msk                  /*!< Filter bit 8 */
9773 #define CAN_F7R2_FB9_Pos                     (9U)
9774 #define CAN_F7R2_FB9_Msk                     (0x1UL << CAN_F7R2_FB9_Pos)        /*!< 0x00000200 */
9775 #define CAN_F7R2_FB9                         CAN_F7R2_FB9_Msk                  /*!< Filter bit 9 */
9776 #define CAN_F7R2_FB10_Pos                    (10U)
9777 #define CAN_F7R2_FB10_Msk                    (0x1UL << CAN_F7R2_FB10_Pos)       /*!< 0x00000400 */
9778 #define CAN_F7R2_FB10                        CAN_F7R2_FB10_Msk                 /*!< Filter bit 10 */
9779 #define CAN_F7R2_FB11_Pos                    (11U)
9780 #define CAN_F7R2_FB11_Msk                    (0x1UL << CAN_F7R2_FB11_Pos)       /*!< 0x00000800 */
9781 #define CAN_F7R2_FB11                        CAN_F7R2_FB11_Msk                 /*!< Filter bit 11 */
9782 #define CAN_F7R2_FB12_Pos                    (12U)
9783 #define CAN_F7R2_FB12_Msk                    (0x1UL << CAN_F7R2_FB12_Pos)       /*!< 0x00001000 */
9784 #define CAN_F7R2_FB12                        CAN_F7R2_FB12_Msk                 /*!< Filter bit 12 */
9785 #define CAN_F7R2_FB13_Pos                    (13U)
9786 #define CAN_F7R2_FB13_Msk                    (0x1UL << CAN_F7R2_FB13_Pos)       /*!< 0x00002000 */
9787 #define CAN_F7R2_FB13                        CAN_F7R2_FB13_Msk                 /*!< Filter bit 13 */
9788 #define CAN_F7R2_FB14_Pos                    (14U)
9789 #define CAN_F7R2_FB14_Msk                    (0x1UL << CAN_F7R2_FB14_Pos)       /*!< 0x00004000 */
9790 #define CAN_F7R2_FB14                        CAN_F7R2_FB14_Msk                 /*!< Filter bit 14 */
9791 #define CAN_F7R2_FB15_Pos                    (15U)
9792 #define CAN_F7R2_FB15_Msk                    (0x1UL << CAN_F7R2_FB15_Pos)       /*!< 0x00008000 */
9793 #define CAN_F7R2_FB15                        CAN_F7R2_FB15_Msk                 /*!< Filter bit 15 */
9794 #define CAN_F7R2_FB16_Pos                    (16U)
9795 #define CAN_F7R2_FB16_Msk                    (0x1UL << CAN_F7R2_FB16_Pos)       /*!< 0x00010000 */
9796 #define CAN_F7R2_FB16                        CAN_F7R2_FB16_Msk                 /*!< Filter bit 16 */
9797 #define CAN_F7R2_FB17_Pos                    (17U)
9798 #define CAN_F7R2_FB17_Msk                    (0x1UL << CAN_F7R2_FB17_Pos)       /*!< 0x00020000 */
9799 #define CAN_F7R2_FB17                        CAN_F7R2_FB17_Msk                 /*!< Filter bit 17 */
9800 #define CAN_F7R2_FB18_Pos                    (18U)
9801 #define CAN_F7R2_FB18_Msk                    (0x1UL << CAN_F7R2_FB18_Pos)       /*!< 0x00040000 */
9802 #define CAN_F7R2_FB18                        CAN_F7R2_FB18_Msk                 /*!< Filter bit 18 */
9803 #define CAN_F7R2_FB19_Pos                    (19U)
9804 #define CAN_F7R2_FB19_Msk                    (0x1UL << CAN_F7R2_FB19_Pos)       /*!< 0x00080000 */
9805 #define CAN_F7R2_FB19                        CAN_F7R2_FB19_Msk                 /*!< Filter bit 19 */
9806 #define CAN_F7R2_FB20_Pos                    (20U)
9807 #define CAN_F7R2_FB20_Msk                    (0x1UL << CAN_F7R2_FB20_Pos)       /*!< 0x00100000 */
9808 #define CAN_F7R2_FB20                        CAN_F7R2_FB20_Msk                 /*!< Filter bit 20 */
9809 #define CAN_F7R2_FB21_Pos                    (21U)
9810 #define CAN_F7R2_FB21_Msk                    (0x1UL << CAN_F7R2_FB21_Pos)       /*!< 0x00200000 */
9811 #define CAN_F7R2_FB21                        CAN_F7R2_FB21_Msk                 /*!< Filter bit 21 */
9812 #define CAN_F7R2_FB22_Pos                    (22U)
9813 #define CAN_F7R2_FB22_Msk                    (0x1UL << CAN_F7R2_FB22_Pos)       /*!< 0x00400000 */
9814 #define CAN_F7R2_FB22                        CAN_F7R2_FB22_Msk                 /*!< Filter bit 22 */
9815 #define CAN_F7R2_FB23_Pos                    (23U)
9816 #define CAN_F7R2_FB23_Msk                    (0x1UL << CAN_F7R2_FB23_Pos)       /*!< 0x00800000 */
9817 #define CAN_F7R2_FB23                        CAN_F7R2_FB23_Msk                 /*!< Filter bit 23 */
9818 #define CAN_F7R2_FB24_Pos                    (24U)
9819 #define CAN_F7R2_FB24_Msk                    (0x1UL << CAN_F7R2_FB24_Pos)       /*!< 0x01000000 */
9820 #define CAN_F7R2_FB24                        CAN_F7R2_FB24_Msk                 /*!< Filter bit 24 */
9821 #define CAN_F7R2_FB25_Pos                    (25U)
9822 #define CAN_F7R2_FB25_Msk                    (0x1UL << CAN_F7R2_FB25_Pos)       /*!< 0x02000000 */
9823 #define CAN_F7R2_FB25                        CAN_F7R2_FB25_Msk                 /*!< Filter bit 25 */
9824 #define CAN_F7R2_FB26_Pos                    (26U)
9825 #define CAN_F7R2_FB26_Msk                    (0x1UL << CAN_F7R2_FB26_Pos)       /*!< 0x04000000 */
9826 #define CAN_F7R2_FB26                        CAN_F7R2_FB26_Msk                 /*!< Filter bit 26 */
9827 #define CAN_F7R2_FB27_Pos                    (27U)
9828 #define CAN_F7R2_FB27_Msk                    (0x1UL << CAN_F7R2_FB27_Pos)       /*!< 0x08000000 */
9829 #define CAN_F7R2_FB27                        CAN_F7R2_FB27_Msk                 /*!< Filter bit 27 */
9830 #define CAN_F7R2_FB28_Pos                    (28U)
9831 #define CAN_F7R2_FB28_Msk                    (0x1UL << CAN_F7R2_FB28_Pos)       /*!< 0x10000000 */
9832 #define CAN_F7R2_FB28                        CAN_F7R2_FB28_Msk                 /*!< Filter bit 28 */
9833 #define CAN_F7R2_FB29_Pos                    (29U)
9834 #define CAN_F7R2_FB29_Msk                    (0x1UL << CAN_F7R2_FB29_Pos)       /*!< 0x20000000 */
9835 #define CAN_F7R2_FB29                        CAN_F7R2_FB29_Msk                 /*!< Filter bit 29 */
9836 #define CAN_F7R2_FB30_Pos                    (30U)
9837 #define CAN_F7R2_FB30_Msk                    (0x1UL << CAN_F7R2_FB30_Pos)       /*!< 0x40000000 */
9838 #define CAN_F7R2_FB30                        CAN_F7R2_FB30_Msk                 /*!< Filter bit 30 */
9839 #define CAN_F7R2_FB31_Pos                    (31U)
9840 #define CAN_F7R2_FB31_Msk                    (0x1UL << CAN_F7R2_FB31_Pos)       /*!< 0x80000000 */
9841 #define CAN_F7R2_FB31                        CAN_F7R2_FB31_Msk                 /*!< Filter bit 31 */
9842 
9843 /*******************  Bit definition for CAN_F8R2 register  *******************/
9844 #define CAN_F8R2_FB0_Pos                     (0U)
9845 #define CAN_F8R2_FB0_Msk                     (0x1UL << CAN_F8R2_FB0_Pos)        /*!< 0x00000001 */
9846 #define CAN_F8R2_FB0                         CAN_F8R2_FB0_Msk                  /*!< Filter bit 0 */
9847 #define CAN_F8R2_FB1_Pos                     (1U)
9848 #define CAN_F8R2_FB1_Msk                     (0x1UL << CAN_F8R2_FB1_Pos)        /*!< 0x00000002 */
9849 #define CAN_F8R2_FB1                         CAN_F8R2_FB1_Msk                  /*!< Filter bit 1 */
9850 #define CAN_F8R2_FB2_Pos                     (2U)
9851 #define CAN_F8R2_FB2_Msk                     (0x1UL << CAN_F8R2_FB2_Pos)        /*!< 0x00000004 */
9852 #define CAN_F8R2_FB2                         CAN_F8R2_FB2_Msk                  /*!< Filter bit 2 */
9853 #define CAN_F8R2_FB3_Pos                     (3U)
9854 #define CAN_F8R2_FB3_Msk                     (0x1UL << CAN_F8R2_FB3_Pos)        /*!< 0x00000008 */
9855 #define CAN_F8R2_FB3                         CAN_F8R2_FB3_Msk                  /*!< Filter bit 3 */
9856 #define CAN_F8R2_FB4_Pos                     (4U)
9857 #define CAN_F8R2_FB4_Msk                     (0x1UL << CAN_F8R2_FB4_Pos)        /*!< 0x00000010 */
9858 #define CAN_F8R2_FB4                         CAN_F8R2_FB4_Msk                  /*!< Filter bit 4 */
9859 #define CAN_F8R2_FB5_Pos                     (5U)
9860 #define CAN_F8R2_FB5_Msk                     (0x1UL << CAN_F8R2_FB5_Pos)        /*!< 0x00000020 */
9861 #define CAN_F8R2_FB5                         CAN_F8R2_FB5_Msk                  /*!< Filter bit 5 */
9862 #define CAN_F8R2_FB6_Pos                     (6U)
9863 #define CAN_F8R2_FB6_Msk                     (0x1UL << CAN_F8R2_FB6_Pos)        /*!< 0x00000040 */
9864 #define CAN_F8R2_FB6                         CAN_F8R2_FB6_Msk                  /*!< Filter bit 6 */
9865 #define CAN_F8R2_FB7_Pos                     (7U)
9866 #define CAN_F8R2_FB7_Msk                     (0x1UL << CAN_F8R2_FB7_Pos)        /*!< 0x00000080 */
9867 #define CAN_F8R2_FB7                         CAN_F8R2_FB7_Msk                  /*!< Filter bit 7 */
9868 #define CAN_F8R2_FB8_Pos                     (8U)
9869 #define CAN_F8R2_FB8_Msk                     (0x1UL << CAN_F8R2_FB8_Pos)        /*!< 0x00000100 */
9870 #define CAN_F8R2_FB8                         CAN_F8R2_FB8_Msk                  /*!< Filter bit 8 */
9871 #define CAN_F8R2_FB9_Pos                     (9U)
9872 #define CAN_F8R2_FB9_Msk                     (0x1UL << CAN_F8R2_FB9_Pos)        /*!< 0x00000200 */
9873 #define CAN_F8R2_FB9                         CAN_F8R2_FB9_Msk                  /*!< Filter bit 9 */
9874 #define CAN_F8R2_FB10_Pos                    (10U)
9875 #define CAN_F8R2_FB10_Msk                    (0x1UL << CAN_F8R2_FB10_Pos)       /*!< 0x00000400 */
9876 #define CAN_F8R2_FB10                        CAN_F8R2_FB10_Msk                 /*!< Filter bit 10 */
9877 #define CAN_F8R2_FB11_Pos                    (11U)
9878 #define CAN_F8R2_FB11_Msk                    (0x1UL << CAN_F8R2_FB11_Pos)       /*!< 0x00000800 */
9879 #define CAN_F8R2_FB11                        CAN_F8R2_FB11_Msk                 /*!< Filter bit 11 */
9880 #define CAN_F8R2_FB12_Pos                    (12U)
9881 #define CAN_F8R2_FB12_Msk                    (0x1UL << CAN_F8R2_FB12_Pos)       /*!< 0x00001000 */
9882 #define CAN_F8R2_FB12                        CAN_F8R2_FB12_Msk                 /*!< Filter bit 12 */
9883 #define CAN_F8R2_FB13_Pos                    (13U)
9884 #define CAN_F8R2_FB13_Msk                    (0x1UL << CAN_F8R2_FB13_Pos)       /*!< 0x00002000 */
9885 #define CAN_F8R2_FB13                        CAN_F8R2_FB13_Msk                 /*!< Filter bit 13 */
9886 #define CAN_F8R2_FB14_Pos                    (14U)
9887 #define CAN_F8R2_FB14_Msk                    (0x1UL << CAN_F8R2_FB14_Pos)       /*!< 0x00004000 */
9888 #define CAN_F8R2_FB14                        CAN_F8R2_FB14_Msk                 /*!< Filter bit 14 */
9889 #define CAN_F8R2_FB15_Pos                    (15U)
9890 #define CAN_F8R2_FB15_Msk                    (0x1UL << CAN_F8R2_FB15_Pos)       /*!< 0x00008000 */
9891 #define CAN_F8R2_FB15                        CAN_F8R2_FB15_Msk                 /*!< Filter bit 15 */
9892 #define CAN_F8R2_FB16_Pos                    (16U)
9893 #define CAN_F8R2_FB16_Msk                    (0x1UL << CAN_F8R2_FB16_Pos)       /*!< 0x00010000 */
9894 #define CAN_F8R2_FB16                        CAN_F8R2_FB16_Msk                 /*!< Filter bit 16 */
9895 #define CAN_F8R2_FB17_Pos                    (17U)
9896 #define CAN_F8R2_FB17_Msk                    (0x1UL << CAN_F8R2_FB17_Pos)       /*!< 0x00020000 */
9897 #define CAN_F8R2_FB17                        CAN_F8R2_FB17_Msk                 /*!< Filter bit 17 */
9898 #define CAN_F8R2_FB18_Pos                    (18U)
9899 #define CAN_F8R2_FB18_Msk                    (0x1UL << CAN_F8R2_FB18_Pos)       /*!< 0x00040000 */
9900 #define CAN_F8R2_FB18                        CAN_F8R2_FB18_Msk                 /*!< Filter bit 18 */
9901 #define CAN_F8R2_FB19_Pos                    (19U)
9902 #define CAN_F8R2_FB19_Msk                    (0x1UL << CAN_F8R2_FB19_Pos)       /*!< 0x00080000 */
9903 #define CAN_F8R2_FB19                        CAN_F8R2_FB19_Msk                 /*!< Filter bit 19 */
9904 #define CAN_F8R2_FB20_Pos                    (20U)
9905 #define CAN_F8R2_FB20_Msk                    (0x1UL << CAN_F8R2_FB20_Pos)       /*!< 0x00100000 */
9906 #define CAN_F8R2_FB20                        CAN_F8R2_FB20_Msk                 /*!< Filter bit 20 */
9907 #define CAN_F8R2_FB21_Pos                    (21U)
9908 #define CAN_F8R2_FB21_Msk                    (0x1UL << CAN_F8R2_FB21_Pos)       /*!< 0x00200000 */
9909 #define CAN_F8R2_FB21                        CAN_F8R2_FB21_Msk                 /*!< Filter bit 21 */
9910 #define CAN_F8R2_FB22_Pos                    (22U)
9911 #define CAN_F8R2_FB22_Msk                    (0x1UL << CAN_F8R2_FB22_Pos)       /*!< 0x00400000 */
9912 #define CAN_F8R2_FB22                        CAN_F8R2_FB22_Msk                 /*!< Filter bit 22 */
9913 #define CAN_F8R2_FB23_Pos                    (23U)
9914 #define CAN_F8R2_FB23_Msk                    (0x1UL << CAN_F8R2_FB23_Pos)       /*!< 0x00800000 */
9915 #define CAN_F8R2_FB23                        CAN_F8R2_FB23_Msk                 /*!< Filter bit 23 */
9916 #define CAN_F8R2_FB24_Pos                    (24U)
9917 #define CAN_F8R2_FB24_Msk                    (0x1UL << CAN_F8R2_FB24_Pos)       /*!< 0x01000000 */
9918 #define CAN_F8R2_FB24                        CAN_F8R2_FB24_Msk                 /*!< Filter bit 24 */
9919 #define CAN_F8R2_FB25_Pos                    (25U)
9920 #define CAN_F8R2_FB25_Msk                    (0x1UL << CAN_F8R2_FB25_Pos)       /*!< 0x02000000 */
9921 #define CAN_F8R2_FB25                        CAN_F8R2_FB25_Msk                 /*!< Filter bit 25 */
9922 #define CAN_F8R2_FB26_Pos                    (26U)
9923 #define CAN_F8R2_FB26_Msk                    (0x1UL << CAN_F8R2_FB26_Pos)       /*!< 0x04000000 */
9924 #define CAN_F8R2_FB26                        CAN_F8R2_FB26_Msk                 /*!< Filter bit 26 */
9925 #define CAN_F8R2_FB27_Pos                    (27U)
9926 #define CAN_F8R2_FB27_Msk                    (0x1UL << CAN_F8R2_FB27_Pos)       /*!< 0x08000000 */
9927 #define CAN_F8R2_FB27                        CAN_F8R2_FB27_Msk                 /*!< Filter bit 27 */
9928 #define CAN_F8R2_FB28_Pos                    (28U)
9929 #define CAN_F8R2_FB28_Msk                    (0x1UL << CAN_F8R2_FB28_Pos)       /*!< 0x10000000 */
9930 #define CAN_F8R2_FB28                        CAN_F8R2_FB28_Msk                 /*!< Filter bit 28 */
9931 #define CAN_F8R2_FB29_Pos                    (29U)
9932 #define CAN_F8R2_FB29_Msk                    (0x1UL << CAN_F8R2_FB29_Pos)       /*!< 0x20000000 */
9933 #define CAN_F8R2_FB29                        CAN_F8R2_FB29_Msk                 /*!< Filter bit 29 */
9934 #define CAN_F8R2_FB30_Pos                    (30U)
9935 #define CAN_F8R2_FB30_Msk                    (0x1UL << CAN_F8R2_FB30_Pos)       /*!< 0x40000000 */
9936 #define CAN_F8R2_FB30                        CAN_F8R2_FB30_Msk                 /*!< Filter bit 30 */
9937 #define CAN_F8R2_FB31_Pos                    (31U)
9938 #define CAN_F8R2_FB31_Msk                    (0x1UL << CAN_F8R2_FB31_Pos)       /*!< 0x80000000 */
9939 #define CAN_F8R2_FB31                        CAN_F8R2_FB31_Msk                 /*!< Filter bit 31 */
9940 
9941 /*******************  Bit definition for CAN_F9R2 register  *******************/
9942 #define CAN_F9R2_FB0_Pos                     (0U)
9943 #define CAN_F9R2_FB0_Msk                     (0x1UL << CAN_F9R2_FB0_Pos)        /*!< 0x00000001 */
9944 #define CAN_F9R2_FB0                         CAN_F9R2_FB0_Msk                  /*!< Filter bit 0 */
9945 #define CAN_F9R2_FB1_Pos                     (1U)
9946 #define CAN_F9R2_FB1_Msk                     (0x1UL << CAN_F9R2_FB1_Pos)        /*!< 0x00000002 */
9947 #define CAN_F9R2_FB1                         CAN_F9R2_FB1_Msk                  /*!< Filter bit 1 */
9948 #define CAN_F9R2_FB2_Pos                     (2U)
9949 #define CAN_F9R2_FB2_Msk                     (0x1UL << CAN_F9R2_FB2_Pos)        /*!< 0x00000004 */
9950 #define CAN_F9R2_FB2                         CAN_F9R2_FB2_Msk                  /*!< Filter bit 2 */
9951 #define CAN_F9R2_FB3_Pos                     (3U)
9952 #define CAN_F9R2_FB3_Msk                     (0x1UL << CAN_F9R2_FB3_Pos)        /*!< 0x00000008 */
9953 #define CAN_F9R2_FB3                         CAN_F9R2_FB3_Msk                  /*!< Filter bit 3 */
9954 #define CAN_F9R2_FB4_Pos                     (4U)
9955 #define CAN_F9R2_FB4_Msk                     (0x1UL << CAN_F9R2_FB4_Pos)        /*!< 0x00000010 */
9956 #define CAN_F9R2_FB4                         CAN_F9R2_FB4_Msk                  /*!< Filter bit 4 */
9957 #define CAN_F9R2_FB5_Pos                     (5U)
9958 #define CAN_F9R2_FB5_Msk                     (0x1UL << CAN_F9R2_FB5_Pos)        /*!< 0x00000020 */
9959 #define CAN_F9R2_FB5                         CAN_F9R2_FB5_Msk                  /*!< Filter bit 5 */
9960 #define CAN_F9R2_FB6_Pos                     (6U)
9961 #define CAN_F9R2_FB6_Msk                     (0x1UL << CAN_F9R2_FB6_Pos)        /*!< 0x00000040 */
9962 #define CAN_F9R2_FB6                         CAN_F9R2_FB6_Msk                  /*!< Filter bit 6 */
9963 #define CAN_F9R2_FB7_Pos                     (7U)
9964 #define CAN_F9R2_FB7_Msk                     (0x1UL << CAN_F9R2_FB7_Pos)        /*!< 0x00000080 */
9965 #define CAN_F9R2_FB7                         CAN_F9R2_FB7_Msk                  /*!< Filter bit 7 */
9966 #define CAN_F9R2_FB8_Pos                     (8U)
9967 #define CAN_F9R2_FB8_Msk                     (0x1UL << CAN_F9R2_FB8_Pos)        /*!< 0x00000100 */
9968 #define CAN_F9R2_FB8                         CAN_F9R2_FB8_Msk                  /*!< Filter bit 8 */
9969 #define CAN_F9R2_FB9_Pos                     (9U)
9970 #define CAN_F9R2_FB9_Msk                     (0x1UL << CAN_F9R2_FB9_Pos)        /*!< 0x00000200 */
9971 #define CAN_F9R2_FB9                         CAN_F9R2_FB9_Msk                  /*!< Filter bit 9 */
9972 #define CAN_F9R2_FB10_Pos                    (10U)
9973 #define CAN_F9R2_FB10_Msk                    (0x1UL << CAN_F9R2_FB10_Pos)       /*!< 0x00000400 */
9974 #define CAN_F9R2_FB10                        CAN_F9R2_FB10_Msk                 /*!< Filter bit 10 */
9975 #define CAN_F9R2_FB11_Pos                    (11U)
9976 #define CAN_F9R2_FB11_Msk                    (0x1UL << CAN_F9R2_FB11_Pos)       /*!< 0x00000800 */
9977 #define CAN_F9R2_FB11                        CAN_F9R2_FB11_Msk                 /*!< Filter bit 11 */
9978 #define CAN_F9R2_FB12_Pos                    (12U)
9979 #define CAN_F9R2_FB12_Msk                    (0x1UL << CAN_F9R2_FB12_Pos)       /*!< 0x00001000 */
9980 #define CAN_F9R2_FB12                        CAN_F9R2_FB12_Msk                 /*!< Filter bit 12 */
9981 #define CAN_F9R2_FB13_Pos                    (13U)
9982 #define CAN_F9R2_FB13_Msk                    (0x1UL << CAN_F9R2_FB13_Pos)       /*!< 0x00002000 */
9983 #define CAN_F9R2_FB13                        CAN_F9R2_FB13_Msk                 /*!< Filter bit 13 */
9984 #define CAN_F9R2_FB14_Pos                    (14U)
9985 #define CAN_F9R2_FB14_Msk                    (0x1UL << CAN_F9R2_FB14_Pos)       /*!< 0x00004000 */
9986 #define CAN_F9R2_FB14                        CAN_F9R2_FB14_Msk                 /*!< Filter bit 14 */
9987 #define CAN_F9R2_FB15_Pos                    (15U)
9988 #define CAN_F9R2_FB15_Msk                    (0x1UL << CAN_F9R2_FB15_Pos)       /*!< 0x00008000 */
9989 #define CAN_F9R2_FB15                        CAN_F9R2_FB15_Msk                 /*!< Filter bit 15 */
9990 #define CAN_F9R2_FB16_Pos                    (16U)
9991 #define CAN_F9R2_FB16_Msk                    (0x1UL << CAN_F9R2_FB16_Pos)       /*!< 0x00010000 */
9992 #define CAN_F9R2_FB16                        CAN_F9R2_FB16_Msk                 /*!< Filter bit 16 */
9993 #define CAN_F9R2_FB17_Pos                    (17U)
9994 #define CAN_F9R2_FB17_Msk                    (0x1UL << CAN_F9R2_FB17_Pos)       /*!< 0x00020000 */
9995 #define CAN_F9R2_FB17                        CAN_F9R2_FB17_Msk                 /*!< Filter bit 17 */
9996 #define CAN_F9R2_FB18_Pos                    (18U)
9997 #define CAN_F9R2_FB18_Msk                    (0x1UL << CAN_F9R2_FB18_Pos)       /*!< 0x00040000 */
9998 #define CAN_F9R2_FB18                        CAN_F9R2_FB18_Msk                 /*!< Filter bit 18 */
9999 #define CAN_F9R2_FB19_Pos                    (19U)
10000 #define CAN_F9R2_FB19_Msk                    (0x1UL << CAN_F9R2_FB19_Pos)       /*!< 0x00080000 */
10001 #define CAN_F9R2_FB19                        CAN_F9R2_FB19_Msk                 /*!< Filter bit 19 */
10002 #define CAN_F9R2_FB20_Pos                    (20U)
10003 #define CAN_F9R2_FB20_Msk                    (0x1UL << CAN_F9R2_FB20_Pos)       /*!< 0x00100000 */
10004 #define CAN_F9R2_FB20                        CAN_F9R2_FB20_Msk                 /*!< Filter bit 20 */
10005 #define CAN_F9R2_FB21_Pos                    (21U)
10006 #define CAN_F9R2_FB21_Msk                    (0x1UL << CAN_F9R2_FB21_Pos)       /*!< 0x00200000 */
10007 #define CAN_F9R2_FB21                        CAN_F9R2_FB21_Msk                 /*!< Filter bit 21 */
10008 #define CAN_F9R2_FB22_Pos                    (22U)
10009 #define CAN_F9R2_FB22_Msk                    (0x1UL << CAN_F9R2_FB22_Pos)       /*!< 0x00400000 */
10010 #define CAN_F9R2_FB22                        CAN_F9R2_FB22_Msk                 /*!< Filter bit 22 */
10011 #define CAN_F9R2_FB23_Pos                    (23U)
10012 #define CAN_F9R2_FB23_Msk                    (0x1UL << CAN_F9R2_FB23_Pos)       /*!< 0x00800000 */
10013 #define CAN_F9R2_FB23                        CAN_F9R2_FB23_Msk                 /*!< Filter bit 23 */
10014 #define CAN_F9R2_FB24_Pos                    (24U)
10015 #define CAN_F9R2_FB24_Msk                    (0x1UL << CAN_F9R2_FB24_Pos)       /*!< 0x01000000 */
10016 #define CAN_F9R2_FB24                        CAN_F9R2_FB24_Msk                 /*!< Filter bit 24 */
10017 #define CAN_F9R2_FB25_Pos                    (25U)
10018 #define CAN_F9R2_FB25_Msk                    (0x1UL << CAN_F9R2_FB25_Pos)       /*!< 0x02000000 */
10019 #define CAN_F9R2_FB25                        CAN_F9R2_FB25_Msk                 /*!< Filter bit 25 */
10020 #define CAN_F9R2_FB26_Pos                    (26U)
10021 #define CAN_F9R2_FB26_Msk                    (0x1UL << CAN_F9R2_FB26_Pos)       /*!< 0x04000000 */
10022 #define CAN_F9R2_FB26                        CAN_F9R2_FB26_Msk                 /*!< Filter bit 26 */
10023 #define CAN_F9R2_FB27_Pos                    (27U)
10024 #define CAN_F9R2_FB27_Msk                    (0x1UL << CAN_F9R2_FB27_Pos)       /*!< 0x08000000 */
10025 #define CAN_F9R2_FB27                        CAN_F9R2_FB27_Msk                 /*!< Filter bit 27 */
10026 #define CAN_F9R2_FB28_Pos                    (28U)
10027 #define CAN_F9R2_FB28_Msk                    (0x1UL << CAN_F9R2_FB28_Pos)       /*!< 0x10000000 */
10028 #define CAN_F9R2_FB28                        CAN_F9R2_FB28_Msk                 /*!< Filter bit 28 */
10029 #define CAN_F9R2_FB29_Pos                    (29U)
10030 #define CAN_F9R2_FB29_Msk                    (0x1UL << CAN_F9R2_FB29_Pos)       /*!< 0x20000000 */
10031 #define CAN_F9R2_FB29                        CAN_F9R2_FB29_Msk                 /*!< Filter bit 29 */
10032 #define CAN_F9R2_FB30_Pos                    (30U)
10033 #define CAN_F9R2_FB30_Msk                    (0x1UL << CAN_F9R2_FB30_Pos)       /*!< 0x40000000 */
10034 #define CAN_F9R2_FB30                        CAN_F9R2_FB30_Msk                 /*!< Filter bit 30 */
10035 #define CAN_F9R2_FB31_Pos                    (31U)
10036 #define CAN_F9R2_FB31_Msk                    (0x1UL << CAN_F9R2_FB31_Pos)       /*!< 0x80000000 */
10037 #define CAN_F9R2_FB31                        CAN_F9R2_FB31_Msk                 /*!< Filter bit 31 */
10038 
10039 /*******************  Bit definition for CAN_F10R2 register  ******************/
10040 #define CAN_F10R2_FB0_Pos                    (0U)
10041 #define CAN_F10R2_FB0_Msk                    (0x1UL << CAN_F10R2_FB0_Pos)       /*!< 0x00000001 */
10042 #define CAN_F10R2_FB0                        CAN_F10R2_FB0_Msk                 /*!< Filter bit 0 */
10043 #define CAN_F10R2_FB1_Pos                    (1U)
10044 #define CAN_F10R2_FB1_Msk                    (0x1UL << CAN_F10R2_FB1_Pos)       /*!< 0x00000002 */
10045 #define CAN_F10R2_FB1                        CAN_F10R2_FB1_Msk                 /*!< Filter bit 1 */
10046 #define CAN_F10R2_FB2_Pos                    (2U)
10047 #define CAN_F10R2_FB2_Msk                    (0x1UL << CAN_F10R2_FB2_Pos)       /*!< 0x00000004 */
10048 #define CAN_F10R2_FB2                        CAN_F10R2_FB2_Msk                 /*!< Filter bit 2 */
10049 #define CAN_F10R2_FB3_Pos                    (3U)
10050 #define CAN_F10R2_FB3_Msk                    (0x1UL << CAN_F10R2_FB3_Pos)       /*!< 0x00000008 */
10051 #define CAN_F10R2_FB3                        CAN_F10R2_FB3_Msk                 /*!< Filter bit 3 */
10052 #define CAN_F10R2_FB4_Pos                    (4U)
10053 #define CAN_F10R2_FB4_Msk                    (0x1UL << CAN_F10R2_FB4_Pos)       /*!< 0x00000010 */
10054 #define CAN_F10R2_FB4                        CAN_F10R2_FB4_Msk                 /*!< Filter bit 4 */
10055 #define CAN_F10R2_FB5_Pos                    (5U)
10056 #define CAN_F10R2_FB5_Msk                    (0x1UL << CAN_F10R2_FB5_Pos)       /*!< 0x00000020 */
10057 #define CAN_F10R2_FB5                        CAN_F10R2_FB5_Msk                 /*!< Filter bit 5 */
10058 #define CAN_F10R2_FB6_Pos                    (6U)
10059 #define CAN_F10R2_FB6_Msk                    (0x1UL << CAN_F10R2_FB6_Pos)       /*!< 0x00000040 */
10060 #define CAN_F10R2_FB6                        CAN_F10R2_FB6_Msk                 /*!< Filter bit 6 */
10061 #define CAN_F10R2_FB7_Pos                    (7U)
10062 #define CAN_F10R2_FB7_Msk                    (0x1UL << CAN_F10R2_FB7_Pos)       /*!< 0x00000080 */
10063 #define CAN_F10R2_FB7                        CAN_F10R2_FB7_Msk                 /*!< Filter bit 7 */
10064 #define CAN_F10R2_FB8_Pos                    (8U)
10065 #define CAN_F10R2_FB8_Msk                    (0x1UL << CAN_F10R2_FB8_Pos)       /*!< 0x00000100 */
10066 #define CAN_F10R2_FB8                        CAN_F10R2_FB8_Msk                 /*!< Filter bit 8 */
10067 #define CAN_F10R2_FB9_Pos                    (9U)
10068 #define CAN_F10R2_FB9_Msk                    (0x1UL << CAN_F10R2_FB9_Pos)       /*!< 0x00000200 */
10069 #define CAN_F10R2_FB9                        CAN_F10R2_FB9_Msk                 /*!< Filter bit 9 */
10070 #define CAN_F10R2_FB10_Pos                   (10U)
10071 #define CAN_F10R2_FB10_Msk                   (0x1UL << CAN_F10R2_FB10_Pos)      /*!< 0x00000400 */
10072 #define CAN_F10R2_FB10                       CAN_F10R2_FB10_Msk                /*!< Filter bit 10 */
10073 #define CAN_F10R2_FB11_Pos                   (11U)
10074 #define CAN_F10R2_FB11_Msk                   (0x1UL << CAN_F10R2_FB11_Pos)      /*!< 0x00000800 */
10075 #define CAN_F10R2_FB11                       CAN_F10R2_FB11_Msk                /*!< Filter bit 11 */
10076 #define CAN_F10R2_FB12_Pos                   (12U)
10077 #define CAN_F10R2_FB12_Msk                   (0x1UL << CAN_F10R2_FB12_Pos)      /*!< 0x00001000 */
10078 #define CAN_F10R2_FB12                       CAN_F10R2_FB12_Msk                /*!< Filter bit 12 */
10079 #define CAN_F10R2_FB13_Pos                   (13U)
10080 #define CAN_F10R2_FB13_Msk                   (0x1UL << CAN_F10R2_FB13_Pos)      /*!< 0x00002000 */
10081 #define CAN_F10R2_FB13                       CAN_F10R2_FB13_Msk                /*!< Filter bit 13 */
10082 #define CAN_F10R2_FB14_Pos                   (14U)
10083 #define CAN_F10R2_FB14_Msk                   (0x1UL << CAN_F10R2_FB14_Pos)      /*!< 0x00004000 */
10084 #define CAN_F10R2_FB14                       CAN_F10R2_FB14_Msk                /*!< Filter bit 14 */
10085 #define CAN_F10R2_FB15_Pos                   (15U)
10086 #define CAN_F10R2_FB15_Msk                   (0x1UL << CAN_F10R2_FB15_Pos)      /*!< 0x00008000 */
10087 #define CAN_F10R2_FB15                       CAN_F10R2_FB15_Msk                /*!< Filter bit 15 */
10088 #define CAN_F10R2_FB16_Pos                   (16U)
10089 #define CAN_F10R2_FB16_Msk                   (0x1UL << CAN_F10R2_FB16_Pos)      /*!< 0x00010000 */
10090 #define CAN_F10R2_FB16                       CAN_F10R2_FB16_Msk                /*!< Filter bit 16 */
10091 #define CAN_F10R2_FB17_Pos                   (17U)
10092 #define CAN_F10R2_FB17_Msk                   (0x1UL << CAN_F10R2_FB17_Pos)      /*!< 0x00020000 */
10093 #define CAN_F10R2_FB17                       CAN_F10R2_FB17_Msk                /*!< Filter bit 17 */
10094 #define CAN_F10R2_FB18_Pos                   (18U)
10095 #define CAN_F10R2_FB18_Msk                   (0x1UL << CAN_F10R2_FB18_Pos)      /*!< 0x00040000 */
10096 #define CAN_F10R2_FB18                       CAN_F10R2_FB18_Msk                /*!< Filter bit 18 */
10097 #define CAN_F10R2_FB19_Pos                   (19U)
10098 #define CAN_F10R2_FB19_Msk                   (0x1UL << CAN_F10R2_FB19_Pos)      /*!< 0x00080000 */
10099 #define CAN_F10R2_FB19                       CAN_F10R2_FB19_Msk                /*!< Filter bit 19 */
10100 #define CAN_F10R2_FB20_Pos                   (20U)
10101 #define CAN_F10R2_FB20_Msk                   (0x1UL << CAN_F10R2_FB20_Pos)      /*!< 0x00100000 */
10102 #define CAN_F10R2_FB20                       CAN_F10R2_FB20_Msk                /*!< Filter bit 20 */
10103 #define CAN_F10R2_FB21_Pos                   (21U)
10104 #define CAN_F10R2_FB21_Msk                   (0x1UL << CAN_F10R2_FB21_Pos)      /*!< 0x00200000 */
10105 #define CAN_F10R2_FB21                       CAN_F10R2_FB21_Msk                /*!< Filter bit 21 */
10106 #define CAN_F10R2_FB22_Pos                   (22U)
10107 #define CAN_F10R2_FB22_Msk                   (0x1UL << CAN_F10R2_FB22_Pos)      /*!< 0x00400000 */
10108 #define CAN_F10R2_FB22                       CAN_F10R2_FB22_Msk                /*!< Filter bit 22 */
10109 #define CAN_F10R2_FB23_Pos                   (23U)
10110 #define CAN_F10R2_FB23_Msk                   (0x1UL << CAN_F10R2_FB23_Pos)      /*!< 0x00800000 */
10111 #define CAN_F10R2_FB23                       CAN_F10R2_FB23_Msk                /*!< Filter bit 23 */
10112 #define CAN_F10R2_FB24_Pos                   (24U)
10113 #define CAN_F10R2_FB24_Msk                   (0x1UL << CAN_F10R2_FB24_Pos)      /*!< 0x01000000 */
10114 #define CAN_F10R2_FB24                       CAN_F10R2_FB24_Msk                /*!< Filter bit 24 */
10115 #define CAN_F10R2_FB25_Pos                   (25U)
10116 #define CAN_F10R2_FB25_Msk                   (0x1UL << CAN_F10R2_FB25_Pos)      /*!< 0x02000000 */
10117 #define CAN_F10R2_FB25                       CAN_F10R2_FB25_Msk                /*!< Filter bit 25 */
10118 #define CAN_F10R2_FB26_Pos                   (26U)
10119 #define CAN_F10R2_FB26_Msk                   (0x1UL << CAN_F10R2_FB26_Pos)      /*!< 0x04000000 */
10120 #define CAN_F10R2_FB26                       CAN_F10R2_FB26_Msk                /*!< Filter bit 26 */
10121 #define CAN_F10R2_FB27_Pos                   (27U)
10122 #define CAN_F10R2_FB27_Msk                   (0x1UL << CAN_F10R2_FB27_Pos)      /*!< 0x08000000 */
10123 #define CAN_F10R2_FB27                       CAN_F10R2_FB27_Msk                /*!< Filter bit 27 */
10124 #define CAN_F10R2_FB28_Pos                   (28U)
10125 #define CAN_F10R2_FB28_Msk                   (0x1UL << CAN_F10R2_FB28_Pos)      /*!< 0x10000000 */
10126 #define CAN_F10R2_FB28                       CAN_F10R2_FB28_Msk                /*!< Filter bit 28 */
10127 #define CAN_F10R2_FB29_Pos                   (29U)
10128 #define CAN_F10R2_FB29_Msk                   (0x1UL << CAN_F10R2_FB29_Pos)      /*!< 0x20000000 */
10129 #define CAN_F10R2_FB29                       CAN_F10R2_FB29_Msk                /*!< Filter bit 29 */
10130 #define CAN_F10R2_FB30_Pos                   (30U)
10131 #define CAN_F10R2_FB30_Msk                   (0x1UL << CAN_F10R2_FB30_Pos)      /*!< 0x40000000 */
10132 #define CAN_F10R2_FB30                       CAN_F10R2_FB30_Msk                /*!< Filter bit 30 */
10133 #define CAN_F10R2_FB31_Pos                   (31U)
10134 #define CAN_F10R2_FB31_Msk                   (0x1UL << CAN_F10R2_FB31_Pos)      /*!< 0x80000000 */
10135 #define CAN_F10R2_FB31                       CAN_F10R2_FB31_Msk                /*!< Filter bit 31 */
10136 
10137 /*******************  Bit definition for CAN_F11R2 register  ******************/
10138 #define CAN_F11R2_FB0_Pos                    (0U)
10139 #define CAN_F11R2_FB0_Msk                    (0x1UL << CAN_F11R2_FB0_Pos)       /*!< 0x00000001 */
10140 #define CAN_F11R2_FB0                        CAN_F11R2_FB0_Msk                 /*!< Filter bit 0 */
10141 #define CAN_F11R2_FB1_Pos                    (1U)
10142 #define CAN_F11R2_FB1_Msk                    (0x1UL << CAN_F11R2_FB1_Pos)       /*!< 0x00000002 */
10143 #define CAN_F11R2_FB1                        CAN_F11R2_FB1_Msk                 /*!< Filter bit 1 */
10144 #define CAN_F11R2_FB2_Pos                    (2U)
10145 #define CAN_F11R2_FB2_Msk                    (0x1UL << CAN_F11R2_FB2_Pos)       /*!< 0x00000004 */
10146 #define CAN_F11R2_FB2                        CAN_F11R2_FB2_Msk                 /*!< Filter bit 2 */
10147 #define CAN_F11R2_FB3_Pos                    (3U)
10148 #define CAN_F11R2_FB3_Msk                    (0x1UL << CAN_F11R2_FB3_Pos)       /*!< 0x00000008 */
10149 #define CAN_F11R2_FB3                        CAN_F11R2_FB3_Msk                 /*!< Filter bit 3 */
10150 #define CAN_F11R2_FB4_Pos                    (4U)
10151 #define CAN_F11R2_FB4_Msk                    (0x1UL << CAN_F11R2_FB4_Pos)       /*!< 0x00000010 */
10152 #define CAN_F11R2_FB4                        CAN_F11R2_FB4_Msk                 /*!< Filter bit 4 */
10153 #define CAN_F11R2_FB5_Pos                    (5U)
10154 #define CAN_F11R2_FB5_Msk                    (0x1UL << CAN_F11R2_FB5_Pos)       /*!< 0x00000020 */
10155 #define CAN_F11R2_FB5                        CAN_F11R2_FB5_Msk                 /*!< Filter bit 5 */
10156 #define CAN_F11R2_FB6_Pos                    (6U)
10157 #define CAN_F11R2_FB6_Msk                    (0x1UL << CAN_F11R2_FB6_Pos)       /*!< 0x00000040 */
10158 #define CAN_F11R2_FB6                        CAN_F11R2_FB6_Msk                 /*!< Filter bit 6 */
10159 #define CAN_F11R2_FB7_Pos                    (7U)
10160 #define CAN_F11R2_FB7_Msk                    (0x1UL << CAN_F11R2_FB7_Pos)       /*!< 0x00000080 */
10161 #define CAN_F11R2_FB7                        CAN_F11R2_FB7_Msk                 /*!< Filter bit 7 */
10162 #define CAN_F11R2_FB8_Pos                    (8U)
10163 #define CAN_F11R2_FB8_Msk                    (0x1UL << CAN_F11R2_FB8_Pos)       /*!< 0x00000100 */
10164 #define CAN_F11R2_FB8                        CAN_F11R2_FB8_Msk                 /*!< Filter bit 8 */
10165 #define CAN_F11R2_FB9_Pos                    (9U)
10166 #define CAN_F11R2_FB9_Msk                    (0x1UL << CAN_F11R2_FB9_Pos)       /*!< 0x00000200 */
10167 #define CAN_F11R2_FB9                        CAN_F11R2_FB9_Msk                 /*!< Filter bit 9 */
10168 #define CAN_F11R2_FB10_Pos                   (10U)
10169 #define CAN_F11R2_FB10_Msk                   (0x1UL << CAN_F11R2_FB10_Pos)      /*!< 0x00000400 */
10170 #define CAN_F11R2_FB10                       CAN_F11R2_FB10_Msk                /*!< Filter bit 10 */
10171 #define CAN_F11R2_FB11_Pos                   (11U)
10172 #define CAN_F11R2_FB11_Msk                   (0x1UL << CAN_F11R2_FB11_Pos)      /*!< 0x00000800 */
10173 #define CAN_F11R2_FB11                       CAN_F11R2_FB11_Msk                /*!< Filter bit 11 */
10174 #define CAN_F11R2_FB12_Pos                   (12U)
10175 #define CAN_F11R2_FB12_Msk                   (0x1UL << CAN_F11R2_FB12_Pos)      /*!< 0x00001000 */
10176 #define CAN_F11R2_FB12                       CAN_F11R2_FB12_Msk                /*!< Filter bit 12 */
10177 #define CAN_F11R2_FB13_Pos                   (13U)
10178 #define CAN_F11R2_FB13_Msk                   (0x1UL << CAN_F11R2_FB13_Pos)      /*!< 0x00002000 */
10179 #define CAN_F11R2_FB13                       CAN_F11R2_FB13_Msk                /*!< Filter bit 13 */
10180 #define CAN_F11R2_FB14_Pos                   (14U)
10181 #define CAN_F11R2_FB14_Msk                   (0x1UL << CAN_F11R2_FB14_Pos)      /*!< 0x00004000 */
10182 #define CAN_F11R2_FB14                       CAN_F11R2_FB14_Msk                /*!< Filter bit 14 */
10183 #define CAN_F11R2_FB15_Pos                   (15U)
10184 #define CAN_F11R2_FB15_Msk                   (0x1UL << CAN_F11R2_FB15_Pos)      /*!< 0x00008000 */
10185 #define CAN_F11R2_FB15                       CAN_F11R2_FB15_Msk                /*!< Filter bit 15 */
10186 #define CAN_F11R2_FB16_Pos                   (16U)
10187 #define CAN_F11R2_FB16_Msk                   (0x1UL << CAN_F11R2_FB16_Pos)      /*!< 0x00010000 */
10188 #define CAN_F11R2_FB16                       CAN_F11R2_FB16_Msk                /*!< Filter bit 16 */
10189 #define CAN_F11R2_FB17_Pos                   (17U)
10190 #define CAN_F11R2_FB17_Msk                   (0x1UL << CAN_F11R2_FB17_Pos)      /*!< 0x00020000 */
10191 #define CAN_F11R2_FB17                       CAN_F11R2_FB17_Msk                /*!< Filter bit 17 */
10192 #define CAN_F11R2_FB18_Pos                   (18U)
10193 #define CAN_F11R2_FB18_Msk                   (0x1UL << CAN_F11R2_FB18_Pos)      /*!< 0x00040000 */
10194 #define CAN_F11R2_FB18                       CAN_F11R2_FB18_Msk                /*!< Filter bit 18 */
10195 #define CAN_F11R2_FB19_Pos                   (19U)
10196 #define CAN_F11R2_FB19_Msk                   (0x1UL << CAN_F11R2_FB19_Pos)      /*!< 0x00080000 */
10197 #define CAN_F11R2_FB19                       CAN_F11R2_FB19_Msk                /*!< Filter bit 19 */
10198 #define CAN_F11R2_FB20_Pos                   (20U)
10199 #define CAN_F11R2_FB20_Msk                   (0x1UL << CAN_F11R2_FB20_Pos)      /*!< 0x00100000 */
10200 #define CAN_F11R2_FB20                       CAN_F11R2_FB20_Msk                /*!< Filter bit 20 */
10201 #define CAN_F11R2_FB21_Pos                   (21U)
10202 #define CAN_F11R2_FB21_Msk                   (0x1UL << CAN_F11R2_FB21_Pos)      /*!< 0x00200000 */
10203 #define CAN_F11R2_FB21                       CAN_F11R2_FB21_Msk                /*!< Filter bit 21 */
10204 #define CAN_F11R2_FB22_Pos                   (22U)
10205 #define CAN_F11R2_FB22_Msk                   (0x1UL << CAN_F11R2_FB22_Pos)      /*!< 0x00400000 */
10206 #define CAN_F11R2_FB22                       CAN_F11R2_FB22_Msk                /*!< Filter bit 22 */
10207 #define CAN_F11R2_FB23_Pos                   (23U)
10208 #define CAN_F11R2_FB23_Msk                   (0x1UL << CAN_F11R2_FB23_Pos)      /*!< 0x00800000 */
10209 #define CAN_F11R2_FB23                       CAN_F11R2_FB23_Msk                /*!< Filter bit 23 */
10210 #define CAN_F11R2_FB24_Pos                   (24U)
10211 #define CAN_F11R2_FB24_Msk                   (0x1UL << CAN_F11R2_FB24_Pos)      /*!< 0x01000000 */
10212 #define CAN_F11R2_FB24                       CAN_F11R2_FB24_Msk                /*!< Filter bit 24 */
10213 #define CAN_F11R2_FB25_Pos                   (25U)
10214 #define CAN_F11R2_FB25_Msk                   (0x1UL << CAN_F11R2_FB25_Pos)      /*!< 0x02000000 */
10215 #define CAN_F11R2_FB25                       CAN_F11R2_FB25_Msk                /*!< Filter bit 25 */
10216 #define CAN_F11R2_FB26_Pos                   (26U)
10217 #define CAN_F11R2_FB26_Msk                   (0x1UL << CAN_F11R2_FB26_Pos)      /*!< 0x04000000 */
10218 #define CAN_F11R2_FB26                       CAN_F11R2_FB26_Msk                /*!< Filter bit 26 */
10219 #define CAN_F11R2_FB27_Pos                   (27U)
10220 #define CAN_F11R2_FB27_Msk                   (0x1UL << CAN_F11R2_FB27_Pos)      /*!< 0x08000000 */
10221 #define CAN_F11R2_FB27                       CAN_F11R2_FB27_Msk                /*!< Filter bit 27 */
10222 #define CAN_F11R2_FB28_Pos                   (28U)
10223 #define CAN_F11R2_FB28_Msk                   (0x1UL << CAN_F11R2_FB28_Pos)      /*!< 0x10000000 */
10224 #define CAN_F11R2_FB28                       CAN_F11R2_FB28_Msk                /*!< Filter bit 28 */
10225 #define CAN_F11R2_FB29_Pos                   (29U)
10226 #define CAN_F11R2_FB29_Msk                   (0x1UL << CAN_F11R2_FB29_Pos)      /*!< 0x20000000 */
10227 #define CAN_F11R2_FB29                       CAN_F11R2_FB29_Msk                /*!< Filter bit 29 */
10228 #define CAN_F11R2_FB30_Pos                   (30U)
10229 #define CAN_F11R2_FB30_Msk                   (0x1UL << CAN_F11R2_FB30_Pos)      /*!< 0x40000000 */
10230 #define CAN_F11R2_FB30                       CAN_F11R2_FB30_Msk                /*!< Filter bit 30 */
10231 #define CAN_F11R2_FB31_Pos                   (31U)
10232 #define CAN_F11R2_FB31_Msk                   (0x1UL << CAN_F11R2_FB31_Pos)      /*!< 0x80000000 */
10233 #define CAN_F11R2_FB31                       CAN_F11R2_FB31_Msk                /*!< Filter bit 31 */
10234 
10235 /*******************  Bit definition for CAN_F12R2 register  ******************/
10236 #define CAN_F12R2_FB0_Pos                    (0U)
10237 #define CAN_F12R2_FB0_Msk                    (0x1UL << CAN_F12R2_FB0_Pos)       /*!< 0x00000001 */
10238 #define CAN_F12R2_FB0                        CAN_F12R2_FB0_Msk                 /*!< Filter bit 0 */
10239 #define CAN_F12R2_FB1_Pos                    (1U)
10240 #define CAN_F12R2_FB1_Msk                    (0x1UL << CAN_F12R2_FB1_Pos)       /*!< 0x00000002 */
10241 #define CAN_F12R2_FB1                        CAN_F12R2_FB1_Msk                 /*!< Filter bit 1 */
10242 #define CAN_F12R2_FB2_Pos                    (2U)
10243 #define CAN_F12R2_FB2_Msk                    (0x1UL << CAN_F12R2_FB2_Pos)       /*!< 0x00000004 */
10244 #define CAN_F12R2_FB2                        CAN_F12R2_FB2_Msk                 /*!< Filter bit 2 */
10245 #define CAN_F12R2_FB3_Pos                    (3U)
10246 #define CAN_F12R2_FB3_Msk                    (0x1UL << CAN_F12R2_FB3_Pos)       /*!< 0x00000008 */
10247 #define CAN_F12R2_FB3                        CAN_F12R2_FB3_Msk                 /*!< Filter bit 3 */
10248 #define CAN_F12R2_FB4_Pos                    (4U)
10249 #define CAN_F12R2_FB4_Msk                    (0x1UL << CAN_F12R2_FB4_Pos)       /*!< 0x00000010 */
10250 #define CAN_F12R2_FB4                        CAN_F12R2_FB4_Msk                 /*!< Filter bit 4 */
10251 #define CAN_F12R2_FB5_Pos                    (5U)
10252 #define CAN_F12R2_FB5_Msk                    (0x1UL << CAN_F12R2_FB5_Pos)       /*!< 0x00000020 */
10253 #define CAN_F12R2_FB5                        CAN_F12R2_FB5_Msk                 /*!< Filter bit 5 */
10254 #define CAN_F12R2_FB6_Pos                    (6U)
10255 #define CAN_F12R2_FB6_Msk                    (0x1UL << CAN_F12R2_FB6_Pos)       /*!< 0x00000040 */
10256 #define CAN_F12R2_FB6                        CAN_F12R2_FB6_Msk                 /*!< Filter bit 6 */
10257 #define CAN_F12R2_FB7_Pos                    (7U)
10258 #define CAN_F12R2_FB7_Msk                    (0x1UL << CAN_F12R2_FB7_Pos)       /*!< 0x00000080 */
10259 #define CAN_F12R2_FB7                        CAN_F12R2_FB7_Msk                 /*!< Filter bit 7 */
10260 #define CAN_F12R2_FB8_Pos                    (8U)
10261 #define CAN_F12R2_FB8_Msk                    (0x1UL << CAN_F12R2_FB8_Pos)       /*!< 0x00000100 */
10262 #define CAN_F12R2_FB8                        CAN_F12R2_FB8_Msk                 /*!< Filter bit 8 */
10263 #define CAN_F12R2_FB9_Pos                    (9U)
10264 #define CAN_F12R2_FB9_Msk                    (0x1UL << CAN_F12R2_FB9_Pos)       /*!< 0x00000200 */
10265 #define CAN_F12R2_FB9                        CAN_F12R2_FB9_Msk                 /*!< Filter bit 9 */
10266 #define CAN_F12R2_FB10_Pos                   (10U)
10267 #define CAN_F12R2_FB10_Msk                   (0x1UL << CAN_F12R2_FB10_Pos)      /*!< 0x00000400 */
10268 #define CAN_F12R2_FB10                       CAN_F12R2_FB10_Msk                /*!< Filter bit 10 */
10269 #define CAN_F12R2_FB11_Pos                   (11U)
10270 #define CAN_F12R2_FB11_Msk                   (0x1UL << CAN_F12R2_FB11_Pos)      /*!< 0x00000800 */
10271 #define CAN_F12R2_FB11                       CAN_F12R2_FB11_Msk                /*!< Filter bit 11 */
10272 #define CAN_F12R2_FB12_Pos                   (12U)
10273 #define CAN_F12R2_FB12_Msk                   (0x1UL << CAN_F12R2_FB12_Pos)      /*!< 0x00001000 */
10274 #define CAN_F12R2_FB12                       CAN_F12R2_FB12_Msk                /*!< Filter bit 12 */
10275 #define CAN_F12R2_FB13_Pos                   (13U)
10276 #define CAN_F12R2_FB13_Msk                   (0x1UL << CAN_F12R2_FB13_Pos)      /*!< 0x00002000 */
10277 #define CAN_F12R2_FB13                       CAN_F12R2_FB13_Msk                /*!< Filter bit 13 */
10278 #define CAN_F12R2_FB14_Pos                   (14U)
10279 #define CAN_F12R2_FB14_Msk                   (0x1UL << CAN_F12R2_FB14_Pos)      /*!< 0x00004000 */
10280 #define CAN_F12R2_FB14                       CAN_F12R2_FB14_Msk                /*!< Filter bit 14 */
10281 #define CAN_F12R2_FB15_Pos                   (15U)
10282 #define CAN_F12R2_FB15_Msk                   (0x1UL << CAN_F12R2_FB15_Pos)      /*!< 0x00008000 */
10283 #define CAN_F12R2_FB15                       CAN_F12R2_FB15_Msk                /*!< Filter bit 15 */
10284 #define CAN_F12R2_FB16_Pos                   (16U)
10285 #define CAN_F12R2_FB16_Msk                   (0x1UL << CAN_F12R2_FB16_Pos)      /*!< 0x00010000 */
10286 #define CAN_F12R2_FB16                       CAN_F12R2_FB16_Msk                /*!< Filter bit 16 */
10287 #define CAN_F12R2_FB17_Pos                   (17U)
10288 #define CAN_F12R2_FB17_Msk                   (0x1UL << CAN_F12R2_FB17_Pos)      /*!< 0x00020000 */
10289 #define CAN_F12R2_FB17                       CAN_F12R2_FB17_Msk                /*!< Filter bit 17 */
10290 #define CAN_F12R2_FB18_Pos                   (18U)
10291 #define CAN_F12R2_FB18_Msk                   (0x1UL << CAN_F12R2_FB18_Pos)      /*!< 0x00040000 */
10292 #define CAN_F12R2_FB18                       CAN_F12R2_FB18_Msk                /*!< Filter bit 18 */
10293 #define CAN_F12R2_FB19_Pos                   (19U)
10294 #define CAN_F12R2_FB19_Msk                   (0x1UL << CAN_F12R2_FB19_Pos)      /*!< 0x00080000 */
10295 #define CAN_F12R2_FB19                       CAN_F12R2_FB19_Msk                /*!< Filter bit 19 */
10296 #define CAN_F12R2_FB20_Pos                   (20U)
10297 #define CAN_F12R2_FB20_Msk                   (0x1UL << CAN_F12R2_FB20_Pos)      /*!< 0x00100000 */
10298 #define CAN_F12R2_FB20                       CAN_F12R2_FB20_Msk                /*!< Filter bit 20 */
10299 #define CAN_F12R2_FB21_Pos                   (21U)
10300 #define CAN_F12R2_FB21_Msk                   (0x1UL << CAN_F12R2_FB21_Pos)      /*!< 0x00200000 */
10301 #define CAN_F12R2_FB21                       CAN_F12R2_FB21_Msk                /*!< Filter bit 21 */
10302 #define CAN_F12R2_FB22_Pos                   (22U)
10303 #define CAN_F12R2_FB22_Msk                   (0x1UL << CAN_F12R2_FB22_Pos)      /*!< 0x00400000 */
10304 #define CAN_F12R2_FB22                       CAN_F12R2_FB22_Msk                /*!< Filter bit 22 */
10305 #define CAN_F12R2_FB23_Pos                   (23U)
10306 #define CAN_F12R2_FB23_Msk                   (0x1UL << CAN_F12R2_FB23_Pos)      /*!< 0x00800000 */
10307 #define CAN_F12R2_FB23                       CAN_F12R2_FB23_Msk                /*!< Filter bit 23 */
10308 #define CAN_F12R2_FB24_Pos                   (24U)
10309 #define CAN_F12R2_FB24_Msk                   (0x1UL << CAN_F12R2_FB24_Pos)      /*!< 0x01000000 */
10310 #define CAN_F12R2_FB24                       CAN_F12R2_FB24_Msk                /*!< Filter bit 24 */
10311 #define CAN_F12R2_FB25_Pos                   (25U)
10312 #define CAN_F12R2_FB25_Msk                   (0x1UL << CAN_F12R2_FB25_Pos)      /*!< 0x02000000 */
10313 #define CAN_F12R2_FB25                       CAN_F12R2_FB25_Msk                /*!< Filter bit 25 */
10314 #define CAN_F12R2_FB26_Pos                   (26U)
10315 #define CAN_F12R2_FB26_Msk                   (0x1UL << CAN_F12R2_FB26_Pos)      /*!< 0x04000000 */
10316 #define CAN_F12R2_FB26                       CAN_F12R2_FB26_Msk                /*!< Filter bit 26 */
10317 #define CAN_F12R2_FB27_Pos                   (27U)
10318 #define CAN_F12R2_FB27_Msk                   (0x1UL << CAN_F12R2_FB27_Pos)      /*!< 0x08000000 */
10319 #define CAN_F12R2_FB27                       CAN_F12R2_FB27_Msk                /*!< Filter bit 27 */
10320 #define CAN_F12R2_FB28_Pos                   (28U)
10321 #define CAN_F12R2_FB28_Msk                   (0x1UL << CAN_F12R2_FB28_Pos)      /*!< 0x10000000 */
10322 #define CAN_F12R2_FB28                       CAN_F12R2_FB28_Msk                /*!< Filter bit 28 */
10323 #define CAN_F12R2_FB29_Pos                   (29U)
10324 #define CAN_F12R2_FB29_Msk                   (0x1UL << CAN_F12R2_FB29_Pos)      /*!< 0x20000000 */
10325 #define CAN_F12R2_FB29                       CAN_F12R2_FB29_Msk                /*!< Filter bit 29 */
10326 #define CAN_F12R2_FB30_Pos                   (30U)
10327 #define CAN_F12R2_FB30_Msk                   (0x1UL << CAN_F12R2_FB30_Pos)      /*!< 0x40000000 */
10328 #define CAN_F12R2_FB30                       CAN_F12R2_FB30_Msk                /*!< Filter bit 30 */
10329 #define CAN_F12R2_FB31_Pos                   (31U)
10330 #define CAN_F12R2_FB31_Msk                   (0x1UL << CAN_F12R2_FB31_Pos)      /*!< 0x80000000 */
10331 #define CAN_F12R2_FB31                       CAN_F12R2_FB31_Msk                /*!< Filter bit 31 */
10332 
10333 /*******************  Bit definition for CAN_F13R2 register  ******************/
10334 #define CAN_F13R2_FB0_Pos                    (0U)
10335 #define CAN_F13R2_FB0_Msk                    (0x1UL << CAN_F13R2_FB0_Pos)       /*!< 0x00000001 */
10336 #define CAN_F13R2_FB0                        CAN_F13R2_FB0_Msk                 /*!< Filter bit 0 */
10337 #define CAN_F13R2_FB1_Pos                    (1U)
10338 #define CAN_F13R2_FB1_Msk                    (0x1UL << CAN_F13R2_FB1_Pos)       /*!< 0x00000002 */
10339 #define CAN_F13R2_FB1                        CAN_F13R2_FB1_Msk                 /*!< Filter bit 1 */
10340 #define CAN_F13R2_FB2_Pos                    (2U)
10341 #define CAN_F13R2_FB2_Msk                    (0x1UL << CAN_F13R2_FB2_Pos)       /*!< 0x00000004 */
10342 #define CAN_F13R2_FB2                        CAN_F13R2_FB2_Msk                 /*!< Filter bit 2 */
10343 #define CAN_F13R2_FB3_Pos                    (3U)
10344 #define CAN_F13R2_FB3_Msk                    (0x1UL << CAN_F13R2_FB3_Pos)       /*!< 0x00000008 */
10345 #define CAN_F13R2_FB3                        CAN_F13R2_FB3_Msk                 /*!< Filter bit 3 */
10346 #define CAN_F13R2_FB4_Pos                    (4U)
10347 #define CAN_F13R2_FB4_Msk                    (0x1UL << CAN_F13R2_FB4_Pos)       /*!< 0x00000010 */
10348 #define CAN_F13R2_FB4                        CAN_F13R2_FB4_Msk                 /*!< Filter bit 4 */
10349 #define CAN_F13R2_FB5_Pos                    (5U)
10350 #define CAN_F13R2_FB5_Msk                    (0x1UL << CAN_F13R2_FB5_Pos)       /*!< 0x00000020 */
10351 #define CAN_F13R2_FB5                        CAN_F13R2_FB5_Msk                 /*!< Filter bit 5 */
10352 #define CAN_F13R2_FB6_Pos                    (6U)
10353 #define CAN_F13R2_FB6_Msk                    (0x1UL << CAN_F13R2_FB6_Pos)       /*!< 0x00000040 */
10354 #define CAN_F13R2_FB6                        CAN_F13R2_FB6_Msk                 /*!< Filter bit 6 */
10355 #define CAN_F13R2_FB7_Pos                    (7U)
10356 #define CAN_F13R2_FB7_Msk                    (0x1UL << CAN_F13R2_FB7_Pos)       /*!< 0x00000080 */
10357 #define CAN_F13R2_FB7                        CAN_F13R2_FB7_Msk                 /*!< Filter bit 7 */
10358 #define CAN_F13R2_FB8_Pos                    (8U)
10359 #define CAN_F13R2_FB8_Msk                    (0x1UL << CAN_F13R2_FB8_Pos)       /*!< 0x00000100 */
10360 #define CAN_F13R2_FB8                        CAN_F13R2_FB8_Msk                 /*!< Filter bit 8 */
10361 #define CAN_F13R2_FB9_Pos                    (9U)
10362 #define CAN_F13R2_FB9_Msk                    (0x1UL << CAN_F13R2_FB9_Pos)       /*!< 0x00000200 */
10363 #define CAN_F13R2_FB9                        CAN_F13R2_FB9_Msk                 /*!< Filter bit 9 */
10364 #define CAN_F13R2_FB10_Pos                   (10U)
10365 #define CAN_F13R2_FB10_Msk                   (0x1UL << CAN_F13R2_FB10_Pos)      /*!< 0x00000400 */
10366 #define CAN_F13R2_FB10                       CAN_F13R2_FB10_Msk                /*!< Filter bit 10 */
10367 #define CAN_F13R2_FB11_Pos                   (11U)
10368 #define CAN_F13R2_FB11_Msk                   (0x1UL << CAN_F13R2_FB11_Pos)      /*!< 0x00000800 */
10369 #define CAN_F13R2_FB11                       CAN_F13R2_FB11_Msk                /*!< Filter bit 11 */
10370 #define CAN_F13R2_FB12_Pos                   (12U)
10371 #define CAN_F13R2_FB12_Msk                   (0x1UL << CAN_F13R2_FB12_Pos)      /*!< 0x00001000 */
10372 #define CAN_F13R2_FB12                       CAN_F13R2_FB12_Msk                /*!< Filter bit 12 */
10373 #define CAN_F13R2_FB13_Pos                   (13U)
10374 #define CAN_F13R2_FB13_Msk                   (0x1UL << CAN_F13R2_FB13_Pos)      /*!< 0x00002000 */
10375 #define CAN_F13R2_FB13                       CAN_F13R2_FB13_Msk                /*!< Filter bit 13 */
10376 #define CAN_F13R2_FB14_Pos                   (14U)
10377 #define CAN_F13R2_FB14_Msk                   (0x1UL << CAN_F13R2_FB14_Pos)      /*!< 0x00004000 */
10378 #define CAN_F13R2_FB14                       CAN_F13R2_FB14_Msk                /*!< Filter bit 14 */
10379 #define CAN_F13R2_FB15_Pos                   (15U)
10380 #define CAN_F13R2_FB15_Msk                   (0x1UL << CAN_F13R2_FB15_Pos)      /*!< 0x00008000 */
10381 #define CAN_F13R2_FB15                       CAN_F13R2_FB15_Msk                /*!< Filter bit 15 */
10382 #define CAN_F13R2_FB16_Pos                   (16U)
10383 #define CAN_F13R2_FB16_Msk                   (0x1UL << CAN_F13R2_FB16_Pos)      /*!< 0x00010000 */
10384 #define CAN_F13R2_FB16                       CAN_F13R2_FB16_Msk                /*!< Filter bit 16 */
10385 #define CAN_F13R2_FB17_Pos                   (17U)
10386 #define CAN_F13R2_FB17_Msk                   (0x1UL << CAN_F13R2_FB17_Pos)      /*!< 0x00020000 */
10387 #define CAN_F13R2_FB17                       CAN_F13R2_FB17_Msk                /*!< Filter bit 17 */
10388 #define CAN_F13R2_FB18_Pos                   (18U)
10389 #define CAN_F13R2_FB18_Msk                   (0x1UL << CAN_F13R2_FB18_Pos)      /*!< 0x00040000 */
10390 #define CAN_F13R2_FB18                       CAN_F13R2_FB18_Msk                /*!< Filter bit 18 */
10391 #define CAN_F13R2_FB19_Pos                   (19U)
10392 #define CAN_F13R2_FB19_Msk                   (0x1UL << CAN_F13R2_FB19_Pos)      /*!< 0x00080000 */
10393 #define CAN_F13R2_FB19                       CAN_F13R2_FB19_Msk                /*!< Filter bit 19 */
10394 #define CAN_F13R2_FB20_Pos                   (20U)
10395 #define CAN_F13R2_FB20_Msk                   (0x1UL << CAN_F13R2_FB20_Pos)      /*!< 0x00100000 */
10396 #define CAN_F13R2_FB20                       CAN_F13R2_FB20_Msk                /*!< Filter bit 20 */
10397 #define CAN_F13R2_FB21_Pos                   (21U)
10398 #define CAN_F13R2_FB21_Msk                   (0x1UL << CAN_F13R2_FB21_Pos)      /*!< 0x00200000 */
10399 #define CAN_F13R2_FB21                       CAN_F13R2_FB21_Msk                /*!< Filter bit 21 */
10400 #define CAN_F13R2_FB22_Pos                   (22U)
10401 #define CAN_F13R2_FB22_Msk                   (0x1UL << CAN_F13R2_FB22_Pos)      /*!< 0x00400000 */
10402 #define CAN_F13R2_FB22                       CAN_F13R2_FB22_Msk                /*!< Filter bit 22 */
10403 #define CAN_F13R2_FB23_Pos                   (23U)
10404 #define CAN_F13R2_FB23_Msk                   (0x1UL << CAN_F13R2_FB23_Pos)      /*!< 0x00800000 */
10405 #define CAN_F13R2_FB23                       CAN_F13R2_FB23_Msk                /*!< Filter bit 23 */
10406 #define CAN_F13R2_FB24_Pos                   (24U)
10407 #define CAN_F13R2_FB24_Msk                   (0x1UL << CAN_F13R2_FB24_Pos)      /*!< 0x01000000 */
10408 #define CAN_F13R2_FB24                       CAN_F13R2_FB24_Msk                /*!< Filter bit 24 */
10409 #define CAN_F13R2_FB25_Pos                   (25U)
10410 #define CAN_F13R2_FB25_Msk                   (0x1UL << CAN_F13R2_FB25_Pos)      /*!< 0x02000000 */
10411 #define CAN_F13R2_FB25                       CAN_F13R2_FB25_Msk                /*!< Filter bit 25 */
10412 #define CAN_F13R2_FB26_Pos                   (26U)
10413 #define CAN_F13R2_FB26_Msk                   (0x1UL << CAN_F13R2_FB26_Pos)      /*!< 0x04000000 */
10414 #define CAN_F13R2_FB26                       CAN_F13R2_FB26_Msk                /*!< Filter bit 26 */
10415 #define CAN_F13R2_FB27_Pos                   (27U)
10416 #define CAN_F13R2_FB27_Msk                   (0x1UL << CAN_F13R2_FB27_Pos)      /*!< 0x08000000 */
10417 #define CAN_F13R2_FB27                       CAN_F13R2_FB27_Msk                /*!< Filter bit 27 */
10418 #define CAN_F13R2_FB28_Pos                   (28U)
10419 #define CAN_F13R2_FB28_Msk                   (0x1UL << CAN_F13R2_FB28_Pos)      /*!< 0x10000000 */
10420 #define CAN_F13R2_FB28                       CAN_F13R2_FB28_Msk                /*!< Filter bit 28 */
10421 #define CAN_F13R2_FB29_Pos                   (29U)
10422 #define CAN_F13R2_FB29_Msk                   (0x1UL << CAN_F13R2_FB29_Pos)      /*!< 0x20000000 */
10423 #define CAN_F13R2_FB29                       CAN_F13R2_FB29_Msk                /*!< Filter bit 29 */
10424 #define CAN_F13R2_FB30_Pos                   (30U)
10425 #define CAN_F13R2_FB30_Msk                   (0x1UL << CAN_F13R2_FB30_Pos)      /*!< 0x40000000 */
10426 #define CAN_F13R2_FB30                       CAN_F13R2_FB30_Msk                /*!< Filter bit 30 */
10427 #define CAN_F13R2_FB31_Pos                   (31U)
10428 #define CAN_F13R2_FB31_Msk                   (0x1UL << CAN_F13R2_FB31_Pos)      /*!< 0x80000000 */
10429 #define CAN_F13R2_FB31                       CAN_F13R2_FB31_Msk                /*!< Filter bit 31 */
10430 
10431 /******************************************************************************/
10432 /*                                                                            */
10433 /*                        Serial Peripheral Interface                         */
10434 /*                                                                            */
10435 /******************************************************************************/
10436 /*
10437  * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
10438  */
10439 #define SPI_I2S_SUPPORT       /*!< I2S support */
10440 #define SPI_CRC_ERROR_WORKAROUND_FEATURE
10441 
10442 /*******************  Bit definition for SPI_CR1 register  ********************/
10443 #define SPI_CR1_CPHA_Pos                    (0U)
10444 #define SPI_CR1_CPHA_Msk                    (0x1UL << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */
10445 #define SPI_CR1_CPHA                        SPI_CR1_CPHA_Msk                   /*!< Clock Phase */
10446 #define SPI_CR1_CPOL_Pos                    (1U)
10447 #define SPI_CR1_CPOL_Msk                    (0x1UL << SPI_CR1_CPOL_Pos)         /*!< 0x00000002 */
10448 #define SPI_CR1_CPOL                        SPI_CR1_CPOL_Msk                   /*!< Clock Polarity */
10449 #define SPI_CR1_MSTR_Pos                    (2U)
10450 #define SPI_CR1_MSTR_Msk                    (0x1UL << SPI_CR1_MSTR_Pos)         /*!< 0x00000004 */
10451 #define SPI_CR1_MSTR                        SPI_CR1_MSTR_Msk                   /*!< Master Selection */
10452 
10453 #define SPI_CR1_BR_Pos                      (3U)
10454 #define SPI_CR1_BR_Msk                      (0x7UL << SPI_CR1_BR_Pos)           /*!< 0x00000038 */
10455 #define SPI_CR1_BR                          SPI_CR1_BR_Msk                     /*!< BR[2:0] bits (Baud Rate Control) */
10456 #define SPI_CR1_BR_0                        (0x1UL << SPI_CR1_BR_Pos)           /*!< 0x00000008 */
10457 #define SPI_CR1_BR_1                        (0x2UL << SPI_CR1_BR_Pos)           /*!< 0x00000010 */
10458 #define SPI_CR1_BR_2                        (0x4UL << SPI_CR1_BR_Pos)           /*!< 0x00000020 */
10459 
10460 #define SPI_CR1_SPE_Pos                     (6U)
10461 #define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)          /*!< 0x00000040 */
10462 #define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                    /*!< SPI Enable */
10463 #define SPI_CR1_LSBFIRST_Pos                (7U)
10464 #define SPI_CR1_LSBFIRST_Msk                (0x1UL << SPI_CR1_LSBFIRST_Pos)     /*!< 0x00000080 */
10465 #define SPI_CR1_LSBFIRST                    SPI_CR1_LSBFIRST_Msk               /*!< Frame Format */
10466 #define SPI_CR1_SSI_Pos                     (8U)
10467 #define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)          /*!< 0x00000100 */
10468 #define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                    /*!< Internal slave select */
10469 #define SPI_CR1_SSM_Pos                     (9U)
10470 #define SPI_CR1_SSM_Msk                     (0x1UL << SPI_CR1_SSM_Pos)          /*!< 0x00000200 */
10471 #define SPI_CR1_SSM                         SPI_CR1_SSM_Msk                    /*!< Software slave management */
10472 #define SPI_CR1_RXONLY_Pos                  (10U)
10473 #define SPI_CR1_RXONLY_Msk                  (0x1UL << SPI_CR1_RXONLY_Pos)       /*!< 0x00000400 */
10474 #define SPI_CR1_RXONLY                      SPI_CR1_RXONLY_Msk                 /*!< Receive only */
10475 #define SPI_CR1_DFF_Pos                     (11U)
10476 #define SPI_CR1_DFF_Msk                     (0x1UL << SPI_CR1_DFF_Pos)          /*!< 0x00000800 */
10477 #define SPI_CR1_DFF                         SPI_CR1_DFF_Msk                    /*!< Data Frame Format */
10478 #define SPI_CR1_CRCNEXT_Pos                 (12U)
10479 #define SPI_CR1_CRCNEXT_Msk                 (0x1UL << SPI_CR1_CRCNEXT_Pos)      /*!< 0x00001000 */
10480 #define SPI_CR1_CRCNEXT                     SPI_CR1_CRCNEXT_Msk                /*!< Transmit CRC next */
10481 #define SPI_CR1_CRCEN_Pos                   (13U)
10482 #define SPI_CR1_CRCEN_Msk                   (0x1UL << SPI_CR1_CRCEN_Pos)        /*!< 0x00002000 */
10483 #define SPI_CR1_CRCEN                       SPI_CR1_CRCEN_Msk                  /*!< Hardware CRC calculation enable */
10484 #define SPI_CR1_BIDIOE_Pos                  (14U)
10485 #define SPI_CR1_BIDIOE_Msk                  (0x1UL << SPI_CR1_BIDIOE_Pos)       /*!< 0x00004000 */
10486 #define SPI_CR1_BIDIOE                      SPI_CR1_BIDIOE_Msk                 /*!< Output enable in bidirectional mode */
10487 #define SPI_CR1_BIDIMODE_Pos                (15U)
10488 #define SPI_CR1_BIDIMODE_Msk                (0x1UL << SPI_CR1_BIDIMODE_Pos)     /*!< 0x00008000 */
10489 #define SPI_CR1_BIDIMODE                    SPI_CR1_BIDIMODE_Msk               /*!< Bidirectional data mode enable */
10490 
10491 /*******************  Bit definition for SPI_CR2 register  ********************/
10492 #define SPI_CR2_RXDMAEN_Pos                 (0U)
10493 #define SPI_CR2_RXDMAEN_Msk                 (0x1UL << SPI_CR2_RXDMAEN_Pos)      /*!< 0x00000001 */
10494 #define SPI_CR2_RXDMAEN                     SPI_CR2_RXDMAEN_Msk                /*!< Rx Buffer DMA Enable */
10495 #define SPI_CR2_TXDMAEN_Pos                 (1U)
10496 #define SPI_CR2_TXDMAEN_Msk                 (0x1UL << SPI_CR2_TXDMAEN_Pos)      /*!< 0x00000002 */
10497 #define SPI_CR2_TXDMAEN                     SPI_CR2_TXDMAEN_Msk                /*!< Tx Buffer DMA Enable */
10498 #define SPI_CR2_SSOE_Pos                    (2U)
10499 #define SPI_CR2_SSOE_Msk                    (0x1UL << SPI_CR2_SSOE_Pos)         /*!< 0x00000004 */
10500 #define SPI_CR2_SSOE                        SPI_CR2_SSOE_Msk                   /*!< SS Output Enable */
10501 #define SPI_CR2_ERRIE_Pos                   (5U)
10502 #define SPI_CR2_ERRIE_Msk                   (0x1UL << SPI_CR2_ERRIE_Pos)        /*!< 0x00000020 */
10503 #define SPI_CR2_ERRIE                       SPI_CR2_ERRIE_Msk                  /*!< Error Interrupt Enable */
10504 #define SPI_CR2_RXNEIE_Pos                  (6U)
10505 #define SPI_CR2_RXNEIE_Msk                  (0x1UL << SPI_CR2_RXNEIE_Pos)       /*!< 0x00000040 */
10506 #define SPI_CR2_RXNEIE                      SPI_CR2_RXNEIE_Msk                 /*!< RX buffer Not Empty Interrupt Enable */
10507 #define SPI_CR2_TXEIE_Pos                   (7U)
10508 #define SPI_CR2_TXEIE_Msk                   (0x1UL << SPI_CR2_TXEIE_Pos)        /*!< 0x00000080 */
10509 #define SPI_CR2_TXEIE                       SPI_CR2_TXEIE_Msk                  /*!< Tx buffer Empty Interrupt Enable */
10510 
10511 /********************  Bit definition for SPI_SR register  ********************/
10512 #define SPI_SR_RXNE_Pos                     (0U)
10513 #define SPI_SR_RXNE_Msk                     (0x1UL << SPI_SR_RXNE_Pos)          /*!< 0x00000001 */
10514 #define SPI_SR_RXNE                         SPI_SR_RXNE_Msk                    /*!< Receive buffer Not Empty */
10515 #define SPI_SR_TXE_Pos                      (1U)
10516 #define SPI_SR_TXE_Msk                      (0x1UL << SPI_SR_TXE_Pos)           /*!< 0x00000002 */
10517 #define SPI_SR_TXE                          SPI_SR_TXE_Msk                     /*!< Transmit buffer Empty */
10518 #define SPI_SR_CHSIDE_Pos                   (2U)
10519 #define SPI_SR_CHSIDE_Msk                   (0x1UL << SPI_SR_CHSIDE_Pos)        /*!< 0x00000004 */
10520 #define SPI_SR_CHSIDE                       SPI_SR_CHSIDE_Msk                  /*!< Channel side */
10521 #define SPI_SR_UDR_Pos                      (3U)
10522 #define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)           /*!< 0x00000008 */
10523 #define SPI_SR_UDR                          SPI_SR_UDR_Msk                     /*!< Underrun flag */
10524 #define SPI_SR_CRCERR_Pos                   (4U)
10525 #define SPI_SR_CRCERR_Msk                   (0x1UL << SPI_SR_CRCERR_Pos)        /*!< 0x00000010 */
10526 #define SPI_SR_CRCERR                       SPI_SR_CRCERR_Msk                  /*!< CRC Error flag */
10527 #define SPI_SR_MODF_Pos                     (5U)
10528 #define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)          /*!< 0x00000020 */
10529 #define SPI_SR_MODF                         SPI_SR_MODF_Msk                    /*!< Mode fault */
10530 #define SPI_SR_OVR_Pos                      (6U)
10531 #define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)           /*!< 0x00000040 */
10532 #define SPI_SR_OVR                          SPI_SR_OVR_Msk                     /*!< Overrun flag */
10533 #define SPI_SR_BSY_Pos                      (7U)
10534 #define SPI_SR_BSY_Msk                      (0x1UL << SPI_SR_BSY_Pos)           /*!< 0x00000080 */
10535 #define SPI_SR_BSY                          SPI_SR_BSY_Msk                     /*!< Busy flag */
10536 
10537 /********************  Bit definition for SPI_DR register  ********************/
10538 #define SPI_DR_DR_Pos                       (0U)
10539 #define SPI_DR_DR_Msk                       (0xFFFFUL << SPI_DR_DR_Pos)         /*!< 0x0000FFFF */
10540 #define SPI_DR_DR                           SPI_DR_DR_Msk                      /*!< Data Register */
10541 
10542 /*******************  Bit definition for SPI_CRCPR register  ******************/
10543 #define SPI_CRCPR_CRCPOLY_Pos               (0U)
10544 #define SPI_CRCPR_CRCPOLY_Msk               (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
10545 #define SPI_CRCPR_CRCPOLY                   SPI_CRCPR_CRCPOLY_Msk              /*!< CRC polynomial register */
10546 
10547 /******************  Bit definition for SPI_RXCRCR register  ******************/
10548 #define SPI_RXCRCR_RXCRC_Pos                (0U)
10549 #define SPI_RXCRCR_RXCRC_Msk                (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)  /*!< 0x0000FFFF */
10550 #define SPI_RXCRCR_RXCRC                    SPI_RXCRCR_RXCRC_Msk               /*!< Rx CRC Register */
10551 
10552 /******************  Bit definition for SPI_TXCRCR register  ******************/
10553 #define SPI_TXCRCR_TXCRC_Pos                (0U)
10554 #define SPI_TXCRCR_TXCRC_Msk                (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)  /*!< 0x0000FFFF */
10555 #define SPI_TXCRCR_TXCRC                    SPI_TXCRCR_TXCRC_Msk               /*!< Tx CRC Register */
10556 
10557 /******************  Bit definition for SPI_I2SCFGR register  *****************/
10558 #define SPI_I2SCFGR_CHLEN_Pos               (0U)
10559 #define SPI_I2SCFGR_CHLEN_Msk               (0x1UL << SPI_I2SCFGR_CHLEN_Pos)    /*!< 0x00000001 */
10560 #define SPI_I2SCFGR_CHLEN                   SPI_I2SCFGR_CHLEN_Msk              /*!< Channel length (number of bits per audio channel) */
10561 
10562 #define SPI_I2SCFGR_DATLEN_Pos              (1U)
10563 #define SPI_I2SCFGR_DATLEN_Msk              (0x3UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000006 */
10564 #define SPI_I2SCFGR_DATLEN                  SPI_I2SCFGR_DATLEN_Msk             /*!< DATLEN[1:0] bits (Data length to be transferred) */
10565 #define SPI_I2SCFGR_DATLEN_0                (0x1UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000002 */
10566 #define SPI_I2SCFGR_DATLEN_1                (0x2UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000004 */
10567 
10568 #define SPI_I2SCFGR_CKPOL_Pos               (3U)
10569 #define SPI_I2SCFGR_CKPOL_Msk               (0x1UL << SPI_I2SCFGR_CKPOL_Pos)    /*!< 0x00000008 */
10570 #define SPI_I2SCFGR_CKPOL                   SPI_I2SCFGR_CKPOL_Msk              /*!< steady state clock polarity */
10571 
10572 #define SPI_I2SCFGR_I2SSTD_Pos              (4U)
10573 #define SPI_I2SCFGR_I2SSTD_Msk              (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000030 */
10574 #define SPI_I2SCFGR_I2SSTD                  SPI_I2SCFGR_I2SSTD_Msk             /*!< I2SSTD[1:0] bits (I2S standard selection) */
10575 #define SPI_I2SCFGR_I2SSTD_0                (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000010 */
10576 #define SPI_I2SCFGR_I2SSTD_1                (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000020 */
10577 
10578 #define SPI_I2SCFGR_PCMSYNC_Pos             (7U)
10579 #define SPI_I2SCFGR_PCMSYNC_Msk             (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)  /*!< 0x00000080 */
10580 #define SPI_I2SCFGR_PCMSYNC                 SPI_I2SCFGR_PCMSYNC_Msk            /*!< PCM frame synchronization */
10581 
10582 #define SPI_I2SCFGR_I2SCFG_Pos              (8U)
10583 #define SPI_I2SCFGR_I2SCFG_Msk              (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000300 */
10584 #define SPI_I2SCFGR_I2SCFG                  SPI_I2SCFGR_I2SCFG_Msk             /*!< I2SCFG[1:0] bits (I2S configuration mode) */
10585 #define SPI_I2SCFGR_I2SCFG_0                (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000100 */
10586 #define SPI_I2SCFGR_I2SCFG_1                (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000200 */
10587 
10588 #define SPI_I2SCFGR_I2SE_Pos                (10U)
10589 #define SPI_I2SCFGR_I2SE_Msk                (0x1UL << SPI_I2SCFGR_I2SE_Pos)     /*!< 0x00000400 */
10590 #define SPI_I2SCFGR_I2SE                    SPI_I2SCFGR_I2SE_Msk               /*!< I2S Enable */
10591 #define SPI_I2SCFGR_I2SMOD_Pos              (11U)
10592 #define SPI_I2SCFGR_I2SMOD_Msk              (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)   /*!< 0x00000800 */
10593 #define SPI_I2SCFGR_I2SMOD                  SPI_I2SCFGR_I2SMOD_Msk             /*!< I2S mode selection */
10594 /******************  Bit definition for SPI_I2SPR register  *******************/
10595 #define SPI_I2SPR_I2SDIV_Pos                (0U)
10596 #define SPI_I2SPR_I2SDIV_Msk                (0xFFUL << SPI_I2SPR_I2SDIV_Pos)    /*!< 0x000000FF */
10597 #define SPI_I2SPR_I2SDIV                    SPI_I2SPR_I2SDIV_Msk               /*!< I2S Linear prescaler */
10598 #define SPI_I2SPR_ODD_Pos                   (8U)
10599 #define SPI_I2SPR_ODD_Msk                   (0x1UL << SPI_I2SPR_ODD_Pos)        /*!< 0x00000100 */
10600 #define SPI_I2SPR_ODD                       SPI_I2SPR_ODD_Msk                  /*!< Odd factor for the prescaler */
10601 #define SPI_I2SPR_MCKOE_Pos                 (9U)
10602 #define SPI_I2SPR_MCKOE_Msk                 (0x1UL << SPI_I2SPR_MCKOE_Pos)      /*!< 0x00000200 */
10603 #define SPI_I2SPR_MCKOE                     SPI_I2SPR_MCKOE_Msk                /*!< Master Clock Output Enable */
10604 
10605 /******************************************************************************/
10606 /*                                                                            */
10607 /*                      Inter-integrated Circuit Interface                    */
10608 /*                                                                            */
10609 /******************************************************************************/
10610 
10611 /*******************  Bit definition for I2C_CR1 register  ********************/
10612 #define I2C_CR1_PE_Pos                      (0U)
10613 #define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)           /*!< 0x00000001 */
10614 #define I2C_CR1_PE                          I2C_CR1_PE_Msk                     /*!< Peripheral Enable */
10615 #define I2C_CR1_SMBUS_Pos                   (1U)
10616 #define I2C_CR1_SMBUS_Msk                   (0x1UL << I2C_CR1_SMBUS_Pos)        /*!< 0x00000002 */
10617 #define I2C_CR1_SMBUS                       I2C_CR1_SMBUS_Msk                  /*!< SMBus Mode */
10618 #define I2C_CR1_SMBTYPE_Pos                 (3U)
10619 #define I2C_CR1_SMBTYPE_Msk                 (0x1UL << I2C_CR1_SMBTYPE_Pos)      /*!< 0x00000008 */
10620 #define I2C_CR1_SMBTYPE                     I2C_CR1_SMBTYPE_Msk                /*!< SMBus Type */
10621 #define I2C_CR1_ENARP_Pos                   (4U)
10622 #define I2C_CR1_ENARP_Msk                   (0x1UL << I2C_CR1_ENARP_Pos)        /*!< 0x00000010 */
10623 #define I2C_CR1_ENARP                       I2C_CR1_ENARP_Msk                  /*!< ARP Enable */
10624 #define I2C_CR1_ENPEC_Pos                   (5U)
10625 #define I2C_CR1_ENPEC_Msk                   (0x1UL << I2C_CR1_ENPEC_Pos)        /*!< 0x00000020 */
10626 #define I2C_CR1_ENPEC                       I2C_CR1_ENPEC_Msk                  /*!< PEC Enable */
10627 #define I2C_CR1_ENGC_Pos                    (6U)
10628 #define I2C_CR1_ENGC_Msk                    (0x1UL << I2C_CR1_ENGC_Pos)         /*!< 0x00000040 */
10629 #define I2C_CR1_ENGC                        I2C_CR1_ENGC_Msk                   /*!< General Call Enable */
10630 #define I2C_CR1_NOSTRETCH_Pos               (7U)
10631 #define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)    /*!< 0x00000080 */
10632 #define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk              /*!< Clock Stretching Disable (Slave mode) */
10633 #define I2C_CR1_START_Pos                   (8U)
10634 #define I2C_CR1_START_Msk                   (0x1UL << I2C_CR1_START_Pos)        /*!< 0x00000100 */
10635 #define I2C_CR1_START                       I2C_CR1_START_Msk                  /*!< Start Generation */
10636 #define I2C_CR1_STOP_Pos                    (9U)
10637 #define I2C_CR1_STOP_Msk                    (0x1UL << I2C_CR1_STOP_Pos)         /*!< 0x00000200 */
10638 #define I2C_CR1_STOP                        I2C_CR1_STOP_Msk                   /*!< Stop Generation */
10639 #define I2C_CR1_ACK_Pos                     (10U)
10640 #define I2C_CR1_ACK_Msk                     (0x1UL << I2C_CR1_ACK_Pos)          /*!< 0x00000400 */
10641 #define I2C_CR1_ACK                         I2C_CR1_ACK_Msk                    /*!< Acknowledge Enable */
10642 #define I2C_CR1_POS_Pos                     (11U)
10643 #define I2C_CR1_POS_Msk                     (0x1UL << I2C_CR1_POS_Pos)          /*!< 0x00000800 */
10644 #define I2C_CR1_POS                         I2C_CR1_POS_Msk                    /*!< Acknowledge/PEC Position (for data reception) */
10645 #define I2C_CR1_PEC_Pos                     (12U)
10646 #define I2C_CR1_PEC_Msk                     (0x1UL << I2C_CR1_PEC_Pos)          /*!< 0x00001000 */
10647 #define I2C_CR1_PEC                         I2C_CR1_PEC_Msk                    /*!< Packet Error Checking */
10648 #define I2C_CR1_ALERT_Pos                   (13U)
10649 #define I2C_CR1_ALERT_Msk                   (0x1UL << I2C_CR1_ALERT_Pos)        /*!< 0x00002000 */
10650 #define I2C_CR1_ALERT                       I2C_CR1_ALERT_Msk                  /*!< SMBus Alert */
10651 #define I2C_CR1_SWRST_Pos                   (15U)
10652 #define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)        /*!< 0x00008000 */
10653 #define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                  /*!< Software Reset */
10654 
10655 /*******************  Bit definition for I2C_CR2 register  ********************/
10656 #define I2C_CR2_FREQ_Pos                    (0U)
10657 #define I2C_CR2_FREQ_Msk                    (0x3FUL << I2C_CR2_FREQ_Pos)        /*!< 0x0000003F */
10658 #define I2C_CR2_FREQ                        I2C_CR2_FREQ_Msk                   /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
10659 #define I2C_CR2_FREQ_0                      (0x01UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000001 */
10660 #define I2C_CR2_FREQ_1                      (0x02UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000002 */
10661 #define I2C_CR2_FREQ_2                      (0x04UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000004 */
10662 #define I2C_CR2_FREQ_3                      (0x08UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000008 */
10663 #define I2C_CR2_FREQ_4                      (0x10UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000010 */
10664 #define I2C_CR2_FREQ_5                      (0x20UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000020 */
10665 
10666 #define I2C_CR2_ITERREN_Pos                 (8U)
10667 #define I2C_CR2_ITERREN_Msk                 (0x1UL << I2C_CR2_ITERREN_Pos)      /*!< 0x00000100 */
10668 #define I2C_CR2_ITERREN                     I2C_CR2_ITERREN_Msk                /*!< Error Interrupt Enable */
10669 #define I2C_CR2_ITEVTEN_Pos                 (9U)
10670 #define I2C_CR2_ITEVTEN_Msk                 (0x1UL << I2C_CR2_ITEVTEN_Pos)      /*!< 0x00000200 */
10671 #define I2C_CR2_ITEVTEN                     I2C_CR2_ITEVTEN_Msk                /*!< Event Interrupt Enable */
10672 #define I2C_CR2_ITBUFEN_Pos                 (10U)
10673 #define I2C_CR2_ITBUFEN_Msk                 (0x1UL << I2C_CR2_ITBUFEN_Pos)      /*!< 0x00000400 */
10674 #define I2C_CR2_ITBUFEN                     I2C_CR2_ITBUFEN_Msk                /*!< Buffer Interrupt Enable */
10675 #define I2C_CR2_DMAEN_Pos                   (11U)
10676 #define I2C_CR2_DMAEN_Msk                   (0x1UL << I2C_CR2_DMAEN_Pos)        /*!< 0x00000800 */
10677 #define I2C_CR2_DMAEN                       I2C_CR2_DMAEN_Msk                  /*!< DMA Requests Enable */
10678 #define I2C_CR2_LAST_Pos                    (12U)
10679 #define I2C_CR2_LAST_Msk                    (0x1UL << I2C_CR2_LAST_Pos)         /*!< 0x00001000 */
10680 #define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */
10681 
10682 /*******************  Bit definition for I2C_OAR1 register  *******************/
10683 #define I2C_OAR1_ADD1_7                     0x000000FEU             /*!< Interface Address */
10684 #define I2C_OAR1_ADD8_9                     0x00000300U             /*!< Interface Address */
10685 
10686 #define I2C_OAR1_ADD0_Pos                   (0U)
10687 #define I2C_OAR1_ADD0_Msk                   (0x1UL << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */
10688 #define I2C_OAR1_ADD0                       I2C_OAR1_ADD0_Msk                  /*!< Bit 0 */
10689 #define I2C_OAR1_ADD1_Pos                   (1U)
10690 #define I2C_OAR1_ADD1_Msk                   (0x1UL << I2C_OAR1_ADD1_Pos)        /*!< 0x00000002 */
10691 #define I2C_OAR1_ADD1                       I2C_OAR1_ADD1_Msk                  /*!< Bit 1 */
10692 #define I2C_OAR1_ADD2_Pos                   (2U)
10693 #define I2C_OAR1_ADD2_Msk                   (0x1UL << I2C_OAR1_ADD2_Pos)        /*!< 0x00000004 */
10694 #define I2C_OAR1_ADD2                       I2C_OAR1_ADD2_Msk                  /*!< Bit 2 */
10695 #define I2C_OAR1_ADD3_Pos                   (3U)
10696 #define I2C_OAR1_ADD3_Msk                   (0x1UL << I2C_OAR1_ADD3_Pos)        /*!< 0x00000008 */
10697 #define I2C_OAR1_ADD3                       I2C_OAR1_ADD3_Msk                  /*!< Bit 3 */
10698 #define I2C_OAR1_ADD4_Pos                   (4U)
10699 #define I2C_OAR1_ADD4_Msk                   (0x1UL << I2C_OAR1_ADD4_Pos)        /*!< 0x00000010 */
10700 #define I2C_OAR1_ADD4                       I2C_OAR1_ADD4_Msk                  /*!< Bit 4 */
10701 #define I2C_OAR1_ADD5_Pos                   (5U)
10702 #define I2C_OAR1_ADD5_Msk                   (0x1UL << I2C_OAR1_ADD5_Pos)        /*!< 0x00000020 */
10703 #define I2C_OAR1_ADD5                       I2C_OAR1_ADD5_Msk                  /*!< Bit 5 */
10704 #define I2C_OAR1_ADD6_Pos                   (6U)
10705 #define I2C_OAR1_ADD6_Msk                   (0x1UL << I2C_OAR1_ADD6_Pos)        /*!< 0x00000040 */
10706 #define I2C_OAR1_ADD6                       I2C_OAR1_ADD6_Msk                  /*!< Bit 6 */
10707 #define I2C_OAR1_ADD7_Pos                   (7U)
10708 #define I2C_OAR1_ADD7_Msk                   (0x1UL << I2C_OAR1_ADD7_Pos)        /*!< 0x00000080 */
10709 #define I2C_OAR1_ADD7                       I2C_OAR1_ADD7_Msk                  /*!< Bit 7 */
10710 #define I2C_OAR1_ADD8_Pos                   (8U)
10711 #define I2C_OAR1_ADD8_Msk                   (0x1UL << I2C_OAR1_ADD8_Pos)        /*!< 0x00000100 */
10712 #define I2C_OAR1_ADD8                       I2C_OAR1_ADD8_Msk                  /*!< Bit 8 */
10713 #define I2C_OAR1_ADD9_Pos                   (9U)
10714 #define I2C_OAR1_ADD9_Msk                   (0x1UL << I2C_OAR1_ADD9_Pos)        /*!< 0x00000200 */
10715 #define I2C_OAR1_ADD9                       I2C_OAR1_ADD9_Msk                  /*!< Bit 9 */
10716 
10717 #define I2C_OAR1_ADDMODE_Pos                (15U)
10718 #define I2C_OAR1_ADDMODE_Msk                (0x1UL << I2C_OAR1_ADDMODE_Pos)     /*!< 0x00008000 */
10719 #define I2C_OAR1_ADDMODE                    I2C_OAR1_ADDMODE_Msk               /*!< Addressing Mode (Slave mode) */
10720 
10721 /*******************  Bit definition for I2C_OAR2 register  *******************/
10722 #define I2C_OAR2_ENDUAL_Pos                 (0U)
10723 #define I2C_OAR2_ENDUAL_Msk                 (0x1UL << I2C_OAR2_ENDUAL_Pos)      /*!< 0x00000001 */
10724 #define I2C_OAR2_ENDUAL                     I2C_OAR2_ENDUAL_Msk                /*!< Dual addressing mode enable */
10725 #define I2C_OAR2_ADD2_Pos                   (1U)
10726 #define I2C_OAR2_ADD2_Msk                   (0x7FUL << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */
10727 #define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */
10728 
10729 /********************  Bit definition for I2C_DR register  ********************/
10730 #define I2C_DR_DR_Pos             (0U)
10731 #define I2C_DR_DR_Msk             (0xFFUL << I2C_DR_DR_Pos)                     /*!< 0x000000FF */
10732 #define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!< 8-bit Data Register         */
10733 
10734 /*******************  Bit definition for I2C_SR1 register  ********************/
10735 #define I2C_SR1_SB_Pos                      (0U)
10736 #define I2C_SR1_SB_Msk                      (0x1UL << I2C_SR1_SB_Pos)           /*!< 0x00000001 */
10737 #define I2C_SR1_SB                          I2C_SR1_SB_Msk                     /*!< Start Bit (Master mode) */
10738 #define I2C_SR1_ADDR_Pos                    (1U)
10739 #define I2C_SR1_ADDR_Msk                    (0x1UL << I2C_SR1_ADDR_Pos)         /*!< 0x00000002 */
10740 #define I2C_SR1_ADDR                        I2C_SR1_ADDR_Msk                   /*!< Address sent (master mode)/matched (slave mode) */
10741 #define I2C_SR1_BTF_Pos                     (2U)
10742 #define I2C_SR1_BTF_Msk                     (0x1UL << I2C_SR1_BTF_Pos)          /*!< 0x00000004 */
10743 #define I2C_SR1_BTF                         I2C_SR1_BTF_Msk                    /*!< Byte Transfer Finished */
10744 #define I2C_SR1_ADD10_Pos                   (3U)
10745 #define I2C_SR1_ADD10_Msk                   (0x1UL << I2C_SR1_ADD10_Pos)        /*!< 0x00000008 */
10746 #define I2C_SR1_ADD10                       I2C_SR1_ADD10_Msk                  /*!< 10-bit header sent (Master mode) */
10747 #define I2C_SR1_STOPF_Pos                   (4U)
10748 #define I2C_SR1_STOPF_Msk                   (0x1UL << I2C_SR1_STOPF_Pos)        /*!< 0x00000010 */
10749 #define I2C_SR1_STOPF                       I2C_SR1_STOPF_Msk                  /*!< Stop detection (Slave mode) */
10750 #define I2C_SR1_RXNE_Pos                    (6U)
10751 #define I2C_SR1_RXNE_Msk                    (0x1UL << I2C_SR1_RXNE_Pos)         /*!< 0x00000040 */
10752 #define I2C_SR1_RXNE                        I2C_SR1_RXNE_Msk                   /*!< Data Register not Empty (receivers) */
10753 #define I2C_SR1_TXE_Pos                     (7U)
10754 #define I2C_SR1_TXE_Msk                     (0x1UL << I2C_SR1_TXE_Pos)          /*!< 0x00000080 */
10755 #define I2C_SR1_TXE                         I2C_SR1_TXE_Msk                    /*!< Data Register Empty (transmitters) */
10756 #define I2C_SR1_BERR_Pos                    (8U)
10757 #define I2C_SR1_BERR_Msk                    (0x1UL << I2C_SR1_BERR_Pos)         /*!< 0x00000100 */
10758 #define I2C_SR1_BERR                        I2C_SR1_BERR_Msk                   /*!< Bus Error */
10759 #define I2C_SR1_ARLO_Pos                    (9U)
10760 #define I2C_SR1_ARLO_Msk                    (0x1UL << I2C_SR1_ARLO_Pos)         /*!< 0x00000200 */
10761 #define I2C_SR1_ARLO                        I2C_SR1_ARLO_Msk                   /*!< Arbitration Lost (master mode) */
10762 #define I2C_SR1_AF_Pos                      (10U)
10763 #define I2C_SR1_AF_Msk                      (0x1UL << I2C_SR1_AF_Pos)           /*!< 0x00000400 */
10764 #define I2C_SR1_AF                          I2C_SR1_AF_Msk                     /*!< Acknowledge Failure */
10765 #define I2C_SR1_OVR_Pos                     (11U)
10766 #define I2C_SR1_OVR_Msk                     (0x1UL << I2C_SR1_OVR_Pos)          /*!< 0x00000800 */
10767 #define I2C_SR1_OVR                         I2C_SR1_OVR_Msk                    /*!< Overrun/Underrun */
10768 #define I2C_SR1_PECERR_Pos                  (12U)
10769 #define I2C_SR1_PECERR_Msk                  (0x1UL << I2C_SR1_PECERR_Pos)       /*!< 0x00001000 */
10770 #define I2C_SR1_PECERR                      I2C_SR1_PECERR_Msk                 /*!< PEC Error in reception */
10771 #define I2C_SR1_TIMEOUT_Pos                 (14U)
10772 #define I2C_SR1_TIMEOUT_Msk                 (0x1UL << I2C_SR1_TIMEOUT_Pos)      /*!< 0x00004000 */
10773 #define I2C_SR1_TIMEOUT                     I2C_SR1_TIMEOUT_Msk                /*!< Timeout or Tlow Error */
10774 #define I2C_SR1_SMBALERT_Pos                (15U)
10775 #define I2C_SR1_SMBALERT_Msk                (0x1UL << I2C_SR1_SMBALERT_Pos)     /*!< 0x00008000 */
10776 #define I2C_SR1_SMBALERT                    I2C_SR1_SMBALERT_Msk               /*!< SMBus Alert */
10777 
10778 /*******************  Bit definition for I2C_SR2 register  ********************/
10779 #define I2C_SR2_MSL_Pos                     (0U)
10780 #define I2C_SR2_MSL_Msk                     (0x1UL << I2C_SR2_MSL_Pos)          /*!< 0x00000001 */
10781 #define I2C_SR2_MSL                         I2C_SR2_MSL_Msk                    /*!< Master/Slave */
10782 #define I2C_SR2_BUSY_Pos                    (1U)
10783 #define I2C_SR2_BUSY_Msk                    (0x1UL << I2C_SR2_BUSY_Pos)         /*!< 0x00000002 */
10784 #define I2C_SR2_BUSY                        I2C_SR2_BUSY_Msk                   /*!< Bus Busy */
10785 #define I2C_SR2_TRA_Pos                     (2U)
10786 #define I2C_SR2_TRA_Msk                     (0x1UL << I2C_SR2_TRA_Pos)          /*!< 0x00000004 */
10787 #define I2C_SR2_TRA                         I2C_SR2_TRA_Msk                    /*!< Transmitter/Receiver */
10788 #define I2C_SR2_GENCALL_Pos                 (4U)
10789 #define I2C_SR2_GENCALL_Msk                 (0x1UL << I2C_SR2_GENCALL_Pos)      /*!< 0x00000010 */
10790 #define I2C_SR2_GENCALL                     I2C_SR2_GENCALL_Msk                /*!< General Call Address (Slave mode) */
10791 #define I2C_SR2_SMBDEFAULT_Pos              (5U)
10792 #define I2C_SR2_SMBDEFAULT_Msk              (0x1UL << I2C_SR2_SMBDEFAULT_Pos)   /*!< 0x00000020 */
10793 #define I2C_SR2_SMBDEFAULT                  I2C_SR2_SMBDEFAULT_Msk             /*!< SMBus Device Default Address (Slave mode) */
10794 #define I2C_SR2_SMBHOST_Pos                 (6U)
10795 #define I2C_SR2_SMBHOST_Msk                 (0x1UL << I2C_SR2_SMBHOST_Pos)      /*!< 0x00000040 */
10796 #define I2C_SR2_SMBHOST                     I2C_SR2_SMBHOST_Msk                /*!< SMBus Host Header (Slave mode) */
10797 #define I2C_SR2_DUALF_Pos                   (7U)
10798 #define I2C_SR2_DUALF_Msk                   (0x1UL << I2C_SR2_DUALF_Pos)        /*!< 0x00000080 */
10799 #define I2C_SR2_DUALF                       I2C_SR2_DUALF_Msk                  /*!< Dual Flag (Slave mode) */
10800 #define I2C_SR2_PEC_Pos                     (8U)
10801 #define I2C_SR2_PEC_Msk                     (0xFFUL << I2C_SR2_PEC_Pos)         /*!< 0x0000FF00 */
10802 #define I2C_SR2_PEC                         I2C_SR2_PEC_Msk                    /*!< Packet Error Checking Register */
10803 
10804 /*******************  Bit definition for I2C_CCR register  ********************/
10805 #define I2C_CCR_CCR_Pos                     (0U)
10806 #define I2C_CCR_CCR_Msk                     (0xFFFUL << I2C_CCR_CCR_Pos)        /*!< 0x00000FFF */
10807 #define I2C_CCR_CCR                         I2C_CCR_CCR_Msk                    /*!< Clock Control Register in Fast/Standard mode (Master mode) */
10808 #define I2C_CCR_DUTY_Pos                    (14U)
10809 #define I2C_CCR_DUTY_Msk                    (0x1UL << I2C_CCR_DUTY_Pos)         /*!< 0x00004000 */
10810 #define I2C_CCR_DUTY                        I2C_CCR_DUTY_Msk                   /*!< Fast Mode Duty Cycle */
10811 #define I2C_CCR_FS_Pos                      (15U)
10812 #define I2C_CCR_FS_Msk                      (0x1UL << I2C_CCR_FS_Pos)           /*!< 0x00008000 */
10813 #define I2C_CCR_FS                          I2C_CCR_FS_Msk                     /*!< I2C Master Mode Selection */
10814 
10815 /******************  Bit definition for I2C_TRISE register  *******************/
10816 #define I2C_TRISE_TRISE_Pos                 (0U)
10817 #define I2C_TRISE_TRISE_Msk                 (0x3FUL << I2C_TRISE_TRISE_Pos)     /*!< 0x0000003F */
10818 #define I2C_TRISE_TRISE                     I2C_TRISE_TRISE_Msk                /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
10819 
10820 /******************************************************************************/
10821 /*                                                                            */
10822 /*         Universal Synchronous Asynchronous Receiver Transmitter            */
10823 /*                                                                            */
10824 /******************************************************************************/
10825 
10826 /*******************  Bit definition for USART_SR register  *******************/
10827 #define USART_SR_PE_Pos                     (0U)
10828 #define USART_SR_PE_Msk                     (0x1UL << USART_SR_PE_Pos)          /*!< 0x00000001 */
10829 #define USART_SR_PE                         USART_SR_PE_Msk                    /*!< Parity Error */
10830 #define USART_SR_FE_Pos                     (1U)
10831 #define USART_SR_FE_Msk                     (0x1UL << USART_SR_FE_Pos)          /*!< 0x00000002 */
10832 #define USART_SR_FE                         USART_SR_FE_Msk                    /*!< Framing Error */
10833 #define USART_SR_NE_Pos                     (2U)
10834 #define USART_SR_NE_Msk                     (0x1UL << USART_SR_NE_Pos)          /*!< 0x00000004 */
10835 #define USART_SR_NE                         USART_SR_NE_Msk                    /*!< Noise Error Flag */
10836 #define USART_SR_ORE_Pos                    (3U)
10837 #define USART_SR_ORE_Msk                    (0x1UL << USART_SR_ORE_Pos)         /*!< 0x00000008 */
10838 #define USART_SR_ORE                        USART_SR_ORE_Msk                   /*!< OverRun Error */
10839 #define USART_SR_IDLE_Pos                   (4U)
10840 #define USART_SR_IDLE_Msk                   (0x1UL << USART_SR_IDLE_Pos)        /*!< 0x00000010 */
10841 #define USART_SR_IDLE                       USART_SR_IDLE_Msk                  /*!< IDLE line detected */
10842 #define USART_SR_RXNE_Pos                   (5U)
10843 #define USART_SR_RXNE_Msk                   (0x1UL << USART_SR_RXNE_Pos)        /*!< 0x00000020 */
10844 #define USART_SR_RXNE                       USART_SR_RXNE_Msk                  /*!< Read Data Register Not Empty */
10845 #define USART_SR_TC_Pos                     (6U)
10846 #define USART_SR_TC_Msk                     (0x1UL << USART_SR_TC_Pos)          /*!< 0x00000040 */
10847 #define USART_SR_TC                         USART_SR_TC_Msk                    /*!< Transmission Complete */
10848 #define USART_SR_TXE_Pos                    (7U)
10849 #define USART_SR_TXE_Msk                    (0x1UL << USART_SR_TXE_Pos)         /*!< 0x00000080 */
10850 #define USART_SR_TXE                        USART_SR_TXE_Msk                   /*!< Transmit Data Register Empty */
10851 #define USART_SR_LBD_Pos                    (8U)
10852 #define USART_SR_LBD_Msk                    (0x1UL << USART_SR_LBD_Pos)         /*!< 0x00000100 */
10853 #define USART_SR_LBD                        USART_SR_LBD_Msk                   /*!< LIN Break Detection Flag */
10854 #define USART_SR_CTS_Pos                    (9U)
10855 #define USART_SR_CTS_Msk                    (0x1UL << USART_SR_CTS_Pos)         /*!< 0x00000200 */
10856 #define USART_SR_CTS                        USART_SR_CTS_Msk                   /*!< CTS Flag */
10857 
10858 /*******************  Bit definition for USART_DR register  *******************/
10859 #define USART_DR_DR_Pos                     (0U)
10860 #define USART_DR_DR_Msk                     (0x1FFUL << USART_DR_DR_Pos)        /*!< 0x000001FF */
10861 #define USART_DR_DR                         USART_DR_DR_Msk                    /*!< Data value */
10862 
10863 /******************  Bit definition for USART_BRR register  *******************/
10864 #define USART_BRR_DIV_Fraction_Pos          (0U)
10865 #define USART_BRR_DIV_Fraction_Msk          (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
10866 #define USART_BRR_DIV_Fraction              USART_BRR_DIV_Fraction_Msk         /*!< Fraction of USARTDIV */
10867 #define USART_BRR_DIV_Mantissa_Pos          (4U)
10868 #define USART_BRR_DIV_Mantissa_Msk          (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
10869 #define USART_BRR_DIV_Mantissa              USART_BRR_DIV_Mantissa_Msk         /*!< Mantissa of USARTDIV */
10870 
10871 /******************  Bit definition for USART_CR1 register  *******************/
10872 #define USART_CR1_SBK_Pos                   (0U)
10873 #define USART_CR1_SBK_Msk                   (0x1UL << USART_CR1_SBK_Pos)        /*!< 0x00000001 */
10874 #define USART_CR1_SBK                       USART_CR1_SBK_Msk                  /*!< Send Break */
10875 #define USART_CR1_RWU_Pos                   (1U)
10876 #define USART_CR1_RWU_Msk                   (0x1UL << USART_CR1_RWU_Pos)        /*!< 0x00000002 */
10877 #define USART_CR1_RWU                       USART_CR1_RWU_Msk                  /*!< Receiver wakeup */
10878 #define USART_CR1_RE_Pos                    (2U)
10879 #define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)         /*!< 0x00000004 */
10880 #define USART_CR1_RE                        USART_CR1_RE_Msk                   /*!< Receiver Enable */
10881 #define USART_CR1_TE_Pos                    (3U)
10882 #define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)         /*!< 0x00000008 */
10883 #define USART_CR1_TE                        USART_CR1_TE_Msk                   /*!< Transmitter Enable */
10884 #define USART_CR1_IDLEIE_Pos                (4U)
10885 #define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)     /*!< 0x00000010 */
10886 #define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk               /*!< IDLE Interrupt Enable */
10887 #define USART_CR1_RXNEIE_Pos                (5U)
10888 #define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)     /*!< 0x00000020 */
10889 #define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk               /*!< RXNE Interrupt Enable */
10890 #define USART_CR1_TCIE_Pos                  (6U)
10891 #define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)       /*!< 0x00000040 */
10892 #define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                 /*!< Transmission Complete Interrupt Enable */
10893 #define USART_CR1_TXEIE_Pos                 (7U)
10894 #define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)      /*!< 0x00000080 */
10895 #define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                /*!< PE Interrupt Enable */
10896 #define USART_CR1_PEIE_Pos                  (8U)
10897 #define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)       /*!< 0x00000100 */
10898 #define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                 /*!< PE Interrupt Enable */
10899 #define USART_CR1_PS_Pos                    (9U)
10900 #define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)         /*!< 0x00000200 */
10901 #define USART_CR1_PS                        USART_CR1_PS_Msk                   /*!< Parity Selection */
10902 #define USART_CR1_PCE_Pos                   (10U)
10903 #define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)        /*!< 0x00000400 */
10904 #define USART_CR1_PCE                       USART_CR1_PCE_Msk                  /*!< Parity Control Enable */
10905 #define USART_CR1_WAKE_Pos                  (11U)
10906 #define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)       /*!< 0x00000800 */
10907 #define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                 /*!< Wakeup method */
10908 #define USART_CR1_M_Pos                     (12U)
10909 #define USART_CR1_M_Msk                     (0x1UL << USART_CR1_M_Pos)          /*!< 0x00001000 */
10910 #define USART_CR1_M                         USART_CR1_M_Msk                    /*!< Word length */
10911 #define USART_CR1_UE_Pos                    (13U)
10912 #define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)         /*!< 0x00002000 */
10913 #define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */
10914 
10915 /******************  Bit definition for USART_CR2 register  *******************/
10916 #define USART_CR2_ADD_Pos                   (0U)
10917 #define USART_CR2_ADD_Msk                   (0xFUL << USART_CR2_ADD_Pos)        /*!< 0x0000000F */
10918 #define USART_CR2_ADD                       USART_CR2_ADD_Msk                  /*!< Address of the USART node */
10919 #define USART_CR2_LBDL_Pos                  (5U)
10920 #define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)       /*!< 0x00000020 */
10921 #define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                 /*!< LIN Break Detection Length */
10922 #define USART_CR2_LBDIE_Pos                 (6U)
10923 #define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)      /*!< 0x00000040 */
10924 #define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                /*!< LIN Break Detection Interrupt Enable */
10925 #define USART_CR2_LBCL_Pos                  (8U)
10926 #define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)       /*!< 0x00000100 */
10927 #define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                 /*!< Last Bit Clock pulse */
10928 #define USART_CR2_CPHA_Pos                  (9U)
10929 #define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)       /*!< 0x00000200 */
10930 #define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                 /*!< Clock Phase */
10931 #define USART_CR2_CPOL_Pos                  (10U)
10932 #define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)       /*!< 0x00000400 */
10933 #define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                 /*!< Clock Polarity */
10934 #define USART_CR2_CLKEN_Pos                 (11U)
10935 #define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)      /*!< 0x00000800 */
10936 #define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                /*!< Clock Enable */
10937 
10938 #define USART_CR2_STOP_Pos                  (12U)
10939 #define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)       /*!< 0x00003000 */
10940 #define USART_CR2_STOP                      USART_CR2_STOP_Msk                 /*!< STOP[1:0] bits (STOP bits) */
10941 #define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)       /*!< 0x00001000 */
10942 #define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)       /*!< 0x00002000 */
10943 
10944 #define USART_CR2_LINEN_Pos                 (14U)
10945 #define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)      /*!< 0x00004000 */
10946 #define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                /*!< LIN mode enable */
10947 
10948 /******************  Bit definition for USART_CR3 register  *******************/
10949 #define USART_CR3_EIE_Pos                   (0U)
10950 #define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)        /*!< 0x00000001 */
10951 #define USART_CR3_EIE                       USART_CR3_EIE_Msk                  /*!< Error Interrupt Enable */
10952 #define USART_CR3_IREN_Pos                  (1U)
10953 #define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)       /*!< 0x00000002 */
10954 #define USART_CR3_IREN                      USART_CR3_IREN_Msk                 /*!< IrDA mode Enable */
10955 #define USART_CR3_IRLP_Pos                  (2U)
10956 #define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)       /*!< 0x00000004 */
10957 #define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                 /*!< IrDA Low-Power */
10958 #define USART_CR3_HDSEL_Pos                 (3U)
10959 #define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)      /*!< 0x00000008 */
10960 #define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                /*!< Half-Duplex Selection */
10961 #define USART_CR3_NACK_Pos                  (4U)
10962 #define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)       /*!< 0x00000010 */
10963 #define USART_CR3_NACK                      USART_CR3_NACK_Msk                 /*!< Smartcard NACK enable */
10964 #define USART_CR3_SCEN_Pos                  (5U)
10965 #define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)       /*!< 0x00000020 */
10966 #define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                 /*!< Smartcard mode enable */
10967 #define USART_CR3_DMAR_Pos                  (6U)
10968 #define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)       /*!< 0x00000040 */
10969 #define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                 /*!< DMA Enable Receiver */
10970 #define USART_CR3_DMAT_Pos                  (7U)
10971 #define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)       /*!< 0x00000080 */
10972 #define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                 /*!< DMA Enable Transmitter */
10973 #define USART_CR3_RTSE_Pos                  (8U)
10974 #define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)       /*!< 0x00000100 */
10975 #define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                 /*!< RTS Enable */
10976 #define USART_CR3_CTSE_Pos                  (9U)
10977 #define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)       /*!< 0x00000200 */
10978 #define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                 /*!< CTS Enable */
10979 #define USART_CR3_CTSIE_Pos                 (10U)
10980 #define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */
10981 #define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */
10982 
10983 /******************  Bit definition for USART_GTPR register  ******************/
10984 #define USART_GTPR_PSC_Pos                  (0U)
10985 #define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)      /*!< 0x000000FF */
10986 #define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                 /*!< PSC[7:0] bits (Prescaler value) */
10987 #define USART_GTPR_PSC_0                    (0x01UL << USART_GTPR_PSC_Pos)      /*!< 0x00000001 */
10988 #define USART_GTPR_PSC_1                    (0x02UL << USART_GTPR_PSC_Pos)      /*!< 0x00000002 */
10989 #define USART_GTPR_PSC_2                    (0x04UL << USART_GTPR_PSC_Pos)      /*!< 0x00000004 */
10990 #define USART_GTPR_PSC_3                    (0x08UL << USART_GTPR_PSC_Pos)      /*!< 0x00000008 */
10991 #define USART_GTPR_PSC_4                    (0x10UL << USART_GTPR_PSC_Pos)      /*!< 0x00000010 */
10992 #define USART_GTPR_PSC_5                    (0x20UL << USART_GTPR_PSC_Pos)      /*!< 0x00000020 */
10993 #define USART_GTPR_PSC_6                    (0x40UL << USART_GTPR_PSC_Pos)      /*!< 0x00000040 */
10994 #define USART_GTPR_PSC_7                    (0x80UL << USART_GTPR_PSC_Pos)      /*!< 0x00000080 */
10995 
10996 #define USART_GTPR_GT_Pos                   (8U)
10997 #define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)       /*!< 0x0000FF00 */
10998 #define USART_GTPR_GT                       USART_GTPR_GT_Msk                  /*!< Guard time value */
10999 
11000 /******************************************************************************/
11001 /*                                                                            */
11002 /*                                 Debug MCU                                  */
11003 /*                                                                            */
11004 /******************************************************************************/
11005 
11006 /****************  Bit definition for DBGMCU_IDCODE register  *****************/
11007 #define DBGMCU_IDCODE_DEV_ID_Pos            (0U)
11008 #define DBGMCU_IDCODE_DEV_ID_Msk            (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
11009 #define DBGMCU_IDCODE_DEV_ID                DBGMCU_IDCODE_DEV_ID_Msk           /*!< Device Identifier */
11010 
11011 #define DBGMCU_IDCODE_REV_ID_Pos            (16U)
11012 #define DBGMCU_IDCODE_REV_ID_Msk            (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
11013 #define DBGMCU_IDCODE_REV_ID                DBGMCU_IDCODE_REV_ID_Msk           /*!< REV_ID[15:0] bits (Revision Identifier) */
11014 #define DBGMCU_IDCODE_REV_ID_0              (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
11015 #define DBGMCU_IDCODE_REV_ID_1              (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
11016 #define DBGMCU_IDCODE_REV_ID_2              (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
11017 #define DBGMCU_IDCODE_REV_ID_3              (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
11018 #define DBGMCU_IDCODE_REV_ID_4              (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
11019 #define DBGMCU_IDCODE_REV_ID_5              (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
11020 #define DBGMCU_IDCODE_REV_ID_6              (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
11021 #define DBGMCU_IDCODE_REV_ID_7              (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
11022 #define DBGMCU_IDCODE_REV_ID_8              (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
11023 #define DBGMCU_IDCODE_REV_ID_9              (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
11024 #define DBGMCU_IDCODE_REV_ID_10             (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
11025 #define DBGMCU_IDCODE_REV_ID_11             (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
11026 #define DBGMCU_IDCODE_REV_ID_12             (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
11027 #define DBGMCU_IDCODE_REV_ID_13             (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
11028 #define DBGMCU_IDCODE_REV_ID_14             (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
11029 #define DBGMCU_IDCODE_REV_ID_15             (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
11030 
11031 /******************  Bit definition for DBGMCU_CR register  *******************/
11032 #define DBGMCU_CR_DBG_SLEEP_Pos             (0U)
11033 #define DBGMCU_CR_DBG_SLEEP_Msk             (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)  /*!< 0x00000001 */
11034 #define DBGMCU_CR_DBG_SLEEP                 DBGMCU_CR_DBG_SLEEP_Msk            /*!< Debug Sleep Mode */
11035 #define DBGMCU_CR_DBG_STOP_Pos              (1U)
11036 #define DBGMCU_CR_DBG_STOP_Msk              (0x1UL << DBGMCU_CR_DBG_STOP_Pos)   /*!< 0x00000002 */
11037 #define DBGMCU_CR_DBG_STOP                  DBGMCU_CR_DBG_STOP_Msk             /*!< Debug Stop Mode */
11038 #define DBGMCU_CR_DBG_STANDBY_Pos           (2U)
11039 #define DBGMCU_CR_DBG_STANDBY_Msk           (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
11040 #define DBGMCU_CR_DBG_STANDBY               DBGMCU_CR_DBG_STANDBY_Msk          /*!< Debug Standby mode */
11041 #define DBGMCU_CR_TRACE_IOEN_Pos            (5U)
11042 #define DBGMCU_CR_TRACE_IOEN_Msk            (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
11043 #define DBGMCU_CR_TRACE_IOEN                DBGMCU_CR_TRACE_IOEN_Msk           /*!< Trace Pin Assignment Control */
11044 
11045 #define DBGMCU_CR_TRACE_MODE_Pos            (6U)
11046 #define DBGMCU_CR_TRACE_MODE_Msk            (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
11047 #define DBGMCU_CR_TRACE_MODE                DBGMCU_CR_TRACE_MODE_Msk           /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
11048 #define DBGMCU_CR_TRACE_MODE_0              (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
11049 #define DBGMCU_CR_TRACE_MODE_1              (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
11050 
11051 #define DBGMCU_CR_DBG_IWDG_STOP_Pos         (8U)
11052 #define DBGMCU_CR_DBG_IWDG_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */
11053 #define DBGMCU_CR_DBG_IWDG_STOP             DBGMCU_CR_DBG_IWDG_STOP_Msk        /*!< Debug Independent Watchdog stopped when Core is halted */
11054 #define DBGMCU_CR_DBG_WWDG_STOP_Pos         (9U)
11055 #define DBGMCU_CR_DBG_WWDG_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */
11056 #define DBGMCU_CR_DBG_WWDG_STOP             DBGMCU_CR_DBG_WWDG_STOP_Msk        /*!< Debug Window Watchdog stopped when Core is halted */
11057 #define DBGMCU_CR_DBG_TIM1_STOP_Pos         (10U)
11058 #define DBGMCU_CR_DBG_TIM1_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_TIM1_STOP_Pos) /*!< 0x00000400 */
11059 #define DBGMCU_CR_DBG_TIM1_STOP             DBGMCU_CR_DBG_TIM1_STOP_Msk        /*!< TIM1 counter stopped when core is halted */
11060 #define DBGMCU_CR_DBG_TIM2_STOP_Pos         (11U)
11061 #define DBGMCU_CR_DBG_TIM2_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */
11062 #define DBGMCU_CR_DBG_TIM2_STOP             DBGMCU_CR_DBG_TIM2_STOP_Msk        /*!< TIM2 counter stopped when core is halted */
11063 #define DBGMCU_CR_DBG_TIM3_STOP_Pos         (12U)
11064 #define DBGMCU_CR_DBG_TIM3_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */
11065 #define DBGMCU_CR_DBG_TIM3_STOP             DBGMCU_CR_DBG_TIM3_STOP_Msk        /*!< TIM3 counter stopped when core is halted */
11066 #define DBGMCU_CR_DBG_TIM4_STOP_Pos         (13U)
11067 #define DBGMCU_CR_DBG_TIM4_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */
11068 #define DBGMCU_CR_DBG_TIM4_STOP             DBGMCU_CR_DBG_TIM4_STOP_Msk        /*!< TIM4 counter stopped when core is halted */
11069 #define DBGMCU_CR_DBG_CAN1_STOP_Pos         (14U)
11070 #define DBGMCU_CR_DBG_CAN1_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_CAN1_STOP_Pos) /*!< 0x00004000 */
11071 #define DBGMCU_CR_DBG_CAN1_STOP             DBGMCU_CR_DBG_CAN1_STOP_Msk        /*!< Debug CAN1 stopped when Core is halted */
11072 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
11073 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */
11074 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT    DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
11075 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)
11076 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */
11077 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT    DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
11078 #define DBGMCU_CR_DBG_TIM8_STOP_Pos         (17U)
11079 #define DBGMCU_CR_DBG_TIM8_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_TIM8_STOP_Pos) /*!< 0x00020000 */
11080 #define DBGMCU_CR_DBG_TIM8_STOP             DBGMCU_CR_DBG_TIM8_STOP_Msk        /*!< TIM8 counter stopped when core is halted */
11081 #define DBGMCU_CR_DBG_TIM5_STOP_Pos         (18U)
11082 #define DBGMCU_CR_DBG_TIM5_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_TIM5_STOP_Pos) /*!< 0x00040000 */
11083 #define DBGMCU_CR_DBG_TIM5_STOP             DBGMCU_CR_DBG_TIM5_STOP_Msk        /*!< TIM5 counter stopped when core is halted */
11084 #define DBGMCU_CR_DBG_TIM6_STOP_Pos         (19U)
11085 #define DBGMCU_CR_DBG_TIM6_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_TIM6_STOP_Pos) /*!< 0x00080000 */
11086 #define DBGMCU_CR_DBG_TIM6_STOP             DBGMCU_CR_DBG_TIM6_STOP_Msk        /*!< TIM6 counter stopped when core is halted */
11087 #define DBGMCU_CR_DBG_TIM7_STOP_Pos         (20U)
11088 #define DBGMCU_CR_DBG_TIM7_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_TIM7_STOP_Pos) /*!< 0x00100000 */
11089 #define DBGMCU_CR_DBG_TIM7_STOP             DBGMCU_CR_DBG_TIM7_STOP_Msk        /*!< TIM7 counter stopped when core is halted */
11090 
11091 /******************************************************************************/
11092 /*                                                                            */
11093 /*                      FLASH and Option Bytes Registers                      */
11094 /*                                                                            */
11095 /******************************************************************************/
11096 /*******************  Bit definition for FLASH_ACR register  ******************/
11097 #define FLASH_ACR_LATENCY_Pos               (0U)
11098 #define FLASH_ACR_LATENCY_Msk               (0x7UL << FLASH_ACR_LATENCY_Pos)    /*!< 0x00000007 */
11099 #define FLASH_ACR_LATENCY                   FLASH_ACR_LATENCY_Msk              /*!< LATENCY[2:0] bits (Latency) */
11100 #define FLASH_ACR_LATENCY_0                 (0x1UL << FLASH_ACR_LATENCY_Pos)    /*!< 0x00000001 */
11101 #define FLASH_ACR_LATENCY_1                 (0x2UL << FLASH_ACR_LATENCY_Pos)    /*!< 0x00000002 */
11102 #define FLASH_ACR_LATENCY_2                 (0x4UL << FLASH_ACR_LATENCY_Pos)    /*!< 0x00000004 */
11103 
11104 #define FLASH_ACR_HLFCYA_Pos                (3U)
11105 #define FLASH_ACR_HLFCYA_Msk                (0x1UL << FLASH_ACR_HLFCYA_Pos)     /*!< 0x00000008 */
11106 #define FLASH_ACR_HLFCYA                    FLASH_ACR_HLFCYA_Msk               /*!< Flash Half Cycle Access Enable */
11107 #define FLASH_ACR_PRFTBE_Pos                (4U)
11108 #define FLASH_ACR_PRFTBE_Msk                (0x1UL << FLASH_ACR_PRFTBE_Pos)     /*!< 0x00000010 */
11109 #define FLASH_ACR_PRFTBE                    FLASH_ACR_PRFTBE_Msk               /*!< Prefetch Buffer Enable */
11110 #define FLASH_ACR_PRFTBS_Pos                (5U)
11111 #define FLASH_ACR_PRFTBS_Msk                (0x1UL << FLASH_ACR_PRFTBS_Pos)     /*!< 0x00000020 */
11112 #define FLASH_ACR_PRFTBS                    FLASH_ACR_PRFTBS_Msk               /*!< Prefetch Buffer Status */
11113 
11114 /******************  Bit definition for FLASH_KEYR register  ******************/
11115 #define FLASH_KEYR_FKEYR_Pos                (0U)
11116 #define FLASH_KEYR_FKEYR_Msk                (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
11117 #define FLASH_KEYR_FKEYR                    FLASH_KEYR_FKEYR_Msk               /*!< FPEC Key */
11118 
11119 #define RDP_KEY_Pos                         (0U)
11120 #define RDP_KEY_Msk                         (0xA5UL << RDP_KEY_Pos)             /*!< 0x000000A5 */
11121 #define RDP_KEY                             RDP_KEY_Msk                        /*!< RDP Key */
11122 #define FLASH_KEY1_Pos                      (0U)
11123 #define FLASH_KEY1_Msk                      (0x45670123UL << FLASH_KEY1_Pos)    /*!< 0x45670123 */
11124 #define FLASH_KEY1                          FLASH_KEY1_Msk                     /*!< FPEC Key1 */
11125 #define FLASH_KEY2_Pos                      (0U)
11126 #define FLASH_KEY2_Msk                      (0xCDEF89ABUL << FLASH_KEY2_Pos)    /*!< 0xCDEF89AB */
11127 #define FLASH_KEY2                          FLASH_KEY2_Msk                     /*!< FPEC Key2 */
11128 
11129 /*****************  Bit definition for FLASH_OPTKEYR register  ****************/
11130 #define FLASH_OPTKEYR_OPTKEYR_Pos           (0U)
11131 #define FLASH_OPTKEYR_OPTKEYR_Msk           (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
11132 #define FLASH_OPTKEYR_OPTKEYR               FLASH_OPTKEYR_OPTKEYR_Msk          /*!< Option Byte Key */
11133 
11134 #define  FLASH_OPTKEY1                       FLASH_KEY1                    /*!< Option Byte Key1 */
11135 #define  FLASH_OPTKEY2                       FLASH_KEY2                    /*!< Option Byte Key2 */
11136 
11137 /******************  Bit definition for FLASH_SR register  ********************/
11138 #define FLASH_SR_BSY_Pos                    (0U)
11139 #define FLASH_SR_BSY_Msk                    (0x1UL << FLASH_SR_BSY_Pos)         /*!< 0x00000001 */
11140 #define FLASH_SR_BSY                        FLASH_SR_BSY_Msk                   /*!< Busy */
11141 #define FLASH_SR_PGERR_Pos                  (2U)
11142 #define FLASH_SR_PGERR_Msk                  (0x1UL << FLASH_SR_PGERR_Pos)       /*!< 0x00000004 */
11143 #define FLASH_SR_PGERR                      FLASH_SR_PGERR_Msk                 /*!< Programming Error */
11144 #define FLASH_SR_WRPRTERR_Pos               (4U)
11145 #define FLASH_SR_WRPRTERR_Msk               (0x1UL << FLASH_SR_WRPRTERR_Pos)    /*!< 0x00000010 */
11146 #define FLASH_SR_WRPRTERR                   FLASH_SR_WRPRTERR_Msk              /*!< Write Protection Error */
11147 #define FLASH_SR_EOP_Pos                    (5U)
11148 #define FLASH_SR_EOP_Msk                    (0x1UL << FLASH_SR_EOP_Pos)         /*!< 0x00000020 */
11149 #define FLASH_SR_EOP                        FLASH_SR_EOP_Msk                   /*!< End of operation */
11150 
11151 /*******************  Bit definition for FLASH_CR register  *******************/
11152 #define FLASH_CR_PG_Pos                     (0U)
11153 #define FLASH_CR_PG_Msk                     (0x1UL << FLASH_CR_PG_Pos)          /*!< 0x00000001 */
11154 #define FLASH_CR_PG                         FLASH_CR_PG_Msk                    /*!< Programming */
11155 #define FLASH_CR_PER_Pos                    (1U)
11156 #define FLASH_CR_PER_Msk                    (0x1UL << FLASH_CR_PER_Pos)         /*!< 0x00000002 */
11157 #define FLASH_CR_PER                        FLASH_CR_PER_Msk                   /*!< Page Erase */
11158 #define FLASH_CR_MER_Pos                    (2U)
11159 #define FLASH_CR_MER_Msk                    (0x1UL << FLASH_CR_MER_Pos)         /*!< 0x00000004 */
11160 #define FLASH_CR_MER                        FLASH_CR_MER_Msk                   /*!< Mass Erase */
11161 #define FLASH_CR_OPTPG_Pos                  (4U)
11162 #define FLASH_CR_OPTPG_Msk                  (0x1UL << FLASH_CR_OPTPG_Pos)       /*!< 0x00000010 */
11163 #define FLASH_CR_OPTPG                      FLASH_CR_OPTPG_Msk                 /*!< Option Byte Programming */
11164 #define FLASH_CR_OPTER_Pos                  (5U)
11165 #define FLASH_CR_OPTER_Msk                  (0x1UL << FLASH_CR_OPTER_Pos)       /*!< 0x00000020 */
11166 #define FLASH_CR_OPTER                      FLASH_CR_OPTER_Msk                 /*!< Option Byte Erase */
11167 #define FLASH_CR_STRT_Pos                   (6U)
11168 #define FLASH_CR_STRT_Msk                   (0x1UL << FLASH_CR_STRT_Pos)        /*!< 0x00000040 */
11169 #define FLASH_CR_STRT                       FLASH_CR_STRT_Msk                  /*!< Start */
11170 #define FLASH_CR_LOCK_Pos                   (7U)
11171 #define FLASH_CR_LOCK_Msk                   (0x1UL << FLASH_CR_LOCK_Pos)        /*!< 0x00000080 */
11172 #define FLASH_CR_LOCK                       FLASH_CR_LOCK_Msk                  /*!< Lock */
11173 #define FLASH_CR_OPTWRE_Pos                 (9U)
11174 #define FLASH_CR_OPTWRE_Msk                 (0x1UL << FLASH_CR_OPTWRE_Pos)      /*!< 0x00000200 */
11175 #define FLASH_CR_OPTWRE                     FLASH_CR_OPTWRE_Msk                /*!< Option Bytes Write Enable */
11176 #define FLASH_CR_ERRIE_Pos                  (10U)
11177 #define FLASH_CR_ERRIE_Msk                  (0x1UL << FLASH_CR_ERRIE_Pos)       /*!< 0x00000400 */
11178 #define FLASH_CR_ERRIE                      FLASH_CR_ERRIE_Msk                 /*!< Error Interrupt Enable */
11179 #define FLASH_CR_EOPIE_Pos                  (12U)
11180 #define FLASH_CR_EOPIE_Msk                  (0x1UL << FLASH_CR_EOPIE_Pos)       /*!< 0x00001000 */
11181 #define FLASH_CR_EOPIE                      FLASH_CR_EOPIE_Msk                 /*!< End of operation interrupt enable */
11182 
11183 /*******************  Bit definition for FLASH_AR register  *******************/
11184 #define FLASH_AR_FAR_Pos                    (0U)
11185 #define FLASH_AR_FAR_Msk                    (0xFFFFFFFFUL << FLASH_AR_FAR_Pos)  /*!< 0xFFFFFFFF */
11186 #define FLASH_AR_FAR                        FLASH_AR_FAR_Msk                   /*!< Flash Address */
11187 
11188 /******************  Bit definition for FLASH_OBR register  *******************/
11189 #define FLASH_OBR_OPTERR_Pos                (0U)
11190 #define FLASH_OBR_OPTERR_Msk                (0x1UL << FLASH_OBR_OPTERR_Pos)     /*!< 0x00000001 */
11191 #define FLASH_OBR_OPTERR                    FLASH_OBR_OPTERR_Msk               /*!< Option Byte Error */
11192 #define FLASH_OBR_RDPRT_Pos                 (1U)
11193 #define FLASH_OBR_RDPRT_Msk                 (0x1UL << FLASH_OBR_RDPRT_Pos)      /*!< 0x00000002 */
11194 #define FLASH_OBR_RDPRT                     FLASH_OBR_RDPRT_Msk                /*!< Read protection */
11195 
11196 #define FLASH_OBR_IWDG_SW_Pos               (2U)
11197 #define FLASH_OBR_IWDG_SW_Msk               (0x1UL << FLASH_OBR_IWDG_SW_Pos)    /*!< 0x00000004 */
11198 #define FLASH_OBR_IWDG_SW                   FLASH_OBR_IWDG_SW_Msk              /*!< IWDG SW */
11199 #define FLASH_OBR_nRST_STOP_Pos             (3U)
11200 #define FLASH_OBR_nRST_STOP_Msk             (0x1UL << FLASH_OBR_nRST_STOP_Pos)  /*!< 0x00000008 */
11201 #define FLASH_OBR_nRST_STOP                 FLASH_OBR_nRST_STOP_Msk            /*!< nRST_STOP */
11202 #define FLASH_OBR_nRST_STDBY_Pos            (4U)
11203 #define FLASH_OBR_nRST_STDBY_Msk            (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */
11204 #define FLASH_OBR_nRST_STDBY                FLASH_OBR_nRST_STDBY_Msk           /*!< nRST_STDBY */
11205 #define FLASH_OBR_USER_Pos                  (2U)
11206 #define FLASH_OBR_USER_Msk                  (0x7UL << FLASH_OBR_USER_Pos)       /*!< 0x0000001C */
11207 #define FLASH_OBR_USER                      FLASH_OBR_USER_Msk                 /*!< User Option Bytes */
11208 #define FLASH_OBR_DATA0_Pos                 (10U)
11209 #define FLASH_OBR_DATA0_Msk                 (0xFFUL << FLASH_OBR_DATA0_Pos)     /*!< 0x0003FC00 */
11210 #define FLASH_OBR_DATA0                     FLASH_OBR_DATA0_Msk                /*!< Data0 */
11211 #define FLASH_OBR_DATA1_Pos                 (18U)
11212 #define FLASH_OBR_DATA1_Msk                 (0xFFUL << FLASH_OBR_DATA1_Pos)     /*!< 0x03FC0000 */
11213 #define FLASH_OBR_DATA1                     FLASH_OBR_DATA1_Msk                /*!< Data1 */
11214 
11215 /******************  Bit definition for FLASH_WRPR register  ******************/
11216 #define FLASH_WRPR_WRP_Pos                  (0U)
11217 #define FLASH_WRPR_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
11218 #define FLASH_WRPR_WRP                      FLASH_WRPR_WRP_Msk                 /*!< Write Protect */
11219 
11220 /*----------------------------------------------------------------------------*/
11221 
11222 /******************  Bit definition for FLASH_RDP register  *******************/
11223 #define FLASH_RDP_RDP_Pos                   (0U)
11224 #define FLASH_RDP_RDP_Msk                   (0xFFUL << FLASH_RDP_RDP_Pos)       /*!< 0x000000FF */
11225 #define FLASH_RDP_RDP                       FLASH_RDP_RDP_Msk                  /*!< Read protection option byte */
11226 #define FLASH_RDP_nRDP_Pos                  (8U)
11227 #define FLASH_RDP_nRDP_Msk                  (0xFFUL << FLASH_RDP_nRDP_Pos)      /*!< 0x0000FF00 */
11228 #define FLASH_RDP_nRDP                      FLASH_RDP_nRDP_Msk                 /*!< Read protection complemented option byte */
11229 
11230 /******************  Bit definition for FLASH_USER register  ******************/
11231 #define FLASH_USER_USER_Pos                 (16U)
11232 #define FLASH_USER_USER_Msk                 (0xFFUL << FLASH_USER_USER_Pos)     /*!< 0x00FF0000 */
11233 #define FLASH_USER_USER                     FLASH_USER_USER_Msk                /*!< User option byte */
11234 #define FLASH_USER_nUSER_Pos                (24U)
11235 #define FLASH_USER_nUSER_Msk                (0xFFUL << FLASH_USER_nUSER_Pos)    /*!< 0xFF000000 */
11236 #define FLASH_USER_nUSER                    FLASH_USER_nUSER_Msk               /*!< User complemented option byte */
11237 
11238 /******************  Bit definition for FLASH_Data0 register  *****************/
11239 #define FLASH_DATA0_DATA0_Pos               (0U)
11240 #define FLASH_DATA0_DATA0_Msk               (0xFFUL << FLASH_DATA0_DATA0_Pos)   /*!< 0x000000FF */
11241 #define FLASH_DATA0_DATA0                   FLASH_DATA0_DATA0_Msk              /*!< User data storage option byte */
11242 #define FLASH_DATA0_nDATA0_Pos              (8U)
11243 #define FLASH_DATA0_nDATA0_Msk              (0xFFUL << FLASH_DATA0_nDATA0_Pos)  /*!< 0x0000FF00 */
11244 #define FLASH_DATA0_nDATA0                  FLASH_DATA0_nDATA0_Msk             /*!< User data storage complemented option byte */
11245 
11246 /******************  Bit definition for FLASH_Data1 register  *****************/
11247 #define FLASH_DATA1_DATA1_Pos               (16U)
11248 #define FLASH_DATA1_DATA1_Msk               (0xFFUL << FLASH_DATA1_DATA1_Pos)   /*!< 0x00FF0000 */
11249 #define FLASH_DATA1_DATA1                   FLASH_DATA1_DATA1_Msk              /*!< User data storage option byte */
11250 #define FLASH_DATA1_nDATA1_Pos              (24U)
11251 #define FLASH_DATA1_nDATA1_Msk              (0xFFUL << FLASH_DATA1_nDATA1_Pos)  /*!< 0xFF000000 */
11252 #define FLASH_DATA1_nDATA1                  FLASH_DATA1_nDATA1_Msk             /*!< User data storage complemented option byte */
11253 
11254 /******************  Bit definition for FLASH_WRP0 register  ******************/
11255 #define FLASH_WRP0_WRP0_Pos                 (0U)
11256 #define FLASH_WRP0_WRP0_Msk                 (0xFFUL << FLASH_WRP0_WRP0_Pos)     /*!< 0x000000FF */
11257 #define FLASH_WRP0_WRP0                     FLASH_WRP0_WRP0_Msk                /*!< Flash memory write protection option bytes */
11258 #define FLASH_WRP0_nWRP0_Pos                (8U)
11259 #define FLASH_WRP0_nWRP0_Msk                (0xFFUL << FLASH_WRP0_nWRP0_Pos)    /*!< 0x0000FF00 */
11260 #define FLASH_WRP0_nWRP0                    FLASH_WRP0_nWRP0_Msk               /*!< Flash memory write protection complemented option bytes */
11261 
11262 /******************  Bit definition for FLASH_WRP1 register  ******************/
11263 #define FLASH_WRP1_WRP1_Pos                 (16U)
11264 #define FLASH_WRP1_WRP1_Msk                 (0xFFUL << FLASH_WRP1_WRP1_Pos)     /*!< 0x00FF0000 */
11265 #define FLASH_WRP1_WRP1                     FLASH_WRP1_WRP1_Msk                /*!< Flash memory write protection option bytes */
11266 #define FLASH_WRP1_nWRP1_Pos                (24U)
11267 #define FLASH_WRP1_nWRP1_Msk                (0xFFUL << FLASH_WRP1_nWRP1_Pos)    /*!< 0xFF000000 */
11268 #define FLASH_WRP1_nWRP1                    FLASH_WRP1_nWRP1_Msk               /*!< Flash memory write protection complemented option bytes */
11269 
11270 /******************  Bit definition for FLASH_WRP2 register  ******************/
11271 #define FLASH_WRP2_WRP2_Pos                 (0U)
11272 #define FLASH_WRP2_WRP2_Msk                 (0xFFUL << FLASH_WRP2_WRP2_Pos)     /*!< 0x000000FF */
11273 #define FLASH_WRP2_WRP2                     FLASH_WRP2_WRP2_Msk                /*!< Flash memory write protection option bytes */
11274 #define FLASH_WRP2_nWRP2_Pos                (8U)
11275 #define FLASH_WRP2_nWRP2_Msk                (0xFFUL << FLASH_WRP2_nWRP2_Pos)    /*!< 0x0000FF00 */
11276 #define FLASH_WRP2_nWRP2                    FLASH_WRP2_nWRP2_Msk               /*!< Flash memory write protection complemented option bytes */
11277 
11278 /******************  Bit definition for FLASH_WRP3 register  ******************/
11279 #define FLASH_WRP3_WRP3_Pos                 (16U)
11280 #define FLASH_WRP3_WRP3_Msk                 (0xFFUL << FLASH_WRP3_WRP3_Pos)     /*!< 0x00FF0000 */
11281 #define FLASH_WRP3_WRP3                     FLASH_WRP3_WRP3_Msk                /*!< Flash memory write protection option bytes */
11282 #define FLASH_WRP3_nWRP3_Pos                (24U)
11283 #define FLASH_WRP3_nWRP3_Msk                (0xFFUL << FLASH_WRP3_nWRP3_Pos)    /*!< 0xFF000000 */
11284 #define FLASH_WRP3_nWRP3                    FLASH_WRP3_nWRP3_Msk               /*!< Flash memory write protection complemented option bytes */
11285 
11286 
11287 
11288 /**
11289   * @}
11290 */
11291 
11292 /**
11293   * @}
11294 */
11295 
11296 /** @addtogroup Exported_macro
11297   * @{
11298   */
11299 
11300 /****************************** ADC Instances *********************************/
11301 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
11302                                        ((INSTANCE) == ADC2) || \
11303                                        ((INSTANCE) == ADC3))
11304 
11305 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
11306 
11307 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
11308 
11309 #define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
11310                                                   ((INSTANCE) == ADC3))
11311 
11312 /****************************** CAN Instances *********************************/
11313 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
11314 
11315 /****************************** CRC Instances *********************************/
11316 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
11317 
11318 /****************************** DAC Instances *********************************/
11319 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
11320 
11321 /****************************** DMA Instances *********************************/
11322 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
11323                                        ((INSTANCE) == DMA1_Channel2) || \
11324                                        ((INSTANCE) == DMA1_Channel3) || \
11325                                        ((INSTANCE) == DMA1_Channel4) || \
11326                                        ((INSTANCE) == DMA1_Channel5) || \
11327                                        ((INSTANCE) == DMA1_Channel6) || \
11328                                        ((INSTANCE) == DMA1_Channel7) || \
11329                                        ((INSTANCE) == DMA2_Channel1) || \
11330                                        ((INSTANCE) == DMA2_Channel2) || \
11331                                        ((INSTANCE) == DMA2_Channel3) || \
11332                                        ((INSTANCE) == DMA2_Channel4) || \
11333                                        ((INSTANCE) == DMA2_Channel5))
11334 
11335 /******************************* GPIO Instances *******************************/
11336 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
11337                                         ((INSTANCE) == GPIOB) || \
11338                                         ((INSTANCE) == GPIOC) || \
11339                                         ((INSTANCE) == GPIOD) || \
11340                                         ((INSTANCE) == GPIOE) || \
11341                                         ((INSTANCE) == GPIOF) || \
11342                                         ((INSTANCE) == GPIOG))
11343 
11344 /**************************** GPIO Alternate Function Instances ***************/
11345 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
11346 
11347 /**************************** GPIO Lock Instances *****************************/
11348 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
11349 
11350 /******************************** I2C Instances *******************************/
11351 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
11352                                        ((INSTANCE) == I2C2))
11353 
11354 /******************************* SMBUS Instances ******************************/
11355 #define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE
11356 
11357 /******************************** I2S Instances *******************************/
11358 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
11359                                        ((INSTANCE) == SPI3))
11360 
11361 /****************************** IWDG Instances ********************************/
11362 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
11363 
11364 /****************************** SDIO Instances *********************************/
11365 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
11366 
11367 /******************************** SPI Instances *******************************/
11368 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
11369                                        ((INSTANCE) == SPI2) || \
11370                                        ((INSTANCE) == SPI3))
11371 
11372 /****************************** START TIM Instances ***************************/
11373 /****************************** TIM Instances *********************************/
11374 #define IS_TIM_INSTANCE(INSTANCE)\
11375   (((INSTANCE) == TIM1)    || \
11376    ((INSTANCE) == TIM8)    || \
11377    ((INSTANCE) == TIM2)    || \
11378    ((INSTANCE) == TIM3)    || \
11379    ((INSTANCE) == TIM4)    || \
11380    ((INSTANCE) == TIM5)    || \
11381    ((INSTANCE) == TIM6)    || \
11382    ((INSTANCE) == TIM7))
11383 
11384 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
11385   (((INSTANCE) == TIM1)    || \
11386    ((INSTANCE) == TIM8))
11387 
11388 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
11389   (((INSTANCE) == TIM1)    || \
11390    ((INSTANCE) == TIM8)    || \
11391    ((INSTANCE) == TIM2)    || \
11392    ((INSTANCE) == TIM3)    || \
11393    ((INSTANCE) == TIM4)    || \
11394    ((INSTANCE) == TIM5))
11395 
11396 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
11397   (((INSTANCE) == TIM1)    || \
11398    ((INSTANCE) == TIM8)    || \
11399    ((INSTANCE) == TIM2)    || \
11400    ((INSTANCE) == TIM3)    || \
11401    ((INSTANCE) == TIM4)    || \
11402    ((INSTANCE) == TIM5))
11403 
11404 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
11405   (((INSTANCE) == TIM1)    || \
11406    ((INSTANCE) == TIM8)    || \
11407    ((INSTANCE) == TIM2)    || \
11408    ((INSTANCE) == TIM3)    || \
11409    ((INSTANCE) == TIM4)    || \
11410    ((INSTANCE) == TIM5))
11411 
11412 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
11413   (((INSTANCE) == TIM1)    || \
11414    ((INSTANCE) == TIM8)    || \
11415    ((INSTANCE) == TIM2)    || \
11416    ((INSTANCE) == TIM3)    || \
11417    ((INSTANCE) == TIM4)    || \
11418    ((INSTANCE) == TIM5))
11419 
11420 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
11421   (((INSTANCE) == TIM1)    || \
11422    ((INSTANCE) == TIM8)    || \
11423    ((INSTANCE) == TIM2)    || \
11424    ((INSTANCE) == TIM3)    || \
11425    ((INSTANCE) == TIM4)    || \
11426    ((INSTANCE) == TIM5))
11427 
11428 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
11429   (((INSTANCE) == TIM1)    || \
11430    ((INSTANCE) == TIM8)    || \
11431    ((INSTANCE) == TIM2)    || \
11432    ((INSTANCE) == TIM3)    || \
11433    ((INSTANCE) == TIM4)    || \
11434    ((INSTANCE) == TIM5))
11435 
11436 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
11437   (((INSTANCE) == TIM1)    || \
11438    ((INSTANCE) == TIM8)    || \
11439    ((INSTANCE) == TIM2)    || \
11440    ((INSTANCE) == TIM3)    || \
11441    ((INSTANCE) == TIM4)    || \
11442    ((INSTANCE) == TIM5))
11443 
11444 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
11445   (((INSTANCE) == TIM1)    || \
11446    ((INSTANCE) == TIM8)    || \
11447    ((INSTANCE) == TIM2)    || \
11448    ((INSTANCE) == TIM3)    || \
11449    ((INSTANCE) == TIM4)    || \
11450    ((INSTANCE) == TIM5))
11451 
11452 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
11453   (((INSTANCE) == TIM1)    || \
11454    ((INSTANCE) == TIM8)    || \
11455    ((INSTANCE) == TIM2)    || \
11456    ((INSTANCE) == TIM3)    || \
11457    ((INSTANCE) == TIM4)    || \
11458    ((INSTANCE) == TIM5))
11459 
11460 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
11461   (((INSTANCE) == TIM1)    || \
11462    ((INSTANCE) == TIM8)    || \
11463    ((INSTANCE) == TIM2)    || \
11464    ((INSTANCE) == TIM3)    || \
11465    ((INSTANCE) == TIM4)    || \
11466    ((INSTANCE) == TIM5))
11467 
11468 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
11469   (((INSTANCE) == TIM1)    || \
11470    ((INSTANCE) == TIM8)    || \
11471    ((INSTANCE) == TIM2)    || \
11472    ((INSTANCE) == TIM3)    || \
11473    ((INSTANCE) == TIM4)    || \
11474    ((INSTANCE) == TIM5))
11475 
11476 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
11477   (((INSTANCE) == TIM1)    || \
11478    ((INSTANCE) == TIM8)    || \
11479    ((INSTANCE) == TIM2)    || \
11480    ((INSTANCE) == TIM3)    || \
11481    ((INSTANCE) == TIM4)    || \
11482    ((INSTANCE) == TIM5)    || \
11483    ((INSTANCE) == TIM6)    || \
11484    ((INSTANCE) == TIM7))
11485 
11486 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
11487   (((INSTANCE) == TIM1)    || \
11488    ((INSTANCE) == TIM8)    || \
11489    ((INSTANCE) == TIM2)    || \
11490    ((INSTANCE) == TIM3)    || \
11491    ((INSTANCE) == TIM4)    || \
11492    ((INSTANCE) == TIM5))
11493 
11494 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
11495   (((INSTANCE) == TIM1)    || \
11496    ((INSTANCE) == TIM8)    || \
11497    ((INSTANCE) == TIM2)    || \
11498    ((INSTANCE) == TIM3)    || \
11499    ((INSTANCE) == TIM4)    || \
11500    ((INSTANCE) == TIM5))
11501 
11502 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
11503   (((INSTANCE) == TIM1)    || \
11504    ((INSTANCE) == TIM8))
11505 
11506 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
11507    ((((INSTANCE) == TIM1) &&                  \
11508      (((CHANNEL) == TIM_CHANNEL_1) ||          \
11509       ((CHANNEL) == TIM_CHANNEL_2) ||          \
11510       ((CHANNEL) == TIM_CHANNEL_3) ||          \
11511       ((CHANNEL) == TIM_CHANNEL_4)))           \
11512     ||                                         \
11513     (((INSTANCE) == TIM8) &&                   \
11514      (((CHANNEL) == TIM_CHANNEL_1) ||          \
11515       ((CHANNEL) == TIM_CHANNEL_2) ||          \
11516       ((CHANNEL) == TIM_CHANNEL_3) ||          \
11517       ((CHANNEL) == TIM_CHANNEL_4)))           \
11518     ||                                         \
11519     (((INSTANCE) == TIM2) &&                   \
11520      (((CHANNEL) == TIM_CHANNEL_1) ||          \
11521       ((CHANNEL) == TIM_CHANNEL_2) ||          \
11522       ((CHANNEL) == TIM_CHANNEL_3) ||          \
11523       ((CHANNEL) == TIM_CHANNEL_4)))           \
11524     ||                                         \
11525     (((INSTANCE) == TIM3) &&                   \
11526      (((CHANNEL) == TIM_CHANNEL_1) ||          \
11527       ((CHANNEL) == TIM_CHANNEL_2) ||          \
11528       ((CHANNEL) == TIM_CHANNEL_3) ||          \
11529       ((CHANNEL) == TIM_CHANNEL_4)))           \
11530     ||                                         \
11531     (((INSTANCE) == TIM4) &&                   \
11532      (((CHANNEL) == TIM_CHANNEL_1) ||          \
11533       ((CHANNEL) == TIM_CHANNEL_2) ||          \
11534       ((CHANNEL) == TIM_CHANNEL_3) ||          \
11535       ((CHANNEL) == TIM_CHANNEL_4)))           \
11536     ||                                         \
11537     (((INSTANCE) == TIM5) &&                   \
11538      (((CHANNEL) == TIM_CHANNEL_1) ||          \
11539       ((CHANNEL) == TIM_CHANNEL_2) ||          \
11540       ((CHANNEL) == TIM_CHANNEL_3) ||          \
11541       ((CHANNEL) == TIM_CHANNEL_4))))
11542 
11543 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
11544    ((((INSTANCE) == TIM1) &&                    \
11545      (((CHANNEL) == TIM_CHANNEL_1) ||           \
11546       ((CHANNEL) == TIM_CHANNEL_2) ||           \
11547       ((CHANNEL) == TIM_CHANNEL_3)))            \
11548     ||                                          \
11549     (((INSTANCE) == TIM8) &&                    \
11550      (((CHANNEL) == TIM_CHANNEL_1) ||           \
11551       ((CHANNEL) == TIM_CHANNEL_2) ||           \
11552       ((CHANNEL) == TIM_CHANNEL_3))))
11553 
11554 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
11555   (((INSTANCE) == TIM1)    || \
11556    ((INSTANCE) == TIM8)    || \
11557    ((INSTANCE) == TIM2)    || \
11558    ((INSTANCE) == TIM3)    || \
11559    ((INSTANCE) == TIM4)    || \
11560    ((INSTANCE) == TIM5))
11561 
11562 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
11563   (((INSTANCE) == TIM1)    || \
11564    ((INSTANCE) == TIM8))
11565 
11566 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
11567   (((INSTANCE) == TIM1)    || \
11568    ((INSTANCE) == TIM8)    || \
11569    ((INSTANCE) == TIM2)    || \
11570    ((INSTANCE) == TIM3)    || \
11571    ((INSTANCE) == TIM4)    || \
11572    ((INSTANCE) == TIM5))
11573 
11574 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
11575   (((INSTANCE) == TIM1)    || \
11576    ((INSTANCE) == TIM8)    || \
11577    ((INSTANCE) == TIM2)    || \
11578    ((INSTANCE) == TIM3)    || \
11579    ((INSTANCE) == TIM4)    || \
11580    ((INSTANCE) == TIM5)    || \
11581    ((INSTANCE) == TIM6)    || \
11582    ((INSTANCE) == TIM7))
11583 
11584 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
11585   (((INSTANCE) == TIM1)    || \
11586    ((INSTANCE) == TIM8)    || \
11587    ((INSTANCE) == TIM2)    || \
11588    ((INSTANCE) == TIM3)    || \
11589    ((INSTANCE) == TIM4)    || \
11590    ((INSTANCE) == TIM5))
11591 
11592 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
11593   (((INSTANCE) == TIM1)    || \
11594    ((INSTANCE) == TIM8))
11595 
11596 #define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)    || \
11597                                         ((INSTANCE) == TIM2)    || \
11598                                         ((INSTANCE) == TIM3)    || \
11599                                         ((INSTANCE) == TIM4)    || \
11600                                         ((INSTANCE) == TIM5)    || \
11601                                         ((INSTANCE) == TIM8))
11602 
11603 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \
11604                                                          ((INSTANCE) == TIM2)    || \
11605                                                          ((INSTANCE) == TIM3)    || \
11606                                                          ((INSTANCE) == TIM4)    || \
11607                                                          ((INSTANCE) == TIM5)    || \
11608                                                          ((INSTANCE) == TIM8))
11609 
11610 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)           0U
11611 
11612 /****************************** END TIM Instances *****************************/
11613 
11614 
11615 /******************** USART Instances : Synchronous mode **********************/
11616 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11617                                      ((INSTANCE) == USART2) || \
11618                                      ((INSTANCE) == USART3))
11619 
11620 /******************** UART Instances : Asynchronous mode **********************/
11621 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11622                                     ((INSTANCE) == USART2) || \
11623                                     ((INSTANCE) == USART3) || \
11624                                     ((INSTANCE) == UART4)  || \
11625                                     ((INSTANCE) == UART5))
11626 
11627 /******************** UART Instances : Half-Duplex mode **********************/
11628 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11629                                                ((INSTANCE) == USART2) || \
11630                                                ((INSTANCE) == USART3) || \
11631                                                ((INSTANCE) == UART4)  || \
11632                                                ((INSTANCE) == UART5))
11633 
11634 /******************** UART Instances : LIN mode **********************/
11635 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11636                                         ((INSTANCE) == USART2) || \
11637                                         ((INSTANCE) == USART3) || \
11638                                         ((INSTANCE) == UART4)  || \
11639                                         ((INSTANCE) == UART5))
11640 
11641 /****************** UART Instances : Hardware Flow control ********************/
11642 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11643                                            ((INSTANCE) == USART2) || \
11644                                            ((INSTANCE) == USART3))
11645 
11646 /********************* UART Instances : Smard card mode ***********************/
11647 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11648                                          ((INSTANCE) == USART2) || \
11649                                          ((INSTANCE) == USART3))
11650 
11651 /*********************** UART Instances : IRDA mode ***************************/
11652 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11653                                     ((INSTANCE) == USART2) || \
11654                                     ((INSTANCE) == USART3) || \
11655                                     ((INSTANCE) == UART4)  || \
11656                                     ((INSTANCE) == UART5))
11657 
11658 /***************** UART Instances : Multi-Processor mode **********************/
11659 #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11660                                                    ((INSTANCE) == USART2) || \
11661                                                    ((INSTANCE) == USART3) || \
11662                                                    ((INSTANCE) == UART4)  || \
11663                                                    ((INSTANCE) == UART5))
11664 
11665 /***************** UART Instances : DMA mode available **********************/
11666 #define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11667                                         ((INSTANCE) == USART2) || \
11668                                         ((INSTANCE) == USART3) || \
11669                                         ((INSTANCE) == UART4))
11670 
11671 /****************************** RTC Instances *********************************/
11672 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
11673 
11674 /**************************** WWDG Instances *****************************/
11675 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
11676 
11677 /****************************** USB Instances ********************************/
11678 #define IS_PCD_ALL_INSTANCE(INSTANCE)   ((INSTANCE) == USB)
11679 
11680 
11681 
11682 #define RCC_HSE_MIN         4000000U
11683 #define RCC_HSE_MAX        16000000U
11684 
11685 #define RCC_MAX_FREQUENCY  72000000U
11686 
11687 /**
11688   * @}
11689   */
11690 /******************************************************************************/
11691 /*  For a painless codes migration between the STM32F1xx device product       */
11692 /*  lines, the aliases defined below are put in place to overcome the         */
11693 /*  differences in the interrupt handlers and IRQn definitions.               */
11694 /*  No need to update developed interrupt code when moving across             */
11695 /*  product lines within the same STM32F1 Family                              */
11696 /******************************************************************************/
11697 
11698 /* Aliases for __IRQn */
11699 #define ADC1_IRQn               ADC1_2_IRQn
11700 #define DMA2_Channel4_IRQn      DMA2_Channel4_5_IRQn
11701 #define TIM1_BRK_TIM9_IRQn      TIM1_BRK_IRQn
11702 #define TIM9_IRQn               TIM1_BRK_IRQn
11703 #define TIM1_BRK_TIM15_IRQn     TIM1_BRK_IRQn
11704 #define TIM11_IRQn              TIM1_TRG_COM_IRQn
11705 #define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
11706 #define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
11707 #define TIM1_UP_TIM10_IRQn      TIM1_UP_IRQn
11708 #define TIM1_UP_TIM16_IRQn      TIM1_UP_IRQn
11709 #define TIM10_IRQn              TIM1_UP_IRQn
11710 #define TIM6_DAC_IRQn           TIM6_IRQn
11711 #define TIM8_BRK_TIM12_IRQn     TIM8_BRK_IRQn
11712 #define TIM12_IRQn              TIM8_BRK_IRQn
11713 #define TIM14_IRQn              TIM8_TRG_COM_IRQn
11714 #define TIM8_TRG_COM_TIM14_IRQn TIM8_TRG_COM_IRQn
11715 #define TIM8_UP_TIM13_IRQn      TIM8_UP_IRQn
11716 #define TIM13_IRQn              TIM8_UP_IRQn
11717 #define CEC_IRQn                USBWakeUp_IRQn
11718 #define OTG_FS_WKUP_IRQn        USBWakeUp_IRQn
11719 #define USB_HP_IRQn             USB_HP_CAN1_TX_IRQn
11720 #define CAN1_TX_IRQn            USB_HP_CAN1_TX_IRQn
11721 #define USB_LP_IRQn             USB_LP_CAN1_RX0_IRQn
11722 #define CAN1_RX0_IRQn           USB_LP_CAN1_RX0_IRQn
11723 
11724 
11725 /* Aliases for __IRQHandler */
11726 #define ADC1_IRQHandler               ADC1_2_IRQHandler
11727 #define DMA2_Channel4_IRQHandler      DMA2_Channel4_5_IRQHandler
11728 #define TIM1_BRK_TIM9_IRQHandler      TIM1_BRK_IRQHandler
11729 #define TIM9_IRQHandler               TIM1_BRK_IRQHandler
11730 #define TIM1_BRK_TIM15_IRQHandler     TIM1_BRK_IRQHandler
11731 #define TIM11_IRQHandler              TIM1_TRG_COM_IRQHandler
11732 #define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
11733 #define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
11734 #define TIM1_UP_TIM10_IRQHandler      TIM1_UP_IRQHandler
11735 #define TIM1_UP_TIM16_IRQHandler      TIM1_UP_IRQHandler
11736 #define TIM10_IRQHandler              TIM1_UP_IRQHandler
11737 #define TIM6_DAC_IRQHandler           TIM6_IRQHandler
11738 #define TIM8_BRK_TIM12_IRQHandler     TIM8_BRK_IRQHandler
11739 #define TIM12_IRQHandler              TIM8_BRK_IRQHandler
11740 #define TIM14_IRQHandler              TIM8_TRG_COM_IRQHandler
11741 #define TIM8_TRG_COM_TIM14_IRQHandler TIM8_TRG_COM_IRQHandler
11742 #define TIM8_UP_TIM13_IRQHandler      TIM8_UP_IRQHandler
11743 #define TIM13_IRQHandler              TIM8_UP_IRQHandler
11744 #define CEC_IRQHandler                USBWakeUp_IRQHandler
11745 #define OTG_FS_WKUP_IRQHandler        USBWakeUp_IRQHandler
11746 #define USB_HP_IRQHandler             USB_HP_CAN1_TX_IRQHandler
11747 #define CAN1_TX_IRQHandler            USB_HP_CAN1_TX_IRQHandler
11748 #define USB_LP_IRQHandler             USB_LP_CAN1_RX0_IRQHandler
11749 #define CAN1_RX0_IRQHandler           USB_LP_CAN1_RX0_IRQHandler
11750 
11751 
11752 /**
11753   * @}
11754   */
11755 
11756 /**
11757   * @}
11758   */
11759 
11760 
11761 #ifdef __cplusplus
11762   }
11763 #endif /* __cplusplus */
11764 
11765 #endif /* __STM32F103xE_H */
11766 
11767 
11768 
11769   /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
11770