1 /**
2 ******************************************************************************
3 * @file stm32f1xx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 @verbatim
7 ==============================================================================
8 ##### How to use this driver #####
9 ==============================================================================
10 [..]
11 The LL SYSTEM driver contains a set of generic APIs that can be
12 used by user:
13 (+) Some of the FLASH features need to be handled in the SYSTEM file.
14 (+) Access to DBGCMU registers
15 (+) Access to SYSCFG registers
16
17 @endverbatim
18 ******************************************************************************
19 * @attention
20 *
21 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
22 * All rights reserved.</center></h2>
23 *
24 * This software component is licensed by ST under BSD 3-Clause license,
25 * the "License"; You may not use this file except in compliance with the
26 * License. You may obtain a copy of the License at:
27 * opensource.org/licenses/BSD-3-Clause
28 *
29 ******************************************************************************
30 */
31
32 /* Define to prevent recursive inclusion -------------------------------------*/
33 #ifndef __STM32F1xx_LL_SYSTEM_H
34 #define __STM32F1xx_LL_SYSTEM_H
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /* Includes ------------------------------------------------------------------*/
41 #include "stm32f1xx.h"
42
43 /** @addtogroup STM32F1xx_LL_Driver
44 * @{
45 */
46
47 #if defined (FLASH) || defined (DBGMCU)
48
49 /** @defgroup SYSTEM_LL SYSTEM
50 * @{
51 */
52
53 /* Private types -------------------------------------------------------------*/
54 /* Private variables ---------------------------------------------------------*/
55
56 /* Private constants ---------------------------------------------------------*/
57 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
58 * @{
59 */
60
61 /**
62 * @}
63 */
64
65 /* Private macros ------------------------------------------------------------*/
66
67 /* Exported types ------------------------------------------------------------*/
68 /* Exported constants --------------------------------------------------------*/
69 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
70 * @{
71 */
72
73
74
75 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
76 * @{
77 */
78 #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
79 #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
80 #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
81 #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
82 #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
83 /**
84 * @}
85 */
86
87 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
88 * @{
89 */
90 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
91 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
92 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */
93 #if defined(DBGMCU_CR_DBG_TIM5_STOP)
94 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */
95 #endif /* DBGMCU_CR_DBG_TIM5_STOP */
96 #if defined(DBGMCU_CR_DBG_TIM6_STOP)
97 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
98 #endif /* DBGMCU_CR_DBG_TIM6_STOP */
99 #if defined(DBGMCU_CR_DBG_TIM7_STOP)
100 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
101 #endif /* DBGMCU_CR_DBG_TIM7_STOP */
102 #if defined(DBGMCU_CR_DBG_TIM12_STOP)
103 #define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_CR_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */
104 #endif /* DBGMCU_CR_DBG_TIM12_STOP */
105 #if defined(DBGMCU_CR_DBG_TIM13_STOP)
106 #define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_CR_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */
107 #endif /* DBGMCU_CR_DBG_TIM13_STOP */
108 #if defined(DBGMCU_CR_DBG_TIM14_STOP)
109 #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_CR_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */
110 #endif /* DBGMCU_CR_DBG_TIM14_STOP */
111 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
112 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
113 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
114 #if defined(DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
115 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
116 #endif /* DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT */
117 #if defined(DBGMCU_CR_DBG_CAN1_STOP)
118 #define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */
119 #endif /* DBGMCU_CR_DBG_CAN1_STOP */
120 #if defined(DBGMCU_CR_DBG_CAN2_STOP)
121 #define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_CR_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */
122 #endif /* DBGMCU_CR_DBG_CAN2_STOP */
123 /**
124 * @}
125 */
126
127 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
128 * @{
129 */
130 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */
131 #if defined(DBGMCU_CR_DBG_TIM8_STOP)
132 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_CR_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */
133 #endif /* DBGMCU_CR_DBG_CAN1_STOP */
134 #if defined(DBGMCU_CR_DBG_TIM9_STOP)
135 #define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */
136 #endif /* DBGMCU_CR_DBG_TIM9_STOP */
137 #if defined(DBGMCU_CR_DBG_TIM10_STOP)
138 #define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */
139 #endif /* DBGMCU_CR_DBG_TIM10_STOP */
140 #if defined(DBGMCU_CR_DBG_TIM11_STOP)
141 #define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */
142 #endif /* DBGMCU_CR_DBG_TIM11_STOP */
143 #if defined(DBGMCU_CR_DBG_TIM15_STOP)
144 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_CR_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */
145 #endif /* DBGMCU_CR_DBG_TIM15_STOP */
146 #if defined(DBGMCU_CR_DBG_TIM16_STOP)
147 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_CR_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */
148 #endif /* DBGMCU_CR_DBG_TIM16_STOP */
149 #if defined(DBGMCU_CR_DBG_TIM17_STOP)
150 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_CR_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */
151 #endif /* DBGMCU_CR_DBG_TIM17_STOP */
152 /**
153 * @}
154 */
155
156 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
157 * @{
158 */
159 #if defined(FLASH_ACR_LATENCY)
160 #define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
161 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
162 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */
163 #else
164 #endif /* FLASH_ACR_LATENCY */
165 /**
166 * @}
167 */
168
169 /**
170 * @}
171 */
172
173 /* Exported macro ------------------------------------------------------------*/
174
175 /* Exported functions --------------------------------------------------------*/
176 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
177 * @{
178 */
179
180
181
182 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
183 * @{
184 */
185
186 /**
187 * @brief Return the device identifier
188 * @note For Low Density devices, the device ID is 0x412
189 * @note For Medium Density devices, the device ID is 0x410
190 * @note For High Density devices, the device ID is 0x414
191 * @note For XL Density devices, the device ID is 0x430
192 * @note For Connectivity Line devices, the device ID is 0x418
193 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
194 * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
195 */
LL_DBGMCU_GetDeviceID(void)196 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
197 {
198 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
199 }
200
201 /**
202 * @brief Return the device revision identifier
203 * @note This field indicates the revision of the device.
204 For example, it is read as revA -> 0x1000,for Low Density devices
205 For example, it is read as revA -> 0x0000, revB -> 0x2000, revZ -> 0x2001, rev1,2,3,X or Y -> 0x2003,for Medium Density devices
206 For example, it is read as revA or 1 -> 0x1000, revZ -> 0x1001,rev1,2,3,X or Y -> 0x1003,for Medium Density devices
207 For example, it is read as revA or 1 -> 0x1003,for XL Density devices
208 For example, it is read as revA -> 0x1000, revZ -> 0x1001 for Connectivity line devices
209 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
210 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
211 */
LL_DBGMCU_GetRevisionID(void)212 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
213 {
214 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
215 }
216
217 /**
218 * @brief Enable the Debug Module during SLEEP mode
219 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
220 * @retval None
221 */
LL_DBGMCU_EnableDBGSleepMode(void)222 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
223 {
224 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
225 }
226
227 /**
228 * @brief Disable the Debug Module during SLEEP mode
229 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
230 * @retval None
231 */
LL_DBGMCU_DisableDBGSleepMode(void)232 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
233 {
234 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
235 }
236
237 /**
238 * @brief Enable the Debug Module during STOP mode
239 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
240 * @retval None
241 */
LL_DBGMCU_EnableDBGStopMode(void)242 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
243 {
244 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
245 }
246
247 /**
248 * @brief Disable the Debug Module during STOP mode
249 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
250 * @retval None
251 */
LL_DBGMCU_DisableDBGStopMode(void)252 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
253 {
254 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
255 }
256
257 /**
258 * @brief Enable the Debug Module during STANDBY mode
259 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
260 * @retval None
261 */
LL_DBGMCU_EnableDBGStandbyMode(void)262 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
263 {
264 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
265 }
266
267 /**
268 * @brief Disable the Debug Module during STANDBY mode
269 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
270 * @retval None
271 */
LL_DBGMCU_DisableDBGStandbyMode(void)272 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
273 {
274 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
275 }
276
277 /**
278 * @brief Set Trace pin assignment control
279 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
280 * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
281 * @param PinAssignment This parameter can be one of the following values:
282 * @arg @ref LL_DBGMCU_TRACE_NONE
283 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
284 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
285 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
286 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
287 * @retval None
288 */
LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)289 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
290 {
291 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
292 }
293
294 /**
295 * @brief Get Trace pin assignment control
296 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
297 * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
298 * @retval Returned value can be one of the following values:
299 * @arg @ref LL_DBGMCU_TRACE_NONE
300 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
301 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
302 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
303 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
304 */
LL_DBGMCU_GetTracePinAssignment(void)305 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
306 {
307 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
308 }
309
310 /**
311 * @brief Freeze APB1 peripherals (group1 peripherals)
312 * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
313 * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
314 * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
315 * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
316 * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
317 * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
318 * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
319 * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
320 * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
321 * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
322 * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
323 * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
324 * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
325 * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
326 * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
327 * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
328 * @param Periphs This parameter can be a combination of the following values:
329 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
330 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
331 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
332 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
333 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
334 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
335 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
336 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
337 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
338 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
339 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
340 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
341 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
342 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
343 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
344 *
345 * (*) value not defined in all devices.
346 * @retval None
347 */
LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)348 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
349 {
350 SET_BIT(DBGMCU->CR, Periphs);
351 }
352
353 /**
354 * @brief Unfreeze APB1 peripherals (group1 peripherals)
355 * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
356 * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
357 * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
358 * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
359 * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
360 * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
361 * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
362 * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
363 * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
364 * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
365 * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
366 * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
367 * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
368 * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
369 * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
370 * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
371 * @param Periphs This parameter can be a combination of the following values:
372 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
373 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
374 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
375 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
376 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
377 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
378 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
379 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
380 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
381 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
382 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
383 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
384 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
385 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
386 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
387 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
388 *
389 * (*) value not defined in all devices.
390 * @retval None
391 */
LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)392 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
393 {
394 CLEAR_BIT(DBGMCU->CR, Periphs);
395 }
396
397 /**
398 * @brief Freeze APB2 peripherals
399 * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
400 * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
401 * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
402 * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
403 * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
404 * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
405 * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
406 * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
407 * @param Periphs This parameter can be a combination of the following values:
408 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
409 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
410 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
411 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
412 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
413 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
414 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
415 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
416 *
417 * (*) value not defined in all devices.
418 * @retval None
419 */
LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)420 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
421 {
422 SET_BIT(DBGMCU->CR, Periphs);
423 }
424
425 /**
426 * @brief Unfreeze APB2 peripherals
427 * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
428 * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
429 * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
430 * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
431 * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
432 * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
433 * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
434 * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
435 * @param Periphs This parameter can be a combination of the following values:
436 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
437 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
438 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
439 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
440 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
441 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
442 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
443 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
444 *
445 * (*) value not defined in all devices.
446 * @retval None
447 */
LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)448 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
449 {
450 CLEAR_BIT(DBGMCU->CR, Periphs);
451 }
452 /**
453 * @}
454 */
455
456 #if defined(FLASH_ACR_LATENCY)
457 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
458 * @{
459 */
460
461 /**
462 * @brief Set FLASH Latency
463 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
464 * @param Latency This parameter can be one of the following values:
465 * @arg @ref LL_FLASH_LATENCY_0
466 * @arg @ref LL_FLASH_LATENCY_1
467 * @arg @ref LL_FLASH_LATENCY_2
468 * @retval None
469 */
LL_FLASH_SetLatency(uint32_t Latency)470 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
471 {
472 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
473 }
474
475 /**
476 * @brief Get FLASH Latency
477 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
478 * @retval Returned value can be one of the following values:
479 * @arg @ref LL_FLASH_LATENCY_0
480 * @arg @ref LL_FLASH_LATENCY_1
481 * @arg @ref LL_FLASH_LATENCY_2
482 */
LL_FLASH_GetLatency(void)483 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
484 {
485 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
486 }
487
488 /**
489 * @brief Enable Prefetch
490 * @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch
491 * @retval None
492 */
LL_FLASH_EnablePrefetch(void)493 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
494 {
495 SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
496 }
497
498 /**
499 * @brief Disable Prefetch
500 * @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch
501 * @retval None
502 */
LL_FLASH_DisablePrefetch(void)503 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
504 {
505 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
506 }
507
508 /**
509 * @brief Check if Prefetch buffer is enabled
510 * @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled
511 * @retval State of bit (1 or 0).
512 */
LL_FLASH_IsPrefetchEnabled(void)513 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
514 {
515 return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS));
516 }
517
518 #endif /* FLASH_ACR_LATENCY */
519 /**
520 * @brief Enable Flash Half Cycle Access
521 * @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess
522 * @retval None
523 */
LL_FLASH_EnableHalfCycleAccess(void)524 __STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void)
525 {
526 SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
527 }
528
529 /**
530 * @brief Disable Flash Half Cycle Access
531 * @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess
532 * @retval None
533 */
LL_FLASH_DisableHalfCycleAccess(void)534 __STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void)
535 {
536 CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
537 }
538
539 /**
540 * @brief Check if Flash Half Cycle Access is enabled or not
541 * @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled
542 * @retval State of bit (1 or 0).
543 */
LL_FLASH_IsHalfCycleAccessEnabled(void)544 __STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void)
545 {
546 return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA));
547 }
548
549
550 /**
551 * @}
552 */
553
554 /**
555 * @}
556 */
557
558 /**
559 * @}
560 */
561
562 #endif /* defined (FLASH) || defined (DBGMCU) */
563
564 /**
565 * @}
566 */
567
568 #ifdef __cplusplus
569 }
570 #endif
571
572 #endif /* __STM32F1xx_LL_SYSTEM_H */
573
574 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
575
