1 /** 2 ****************************************************************************** 3 * @file stm32_hal_legacy.h 4 * @author MCD Application Team 5 * @brief This file contains aliases definition for the STM32Cube HAL constants 6 * macros and functions maintained for legacy purpose. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef STM32_HAL_LEGACY 23 #define STM32_HAL_LEGACY 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 /* Exported types ------------------------------------------------------------*/ 31 /* Exported constants --------------------------------------------------------*/ 32 33 /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose 34 * @{ 35 */ 36 #define AES_FLAG_RDERR CRYP_FLAG_RDERR 37 #define AES_FLAG_WRERR CRYP_FLAG_WRERR 38 #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF 39 #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR 40 #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR 41 #if defined(STM32U5) 42 #define CRYP_DATATYPE_32B CRYP_NO_SWAP 43 #define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP 44 #define CRYP_DATATYPE_8B CRYP_BYTE_SWAP 45 #define CRYP_DATATYPE_1B CRYP_BIT_SWAP 46 #define CRYP_CCF_CLEAR CRYP_CLEAR_CCF 47 #define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF 48 #endif /* STM32U5 */ 49 /** 50 * @} 51 */ 52 53 /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose 54 * @{ 55 */ 56 #define ADC_RESOLUTION12b ADC_RESOLUTION_12B 57 #define ADC_RESOLUTION10b ADC_RESOLUTION_10B 58 #define ADC_RESOLUTION8b ADC_RESOLUTION_8B 59 #define ADC_RESOLUTION6b ADC_RESOLUTION_6B 60 #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN 61 #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED 62 #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV 63 #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV 64 #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV 65 #define REGULAR_GROUP ADC_REGULAR_GROUP 66 #define INJECTED_GROUP ADC_INJECTED_GROUP 67 #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP 68 #define AWD_EVENT ADC_AWD_EVENT 69 #define AWD1_EVENT ADC_AWD1_EVENT 70 #define AWD2_EVENT ADC_AWD2_EVENT 71 #define AWD3_EVENT ADC_AWD3_EVENT 72 #define OVR_EVENT ADC_OVR_EVENT 73 #define JQOVF_EVENT ADC_JQOVF_EVENT 74 #define ALL_CHANNELS ADC_ALL_CHANNELS 75 #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS 76 #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS 77 #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR 78 #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT 79 #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 80 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 81 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 82 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 83 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 84 #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO 85 #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 86 #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO 87 #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 88 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO 89 #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 90 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 91 #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE 92 #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING 93 #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING 94 #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING 95 #define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 96 97 #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY 98 #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY 99 #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC 100 #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC 101 #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL 102 #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL 103 #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 104 105 #if defined(STM32H7) 106 #define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT 107 #endif /* STM32H7 */ 108 /** 109 * @} 110 */ 111 112 /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose 113 * @{ 114 */ 115 116 #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG 117 118 /** 119 * @} 120 */ 121 122 /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose 123 * @{ 124 */ 125 #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE 126 #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE 127 #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 128 #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 129 #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 130 #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 131 #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 132 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 133 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 134 #if defined(STM32L0) 135 #define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ 136 #endif 137 #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR 138 #if defined(STM32F373xC) || defined(STM32F378xx) 139 #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 140 #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR 141 #endif /* STM32F373xC || STM32F378xx */ 142 143 #if defined(STM32L0) || defined(STM32L4) 144 #define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON 145 146 #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 147 #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 148 #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 149 #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 150 #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 151 #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 152 153 #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT 154 #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT 155 #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT 156 #define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT 157 #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 158 #define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 159 #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 160 #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 161 #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 162 #if defined(STM32L0) 163 /* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ 164 /* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ 165 /* to the second dedicated IO (only for COMP2). */ 166 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 167 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 168 #else 169 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 170 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 171 #endif 172 #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 173 #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 174 175 #define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW 176 #define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH 177 178 /* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ 179 /* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ 180 #if defined(COMP_CSR_LOCK) 181 #define COMP_FLAG_LOCK COMP_CSR_LOCK 182 #elif defined(COMP_CSR_COMP1LOCK) 183 #define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK 184 #elif defined(COMP_CSR_COMPxLOCK) 185 #define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK 186 #endif 187 188 #if defined(STM32L4) 189 #define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 190 #define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 191 #define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 192 #define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 193 #define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 194 #define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 195 #define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE 196 #endif 197 198 #if defined(STM32L0) 199 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED 200 #define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER 201 #else 202 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED 203 #define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED 204 #define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER 205 #define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER 206 #endif 207 208 #endif 209 /** 210 * @} 211 */ 212 213 /** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose 214 * @{ 215 */ 216 #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig 217 /** 218 * @} 219 */ 220 221 /** @defgroup CRC_Aliases CRC API aliases 222 * @{ 223 */ 224 #if defined(STM32WL) || defined(STM32WB) || defined(STM32L5) || defined(STM32L4) 225 #else 226 #define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ 227 #define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ 228 #endif 229 /** 230 * @} 231 */ 232 233 /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose 234 * @{ 235 */ 236 237 #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE 238 #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE 239 240 /** 241 * @} 242 */ 243 244 /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose 245 * @{ 246 */ 247 248 #define DAC1_CHANNEL_1 DAC_CHANNEL_1 249 #define DAC1_CHANNEL_2 DAC_CHANNEL_2 250 #define DAC2_CHANNEL_1 DAC_CHANNEL_1 251 #define DAC_WAVE_NONE 0x00000000U 252 #define DAC_WAVE_NOISE DAC_CR_WAVE1_0 253 #define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 254 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE 255 #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE 256 #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE 257 258 #if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) 259 #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL 260 #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL 261 #endif 262 263 #if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) 264 #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID 265 #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID 266 #endif 267 268 /** 269 * @} 270 */ 271 272 /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose 273 * @{ 274 */ 275 #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 276 #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 277 #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 278 #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 279 #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 280 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 281 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 282 #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 283 #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 284 #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 285 #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 286 #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 287 #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 288 #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 289 290 #define IS_HAL_REMAPDMA IS_DMA_REMAP 291 #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE 292 #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE 293 294 #if defined(STM32L4) 295 296 #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 297 #define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 298 #define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 299 #define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 300 #define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 301 #define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 302 #define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 303 #define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 304 #define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 305 #define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 306 #define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 307 #define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 308 #define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 309 #define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 310 #define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 311 #define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 312 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 313 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 314 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 315 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT 316 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 317 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 318 #define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE 319 #define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT 320 #define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT 321 #define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT 322 323 #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT 324 #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING 325 #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING 326 #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING 327 328 #if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 329 #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI 330 #endif 331 332 #endif /* STM32L4 */ 333 334 #if defined(STM32G0) 335 #define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 336 #define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 337 #define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM 338 #define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM 339 340 #define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM 341 #define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM 342 #endif 343 344 #if defined(STM32H7) 345 346 #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 347 #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 348 349 #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX 350 #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX 351 352 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 353 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 354 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 355 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 356 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 357 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT 358 #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 359 #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO 360 361 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 362 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 363 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 364 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 365 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 366 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 367 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 368 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 369 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 370 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 371 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT 372 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 373 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT 374 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 375 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 376 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP 377 #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP 378 #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT 379 #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT 380 #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP 381 #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 382 #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 383 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 384 #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT 385 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 386 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 387 #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT 388 #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 389 #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 390 #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 391 392 #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT 393 #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING 394 #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING 395 #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING 396 397 #define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT 398 #define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT 399 #define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT 400 401 #define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT 402 #define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT 403 404 #endif /* STM32H7 */ 405 /** 406 * @} 407 */ 408 409 /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose 410 * @{ 411 */ 412 413 #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE 414 #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD 415 #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD 416 #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD 417 #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS 418 #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES 419 #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES 420 #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE 421 #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE 422 #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE 423 #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE 424 #define OBEX_PCROP OPTIONBYTE_PCROP 425 #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG 426 #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE 427 #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE 428 #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE 429 #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD 430 #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD 431 #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE 432 #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD 433 #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD 434 #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE 435 #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD 436 #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD 437 #define PAGESIZE FLASH_PAGE_SIZE 438 #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE 439 #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD 440 #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD 441 #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 442 #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 443 #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 444 #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 445 #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST 446 #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST 447 #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA 448 #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB 449 #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA 450 #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB 451 #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE 452 #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN 453 #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE 454 #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN 455 #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE 456 #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD 457 #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG 458 #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS 459 #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP 460 #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV 461 #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR 462 #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG 463 #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION 464 #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA 465 #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE 466 #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE 467 #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS 468 #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS 469 #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST 470 #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR 471 #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO 472 #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION 473 #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS 474 #define OB_WDG_SW OB_IWDG_SW 475 #define OB_WDG_HW OB_IWDG_HW 476 #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET 477 #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET 478 #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET 479 #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET 480 #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR 481 #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 482 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 483 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 484 #if defined(STM32G0) 485 #define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE 486 #define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH 487 #else 488 #define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE 489 #define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE 490 #endif 491 #if defined(STM32H7) 492 #define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 493 #define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 494 #define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 495 #define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 496 #define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 497 #define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 498 #define FLASH_FLAG_WDW FLASH_FLAG_WBNE 499 #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL 500 #endif /* STM32H7 */ 501 #if defined(STM32U5) 502 #define OB_USER_nRST_STOP OB_USER_NRST_STOP 503 #define OB_USER_nRST_STDBY OB_USER_NRST_STDBY 504 #define OB_USER_nRST_SHDW OB_USER_NRST_SHDW 505 #define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 506 #define OB_USER_nBOOT0 OB_USER_NBOOT0 507 #define OB_nBOOT0_RESET OB_NBOOT0_RESET 508 #define OB_nBOOT0_SET OB_NBOOT0_SET 509 #endif /* STM32U5 */ 510 511 /** 512 * @} 513 */ 514 515 /** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose 516 * @{ 517 */ 518 519 #if defined(STM32H7) 520 #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE 521 #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE 522 #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET 523 #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET 524 #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE 525 #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE 526 #endif /* STM32H7 */ 527 528 /** 529 * @} 530 */ 531 532 /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose 533 * @{ 534 */ 535 536 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 537 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 538 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 539 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 540 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 541 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 542 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 543 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 544 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 545 #if defined(STM32G4) 546 547 #define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster 548 #define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster 549 #define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD 550 #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD 551 #endif /* STM32G4 */ 552 553 /** 554 * @} 555 */ 556 557 558 /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose 559 * @{ 560 */ 561 #if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) 562 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE 563 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE 564 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 565 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 566 #elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) 567 #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE 568 #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE 569 #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 570 #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 571 #endif 572 /** 573 * @} 574 */ 575 576 /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose 577 * @{ 578 */ 579 580 #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef 581 #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef 582 /** 583 * @} 584 */ 585 586 /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose 587 * @{ 588 */ 589 #define GET_GPIO_SOURCE GPIO_GET_INDEX 590 #define GET_GPIO_INDEX GPIO_GET_INDEX 591 592 #if defined(STM32F4) 593 #define GPIO_AF12_SDMMC GPIO_AF12_SDIO 594 #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO 595 #endif 596 597 #if defined(STM32F7) 598 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 599 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 600 #endif 601 602 #if defined(STM32L4) 603 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 604 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 605 #endif 606 607 #if defined(STM32H7) 608 #define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 609 #define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 610 #define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 611 #define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 612 #define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 613 #define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 614 615 #if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ 616 defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) 617 #define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS 618 #define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS 619 #define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS 620 #endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ 621 #endif /* STM32H7 */ 622 623 #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 624 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 625 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 626 627 #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) 628 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW 629 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM 630 #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH 631 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH 632 #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/ 633 634 #if defined(STM32L1) 635 #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW 636 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM 637 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH 638 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH 639 #endif /* STM32L1 */ 640 641 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) 642 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW 643 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM 644 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH 645 #endif /* STM32F0 || STM32F3 || STM32F1 */ 646 647 #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 648 /** 649 * @} 650 */ 651 652 /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose 653 * @{ 654 */ 655 #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED 656 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 657 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 658 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 659 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 660 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 661 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 662 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 663 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 664 665 #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER 666 #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER 667 #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD 668 #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD 669 #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER 670 #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER 671 #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE 672 #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE 673 674 #if defined(STM32G4) 675 #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig 676 #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable 677 #define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable 678 #define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset 679 #define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A 680 #define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B 681 #define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL 682 #define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL 683 #endif /* STM32G4 */ 684 685 #if defined(STM32H7) 686 #define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 687 #define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 688 #define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 689 #define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 690 #define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 691 #define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 692 #define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 693 #define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 694 #define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 695 #define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 696 #define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 697 #define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 698 #define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 699 #define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 700 #define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 701 #define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 702 #define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 703 #define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 704 #define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 705 #define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 706 #define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 707 #define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 708 #define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 709 #define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 710 #define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 711 #define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 712 #define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 713 #define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 714 #define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 715 #define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 716 #define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 717 #define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 718 #define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 719 #define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 720 #define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 721 #define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 722 #define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 723 #define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 724 #define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 725 #define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 726 #define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 727 #define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 728 #define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 729 #define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 730 #define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 731 #define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 732 #define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 733 #define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 734 #define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 735 #define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 736 #define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 737 #define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 738 #define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 739 #define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 740 741 #define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 742 #define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 743 #define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 744 #define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 745 #define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 746 #define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 747 #define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 748 #define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 749 #define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 750 #define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 751 #define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 752 #define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 753 #define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 754 #define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 755 #define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 756 #define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 757 #define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 758 #define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 759 #define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 760 #define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 761 #define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 762 #define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 763 #define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 764 #define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 765 #define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 766 #define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 767 #define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 768 #define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 769 #define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 770 #define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 771 #define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 772 #define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 773 #define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 774 #define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 775 #define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 776 #define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 777 #define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 778 #define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 779 #define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 780 #define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 781 #define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 782 #define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 783 #define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 784 #define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 785 #define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 786 #define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 787 #define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 788 #define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 789 #define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 790 #define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 791 #define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 792 #define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 793 #define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 794 #define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 795 #endif /* STM32H7 */ 796 797 #if defined(STM32F3) 798 /** @brief Constants defining available sources associated to external events. 799 */ 800 #define HRTIM_EVENTSRC_1 (0x00000000U) 801 #define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) 802 #define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) 803 #define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) 804 805 /** @brief Constants defining the DLL calibration periods (in micro seconds) 806 */ 807 #define HRTIM_CALIBRATIONRATE_7300 0x00000000U 808 #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) 809 #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) 810 #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) 811 812 #endif /* STM32F3 */ 813 /** 814 * @} 815 */ 816 817 /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose 818 * @{ 819 */ 820 #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE 821 #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE 822 #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE 823 #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE 824 #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE 825 #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE 826 #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE 827 #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE 828 #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) 829 #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX 830 #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX 831 #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX 832 #define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX 833 #define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX 834 #define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX 835 #endif 836 /** 837 * @} 838 */ 839 840 /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose 841 * @{ 842 */ 843 #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE 844 #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE 845 846 /** 847 * @} 848 */ 849 850 /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose 851 * @{ 852 */ 853 #define KR_KEY_RELOAD IWDG_KEY_RELOAD 854 #define KR_KEY_ENABLE IWDG_KEY_ENABLE 855 #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE 856 #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE 857 /** 858 * @} 859 */ 860 861 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose 862 * @{ 863 */ 864 865 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 866 #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS 867 #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS 868 #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS 869 870 #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING 871 #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING 872 #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING 873 874 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 875 #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS 876 #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS 877 #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS 878 879 /* The following 3 definition have also been present in a temporary version of lptim.h */ 880 /* They need to be renamed also to the right name, just in case */ 881 #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS 882 #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS 883 #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS 884 885 #if defined(STM32U5) 886 #define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF 887 #define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF 888 #endif /* STM32U5 */ 889 /** 890 * @} 891 */ 892 893 /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose 894 * @{ 895 */ 896 #define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b 897 #define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b 898 #define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b 899 #define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b 900 901 #define NAND_AddressTypedef NAND_AddressTypeDef 902 903 #define __ARRAY_ADDRESS ARRAY_ADDRESS 904 #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE 905 #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE 906 #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE 907 #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE 908 /** 909 * @} 910 */ 911 912 /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose 913 * @{ 914 */ 915 #define NOR_StatusTypedef HAL_NOR_StatusTypeDef 916 #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS 917 #define NOR_ONGOING HAL_NOR_STATUS_ONGOING 918 #define NOR_ERROR HAL_NOR_STATUS_ERROR 919 #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT 920 921 #define __NOR_WRITE NOR_WRITE 922 #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT 923 /** 924 * @} 925 */ 926 927 /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose 928 * @{ 929 */ 930 931 #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 932 #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 933 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 934 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 935 936 #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 937 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 938 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 939 #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 940 941 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 942 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 943 944 #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 945 #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 946 947 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 948 #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 949 950 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 951 952 #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO 953 #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 954 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 955 956 #if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) 957 #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID 958 #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID 959 #endif 960 961 #if defined(STM32L4) || defined(STM32L5) 962 #define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER 963 #elif defined(STM32G4) 964 #define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED 965 #endif 966 967 /** 968 * @} 969 */ 970 971 /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose 972 * @{ 973 */ 974 #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS 975 976 #if defined(STM32H7) 977 #define I2S_IT_TXE I2S_IT_TXP 978 #define I2S_IT_RXNE I2S_IT_RXP 979 980 #define I2S_FLAG_TXE I2S_FLAG_TXP 981 #define I2S_FLAG_RXNE I2S_FLAG_RXP 982 #endif 983 984 #if defined(STM32F7) 985 #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL 986 #endif 987 /** 988 * @} 989 */ 990 991 /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose 992 * @{ 993 */ 994 995 /* Compact Flash-ATA registers description */ 996 #define CF_DATA ATA_DATA 997 #define CF_SECTOR_COUNT ATA_SECTOR_COUNT 998 #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER 999 #define CF_CYLINDER_LOW ATA_CYLINDER_LOW 1000 #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH 1001 #define CF_CARD_HEAD ATA_CARD_HEAD 1002 #define CF_STATUS_CMD ATA_STATUS_CMD 1003 #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE 1004 #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA 1005 1006 /* Compact Flash-ATA commands */ 1007 #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD 1008 #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD 1009 #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD 1010 #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD 1011 1012 #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef 1013 #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS 1014 #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING 1015 #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR 1016 #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT 1017 /** 1018 * @} 1019 */ 1020 1021 /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose 1022 * @{ 1023 */ 1024 1025 #define FORMAT_BIN RTC_FORMAT_BIN 1026 #define FORMAT_BCD RTC_FORMAT_BCD 1027 1028 #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE 1029 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE 1030 #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 1031 #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 1032 1033 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 1034 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 1035 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE 1036 #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT 1037 #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT 1038 1039 #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT 1040 #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 1041 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 1042 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 1043 1044 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE 1045 #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 1046 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 1047 1048 #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT 1049 #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 1050 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 1051 1052 #if defined(STM32H7) 1053 #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X 1054 #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT 1055 1056 #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 1057 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 1058 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 1059 #define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL 1060 #endif /* STM32H7 */ 1061 1062 /** 1063 * @} 1064 */ 1065 1066 1067 /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose 1068 * @{ 1069 */ 1070 #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE 1071 #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE 1072 1073 #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE 1074 #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE 1075 #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE 1076 #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE 1077 1078 #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE 1079 #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE 1080 1081 #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE 1082 #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE 1083 /** 1084 * @} 1085 */ 1086 1087 1088 /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose 1089 * @{ 1090 */ 1091 #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE 1092 #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE 1093 #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE 1094 #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE 1095 #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE 1096 #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE 1097 #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE 1098 #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE 1099 #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE 1100 #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE 1101 #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN 1102 /** 1103 * @} 1104 */ 1105 1106 /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose 1107 * @{ 1108 */ 1109 #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE 1110 #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE 1111 1112 #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE 1113 #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE 1114 1115 #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE 1116 #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE 1117 1118 #if defined(STM32H7) 1119 1120 #define SPI_FLAG_TXE SPI_FLAG_TXP 1121 #define SPI_FLAG_RXNE SPI_FLAG_RXP 1122 1123 #define SPI_IT_TXE SPI_IT_TXP 1124 #define SPI_IT_RXNE SPI_IT_RXP 1125 1126 #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET 1127 #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET 1128 #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET 1129 #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET 1130 1131 #endif /* STM32H7 */ 1132 1133 /** 1134 * @} 1135 */ 1136 1137 /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose 1138 * @{ 1139 */ 1140 #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK 1141 #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK 1142 1143 #define TIM_DMABase_CR1 TIM_DMABASE_CR1 1144 #define TIM_DMABase_CR2 TIM_DMABASE_CR2 1145 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR 1146 #define TIM_DMABase_DIER TIM_DMABASE_DIER 1147 #define TIM_DMABase_SR TIM_DMABASE_SR 1148 #define TIM_DMABase_EGR TIM_DMABASE_EGR 1149 #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 1150 #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 1151 #define TIM_DMABase_CCER TIM_DMABASE_CCER 1152 #define TIM_DMABase_CNT TIM_DMABASE_CNT 1153 #define TIM_DMABase_PSC TIM_DMABASE_PSC 1154 #define TIM_DMABase_ARR TIM_DMABASE_ARR 1155 #define TIM_DMABase_RCR TIM_DMABASE_RCR 1156 #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 1157 #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 1158 #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 1159 #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 1160 #define TIM_DMABase_BDTR TIM_DMABASE_BDTR 1161 #define TIM_DMABase_DCR TIM_DMABASE_DCR 1162 #define TIM_DMABase_DMAR TIM_DMABASE_DMAR 1163 #define TIM_DMABase_OR1 TIM_DMABASE_OR1 1164 #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 1165 #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 1166 #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 1167 #define TIM_DMABase_OR2 TIM_DMABASE_OR2 1168 #define TIM_DMABase_OR3 TIM_DMABASE_OR3 1169 #define TIM_DMABase_OR TIM_DMABASE_OR 1170 1171 #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE 1172 #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 1173 #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 1174 #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 1175 #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 1176 #define TIM_EventSource_COM TIM_EVENTSOURCE_COM 1177 #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER 1178 #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK 1179 #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 1180 1181 #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER 1182 #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS 1183 #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS 1184 #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS 1185 #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS 1186 #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS 1187 #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS 1188 #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS 1189 #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS 1190 #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS 1191 #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS 1192 #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS 1193 #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS 1194 #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS 1195 #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS 1196 #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS 1197 #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS 1198 #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS 1199 1200 #if defined(STM32L0) 1201 #define TIM22_TI1_GPIO1 TIM22_TI1_GPIO 1202 #define TIM22_TI1_GPIO2 TIM22_TI1_GPIO 1203 #endif 1204 1205 #if defined(STM32F3) 1206 #define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE 1207 #endif 1208 1209 #if defined(STM32H7) 1210 #define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 1211 #define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 1212 #define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 1213 #define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 1214 #define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 1215 #define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 1216 #define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 1217 #define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 1218 #define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 1219 #define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 1220 #define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 1221 #define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 1222 #define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 1223 #define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 1224 #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 1225 #endif 1226 1227 /** 1228 * @} 1229 */ 1230 1231 /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose 1232 * @{ 1233 */ 1234 #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING 1235 #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING 1236 /** 1237 * @} 1238 */ 1239 1240 /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose 1241 * @{ 1242 */ 1243 #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE 1244 #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE 1245 #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE 1246 #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE 1247 1248 #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE 1249 #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE 1250 1251 #define __DIV_SAMPLING16 UART_DIV_SAMPLING16 1252 #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 1253 #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 1254 #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 1255 1256 #define __DIV_SAMPLING8 UART_DIV_SAMPLING8 1257 #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 1258 #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 1259 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 1260 1261 #define __DIV_LPUART UART_DIV_LPUART 1262 1263 #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE 1264 #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK 1265 1266 /** 1267 * @} 1268 */ 1269 1270 1271 /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose 1272 * @{ 1273 */ 1274 1275 #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE 1276 #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE 1277 1278 #define USARTNACK_ENABLED USART_NACK_ENABLE 1279 #define USARTNACK_DISABLED USART_NACK_DISABLE 1280 /** 1281 * @} 1282 */ 1283 1284 /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose 1285 * @{ 1286 */ 1287 #define CFR_BASE WWDG_CFR_BASE 1288 1289 /** 1290 * @} 1291 */ 1292 1293 /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose 1294 * @{ 1295 */ 1296 #define CAN_FilterFIFO0 CAN_FILTER_FIFO0 1297 #define CAN_FilterFIFO1 CAN_FILTER_FIFO1 1298 #define CAN_IT_RQCP0 CAN_IT_TME 1299 #define CAN_IT_RQCP1 CAN_IT_TME 1300 #define CAN_IT_RQCP2 CAN_IT_TME 1301 #define INAK_TIMEOUT CAN_TIMEOUT_VALUE 1302 #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE 1303 #define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) 1304 #define CAN_TXSTATUS_OK ((uint8_t)0x01U) 1305 #define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) 1306 1307 /** 1308 * @} 1309 */ 1310 1311 /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose 1312 * @{ 1313 */ 1314 1315 #define VLAN_TAG ETH_VLAN_TAG 1316 #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD 1317 #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD 1318 #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD 1319 #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK 1320 #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK 1321 #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK 1322 #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK 1323 1324 #define ETH_MMCCR 0x00000100U 1325 #define ETH_MMCRIR 0x00000104U 1326 #define ETH_MMCTIR 0x00000108U 1327 #define ETH_MMCRIMR 0x0000010CU 1328 #define ETH_MMCTIMR 0x00000110U 1329 #define ETH_MMCTGFSCCR 0x0000014CU 1330 #define ETH_MMCTGFMSCCR 0x00000150U 1331 #define ETH_MMCTGFCR 0x00000168U 1332 #define ETH_MMCRFCECR 0x00000194U 1333 #define ETH_MMCRFAECR 0x00000198U 1334 #define ETH_MMCRGUFCR 0x000001C4U 1335 1336 #define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ 1337 #define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ 1338 #define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ 1339 #define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ 1340 #define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ 1341 #define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ 1342 #define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ 1343 #define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ 1344 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ 1345 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ 1346 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ 1347 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ 1348 #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ 1349 #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ 1350 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ 1351 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ 1352 #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ 1353 #if defined(STM32F1) 1354 #else 1355 #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ 1356 #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ 1357 #define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ 1358 #endif 1359 #define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ 1360 #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ 1361 #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ 1362 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ 1363 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ 1364 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ 1365 #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ 1366 1367 /** 1368 * @} 1369 */ 1370 1371 /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose 1372 * @{ 1373 */ 1374 #define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR 1375 #define DCMI_IT_OVF DCMI_IT_OVR 1376 #define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI 1377 #define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI 1378 1379 #define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop 1380 #define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop 1381 #define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop 1382 1383 /** 1384 * @} 1385 */ 1386 1387 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ 1388 || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ 1389 || defined(STM32H7) 1390 /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose 1391 * @{ 1392 */ 1393 #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 1394 #define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 1395 #define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 1396 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 1397 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 1398 1399 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888 1400 #define CM_RGB888 DMA2D_INPUT_RGB888 1401 #define CM_RGB565 DMA2D_INPUT_RGB565 1402 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555 1403 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444 1404 #define CM_L8 DMA2D_INPUT_L8 1405 #define CM_AL44 DMA2D_INPUT_AL44 1406 #define CM_AL88 DMA2D_INPUT_AL88 1407 #define CM_L4 DMA2D_INPUT_L4 1408 #define CM_A8 DMA2D_INPUT_A8 1409 #define CM_A4 DMA2D_INPUT_A4 1410 /** 1411 * @} 1412 */ 1413 #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ 1414 1415 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ 1416 || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ 1417 || defined(STM32H7) || defined(STM32U5) 1418 /** @defgroup DMA2D_Aliases DMA2D API Aliases 1419 * @{ 1420 */ 1421 #define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort 1422 for compatibility with legacy code */ 1423 /** 1424 * @} 1425 */ 1426 1427 #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ 1428 1429 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose 1430 * @{ 1431 */ 1432 1433 /** 1434 * @} 1435 */ 1436 1437 /* Exported functions --------------------------------------------------------*/ 1438 1439 /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose 1440 * @{ 1441 */ 1442 #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback 1443 /** 1444 * @} 1445 */ 1446 1447 #if !defined(STM32F2) 1448 /** @defgroup HASH_alias HASH API alias 1449 * @{ 1450 */ 1451 #define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ 1452 /** 1453 * 1454 * @} 1455 */ 1456 #endif /* STM32F2 */ 1457 /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose 1458 * @{ 1459 */ 1460 #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef 1461 #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef 1462 #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish 1463 #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish 1464 #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish 1465 #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish 1466 1467 /*HASH Algorithm Selection*/ 1468 1469 #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 1470 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 1471 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 1472 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 1473 1474 #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH 1475 #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC 1476 1477 #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY 1478 #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY 1479 1480 #if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) 1481 1482 #define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt 1483 #define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End 1484 #define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT 1485 #define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT 1486 1487 #define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt 1488 #define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End 1489 #define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT 1490 #define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT 1491 1492 #define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt 1493 #define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End 1494 #define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT 1495 #define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT 1496 1497 #define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt 1498 #define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End 1499 #define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT 1500 #define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT 1501 1502 #endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ 1503 /** 1504 * @} 1505 */ 1506 1507 /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose 1508 * @{ 1509 */ 1510 #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode 1511 #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode 1512 #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode 1513 #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode 1514 #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode 1515 #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode 1516 #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ 1517 )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) 1518 #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect 1519 #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) 1520 #if defined(STM32L0) 1521 #else 1522 #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) 1523 #endif 1524 #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) 1525 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ 1526 )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) 1527 #if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) 1528 #define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode 1529 #define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode 1530 #define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode 1531 #define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode 1532 #endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ 1533 1534 /** 1535 * @} 1536 */ 1537 1538 /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose 1539 * @{ 1540 */ 1541 #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram 1542 #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown 1543 #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown 1544 #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock 1545 #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock 1546 #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase 1547 #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program 1548 1549 /** 1550 * @} 1551 */ 1552 1553 /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose 1554 * @{ 1555 */ 1556 #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter 1557 #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter 1558 #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter 1559 #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter 1560 1561 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\ 1562 )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) 1563 1564 #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) 1565 #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT 1566 #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT 1567 #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT 1568 #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT 1569 #endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ 1570 #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) 1571 #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA 1572 #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA 1573 #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA 1574 #define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA 1575 #endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ 1576 1577 #if defined(STM32F4) 1578 #define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT 1579 #define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT 1580 #define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT 1581 #define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT 1582 #define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA 1583 #define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA 1584 #define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA 1585 #define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA 1586 #endif /* STM32F4 */ 1587 /** 1588 * @} 1589 */ 1590 1591 /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose 1592 * @{ 1593 */ 1594 1595 #if defined(STM32G0) 1596 #define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD 1597 #define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD 1598 #define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD 1599 #define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler 1600 #endif 1601 #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD 1602 #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg 1603 #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown 1604 #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor 1605 #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg 1606 #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown 1607 #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor 1608 #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler 1609 #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD 1610 #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler 1611 #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback 1612 #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive 1613 #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive 1614 #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC 1615 #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC 1616 #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM 1617 1618 #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL 1619 #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING 1620 #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING 1621 #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING 1622 #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING 1623 #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING 1624 #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING 1625 1626 #define CR_OFFSET_BB PWR_CR_OFFSET_BB 1627 #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB 1628 #define PMODE_BIT_NUMBER VOS_BIT_NUMBER 1629 #define CR_PMODE_BB CR_VOS_BB 1630 1631 #define DBP_BitNumber DBP_BIT_NUMBER 1632 #define PVDE_BitNumber PVDE_BIT_NUMBER 1633 #define PMODE_BitNumber PMODE_BIT_NUMBER 1634 #define EWUP_BitNumber EWUP_BIT_NUMBER 1635 #define FPDS_BitNumber FPDS_BIT_NUMBER 1636 #define ODEN_BitNumber ODEN_BIT_NUMBER 1637 #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER 1638 #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER 1639 #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER 1640 #define BRE_BitNumber BRE_BIT_NUMBER 1641 1642 #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL 1643 1644 /** 1645 * @} 1646 */ 1647 1648 /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose 1649 * @{ 1650 */ 1651 #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT 1652 #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback 1653 #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback 1654 /** 1655 * @} 1656 */ 1657 1658 /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose 1659 * @{ 1660 */ 1661 #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo 1662 /** 1663 * @} 1664 */ 1665 1666 /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose 1667 * @{ 1668 */ 1669 #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt 1670 #define HAL_TIM_DMAError TIM_DMAError 1671 #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt 1672 #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt 1673 #if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) 1674 #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro 1675 #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT 1676 #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback 1677 #define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent 1678 #define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT 1679 #define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA 1680 #endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ 1681 /** 1682 * @} 1683 */ 1684 1685 /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose 1686 * @{ 1687 */ 1688 #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback 1689 /** 1690 * @} 1691 */ 1692 1693 /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose 1694 * @{ 1695 */ 1696 #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback 1697 #define HAL_LTDC_Relaod HAL_LTDC_Reload 1698 #define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig 1699 #define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig 1700 /** 1701 * @} 1702 */ 1703 1704 1705 /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose 1706 * @{ 1707 */ 1708 1709 /** 1710 * @} 1711 */ 1712 1713 /* Exported macros ------------------------------------------------------------*/ 1714 1715 /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose 1716 * @{ 1717 */ 1718 #define AES_IT_CC CRYP_IT_CC 1719 #define AES_IT_ERR CRYP_IT_ERR 1720 #define AES_FLAG_CCF CRYP_FLAG_CCF 1721 /** 1722 * @} 1723 */ 1724 1725 /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose 1726 * @{ 1727 */ 1728 #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE 1729 #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH 1730 #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH 1731 #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM 1732 #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC 1733 #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM 1734 #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC 1735 #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI 1736 #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK 1737 #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG 1738 #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG 1739 #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE 1740 #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE 1741 #define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE 1742 1743 #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY 1744 #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 1745 #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS 1746 #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER 1747 #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER 1748 1749 /** 1750 * @} 1751 */ 1752 1753 1754 /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose 1755 * @{ 1756 */ 1757 #define __ADC_ENABLE __HAL_ADC_ENABLE 1758 #define __ADC_DISABLE __HAL_ADC_DISABLE 1759 #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS 1760 #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS 1761 #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE 1762 #define __ADC_IS_ENABLED ADC_IS_ENABLE 1763 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR 1764 #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED 1765 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED 1766 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR 1767 #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED 1768 #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING 1769 #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE 1770 1771 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION 1772 #define __HAL_ADC_JSQR_RK ADC_JSQR_RK 1773 #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT 1774 #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR 1775 #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION 1776 #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE 1777 #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS 1778 #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS 1779 #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM 1780 #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT 1781 #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS 1782 #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN 1783 #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ 1784 #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET 1785 #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET 1786 #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL 1787 #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL 1788 #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET 1789 #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET 1790 #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD 1791 1792 #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION 1793 #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION 1794 #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION 1795 #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER 1796 #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI 1797 #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE 1798 #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE 1799 #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER 1800 #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER 1801 #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE 1802 1803 #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT 1804 #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT 1805 #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL 1806 #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM 1807 #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET 1808 #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE 1809 #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE 1810 #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER 1811 1812 #define __HAL_ADC_SQR1 ADC_SQR1 1813 #define __HAL_ADC_SMPR1 ADC_SMPR1 1814 #define __HAL_ADC_SMPR2 ADC_SMPR2 1815 #define __HAL_ADC_SQR3_RK ADC_SQR3_RK 1816 #define __HAL_ADC_SQR2_RK ADC_SQR2_RK 1817 #define __HAL_ADC_SQR1_RK ADC_SQR1_RK 1818 #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS 1819 #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS 1820 #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV 1821 #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection 1822 #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq 1823 #define __HAL_ADC_JSQR ADC_JSQR 1824 1825 #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL 1826 #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS 1827 #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF 1828 #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT 1829 #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS 1830 #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN 1831 #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR 1832 #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ 1833 1834 /** 1835 * @} 1836 */ 1837 1838 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose 1839 * @{ 1840 */ 1841 #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT 1842 #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT 1843 #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT 1844 #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE 1845 1846 /** 1847 * @} 1848 */ 1849 1850 /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose 1851 * @{ 1852 */ 1853 #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 1854 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 1855 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 1856 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 1857 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 1858 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 1859 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 1860 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 1861 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 1862 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 1863 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 1864 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 1865 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 1866 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 1867 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 1868 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 1869 1870 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 1871 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 1872 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 1873 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 1874 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 1875 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 1876 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 1877 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 1878 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 1879 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 1880 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 1881 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 1882 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 1883 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 1884 1885 1886 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 1887 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 1888 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 1889 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 1890 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 1891 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 1892 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC 1893 #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC 1894 #if defined(STM32H7) 1895 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 1896 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 1897 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 1898 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 1899 #else 1900 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG 1901 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG 1902 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG 1903 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG 1904 #endif /* STM32H7 */ 1905 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT 1906 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT 1907 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT 1908 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT 1909 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT 1910 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT 1911 #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 1912 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 1913 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 1914 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 1915 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 1916 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 1917 1918 /** 1919 * @} 1920 */ 1921 1922 /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose 1923 * @{ 1924 */ 1925 #if defined(STM32F3) 1926 #define COMP_START __HAL_COMP_ENABLE 1927 #define COMP_STOP __HAL_COMP_DISABLE 1928 #define COMP_LOCK __HAL_COMP_LOCK 1929 1930 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 1931 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 1932 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 1933 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) 1934 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 1935 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 1936 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) 1937 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 1938 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 1939 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) 1940 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 1941 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 1942 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) 1943 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 1944 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 1945 __HAL_COMP_COMP6_EXTI_ENABLE_IT()) 1946 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 1947 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 1948 __HAL_COMP_COMP6_EXTI_DISABLE_IT()) 1949 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 1950 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 1951 __HAL_COMP_COMP6_EXTI_GET_FLAG()) 1952 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 1953 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 1954 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) 1955 # endif 1956 # if defined(STM32F302xE) || defined(STM32F302xC) 1957 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 1958 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 1959 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 1960 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) 1961 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 1962 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 1963 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 1964 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) 1965 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 1966 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 1967 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 1968 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) 1969 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 1970 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 1971 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 1972 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) 1973 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 1974 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 1975 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 1976 __HAL_COMP_COMP6_EXTI_ENABLE_IT()) 1977 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 1978 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 1979 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 1980 __HAL_COMP_COMP6_EXTI_DISABLE_IT()) 1981 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 1982 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 1983 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 1984 __HAL_COMP_COMP6_EXTI_GET_FLAG()) 1985 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 1986 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 1987 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 1988 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) 1989 # endif 1990 # if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) 1991 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 1992 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 1993 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ 1994 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 1995 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ 1996 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ 1997 __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) 1998 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 1999 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 2000 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ 2001 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 2002 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ 2003 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ 2004 __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) 2005 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2006 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 2007 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ 2008 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 2009 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ 2010 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ 2011 __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) 2012 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2013 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 2014 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ 2015 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 2016 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ 2017 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ 2018 __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) 2019 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2020 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 2021 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ 2022 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 2023 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ 2024 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ 2025 __HAL_COMP_COMP7_EXTI_ENABLE_IT()) 2026 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2027 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 2028 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ 2029 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 2030 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ 2031 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ 2032 __HAL_COMP_COMP7_EXTI_DISABLE_IT()) 2033 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2034 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 2035 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ 2036 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 2037 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ 2038 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ 2039 __HAL_COMP_COMP7_EXTI_GET_FLAG()) 2040 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2041 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 2042 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ 2043 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 2044 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ 2045 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ 2046 __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) 2047 # endif 2048 # if defined(STM32F373xC) ||defined(STM32F378xx) 2049 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2050 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) 2051 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2052 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) 2053 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2054 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) 2055 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2056 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) 2057 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2058 __HAL_COMP_COMP2_EXTI_ENABLE_IT()) 2059 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2060 __HAL_COMP_COMP2_EXTI_DISABLE_IT()) 2061 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2062 __HAL_COMP_COMP2_EXTI_GET_FLAG()) 2063 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2064 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) 2065 # endif 2066 #else 2067 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2068 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) 2069 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2070 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) 2071 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2072 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) 2073 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2074 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) 2075 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2076 __HAL_COMP_COMP2_EXTI_ENABLE_IT()) 2077 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2078 __HAL_COMP_COMP2_EXTI_DISABLE_IT()) 2079 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2080 __HAL_COMP_COMP2_EXTI_GET_FLAG()) 2081 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2082 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) 2083 #endif 2084 2085 #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE 2086 2087 #if defined(STM32L0) || defined(STM32L4) 2088 /* Note: On these STM32 families, the only argument of this macro */ 2089 /* is COMP_FLAG_LOCK. */ 2090 /* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ 2091 /* argument. */ 2092 #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) 2093 #endif 2094 /** 2095 * @} 2096 */ 2097 2098 #if defined(STM32L0) || defined(STM32L4) 2099 /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose 2100 * @{ 2101 */ 2102 #define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ 2103 #define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ 2104 /** 2105 * @} 2106 */ 2107 #endif 2108 2109 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose 2110 * @{ 2111 */ 2112 2113 #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ 2114 ((WAVE) == DAC_WAVE_NOISE)|| \ 2115 ((WAVE) == DAC_WAVE_TRIANGLE)) 2116 2117 /** 2118 * @} 2119 */ 2120 2121 /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose 2122 * @{ 2123 */ 2124 2125 #define IS_WRPAREA IS_OB_WRPAREA 2126 #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM 2127 #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM 2128 #define IS_TYPEERASE IS_FLASH_TYPEERASE 2129 #define IS_NBSECTORS IS_FLASH_NBSECTORS 2130 #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE 2131 2132 /** 2133 * @} 2134 */ 2135 2136 /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose 2137 * @{ 2138 */ 2139 2140 #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 2141 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START 2142 #if defined(STM32F1) 2143 #define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE 2144 #else 2145 #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE 2146 #endif /* STM32F1 */ 2147 #define __HAL_I2C_RISE_TIME I2C_RISE_TIME 2148 #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD 2149 #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST 2150 #define __HAL_I2C_SPEED I2C_SPEED 2151 #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE 2152 #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ 2153 #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS 2154 #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE 2155 #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ 2156 #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB 2157 #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB 2158 #define __HAL_I2C_FREQRANGE I2C_FREQRANGE 2159 /** 2160 * @} 2161 */ 2162 2163 /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose 2164 * @{ 2165 */ 2166 2167 #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE 2168 #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT 2169 2170 #if defined(STM32H7) 2171 #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG 2172 #endif 2173 2174 /** 2175 * @} 2176 */ 2177 2178 /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose 2179 * @{ 2180 */ 2181 2182 #define __IRDA_DISABLE __HAL_IRDA_DISABLE 2183 #define __IRDA_ENABLE __HAL_IRDA_ENABLE 2184 2185 #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE 2186 #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION 2187 #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE 2188 #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION 2189 2190 #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE 2191 2192 2193 /** 2194 * @} 2195 */ 2196 2197 2198 /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose 2199 * @{ 2200 */ 2201 #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS 2202 #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS 2203 /** 2204 * @} 2205 */ 2206 2207 2208 /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose 2209 * @{ 2210 */ 2211 2212 #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT 2213 #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT 2214 #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE 2215 2216 /** 2217 * @} 2218 */ 2219 2220 2221 /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose 2222 * @{ 2223 */ 2224 #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD 2225 #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX 2226 #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX 2227 #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX 2228 #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX 2229 #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L 2230 #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H 2231 #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM 2232 #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES 2233 #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX 2234 #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT 2235 #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION 2236 #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET 2237 2238 /** 2239 * @} 2240 */ 2241 2242 2243 /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose 2244 * @{ 2245 */ 2246 #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT 2247 #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT 2248 #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE 2249 #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2250 #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE 2251 #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2252 #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE 2253 #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE 2254 #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE 2255 #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE 2256 #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE 2257 #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE 2258 #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine 2259 #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine 2260 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig 2261 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig 2262 #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) 2263 #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT 2264 #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT 2265 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE 2266 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2267 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE 2268 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2269 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2270 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2271 #define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) 2272 #define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) 2273 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention 2274 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention 2275 #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 2276 #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 2277 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE 2278 #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE 2279 #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB 2280 #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB 2281 2282 #if defined (STM32F4) 2283 #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() 2284 #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() 2285 #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() 2286 #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() 2287 #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() 2288 #else 2289 #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG 2290 #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT 2291 #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT 2292 #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT 2293 #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG 2294 #endif /* STM32F4 */ 2295 /** 2296 * @} 2297 */ 2298 2299 2300 /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose 2301 * @{ 2302 */ 2303 2304 #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI 2305 #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI 2306 2307 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback 2308 #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\ 2309 )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) 2310 2311 #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE 2312 #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE 2313 #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE 2314 #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE 2315 #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET 2316 #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET 2317 #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE 2318 #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE 2319 #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET 2320 #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET 2321 #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE 2322 #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE 2323 #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE 2324 #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE 2325 #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET 2326 #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET 2327 #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE 2328 #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE 2329 #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET 2330 #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET 2331 #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE 2332 #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE 2333 #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE 2334 #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE 2335 #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET 2336 #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET 2337 #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE 2338 #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE 2339 #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE 2340 #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE 2341 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET 2342 #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET 2343 #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE 2344 #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE 2345 #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET 2346 #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET 2347 #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET 2348 #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET 2349 #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET 2350 #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET 2351 #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET 2352 #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET 2353 #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET 2354 #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET 2355 #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET 2356 #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET 2357 #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET 2358 #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET 2359 #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE 2360 #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE 2361 #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET 2362 #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET 2363 #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE 2364 #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE 2365 #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE 2366 #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE 2367 #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET 2368 #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET 2369 #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE 2370 #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE 2371 #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET 2372 #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET 2373 #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE 2374 #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE 2375 #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET 2376 #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET 2377 #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE 2378 #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE 2379 #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE 2380 #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE 2381 #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET 2382 #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET 2383 #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE 2384 #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE 2385 #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET 2386 #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET 2387 #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE 2388 #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE 2389 #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE 2390 #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE 2391 #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET 2392 #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET 2393 #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE 2394 #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE 2395 #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET 2396 #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET 2397 #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE 2398 #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE 2399 #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE 2400 #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE 2401 #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET 2402 #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET 2403 #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE 2404 #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE 2405 #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET 2406 #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET 2407 #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE 2408 #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE 2409 #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE 2410 #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE 2411 #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET 2412 #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET 2413 #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE 2414 #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE 2415 #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE 2416 #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE 2417 #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET 2418 #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET 2419 #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE 2420 #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE 2421 #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE 2422 #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE 2423 #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET 2424 #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET 2425 #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE 2426 #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE 2427 #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET 2428 #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET 2429 #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE 2430 #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE 2431 #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE 2432 #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE 2433 #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE 2434 #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE 2435 #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE 2436 #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE 2437 #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE 2438 #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE 2439 #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET 2440 #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET 2441 #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE 2442 #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE 2443 #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET 2444 #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET 2445 #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE 2446 #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE 2447 #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE 2448 #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE 2449 #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE 2450 #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE 2451 #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET 2452 #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET 2453 #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE 2454 #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE 2455 #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE 2456 #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE 2457 #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE 2458 #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE 2459 #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET 2460 #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET 2461 #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE 2462 #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE 2463 #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE 2464 #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE 2465 #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET 2466 #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET 2467 #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE 2468 #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE 2469 #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE 2470 #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE 2471 #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET 2472 #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET 2473 #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE 2474 #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE 2475 #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE 2476 #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE 2477 #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET 2478 #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET 2479 #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE 2480 #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE 2481 #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE 2482 #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE 2483 #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET 2484 #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET 2485 #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE 2486 #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE 2487 #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE 2488 #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE 2489 #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET 2490 #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET 2491 #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE 2492 #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE 2493 #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE 2494 #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE 2495 #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET 2496 #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET 2497 #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE 2498 #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE 2499 #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE 2500 #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE 2501 #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET 2502 #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET 2503 #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE 2504 #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE 2505 #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE 2506 #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE 2507 #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET 2508 #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET 2509 #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE 2510 #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE 2511 #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE 2512 #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE 2513 #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET 2514 #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET 2515 #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE 2516 #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE 2517 #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE 2518 #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE 2519 #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET 2520 #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET 2521 #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE 2522 #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE 2523 #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE 2524 #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE 2525 #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET 2526 #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET 2527 #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE 2528 #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE 2529 #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE 2530 #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE 2531 #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET 2532 #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET 2533 #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE 2534 #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE 2535 #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE 2536 #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE 2537 #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET 2538 #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET 2539 #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE 2540 #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE 2541 #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE 2542 #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE 2543 #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET 2544 #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET 2545 #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE 2546 #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE 2547 #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE 2548 #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE 2549 #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET 2550 #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET 2551 #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE 2552 #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE 2553 #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE 2554 #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE 2555 #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET 2556 #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET 2557 #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE 2558 #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE 2559 #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE 2560 #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE 2561 #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET 2562 #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET 2563 #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE 2564 #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE 2565 #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE 2566 #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE 2567 #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET 2568 #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET 2569 2570 #if defined(STM32WB) 2571 #define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE 2572 #define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE 2573 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE 2574 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE 2575 #define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET 2576 #define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET 2577 #define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED 2578 #define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED 2579 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED 2580 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED 2581 #define QSPI_IRQHandler QUADSPI_IRQHandler 2582 #endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ 2583 2584 #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE 2585 #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE 2586 #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE 2587 #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE 2588 #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET 2589 #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET 2590 #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE 2591 #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE 2592 #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE 2593 #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE 2594 #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET 2595 #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET 2596 #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE 2597 #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE 2598 #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE 2599 #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE 2600 #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET 2601 #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET 2602 #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE 2603 #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE 2604 #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE 2605 #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE 2606 #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE 2607 #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE 2608 #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET 2609 #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET 2610 #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE 2611 #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE 2612 #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE 2613 #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE 2614 #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET 2615 #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET 2616 #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE 2617 #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE 2618 #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE 2619 #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE 2620 #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET 2621 #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET 2622 #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE 2623 #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE 2624 #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE 2625 #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE 2626 #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET 2627 #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET 2628 #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE 2629 #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE 2630 #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE 2631 #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE 2632 #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE 2633 #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE 2634 #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE 2635 #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE 2636 #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE 2637 #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE 2638 #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET 2639 #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET 2640 #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE 2641 #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE 2642 #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE 2643 #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE 2644 #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET 2645 #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET 2646 #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE 2647 #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE 2648 #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE 2649 #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE 2650 #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET 2651 #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET 2652 #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE 2653 #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE 2654 #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET 2655 #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET 2656 #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE 2657 #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE 2658 #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET 2659 #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET 2660 #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE 2661 #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE 2662 #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET 2663 #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET 2664 #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE 2665 #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE 2666 #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET 2667 #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET 2668 #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE 2669 #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE 2670 #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET 2671 #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET 2672 #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE 2673 #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE 2674 #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE 2675 #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE 2676 #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET 2677 #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET 2678 #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE 2679 #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE 2680 #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE 2681 #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE 2682 #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET 2683 #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET 2684 #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE 2685 #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE 2686 #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE 2687 #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE 2688 #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET 2689 #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET 2690 #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE 2691 #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE 2692 #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE 2693 #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE 2694 #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET 2695 #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET 2696 #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE 2697 #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE 2698 #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE 2699 #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE 2700 #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET 2701 #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET 2702 #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE 2703 #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE 2704 #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE 2705 #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE 2706 #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET 2707 #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET 2708 #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE 2709 #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE 2710 #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE 2711 #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE 2712 #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET 2713 #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET 2714 #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE 2715 #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE 2716 #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE 2717 #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE 2718 #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET 2719 #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET 2720 #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE 2721 #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE 2722 #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE 2723 #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE 2724 #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET 2725 #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET 2726 #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE 2727 #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE 2728 #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE 2729 #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE 2730 #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET 2731 #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET 2732 #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE 2733 #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE 2734 #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET 2735 #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET 2736 #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE 2737 #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE 2738 #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE 2739 #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE 2740 #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET 2741 #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET 2742 #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE 2743 #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE 2744 #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE 2745 #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE 2746 #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET 2747 #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET 2748 #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE 2749 #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE 2750 #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE 2751 #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE 2752 #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET 2753 #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET 2754 #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE 2755 #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE 2756 #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE 2757 #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE 2758 #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET 2759 #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET 2760 #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE 2761 #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE 2762 #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE 2763 #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE 2764 #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET 2765 #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET 2766 #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE 2767 #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE 2768 #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE 2769 #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE 2770 #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET 2771 #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET 2772 #define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE 2773 #define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE 2774 #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE 2775 #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE 2776 #define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET 2777 #define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET 2778 #define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE 2779 #define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE 2780 #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE 2781 #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE 2782 #define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET 2783 #define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET 2784 #define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE 2785 #define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE 2786 #define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET 2787 #define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET 2788 #define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE 2789 #define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE 2790 #define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET 2791 #define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET 2792 #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE 2793 #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE 2794 #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET 2795 #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE 2796 #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE 2797 #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE 2798 #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE 2799 #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET 2800 2801 #if defined(STM32H7) 2802 #define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE 2803 #define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE 2804 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE 2805 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE 2806 2807 #define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ 2808 #define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ 2809 2810 2811 #define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED 2812 #define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED 2813 #endif 2814 2815 #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE 2816 #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE 2817 #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE 2818 #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE 2819 #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET 2820 #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET 2821 2822 #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE 2823 #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE 2824 #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET 2825 #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET 2826 #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE 2827 #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE 2828 #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE 2829 #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE 2830 #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET 2831 #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET 2832 #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE 2833 #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE 2834 #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE 2835 #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE 2836 #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE 2837 #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE 2838 #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET 2839 #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET 2840 #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE 2841 #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE 2842 2843 #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET 2844 #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET 2845 #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE 2846 #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE 2847 #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE 2848 #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE 2849 #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE 2850 #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE 2851 #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE 2852 #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE 2853 #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE 2854 #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE 2855 #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE 2856 #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE 2857 #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE 2858 #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE 2859 #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE 2860 #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE 2861 #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE 2862 #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET 2863 #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET 2864 #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE 2865 #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE 2866 #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE 2867 #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE 2868 #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE 2869 #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET 2870 #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET 2871 #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE 2872 #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE 2873 #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE 2874 #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE 2875 #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET 2876 #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET 2877 #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE 2878 #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE 2879 #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE 2880 #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE 2881 #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET 2882 #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET 2883 #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE 2884 #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE 2885 #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE 2886 #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE 2887 #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE 2888 #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE 2889 #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE 2890 #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE 2891 #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE 2892 #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE 2893 #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE 2894 #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE 2895 #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE 2896 #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE 2897 #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE 2898 #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE 2899 #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE 2900 #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE 2901 #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE 2902 #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE 2903 #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE 2904 #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET 2905 #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET 2906 #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE 2907 #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE 2908 #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE 2909 #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE 2910 #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET 2911 #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET 2912 #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE 2913 #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE 2914 #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE 2915 #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE 2916 #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET 2917 #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET 2918 #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE 2919 #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE 2920 #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE 2921 #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE 2922 #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET 2923 #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET 2924 #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE 2925 #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE 2926 #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE 2927 #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE 2928 #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET 2929 #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE 2930 #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE 2931 #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE 2932 #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE 2933 #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE 2934 #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE 2935 #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET 2936 #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET 2937 #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE 2938 #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE 2939 #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE 2940 #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE 2941 #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET 2942 #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET 2943 #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE 2944 #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE 2945 #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE 2946 #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE 2947 #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET 2948 #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET 2949 #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE 2950 #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE 2951 #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE 2952 #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE 2953 #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET 2954 #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET 2955 #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE 2956 #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 2957 #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE 2958 #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE 2959 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED 2960 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED 2961 #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET 2962 #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET 2963 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE 2964 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 2965 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED 2966 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED 2967 #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE 2968 #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE 2969 #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE 2970 #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE 2971 #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE 2972 #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE 2973 #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE 2974 #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE 2975 #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE 2976 #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET 2977 #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET 2978 #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE 2979 #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE 2980 #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET 2981 #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET 2982 #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE 2983 #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE 2984 #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE 2985 #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE 2986 #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET 2987 #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET 2988 #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE 2989 #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE 2990 2991 /* alias define maintained for legacy */ 2992 #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET 2993 #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET 2994 2995 #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE 2996 #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE 2997 #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE 2998 #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE 2999 #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE 3000 #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE 3001 #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE 3002 #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE 3003 #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE 3004 #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE 3005 #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE 3006 #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE 3007 #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE 3008 #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE 3009 #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE 3010 #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE 3011 #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE 3012 #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE 3013 #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE 3014 #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE 3015 3016 #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET 3017 #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET 3018 #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET 3019 #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET 3020 #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET 3021 #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET 3022 #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET 3023 #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET 3024 #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET 3025 #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET 3026 #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET 3027 #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET 3028 #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET 3029 #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET 3030 #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET 3031 #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET 3032 #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET 3033 #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET 3034 #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET 3035 #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET 3036 3037 #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED 3038 #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED 3039 #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED 3040 #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED 3041 #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED 3042 #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED 3043 #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED 3044 #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED 3045 #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED 3046 #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED 3047 #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED 3048 #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED 3049 #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED 3050 #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED 3051 #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED 3052 #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED 3053 #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED 3054 #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED 3055 #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED 3056 #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED 3057 #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED 3058 #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED 3059 #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED 3060 #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED 3061 #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED 3062 #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED 3063 #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED 3064 #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED 3065 #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED 3066 #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED 3067 #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED 3068 #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED 3069 #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED 3070 #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED 3071 #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED 3072 #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED 3073 #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED 3074 #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED 3075 #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED 3076 #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED 3077 #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED 3078 #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED 3079 #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED 3080 #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED 3081 #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED 3082 #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED 3083 #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED 3084 #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED 3085 #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED 3086 #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED 3087 #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED 3088 #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED 3089 #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED 3090 #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED 3091 #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED 3092 #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED 3093 #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED 3094 #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED 3095 #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED 3096 #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED 3097 #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED 3098 #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED 3099 #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED 3100 #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED 3101 #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED 3102 #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED 3103 #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED 3104 #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED 3105 #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED 3106 #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED 3107 #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED 3108 #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED 3109 #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED 3110 #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED 3111 #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED 3112 #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED 3113 #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED 3114 #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED 3115 #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED 3116 #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED 3117 #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED 3118 #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED 3119 #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED 3120 #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED 3121 #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED 3122 #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED 3123 #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED 3124 #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED 3125 #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED 3126 #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED 3127 #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED 3128 #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED 3129 #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED 3130 #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED 3131 #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED 3132 #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED 3133 #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED 3134 #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED 3135 #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED 3136 #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED 3137 #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED 3138 #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED 3139 #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED 3140 #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED 3141 #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED 3142 #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED 3143 #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED 3144 #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED 3145 #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED 3146 #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED 3147 #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED 3148 #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED 3149 #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED 3150 #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED 3151 #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED 3152 #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED 3153 3154 #if defined(STM32L1) 3155 #define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE 3156 #define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE 3157 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE 3158 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE 3159 #define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET 3160 #define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET 3161 #endif /* STM32L1 */ 3162 3163 #if defined(STM32F4) 3164 #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET 3165 #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET 3166 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE 3167 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE 3168 #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE 3169 #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE 3170 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED 3171 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED 3172 #define Sdmmc1ClockSelection SdioClockSelection 3173 #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO 3174 #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 3175 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK 3176 #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG 3177 #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE 3178 #endif 3179 3180 #if defined(STM32F7) || defined(STM32L4) 3181 #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET 3182 #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET 3183 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE 3184 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE 3185 #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE 3186 #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE 3187 #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED 3188 #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED 3189 #define SdioClockSelection Sdmmc1ClockSelection 3190 #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 3191 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG 3192 #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE 3193 #endif 3194 3195 #if defined(STM32F7) 3196 #define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 3197 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK 3198 #endif 3199 3200 #if defined(STM32H7) 3201 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() 3202 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() 3203 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() 3204 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() 3205 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() 3206 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() 3207 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() 3208 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() 3209 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() 3210 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() 3211 3212 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() 3213 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() 3214 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() 3215 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() 3216 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() 3217 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() 3218 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() 3219 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() 3220 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() 3221 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() 3222 #endif 3223 3224 #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG 3225 #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG 3226 3227 #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE 3228 3229 #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE 3230 #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE 3231 #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK 3232 #define IS_RCC_HCLK_DIV IS_RCC_PCLK 3233 #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK 3234 3235 #define RCC_IT_HSI14 RCC_IT_HSI14RDY 3236 3237 #define RCC_IT_CSSLSE RCC_IT_LSECSS 3238 #define RCC_IT_CSSHSE RCC_IT_CSS 3239 3240 #define RCC_PLLMUL_3 RCC_PLL_MUL3 3241 #define RCC_PLLMUL_4 RCC_PLL_MUL4 3242 #define RCC_PLLMUL_6 RCC_PLL_MUL6 3243 #define RCC_PLLMUL_8 RCC_PLL_MUL8 3244 #define RCC_PLLMUL_12 RCC_PLL_MUL12 3245 #define RCC_PLLMUL_16 RCC_PLL_MUL16 3246 #define RCC_PLLMUL_24 RCC_PLL_MUL24 3247 #define RCC_PLLMUL_32 RCC_PLL_MUL32 3248 #define RCC_PLLMUL_48 RCC_PLL_MUL48 3249 3250 #define RCC_PLLDIV_2 RCC_PLL_DIV2 3251 #define RCC_PLLDIV_3 RCC_PLL_DIV3 3252 #define RCC_PLLDIV_4 RCC_PLL_DIV4 3253 3254 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE 3255 #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG 3256 #define RCC_MCO_NODIV RCC_MCODIV_1 3257 #define RCC_MCO_DIV1 RCC_MCODIV_1 3258 #define RCC_MCO_DIV2 RCC_MCODIV_2 3259 #define RCC_MCO_DIV4 RCC_MCODIV_4 3260 #define RCC_MCO_DIV8 RCC_MCODIV_8 3261 #define RCC_MCO_DIV16 RCC_MCODIV_16 3262 #define RCC_MCO_DIV32 RCC_MCODIV_32 3263 #define RCC_MCO_DIV64 RCC_MCODIV_64 3264 #define RCC_MCO_DIV128 RCC_MCODIV_128 3265 #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK 3266 #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI 3267 #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE 3268 #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK 3269 #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI 3270 #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 3271 #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 3272 #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE 3273 #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK 3274 #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK 3275 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 3276 3277 #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) 3278 #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE 3279 #else 3280 #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK 3281 #endif 3282 3283 #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 3284 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL 3285 #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI 3286 #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL 3287 #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL 3288 #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 3289 #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 3290 #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 3291 3292 #define HSION_BitNumber RCC_HSION_BIT_NUMBER 3293 #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER 3294 #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER 3295 #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER 3296 #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER 3297 #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER 3298 #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER 3299 #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER 3300 #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER 3301 #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER 3302 #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER 3303 #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER 3304 #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER 3305 #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER 3306 #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER 3307 #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER 3308 #define LSION_BitNumber RCC_LSION_BIT_NUMBER 3309 #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER 3310 #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER 3311 #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER 3312 #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER 3313 #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER 3314 #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER 3315 #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER 3316 #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER 3317 #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER 3318 #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS 3319 #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS 3320 #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS 3321 #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS 3322 #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE 3323 #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE 3324 3325 #define CR_HSION_BB RCC_CR_HSION_BB 3326 #define CR_CSSON_BB RCC_CR_CSSON_BB 3327 #define CR_PLLON_BB RCC_CR_PLLON_BB 3328 #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB 3329 #define CR_MSION_BB RCC_CR_MSION_BB 3330 #define CSR_LSION_BB RCC_CSR_LSION_BB 3331 #define CSR_LSEON_BB RCC_CSR_LSEON_BB 3332 #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB 3333 #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB 3334 #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB 3335 #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB 3336 #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB 3337 #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB 3338 #define CR_HSEON_BB RCC_CR_HSEON_BB 3339 #define CSR_RMVF_BB RCC_CSR_RMVF_BB 3340 #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB 3341 #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB 3342 3343 #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE 3344 #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE 3345 #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE 3346 #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE 3347 #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE 3348 3349 #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT 3350 3351 #define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN 3352 #define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF 3353 3354 #define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 3355 #define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ 3356 #define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP 3357 #define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ 3358 #define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE 3359 #define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 3360 3361 #define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE 3362 #define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE 3363 #define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED 3364 #define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED 3365 #define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET 3366 #define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET 3367 #define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE 3368 #define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE 3369 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED 3370 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED 3371 #define DfsdmClockSelection Dfsdm1ClockSelection 3372 #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 3373 #define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 3374 #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK 3375 #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG 3376 #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE 3377 #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 3378 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 3379 #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 3380 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 3381 3382 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 3383 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 3384 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 3385 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 3386 #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 3387 #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 3388 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 3389 #if defined(STM32U5) 3390 #define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL 3391 #define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL 3392 #define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE 3393 #define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE 3394 #define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE 3395 #define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE 3396 #define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE 3397 #define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE 3398 #define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE 3399 #define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE 3400 #define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE 3401 #define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT 3402 #endif 3403 /** 3404 * @} 3405 */ 3406 3407 /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose 3408 * @{ 3409 */ 3410 #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) 3411 3412 /** 3413 * @} 3414 */ 3415 3416 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose 3417 * @{ 3418 */ 3419 #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) 3420 #else 3421 #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG 3422 #endif 3423 #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT 3424 #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT 3425 3426 #if defined (STM32F1) 3427 #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() 3428 3429 #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() 3430 3431 #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() 3432 3433 #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() 3434 3435 #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() 3436 #else 3437 #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ 3438 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ 3439 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) 3440 #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ 3441 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ 3442 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) 3443 #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ 3444 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ 3445 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) 3446 #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ 3447 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ 3448 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) 3449 #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ 3450 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ 3451 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) 3452 #endif /* STM32F1 */ 3453 3454 #define IS_ALARM IS_RTC_ALARM 3455 #define IS_ALARM_MASK IS_RTC_ALARM_MASK 3456 #define IS_TAMPER IS_RTC_TAMPER 3457 #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE 3458 #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER 3459 #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT 3460 #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE 3461 #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION 3462 #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE 3463 #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ 3464 #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION 3465 #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER 3466 #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK 3467 #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER 3468 3469 #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE 3470 #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE 3471 3472 /** 3473 * @} 3474 */ 3475 3476 /** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose 3477 * @{ 3478 */ 3479 3480 #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE 3481 #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS 3482 3483 #define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE 3484 #define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE 3485 #define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE 3486 3487 #if defined(STM32F4) || defined(STM32F2) 3488 #define SD_SDMMC_DISABLED SD_SDIO_DISABLED 3489 #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY 3490 #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED 3491 #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION 3492 #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND 3493 #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT 3494 #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED 3495 #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE 3496 #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE 3497 #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE 3498 #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL 3499 #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT 3500 #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT 3501 #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG 3502 #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG 3503 #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT 3504 #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT 3505 #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS 3506 #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT 3507 #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND 3508 /* alias CMSIS */ 3509 #define SDMMC1_IRQn SDIO_IRQn 3510 #define SDMMC1_IRQHandler SDIO_IRQHandler 3511 #endif 3512 3513 #if defined(STM32F7) || defined(STM32L4) 3514 #define SD_SDIO_DISABLED SD_SDMMC_DISABLED 3515 #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY 3516 #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED 3517 #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION 3518 #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND 3519 #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT 3520 #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED 3521 #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE 3522 #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE 3523 #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE 3524 #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE 3525 #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT 3526 #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT 3527 #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG 3528 #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG 3529 #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT 3530 #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT 3531 #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS 3532 #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT 3533 #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND 3534 /* alias CMSIS for compatibilities */ 3535 #define SDIO_IRQn SDMMC1_IRQn 3536 #define SDIO_IRQHandler SDMMC1_IRQHandler 3537 #endif 3538 3539 #if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) 3540 #define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef 3541 #define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef 3542 #define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef 3543 #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef 3544 #endif 3545 3546 #if defined(STM32H7) || defined(STM32L5) 3547 #define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback 3548 #define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback 3549 #define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback 3550 #define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback 3551 #define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback 3552 #define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback 3553 #define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback 3554 #define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback 3555 #define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback 3556 #endif 3557 /** 3558 * @} 3559 */ 3560 3561 /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose 3562 * @{ 3563 */ 3564 3565 #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT 3566 #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT 3567 #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE 3568 #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE 3569 #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE 3570 #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE 3571 3572 #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE 3573 #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE 3574 3575 #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE 3576 3577 /** 3578 * @} 3579 */ 3580 3581 /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose 3582 * @{ 3583 */ 3584 #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 3585 #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 3586 #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START 3587 #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH 3588 #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR 3589 #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE 3590 #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE 3591 #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED 3592 /** 3593 * @} 3594 */ 3595 3596 /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose 3597 * @{ 3598 */ 3599 3600 #define __HAL_SPI_1LINE_TX SPI_1LINE_TX 3601 #define __HAL_SPI_1LINE_RX SPI_1LINE_RX 3602 #define __HAL_SPI_RESET_CRC SPI_RESET_CRC 3603 3604 /** 3605 * @} 3606 */ 3607 3608 /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose 3609 * @{ 3610 */ 3611 3612 #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE 3613 #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION 3614 #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE 3615 #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION 3616 3617 #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD 3618 3619 #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE 3620 #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE 3621 3622 /** 3623 * @} 3624 */ 3625 3626 3627 /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose 3628 * @{ 3629 */ 3630 3631 #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT 3632 #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT 3633 #define __USART_ENABLE __HAL_USART_ENABLE 3634 #define __USART_DISABLE __HAL_USART_DISABLE 3635 3636 #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE 3637 #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE 3638 3639 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) 3640 #define USART_OVERSAMPLING_16 0x00000000U 3641 #define USART_OVERSAMPLING_8 USART_CR1_OVER8 3642 3643 #define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ 3644 ((__SAMPLING__) == USART_OVERSAMPLING_8)) 3645 #endif /* STM32F0 || STM32F3 || STM32F7 */ 3646 /** 3647 * @} 3648 */ 3649 3650 /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose 3651 * @{ 3652 */ 3653 #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE 3654 3655 #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 3656 #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 3657 #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 3658 #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE 3659 3660 #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 3661 #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 3662 #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 3663 #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE 3664 3665 #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT 3666 #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT 3667 #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG 3668 #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG 3669 #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE 3670 #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE 3671 #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 3672 3673 #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT 3674 #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT 3675 #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG 3676 #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG 3677 #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE 3678 #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE 3679 #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 3680 #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT 3681 3682 #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT 3683 #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT 3684 #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG 3685 #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG 3686 #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE 3687 #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE 3688 #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 3689 #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT 3690 3691 #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup 3692 #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup 3693 3694 #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo 3695 #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo 3696 /** 3697 * @} 3698 */ 3699 3700 /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose 3701 * @{ 3702 */ 3703 #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE 3704 #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE 3705 3706 #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE 3707 #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT 3708 3709 #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE 3710 3711 #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN 3712 #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER 3713 #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER 3714 #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER 3715 #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD 3716 #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD 3717 #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION 3718 #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION 3719 #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER 3720 #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER 3721 #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE 3722 #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE 3723 3724 #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 3725 /** 3726 * @} 3727 */ 3728 3729 /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose 3730 * @{ 3731 */ 3732 3733 #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT 3734 #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT 3735 #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG 3736 #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG 3737 #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER 3738 #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER 3739 #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER 3740 3741 #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE 3742 #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE 3743 #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE 3744 /** 3745 * @} 3746 */ 3747 3748 /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose 3749 * @{ 3750 */ 3751 #define __HAL_LTDC_LAYER LTDC_LAYER 3752 #define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG 3753 /** 3754 * @} 3755 */ 3756 3757 /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose 3758 * @{ 3759 */ 3760 #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE 3761 #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE 3762 #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE 3763 #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE 3764 #define SAI_STREOMODE SAI_STEREOMODE 3765 #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY 3766 #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL 3767 #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL 3768 #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL 3769 #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL 3770 #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL 3771 #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE 3772 #define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 3773 #define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE 3774 /** 3775 * @} 3776 */ 3777 3778 /** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose 3779 * @{ 3780 */ 3781 #if defined(STM32H7) 3782 #define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow 3783 #define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT 3784 #define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA 3785 #endif 3786 /** 3787 * @} 3788 */ 3789 3790 /** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose 3791 * @{ 3792 */ 3793 #if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) 3794 #define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT 3795 #define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA 3796 #define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart 3797 #define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT 3798 #define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA 3799 #define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop 3800 #endif 3801 /** 3802 * @} 3803 */ 3804 3805 /** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose 3806 * @{ 3807 */ 3808 #if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) 3809 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE 3810 #endif /* STM32L4 || STM32F4 || STM32F7 */ 3811 /** 3812 * @} 3813 */ 3814 3815 /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose 3816 * @{ 3817 */ 3818 3819 /** 3820 * @} 3821 */ 3822 3823 #ifdef __cplusplus 3824 } 3825 #endif 3826 3827 #endif /* STM32_HAL_LEGACY */ 3828 3829 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 3830
